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r8152: fix setting RTL8152_UNPLUG
[deliverable/linux.git] / drivers / net / ethernet / broadcom / tg3.c
CommitLineData
1da177e4
LT		 1/*
2 * tg3.c: Broadcom Tigon3 ethernet driver.
3 *
4 * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
5 * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
6 * Copyright (C) 2004 Sun Microsystems Inc.
de750e4c 7 * Copyright (C) 2005-2014 Broadcom Corporation.
1da177e4
LT		 8 *
9 * Firmware is:
49cabf49
MC		 10 * Derived from proprietary unpublished source code,
11 * Copyright (C) 2000-2003 Broadcom Corporation.
12 *
13 * Permission is hereby granted for the distribution of this firmware
14 * data in hexadecimal or equivalent format, provided this copyright
15 * notice is accompanying it.
1da177e4
LT		 16 */
17
1da177e4
LT		 18
19#include <linux/module.h>
20#include <linux/moduleparam.h>
6867c843 21#include <linux/stringify.h>
1da177e4
LT		 22#include <linux/kernel.h>
23#include <linux/types.h>
24#include <linux/compiler.h>
25#include <linux/slab.h>
26#include <linux/delay.h>
14c85021 27#include <linux/in.h>
a6b7a407 28#include <linux/interrupt.h>
1da177e4
LT		 29#include <linux/ioport.h>
30#include <linux/pci.h>
31#include <linux/netdevice.h>
32#include <linux/etherdevice.h>
33#include <linux/skbuff.h>
34#include <linux/ethtool.h>
3110f5f5 35#include <linux/mdio.h>
1da177e4 36#include <linux/mii.h>
158d7abd 37#include <linux/phy.h>
a9daf367 38#include <linux/brcmphy.h>
e565eec3 39#include <linux/if.h>
1da177e4
LT		 40#include <linux/if_vlan.h>
41#include <linux/ip.h>
42#include <linux/tcp.h>
43#include <linux/workqueue.h>
61487480 44#include <linux/prefetch.h>
f9a5f7d3 45#include <linux/dma-mapping.h>
077f849d 46#include <linux/firmware.h>
7e6c63f0 47#include <linux/ssb/ssb_driver_gige.h>
aed93e0b
MC		 48#include <linux/hwmon.h>
49#include <linux/hwmon-sysfs.h>
1da177e4
LT		 50
51#include <net/checksum.h>
c9bdd4b5 52#include <net/ip.h>
1da177e4 53
27fd9de8 54#include <linux/io.h>
1da177e4 55#include <asm/byteorder.h>
27fd9de8 56#include <linux/uaccess.h>
1da177e4 57
be947307
MC		 58#include <uapi/linux/net_tstamp.h>
59#include <linux/ptp_clock_kernel.h>
60
49b6e95f 61#ifdef CONFIG_SPARC
1da177e4 62#include <asm/idprom.h>
49b6e95f 63#include <asm/prom.h>
1da177e4
LT		 64#endif
65
63532394
MC		 66#define BAR_0 0
67#define BAR_2 2
68
1da177e4
LT		 69#include "tg3.h"
70
63c3a66f
JP		 71/* Functions & macros to verify TG3_FLAGS types */
72
73static inline int _tg3_flag(enum TG3_FLAGS flag, unsigned long *bits)
74{
75 return test_bit(flag, bits);
76}
77
78static inline void _tg3_flag_set(enum TG3_FLAGS flag, unsigned long *bits)
79{
80 set_bit(flag, bits);
81}
82
83static inline void _tg3_flag_clear(enum TG3_FLAGS flag, unsigned long *bits)
84{
85 clear_bit(flag, bits);
86}
87
88#define tg3_flag(tp, flag) \
89 _tg3_flag(TG3_FLAG_##flag, (tp)->tg3_flags)
90#define tg3_flag_set(tp, flag) \
91 _tg3_flag_set(TG3_FLAG_##flag, (tp)->tg3_flags)
92#define tg3_flag_clear(tp, flag) \
93 _tg3_flag_clear(TG3_FLAG_##flag, (tp)->tg3_flags)
94
1da177e4 95#define DRV_MODULE_NAME "tg3"
6867c843 96#define TG3_MAJ_NUM 3
de750e4c 97#define TG3_MIN_NUM 137
6867c843
MC		 98#define DRV_MODULE_VERSION \
99 __stringify(TG3_MAJ_NUM) "." __stringify(TG3_MIN_NUM)
de750e4c 100#define DRV_MODULE_RELDATE "May 11, 2014"
1da177e4 101
fd6d3f0e
MC		 102#define RESET_KIND_SHUTDOWN 0
103#define RESET_KIND_INIT 1
104#define RESET_KIND_SUSPEND 2
105
1da177e4
LT		 106#define TG3_DEF_RX_MODE 0
107#define TG3_DEF_TX_MODE 0
108#define TG3_DEF_MSG_ENABLE \
109 (NETIF_MSG_DRV | \
110 NETIF_MSG_PROBE | \
111 NETIF_MSG_LINK | \
112 NETIF_MSG_TIMER | \
113 NETIF_MSG_IFDOWN | \
114 NETIF_MSG_IFUP | \
115 NETIF_MSG_RX_ERR | \
116 NETIF_MSG_TX_ERR)
117
520b2756
MC		 118#define TG3_GRC_LCLCTL_PWRSW_DELAY 100
119
1da177e4
LT		 120/* length of time before we decide the hardware is borked,
121 * and dev->tx_timeout() should be called to fix the problem
122 */
63c3a66f 123
1da177e4
LT		 124#define TG3_TX_TIMEOUT (5 * HZ)
125
126/* hardware minimum and maximum for a single frame's data payload */
127#define TG3_MIN_MTU 60
128#define TG3_MAX_MTU(tp) \
63c3a66f 129 (tg3_flag(tp, JUMBO_CAPABLE) ? 9000 : 1500)
1da177e4
LT		 130
131/* These numbers seem to be hard coded in the NIC firmware somehow.
132 * You can't change the ring sizes, but you can change where you place
133 * them in the NIC onboard memory.
134 */
7cb32cf2 135#define TG3_RX_STD_RING_SIZE(tp) \
63c3a66f 136 (tg3_flag(tp, LRG_PROD_RING_CAP) ? \
de9f5230 137 TG3_RX_STD_MAX_SIZE_5717 : TG3_RX_STD_MAX_SIZE_5700)
1da177e4 138#define TG3_DEF_RX_RING_PENDING 200
7cb32cf2 139#define TG3_RX_JMB_RING_SIZE(tp) \
63c3a66f 140 (tg3_flag(tp, LRG_PROD_RING_CAP) ? \
de9f5230 141 TG3_RX_JMB_MAX_SIZE_5717 : TG3_RX_JMB_MAX_SIZE_5700)
1da177e4
LT		 142#define TG3_DEF_RX_JUMBO_RING_PENDING 100
143
144/* Do not place this n-ring entries value into the tp struct itself,
145 * we really want to expose these constants to GCC so that modulo et
146 * al. operations are done with shifts and masks instead of with
147 * hw multiply/modulo instructions. Another solution would be to
148 * replace things like '% foo' with '& (foo - 1)'.
149 */
1da177e4
LT		 150
151#define TG3_TX_RING_SIZE 512
152#define TG3_DEF_TX_RING_PENDING (TG3_TX_RING_SIZE - 1)
153
2c49a44d
MC		 154#define TG3_RX_STD_RING_BYTES(tp) \
155 (sizeof(struct tg3_rx_buffer_desc) * TG3_RX_STD_RING_SIZE(tp))
156#define TG3_RX_JMB_RING_BYTES(tp) \
157 (sizeof(struct tg3_ext_rx_buffer_desc) * TG3_RX_JMB_RING_SIZE(tp))
158#define TG3_RX_RCB_RING_BYTES(tp) \
7cb32cf2 159 (sizeof(struct tg3_rx_buffer_desc) * (tp->rx_ret_ring_mask + 1))
1da177e4
LT		 160#define TG3_TX_RING_BYTES (sizeof(struct tg3_tx_buffer_desc) * \
161 TG3_TX_RING_SIZE)
1da177e4
LT		 162#define NEXT_TX(N) (((N) + 1) & (TG3_TX_RING_SIZE - 1))
163
287be12e
MC		 164#define TG3_DMA_BYTE_ENAB 64
165
166#define TG3_RX_STD_DMA_SZ 1536
167#define TG3_RX_JMB_DMA_SZ 9046
168
169#define TG3_RX_DMA_TO_MAP_SZ(x) ((x) + TG3_DMA_BYTE_ENAB)
170
171#define TG3_RX_STD_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_STD_DMA_SZ)
172#define TG3_RX_JMB_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_JMB_DMA_SZ)
1da177e4 173
2c49a44d
MC		 174#define TG3_RX_STD_BUFF_RING_SIZE(tp) \
175 (sizeof(struct ring_info) * TG3_RX_STD_RING_SIZE(tp))
2b2cdb65 176
2c49a44d
MC		 177#define TG3_RX_JMB_BUFF_RING_SIZE(tp) \
178 (sizeof(struct ring_info) * TG3_RX_JMB_RING_SIZE(tp))
2b2cdb65 179
d2757fc4
MC		 180/* Due to a hardware bug, the 5701 can only DMA to memory addresses
181 * that are at least dword aligned when used in PCIX mode. The driver
182 * works around this bug by double copying the packet. This workaround
183 * is built into the normal double copy length check for efficiency.
184 *
185 * However, the double copy is only necessary on those architectures
186 * where unaligned memory accesses are inefficient. For those architectures
187 * where unaligned memory accesses incur little penalty, we can reintegrate
188 * the 5701 in the normal rx path. Doing so saves a device structure
189 * dereference by hardcoding the double copy threshold in place.
190 */
191#define TG3_RX_COPY_THRESHOLD 256
192#if NET_IP_ALIGN == 0 || defined(CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS)
193 #define TG3_RX_COPY_THRESH(tp) TG3_RX_COPY_THRESHOLD
194#else
195 #define TG3_RX_COPY_THRESH(tp) ((tp)->rx_copy_thresh)
196#endif
197
81389f57
MC		 198#if (NET_IP_ALIGN != 0)
199#define TG3_RX_OFFSET(tp) ((tp)->rx_offset)
200#else
9205fd9c 201#define TG3_RX_OFFSET(tp) (NET_SKB_PAD)
81389f57
MC		 202#endif
203
1da177e4 204/* minimum number of free TX descriptors required to wake up TX process */
f3f3f27e 205#define TG3_TX_WAKEUP_THRESH(tnapi) ((tnapi)->tx_pending / 4)
55086ad9 206#define TG3_TX_BD_DMA_MAX_2K 2048
a4cb428d 207#define TG3_TX_BD_DMA_MAX_4K 4096
1da177e4 208
ad829268
MC		 209#define TG3_RAW_IP_ALIGN 2
210
e565eec3
MC		 211#define TG3_MAX_UCAST_ADDR(tp) (tg3_flag((tp), ENABLE_ASF) ? 2 : 3)
212#define TG3_UCAST_ADDR_IDX(tp) (tg3_flag((tp), ENABLE_ASF) ? 2 : 1)
213
c6cdf436 214#define TG3_FW_UPDATE_TIMEOUT_SEC 5
21f7638e 215#define TG3_FW_UPDATE_FREQ_SEC (TG3_FW_UPDATE_TIMEOUT_SEC / 2)
c6cdf436 216
077f849d 217#define FIRMWARE_TG3 "tigon/tg3.bin"
c4dab506 218#define FIRMWARE_TG357766 "tigon/tg357766.bin"
077f849d
JSR		 219#define FIRMWARE_TG3TSO "tigon/tg3_tso.bin"
220#define FIRMWARE_TG3TSO5 "tigon/tg3_tso5.bin"
221
229b1ad1 222static char version[] =
05dbe005 223 DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")";
1da177e4
LT		 224
225MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
226MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
227MODULE_LICENSE("GPL");
228MODULE_VERSION(DRV_MODULE_VERSION);
077f849d
JSR		 229MODULE_FIRMWARE(FIRMWARE_TG3);
230MODULE_FIRMWARE(FIRMWARE_TG3TSO);
231MODULE_FIRMWARE(FIRMWARE_TG3TSO5);
232
1da177e4
LT		 233static int tg3_debug = -1; /* -1 == use TG3_DEF_MSG_ENABLE as value */
234module_param(tg3_debug, int, 0);
235MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
236
3d567e0e
NNS		 237#define TG3_DRV_DATA_FLAG_10_100_ONLY 0x0001
238#define TG3_DRV_DATA_FLAG_5705_10_100 0x0002
239
9baa3c34 240static const struct pci_device_id tg3_pci_tbl[] = {
13185217
HK		 241 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
242 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
243 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
244 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
245 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
246 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
247 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
248 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
249 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
250 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
251 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
252 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
253 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
254 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
255 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
256 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
257 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
258 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
3d567e0e
NNS		 259 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901),
260 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY |
261 TG3_DRV_DATA_FLAG_5705_10_100},
262 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2),
263 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY |
264 TG3_DRV_DATA_FLAG_5705_10_100},
13185217 265 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
3d567e0e
NNS		 266 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F),
267 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY |
268 TG3_DRV_DATA_FLAG_5705_10_100},
13185217 269 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
126a3368 270 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
7e6c63f0 271 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750)},
13185217 272 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
13185217 273 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
3d567e0e
NNS		 274 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F),
275 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
13185217
HK		 276 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
277 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
278 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
279 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
3d567e0e
NNS		 280 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F),
281 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
13185217
HK		 282 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
283 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
284 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
285 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
126a3368 286 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
13185217
HK		 287 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
288 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
3d567e0e
NNS		 289 {PCI_DEVICE_SUB(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5787M,
290 PCI_VENDOR_ID_LENOVO,
291 TG3PCI_SUBDEVICE_ID_LENOVO_5787M),
292 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
13185217 293 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
3d567e0e
NNS		 294 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F),
295 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
13185217
HK		 296 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
297 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
298 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
299 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
300 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
301 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
302 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
b5d3772c
MC		 303 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
304 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
d30cdd28
MC		 305 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)},
306 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)},
6c7af27c 307 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)},
9936bcf6
MC		 308 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)},
309 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)},
c88e668b
MC		 310 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761S)},
311 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761SE)},
2befdcea
MC		 312 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_G)},
313 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_F)},
3d567e0e
NNS		 314 {PCI_DEVICE_SUB(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780,
315 PCI_VENDOR_ID_AI, TG3PCI_SUBDEVICE_ID_ACER_57780_A),
316 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
317 {PCI_DEVICE_SUB(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780,
318 PCI_VENDOR_ID_AI, TG3PCI_SUBDEVICE_ID_ACER_57780_B),
319 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
321d32a0
MC		 320 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780)},
321 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57760)},
3d567e0e
NNS		 322 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57790),
323 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
5e7ccf20 324 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57788)},
5001e2f6 325 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5717)},
79d49695 326 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5717_C)},
5001e2f6 327 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5718)},
b0f75221
MC		 328 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57781)},
329 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57785)},
330 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57761)},
331 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57765)},
3d567e0e
NNS		 332 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57791),
333 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
334 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57795),
335 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
302b500b 336 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5719)},
ba1f3c76 337 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5720)},
02eca3f5 338 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57762)},
d3f677af 339 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57766)},
c86a8560
MC		 340 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5762)},
341 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5725)},
342 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5727)},
68273712
NS		 343 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57764)},
344 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57767)},
345 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57787)},
346 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57782)},
347 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57786)},
13185217
HK		 348 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
349 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
350 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
351 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
352 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
353 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
354 {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
1dcb14d9 355 {PCI_DEVICE(0x10cf, 0x11a2)}, /* Fujitsu 1000base-SX with BCM5703SKHB */
13185217 356 {}
1da177e4
LT		 357};
358
359MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
360
50da859d 361static const struct {
1da177e4 362 const char string[ETH_GSTRING_LEN];
48fa55a0 363} ethtool_stats_keys[] = {
1da177e4
LT		 364 { "rx_octets" },
365 { "rx_fragments" },
366 { "rx_ucast_packets" },
367 { "rx_mcast_packets" },
368 { "rx_bcast_packets" },
369 { "rx_fcs_errors" },
370 { "rx_align_errors" },
371 { "rx_xon_pause_rcvd" },
372 { "rx_xoff_pause_rcvd" },
373 { "rx_mac_ctrl_rcvd" },
374 { "rx_xoff_entered" },
375 { "rx_frame_too_long_errors" },
376 { "rx_jabbers" },
377 { "rx_undersize_packets" },
378 { "rx_in_length_errors" },
379 { "rx_out_length_errors" },
380 { "rx_64_or_less_octet_packets" },
381 { "rx_65_to_127_octet_packets" },
382 { "rx_128_to_255_octet_packets" },
383 { "rx_256_to_511_octet_packets" },
384 { "rx_512_to_1023_octet_packets" },
385 { "rx_1024_to_1522_octet_packets" },
386 { "rx_1523_to_2047_octet_packets" },
387 { "rx_2048_to_4095_octet_packets" },
388 { "rx_4096_to_8191_octet_packets" },
389 { "rx_8192_to_9022_octet_packets" },
390
391 { "tx_octets" },
392 { "tx_collisions" },
393
394 { "tx_xon_sent" },
395 { "tx_xoff_sent" },
396 { "tx_flow_control" },
397 { "tx_mac_errors" },
398 { "tx_single_collisions" },
399 { "tx_mult_collisions" },
400 { "tx_deferred" },
401 { "tx_excessive_collisions" },
402 { "tx_late_collisions" },
403 { "tx_collide_2times" },
404 { "tx_collide_3times" },
405 { "tx_collide_4times" },
406 { "tx_collide_5times" },
407 { "tx_collide_6times" },
408 { "tx_collide_7times" },
409 { "tx_collide_8times" },
410 { "tx_collide_9times" },
411 { "tx_collide_10times" },
412 { "tx_collide_11times" },
413 { "tx_collide_12times" },
414 { "tx_collide_13times" },
415 { "tx_collide_14times" },
416 { "tx_collide_15times" },
417 { "tx_ucast_packets" },
418 { "tx_mcast_packets" },
419 { "tx_bcast_packets" },
420 { "tx_carrier_sense_errors" },
421 { "tx_discards" },
422 { "tx_errors" },
423
424 { "dma_writeq_full" },
425 { "dma_write_prioq_full" },
426 { "rxbds_empty" },
427 { "rx_discards" },
428 { "rx_errors" },
429 { "rx_threshold_hit" },
430
431 { "dma_readq_full" },
432 { "dma_read_prioq_full" },
433 { "tx_comp_queue_full" },
434
435 { "ring_set_send_prod_index" },
436 { "ring_status_update" },
437 { "nic_irqs" },
438 { "nic_avoided_irqs" },
4452d099
MC		 439 { "nic_tx_threshold_hit" },
440
441 { "mbuf_lwm_thresh_hit" },
1da177e4
LT		 442};
443
48fa55a0 444#define TG3_NUM_STATS ARRAY_SIZE(ethtool_stats_keys)
93df8b8f
NNS		 445#define TG3_NVRAM_TEST 0
446#define TG3_LINK_TEST 1
447#define TG3_REGISTER_TEST 2
448#define TG3_MEMORY_TEST 3
449#define TG3_MAC_LOOPB_TEST 4
450#define TG3_PHY_LOOPB_TEST 5
451#define TG3_EXT_LOOPB_TEST 6
452#define TG3_INTERRUPT_TEST 7
48fa55a0
MC		 453
454
50da859d 455static const struct {
4cafd3f5 456 const char string[ETH_GSTRING_LEN];
48fa55a0 457} ethtool_test_keys[] = {
93df8b8f
NNS		 458 [TG3_NVRAM_TEST] = { "nvram test (online) " },
459 [TG3_LINK_TEST] = { "link test (online) " },
460 [TG3_REGISTER_TEST] = { "register test (offline)" },
461 [TG3_MEMORY_TEST] = { "memory test (offline)" },
462 [TG3_MAC_LOOPB_TEST] = { "mac loopback test (offline)" },
463 [TG3_PHY_LOOPB_TEST] = { "phy loopback test (offline)" },
464 [TG3_EXT_LOOPB_TEST] = { "ext loopback test (offline)" },
465 [TG3_INTERRUPT_TEST] = { "interrupt test (offline)" },
4cafd3f5
MC		 466};
467
48fa55a0
MC		 468#define TG3_NUM_TEST ARRAY_SIZE(ethtool_test_keys)
469
470
b401e9e2
MC		 471static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
472{
473 writel(val, tp->regs + off);
474}
475
476static u32 tg3_read32(struct tg3 *tp, u32 off)
477{
de6f31eb 478 return readl(tp->regs + off);
b401e9e2
MC		 479}
480
0d3031d9
MC		 481static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val)
482{
483 writel(val, tp->aperegs + off);
484}
485
486static u32 tg3_ape_read32(struct tg3 *tp, u32 off)
487{
de6f31eb 488 return readl(tp->aperegs + off);
0d3031d9
MC		 489}
490
1da177e4
LT		 491static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
492{
6892914f
MC		 493 unsigned long flags;
494
495 spin_lock_irqsave(&tp->indirect_lock, flags);
1ee582d8
MC		 496 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
497 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
6892914f 498 spin_unlock_irqrestore(&tp->indirect_lock, flags);
1ee582d8
MC		 499}
500
501static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
502{
503 writel(val, tp->regs + off);
504 readl(tp->regs + off);
1da177e4
LT		 505}
506
6892914f 507static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
1da177e4 508{
6892914f
MC		 509 unsigned long flags;
510 u32 val;
511
512 spin_lock_irqsave(&tp->indirect_lock, flags);
513 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
514 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
515 spin_unlock_irqrestore(&tp->indirect_lock, flags);
516 return val;
517}
518
519static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
520{
521 unsigned long flags;
522
523 if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
524 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
525 TG3_64BIT_REG_LOW, val);
526 return;
527 }
66711e66 528 if (off == TG3_RX_STD_PROD_IDX_REG) {
6892914f
MC		 529 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
530 TG3_64BIT_REG_LOW, val);
531 return;
1da177e4 532 }
6892914f
MC		 533
534 spin_lock_irqsave(&tp->indirect_lock, flags);
535 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
536 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
537 spin_unlock_irqrestore(&tp->indirect_lock, flags);
538
539 /* In indirect mode when disabling interrupts, we also need
540 * to clear the interrupt bit in the GRC local ctrl register.
541 */
542 if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
543 (val == 0x1)) {
544 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
545 tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
546 }
547}
548
549static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
550{
551 unsigned long flags;
552 u32 val;
553
554 spin_lock_irqsave(&tp->indirect_lock, flags);
555 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
556 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
557 spin_unlock_irqrestore(&tp->indirect_lock, flags);
558 return val;
559}
560
b401e9e2
MC		 561/* usec_wait specifies the wait time in usec when writing to certain registers
562 * where it is unsafe to read back the register without some delay.
563 * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
564 * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
565 */
566static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
6892914f 567{
63c3a66f 568 if (tg3_flag(tp, PCIX_TARGET_HWBUG) || tg3_flag(tp, ICH_WORKAROUND))
b401e9e2
MC		 569 /* Non-posted methods */
570 tp->write32(tp, off, val);
571 else {
572 /* Posted method */
573 tg3_write32(tp, off, val);
574 if (usec_wait)
575 udelay(usec_wait);
576 tp->read32(tp, off);
577 }
578 /* Wait again after the read for the posted method to guarantee that
579 * the wait time is met.
580 */
581 if (usec_wait)
582 udelay(usec_wait);
1da177e4
LT		 583}
584
09ee929c
MC		 585static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
586{
587 tp->write32_mbox(tp, off, val);
7e6c63f0
HM		 588 if (tg3_flag(tp, FLUSH_POSTED_WRITES) ||
589 (!tg3_flag(tp, MBOX_WRITE_REORDER) &&
590 !tg3_flag(tp, ICH_WORKAROUND)))
6892914f 591 tp->read32_mbox(tp, off);
09ee929c
MC		 592}
593
20094930 594static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
1da177e4
LT		 595{
596 void __iomem *mbox = tp->regs + off;
597 writel(val, mbox);
63c3a66f 598 if (tg3_flag(tp, TXD_MBOX_HWBUG))
1da177e4 599 writel(val, mbox);
7e6c63f0
HM		 600 if (tg3_flag(tp, MBOX_WRITE_REORDER) ||
601 tg3_flag(tp, FLUSH_POSTED_WRITES))
1da177e4
LT		 602 readl(mbox);
603}
604
b5d3772c
MC		 605static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
606{
de6f31eb 607 return readl(tp->regs + off + GRCMBOX_BASE);
b5d3772c
MC		 608}
609
610static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
611{
612 writel(val, tp->regs + off + GRCMBOX_BASE);
613}
614
c6cdf436 615#define tw32_mailbox(reg, val) tp->write32_mbox(tp, reg, val)
09ee929c 616#define tw32_mailbox_f(reg, val) tw32_mailbox_flush(tp, (reg), (val))
c6cdf436
MC		 617#define tw32_rx_mbox(reg, val) tp->write32_rx_mbox(tp, reg, val)
618#define tw32_tx_mbox(reg, val) tp->write32_tx_mbox(tp, reg, val)
619#define tr32_mailbox(reg) tp->read32_mbox(tp, reg)
20094930 620
c6cdf436
MC		 621#define tw32(reg, val) tp->write32(tp, reg, val)
622#define tw32_f(reg, val) _tw32_flush(tp, (reg), (val), 0)
623#define tw32_wait_f(reg, val, us) _tw32_flush(tp, (reg), (val), (us))
624#define tr32(reg) tp->read32(tp, reg)
1da177e4
LT		 625
626static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
627{
6892914f
MC		 628 unsigned long flags;
629
4153577a 630 if (tg3_asic_rev(tp) == ASIC_REV_5906 &&
b5d3772c
MC		 631 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
632 return;
633
6892914f 634 spin_lock_irqsave(&tp->indirect_lock, flags);
63c3a66f 635 if (tg3_flag(tp, SRAM_USE_CONFIG)) {
bbadf503
MC		 636 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
637 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
1da177e4 638
bbadf503
MC		 639 /* Always leave this as zero. */
640 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
641 } else {
642 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
643 tw32_f(TG3PCI_MEM_WIN_DATA, val);
28fbef78 644
bbadf503
MC		 645 /* Always leave this as zero. */
646 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
647 }
648 spin_unlock_irqrestore(&tp->indirect_lock, flags);
758a6139
DM		 649}
650
1da177e4
LT		 651static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
652{
6892914f
MC		 653 unsigned long flags;
654
4153577a 655 if (tg3_asic_rev(tp) == ASIC_REV_5906 &&
b5d3772c
MC		 656 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
657 *val = 0;
658 return;
659 }
660
6892914f 661 spin_lock_irqsave(&tp->indirect_lock, flags);
63c3a66f 662 if (tg3_flag(tp, SRAM_USE_CONFIG)) {
bbadf503
MC		 663 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
664 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
1da177e4 665
bbadf503
MC		 666 /* Always leave this as zero. */
667 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
668 } else {
669 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
670 *val = tr32(TG3PCI_MEM_WIN_DATA);
671
672 /* Always leave this as zero. */
673 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
674 }
6892914f 675 spin_unlock_irqrestore(&tp->indirect_lock, flags);
1da177e4
LT		 676}
677
0d3031d9
MC		 678static void tg3_ape_lock_init(struct tg3 *tp)
679{
680 int i;
6f5c8f83 681 u32 regbase, bit;
f92d9dc1 682
4153577a 683 if (tg3_asic_rev(tp) == ASIC_REV_5761)
f92d9dc1
MC		 684 regbase = TG3_APE_LOCK_GRANT;
685 else
686 regbase = TG3_APE_PER_LOCK_GRANT;
0d3031d9
MC		 687
688 /* Make sure the driver hasn't any stale locks. */
78f94dc7
MC		 689 for (i = TG3_APE_LOCK_PHY0; i <= TG3_APE_LOCK_GPIO; i++) {
690 switch (i) {
691 case TG3_APE_LOCK_PHY0:
692 case TG3_APE_LOCK_PHY1:
693 case TG3_APE_LOCK_PHY2:
694 case TG3_APE_LOCK_PHY3:
695 bit = APE_LOCK_GRANT_DRIVER;
696 break;
697 default:
698 if (!tp->pci_fn)
699 bit = APE_LOCK_GRANT_DRIVER;
700 else
701 bit = 1 << tp->pci_fn;
702 }
703 tg3_ape_write32(tp, regbase + 4 * i, bit);
6f5c8f83
MC		 704 }
705
0d3031d9
MC		 706}
707
708static int tg3_ape_lock(struct tg3 *tp, int locknum)
709{
710 int i, off;
711 int ret = 0;
6f5c8f83 712 u32 status, req, gnt, bit;
0d3031d9 713
63c3a66f 714 if (!tg3_flag(tp, ENABLE_APE))
0d3031d9
MC		 715 return 0;
716
717 switch (locknum) {
6f5c8f83 718 case TG3_APE_LOCK_GPIO:
4153577a 719 if (tg3_asic_rev(tp) == ASIC_REV_5761)
6f5c8f83 720 return 0;
33f401ae
MC		 721 case TG3_APE_LOCK_GRC:
722 case TG3_APE_LOCK_MEM:
78f94dc7
MC		 723 if (!tp->pci_fn)
724 bit = APE_LOCK_REQ_DRIVER;
725 else
726 bit = 1 << tp->pci_fn;
33f401ae 727 break;
8151ad57
MC		 728 case TG3_APE_LOCK_PHY0:
729 case TG3_APE_LOCK_PHY1:
730 case TG3_APE_LOCK_PHY2:
731 case TG3_APE_LOCK_PHY3:
732 bit = APE_LOCK_REQ_DRIVER;
733 break;
33f401ae
MC		 734 default:
735 return -EINVAL;
0d3031d9
MC		 736 }
737
4153577a 738 if (tg3_asic_rev(tp) == ASIC_REV_5761) {
f92d9dc1
MC		 739 req = TG3_APE_LOCK_REQ;
740 gnt = TG3_APE_LOCK_GRANT;
741 } else {
742 req = TG3_APE_PER_LOCK_REQ;
743 gnt = TG3_APE_PER_LOCK_GRANT;
744 }
745
0d3031d9
MC		 746 off = 4 * locknum;
747
6f5c8f83 748 tg3_ape_write32(tp, req + off, bit);
0d3031d9
MC		 749
750 /* Wait for up to 1 millisecond to acquire lock. */
751 for (i = 0; i < 100; i++) {
f92d9dc1 752 status = tg3_ape_read32(tp, gnt + off);
6f5c8f83 753 if (status == bit)
0d3031d9 754 break;
6d446ec3
GS		 755 if (pci_channel_offline(tp->pdev))
756 break;
757
0d3031d9
MC		 758 udelay(10);
759 }
760
6f5c8f83 761 if (status != bit) {
0d3031d9 762 /* Revoke the lock request. */
6f5c8f83 763 tg3_ape_write32(tp, gnt + off, bit);
0d3031d9
MC		 764 ret = -EBUSY;
765 }
766
767 return ret;
768}
769
770static void tg3_ape_unlock(struct tg3 *tp, int locknum)
771{
6f5c8f83 772 u32 gnt, bit;
0d3031d9 773
63c3a66f 774 if (!tg3_flag(tp, ENABLE_APE))
0d3031d9
MC		 775 return;
776
777 switch (locknum) {
6f5c8f83 778 case TG3_APE_LOCK_GPIO:
4153577a 779 if (tg3_asic_rev(tp) == ASIC_REV_5761)
6f5c8f83 780 return;
33f401ae
MC		 781 case TG3_APE_LOCK_GRC:
782 case TG3_APE_LOCK_MEM:
78f94dc7
MC		 783 if (!tp->pci_fn)
784 bit = APE_LOCK_GRANT_DRIVER;
785 else
786 bit = 1 << tp->pci_fn;
33f401ae 787 break;
8151ad57
MC		 788 case TG3_APE_LOCK_PHY0:
789 case TG3_APE_LOCK_PHY1:
790 case TG3_APE_LOCK_PHY2:
791 case TG3_APE_LOCK_PHY3:
792 bit = APE_LOCK_GRANT_DRIVER;
793 break;
33f401ae
MC		 794 default:
795 return;
0d3031d9
MC		 796 }
797
4153577a 798 if (tg3_asic_rev(tp) == ASIC_REV_5761)
f92d9dc1
MC		 799 gnt = TG3_APE_LOCK_GRANT;
800 else
801 gnt = TG3_APE_PER_LOCK_GRANT;
802
6f5c8f83 803 tg3_ape_write32(tp, gnt + 4 * locknum, bit);
0d3031d9
MC		 804}
805
b65a372b 806static int tg3_ape_event_lock(struct tg3 *tp, u32 timeout_us)
fd6d3f0e 807{
fd6d3f0e
MC		 808 u32 apedata;
809
b65a372b
MC		 810 while (timeout_us) {
811 if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM))
812 return -EBUSY;
813
814 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
815 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
816 break;
817
818 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
819
820 udelay(10);
821 timeout_us -= (timeout_us > 10) ? 10 : timeout_us;
822 }
823
824 return timeout_us ? 0 : -EBUSY;
825}
826
cf8d55ae
MC		 827static int tg3_ape_wait_for_event(struct tg3 *tp, u32 timeout_us)
828{
829 u32 i, apedata;
830
831 for (i = 0; i < timeout_us / 10; i++) {
832 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
833
834 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
835 break;
836
837 udelay(10);
838 }
839
840 return i == timeout_us / 10;
841}
842
86449944
MC		 843static int tg3_ape_scratchpad_read(struct tg3 *tp, u32 *data, u32 base_off,
844 u32 len)
cf8d55ae
MC		 845{
846 int err;
847 u32 i, bufoff, msgoff, maxlen, apedata;
848
849 if (!tg3_flag(tp, APE_HAS_NCSI))
850 return 0;
851
852 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
853 if (apedata != APE_SEG_SIG_MAGIC)
854 return -ENODEV;
855
856 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
857 if (!(apedata & APE_FW_STATUS_READY))
858 return -EAGAIN;
859
860 bufoff = tg3_ape_read32(tp, TG3_APE_SEG_MSG_BUF_OFF) +
861 TG3_APE_SHMEM_BASE;
862 msgoff = bufoff + 2 * sizeof(u32);
863 maxlen = tg3_ape_read32(tp, TG3_APE_SEG_MSG_BUF_LEN);
864
865 while (len) {
866 u32 length;
867
868 /* Cap xfer sizes to scratchpad limits. */
869 length = (len > maxlen) ? maxlen : len;
870 len -= length;
871
872 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
873 if (!(apedata & APE_FW_STATUS_READY))
874 return -EAGAIN;
875
876 /* Wait for up to 1 msec for APE to service previous event. */
877 err = tg3_ape_event_lock(tp, 1000);
878 if (err)
879 return err;
880
881 apedata = APE_EVENT_STATUS_DRIVER_EVNT |
882 APE_EVENT_STATUS_SCRTCHPD_READ |
883 APE_EVENT_STATUS_EVENT_PENDING;
884 tg3_ape_write32(tp, TG3_APE_EVENT_STATUS, apedata);
885
886 tg3_ape_write32(tp, bufoff, base_off);
887 tg3_ape_write32(tp, bufoff + sizeof(u32), length);
888
889 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
890 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
891
892 base_off += length;
893
894 if (tg3_ape_wait_for_event(tp, 30000))
895 return -EAGAIN;
896
897 for (i = 0; length; i += 4, length -= 4) {
898 u32 val = tg3_ape_read32(tp, msgoff + i);
899 memcpy(data, &val, sizeof(u32));
900 data++;
901 }
902 }
903
904 return 0;
905}
906
b65a372b
MC		 907static int tg3_ape_send_event(struct tg3 *tp, u32 event)
908{
909 int err;
910 u32 apedata;
fd6d3f0e
MC		 911
912 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
913 if (apedata != APE_SEG_SIG_MAGIC)
b65a372b 914 return -EAGAIN;
fd6d3f0e
MC		 915
916 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
917 if (!(apedata & APE_FW_STATUS_READY))
b65a372b 918 return -EAGAIN;
fd6d3f0e
MC		 919
920 /* Wait for up to 1 millisecond for APE to service previous event. */
b65a372b
MC		 921 err = tg3_ape_event_lock(tp, 1000);
922 if (err)
923 return err;
fd6d3f0e 924
b65a372b
MC		 925 tg3_ape_write32(tp, TG3_APE_EVENT_STATUS,
926 event | APE_EVENT_STATUS_EVENT_PENDING);
fd6d3f0e 927
b65a372b
MC		 928 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
929 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
fd6d3f0e 930
b65a372b 931 return 0;
fd6d3f0e
MC		 932}
933
934static void tg3_ape_driver_state_change(struct tg3 *tp, int kind)
935{
936 u32 event;
937 u32 apedata;
938
939 if (!tg3_flag(tp, ENABLE_APE))
940 return;
941
942 switch (kind) {
943 case RESET_KIND_INIT:
944 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG,
945 APE_HOST_SEG_SIG_MAGIC);
946 tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN,
947 APE_HOST_SEG_LEN_MAGIC);
948 apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT);
949 tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata);
950 tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID,
951 APE_HOST_DRIVER_ID_MAGIC(TG3_MAJ_NUM, TG3_MIN_NUM));
952 tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR,
953 APE_HOST_BEHAV_NO_PHYLOCK);
954 tg3_ape_write32(tp, TG3_APE_HOST_DRVR_STATE,
955 TG3_APE_HOST_DRVR_STATE_START);
956
957 event = APE_EVENT_STATUS_STATE_START;
958 break;
959 case RESET_KIND_SHUTDOWN:
960 /* With the interface we are currently using,
961 * APE does not track driver state. Wiping
962 * out the HOST SEGMENT SIGNATURE forces
963 * the APE to assume OS absent status.
964 */
965 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, 0x0);
966
967 if (device_may_wakeup(&tp->pdev->dev) &&
968 tg3_flag(tp, WOL_ENABLE)) {
969 tg3_ape_write32(tp, TG3_APE_HOST_WOL_SPEED,
970 TG3_APE_HOST_WOL_SPEED_AUTO);
971 apedata = TG3_APE_HOST_DRVR_STATE_WOL;
972 } else
973 apedata = TG3_APE_HOST_DRVR_STATE_UNLOAD;
974
975 tg3_ape_write32(tp, TG3_APE_HOST_DRVR_STATE, apedata);
976
977 event = APE_EVENT_STATUS_STATE_UNLOAD;
978 break;
fd6d3f0e
MC		 979 default:
980 return;
981 }
982
983 event |= APE_EVENT_STATUS_DRIVER_EVNT | APE_EVENT_STATUS_STATE_CHNGE;
984
985 tg3_ape_send_event(tp, event);
986}
987
1da177e4
LT		 988static void tg3_disable_ints(struct tg3 *tp)
989{
89aeb3bc
MC		 990 int i;
991
1da177e4
LT		 992 tw32(TG3PCI_MISC_HOST_CTRL,
993 (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
89aeb3bc
MC		 994 for (i = 0; i < tp->irq_max; i++)
995 tw32_mailbox_f(tp->napi[i].int_mbox, 0x00000001);
1da177e4
LT		 996}
997
1da177e4
LT		 998static void tg3_enable_ints(struct tg3 *tp)
999{
89aeb3bc 1000 int i;
89aeb3bc 1001
bbe832c0
MC		 1002 tp->irq_sync = 0;
1003 wmb();
1004
1da177e4
LT		 1005 tw32(TG3PCI_MISC_HOST_CTRL,
1006 (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
89aeb3bc 1007
f89f38b8 1008 tp->coal_now = tp->coalesce_mode | HOSTCC_MODE_ENABLE;
89aeb3bc
MC		 1009 for (i = 0; i < tp->irq_cnt; i++) {
1010 struct tg3_napi *tnapi = &tp->napi[i];
c6cdf436 1011
898a56f8 1012 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
63c3a66f 1013 if (tg3_flag(tp, 1SHOT_MSI))
89aeb3bc 1014 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
f19af9c2 1015
f89f38b8 1016 tp->coal_now |= tnapi->coal_now;
89aeb3bc 1017 }
f19af9c2
MC		 1018
1019 /* Force an initial interrupt */
63c3a66f 1020 if (!tg3_flag(tp, TAGGED_STATUS) &&
f19af9c2
MC		 1021 (tp->napi[0].hw_status->status & SD_STATUS_UPDATED))
1022 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
1023 else
f89f38b8
MC		 1024 tw32(HOSTCC_MODE, tp->coal_now);
1025
1026 tp->coal_now &= ~(tp->napi[0].coal_now | tp->napi[1].coal_now);
1da177e4
LT		 1027}
1028
17375d25 1029static inline unsigned int tg3_has_work(struct tg3_napi *tnapi)
04237ddd 1030{
17375d25 1031 struct tg3 *tp = tnapi->tp;
898a56f8 1032 struct tg3_hw_status *sblk = tnapi->hw_status;
04237ddd
MC		 1033 unsigned int work_exists = 0;
1034
1035 /* check for phy events */
63c3a66f 1036 if (!(tg3_flag(tp, USE_LINKCHG_REG) || tg3_flag(tp, POLL_SERDES))) {
04237ddd
MC		 1037 if (sblk->status & SD_STATUS_LINK_CHG)
1038 work_exists = 1;
1039 }
f891ea16
MC		 1040
1041 /* check for TX work to do */
1042 if (sblk->idx[0].tx_consumer != tnapi->tx_cons)
1043 work_exists = 1;
1044
1045 /* check for RX work to do */
1046 if (tnapi->rx_rcb_prod_idx &&
8d9d7cfc 1047 *(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
04237ddd
MC		 1048 work_exists = 1;
1049
1050 return work_exists;
1051}
1052
17375d25 1053/* tg3_int_reenable
04237ddd
MC		 1054 * similar to tg3_enable_ints, but it accurately determines whether there
1055 * is new work pending and can return without flushing the PIO write
6aa20a22 1056 * which reenables interrupts
1da177e4 1057 */
17375d25 1058static void tg3_int_reenable(struct tg3_napi *tnapi)
1da177e4 1059{
17375d25
MC		 1060 struct tg3 *tp = tnapi->tp;
1061
898a56f8 1062 tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
1da177e4
LT		 1063 mmiowb();
1064
fac9b83e
DM		 1065 /* When doing tagged status, this work check is unnecessary.
1066 * The last_tag we write above tells the chip which piece of
1067 * work we've completed.
1068 */
63c3a66f 1069 if (!tg3_flag(tp, TAGGED_STATUS) && tg3_has_work(tnapi))
04237ddd 1070 tw32(HOSTCC_MODE, tp->coalesce_mode |
fd2ce37f 1071 HOSTCC_MODE_ENABLE | tnapi->coal_now);
1da177e4
LT		 1072}
1073
1da177e4
LT		 1074static void tg3_switch_clocks(struct tg3 *tp)
1075{
f6eb9b1f 1076 u32 clock_ctrl;
1da177e4
LT		 1077 u32 orig_clock_ctrl;
1078
63c3a66f 1079 if (tg3_flag(tp, CPMU_PRESENT) || tg3_flag(tp, 5780_CLASS))
4cf78e4f
MC		 1080 return;
1081
f6eb9b1f
MC		 1082 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
1083
1da177e4
LT		 1084 orig_clock_ctrl = clock_ctrl;
1085 clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
1086 CLOCK_CTRL_CLKRUN_OENABLE |
1087 0x1f);
1088 tp->pci_clock_ctrl = clock_ctrl;
1089
63c3a66f 1090 if (tg3_flag(tp, 5705_PLUS)) {
1da177e4 1091 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
b401e9e2
MC		 1092 tw32_wait_f(TG3PCI_CLOCK_CTRL,
1093 clock_ctrl | CLOCK_CTRL_625_CORE, 40);
1da177e4
LT		 1094 }
1095 } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
b401e9e2
MC		 1096 tw32_wait_f(TG3PCI_CLOCK_CTRL,
1097 clock_ctrl |
1098 (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
1099 40);
1100 tw32_wait_f(TG3PCI_CLOCK_CTRL,
1101 clock_ctrl | (CLOCK_CTRL_ALTCLK),
1102 40);
1da177e4 1103 }
b401e9e2 1104 tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
1da177e4
LT		 1105}
1106
1107#define PHY_BUSY_LOOPS 5000
1108
5c358045
HM		 1109static int __tg3_readphy(struct tg3 *tp, unsigned int phy_addr, int reg,
1110 u32 *val)
1da177e4
LT		 1111{
1112 u32 frame_val;
1113 unsigned int loops;
1114 int ret;
1115
1116 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
1117 tw32_f(MAC_MI_MODE,
1118 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
1119 udelay(80);
1120 }
1121
8151ad57
MC		 1122 tg3_ape_lock(tp, tp->phy_ape_lock);
1123
1da177e4
LT		 1124 *val = 0x0;
1125
5c358045 1126 frame_val = ((phy_addr << MI_COM_PHY_ADDR_SHIFT) &
1da177e4
LT		 1127 MI_COM_PHY_ADDR_MASK);
1128 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
1129 MI_COM_REG_ADDR_MASK);
1130 frame_val |= (MI_COM_CMD_READ | MI_COM_START);
6aa20a22 1131
1da177e4
LT		 1132 tw32_f(MAC_MI_COM, frame_val);
1133
1134 loops = PHY_BUSY_LOOPS;
1135 while (loops != 0) {
1136 udelay(10);
1137 frame_val = tr32(MAC_MI_COM);
1138
1139 if ((frame_val & MI_COM_BUSY) == 0) {
1140 udelay(5);
1141 frame_val = tr32(MAC_MI_COM);
1142 break;
1143 }
1144 loops -= 1;
1145 }
1146
1147 ret = -EBUSY;
1148 if (loops != 0) {
1149 *val = frame_val & MI_COM_DATA_MASK;
1150 ret = 0;
1151 }
1152
1153 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
1154 tw32_f(MAC_MI_MODE, tp->mi_mode);
1155 udelay(80);
1156 }
1157
8151ad57
MC		 1158 tg3_ape_unlock(tp, tp->phy_ape_lock);
1159
1da177e4
LT		 1160 return ret;
1161}
1162
5c358045
HM		 1163static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
1164{
1165 return __tg3_readphy(tp, tp->phy_addr, reg, val);
1166}
1167
1168static int __tg3_writephy(struct tg3 *tp, unsigned int phy_addr, int reg,
1169 u32 val)
1da177e4
LT		 1170{
1171 u32 frame_val;
1172 unsigned int loops;
1173 int ret;
1174
f07e9af3 1175 if ((tp->phy_flags & TG3_PHYFLG_IS_FET) &&
221c5637 1176 (reg == MII_CTRL1000 || reg == MII_TG3_AUX_CTRL))
b5d3772c
MC		 1177 return 0;
1178
1da177e4
LT		 1179 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
1180 tw32_f(MAC_MI_MODE,
1181 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
1182 udelay(80);
1183 }
1184
8151ad57
MC		 1185 tg3_ape_lock(tp, tp->phy_ape_lock);
1186
5c358045 1187 frame_val = ((phy_addr << MI_COM_PHY_ADDR_SHIFT) &
1da177e4
LT		 1188 MI_COM_PHY_ADDR_MASK);
1189 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
1190 MI_COM_REG_ADDR_MASK);
1191 frame_val |= (val & MI_COM_DATA_MASK);
1192 frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
6aa20a22 1193
1da177e4
LT		 1194 tw32_f(MAC_MI_COM, frame_val);
1195
1196 loops = PHY_BUSY_LOOPS;
1197 while (loops != 0) {
1198 udelay(10);
1199 frame_val = tr32(MAC_MI_COM);
1200 if ((frame_val & MI_COM_BUSY) == 0) {
1201 udelay(5);
1202 frame_val = tr32(MAC_MI_COM);
1203 break;
1204 }
1205 loops -= 1;
1206 }
1207
1208 ret = -EBUSY;
1209 if (loops != 0)
1210 ret = 0;
1211
1212 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
1213 tw32_f(MAC_MI_MODE, tp->mi_mode);
1214 udelay(80);
1215 }
1216
8151ad57
MC		 1217 tg3_ape_unlock(tp, tp->phy_ape_lock);
1218
1da177e4
LT		 1219 return ret;
1220}
1221
5c358045
HM		 1222static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
1223{
1224 return __tg3_writephy(tp, tp->phy_addr, reg, val);
1225}
1226
b0988c15
MC		 1227static int tg3_phy_cl45_write(struct tg3 *tp, u32 devad, u32 addr, u32 val)
1228{
1229 int err;
1230
1231 err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad);
1232 if (err)
1233 goto done;
1234
1235 err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr);
1236 if (err)
1237 goto done;
1238
1239 err = tg3_writephy(tp, MII_TG3_MMD_CTRL,
1240 MII_TG3_MMD_CTRL_DATA_NOINC | devad);
1241 if (err)
1242 goto done;
1243
1244 err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, val);
1245
1246done:
1247 return err;
1248}
1249
1250static int tg3_phy_cl45_read(struct tg3 *tp, u32 devad, u32 addr, u32 *val)
1251{
1252 int err;
1253
1254 err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad);
1255 if (err)
1256 goto done;
1257
1258 err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr);
1259 if (err)
1260 goto done;
1261
1262 err = tg3_writephy(tp, MII_TG3_MMD_CTRL,
1263 MII_TG3_MMD_CTRL_DATA_NOINC | devad);
1264 if (err)
1265 goto done;
1266
1267 err = tg3_readphy(tp, MII_TG3_MMD_ADDRESS, val);
1268
1269done:
1270 return err;
1271}
1272
1273static int tg3_phydsp_read(struct tg3 *tp, u32 reg, u32 *val)
1274{
1275 int err;
1276
1277 err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1278 if (!err)
1279 err = tg3_readphy(tp, MII_TG3_DSP_RW_PORT, val);
1280
1281 return err;
1282}
1283
1284static int tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
1285{
1286 int err;
1287
1288 err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1289 if (!err)
1290 err = tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
1291
1292 return err;
1293}
1294
15ee95c3
MC		 1295static int tg3_phy_auxctl_read(struct tg3 *tp, int reg, u32 *val)
1296{
1297 int err;
1298
1299 err = tg3_writephy(tp, MII_TG3_AUX_CTRL,
1300 (reg << MII_TG3_AUXCTL_MISC_RDSEL_SHIFT) |
1301 MII_TG3_AUXCTL_SHDWSEL_MISC);
1302 if (!err)
1303 err = tg3_readphy(tp, MII_TG3_AUX_CTRL, val);
1304
1305 return err;
1306}
1307
b4bd2929
MC		 1308static int tg3_phy_auxctl_write(struct tg3 *tp, int reg, u32 set)
1309{
1310 if (reg == MII_TG3_AUXCTL_SHDWSEL_MISC)
1311 set |= MII_TG3_AUXCTL_MISC_WREN;
1312
1313 return tg3_writephy(tp, MII_TG3_AUX_CTRL, set | reg);
1314}
1315
daf3ec68
NNS		 1316static int tg3_phy_toggle_auxctl_smdsp(struct tg3 *tp, bool enable)
1317{
1318 u32 val;
1319 int err;
1d36ba45 1320
daf3ec68 1321 err = tg3_phy_auxctl_read(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, &val);
1d36ba45 1322
daf3ec68
NNS		 1323 if (err)
1324 return err;
daf3ec68 1325
7c10ee32 1326 if (enable)
daf3ec68
NNS		 1327 val |= MII_TG3_AUXCTL_ACTL_SMDSP_ENA;
1328 else
1329 val &= ~MII_TG3_AUXCTL_ACTL_SMDSP_ENA;
1330
1331 err = tg3_phy_auxctl_write((tp), MII_TG3_AUXCTL_SHDWSEL_AUXCTL,
1332 val | MII_TG3_AUXCTL_ACTL_TX_6DB);
1333
1334 return err;
1335}
1d36ba45 1336
3ab71071
NS		 1337static int tg3_phy_shdw_write(struct tg3 *tp, int reg, u32 val)
1338{
1339 return tg3_writephy(tp, MII_TG3_MISC_SHDW,
1340 reg | val | MII_TG3_MISC_SHDW_WREN);
1341}
1342
95e2869a
MC		 1343static int tg3_bmcr_reset(struct tg3 *tp)
1344{
1345 u32 phy_control;
1346 int limit, err;
1347
1348 /* OK, reset it, and poll the BMCR_RESET bit until it
1349 * clears or we time out.
1350 */
1351 phy_control = BMCR_RESET;
1352 err = tg3_writephy(tp, MII_BMCR, phy_control);
1353 if (err != 0)
1354 return -EBUSY;
1355
1356 limit = 5000;
1357 while (limit--) {
1358 err = tg3_readphy(tp, MII_BMCR, &phy_control);
1359 if (err != 0)
1360 return -EBUSY;
1361
1362 if ((phy_control & BMCR_RESET) == 0) {
1363 udelay(40);
1364 break;
1365 }
1366 udelay(10);
1367 }
d4675b52 1368 if (limit < 0)
95e2869a
MC		 1369 return -EBUSY;
1370
1371 return 0;
1372}
1373
158d7abd
MC		 1374static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg)
1375{
3d16543d 1376 struct tg3 *tp = bp->priv;
158d7abd
MC		 1377 u32 val;
1378
24bb4fb6 1379 spin_lock_bh(&tp->lock);
158d7abd 1380
ead2402c 1381 if (__tg3_readphy(tp, mii_id, reg, &val))
24bb4fb6
MC		 1382 val = -EIO;
1383
1384 spin_unlock_bh(&tp->lock);
158d7abd
MC		 1385
1386 return val;
1387}
1388
1389static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val)
1390{
3d16543d 1391 struct tg3 *tp = bp->priv;
24bb4fb6 1392 u32 ret = 0;
158d7abd 1393
24bb4fb6 1394 spin_lock_bh(&tp->lock);
158d7abd 1395
ead2402c 1396 if (__tg3_writephy(tp, mii_id, reg, val))
24bb4fb6 1397 ret = -EIO;
158d7abd 1398
24bb4fb6
MC		 1399 spin_unlock_bh(&tp->lock);
1400
1401 return ret;
158d7abd
MC		 1402}
1403
9c61d6bc 1404static void tg3_mdio_config_5785(struct tg3 *tp)
a9daf367
MC		 1405{
1406 u32 val;
fcb389df 1407 struct phy_device *phydev;
a9daf367 1408
ead2402c 1409 phydev = tp->mdio_bus->phy_map[tp->phy_addr];
fcb389df 1410 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
6a443a0f
MC		 1411 case PHY_ID_BCM50610:
1412 case PHY_ID_BCM50610M:
fcb389df
MC		 1413 val = MAC_PHYCFG2_50610_LED_MODES;
1414 break;
6a443a0f 1415 case PHY_ID_BCMAC131:
fcb389df
MC		 1416 val = MAC_PHYCFG2_AC131_LED_MODES;
1417 break;
6a443a0f 1418 case PHY_ID_RTL8211C:
fcb389df
MC		 1419 val = MAC_PHYCFG2_RTL8211C_LED_MODES;
1420 break;
6a443a0f 1421 case PHY_ID_RTL8201E:
fcb389df
MC		 1422 val = MAC_PHYCFG2_RTL8201E_LED_MODES;
1423 break;
1424 default:
a9daf367 1425 return;
fcb389df
MC		 1426 }
1427
1428 if (phydev->interface != PHY_INTERFACE_MODE_RGMII) {
1429 tw32(MAC_PHYCFG2, val);
1430
1431 val = tr32(MAC_PHYCFG1);
bb85fbb6
MC		 1432 val &= ~(MAC_PHYCFG1_RGMII_INT |
1433 MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK);
1434 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT;
fcb389df
MC		 1435 tw32(MAC_PHYCFG1, val);
1436
1437 return;
1438 }
1439
63c3a66f 1440 if (!tg3_flag(tp, RGMII_INBAND_DISABLE))
fcb389df
MC		 1441 val |= MAC_PHYCFG2_EMODE_MASK_MASK |
1442 MAC_PHYCFG2_FMODE_MASK_MASK |
1443 MAC_PHYCFG2_GMODE_MASK_MASK |
1444 MAC_PHYCFG2_ACT_MASK_MASK |
1445 MAC_PHYCFG2_QUAL_MASK_MASK |
1446 MAC_PHYCFG2_INBAND_ENABLE;
1447
1448 tw32(MAC_PHYCFG2, val);
a9daf367 1449
bb85fbb6
MC		 1450 val = tr32(MAC_PHYCFG1);
1451 val &= ~(MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK |
1452 MAC_PHYCFG1_RGMII_EXT_RX_DEC | MAC_PHYCFG1_RGMII_SND_STAT_EN);
63c3a66f
JP		 1453 if (!tg3_flag(tp, RGMII_INBAND_DISABLE)) {
1454 if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN))
a9daf367 1455 val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC;
63c3a66f 1456 if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN))
a9daf367
MC		 1457 val |= MAC_PHYCFG1_RGMII_SND_STAT_EN;
1458 }
bb85fbb6
MC		 1459 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT |
1460 MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV;
1461 tw32(MAC_PHYCFG1, val);
a9daf367 1462
a9daf367
MC		 1463 val = tr32(MAC_EXT_RGMII_MODE);
1464 val &= ~(MAC_RGMII_MODE_RX_INT_B |
1465 MAC_RGMII_MODE_RX_QUALITY |
1466 MAC_RGMII_MODE_RX_ACTIVITY |
1467 MAC_RGMII_MODE_RX_ENG_DET |
1468 MAC_RGMII_MODE_TX_ENABLE |
1469 MAC_RGMII_MODE_TX_LOWPWR |
1470 MAC_RGMII_MODE_TX_RESET);
63c3a66f
JP		 1471 if (!tg3_flag(tp, RGMII_INBAND_DISABLE)) {
1472 if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN))
a9daf367
MC		 1473 val |= MAC_RGMII_MODE_RX_INT_B |
1474 MAC_RGMII_MODE_RX_QUALITY |
1475 MAC_RGMII_MODE_RX_ACTIVITY |
1476 MAC_RGMII_MODE_RX_ENG_DET;
63c3a66f 1477 if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN))
a9daf367
MC		 1478 val |= MAC_RGMII_MODE_TX_ENABLE |
1479 MAC_RGMII_MODE_TX_LOWPWR |
1480 MAC_RGMII_MODE_TX_RESET;
1481 }
1482 tw32(MAC_EXT_RGMII_MODE, val);
1483}
1484
158d7abd
MC		 1485static void tg3_mdio_start(struct tg3 *tp)
1486{
158d7abd
MC		 1487 tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL;
1488 tw32_f(MAC_MI_MODE, tp->mi_mode);
1489 udelay(80);
a9daf367 1490
63c3a66f 1491 if (tg3_flag(tp, MDIOBUS_INITED) &&
4153577a 1492 tg3_asic_rev(tp) == ASIC_REV_5785)
9ea4818d
MC		 1493 tg3_mdio_config_5785(tp);
1494}
1495
1496static int tg3_mdio_init(struct tg3 *tp)
1497{
1498 int i;
1499 u32 reg;
1500 struct phy_device *phydev;
1501
63c3a66f 1502 if (tg3_flag(tp, 5717_PLUS)) {
9c7df915 1503 u32 is_serdes;
882e9793 1504
69f11c99 1505 tp->phy_addr = tp->pci_fn + 1;
882e9793 1506
4153577a 1507 if (tg3_chip_rev_id(tp) != CHIPREV_ID_5717_A0)
d1ec96af
MC		 1508 is_serdes = tr32(SG_DIG_STATUS) & SG_DIG_IS_SERDES;
1509 else
1510 is_serdes = tr32(TG3_CPMU_PHY_STRAP) &
1511 TG3_CPMU_PHY_STRAP_IS_SERDES;
882e9793
MC		 1512 if (is_serdes)
1513 tp->phy_addr += 7;
ee002b64
HM		 1514 } else if (tg3_flag(tp, IS_SSB_CORE) && tg3_flag(tp, ROBOSWITCH)) {
1515 int addr;
1516
1517 addr = ssb_gige_get_phyaddr(tp->pdev);
1518 if (addr < 0)
1519 return addr;
1520 tp->phy_addr = addr;
882e9793 1521 } else
3f0e3ad7 1522 tp->phy_addr = TG3_PHY_MII_ADDR;
882e9793 1523
158d7abd
MC		 1524 tg3_mdio_start(tp);
1525
63c3a66f 1526 if (!tg3_flag(tp, USE_PHYLIB) || tg3_flag(tp, MDIOBUS_INITED))
158d7abd
MC		 1527 return 0;
1528
298cf9be
LB		 1529 tp->mdio_bus = mdiobus_alloc();
1530 if (tp->mdio_bus == NULL)
1531 return -ENOMEM;
158d7abd 1532
298cf9be
LB		 1533 tp->mdio_bus->name = "tg3 mdio bus";
1534 snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x",
158d7abd 1535 (tp->pdev->bus->number << 8) | tp->pdev->devfn);
298cf9be
LB		 1536 tp->mdio_bus->priv = tp;
1537 tp->mdio_bus->parent = &tp->pdev->dev;
1538 tp->mdio_bus->read = &tg3_mdio_read;
1539 tp->mdio_bus->write = &tg3_mdio_write;
ead2402c 1540 tp->mdio_bus->phy_mask = ~(1 << tp->phy_addr);
298cf9be 1541 tp->mdio_bus->irq = &tp->mdio_irq[0];
158d7abd
MC		 1542
1543 for (i = 0; i < PHY_MAX_ADDR; i++)
298cf9be 1544 tp->mdio_bus->irq[i] = PHY_POLL;
158d7abd
MC		 1545
1546 /* The bus registration will look for all the PHYs on the mdio bus.
1547 * Unfortunately, it does not ensure the PHY is powered up before
1548 * accessing the PHY ID registers. A chip reset is the
1549 * quickest way to bring the device back to an operational state..
1550 */
1551 if (tg3_readphy(tp, MII_BMCR, &reg) || (reg & BMCR_PDOWN))
1552 tg3_bmcr_reset(tp);
1553
298cf9be 1554 i = mdiobus_register(tp->mdio_bus);
a9daf367 1555 if (i) {
ab96b241 1556 dev_warn(&tp->pdev->dev, "mdiobus_reg failed (0x%x)\n", i);
9c61d6bc 1557 mdiobus_free(tp->mdio_bus);
a9daf367
MC		 1558 return i;
1559 }
158d7abd 1560
ead2402c 1561 phydev = tp->mdio_bus->phy_map[tp->phy_addr];
a9daf367 1562
9c61d6bc 1563 if (!phydev || !phydev->drv) {
ab96b241 1564 dev_warn(&tp->pdev->dev, "No PHY devices\n");
9c61d6bc
MC		 1565 mdiobus_unregister(tp->mdio_bus);
1566 mdiobus_free(tp->mdio_bus);
1567 return -ENODEV;
1568 }
1569
1570 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
6a443a0f 1571 case PHY_ID_BCM57780:
321d32a0 1572 phydev->interface = PHY_INTERFACE_MODE_GMII;
c704dc23 1573 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
321d32a0 1574 break;
6a443a0f
MC		 1575 case PHY_ID_BCM50610:
1576 case PHY_ID_BCM50610M:
32e5a8d6 1577 phydev->dev_flags |= PHY_BRCM_CLEAR_RGMII_MODE |
c704dc23 1578 PHY_BRCM_RX_REFCLK_UNUSED |
52fae083 1579 PHY_BRCM_DIS_TXCRXC_NOENRGY |
c704dc23 1580 PHY_BRCM_AUTO_PWRDWN_ENABLE;
63c3a66f 1581 if (tg3_flag(tp, RGMII_INBAND_DISABLE))
a9daf367 1582 phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE;
63c3a66f 1583 if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN))
a9daf367 1584 phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE;
63c3a66f 1585 if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN))
a9daf367 1586 phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE;
fcb389df 1587 /* fallthru */
6a443a0f 1588 case PHY_ID_RTL8211C:
fcb389df 1589 phydev->interface = PHY_INTERFACE_MODE_RGMII;
a9daf367 1590 break;
6a443a0f
MC		 1591 case PHY_ID_RTL8201E:
1592 case PHY_ID_BCMAC131:
a9daf367 1593 phydev->interface = PHY_INTERFACE_MODE_MII;
cdd4e09d 1594 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
f07e9af3 1595 tp->phy_flags |= TG3_PHYFLG_IS_FET;
a9daf367
MC		 1596 break;
1597 }
1598
63c3a66f 1599 tg3_flag_set(tp, MDIOBUS_INITED);
9c61d6bc 1600
4153577a 1601 if (tg3_asic_rev(tp) == ASIC_REV_5785)
9c61d6bc 1602 tg3_mdio_config_5785(tp);
a9daf367
MC		 1603
1604 return 0;
158d7abd
MC		 1605}
1606
1607static void tg3_mdio_fini(struct tg3 *tp)
1608{
63c3a66f
JP		 1609 if (tg3_flag(tp, MDIOBUS_INITED)) {
1610 tg3_flag_clear(tp, MDIOBUS_INITED);
298cf9be
LB		 1611 mdiobus_unregister(tp->mdio_bus);
1612 mdiobus_free(tp->mdio_bus);
158d7abd
MC		 1613 }
1614}
1615
4ba526ce
MC		 1616/* tp->lock is held. */
1617static inline void tg3_generate_fw_event(struct tg3 *tp)
1618{
1619 u32 val;
1620
1621 val = tr32(GRC_RX_CPU_EVENT);
1622 val |= GRC_RX_CPU_DRIVER_EVENT;
1623 tw32_f(GRC_RX_CPU_EVENT, val);
1624
1625 tp->last_event_jiffies = jiffies;
1626}
1627
1628#define TG3_FW_EVENT_TIMEOUT_USEC 2500
1629
95e2869a
MC		 1630/* tp->lock is held. */
1631static void tg3_wait_for_event_ack(struct tg3 *tp)
1632{
1633 int i;
4ba526ce
MC		 1634 unsigned int delay_cnt;
1635 long time_remain;
1636
1637 /* If enough time has passed, no wait is necessary. */
1638 time_remain = (long)(tp->last_event_jiffies + 1 +
1639 usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) -
1640 (long)jiffies;
1641 if (time_remain < 0)
1642 return;
1643
1644 /* Check if we can shorten the wait time. */
1645 delay_cnt = jiffies_to_usecs(time_remain);
1646 if (delay_cnt > TG3_FW_EVENT_TIMEOUT_USEC)
1647 delay_cnt = TG3_FW_EVENT_TIMEOUT_USEC;
1648 delay_cnt = (delay_cnt >> 3) + 1;
95e2869a 1649
4ba526ce 1650 for (i = 0; i < delay_cnt; i++) {
95e2869a
MC		 1651 if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT))
1652 break;
6d446ec3
GS		 1653 if (pci_channel_offline(tp->pdev))
1654 break;
1655
4ba526ce 1656 udelay(8);
95e2869a
MC		 1657 }
1658}
1659
1660/* tp->lock is held. */
b28f389d 1661static void tg3_phy_gather_ump_data(struct tg3 *tp, u32 *data)
95e2869a 1662{
b28f389d 1663 u32 reg, val;
95e2869a
MC		 1664
1665 val = 0;
1666 if (!tg3_readphy(tp, MII_BMCR, &reg))
1667 val = reg << 16;
1668 if (!tg3_readphy(tp, MII_BMSR, &reg))
1669 val |= (reg & 0xffff);
b28f389d 1670 *data++ = val;
95e2869a
MC		 1671
1672 val = 0;
1673 if (!tg3_readphy(tp, MII_ADVERTISE, &reg))
1674 val = reg << 16;
1675 if (!tg3_readphy(tp, MII_LPA, &reg))
1676 val |= (reg & 0xffff);
b28f389d 1677 *data++ = val;
95e2869a
MC		 1678
1679 val = 0;
f07e9af3 1680 if (!(tp->phy_flags & TG3_PHYFLG_MII_SERDES)) {
95e2869a
MC		 1681 if (!tg3_readphy(tp, MII_CTRL1000, &reg))
1682 val = reg << 16;
1683 if (!tg3_readphy(tp, MII_STAT1000, &reg))
1684 val |= (reg & 0xffff);
1685 }
b28f389d 1686 *data++ = val;
95e2869a
MC		 1687
1688 if (!tg3_readphy(tp, MII_PHYADDR, &reg))
1689 val = reg << 16;
1690 else
1691 val = 0;
b28f389d
MC		 1692 *data++ = val;
1693}
1694
1695/* tp->lock is held. */
1696static void tg3_ump_link_report(struct tg3 *tp)
1697{
1698 u32 data[4];
1699
1700 if (!tg3_flag(tp, 5780_CLASS) || !tg3_flag(tp, ENABLE_ASF))
1701 return;
1702
1703 tg3_phy_gather_ump_data(tp, data);
1704
1705 tg3_wait_for_event_ack(tp);
1706
1707 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE);
1708 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14);
1709 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0x0, data[0]);
1710 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0x4, data[1]);
1711 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0x8, data[2]);
1712 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0xc, data[3]);
95e2869a 1713
4ba526ce 1714 tg3_generate_fw_event(tp);
95e2869a
MC		 1715}
1716
8d5a89b3
MC		 1717/* tp->lock is held. */
1718static void tg3_stop_fw(struct tg3 *tp)
1719{
1720 if (tg3_flag(tp, ENABLE_ASF) && !tg3_flag(tp, ENABLE_APE)) {
1721 /* Wait for RX cpu to ACK the previous event. */
1722 tg3_wait_for_event_ack(tp);
1723
1724 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
1725
1726 tg3_generate_fw_event(tp);
1727
1728 /* Wait for RX cpu to ACK this event. */
1729 tg3_wait_for_event_ack(tp);
1730 }
1731}
1732
fd6d3f0e
MC		 1733/* tp->lock is held. */
1734static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
1735{
1736 tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
1737 NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
1738
1739 if (tg3_flag(tp, ASF_NEW_HANDSHAKE)) {
1740 switch (kind) {
1741 case RESET_KIND_INIT:
1742 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1743 DRV_STATE_START);
1744 break;
1745
1746 case RESET_KIND_SHUTDOWN:
1747 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1748 DRV_STATE_UNLOAD);
1749 break;
1750
1751 case RESET_KIND_SUSPEND:
1752 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1753 DRV_STATE_SUSPEND);
1754 break;
1755
1756 default:
1757 break;
1758 }
1759 }
fd6d3f0e
MC		 1760}
1761
1762/* tp->lock is held. */
1763static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
1764{
1765 if (tg3_flag(tp, ASF_NEW_HANDSHAKE)) {
1766 switch (kind) {
1767 case RESET_KIND_INIT:
1768 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1769 DRV_STATE_START_DONE);
1770 break;
1771
1772 case RESET_KIND_SHUTDOWN:
1773 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1774 DRV_STATE_UNLOAD_DONE);
1775 break;
1776
1777 default:
1778 break;
1779 }
1780 }
fd6d3f0e
MC		 1781}
1782
1783/* tp->lock is held. */
1784static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
1785{
1786 if (tg3_flag(tp, ENABLE_ASF)) {
1787 switch (kind) {
1788 case RESET_KIND_INIT:
1789 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1790 DRV_STATE_START);
1791 break;
1792
1793 case RESET_KIND_SHUTDOWN:
1794 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1795 DRV_STATE_UNLOAD);
1796 break;
1797
1798 case RESET_KIND_SUSPEND:
1799 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1800 DRV_STATE_SUSPEND);
1801 break;
1802
1803 default:
1804 break;
1805 }
1806 }
1807}
1808
1809static int tg3_poll_fw(struct tg3 *tp)
1810{
1811 int i;
1812 u32 val;
1813
df465abf
NS		 1814 if (tg3_flag(tp, NO_FWARE_REPORTED))
1815 return 0;
1816
7e6c63f0
HM		 1817 if (tg3_flag(tp, IS_SSB_CORE)) {
1818 /* We don't use firmware. */
1819 return 0;
1820 }
1821
4153577a 1822 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
fd6d3f0e
MC		 1823 /* Wait up to 20ms for init done. */
1824 for (i = 0; i < 200; i++) {
1825 if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
1826 return 0;
6d446ec3
GS		 1827 if (pci_channel_offline(tp->pdev))
1828 return -ENODEV;
1829
fd6d3f0e
MC		 1830 udelay(100);
1831 }
1832 return -ENODEV;
1833 }
1834
1835 /* Wait for firmware initialization to complete. */
1836 for (i = 0; i < 100000; i++) {
1837 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
1838 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
1839 break;
6d446ec3
GS		 1840 if (pci_channel_offline(tp->pdev)) {
1841 if (!tg3_flag(tp, NO_FWARE_REPORTED)) {
1842 tg3_flag_set(tp, NO_FWARE_REPORTED);
1843 netdev_info(tp->dev, "No firmware running\n");
1844 }
1845
1846 break;
1847 }
1848
fd6d3f0e
MC		 1849 udelay(10);
1850 }
1851
1852 /* Chip might not be fitted with firmware. Some Sun onboard
1853 * parts are configured like that. So don't signal the timeout
1854 * of the above loop as an error, but do report the lack of
1855 * running firmware once.
1856 */
1857 if (i >= 100000 && !tg3_flag(tp, NO_FWARE_REPORTED)) {
1858 tg3_flag_set(tp, NO_FWARE_REPORTED);
1859
1860 netdev_info(tp->dev, "No firmware running\n");
1861 }
1862
4153577a 1863 if (tg3_chip_rev_id(tp) == CHIPREV_ID_57765_A0) {
fd6d3f0e
MC		 1864 /* The 57765 A0 needs a little more
1865 * time to do some important work.
1866 */
1867 mdelay(10);
1868 }
1869
1870 return 0;
1871}
1872
95e2869a
MC		 1873static void tg3_link_report(struct tg3 *tp)
1874{
1875 if (!netif_carrier_ok(tp->dev)) {
05dbe005 1876 netif_info(tp, link, tp->dev, "Link is down\n");
95e2869a
MC		 1877 tg3_ump_link_report(tp);
1878 } else if (netif_msg_link(tp)) {
05dbe005
JP		 1879 netdev_info(tp->dev, "Link is up at %d Mbps, %s duplex\n",
1880 (tp->link_config.active_speed == SPEED_1000 ?
1881 1000 :
1882 (tp->link_config.active_speed == SPEED_100 ?
1883 100 : 10)),
1884 (tp->link_config.active_duplex == DUPLEX_FULL ?
1885 "full" : "half"));
1886
1887 netdev_info(tp->dev, "Flow control is %s for TX and %s for RX\n",
1888 (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ?
1889 "on" : "off",
1890 (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ?
1891 "on" : "off");
47007831
MC		 1892
1893 if (tp->phy_flags & TG3_PHYFLG_EEE_CAP)
1894 netdev_info(tp->dev, "EEE is %s\n",
1895 tp->setlpicnt ? "enabled" : "disabled");
1896
95e2869a
MC		 1897 tg3_ump_link_report(tp);
1898 }
84421b99
NS		 1899
1900 tp->link_up = netif_carrier_ok(tp->dev);
95e2869a
MC		 1901}
1902
fdad8de4
NS		 1903static u32 tg3_decode_flowctrl_1000T(u32 adv)
1904{
1905 u32 flowctrl = 0;
1906
1907 if (adv & ADVERTISE_PAUSE_CAP) {
1908 flowctrl |= FLOW_CTRL_RX;
1909 if (!(adv & ADVERTISE_PAUSE_ASYM))
1910 flowctrl |= FLOW_CTRL_TX;
1911 } else if (adv & ADVERTISE_PAUSE_ASYM)
1912 flowctrl |= FLOW_CTRL_TX;
1913
1914 return flowctrl;
1915}
1916
95e2869a
MC		 1917static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl)
1918{
1919 u16 miireg;
1920
e18ce346 1921 if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
95e2869a 1922 miireg = ADVERTISE_1000XPAUSE;
e18ce346 1923 else if (flow_ctrl & FLOW_CTRL_TX)
95e2869a 1924 miireg = ADVERTISE_1000XPSE_ASYM;
e18ce346 1925 else if (flow_ctrl & FLOW_CTRL_RX)
95e2869a
MC		 1926 miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1927 else
1928 miireg = 0;
1929
1930 return miireg;
1931}
1932
fdad8de4
NS		 1933static u32 tg3_decode_flowctrl_1000X(u32 adv)
1934{
1935 u32 flowctrl = 0;
1936
1937 if (adv & ADVERTISE_1000XPAUSE) {
1938 flowctrl |= FLOW_CTRL_RX;
1939 if (!(adv & ADVERTISE_1000XPSE_ASYM))
1940 flowctrl |= FLOW_CTRL_TX;
1941 } else if (adv & ADVERTISE_1000XPSE_ASYM)
1942 flowctrl |= FLOW_CTRL_TX;
1943
1944 return flowctrl;
1945}
1946
95e2869a
MC		 1947static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv)
1948{
1949 u8 cap = 0;
1950
f3791cdf
MC		 1951 if (lcladv & rmtadv & ADVERTISE_1000XPAUSE) {
1952 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1953 } else if (lcladv & rmtadv & ADVERTISE_1000XPSE_ASYM) {
1954 if (lcladv & ADVERTISE_1000XPAUSE)
1955 cap = FLOW_CTRL_RX;
1956 if (rmtadv & ADVERTISE_1000XPAUSE)
e18ce346 1957 cap = FLOW_CTRL_TX;
95e2869a
MC		 1958 }
1959
1960 return cap;
1961}
1962
f51f3562 1963static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv)
95e2869a 1964{
b02fd9e3 1965 u8 autoneg;
f51f3562 1966 u8 flowctrl = 0;
95e2869a
MC		 1967 u32 old_rx_mode = tp->rx_mode;
1968 u32 old_tx_mode = tp->tx_mode;
1969
63c3a66f 1970 if (tg3_flag(tp, USE_PHYLIB))
ead2402c 1971 autoneg = tp->mdio_bus->phy_map[tp->phy_addr]->autoneg;
b02fd9e3
MC		 1972 else
1973 autoneg = tp->link_config.autoneg;
1974
63c3a66f 1975 if (autoneg == AUTONEG_ENABLE && tg3_flag(tp, PAUSE_AUTONEG)) {
f07e9af3 1976 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
f51f3562 1977 flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv);
95e2869a 1978 else
bc02ff95 1979 flowctrl = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
f51f3562
MC		 1980 } else
1981 flowctrl = tp->link_config.flowctrl;
95e2869a 1982
f51f3562 1983 tp->link_config.active_flowctrl = flowctrl;
95e2869a 1984
e18ce346 1985 if (flowctrl & FLOW_CTRL_RX)
95e2869a
MC		 1986 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1987 else
1988 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1989
f51f3562 1990 if (old_rx_mode != tp->rx_mode)
95e2869a 1991 tw32_f(MAC_RX_MODE, tp->rx_mode);
95e2869a 1992
e18ce346 1993 if (flowctrl & FLOW_CTRL_TX)
95e2869a
MC		 1994 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1995 else
1996 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1997
f51f3562 1998 if (old_tx_mode != tp->tx_mode)
95e2869a 1999 tw32_f(MAC_TX_MODE, tp->tx_mode);
95e2869a
MC		 2000}
2001
b02fd9e3
MC		 2002static void tg3_adjust_link(struct net_device *dev)
2003{
2004 u8 oldflowctrl, linkmesg = 0;
2005 u32 mac_mode, lcl_adv, rmt_adv;
2006 struct tg3 *tp = netdev_priv(dev);
ead2402c 2007 struct phy_device *phydev = tp->mdio_bus->phy_map[tp->phy_addr];
b02fd9e3 2008
24bb4fb6 2009 spin_lock_bh(&tp->lock);
b02fd9e3
MC		 2010
2011 mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK |
2012 MAC_MODE_HALF_DUPLEX);
2013
2014 oldflowctrl = tp->link_config.active_flowctrl;
2015
2016 if (phydev->link) {
2017 lcl_adv = 0;
2018 rmt_adv = 0;
2019
2020 if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10)
2021 mac_mode |= MAC_MODE_PORT_MODE_MII;
c3df0748 2022 else if (phydev->speed == SPEED_1000 ||
4153577a 2023 tg3_asic_rev(tp) != ASIC_REV_5785)
b02fd9e3 2024 mac_mode |= MAC_MODE_PORT_MODE_GMII;
c3df0748
MC		 2025 else
2026 mac_mode |= MAC_MODE_PORT_MODE_MII;
b02fd9e3
MC		 2027
2028 if (phydev->duplex == DUPLEX_HALF)
2029 mac_mode |= MAC_MODE_HALF_DUPLEX;
2030 else {
f88788f0 2031 lcl_adv = mii_advertise_flowctrl(
b02fd9e3
MC		 2032 tp->link_config.flowctrl);
2033
2034 if (phydev->pause)
2035 rmt_adv = LPA_PAUSE_CAP;
2036 if (phydev->asym_pause)
2037 rmt_adv |= LPA_PAUSE_ASYM;
2038 }
2039
2040 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
2041 } else
2042 mac_mode |= MAC_MODE_PORT_MODE_GMII;
2043
2044 if (mac_mode != tp->mac_mode) {
2045 tp->mac_mode = mac_mode;
2046 tw32_f(MAC_MODE, tp->mac_mode);
2047 udelay(40);
2048 }
2049
4153577a 2050 if (tg3_asic_rev(tp) == ASIC_REV_5785) {
fcb389df
MC		 2051 if (phydev->speed == SPEED_10)
2052 tw32(MAC_MI_STAT,
2053 MAC_MI_STAT_10MBPS_MODE |
2054 MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
2055 else
2056 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
2057 }
2058
b02fd9e3
MC		 2059 if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF)
2060 tw32(MAC_TX_LENGTHS,
2061 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
2062 (6 << TX_LENGTHS_IPG_SHIFT) |
2063 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
2064 else
2065 tw32(MAC_TX_LENGTHS,
2066 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
2067 (6 << TX_LENGTHS_IPG_SHIFT) |
2068 (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
2069
34655ad6 2070 if (phydev->link != tp->old_link ||
b02fd9e3
MC		 2071 phydev->speed != tp->link_config.active_speed ||
2072 phydev->duplex != tp->link_config.active_duplex ||
2073 oldflowctrl != tp->link_config.active_flowctrl)
c6cdf436 2074 linkmesg = 1;
b02fd9e3 2075
34655ad6 2076 tp->old_link = phydev->link;
b02fd9e3
MC		 2077 tp->link_config.active_speed = phydev->speed;
2078 tp->link_config.active_duplex = phydev->duplex;
2079
24bb4fb6 2080 spin_unlock_bh(&tp->lock);
b02fd9e3
MC		 2081
2082 if (linkmesg)
2083 tg3_link_report(tp);
2084}
2085
2086static int tg3_phy_init(struct tg3 *tp)
2087{
2088 struct phy_device *phydev;
2089
f07e9af3 2090 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)
b02fd9e3
MC		 2091 return 0;
2092
2093 /* Bring the PHY back to a known state. */
2094 tg3_bmcr_reset(tp);
2095
ead2402c 2096 phydev = tp->mdio_bus->phy_map[tp->phy_addr];
b02fd9e3
MC		 2097
2098 /* Attach the MAC to the PHY. */
f9a8f83b
FF		 2099 phydev = phy_connect(tp->dev, dev_name(&phydev->dev),
2100 tg3_adjust_link, phydev->interface);
b02fd9e3 2101 if (IS_ERR(phydev)) {
ab96b241 2102 dev_err(&tp->pdev->dev, "Could not attach to PHY\n");
b02fd9e3
MC		 2103 return PTR_ERR(phydev);
2104 }
2105
b02fd9e3 2106 /* Mask with MAC supported features. */
9c61d6bc
MC		 2107 switch (phydev->interface) {
2108 case PHY_INTERFACE_MODE_GMII:
2109 case PHY_INTERFACE_MODE_RGMII:
f07e9af3 2110 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
321d32a0
MC		 2111 phydev->supported &= (PHY_GBIT_FEATURES |
2112 SUPPORTED_Pause |
2113 SUPPORTED_Asym_Pause);
2114 break;
2115 }
2116 /* fallthru */
9c61d6bc
MC		 2117 case PHY_INTERFACE_MODE_MII:
2118 phydev->supported &= (PHY_BASIC_FEATURES |
2119 SUPPORTED_Pause |
2120 SUPPORTED_Asym_Pause);
2121 break;
2122 default:
ead2402c 2123 phy_disconnect(tp->mdio_bus->phy_map[tp->phy_addr]);
9c61d6bc
MC		 2124 return -EINVAL;
2125 }
2126
f07e9af3 2127 tp->phy_flags |= TG3_PHYFLG_IS_CONNECTED;
b02fd9e3
MC		 2128
2129 phydev->advertising = phydev->supported;
2130
b02fd9e3
MC		 2131 return 0;
2132}
2133
2134static void tg3_phy_start(struct tg3 *tp)
2135{
2136 struct phy_device *phydev;
2137
f07e9af3 2138 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
b02fd9e3
MC		 2139 return;
2140
ead2402c 2141 phydev = tp->mdio_bus->phy_map[tp->phy_addr];
b02fd9e3 2142
80096068
MC		 2143 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
2144 tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER;
c6700ce2
MC		 2145 phydev->speed = tp->link_config.speed;
2146 phydev->duplex = tp->link_config.duplex;
2147 phydev->autoneg = tp->link_config.autoneg;
2148 phydev->advertising = tp->link_config.advertising;
b02fd9e3
MC		 2149 }
2150
2151 phy_start(phydev);
2152
2153 phy_start_aneg(phydev);
2154}
2155
2156static void tg3_phy_stop(struct tg3 *tp)
2157{
f07e9af3 2158 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
b02fd9e3
MC		 2159 return;
2160
ead2402c 2161 phy_stop(tp->mdio_bus->phy_map[tp->phy_addr]);
b02fd9e3
MC		 2162}
2163
2164static void tg3_phy_fini(struct tg3 *tp)
2165{
f07e9af3 2166 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
ead2402c 2167 phy_disconnect(tp->mdio_bus->phy_map[tp->phy_addr]);
f07e9af3 2168 tp->phy_flags &= ~TG3_PHYFLG_IS_CONNECTED;
b02fd9e3
MC		 2169 }
2170}
2171
941ec90f
MC		 2172static int tg3_phy_set_extloopbk(struct tg3 *tp)
2173{
2174 int err;
2175 u32 val;
2176
2177 if (tp->phy_flags & TG3_PHYFLG_IS_FET)
2178 return 0;
2179
2180 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
2181 /* Cannot do read-modify-write on 5401 */
2182 err = tg3_phy_auxctl_write(tp,
2183 MII_TG3_AUXCTL_SHDWSEL_AUXCTL,
2184 MII_TG3_AUXCTL_ACTL_EXTLOOPBK |
2185 0x4c20);
2186 goto done;
2187 }
2188
2189 err = tg3_phy_auxctl_read(tp,
2190 MII_TG3_AUXCTL_SHDWSEL_AUXCTL, &val);
2191 if (err)
2192 return err;
2193
2194 val |= MII_TG3_AUXCTL_ACTL_EXTLOOPBK;
2195 err = tg3_phy_auxctl_write(tp,
2196 MII_TG3_AUXCTL_SHDWSEL_AUXCTL, val);
2197
2198done:
2199 return err;
2200}
2201
7f97a4bd
MC		 2202static void tg3_phy_fet_toggle_apd(struct tg3 *tp, bool enable)
2203{
2204 u32 phytest;
2205
2206 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
2207 u32 phy;
2208
2209 tg3_writephy(tp, MII_TG3_FET_TEST,
2210 phytest | MII_TG3_FET_SHADOW_EN);
2211 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXSTAT2, &phy)) {
2212 if (enable)
2213 phy |= MII_TG3_FET_SHDW_AUXSTAT2_APD;
2214 else
2215 phy &= ~MII_TG3_FET_SHDW_AUXSTAT2_APD;
2216 tg3_writephy(tp, MII_TG3_FET_SHDW_AUXSTAT2, phy);
2217 }
2218 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
2219 }
2220}
2221
6833c043
MC		 2222static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable)
2223{
2224 u32 reg;
2225
63c3a66f
JP		 2226 if (!tg3_flag(tp, 5705_PLUS) ||
2227 (tg3_flag(tp, 5717_PLUS) &&
f07e9af3 2228 (tp->phy_flags & TG3_PHYFLG_MII_SERDES)))
6833c043
MC		 2229 return;
2230
f07e9af3 2231 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
7f97a4bd
MC		 2232 tg3_phy_fet_toggle_apd(tp, enable);
2233 return;
2234 }
2235
3ab71071 2236 reg = MII_TG3_MISC_SHDW_SCR5_LPED |
6833c043
MC		 2237 MII_TG3_MISC_SHDW_SCR5_DLPTLM |
2238 MII_TG3_MISC_SHDW_SCR5_SDTL |
2239 MII_TG3_MISC_SHDW_SCR5_C125OE;
4153577a 2240 if (tg3_asic_rev(tp) != ASIC_REV_5784 || !enable)
6833c043
MC		 2241 reg |= MII_TG3_MISC_SHDW_SCR5_DLLAPD;
2242
3ab71071 2243 tg3_phy_shdw_write(tp, MII_TG3_MISC_SHDW_SCR5_SEL, reg);
6833c043
MC		 2244
2245
3ab71071 2246 reg = MII_TG3_MISC_SHDW_APD_WKTM_84MS;
6833c043
MC		 2247 if (enable)
2248 reg |= MII_TG3_MISC_SHDW_APD_ENABLE;
2249
3ab71071 2250 tg3_phy_shdw_write(tp, MII_TG3_MISC_SHDW_APD_SEL, reg);
6833c043
MC		 2251}
2252
953c96e0 2253static void tg3_phy_toggle_automdix(struct tg3 *tp, bool enable)
9ef8ca99
MC		 2254{
2255 u32 phy;
2256
63c3a66f 2257 if (!tg3_flag(tp, 5705_PLUS) ||
f07e9af3 2258 (tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
9ef8ca99
MC		 2259 return;
2260
f07e9af3 2261 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
9ef8ca99
MC		 2262 u32 ephy;
2263
535ef6e1
MC		 2264 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &ephy)) {
2265 u32 reg = MII_TG3_FET_SHDW_MISCCTRL;
2266
2267 tg3_writephy(tp, MII_TG3_FET_TEST,
2268 ephy | MII_TG3_FET_SHADOW_EN);
2269 if (!tg3_readphy(tp, reg, &phy)) {
9ef8ca99 2270 if (enable)
535ef6e1 2271 phy |= MII_TG3_FET_SHDW_MISCCTRL_MDIX;
9ef8ca99 2272 else
535ef6e1
MC		 2273 phy &= ~MII_TG3_FET_SHDW_MISCCTRL_MDIX;
2274 tg3_writephy(tp, reg, phy);
9ef8ca99 2275 }
535ef6e1 2276 tg3_writephy(tp, MII_TG3_FET_TEST, ephy);
9ef8ca99
MC		 2277 }
2278 } else {
15ee95c3
MC		 2279 int ret;
2280
2281 ret = tg3_phy_auxctl_read(tp,
2282 MII_TG3_AUXCTL_SHDWSEL_MISC, &phy);
2283 if (!ret) {
9ef8ca99
MC		 2284 if (enable)
2285 phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
2286 else
2287 phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
b4bd2929
MC		 2288 tg3_phy_auxctl_write(tp,
2289 MII_TG3_AUXCTL_SHDWSEL_MISC, phy);
9ef8ca99
MC		 2290 }
2291 }
2292}
2293
1da177e4
LT		 2294static void tg3_phy_set_wirespeed(struct tg3 *tp)
2295{
15ee95c3 2296 int ret;
1da177e4
LT		 2297 u32 val;
2298
f07e9af3 2299 if (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED)
1da177e4
LT		 2300 return;
2301
15ee95c3
MC		 2302 ret = tg3_phy_auxctl_read(tp, MII_TG3_AUXCTL_SHDWSEL_MISC, &val);
2303 if (!ret)
b4bd2929
MC		 2304 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_MISC,
2305 val | MII_TG3_AUXCTL_MISC_WIRESPD_EN);
1da177e4
LT		 2306}
2307
b2a5c19c
MC		 2308static void tg3_phy_apply_otp(struct tg3 *tp)
2309{
2310 u32 otp, phy;
2311
2312 if (!tp->phy_otp)
2313 return;
2314
2315 otp = tp->phy_otp;
2316
daf3ec68 2317 if (tg3_phy_toggle_auxctl_smdsp(tp, true))
1d36ba45 2318 return;
b2a5c19c
MC		 2319
2320 phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT);
2321 phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT;
2322 tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy);
2323
2324 phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) |
2325 ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT);
2326 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy);
2327
2328 phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT);
2329 phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ;
2330 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy);
2331
2332 phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT);
2333 tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy);
2334
2335 phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT);
2336 tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy);
2337
2338 phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) |
2339 ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT);
2340 tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy);
2341
daf3ec68 2342 tg3_phy_toggle_auxctl_smdsp(tp, false);
b2a5c19c
MC		 2343}
2344
400dfbaa
NS		 2345static void tg3_eee_pull_config(struct tg3 *tp, struct ethtool_eee *eee)
2346{
2347 u32 val;
2348 struct ethtool_eee *dest = &tp->eee;
2349
2350 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP))
2351 return;
2352
2353 if (eee)
2354 dest = eee;
2355
2356 if (tg3_phy_cl45_read(tp, MDIO_MMD_AN, TG3_CL45_D7_EEERES_STAT, &val))
2357 return;
2358
2359 /* Pull eee_active */
2360 if (val == TG3_CL45_D7_EEERES_STAT_LP_1000T ||
2361 val == TG3_CL45_D7_EEERES_STAT_LP_100TX) {
2362 dest->eee_active = 1;
2363 } else
2364 dest->eee_active = 0;
2365
2366 /* Pull lp advertised settings */
2367 if (tg3_phy_cl45_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_LPABLE, &val))
2368 return;
2369 dest->lp_advertised = mmd_eee_adv_to_ethtool_adv_t(val);
2370
2371 /* Pull advertised and eee_enabled settings */
2372 if (tg3_phy_cl45_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, &val))
2373 return;
2374 dest->eee_enabled = !!val;
2375 dest->advertised = mmd_eee_adv_to_ethtool_adv_t(val);
2376
2377 /* Pull tx_lpi_enabled */
2378 val = tr32(TG3_CPMU_EEE_MODE);
2379 dest->tx_lpi_enabled = !!(val & TG3_CPMU_EEEMD_LPI_IN_TX);
2380
2381 /* Pull lpi timer value */
2382 dest->tx_lpi_timer = tr32(TG3_CPMU_EEE_DBTMR1) & 0xffff;
2383}
2384
953c96e0 2385static void tg3_phy_eee_adjust(struct tg3 *tp, bool current_link_up)
52b02d04
MC		 2386{
2387 u32 val;
2388
2389 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP))
2390 return;
2391
2392 tp->setlpicnt = 0;
2393
2394 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
953c96e0 2395 current_link_up &&
a6b68dab
MC		 2396 tp->link_config.active_duplex == DUPLEX_FULL &&
2397 (tp->link_config.active_speed == SPEED_100 ||
2398 tp->link_config.active_speed == SPEED_1000)) {
52b02d04
MC		 2399 u32 eeectl;
2400
2401 if (tp->link_config.active_speed == SPEED_1000)
2402 eeectl = TG3_CPMU_EEE_CTRL_EXIT_16_5_US;
2403 else
2404 eeectl = TG3_CPMU_EEE_CTRL_EXIT_36_US;
2405
2406 tw32(TG3_CPMU_EEE_CTRL, eeectl);
2407
400dfbaa
NS		 2408 tg3_eee_pull_config(tp, NULL);
2409 if (tp->eee.eee_active)
52b02d04
MC		 2410 tp->setlpicnt = 2;
2411 }
2412
2413 if (!tp->setlpicnt) {
953c96e0 2414 if (current_link_up &&
daf3ec68 2415 !tg3_phy_toggle_auxctl_smdsp(tp, true)) {
b715ce94 2416 tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, 0x0000);
daf3ec68 2417 tg3_phy_toggle_auxctl_smdsp(tp, false);
b715ce94
MC		 2418 }
2419
52b02d04
MC		 2420 val = tr32(TG3_CPMU_EEE_MODE);
2421 tw32(TG3_CPMU_EEE_MODE, val & ~TG3_CPMU_EEEMD_LPI_ENABLE);
2422 }
2423}
2424
b0c5943f
MC		 2425static void tg3_phy_eee_enable(struct tg3 *tp)
2426{
2427 u32 val;
2428
2429 if (tp->link_config.active_speed == SPEED_1000 &&
4153577a
JP		 2430 (tg3_asic_rev(tp) == ASIC_REV_5717 ||
2431 tg3_asic_rev(tp) == ASIC_REV_5719 ||
55086ad9 2432 tg3_flag(tp, 57765_CLASS)) &&
daf3ec68 2433 !tg3_phy_toggle_auxctl_smdsp(tp, true)) {
b715ce94
MC		 2434 val = MII_TG3_DSP_TAP26_ALNOKO |
2435 MII_TG3_DSP_TAP26_RMRXSTO;
2436 tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, val);
daf3ec68 2437 tg3_phy_toggle_auxctl_smdsp(tp, false);
b0c5943f
MC		 2438 }
2439
2440 val = tr32(TG3_CPMU_EEE_MODE);
2441 tw32(TG3_CPMU_EEE_MODE, val | TG3_CPMU_EEEMD_LPI_ENABLE);
2442}
2443
1da177e4
LT		 2444static int tg3_wait_macro_done(struct tg3 *tp)
2445{
2446 int limit = 100;
2447
2448 while (limit--) {
2449 u32 tmp32;
2450
f08aa1a8 2451 if (!tg3_readphy(tp, MII_TG3_DSP_CONTROL, &tmp32)) {
1da177e4
LT		 2452 if ((tmp32 & 0x1000) == 0)
2453 break;
2454 }
2455 }
d4675b52 2456 if (limit < 0)
1da177e4
LT		 2457 return -EBUSY;
2458
2459 return 0;
2460}
2461
2462static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
2463{
2464 static const u32 test_pat[4][6] = {
2465 { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
2466 { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
2467 { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
2468 { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
2469 };
2470 int chan;
2471
2472 for (chan = 0; chan < 4; chan++) {
2473 int i;
2474
2475 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
2476 (chan * 0x2000) | 0x0200);
f08aa1a8 2477 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002);
1da177e4
LT		 2478
2479 for (i = 0; i < 6; i++)
2480 tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
2481 test_pat[chan][i]);
2482
f08aa1a8 2483 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202);
1da177e4
LT		 2484 if (tg3_wait_macro_done(tp)) {
2485 *resetp = 1;
2486 return -EBUSY;
2487 }
2488
2489 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
2490 (chan * 0x2000) | 0x0200);
f08aa1a8 2491 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0082);
1da177e4
LT		 2492 if (tg3_wait_macro_done(tp)) {
2493 *resetp = 1;
2494 return -EBUSY;
2495 }
2496
f08aa1a8 2497 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0802);
1da177e4
LT		 2498 if (tg3_wait_macro_done(tp)) {
2499 *resetp = 1;
2500 return -EBUSY;
2501 }
2502
2503 for (i = 0; i < 6; i += 2) {
2504 u32 low, high;
2505
2506 if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
2507 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
2508 tg3_wait_macro_done(tp)) {
2509 *resetp = 1;
2510 return -EBUSY;
2511 }
2512 low &= 0x7fff;
2513 high &= 0x000f;
2514 if (low != test_pat[chan][i] ||
2515 high != test_pat[chan][i+1]) {
2516 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
2517 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
2518 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
2519
2520 return -EBUSY;
2521 }
2522 }
2523 }
2524
2525 return 0;
2526}
2527
2528static int tg3_phy_reset_chanpat(struct tg3 *tp)
2529{
2530 int chan;
2531
2532 for (chan = 0; chan < 4; chan++) {
2533 int i;
2534
2535 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
2536 (chan * 0x2000) | 0x0200);
f08aa1a8 2537 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002);
1da177e4
LT		 2538 for (i = 0; i < 6; i++)
2539 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
f08aa1a8 2540 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202);
1da177e4
LT		 2541 if (tg3_wait_macro_done(tp))
2542 return -EBUSY;
2543 }
2544
2545 return 0;
2546}
2547
2548static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
2549{
2550 u32 reg32, phy9_orig;
2551 int retries, do_phy_reset, err;
2552
2553 retries = 10;
2554 do_phy_reset = 1;
2555 do {
2556 if (do_phy_reset) {
2557 err = tg3_bmcr_reset(tp);
2558 if (err)
2559 return err;
2560 do_phy_reset = 0;
2561 }
2562
2563 /* Disable transmitter and interrupt. */
2564 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
2565 continue;
2566
2567 reg32 |= 0x3000;
2568 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
2569
2570 /* Set full-duplex, 1000 mbps. */
2571 tg3_writephy(tp, MII_BMCR,
221c5637 2572 BMCR_FULLDPLX | BMCR_SPEED1000);
1da177e4
LT		 2573
2574 /* Set to master mode. */
221c5637 2575 if (tg3_readphy(tp, MII_CTRL1000, &phy9_orig))
1da177e4
LT		 2576 continue;
2577
221c5637
MC		 2578 tg3_writephy(tp, MII_CTRL1000,
2579 CTL1000_AS_MASTER | CTL1000_ENABLE_MASTER);
1da177e4 2580
daf3ec68 2581 err = tg3_phy_toggle_auxctl_smdsp(tp, true);
1d36ba45
MC		 2582 if (err)
2583 return err;
1da177e4
LT		 2584
2585 /* Block the PHY control access. */
6ee7c0a0 2586 tg3_phydsp_write(tp, 0x8005, 0x0800);
1da177e4
LT		 2587
2588 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
2589 if (!err)
2590 break;
2591 } while (--retries);
2592
2593 err = tg3_phy_reset_chanpat(tp);
2594 if (err)
2595 return err;
2596
6ee7c0a0 2597 tg3_phydsp_write(tp, 0x8005, 0x0000);
1da177e4
LT		 2598
2599 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
f08aa1a8 2600 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0000);
1da177e4 2601
daf3ec68 2602 tg3_phy_toggle_auxctl_smdsp(tp, false);
1da177e4 2603
221c5637 2604 tg3_writephy(tp, MII_CTRL1000, phy9_orig);
1da177e4 2605
c6e27f2f
DC		 2606 err = tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32);
2607 if (err)
2608 return err;
1da177e4 2609
c6e27f2f
DC		 2610 reg32 &= ~0x3000;
2611 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
2612
2613 return 0;
1da177e4
LT		 2614}
2615
f4a46d1f
NNS		 2616static void tg3_carrier_off(struct tg3 *tp)
2617{
2618 netif_carrier_off(tp->dev);
2619 tp->link_up = false;
2620}
2621
ce20f161
NS		 2622static void tg3_warn_mgmt_link_flap(struct tg3 *tp)
2623{
2624 if (tg3_flag(tp, ENABLE_ASF))
2625 netdev_warn(tp->dev,
2626 "Management side-band traffic will be interrupted during phy settings change\n");
2627}
2628
1da177e4
LT		 2629/* This will reset the tigon3 PHY if there is no valid
2630 * link unless the FORCE argument is non-zero.
2631 */
2632static int tg3_phy_reset(struct tg3 *tp)
2633{
f833c4c1 2634 u32 val, cpmuctrl;
1da177e4
LT		 2635 int err;
2636
4153577a 2637 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
60189ddf
MC		 2638 val = tr32(GRC_MISC_CFG);
2639 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
2640 udelay(40);
2641 }
f833c4c1
MC		 2642 err = tg3_readphy(tp, MII_BMSR, &val);
2643 err |= tg3_readphy(tp, MII_BMSR, &val);
1da177e4
LT		 2644 if (err != 0)
2645 return -EBUSY;
2646
f4a46d1f 2647 if (netif_running(tp->dev) && tp->link_up) {
84421b99 2648 netif_carrier_off(tp->dev);
c8e1e82b
MC		 2649 tg3_link_report(tp);
2650 }
2651
4153577a
JP		 2652 if (tg3_asic_rev(tp) == ASIC_REV_5703 ||
2653 tg3_asic_rev(tp) == ASIC_REV_5704 ||
2654 tg3_asic_rev(tp) == ASIC_REV_5705) {
1da177e4
LT		 2655 err = tg3_phy_reset_5703_4_5(tp);
2656 if (err)
2657 return err;
2658 goto out;
2659 }
2660
b2a5c19c 2661 cpmuctrl = 0;
4153577a
JP		 2662 if (tg3_asic_rev(tp) == ASIC_REV_5784 &&
2663 tg3_chip_rev(tp) != CHIPREV_5784_AX) {
b2a5c19c
MC		 2664 cpmuctrl = tr32(TG3_CPMU_CTRL);
2665 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY)
2666 tw32(TG3_CPMU_CTRL,
2667 cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY);
2668 }
2669
1da177e4
LT		 2670 err = tg3_bmcr_reset(tp);
2671 if (err)
2672 return err;
2673
b2a5c19c 2674 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) {
f833c4c1
MC		 2675 val = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz;
2676 tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, val);
b2a5c19c
MC		 2677
2678 tw32(TG3_CPMU_CTRL, cpmuctrl);
2679 }
2680
4153577a
JP		 2681 if (tg3_chip_rev(tp) == CHIPREV_5784_AX ||
2682 tg3_chip_rev(tp) == CHIPREV_5761_AX) {
ce057f01
MC		 2683 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2684 if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) ==
2685 CPMU_LSPD_1000MB_MACCLK_12_5) {
2686 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2687 udelay(40);
2688 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2689 }
2690 }
2691
63c3a66f 2692 if (tg3_flag(tp, 5717_PLUS) &&
f07e9af3 2693 (tp->phy_flags & TG3_PHYFLG_MII_SERDES))
ecf1410b
MC		 2694 return 0;
2695
b2a5c19c
MC		 2696 tg3_phy_apply_otp(tp);
2697
f07e9af3 2698 if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD)
6833c043
MC		 2699 tg3_phy_toggle_apd(tp, true);
2700 else
2701 tg3_phy_toggle_apd(tp, false);
2702
1da177e4 2703out:
1d36ba45 2704 if ((tp->phy_flags & TG3_PHYFLG_ADC_BUG) &&
daf3ec68 2705 !tg3_phy_toggle_auxctl_smdsp(tp, true)) {
6ee7c0a0
MC		 2706 tg3_phydsp_write(tp, 0x201f, 0x2aaa);
2707 tg3_phydsp_write(tp, 0x000a, 0x0323);
daf3ec68 2708 tg3_phy_toggle_auxctl_smdsp(tp, false);
1da177e4 2709 }
1d36ba45 2710
f07e9af3 2711 if (tp->phy_flags & TG3_PHYFLG_5704_A0_BUG) {
f08aa1a8
MC		 2712 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
2713 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
1da177e4 2714 }
1d36ba45 2715
f07e9af3 2716 if (tp->phy_flags & TG3_PHYFLG_BER_BUG) {
daf3ec68 2717 if (!tg3_phy_toggle_auxctl_smdsp(tp, true)) {
1d36ba45
MC		 2718 tg3_phydsp_write(tp, 0x000a, 0x310b);
2719 tg3_phydsp_write(tp, 0x201f, 0x9506);
2720 tg3_phydsp_write(tp, 0x401f, 0x14e2);
daf3ec68 2721 tg3_phy_toggle_auxctl_smdsp(tp, false);
1d36ba45 2722 }
f07e9af3 2723 } else if (tp->phy_flags & TG3_PHYFLG_JITTER_BUG) {
daf3ec68 2724 if (!tg3_phy_toggle_auxctl_smdsp(tp, true)) {
1d36ba45
MC		 2725 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
2726 if (tp->phy_flags & TG3_PHYFLG_ADJUST_TRIM) {
2727 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
2728 tg3_writephy(tp, MII_TG3_TEST1,
2729 MII_TG3_TEST1_TRIM_EN | 0x4);
2730 } else
2731 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
2732
daf3ec68 2733 tg3_phy_toggle_auxctl_smdsp(tp, false);
1d36ba45 2734 }
c424cb24 2735 }
1d36ba45 2736
1da177e4
LT		 2737 /* Set Extended packet length bit (bit 14) on all chips that */
2738 /* support jumbo frames */
79eb6904 2739 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
1da177e4 2740 /* Cannot do read-modify-write on 5401 */
b4bd2929 2741 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, 0x4c20);
63c3a66f 2742 } else if (tg3_flag(tp, JUMBO_CAPABLE)) {
1da177e4 2743 /* Set bit 14 with read-modify-write to preserve other bits */
15ee95c3
MC		 2744 err = tg3_phy_auxctl_read(tp,
2745 MII_TG3_AUXCTL_SHDWSEL_AUXCTL, &val);
2746 if (!err)
b4bd2929
MC		 2747 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL,
2748 val | MII_TG3_AUXCTL_ACTL_EXTPKTLEN);
1da177e4
LT		 2749 }
2750
2751 /* Set phy register 0x10 bit 0 to high fifo elasticity to support
2752 * jumbo frames transmission.
2753 */
63c3a66f 2754 if (tg3_flag(tp, JUMBO_CAPABLE)) {
f833c4c1 2755 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &val))
c6cdf436 2756 tg3_writephy(tp, MII_TG3_EXT_CTRL,
f833c4c1 2757 val | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
1da177e4
LT		 2758 }
2759
4153577a 2760 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
715116a1 2761 /* adjust output voltage */
535ef6e1 2762 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x12);
715116a1
MC		 2763 }
2764
4153577a 2765 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5762_A0)
c65a17f4
MC		 2766 tg3_phydsp_write(tp, 0xffb, 0x4000);
2767
953c96e0 2768 tg3_phy_toggle_automdix(tp, true);
1da177e4
LT		 2769 tg3_phy_set_wirespeed(tp);
2770 return 0;
2771}
2772
3a1e19d3
MC		 2773#define TG3_GPIO_MSG_DRVR_PRES 0x00000001
2774#define TG3_GPIO_MSG_NEED_VAUX 0x00000002
2775#define TG3_GPIO_MSG_MASK (TG3_GPIO_MSG_DRVR_PRES | \
2776 TG3_GPIO_MSG_NEED_VAUX)
2777#define TG3_GPIO_MSG_ALL_DRVR_PRES_MASK \
2778 ((TG3_GPIO_MSG_DRVR_PRES << 0) | \
2779 (TG3_GPIO_MSG_DRVR_PRES << 4) | \
2780 (TG3_GPIO_MSG_DRVR_PRES << 8) | \
2781 (TG3_GPIO_MSG_DRVR_PRES << 12))
2782
2783#define TG3_GPIO_MSG_ALL_NEED_VAUX_MASK \
2784 ((TG3_GPIO_MSG_NEED_VAUX << 0) | \
2785 (TG3_GPIO_MSG_NEED_VAUX << 4) | \
2786 (TG3_GPIO_MSG_NEED_VAUX << 8) | \
2787 (TG3_GPIO_MSG_NEED_VAUX << 12))
2788
2789static inline u32 tg3_set_function_status(struct tg3 *tp, u32 newstat)
2790{
2791 u32 status, shift;
2792
4153577a
JP		 2793 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
2794 tg3_asic_rev(tp) == ASIC_REV_5719)
3a1e19d3
MC		 2795 status = tg3_ape_read32(tp, TG3_APE_GPIO_MSG);
2796 else
2797 status = tr32(TG3_CPMU_DRV_STATUS);
2798
2799 shift = TG3_APE_GPIO_MSG_SHIFT + 4 * tp->pci_fn;
2800 status &= ~(TG3_GPIO_MSG_MASK << shift);
2801 status |= (newstat << shift);
2802
4153577a
JP		 2803 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
2804 tg3_asic_rev(tp) == ASIC_REV_5719)
3a1e19d3
MC		 2805 tg3_ape_write32(tp, TG3_APE_GPIO_MSG, status);
2806 else
2807 tw32(TG3_CPMU_DRV_STATUS, status);
2808
2809 return status >> TG3_APE_GPIO_MSG_SHIFT;
2810}
2811
520b2756
MC		 2812static inline int tg3_pwrsrc_switch_to_vmain(struct tg3 *tp)
2813{
2814 if (!tg3_flag(tp, IS_NIC))
2815 return 0;
2816
4153577a
JP		 2817 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
2818 tg3_asic_rev(tp) == ASIC_REV_5719 ||
2819 tg3_asic_rev(tp) == ASIC_REV_5720) {
3a1e19d3
MC		 2820 if (tg3_ape_lock(tp, TG3_APE_LOCK_GPIO))
2821 return -EIO;
520b2756 2822
3a1e19d3
MC		 2823 tg3_set_function_status(tp, TG3_GPIO_MSG_DRVR_PRES);
2824
2825 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl,
2826 TG3_GRC_LCLCTL_PWRSW_DELAY);
2827
2828 tg3_ape_unlock(tp, TG3_APE_LOCK_GPIO);
2829 } else {
2830 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl,
2831 TG3_GRC_LCLCTL_PWRSW_DELAY);
2832 }
6f5c8f83 2833
520b2756
MC		 2834 return 0;
2835}
2836
2837static void tg3_pwrsrc_die_with_vmain(struct tg3 *tp)
2838{
2839 u32 grc_local_ctrl;
2840
2841 if (!tg3_flag(tp, IS_NIC) ||
4153577a
JP		 2842 tg3_asic_rev(tp) == ASIC_REV_5700 ||
2843 tg3_asic_rev(tp) == ASIC_REV_5701)
520b2756
MC		 2844 return;
2845
2846 grc_local_ctrl = tp->grc_local_ctrl | GRC_LCLCTRL_GPIO_OE1;
2847
2848 tw32_wait_f(GRC_LOCAL_CTRL,
2849 grc_local_ctrl | GRC_LCLCTRL_GPIO_OUTPUT1,
2850 TG3_GRC_LCLCTL_PWRSW_DELAY);
2851
2852 tw32_wait_f(GRC_LOCAL_CTRL,
2853 grc_local_ctrl,
2854 TG3_GRC_LCLCTL_PWRSW_DELAY);
2855
2856 tw32_wait_f(GRC_LOCAL_CTRL,
2857 grc_local_ctrl | GRC_LCLCTRL_GPIO_OUTPUT1,
2858 TG3_GRC_LCLCTL_PWRSW_DELAY);
2859}
2860
2861static void tg3_pwrsrc_switch_to_vaux(struct tg3 *tp)
2862{
2863 if (!tg3_flag(tp, IS_NIC))
2864 return;
2865
4153577a
JP		 2866 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
2867 tg3_asic_rev(tp) == ASIC_REV_5701) {
520b2756
MC		 2868 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2869 (GRC_LCLCTRL_GPIO_OE0 |
2870 GRC_LCLCTRL_GPIO_OE1 |
2871 GRC_LCLCTRL_GPIO_OE2 |
2872 GRC_LCLCTRL_GPIO_OUTPUT0 |
2873 GRC_LCLCTRL_GPIO_OUTPUT1),
2874 TG3_GRC_LCLCTL_PWRSW_DELAY);
2875 } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
2876 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
2877 /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */
2878 u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
2879 GRC_LCLCTRL_GPIO_OE1 |
2880 GRC_LCLCTRL_GPIO_OE2 |
2881 GRC_LCLCTRL_GPIO_OUTPUT0 |
2882 GRC_LCLCTRL_GPIO_OUTPUT1 |
2883 tp->grc_local_ctrl;
2884 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl,
2885 TG3_GRC_LCLCTL_PWRSW_DELAY);
2886
2887 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2;
2888 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl,
2889 TG3_GRC_LCLCTL_PWRSW_DELAY);
2890
2891 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0;
2892 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl,
2893 TG3_GRC_LCLCTL_PWRSW_DELAY);
2894 } else {
2895 u32 no_gpio2;
2896 u32 grc_local_ctrl = 0;
2897
2898 /* Workaround to prevent overdrawing Amps. */
4153577a 2899 if (tg3_asic_rev(tp) == ASIC_REV_5714) {
520b2756
MC		 2900 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
2901 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2902 grc_local_ctrl,
2903 TG3_GRC_LCLCTL_PWRSW_DELAY);
2904 }
2905
2906 /* On 5753 and variants, GPIO2 cannot be used. */
2907 no_gpio2 = tp->nic_sram_data_cfg &
2908 NIC_SRAM_DATA_CFG_NO_GPIO2;
2909
2910 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
2911 GRC_LCLCTRL_GPIO_OE1 |
2912 GRC_LCLCTRL_GPIO_OE2 |
2913 GRC_LCLCTRL_GPIO_OUTPUT1 |
2914 GRC_LCLCTRL_GPIO_OUTPUT2;
2915 if (no_gpio2) {
2916 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
2917 GRC_LCLCTRL_GPIO_OUTPUT2);
2918 }
2919 tw32_wait_f(GRC_LOCAL_CTRL,
2920 tp->grc_local_ctrl | grc_local_ctrl,
2921 TG3_GRC_LCLCTL_PWRSW_DELAY);
2922
2923 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
2924
2925 tw32_wait_f(GRC_LOCAL_CTRL,
2926 tp->grc_local_ctrl | grc_local_ctrl,
2927 TG3_GRC_LCLCTL_PWRSW_DELAY);
2928
2929 if (!no_gpio2) {
2930 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
2931 tw32_wait_f(GRC_LOCAL_CTRL,
2932 tp->grc_local_ctrl | grc_local_ctrl,
2933 TG3_GRC_LCLCTL_PWRSW_DELAY);
2934 }
2935 }
3a1e19d3
MC		 2936}
2937
cd0d7228 2938static void tg3_frob_aux_power_5717(struct tg3 *tp, bool wol_enable)
3a1e19d3
MC		 2939{
2940 u32 msg = 0;
2941
2942 /* Serialize power state transitions */
2943 if (tg3_ape_lock(tp, TG3_APE_LOCK_GPIO))
2944 return;
2945
cd0d7228 2946 if (tg3_flag(tp, ENABLE_ASF) || tg3_flag(tp, ENABLE_APE) || wol_enable)
3a1e19d3
MC		 2947 msg = TG3_GPIO_MSG_NEED_VAUX;
2948
2949 msg = tg3_set_function_status(tp, msg);
2950
2951 if (msg & TG3_GPIO_MSG_ALL_DRVR_PRES_MASK)
2952 goto done;
6f5c8f83 2953
3a1e19d3
MC		 2954 if (msg & TG3_GPIO_MSG_ALL_NEED_VAUX_MASK)
2955 tg3_pwrsrc_switch_to_vaux(tp);
2956 else
2957 tg3_pwrsrc_die_with_vmain(tp);
2958
2959done:
6f5c8f83 2960 tg3_ape_unlock(tp, TG3_APE_LOCK_GPIO);
520b2756
MC		 2961}
2962
cd0d7228 2963static void tg3_frob_aux_power(struct tg3 *tp, bool include_wol)
1da177e4 2964{
683644b7 2965 bool need_vaux = false;
1da177e4 2966
334355aa 2967 /* The GPIOs do something completely different on 57765. */
55086ad9 2968 if (!tg3_flag(tp, IS_NIC) || tg3_flag(tp, 57765_CLASS))
1da177e4
LT		 2969 return;
2970
4153577a
JP		 2971 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
2972 tg3_asic_rev(tp) == ASIC_REV_5719 ||
2973 tg3_asic_rev(tp) == ASIC_REV_5720) {
cd0d7228
MC		 2974 tg3_frob_aux_power_5717(tp, include_wol ?
2975 tg3_flag(tp, WOL_ENABLE) != 0 : 0);
3a1e19d3
MC		 2976 return;
2977 }
2978
2979 if (tp->pdev_peer && tp->pdev_peer != tp->pdev) {
8c2dc7e1
MC		 2980 struct net_device *dev_peer;
2981
2982 dev_peer = pci_get_drvdata(tp->pdev_peer);
683644b7 2983
bc1c7567 2984 /* remove_one() may have been run on the peer. */
683644b7
MC		 2985 if (dev_peer) {
2986 struct tg3 *tp_peer = netdev_priv(dev_peer);
2987
63c3a66f 2988 if (tg3_flag(tp_peer, INIT_COMPLETE))
683644b7
MC		 2989 return;
2990
cd0d7228 2991 if ((include_wol && tg3_flag(tp_peer, WOL_ENABLE)) ||
63c3a66f 2992 tg3_flag(tp_peer, ENABLE_ASF))
683644b7
MC		 2993 need_vaux = true;
2994 }
1da177e4
LT		 2995 }
2996
cd0d7228
MC		 2997 if ((include_wol && tg3_flag(tp, WOL_ENABLE)) ||
2998 tg3_flag(tp, ENABLE_ASF))
683644b7
MC		 2999 need_vaux = true;
3000
520b2756
MC		 3001 if (need_vaux)
3002 tg3_pwrsrc_switch_to_vaux(tp);
3003 else
3004 tg3_pwrsrc_die_with_vmain(tp);
1da177e4
LT		 3005}
3006
e8f3f6ca
MC		 3007static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
3008{
3009 if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
3010 return 1;
79eb6904 3011 else if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411) {
e8f3f6ca
MC		 3012 if (speed != SPEED_10)
3013 return 1;
3014 } else if (speed == SPEED_10)
3015 return 1;
3016
3017 return 0;
3018}
3019
44f3b503
NS		 3020static bool tg3_phy_power_bug(struct tg3 *tp)
3021{
3022 switch (tg3_asic_rev(tp)) {
3023 case ASIC_REV_5700:
3024 case ASIC_REV_5704:
3025 return true;
3026 case ASIC_REV_5780:
3027 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
3028 return true;
3029 return false;
3030 case ASIC_REV_5717:
3031 if (!tp->pci_fn)
3032 return true;
3033 return false;
3034 case ASIC_REV_5719:
3035 case ASIC_REV_5720:
3036 if ((tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
3037 !tp->pci_fn)
3038 return true;
3039 return false;
3040 }
3041
3042 return false;
3043}
3044
989038e2
NS		 3045static bool tg3_phy_led_bug(struct tg3 *tp)
3046{
3047 switch (tg3_asic_rev(tp)) {
3048 case ASIC_REV_5719:
300cf9b9 3049 case ASIC_REV_5720:
989038e2
NS		 3050 if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
3051 !tp->pci_fn)
3052 return true;
3053 return false;
3054 }
3055
3056 return false;
3057}
3058
0a459aac 3059static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power)
15c3b696 3060{
ce057f01
MC		 3061 u32 val;
3062
942d1af0
NS		 3063 if (tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN)
3064 return;
3065
f07e9af3 3066 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
4153577a 3067 if (tg3_asic_rev(tp) == ASIC_REV_5704) {
5129724a
MC		 3068 u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
3069 u32 serdes_cfg = tr32(MAC_SERDES_CFG);
3070
3071 sg_dig_ctrl |=
3072 SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
3073 tw32(SG_DIG_CTRL, sg_dig_ctrl);
3074 tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
3075 }
3f7045c1 3076 return;
5129724a 3077 }
3f7045c1 3078
4153577a 3079 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
60189ddf
MC		 3080 tg3_bmcr_reset(tp);
3081 val = tr32(GRC_MISC_CFG);
3082 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
3083 udelay(40);
3084 return;
f07e9af3 3085 } else if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
0e5f784c
MC		 3086 u32 phytest;
3087 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
3088 u32 phy;
3089
3090 tg3_writephy(tp, MII_ADVERTISE, 0);
3091 tg3_writephy(tp, MII_BMCR,
3092 BMCR_ANENABLE | BMCR_ANRESTART);
3093
3094 tg3_writephy(tp, MII_TG3_FET_TEST,
3095 phytest | MII_TG3_FET_SHADOW_EN);
3096 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXMODE4, &phy)) {
3097 phy |= MII_TG3_FET_SHDW_AUXMODE4_SBPD;
3098 tg3_writephy(tp,
3099 MII_TG3_FET_SHDW_AUXMODE4,
3100 phy);
3101 }
3102 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
3103 }
3104 return;
0a459aac 3105 } else if (do_low_power) {
989038e2
NS		 3106 if (!tg3_phy_led_bug(tp))
3107 tg3_writephy(tp, MII_TG3_EXT_CTRL,
3108 MII_TG3_EXT_CTRL_FORCE_LED_OFF);
0a459aac 3109
b4bd2929
MC		 3110 val = MII_TG3_AUXCTL_PCTL_100TX_LPWR |
3111 MII_TG3_AUXCTL_PCTL_SPR_ISOLATE |
3112 MII_TG3_AUXCTL_PCTL_VREG_11V;
3113 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_PWRCTL, val);
715116a1 3114 }
3f7045c1 3115
15c3b696
MC		 3116 /* The PHY should not be powered down on some chips because
3117 * of bugs.
3118 */
44f3b503 3119 if (tg3_phy_power_bug(tp))
15c3b696 3120 return;
ce057f01 3121
4153577a
JP		 3122 if (tg3_chip_rev(tp) == CHIPREV_5784_AX ||
3123 tg3_chip_rev(tp) == CHIPREV_5761_AX) {
ce057f01
MC		 3124 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
3125 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
3126 val |= CPMU_LSPD_1000MB_MACCLK_12_5;
3127 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
3128 }
3129
15c3b696
MC		 3130 tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
3131}
3132
ffbcfed4
MC		 3133/* tp->lock is held. */
3134static int tg3_nvram_lock(struct tg3 *tp)
3135{
63c3a66f 3136 if (tg3_flag(tp, NVRAM)) {
ffbcfed4
MC		 3137 int i;
3138
3139 if (tp->nvram_lock_cnt == 0) {
3140 tw32(NVRAM_SWARB, SWARB_REQ_SET1);
3141 for (i = 0; i < 8000; i++) {
3142 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
3143 break;
3144 udelay(20);
3145 }
3146 if (i == 8000) {
3147 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
3148 return -ENODEV;
3149 }
3150 }
3151 tp->nvram_lock_cnt++;
3152 }
3153 return 0;
3154}
3155
3156/* tp->lock is held. */
3157static void tg3_nvram_unlock(struct tg3 *tp)
3158{
63c3a66f 3159 if (tg3_flag(tp, NVRAM)) {
ffbcfed4
MC		 3160 if (tp->nvram_lock_cnt > 0)
3161 tp->nvram_lock_cnt--;
3162 if (tp->nvram_lock_cnt == 0)
3163 tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
3164 }
3165}
3166
3167/* tp->lock is held. */
3168static void tg3_enable_nvram_access(struct tg3 *tp)
3169{
63c3a66f 3170 if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM)) {
ffbcfed4
MC		 3171 u32 nvaccess = tr32(NVRAM_ACCESS);
3172
3173 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
3174 }
3175}
3176
3177/* tp->lock is held. */
3178static void tg3_disable_nvram_access(struct tg3 *tp)
3179{
63c3a66f 3180 if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM)) {
ffbcfed4
MC		 3181 u32 nvaccess = tr32(NVRAM_ACCESS);
3182
3183 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
3184 }
3185}
3186
3187static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
3188 u32 offset, u32 *val)
3189{
3190 u32 tmp;
3191 int i;
3192
3193 if (offset > EEPROM_ADDR_ADDR_MASK || (offset % 4) != 0)
3194 return -EINVAL;
3195
3196 tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
3197 EEPROM_ADDR_DEVID_MASK |
3198 EEPROM_ADDR_READ);
3199 tw32(GRC_EEPROM_ADDR,
3200 tmp |
3201 (0 << EEPROM_ADDR_DEVID_SHIFT) |
3202 ((offset << EEPROM_ADDR_ADDR_SHIFT) &
3203 EEPROM_ADDR_ADDR_MASK) |
3204 EEPROM_ADDR_READ | EEPROM_ADDR_START);
3205
3206 for (i = 0; i < 1000; i++) {
3207 tmp = tr32(GRC_EEPROM_ADDR);
3208
3209 if (tmp & EEPROM_ADDR_COMPLETE)
3210 break;
3211 msleep(1);
3212 }
3213 if (!(tmp & EEPROM_ADDR_COMPLETE))
3214 return -EBUSY;
3215
62cedd11
MC		 3216 tmp = tr32(GRC_EEPROM_DATA);
3217
3218 /*
3219 * The data will always be opposite the native endian
3220 * format. Perform a blind byteswap to compensate.
3221 */
3222 *val = swab32(tmp);
3223
ffbcfed4
MC		 3224 return 0;
3225}
3226
66c965f5 3227#define NVRAM_CMD_TIMEOUT 5000
ffbcfed4
MC		 3228
3229static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
3230{
3231 int i;
3232
3233 tw32(NVRAM_CMD, nvram_cmd);
3234 for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
66c965f5 3235 usleep_range(10, 40);
ffbcfed4
MC		 3236 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
3237 udelay(10);
3238 break;
3239 }
3240 }
3241
3242 if (i == NVRAM_CMD_TIMEOUT)
3243 return -EBUSY;
3244
3245 return 0;
3246}
3247
3248static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
3249{
63c3a66f
JP		 3250 if (tg3_flag(tp, NVRAM) &&
3251 tg3_flag(tp, NVRAM_BUFFERED) &&
3252 tg3_flag(tp, FLASH) &&
3253 !tg3_flag(tp, NO_NVRAM_ADDR_TRANS) &&
ffbcfed4
MC		 3254 (tp->nvram_jedecnum == JEDEC_ATMEL))
3255
3256 addr = ((addr / tp->nvram_pagesize) <<
3257 ATMEL_AT45DB0X1B_PAGE_POS) +
3258 (addr % tp->nvram_pagesize);
3259
3260 return addr;
3261}
3262
3263static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
3264{
63c3a66f
JP		 3265 if (tg3_flag(tp, NVRAM) &&
3266 tg3_flag(tp, NVRAM_BUFFERED) &&
3267 tg3_flag(tp, FLASH) &&
3268 !tg3_flag(tp, NO_NVRAM_ADDR_TRANS) &&
ffbcfed4
MC		 3269 (tp->nvram_jedecnum == JEDEC_ATMEL))
3270
3271 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
3272 tp->nvram_pagesize) +
3273 (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
3274
3275 return addr;
3276}
3277
e4f34110
MC		 3278/* NOTE: Data read in from NVRAM is byteswapped according to
3279 * the byteswapping settings for all other register accesses.
3280 * tg3 devices are BE devices, so on a BE machine, the data
3281 * returned will be exactly as it is seen in NVRAM. On a LE
3282 * machine, the 32-bit value will be byteswapped.
3283 */
ffbcfed4
MC		 3284static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
3285{
3286 int ret;
3287
63c3a66f 3288 if (!tg3_flag(tp, NVRAM))
ffbcfed4
MC		 3289 return tg3_nvram_read_using_eeprom(tp, offset, val);
3290
3291 offset = tg3_nvram_phys_addr(tp, offset);
3292
3293 if (offset > NVRAM_ADDR_MSK)
3294 return -EINVAL;
3295
3296 ret = tg3_nvram_lock(tp);
3297 if (ret)
3298 return ret;
3299
3300 tg3_enable_nvram_access(tp);
3301
3302 tw32(NVRAM_ADDR, offset);
3303 ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
3304 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
3305
3306 if (ret == 0)
e4f34110 3307 *val = tr32(NVRAM_RDDATA);
ffbcfed4
MC		 3308
3309 tg3_disable_nvram_access(tp);
3310
3311 tg3_nvram_unlock(tp);
3312
3313 return ret;
3314}
3315
a9dc529d
MC		 3316/* Ensures NVRAM data is in bytestream format. */
3317static int tg3_nvram_read_be32(struct tg3 *tp, u32 offset, __be32 *val)
ffbcfed4
MC		 3318{
3319 u32 v;
a9dc529d 3320 int res = tg3_nvram_read(tp, offset, &v);
ffbcfed4 3321 if (!res)
a9dc529d 3322 *val = cpu_to_be32(v);
ffbcfed4
MC		 3323 return res;
3324}
3325
dbe9b92a
MC		 3326static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
3327 u32 offset, u32 len, u8 *buf)
3328{
3329 int i, j, rc = 0;
3330 u32 val;
3331
3332 for (i = 0; i < len; i += 4) {
3333 u32 addr;
3334 __be32 data;
3335
3336 addr = offset + i;
3337
3338 memcpy(&data, buf + i, 4);
3339
3340 /*
3341 * The SEEPROM interface expects the data to always be opposite
3342 * the native endian format. We accomplish this by reversing
3343 * all the operations that would have been performed on the
3344 * data from a call to tg3_nvram_read_be32().
3345 */
3346 tw32(GRC_EEPROM_DATA, swab32(be32_to_cpu(data)));
3347
3348 val = tr32(GRC_EEPROM_ADDR);
3349 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
3350
3351 val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
3352 EEPROM_ADDR_READ);
3353 tw32(GRC_EEPROM_ADDR, val |
3354 (0 << EEPROM_ADDR_DEVID_SHIFT) |
3355 (addr & EEPROM_ADDR_ADDR_MASK) |
3356 EEPROM_ADDR_START |
3357 EEPROM_ADDR_WRITE);
3358
3359 for (j = 0; j < 1000; j++) {
3360 val = tr32(GRC_EEPROM_ADDR);
3361
3362 if (val & EEPROM_ADDR_COMPLETE)
3363 break;
3364 msleep(1);
3365 }
3366 if (!(val & EEPROM_ADDR_COMPLETE)) {
3367 rc = -EBUSY;
3368 break;
3369 }
3370 }
3371
3372 return rc;
3373}
3374
3375/* offset and length are dword aligned */
3376static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
3377 u8 *buf)
3378{
3379 int ret = 0;
3380 u32 pagesize = tp->nvram_pagesize;
3381 u32 pagemask = pagesize - 1;
3382 u32 nvram_cmd;
3383 u8 *tmp;
3384
3385 tmp = kmalloc(pagesize, GFP_KERNEL);
3386 if (tmp == NULL)
3387 return -ENOMEM;
3388
3389 while (len) {
3390 int j;
3391 u32 phy_addr, page_off, size;
3392
3393 phy_addr = offset & ~pagemask;
3394
3395 for (j = 0; j < pagesize; j += 4) {
3396 ret = tg3_nvram_read_be32(tp, phy_addr + j,
3397 (__be32 *) (tmp + j));
3398 if (ret)
3399 break;
3400 }
3401 if (ret)
3402 break;
3403
3404 page_off = offset & pagemask;
3405 size = pagesize;
3406 if (len < size)
3407 size = len;
3408
3409 len -= size;
3410
3411 memcpy(tmp + page_off, buf, size);
3412
3413 offset = offset + (pagesize - page_off);
3414
3415 tg3_enable_nvram_access(tp);
3416
3417 /*
3418 * Before we can erase the flash page, we need
3419 * to issue a special "write enable" command.
3420 */
3421 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
3422
3423 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
3424 break;
3425
3426 /* Erase the target page */
3427 tw32(NVRAM_ADDR, phy_addr);
3428
3429 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
3430 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
3431
3432 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
3433 break;
3434
3435 /* Issue another write enable to start the write. */
3436 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
3437
3438 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
3439 break;
3440
3441 for (j = 0; j < pagesize; j += 4) {
3442 __be32 data;
3443
3444 data = *((__be32 *) (tmp + j));
3445
3446 tw32(NVRAM_WRDATA, be32_to_cpu(data));
3447
3448 tw32(NVRAM_ADDR, phy_addr + j);
3449
3450 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
3451 NVRAM_CMD_WR;
3452
3453 if (j == 0)
3454 nvram_cmd |= NVRAM_CMD_FIRST;
3455 else if (j == (pagesize - 4))
3456 nvram_cmd |= NVRAM_CMD_LAST;
3457
3458 ret = tg3_nvram_exec_cmd(tp, nvram_cmd);
3459 if (ret)
3460 break;
3461 }
3462 if (ret)
3463 break;
3464 }
3465
3466 nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
3467 tg3_nvram_exec_cmd(tp, nvram_cmd);
3468
3469 kfree(tmp);
3470
3471 return ret;
3472}
3473
3474/* offset and length are dword aligned */
3475static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
3476 u8 *buf)
3477{
3478 int i, ret = 0;
3479
3480 for (i = 0; i < len; i += 4, offset += 4) {
3481 u32 page_off, phy_addr, nvram_cmd;
3482 __be32 data;
3483
3484 memcpy(&data, buf + i, 4);
3485 tw32(NVRAM_WRDATA, be32_to_cpu(data));
3486
3487 page_off = offset % tp->nvram_pagesize;
3488
3489 phy_addr = tg3_nvram_phys_addr(tp, offset);
3490
dbe9b92a
MC		 3491 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
3492
3493 if (page_off == 0 || i == 0)
3494 nvram_cmd |= NVRAM_CMD_FIRST;
3495 if (page_off == (tp->nvram_pagesize - 4))
3496 nvram_cmd |= NVRAM_CMD_LAST;
3497
3498 if (i == (len - 4))
3499 nvram_cmd |= NVRAM_CMD_LAST;
3500
42278224
MC		 3501 if ((nvram_cmd & NVRAM_CMD_FIRST) ||
3502 !tg3_flag(tp, FLASH) ||
3503 !tg3_flag(tp, 57765_PLUS))
3504 tw32(NVRAM_ADDR, phy_addr);
3505
4153577a 3506 if (tg3_asic_rev(tp) != ASIC_REV_5752 &&
dbe9b92a
MC		 3507 !tg3_flag(tp, 5755_PLUS) &&
3508 (tp->nvram_jedecnum == JEDEC_ST) &&
3509 (nvram_cmd & NVRAM_CMD_FIRST)) {
3510 u32 cmd;
3511
3512 cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
3513 ret = tg3_nvram_exec_cmd(tp, cmd);
3514 if (ret)
3515 break;
3516 }
3517 if (!tg3_flag(tp, FLASH)) {
3518 /* We always do complete word writes to eeprom. */
3519 nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
3520 }
3521
3522 ret = tg3_nvram_exec_cmd(tp, nvram_cmd);
3523 if (ret)
3524 break;
3525 }
3526 return ret;
3527}
3528
3529/* offset and length are dword aligned */
3530static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
3531{
3532 int ret;
3533
3534 if (tg3_flag(tp, EEPROM_WRITE_PROT)) {
3535 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
3536 ~GRC_LCLCTRL_GPIO_OUTPUT1);
3537 udelay(40);
3538 }
3539
3540 if (!tg3_flag(tp, NVRAM)) {
3541 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
3542 } else {
3543 u32 grc_mode;
3544
3545 ret = tg3_nvram_lock(tp);
3546 if (ret)
3547 return ret;
3548
3549 tg3_enable_nvram_access(tp);
3550 if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM))
3551 tw32(NVRAM_WRITE1, 0x406);
3552
3553 grc_mode = tr32(GRC_MODE);
3554 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
3555
3556 if (tg3_flag(tp, NVRAM_BUFFERED) || !tg3_flag(tp, FLASH)) {
3557 ret = tg3_nvram_write_block_buffered(tp, offset, len,
3558 buf);
3559 } else {
3560 ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
3561 buf);
3562 }
3563
3564 grc_mode = tr32(GRC_MODE);
3565 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
3566
3567 tg3_disable_nvram_access(tp);
3568 tg3_nvram_unlock(tp);
3569 }
3570
3571 if (tg3_flag(tp, EEPROM_WRITE_PROT)) {
3572 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
3573 udelay(40);
3574 }
3575
3576 return ret;
3577}
3578
997b4f13
MC		 3579#define RX_CPU_SCRATCH_BASE 0x30000
3580#define RX_CPU_SCRATCH_SIZE 0x04000
3581#define TX_CPU_SCRATCH_BASE 0x34000
3582#define TX_CPU_SCRATCH_SIZE 0x04000
3583
3584/* tp->lock is held. */
837c45bb 3585static int tg3_pause_cpu(struct tg3 *tp, u32 cpu_base)
997b4f13
MC		 3586{
3587 int i;
837c45bb 3588 const int iters = 10000;
997b4f13 3589
837c45bb
NS		 3590 for (i = 0; i < iters; i++) {
3591 tw32(cpu_base + CPU_STATE, 0xffffffff);
3592 tw32(cpu_base + CPU_MODE, CPU_MODE_HALT);
3593 if (tr32(cpu_base + CPU_MODE) & CPU_MODE_HALT)
3594 break;
6d446ec3
GS		 3595 if (pci_channel_offline(tp->pdev))
3596 return -EBUSY;
837c45bb
NS		 3597 }
3598
3599 return (i == iters) ? -EBUSY : 0;
3600}
3601
3602/* tp->lock is held. */
3603static int tg3_rxcpu_pause(struct tg3 *tp)
3604{
3605 int rc = tg3_pause_cpu(tp, RX_CPU_BASE);
3606
3607 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
3608 tw32_f(RX_CPU_BASE + CPU_MODE, CPU_MODE_HALT);
3609 udelay(10);
3610
3611 return rc;
3612}
3613
3614/* tp->lock is held. */
3615static int tg3_txcpu_pause(struct tg3 *tp)
3616{
3617 return tg3_pause_cpu(tp, TX_CPU_BASE);
3618}
3619
3620/* tp->lock is held. */
3621static void tg3_resume_cpu(struct tg3 *tp, u32 cpu_base)
3622{
3623 tw32(cpu_base + CPU_STATE, 0xffffffff);
3624 tw32_f(cpu_base + CPU_MODE, 0x00000000);
3625}
3626
3627/* tp->lock is held. */
3628static void tg3_rxcpu_resume(struct tg3 *tp)
3629{
3630 tg3_resume_cpu(tp, RX_CPU_BASE);
3631}
3632
3633/* tp->lock is held. */
3634static int tg3_halt_cpu(struct tg3 *tp, u32 cpu_base)
3635{
3636 int rc;
3637
3638 BUG_ON(cpu_base == TX_CPU_BASE && tg3_flag(tp, 5705_PLUS));
997b4f13 3639
4153577a 3640 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
997b4f13
MC		 3641 u32 val = tr32(GRC_VCPU_EXT_CTRL);
3642
3643 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
3644 return 0;
3645 }
837c45bb
NS		 3646 if (cpu_base == RX_CPU_BASE) {
3647 rc = tg3_rxcpu_pause(tp);
997b4f13 3648 } else {
7e6c63f0
HM		 3649 /*
3650 * There is only an Rx CPU for the 5750 derivative in the
3651 * BCM4785.
3652 */
3653 if (tg3_flag(tp, IS_SSB_CORE))
3654 return 0;
3655
837c45bb 3656 rc = tg3_txcpu_pause(tp);
997b4f13
MC		 3657 }
3658
837c45bb 3659 if (rc) {
997b4f13 3660 netdev_err(tp->dev, "%s timed out, %s CPU\n",
837c45bb 3661 __func__, cpu_base == RX_CPU_BASE ? "RX" : "TX");
997b4f13
MC		 3662 return -ENODEV;
3663 }
3664
3665 /* Clear firmware's nvram arbitration. */
3666 if (tg3_flag(tp, NVRAM))
3667 tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
3668 return 0;
3669}
3670
31f11a95
NS		 3671static int tg3_fw_data_len(struct tg3 *tp,
3672 const struct tg3_firmware_hdr *fw_hdr)
3673{
3674 int fw_len;
3675
3676 /* Non fragmented firmware have one firmware header followed by a
3677 * contiguous chunk of data to be written. The length field in that
3678 * header is not the length of data to be written but the complete
3679 * length of the bss. The data length is determined based on
3680 * tp->fw->size minus headers.
3681 *
3682 * Fragmented firmware have a main header followed by multiple
3683 * fragments. Each fragment is identical to non fragmented firmware
3684 * with a firmware header followed by a contiguous chunk of data. In
3685 * the main header, the length field is unused and set to 0xffffffff.
3686 * In each fragment header the length is the entire size of that
3687 * fragment i.e. fragment data + header length. Data length is
3688 * therefore length field in the header minus TG3_FW_HDR_LEN.
3689 */
3690 if (tp->fw_len == 0xffffffff)
3691 fw_len = be32_to_cpu(fw_hdr->len);
3692 else
3693 fw_len = tp->fw->size;
3694
3695 return (fw_len - TG3_FW_HDR_LEN) / sizeof(u32);
3696}
3697
997b4f13
MC		 3698/* tp->lock is held. */
3699static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base,
3700 u32 cpu_scratch_base, int cpu_scratch_size,
77997ea3 3701 const struct tg3_firmware_hdr *fw_hdr)
997b4f13 3702{
c4dab506 3703 int err, i;
997b4f13 3704 void (*write_op)(struct tg3 *, u32, u32);
31f11a95 3705 int total_len = tp->fw->size;
997b4f13
MC		 3706
3707 if (cpu_base == TX_CPU_BASE && tg3_flag(tp, 5705_PLUS)) {
3708 netdev_err(tp->dev,
3709 "%s: Trying to load TX cpu firmware which is 5705\n",
3710 __func__);
3711 return -EINVAL;
3712 }
3713
c4dab506 3714 if (tg3_flag(tp, 5705_PLUS) && tg3_asic_rev(tp) != ASIC_REV_57766)
997b4f13
MC		 3715 write_op = tg3_write_mem;
3716 else
3717 write_op = tg3_write_indirect_reg32;
3718
c4dab506
NS		 3719 if (tg3_asic_rev(tp) != ASIC_REV_57766) {
3720 /* It is possible that bootcode is still loading at this point.
3721 * Get the nvram lock first before halting the cpu.
3722 */
3723 int lock_err = tg3_nvram_lock(tp);
3724 err = tg3_halt_cpu(tp, cpu_base);
3725 if (!lock_err)
3726 tg3_nvram_unlock(tp);
3727 if (err)
3728 goto out;
997b4f13 3729
c4dab506
NS		 3730 for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
3731 write_op(tp, cpu_scratch_base + i, 0);
3732 tw32(cpu_base + CPU_STATE, 0xffffffff);
3733 tw32(cpu_base + CPU_MODE,
3734 tr32(cpu_base + CPU_MODE) | CPU_MODE_HALT);
3735 } else {
3736 /* Subtract additional main header for fragmented firmware and
3737 * advance to the first fragment
3738 */
3739 total_len -= TG3_FW_HDR_LEN;
3740 fw_hdr++;
3741 }
77997ea3 3742
31f11a95
NS		 3743 do {
3744 u32 *fw_data = (u32 *)(fw_hdr + 1);
3745 for (i = 0; i < tg3_fw_data_len(tp, fw_hdr); i++)
3746 write_op(tp, cpu_scratch_base +
3747 (be32_to_cpu(fw_hdr->base_addr) & 0xffff) +
3748 (i * sizeof(u32)),
3749 be32_to_cpu(fw_data[i]));
3750
3751 total_len -= be32_to_cpu(fw_hdr->len);
3752
3753 /* Advance to next fragment */
3754 fw_hdr = (struct tg3_firmware_hdr *)
3755 ((void *)fw_hdr + be32_to_cpu(fw_hdr->len));
3756 } while (total_len > 0);
997b4f13
MC		 3757
3758 err = 0;
3759
3760out:
3761 return err;
3762}
3763
f4bffb28
NS		 3764/* tp->lock is held. */
3765static int tg3_pause_cpu_and_set_pc(struct tg3 *tp, u32 cpu_base, u32 pc)
3766{
3767 int i;
3768 const int iters = 5;
3769
3770 tw32(cpu_base + CPU_STATE, 0xffffffff);
3771 tw32_f(cpu_base + CPU_PC, pc);
3772
3773 for (i = 0; i < iters; i++) {
3774 if (tr32(cpu_base + CPU_PC) == pc)
3775 break;
3776 tw32(cpu_base + CPU_STATE, 0xffffffff);
3777 tw32(cpu_base + CPU_MODE, CPU_MODE_HALT);
3778 tw32_f(cpu_base + CPU_PC, pc);
3779 udelay(1000);
3780 }
3781
3782 return (i == iters) ? -EBUSY : 0;
3783}
3784
997b4f13
MC		 3785/* tp->lock is held. */
3786static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
3787{
77997ea3 3788 const struct tg3_firmware_hdr *fw_hdr;
f4bffb28 3789 int err;
997b4f13 3790
77997ea3 3791 fw_hdr = (struct tg3_firmware_hdr *)tp->fw->data;
997b4f13
MC		 3792
3793 /* Firmware blob starts with version numbers, followed by
3794 start address and length. We are setting complete length.
3795 length = end_address_of_bss - start_address_of_text.
3796 Remainder is the blob to be loaded contiguously
3797 from start address. */
3798
997b4f13
MC		 3799 err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
3800 RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
77997ea3 3801 fw_hdr);
997b4f13
MC		 3802 if (err)
3803 return err;
3804
3805 err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
3806 TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
77997ea3 3807 fw_hdr);
997b4f13
MC		 3808 if (err)
3809 return err;
3810
3811 /* Now startup only the RX cpu. */
77997ea3
NS		 3812 err = tg3_pause_cpu_and_set_pc(tp, RX_CPU_BASE,
3813 be32_to_cpu(fw_hdr->base_addr));
f4bffb28 3814 if (err) {
997b4f13
MC		 3815 netdev_err(tp->dev, "%s fails to set RX CPU PC, is %08x "
3816 "should be %08x\n", __func__,
77997ea3
NS		 3817 tr32(RX_CPU_BASE + CPU_PC),
3818 be32_to_cpu(fw_hdr->base_addr));
997b4f13
MC		 3819 return -ENODEV;
3820 }
837c45bb
NS		 3821
3822 tg3_rxcpu_resume(tp);
997b4f13
MC		 3823
3824 return 0;
3825}
3826
c4dab506
NS		 3827static int tg3_validate_rxcpu_state(struct tg3 *tp)
3828{
3829 const int iters = 1000;
3830 int i;
3831 u32 val;
3832
3833 /* Wait for boot code to complete initialization and enter service
3834 * loop. It is then safe to download service patches
3835 */
3836 for (i = 0; i < iters; i++) {
3837 if (tr32(RX_CPU_HWBKPT) == TG3_SBROM_IN_SERVICE_LOOP)
3838 break;
3839
3840 udelay(10);
3841 }
3842
3843 if (i == iters) {
3844 netdev_err(tp->dev, "Boot code not ready for service patches\n");
3845 return -EBUSY;
3846 }
3847
3848 val = tg3_read_indirect_reg32(tp, TG3_57766_FW_HANDSHAKE);
3849 if (val & 0xff) {
3850 netdev_warn(tp->dev,
3851 "Other patches exist. Not downloading EEE patch\n");
3852 return -EEXIST;
3853 }
3854
3855 return 0;
3856}
3857
3858/* tp->lock is held. */
3859static void tg3_load_57766_firmware(struct tg3 *tp)
3860{
3861 struct tg3_firmware_hdr *fw_hdr;
3862
3863 if (!tg3_flag(tp, NO_NVRAM))
3864 return;
3865
3866 if (tg3_validate_rxcpu_state(tp))
3867 return;
3868
3869 if (!tp->fw)
3870 return;
3871
3872 /* This firmware blob has a different format than older firmware
3873 * releases as given below. The main difference is we have fragmented
3874 * data to be written to non-contiguous locations.
3875 *
3876 * In the beginning we have a firmware header identical to other
3877 * firmware which consists of version, base addr and length. The length
3878 * here is unused and set to 0xffffffff.
3879 *
3880 * This is followed by a series of firmware fragments which are
3881 * individually identical to previous firmware. i.e. they have the
3882 * firmware header and followed by data for that fragment. The version
3883 * field of the individual fragment header is unused.
3884 */
3885
3886 fw_hdr = (struct tg3_firmware_hdr *)tp->fw->data;
3887 if (be32_to_cpu(fw_hdr->base_addr) != TG3_57766_FW_BASE_ADDR)
3888 return;
3889
3890 if (tg3_rxcpu_pause(tp))
3891 return;
3892
3893 /* tg3_load_firmware_cpu() will always succeed for the 57766 */
3894 tg3_load_firmware_cpu(tp, 0, TG3_57766_FW_BASE_ADDR, 0, fw_hdr);
3895
3896 tg3_rxcpu_resume(tp);
3897}
3898
997b4f13
MC		 3899/* tp->lock is held. */
3900static int tg3_load_tso_firmware(struct tg3 *tp)
3901{
77997ea3 3902 const struct tg3_firmware_hdr *fw_hdr;
997b4f13 3903 unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
f4bffb28 3904 int err;
997b4f13 3905
1caf13eb 3906 if (!tg3_flag(tp, FW_TSO))
997b4f13
MC		 3907 return 0;
3908
77997ea3 3909 fw_hdr = (struct tg3_firmware_hdr *)tp->fw->data;
997b4f13
MC		 3910
3911 /* Firmware blob starts with version numbers, followed by
3912 start address and length. We are setting complete length.
3913 length = end_address_of_bss - start_address_of_text.
3914 Remainder is the blob to be loaded contiguously
3915 from start address. */
3916
997b4f13 3917 cpu_scratch_size = tp->fw_len;
997b4f13 3918
4153577a 3919 if (tg3_asic_rev(tp) == ASIC_REV_5705) {
997b4f13
MC		 3920 cpu_base = RX_CPU_BASE;
3921 cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
3922 } else {
3923 cpu_base = TX_CPU_BASE;
3924 cpu_scratch_base = TX_CPU_SCRATCH_BASE;
3925 cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
3926 }
3927
3928 err = tg3_load_firmware_cpu(tp, cpu_base,
3929 cpu_scratch_base, cpu_scratch_size,
77997ea3 3930 fw_hdr);
997b4f13
MC		 3931 if (err)
3932 return err;
3933
3934 /* Now startup the cpu. */
77997ea3
NS		 3935 err = tg3_pause_cpu_and_set_pc(tp, cpu_base,
3936 be32_to_cpu(fw_hdr->base_addr));
f4bffb28 3937 if (err) {
997b4f13
MC		 3938 netdev_err(tp->dev,
3939 "%s fails to set CPU PC, is %08x should be %08x\n",
77997ea3
NS		 3940 __func__, tr32(cpu_base + CPU_PC),
3941 be32_to_cpu(fw_hdr->base_addr));
997b4f13
MC		 3942 return -ENODEV;
3943 }
837c45bb
NS		 3944
3945 tg3_resume_cpu(tp, cpu_base);
997b4f13
MC		 3946 return 0;
3947}
3948
f022ae62
MC		 3949/* tp->lock is held. */
3950static void __tg3_set_one_mac_addr(struct tg3 *tp, u8 *mac_addr, int index)
3951{
3952 u32 addr_high, addr_low;
3953
3954 addr_high = ((mac_addr[0] << 8) | mac_addr[1]);
3955 addr_low = ((mac_addr[2] << 24) | (mac_addr[3] << 16) |
3956 (mac_addr[4] << 8) | mac_addr[5]);
3957
3958 if (index < 4) {
3959 tw32(MAC_ADDR_0_HIGH + (index * 8), addr_high);
3960 tw32(MAC_ADDR_0_LOW + (index * 8), addr_low);
3961 } else {
3962 index -= 4;
3963 tw32(MAC_EXTADDR_0_HIGH + (index * 8), addr_high);
3964 tw32(MAC_EXTADDR_0_LOW + (index * 8), addr_low);
3965 }
3966}
997b4f13 3967
3f007891 3968/* tp->lock is held. */
953c96e0 3969static void __tg3_set_mac_addr(struct tg3 *tp, bool skip_mac_1)
3f007891 3970{
f022ae62 3971 u32 addr_high;
3f007891
MC		 3972 int i;
3973
3f007891
MC		 3974 for (i = 0; i < 4; i++) {
3975 if (i == 1 && skip_mac_1)
3976 continue;
f022ae62 3977 __tg3_set_one_mac_addr(tp, tp->dev->dev_addr, i);
3f007891
MC		 3978 }
3979
4153577a
JP		 3980 if (tg3_asic_rev(tp) == ASIC_REV_5703 ||
3981 tg3_asic_rev(tp) == ASIC_REV_5704) {
f022ae62
MC		 3982 for (i = 4; i < 16; i++)
3983 __tg3_set_one_mac_addr(tp, tp->dev->dev_addr, i);
3f007891
MC		 3984 }
3985
3986 addr_high = (tp->dev->dev_addr[0] +
3987 tp->dev->dev_addr[1] +
3988 tp->dev->dev_addr[2] +
3989 tp->dev->dev_addr[3] +
3990 tp->dev->dev_addr[4] +
3991 tp->dev->dev_addr[5]) &
3992 TX_BACKOFF_SEED_MASK;
3993 tw32(MAC_TX_BACKOFF_SEED, addr_high);
3994}
3995
c866b7ea 3996static void tg3_enable_register_access(struct tg3 *tp)
1da177e4 3997{
c866b7ea
RW		 3998 /*
3999 * Make sure register accesses (indirect or otherwise) will function
4000 * correctly.
1da177e4
LT		 4001 */
4002 pci_write_config_dword(tp->pdev,
c866b7ea
RW		 4003 TG3PCI_MISC_HOST_CTRL, tp->misc_host_ctrl);
4004}
1da177e4 4005
c866b7ea
RW		 4006static int tg3_power_up(struct tg3 *tp)
4007{
bed9829f 4008 int err;
8c6bda1a 4009
bed9829f 4010 tg3_enable_register_access(tp);
1da177e4 4011
bed9829f
MC		 4012 err = pci_set_power_state(tp->pdev, PCI_D0);
4013 if (!err) {
4014 /* Switch out of Vaux if it is a NIC */
4015 tg3_pwrsrc_switch_to_vmain(tp);
4016 } else {
4017 netdev_err(tp->dev, "Transition to D0 failed\n");
4018 }
1da177e4 4019
bed9829f 4020 return err;
c866b7ea 4021}
1da177e4 4022
953c96e0 4023static int tg3_setup_phy(struct tg3 *, bool);
4b409522 4024
c866b7ea
RW		 4025static int tg3_power_down_prepare(struct tg3 *tp)
4026{
4027 u32 misc_host_ctrl;
4028 bool device_should_wake, do_low_power;
4029
4030 tg3_enable_register_access(tp);
5e7dfd0f
MC		 4031
4032 /* Restore the CLKREQ setting. */
0f49bfbd
JL		 4033 if (tg3_flag(tp, CLKREQ_BUG))
4034 pcie_capability_set_word(tp->pdev, PCI_EXP_LNKCTL,
4035 PCI_EXP_LNKCTL_CLKREQ_EN);
5e7dfd0f 4036
1da177e4
LT		 4037 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
4038 tw32(TG3PCI_MISC_HOST_CTRL,
4039 misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
4040
c866b7ea 4041 device_should_wake = device_may_wakeup(&tp->pdev->dev) &&
63c3a66f 4042 tg3_flag(tp, WOL_ENABLE);
05ac4cb7 4043
63c3a66f 4044 if (tg3_flag(tp, USE_PHYLIB)) {
0a459aac 4045 do_low_power = false;
f07e9af3 4046 if ((tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) &&
80096068 4047 !(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
b02fd9e3 4048 struct phy_device *phydev;
0a459aac 4049 u32 phyid, advertising;
b02fd9e3 4050
ead2402c 4051 phydev = tp->mdio_bus->phy_map[tp->phy_addr];
b02fd9e3 4052
80096068 4053 tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER;
b02fd9e3 4054
c6700ce2
MC		 4055 tp->link_config.speed = phydev->speed;
4056 tp->link_config.duplex = phydev->duplex;
4057 tp->link_config.autoneg = phydev->autoneg;
4058 tp->link_config.advertising = phydev->advertising;
b02fd9e3
MC		 4059
4060 advertising = ADVERTISED_TP |
4061 ADVERTISED_Pause |
4062 ADVERTISED_Autoneg |
4063 ADVERTISED_10baseT_Half;
4064
63c3a66f
JP		 4065 if (tg3_flag(tp, ENABLE_ASF) || device_should_wake) {
4066 if (tg3_flag(tp, WOL_SPEED_100MB))
b02fd9e3
MC		 4067 advertising |=
4068 ADVERTISED_100baseT_Half |
4069 ADVERTISED_100baseT_Full |
4070 ADVERTISED_10baseT_Full;
4071 else
4072 advertising |= ADVERTISED_10baseT_Full;
4073 }
4074
4075 phydev->advertising = advertising;
4076
4077 phy_start_aneg(phydev);
0a459aac
MC		 4078
4079 phyid = phydev->drv->phy_id & phydev->drv->phy_id_mask;
6a443a0f
MC		 4080 if (phyid != PHY_ID_BCMAC131) {
4081 phyid &= PHY_BCM_OUI_MASK;
4082 if (phyid == PHY_BCM_OUI_1 ||
4083 phyid == PHY_BCM_OUI_2 ||
4084 phyid == PHY_BCM_OUI_3)
0a459aac
MC		 4085 do_low_power = true;
4086 }
b02fd9e3 4087 }
dd477003 4088 } else {
2023276e 4089 do_low_power = true;
0a459aac 4090
c6700ce2 4091 if (!(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER))
80096068 4092 tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER;
1da177e4 4093
2855b9fe 4094 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
953c96e0 4095 tg3_setup_phy(tp, false);
1da177e4
LT		 4096 }
4097
4153577a 4098 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
b5d3772c
MC		 4099 u32 val;
4100
4101 val = tr32(GRC_VCPU_EXT_CTRL);
4102 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
63c3a66f 4103 } else if (!tg3_flag(tp, ENABLE_ASF)) {
6921d201
MC		 4104 int i;
4105 u32 val;
4106
4107 for (i = 0; i < 200; i++) {
4108 tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
4109 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
4110 break;
4111 msleep(1);
4112 }
4113 }
63c3a66f 4114 if (tg3_flag(tp, WOL_CAP))
a85feb8c
GZ		 4115 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
4116 WOL_DRV_STATE_SHUTDOWN |
4117 WOL_DRV_WOL |
4118 WOL_SET_MAGIC_PKT);
6921d201 4119
05ac4cb7 4120 if (device_should_wake) {
1da177e4
LT		 4121 u32 mac_mode;
4122
f07e9af3 4123 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
b4bd2929
MC		 4124 if (do_low_power &&
4125 !(tp->phy_flags & TG3_PHYFLG_IS_FET)) {
4126 tg3_phy_auxctl_write(tp,
4127 MII_TG3_AUXCTL_SHDWSEL_PWRCTL,
4128 MII_TG3_AUXCTL_PCTL_WOL_EN |
4129 MII_TG3_AUXCTL_PCTL_100TX_LPWR |
4130 MII_TG3_AUXCTL_PCTL_CL_AB_TXDAC);
dd477003
MC		 4131 udelay(40);
4132 }
1da177e4 4133
f07e9af3 4134 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
3f7045c1 4135 mac_mode = MAC_MODE_PORT_MODE_GMII;
942d1af0
NS		 4136 else if (tp->phy_flags &
4137 TG3_PHYFLG_KEEP_LINK_ON_PWRDN) {
4138 if (tp->link_config.active_speed == SPEED_1000)
4139 mac_mode = MAC_MODE_PORT_MODE_GMII;
4140 else
4141 mac_mode = MAC_MODE_PORT_MODE_MII;
4142 } else
3f7045c1 4143 mac_mode = MAC_MODE_PORT_MODE_MII;
1da177e4 4144
e8f3f6ca 4145 mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
4153577a 4146 if (tg3_asic_rev(tp) == ASIC_REV_5700) {
63c3a66f 4147 u32 speed = tg3_flag(tp, WOL_SPEED_100MB) ?
e8f3f6ca
MC		 4148 SPEED_100 : SPEED_10;
4149 if (tg3_5700_link_polarity(tp, speed))
4150 mac_mode |= MAC_MODE_LINK_POLARITY;
4151 else
4152 mac_mode &= ~MAC_MODE_LINK_POLARITY;
4153 }
1da177e4
LT		 4154 } else {
4155 mac_mode = MAC_MODE_PORT_MODE_TBI;
4156 }
4157
63c3a66f 4158 if (!tg3_flag(tp, 5750_PLUS))
1da177e4
LT		 4159 tw32(MAC_LED_CTRL, tp->led_ctrl);
4160
05ac4cb7 4161 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
63c3a66f
JP		 4162 if ((tg3_flag(tp, 5705_PLUS) && !tg3_flag(tp, 5780_CLASS)) &&
4163 (tg3_flag(tp, ENABLE_ASF) || tg3_flag(tp, ENABLE_APE)))
05ac4cb7 4164 mac_mode |= MAC_MODE_KEEP_FRAME_IN_WOL;
1da177e4 4165
63c3a66f 4166 if (tg3_flag(tp, ENABLE_APE))
d2394e6b
MC		 4167 mac_mode |= MAC_MODE_APE_TX_EN |
4168 MAC_MODE_APE_RX_EN |
4169 MAC_MODE_TDE_ENABLE;
3bda1258 4170
1da177e4
LT		 4171 tw32_f(MAC_MODE, mac_mode);
4172 udelay(100);
4173
4174 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
4175 udelay(10);
4176 }
4177
63c3a66f 4178 if (!tg3_flag(tp, WOL_SPEED_100MB) &&
4153577a
JP		 4179 (tg3_asic_rev(tp) == ASIC_REV_5700 ||
4180 tg3_asic_rev(tp) == ASIC_REV_5701)) {
1da177e4
LT		 4181 u32 base_val;
4182
4183 base_val = tp->pci_clock_ctrl;
4184 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
4185 CLOCK_CTRL_TXCLK_DISABLE);
4186
b401e9e2
MC		 4187 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
4188 CLOCK_CTRL_PWRDOWN_PLL133, 40);
63c3a66f
JP		 4189 } else if (tg3_flag(tp, 5780_CLASS) ||
4190 tg3_flag(tp, CPMU_PRESENT) ||
4153577a 4191 tg3_asic_rev(tp) == ASIC_REV_5906) {
4cf78e4f 4192 /* do nothing */
63c3a66f 4193 } else if (!(tg3_flag(tp, 5750_PLUS) && tg3_flag(tp, ENABLE_ASF))) {
1da177e4
LT		 4194 u32 newbits1, newbits2;
4195
4153577a
JP		 4196 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
4197 tg3_asic_rev(tp) == ASIC_REV_5701) {
1da177e4
LT		 4198 newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
4199 CLOCK_CTRL_TXCLK_DISABLE |
4200 CLOCK_CTRL_ALTCLK);
4201 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
63c3a66f 4202 } else if (tg3_flag(tp, 5705_PLUS)) {
1da177e4
LT		 4203 newbits1 = CLOCK_CTRL_625_CORE;
4204 newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
4205 } else {
4206 newbits1 = CLOCK_CTRL_ALTCLK;
4207 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
4208 }
4209
b401e9e2
MC		 4210 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
4211 40);
1da177e4 4212
b401e9e2
MC		 4213 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
4214 40);
1da177e4 4215
63c3a66f 4216 if (!tg3_flag(tp, 5705_PLUS)) {
1da177e4
LT		 4217 u32 newbits3;
4218
4153577a
JP		 4219 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
4220 tg3_asic_rev(tp) == ASIC_REV_5701) {
1da177e4
LT		 4221 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
4222 CLOCK_CTRL_TXCLK_DISABLE |
4223 CLOCK_CTRL_44MHZ_CORE);
4224 } else {
4225 newbits3 = CLOCK_CTRL_44MHZ_CORE;
4226 }
4227
b401e9e2
MC		 4228 tw32_wait_f(TG3PCI_CLOCK_CTRL,
4229 tp->pci_clock_ctrl | newbits3, 40);
1da177e4
LT		 4230 }
4231 }
4232
63c3a66f 4233 if (!(device_should_wake) && !tg3_flag(tp, ENABLE_ASF))
0a459aac 4234 tg3_power_down_phy(tp, do_low_power);
6921d201 4235
cd0d7228 4236 tg3_frob_aux_power(tp, true);
1da177e4
LT		 4237
4238 /* Workaround for unstable PLL clock */
7e6c63f0 4239 if ((!tg3_flag(tp, IS_SSB_CORE)) &&
4153577a
JP		 4240 ((tg3_chip_rev(tp) == CHIPREV_5750_AX) ||
4241 (tg3_chip_rev(tp) == CHIPREV_5750_BX))) {
1da177e4
LT		 4242 u32 val = tr32(0x7d00);
4243
4244 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
4245 tw32(0x7d00, val);
63c3a66f 4246 if (!tg3_flag(tp, ENABLE_ASF)) {
ec41c7df
MC		 4247 int err;
4248
4249 err = tg3_nvram_lock(tp);
1da177e4 4250 tg3_halt_cpu(tp, RX_CPU_BASE);
ec41c7df
MC		 4251 if (!err)
4252 tg3_nvram_unlock(tp);
6921d201 4253 }
1da177e4
LT		 4254 }
4255
bbadf503
MC		 4256 tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
4257
2e460fc0
NS		 4258 tg3_ape_driver_state_change(tp, RESET_KIND_SHUTDOWN);
4259
c866b7ea
RW		 4260 return 0;
4261}
12dac075 4262
c866b7ea
RW		 4263static void tg3_power_down(struct tg3 *tp)
4264{
63c3a66f 4265 pci_wake_from_d3(tp->pdev, tg3_flag(tp, WOL_ENABLE));
c866b7ea 4266 pci_set_power_state(tp->pdev, PCI_D3hot);
1da177e4
LT		 4267}
4268
1da177e4
LT		 4269static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
4270{
4271 switch (val & MII_TG3_AUX_STAT_SPDMASK) {
4272 case MII_TG3_AUX_STAT_10HALF:
4273 *speed = SPEED_10;
4274 *duplex = DUPLEX_HALF;
4275 break;
4276
4277 case MII_TG3_AUX_STAT_10FULL:
4278 *speed = SPEED_10;
4279 *duplex = DUPLEX_FULL;
4280 break;
4281
4282 case MII_TG3_AUX_STAT_100HALF:
4283 *speed = SPEED_100;
4284 *duplex = DUPLEX_HALF;
4285 break;
4286
4287 case MII_TG3_AUX_STAT_100FULL:
4288 *speed = SPEED_100;
4289 *duplex = DUPLEX_FULL;
4290 break;
4291
4292 case MII_TG3_AUX_STAT_1000HALF:
4293 *speed = SPEED_1000;
4294 *duplex = DUPLEX_HALF;
4295 break;
4296
4297 case MII_TG3_AUX_STAT_1000FULL:
4298 *speed = SPEED_1000;
4299 *duplex = DUPLEX_FULL;
4300 break;
4301
4302 default:
f07e9af3 4303 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
715116a1
MC		 4304 *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
4305 SPEED_10;
4306 *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
4307 DUPLEX_HALF;
4308 break;
4309 }
e740522e
MC		 4310 *speed = SPEED_UNKNOWN;
4311 *duplex = DUPLEX_UNKNOWN;
1da177e4 4312 break;
855e1111 4313 }
1da177e4
LT		 4314}
4315
42b64a45 4316static int tg3_phy_autoneg_cfg(struct tg3 *tp, u32 advertise, u32 flowctrl)
1da177e4 4317{
42b64a45
MC		 4318 int err = 0;
4319 u32 val, new_adv;
1da177e4 4320
42b64a45 4321 new_adv = ADVERTISE_CSMA;
202ff1c2 4322 new_adv |= ethtool_adv_to_mii_adv_t(advertise) & ADVERTISE_ALL;
f88788f0 4323 new_adv |= mii_advertise_flowctrl(flowctrl);
1da177e4 4324
42b64a45
MC		 4325 err = tg3_writephy(tp, MII_ADVERTISE, new_adv);
4326 if (err)
4327 goto done;
ba4d07a8 4328
4f272096
MC		 4329 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
4330 new_adv = ethtool_adv_to_mii_ctrl1000_t(advertise);
ba4d07a8 4331
4153577a
JP		 4332 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0 ||
4333 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B0)
4f272096 4334 new_adv |= CTL1000_AS_MASTER | CTL1000_ENABLE_MASTER;
ba4d07a8 4335
4f272096
MC		 4336 err = tg3_writephy(tp, MII_CTRL1000, new_adv);
4337 if (err)
4338 goto done;
4339 }
1da177e4 4340
42b64a45
MC		 4341 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP))
4342 goto done;
52b02d04 4343
42b64a45
MC		 4344 tw32(TG3_CPMU_EEE_MODE,
4345 tr32(TG3_CPMU_EEE_MODE) & ~TG3_CPMU_EEEMD_LPI_ENABLE);
52b02d04 4346
daf3ec68 4347 err = tg3_phy_toggle_auxctl_smdsp(tp, true);
42b64a45
MC		 4348 if (!err) {
4349 u32 err2;
52b02d04 4350
b715ce94
MC		 4351 val = 0;
4352 /* Advertise 100-BaseTX EEE ability */
4353 if (advertise & ADVERTISED_100baseT_Full)
4354 val |= MDIO_AN_EEE_ADV_100TX;
4355 /* Advertise 1000-BaseT EEE ability */
4356 if (advertise & ADVERTISED_1000baseT_Full)
4357 val |= MDIO_AN_EEE_ADV_1000T;
9e2ecbeb
NS		 4358
4359 if (!tp->eee.eee_enabled) {
4360 val = 0;
4361 tp->eee.advertised = 0;
4362 } else {
4363 tp->eee.advertised = advertise &
4364 (ADVERTISED_100baseT_Full |
4365 ADVERTISED_1000baseT_Full);
4366 }
4367
b715ce94
MC		 4368 err = tg3_phy_cl45_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, val);
4369 if (err)
4370 val = 0;
4371
4153577a 4372 switch (tg3_asic_rev(tp)) {
21a00ab2
MC		 4373 case ASIC_REV_5717:
4374 case ASIC_REV_57765:
55086ad9 4375 case ASIC_REV_57766:
21a00ab2 4376 case ASIC_REV_5719:
b715ce94
MC		 4377 /* If we advertised any eee advertisements above... */
4378 if (val)
4379 val = MII_TG3_DSP_TAP26_ALNOKO |
4380 MII_TG3_DSP_TAP26_RMRXSTO |
4381 MII_TG3_DSP_TAP26_OPCSINPT;
21a00ab2 4382 tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, val);
be671947
MC		 4383 /* Fall through */
4384 case ASIC_REV_5720:
c65a17f4 4385 case ASIC_REV_5762:
be671947
MC		 4386 if (!tg3_phydsp_read(tp, MII_TG3_DSP_CH34TP2, &val))
4387 tg3_phydsp_write(tp, MII_TG3_DSP_CH34TP2, val |
4388 MII_TG3_DSP_CH34TP2_HIBW01);
21a00ab2 4389 }
52b02d04 4390
daf3ec68 4391 err2 = tg3_phy_toggle_auxctl_smdsp(tp, false);
42b64a45
MC		 4392 if (!err)
4393 err = err2;
4394 }
4395
4396done:
4397 return err;
4398}
4399
4400static void tg3_phy_copper_begin(struct tg3 *tp)
4401{
d13ba512
MC		 4402 if (tp->link_config.autoneg == AUTONEG_ENABLE ||
4403 (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
4404 u32 adv, fc;
4405
942d1af0
NS		 4406 if ((tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) &&
4407 !(tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN)) {
d13ba512
MC		 4408 adv = ADVERTISED_10baseT_Half |
4409 ADVERTISED_10baseT_Full;
4410 if (tg3_flag(tp, WOL_SPEED_100MB))
4411 adv |= ADVERTISED_100baseT_Half |
4412 ADVERTISED_100baseT_Full;
7c786065
NS		 4413 if (tp->phy_flags & TG3_PHYFLG_1G_ON_VAUX_OK) {
4414 if (!(tp->phy_flags &
4415 TG3_PHYFLG_DISABLE_1G_HD_ADV))
4416 adv |= ADVERTISED_1000baseT_Half;
4417 adv |= ADVERTISED_1000baseT_Full;
4418 }
d13ba512
MC		 4419
4420 fc = FLOW_CTRL_TX | FLOW_CTRL_RX;
42b64a45 4421 } else {
d13ba512
MC		 4422 adv = tp->link_config.advertising;
4423 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
4424 adv &= ~(ADVERTISED_1000baseT_Half |
4425 ADVERTISED_1000baseT_Full);
4426
4427 fc = tp->link_config.flowctrl;
52b02d04 4428 }
52b02d04 4429
d13ba512 4430 tg3_phy_autoneg_cfg(tp, adv, fc);
52b02d04 4431
942d1af0
NS		 4432 if ((tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) &&
4433 (tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN)) {
4434 /* Normally during power down we want to autonegotiate
4435 * the lowest possible speed for WOL. However, to avoid
4436 * link flap, we leave it untouched.
4437 */
4438 return;
4439 }
4440
d13ba512
MC		 4441 tg3_writephy(tp, MII_BMCR,
4442 BMCR_ANENABLE | BMCR_ANRESTART);
4443 } else {
4444 int i;
1da177e4
LT		 4445 u32 bmcr, orig_bmcr;
4446
4447 tp->link_config.active_speed = tp->link_config.speed;
4448 tp->link_config.active_duplex = tp->link_config.duplex;
4449
7c6cdead
NS		 4450 if (tg3_asic_rev(tp) == ASIC_REV_5714) {
4451 /* With autoneg disabled, 5715 only links up when the
4452 * advertisement register has the configured speed
4453 * enabled.
4454 */
4455 tg3_writephy(tp, MII_ADVERTISE, ADVERTISE_ALL);
4456 }
4457
1da177e4
LT		 4458 bmcr = 0;
4459 switch (tp->link_config.speed) {
4460 default:
4461 case SPEED_10:
4462 break;
4463
4464 case SPEED_100:
4465 bmcr |= BMCR_SPEED100;
4466 break;
4467
4468 case SPEED_1000:
221c5637 4469 bmcr |= BMCR_SPEED1000;
1da177e4 4470 break;
855e1111 4471 }
1da177e4
LT		 4472
4473 if (tp->link_config.duplex == DUPLEX_FULL)
4474 bmcr |= BMCR_FULLDPLX;
4475
4476 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
4477 (bmcr != orig_bmcr)) {
4478 tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
4479 for (i = 0; i < 1500; i++) {
4480 u32 tmp;
4481
4482 udelay(10);
4483 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
4484 tg3_readphy(tp, MII_BMSR, &tmp))
4485 continue;
4486 if (!(tmp & BMSR_LSTATUS)) {
4487 udelay(40);
4488 break;
4489 }
4490 }
4491 tg3_writephy(tp, MII_BMCR, bmcr);
4492 udelay(40);
4493 }
1da177e4
LT		 4494 }
4495}
4496
fdad8de4
NS		 4497static int tg3_phy_pull_config(struct tg3 *tp)
4498{
4499 int err;
4500 u32 val;
4501
4502 err = tg3_readphy(tp, MII_BMCR, &val);
4503 if (err)
4504 goto done;
4505
4506 if (!(val & BMCR_ANENABLE)) {
4507 tp->link_config.autoneg = AUTONEG_DISABLE;
4508 tp->link_config.advertising = 0;
4509 tg3_flag_clear(tp, PAUSE_AUTONEG);
4510
4511 err = -EIO;
4512
4513 switch (val & (BMCR_SPEED1000 | BMCR_SPEED100)) {
4514 case 0:
4515 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
4516 goto done;
4517
4518 tp->link_config.speed = SPEED_10;
4519 break;
4520 case BMCR_SPEED100:
4521 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
4522 goto done;
4523
4524 tp->link_config.speed = SPEED_100;
4525 break;
4526 case BMCR_SPEED1000:
4527 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
4528 tp->link_config.speed = SPEED_1000;
4529 break;
4530 }
4531 /* Fall through */
4532 default:
4533 goto done;
4534 }
4535
4536 if (val & BMCR_FULLDPLX)
4537 tp->link_config.duplex = DUPLEX_FULL;
4538 else
4539 tp->link_config.duplex = DUPLEX_HALF;
4540
4541 tp->link_config.flowctrl = FLOW_CTRL_RX | FLOW_CTRL_TX;
4542
4543 err = 0;
4544 goto done;
4545 }
4546
4547 tp->link_config.autoneg = AUTONEG_ENABLE;
4548 tp->link_config.advertising = ADVERTISED_Autoneg;
4549 tg3_flag_set(tp, PAUSE_AUTONEG);
4550
4551 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
4552 u32 adv;
4553
4554 err = tg3_readphy(tp, MII_ADVERTISE, &val);
4555 if (err)
4556 goto done;
4557
4558 adv = mii_adv_to_ethtool_adv_t(val & ADVERTISE_ALL);
4559 tp->link_config.advertising |= adv | ADVERTISED_TP;
4560
4561 tp->link_config.flowctrl = tg3_decode_flowctrl_1000T(val);
4562 } else {
4563 tp->link_config.advertising |= ADVERTISED_FIBRE;
4564 }
4565
4566 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
4567 u32 adv;
4568
4569 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
4570 err = tg3_readphy(tp, MII_CTRL1000, &val);
4571 if (err)
4572 goto done;
4573
4574 adv = mii_ctrl1000_to_ethtool_adv_t(val);
4575 } else {
4576 err = tg3_readphy(tp, MII_ADVERTISE, &val);
4577 if (err)
4578 goto done;
4579
4580 adv = tg3_decode_flowctrl_1000X(val);
4581 tp->link_config.flowctrl = adv;
4582
4583 val &= (ADVERTISE_1000XHALF | ADVERTISE_1000XFULL);
4584 adv = mii_adv_to_ethtool_adv_x(val);
4585 }
4586
4587 tp->link_config.advertising |= adv;
4588 }
4589
4590done:
4591 return err;
4592}
4593
1da177e4
LT		 4594static int tg3_init_5401phy_dsp(struct tg3 *tp)
4595{
4596 int err;
4597
4598 /* Turn off tap power management. */
4599 /* Set Extended packet length bit */
b4bd2929 4600 err = tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, 0x4c20);
1da177e4 4601
6ee7c0a0
MC		 4602 err |= tg3_phydsp_write(tp, 0x0012, 0x1804);
4603 err |= tg3_phydsp_write(tp, 0x0013, 0x1204);
4604 err |= tg3_phydsp_write(tp, 0x8006, 0x0132);
4605 err |= tg3_phydsp_write(tp, 0x8006, 0x0232);
4606 err |= tg3_phydsp_write(tp, 0x201f, 0x0a20);
1da177e4
LT		 4607
4608 udelay(40);
4609
4610 return err;
4611}
4612
ed1ff5c3
NS		 4613static bool tg3_phy_eee_config_ok(struct tg3 *tp)
4614{
5b6c273a 4615 struct ethtool_eee eee;
ed1ff5c3
NS		 4616
4617 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP))
4618 return true;
4619
5b6c273a 4620 tg3_eee_pull_config(tp, &eee);
ed1ff5c3 4621
5b6c273a
NS		 4622 if (tp->eee.eee_enabled) {
4623 if (tp->eee.advertised != eee.advertised ||
4624 tp->eee.tx_lpi_timer != eee.tx_lpi_timer ||
4625 tp->eee.tx_lpi_enabled != eee.tx_lpi_enabled)
4626 return false;
4627 } else {
4628 /* EEE is disabled but we're advertising */
4629 if (eee.advertised)
4630 return false;
4631 }
ed1ff5c3
NS		 4632
4633 return true;
4634}
4635
e2bf73e7 4636static bool tg3_phy_copper_an_config_ok(struct tg3 *tp, u32 *lcladv)
1da177e4 4637{
e2bf73e7 4638 u32 advmsk, tgtadv, advertising;
3600d918 4639
e2bf73e7
MC		 4640 advertising = tp->link_config.advertising;
4641 tgtadv = ethtool_adv_to_mii_adv_t(advertising) & ADVERTISE_ALL;
1da177e4 4642
e2bf73e7
MC		 4643 advmsk = ADVERTISE_ALL;
4644 if (tp->link_config.active_duplex == DUPLEX_FULL) {
f88788f0 4645 tgtadv |= mii_advertise_flowctrl(tp->link_config.flowctrl);
e2bf73e7
MC		 4646 advmsk |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
4647 }
1da177e4 4648
e2bf73e7
MC		 4649 if (tg3_readphy(tp, MII_ADVERTISE, lcladv))
4650 return false;
4651
4652 if ((*lcladv & advmsk) != tgtadv)
4653 return false;
b99d2a57 4654
f07e9af3 4655 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
1da177e4
LT		 4656 u32 tg3_ctrl;
4657
e2bf73e7 4658 tgtadv = ethtool_adv_to_mii_ctrl1000_t(advertising);
3600d918 4659
221c5637 4660 if (tg3_readphy(tp, MII_CTRL1000, &tg3_ctrl))
e2bf73e7 4661 return false;
1da177e4 4662
3198e07f 4663 if (tgtadv &&
4153577a
JP		 4664 (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0 ||
4665 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B0)) {
3198e07f
MC		 4666 tgtadv |= CTL1000_AS_MASTER | CTL1000_ENABLE_MASTER;
4667 tg3_ctrl &= (ADVERTISE_1000HALF | ADVERTISE_1000FULL |
4668 CTL1000_AS_MASTER | CTL1000_ENABLE_MASTER);
4669 } else {
4670 tg3_ctrl &= (ADVERTISE_1000HALF | ADVERTISE_1000FULL);
4671 }
4672
e2bf73e7
MC		 4673 if (tg3_ctrl != tgtadv)
4674 return false;
ef167e27
MC		 4675 }
4676
e2bf73e7 4677 return true;
ef167e27
MC		 4678}
4679
859edb26
MC		 4680static bool tg3_phy_copper_fetch_rmtadv(struct tg3 *tp, u32 *rmtadv)
4681{
4682 u32 lpeth = 0;
4683
4684 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
4685 u32 val;
4686
4687 if (tg3_readphy(tp, MII_STAT1000, &val))
4688 return false;
4689
4690 lpeth = mii_stat1000_to_ethtool_lpa_t(val);
4691 }
4692
4693 if (tg3_readphy(tp, MII_LPA, rmtadv))
4694 return false;
4695
4696 lpeth |= mii_lpa_to_ethtool_lpa_t(*rmtadv);
4697 tp->link_config.rmt_adv = lpeth;
4698
4699 return true;
4700}
4701
953c96e0 4702static bool tg3_test_and_report_link_chg(struct tg3 *tp, bool curr_link_up)
f4a46d1f
NNS		 4703{
4704 if (curr_link_up != tp->link_up) {
4705 if (curr_link_up) {
84421b99 4706 netif_carrier_on(tp->dev);
f4a46d1f 4707 } else {
84421b99 4708 netif_carrier_off(tp->dev);
f4a46d1f
NNS		 4709 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
4710 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4711 }
4712
4713 tg3_link_report(tp);
4714 return true;
4715 }
4716
4717 return false;
4718}
4719
3310e248
MC		 4720static void tg3_clear_mac_status(struct tg3 *tp)
4721{
4722 tw32(MAC_EVENT, 0);
4723
4724 tw32_f(MAC_STATUS,
4725 MAC_STATUS_SYNC_CHANGED |
4726 MAC_STATUS_CFG_CHANGED |
4727 MAC_STATUS_MI_COMPLETION |
4728 MAC_STATUS_LNKSTATE_CHANGED);
4729 udelay(40);
4730}
4731
9e2ecbeb
NS		 4732static void tg3_setup_eee(struct tg3 *tp)
4733{
4734 u32 val;
4735
4736 val = TG3_CPMU_EEE_LNKIDL_PCIE_NL0 |
4737 TG3_CPMU_EEE_LNKIDL_UART_IDL;
4738 if (tg3_chip_rev_id(tp) == CHIPREV_ID_57765_A0)
4739 val |= TG3_CPMU_EEE_LNKIDL_APE_TX_MT;
4740
4741 tw32_f(TG3_CPMU_EEE_LNKIDL_CTRL, val);
4742
4743 tw32_f(TG3_CPMU_EEE_CTRL,
4744 TG3_CPMU_EEE_CTRL_EXIT_20_1_US);
4745
4746 val = TG3_CPMU_EEEMD_ERLY_L1_XIT_DET |
4747 (tp->eee.tx_lpi_enabled ? TG3_CPMU_EEEMD_LPI_IN_TX : 0) |
4748 TG3_CPMU_EEEMD_LPI_IN_RX |
4749 TG3_CPMU_EEEMD_EEE_ENABLE;
4750
4751 if (tg3_asic_rev(tp) != ASIC_REV_5717)
4752 val |= TG3_CPMU_EEEMD_SND_IDX_DET_EN;
4753
4754 if (tg3_flag(tp, ENABLE_APE))
4755 val |= TG3_CPMU_EEEMD_APE_TX_DET_EN;
4756
4757 tw32_f(TG3_CPMU_EEE_MODE, tp->eee.eee_enabled ? val : 0);
4758
4759 tw32_f(TG3_CPMU_EEE_DBTMR1,
4760 TG3_CPMU_DBTMR1_PCIEXIT_2047US |
4761 (tp->eee.tx_lpi_timer & 0xffff));
4762
4763 tw32_f(TG3_CPMU_EEE_DBTMR2,
4764 TG3_CPMU_DBTMR2_APE_TX_2047US |
4765 TG3_CPMU_DBTMR2_TXIDXEQ_2047US);
4766}
4767
953c96e0 4768static int tg3_setup_copper_phy(struct tg3 *tp, bool force_reset)
1da177e4 4769{
953c96e0 4770 bool current_link_up;
f833c4c1 4771 u32 bmsr, val;
ef167e27 4772 u32 lcl_adv, rmt_adv;
1da177e4
LT		 4773 u16 current_speed;
4774 u8 current_duplex;
4775 int i, err;
4776
3310e248 4777 tg3_clear_mac_status(tp);
1da177e4 4778
8ef21428
MC		 4779 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
4780 tw32_f(MAC_MI_MODE,
4781 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
4782 udelay(80);
4783 }
1da177e4 4784
b4bd2929 4785 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_PWRCTL, 0);
1da177e4
LT		 4786
4787 /* Some third-party PHYs need to be reset on link going
4788 * down.
4789 */
4153577a
JP		 4790 if ((tg3_asic_rev(tp) == ASIC_REV_5703 ||
4791 tg3_asic_rev(tp) == ASIC_REV_5704 ||
4792 tg3_asic_rev(tp) == ASIC_REV_5705) &&
f4a46d1f 4793 tp->link_up) {
1da177e4
LT		 4794 tg3_readphy(tp, MII_BMSR, &bmsr);
4795 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
4796 !(bmsr & BMSR_LSTATUS))
953c96e0 4797 force_reset = true;
1da177e4
LT		 4798 }
4799 if (force_reset)
4800 tg3_phy_reset(tp);
4801
79eb6904 4802 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
1da177e4
LT		 4803 tg3_readphy(tp, MII_BMSR, &bmsr);
4804 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
63c3a66f 4805 !tg3_flag(tp, INIT_COMPLETE))
1da177e4
LT		 4806 bmsr = 0;
4807
4808 if (!(bmsr & BMSR_LSTATUS)) {
4809 err = tg3_init_5401phy_dsp(tp);
4810 if (err)
4811 return err;
4812
4813 tg3_readphy(tp, MII_BMSR, &bmsr);
4814 for (i = 0; i < 1000; i++) {
4815 udelay(10);
4816 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
4817 (bmsr & BMSR_LSTATUS)) {
4818 udelay(40);
4819 break;
4820 }
4821 }
4822
79eb6904
MC		 4823 if ((tp->phy_id & TG3_PHY_ID_REV_MASK) ==
4824 TG3_PHY_REV_BCM5401_B0 &&
1da177e4
LT		 4825 !(bmsr & BMSR_LSTATUS) &&
4826 tp->link_config.active_speed == SPEED_1000) {
4827 err = tg3_phy_reset(tp);
4828 if (!err)
4829 err = tg3_init_5401phy_dsp(tp);
4830 if (err)
4831 return err;
4832 }
4833 }
4153577a
JP		 4834 } else if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0 ||
4835 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B0) {
1da177e4
LT		 4836 /* 5701 {A0,B0} CRC bug workaround */
4837 tg3_writephy(tp, 0x15, 0x0a75);
f08aa1a8
MC		 4838 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68);
4839 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
4840 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68);
1da177e4
LT		 4841 }
4842
4843 /* Clear pending interrupts... */
f833c4c1
MC		 4844 tg3_readphy(tp, MII_TG3_ISTAT, &val);
4845 tg3_readphy(tp, MII_TG3_ISTAT, &val);
1da177e4 4846
f07e9af3 4847 if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT)
1da177e4 4848 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
f07e9af3 4849 else if (!(tp->phy_flags & TG3_PHYFLG_IS_FET))
1da177e4
LT		 4850 tg3_writephy(tp, MII_TG3_IMASK, ~0);
4851
4153577a
JP		 4852 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
4853 tg3_asic_rev(tp) == ASIC_REV_5701) {
1da177e4
LT		 4854 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
4855 tg3_writephy(tp, MII_TG3_EXT_CTRL,
4856 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
4857 else
4858 tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
4859 }
4860
953c96e0 4861 current_link_up = false;
e740522e
MC		 4862 current_speed = SPEED_UNKNOWN;
4863 current_duplex = DUPLEX_UNKNOWN;
e348c5e7 4864 tp->phy_flags &= ~TG3_PHYFLG_MDIX_STATE;
859edb26 4865 tp->link_config.rmt_adv = 0;
1da177e4 4866
f07e9af3 4867 if (tp->phy_flags & TG3_PHYFLG_CAPACITIVE_COUPLING) {
15ee95c3
MC		 4868 err = tg3_phy_auxctl_read(tp,
4869 MII_TG3_AUXCTL_SHDWSEL_MISCTEST,
4870 &val);
4871 if (!err && !(val & (1 << 10))) {
b4bd2929
MC		 4872 tg3_phy_auxctl_write(tp,
4873 MII_TG3_AUXCTL_SHDWSEL_MISCTEST,
4874 val | (1 << 10));
1da177e4
LT		 4875 goto relink;
4876 }
4877 }
4878
4879 bmsr = 0;
4880 for (i = 0; i < 100; i++) {
4881 tg3_readphy(tp, MII_BMSR, &bmsr);
4882 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
4883 (bmsr & BMSR_LSTATUS))
4884 break;
4885 udelay(40);
4886 }
4887
4888 if (bmsr & BMSR_LSTATUS) {
4889 u32 aux_stat, bmcr;
4890
4891 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
4892 for (i = 0; i < 2000; i++) {
4893 udelay(10);
4894 if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
4895 aux_stat)
4896 break;
4897 }
4898
4899 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
4900 &current_speed,
4901 &current_duplex);
4902
4903 bmcr = 0;
4904 for (i = 0; i < 200; i++) {
4905 tg3_readphy(tp, MII_BMCR, &bmcr);
4906 if (tg3_readphy(tp, MII_BMCR, &bmcr))
4907 continue;
4908 if (bmcr && bmcr != 0x7fff)
4909 break;
4910 udelay(10);
4911 }
4912
ef167e27
MC		 4913 lcl_adv = 0;
4914 rmt_adv = 0;
1da177e4 4915
ef167e27
MC		 4916 tp->link_config.active_speed = current_speed;
4917 tp->link_config.active_duplex = current_duplex;
4918
4919 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
ed1ff5c3
NS		 4920 bool eee_config_ok = tg3_phy_eee_config_ok(tp);
4921
ef167e27 4922 if ((bmcr & BMCR_ANENABLE) &&
ed1ff5c3 4923 eee_config_ok &&
e2bf73e7 4924 tg3_phy_copper_an_config_ok(tp, &lcl_adv) &&
859edb26 4925 tg3_phy_copper_fetch_rmtadv(tp, &rmt_adv))
953c96e0 4926 current_link_up = true;
ed1ff5c3
NS		 4927
4928 /* EEE settings changes take effect only after a phy
4929 * reset. If we have skipped a reset due to Link Flap
4930 * Avoidance being enabled, do it now.
4931 */
4932 if (!eee_config_ok &&
4933 (tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN) &&
5b6c273a
NS		 4934 !force_reset) {
4935 tg3_setup_eee(tp);
ed1ff5c3 4936 tg3_phy_reset(tp);
5b6c273a 4937 }
1da177e4
LT		 4938 } else {
4939 if (!(bmcr & BMCR_ANENABLE) &&
4940 tp->link_config.speed == current_speed &&
f0fcd7a9 4941 tp->link_config.duplex == current_duplex) {
953c96e0 4942 current_link_up = true;
1da177e4
LT		 4943 }
4944 }
4945
953c96e0 4946 if (current_link_up &&
e348c5e7
MC		 4947 tp->link_config.active_duplex == DUPLEX_FULL) {
4948 u32 reg, bit;
4949
4950 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
4951 reg = MII_TG3_FET_GEN_STAT;
4952 bit = MII_TG3_FET_GEN_STAT_MDIXSTAT;
4953 } else {
4954 reg = MII_TG3_EXT_STAT;
4955 bit = MII_TG3_EXT_STAT_MDIX;
4956 }
4957
4958 if (!tg3_readphy(tp, reg, &val) && (val & bit))
4959 tp->phy_flags |= TG3_PHYFLG_MDIX_STATE;
4960
ef167e27 4961 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
e348c5e7 4962 }
1da177e4
LT		 4963 }
4964
1da177e4 4965relink:
953c96e0 4966 if (!current_link_up || (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
1da177e4
LT		 4967 tg3_phy_copper_begin(tp);
4968
7e6c63f0 4969 if (tg3_flag(tp, ROBOSWITCH)) {
953c96e0 4970 current_link_up = true;
7e6c63f0
HM		 4971 /* FIXME: when BCM5325 switch is used use 100 MBit/s */
4972 current_speed = SPEED_1000;
4973 current_duplex = DUPLEX_FULL;
4974 tp->link_config.active_speed = current_speed;
4975 tp->link_config.active_duplex = current_duplex;
4976 }
4977
f833c4c1 4978 tg3_readphy(tp, MII_BMSR, &bmsr);
06c03c02
MB		 4979 if ((!tg3_readphy(tp, MII_BMSR, &bmsr) && (bmsr & BMSR_LSTATUS)) ||
4980 (tp->mac_mode & MAC_MODE_PORT_INT_LPBACK))
953c96e0 4981 current_link_up = true;
1da177e4
LT		 4982 }
4983
4984 tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
953c96e0 4985 if (current_link_up) {
1da177e4
LT		 4986 if (tp->link_config.active_speed == SPEED_100 ||
4987 tp->link_config.active_speed == SPEED_10)
4988 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
4989 else
4990 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
f07e9af3 4991 } else if (tp->phy_flags & TG3_PHYFLG_IS_FET)
7f97a4bd
MC		 4992 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
4993 else
1da177e4
LT		 4994 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
4995
7e6c63f0
HM		 4996 /* In order for the 5750 core in BCM4785 chip to work properly
4997 * in RGMII mode, the Led Control Register must be set up.
4998 */
4999 if (tg3_flag(tp, RGMII_MODE)) {
5000 u32 led_ctrl = tr32(MAC_LED_CTRL);
5001 led_ctrl &= ~(LED_CTRL_1000MBPS_ON | LED_CTRL_100MBPS_ON);
5002
5003 if (tp->link_config.active_speed == SPEED_10)
5004 led_ctrl |= LED_CTRL_LNKLED_OVERRIDE;
5005 else if (tp->link_config.active_speed == SPEED_100)
5006 led_ctrl |= (LED_CTRL_LNKLED_OVERRIDE |
5007 LED_CTRL_100MBPS_ON);
5008 else if (tp->link_config.active_speed == SPEED_1000)
5009 led_ctrl |= (LED_CTRL_LNKLED_OVERRIDE |
5010 LED_CTRL_1000MBPS_ON);
5011
5012 tw32(MAC_LED_CTRL, led_ctrl);
5013 udelay(40);
5014 }
5015
1da177e4
LT		 5016 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
5017 if (tp->link_config.active_duplex == DUPLEX_HALF)
5018 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
5019
4153577a 5020 if (tg3_asic_rev(tp) == ASIC_REV_5700) {
953c96e0 5021 if (current_link_up &&
e8f3f6ca 5022 tg3_5700_link_polarity(tp, tp->link_config.active_speed))
1da177e4 5023 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
e8f3f6ca
MC		 5024 else
5025 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
1da177e4
LT		 5026 }
5027
5028 /* ??? Without this setting Netgear GA302T PHY does not
5029 * ??? send/receive packets...
5030 */
79eb6904 5031 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411 &&
4153577a 5032 tg3_chip_rev_id(tp) == CHIPREV_ID_5700_ALTIMA) {
1da177e4
LT		 5033 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
5034 tw32_f(MAC_MI_MODE, tp->mi_mode);
5035 udelay(80);
5036 }
5037
5038 tw32_f(MAC_MODE, tp->mac_mode);
5039 udelay(40);
5040
52b02d04
MC		 5041 tg3_phy_eee_adjust(tp, current_link_up);
5042
63c3a66f 5043 if (tg3_flag(tp, USE_LINKCHG_REG)) {
1da177e4
LT		 5044 /* Polled via timer. */
5045 tw32_f(MAC_EVENT, 0);
5046 } else {
5047 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
5048 }
5049 udelay(40);
5050
4153577a 5051 if (tg3_asic_rev(tp) == ASIC_REV_5700 &&
953c96e0 5052 current_link_up &&
1da177e4 5053 tp->link_config.active_speed == SPEED_1000 &&
63c3a66f 5054 (tg3_flag(tp, PCIX_MODE) || tg3_flag(tp, PCI_HIGH_SPEED))) {
1da177e4
LT		 5055 udelay(120);
5056 tw32_f(MAC_STATUS,
5057 (MAC_STATUS_SYNC_CHANGED |
5058 MAC_STATUS_CFG_CHANGED));
5059 udelay(40);
5060 tg3_write_mem(tp,
5061 NIC_SRAM_FIRMWARE_MBOX,
5062 NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
5063 }
5064
5e7dfd0f 5065 /* Prevent send BD corruption. */
63c3a66f 5066 if (tg3_flag(tp, CLKREQ_BUG)) {
5e7dfd0f
MC		 5067 if (tp->link_config.active_speed == SPEED_100 ||
5068 tp->link_config.active_speed == SPEED_10)
0f49bfbd
JL		 5069 pcie_capability_clear_word(tp->pdev, PCI_EXP_LNKCTL,
5070 PCI_EXP_LNKCTL_CLKREQ_EN);
5e7dfd0f 5071 else
0f49bfbd
JL		 5072 pcie_capability_set_word(tp->pdev, PCI_EXP_LNKCTL,
5073 PCI_EXP_LNKCTL_CLKREQ_EN);
5e7dfd0f
MC		 5074 }
5075
f4a46d1f 5076 tg3_test_and_report_link_chg(tp, current_link_up);
1da177e4
LT		 5077
5078 return 0;
5079}
5080
5081struct tg3_fiber_aneginfo {
5082 int state;
5083#define ANEG_STATE_UNKNOWN 0
5084#define ANEG_STATE_AN_ENABLE 1
5085#define ANEG_STATE_RESTART_INIT 2
5086#define ANEG_STATE_RESTART 3
5087#define ANEG_STATE_DISABLE_LINK_OK 4
5088#define ANEG_STATE_ABILITY_DETECT_INIT 5
5089#define ANEG_STATE_ABILITY_DETECT 6
5090#define ANEG_STATE_ACK_DETECT_INIT 7
5091#define ANEG_STATE_ACK_DETECT 8
5092#define ANEG_STATE_COMPLETE_ACK_INIT 9
5093#define ANEG_STATE_COMPLETE_ACK 10
5094#define ANEG_STATE_IDLE_DETECT_INIT 11
5095#define ANEG_STATE_IDLE_DETECT 12
5096#define ANEG_STATE_LINK_OK 13
5097#define ANEG_STATE_NEXT_PAGE_WAIT_INIT 14
5098#define ANEG_STATE_NEXT_PAGE_WAIT 15
5099
5100 u32 flags;
5101#define MR_AN_ENABLE 0x00000001
5102#define MR_RESTART_AN 0x00000002
5103#define MR_AN_COMPLETE 0x00000004
5104#define MR_PAGE_RX 0x00000008
5105#define MR_NP_LOADED 0x00000010
5106#define MR_TOGGLE_TX 0x00000020
5107#define MR_LP_ADV_FULL_DUPLEX 0x00000040
5108#define MR_LP_ADV_HALF_DUPLEX 0x00000080
5109#define MR_LP_ADV_SYM_PAUSE 0x00000100
5110#define MR_LP_ADV_ASYM_PAUSE 0x00000200
5111#define MR_LP_ADV_REMOTE_FAULT1 0x00000400
5112#define MR_LP_ADV_REMOTE_FAULT2 0x00000800
5113#define MR_LP_ADV_NEXT_PAGE 0x00001000
5114#define MR_TOGGLE_RX 0x00002000
5115#define MR_NP_RX 0x00004000
5116
5117#define MR_LINK_OK 0x80000000
5118
5119 unsigned long link_time, cur_time;
5120
5121 u32 ability_match_cfg;
5122 int ability_match_count;
5123
5124 char ability_match, idle_match, ack_match;
5125
5126 u32 txconfig, rxconfig;
5127#define ANEG_CFG_NP 0x00000080
5128#define ANEG_CFG_ACK 0x00000040
5129#define ANEG_CFG_RF2 0x00000020
5130#define ANEG_CFG_RF1 0x00000010
5131#define ANEG_CFG_PS2 0x00000001
5132#define ANEG_CFG_PS1 0x00008000
5133#define ANEG_CFG_HD 0x00004000
5134#define ANEG_CFG_FD 0x00002000
5135#define ANEG_CFG_INVAL 0x00001f06
5136
5137};
5138#define ANEG_OK 0
5139#define ANEG_DONE 1
5140#define ANEG_TIMER_ENAB 2
5141#define ANEG_FAILED -1
5142
5143#define ANEG_STATE_SETTLE_TIME 10000
5144
5145static int tg3_fiber_aneg_smachine(struct tg3 *tp,
5146 struct tg3_fiber_aneginfo *ap)
5147{
5be73b47 5148 u16 flowctrl;
1da177e4
LT		 5149 unsigned long delta;
5150 u32 rx_cfg_reg;
5151 int ret;
5152
5153 if (ap->state == ANEG_STATE_UNKNOWN) {
5154 ap->rxconfig = 0;
5155 ap->link_time = 0;
5156 ap->cur_time = 0;
5157 ap->ability_match_cfg = 0;
5158 ap->ability_match_count = 0;
5159 ap->ability_match = 0;
5160 ap->idle_match = 0;
5161 ap->ack_match = 0;
5162 }
5163 ap->cur_time++;
5164
5165 if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
5166 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
5167
5168 if (rx_cfg_reg != ap->ability_match_cfg) {
5169 ap->ability_match_cfg = rx_cfg_reg;
5170 ap->ability_match = 0;
5171 ap->ability_match_count = 0;
5172 } else {
5173 if (++ap->ability_match_count > 1) {
5174 ap->ability_match = 1;
5175 ap->ability_match_cfg = rx_cfg_reg;
5176 }
5177 }
5178 if (rx_cfg_reg & ANEG_CFG_ACK)
5179 ap->ack_match = 1;
5180 else
5181 ap->ack_match = 0;
5182
5183 ap->idle_match = 0;
5184 } else {
5185 ap->idle_match = 1;
5186 ap->ability_match_cfg = 0;
5187 ap->ability_match_count = 0;
5188 ap->ability_match = 0;
5189 ap->ack_match = 0;
5190
5191 rx_cfg_reg = 0;
5192 }
5193
5194 ap->rxconfig = rx_cfg_reg;
5195 ret = ANEG_OK;
5196
33f401ae 5197 switch (ap->state) {
1da177e4
LT		 5198 case ANEG_STATE_UNKNOWN:
5199 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
5200 ap->state = ANEG_STATE_AN_ENABLE;
5201
5202 /* fallthru */
5203 case ANEG_STATE_AN_ENABLE:
5204 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
5205 if (ap->flags & MR_AN_ENABLE) {
5206 ap->link_time = 0;
5207 ap->cur_time = 0;
5208 ap->ability_match_cfg = 0;
5209 ap->ability_match_count = 0;
5210 ap->ability_match = 0;
5211 ap->idle_match = 0;
5212 ap->ack_match = 0;
5213
5214 ap->state = ANEG_STATE_RESTART_INIT;
5215 } else {
5216 ap->state = ANEG_STATE_DISABLE_LINK_OK;
5217 }
5218 break;
5219
5220 case ANEG_STATE_RESTART_INIT:
5221 ap->link_time = ap->cur_time;
5222 ap->flags &= ~(MR_NP_LOADED);
5223 ap->txconfig = 0;
5224 tw32(MAC_TX_AUTO_NEG, 0);
5225 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
5226 tw32_f(MAC_MODE, tp->mac_mode);
5227 udelay(40);
5228
5229 ret = ANEG_TIMER_ENAB;
5230 ap->state = ANEG_STATE_RESTART;
5231
5232 /* fallthru */
5233 case ANEG_STATE_RESTART:
5234 delta = ap->cur_time - ap->link_time;
859a5887 5235 if (delta > ANEG_STATE_SETTLE_TIME)
1da177e4 5236 ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
859a5887 5237 else
1da177e4 5238 ret = ANEG_TIMER_ENAB;
1da177e4
LT		 5239 break;
5240
5241 case ANEG_STATE_DISABLE_LINK_OK:
5242 ret = ANEG_DONE;
5243 break;
5244
5245 case ANEG_STATE_ABILITY_DETECT_INIT:
5246 ap->flags &= ~(MR_TOGGLE_TX);
5be73b47
MC		 5247 ap->txconfig = ANEG_CFG_FD;
5248 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
5249 if (flowctrl & ADVERTISE_1000XPAUSE)
5250 ap->txconfig |= ANEG_CFG_PS1;
5251 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
5252 ap->txconfig |= ANEG_CFG_PS2;
1da177e4
LT		 5253 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
5254 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
5255 tw32_f(MAC_MODE, tp->mac_mode);
5256 udelay(40);
5257
5258 ap->state = ANEG_STATE_ABILITY_DETECT;
5259 break;
5260
5261 case ANEG_STATE_ABILITY_DETECT:
859a5887 5262 if (ap->ability_match != 0 && ap->rxconfig != 0)
1da177e4 5263 ap->state = ANEG_STATE_ACK_DETECT_INIT;
1da177e4
LT		 5264 break;
5265
5266 case ANEG_STATE_ACK_DETECT_INIT:
5267 ap->txconfig |= ANEG_CFG_ACK;
5268 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
5269 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
5270 tw32_f(MAC_MODE, tp->mac_mode);
5271 udelay(40);
5272
5273 ap->state = ANEG_STATE_ACK_DETECT;
5274
5275 /* fallthru */
5276 case ANEG_STATE_ACK_DETECT:
5277 if (ap->ack_match != 0) {
5278 if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
5279 (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
5280 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
5281 } else {
5282 ap->state = ANEG_STATE_AN_ENABLE;
5283 }
5284 } else if (ap->ability_match != 0 &&
5285 ap->rxconfig == 0) {
5286 ap->state = ANEG_STATE_AN_ENABLE;
5287 }
5288 break;
5289
5290 case ANEG_STATE_COMPLETE_ACK_INIT:
5291 if (ap->rxconfig & ANEG_CFG_INVAL) {
5292 ret = ANEG_FAILED;
5293 break;
5294 }
5295 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
5296 MR_LP_ADV_HALF_DUPLEX |
5297 MR_LP_ADV_SYM_PAUSE |
5298 MR_LP_ADV_ASYM_PAUSE |
5299 MR_LP_ADV_REMOTE_FAULT1 |
5300 MR_LP_ADV_REMOTE_FAULT2 |
5301 MR_LP_ADV_NEXT_PAGE |
5302 MR_TOGGLE_RX |
5303 MR_NP_RX);
5304 if (ap->rxconfig & ANEG_CFG_FD)
5305 ap->flags |= MR_LP_ADV_FULL_DUPLEX;
5306 if (ap->rxconfig & ANEG_CFG_HD)
5307 ap->flags |= MR_LP_ADV_HALF_DUPLEX;
5308 if (ap->rxconfig & ANEG_CFG_PS1)
5309 ap->flags |= MR_LP_ADV_SYM_PAUSE;
5310 if (ap->rxconfig & ANEG_CFG_PS2)
5311 ap->flags |= MR_LP_ADV_ASYM_PAUSE;
5312 if (ap->rxconfig & ANEG_CFG_RF1)
5313 ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
5314 if (ap->rxconfig & ANEG_CFG_RF2)
5315 ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
5316 if (ap->rxconfig & ANEG_CFG_NP)
5317 ap->flags |= MR_LP_ADV_NEXT_PAGE;
5318
5319 ap->link_time = ap->cur_time;
5320
5321 ap->flags ^= (MR_TOGGLE_TX);
5322 if (ap->rxconfig & 0x0008)
5323 ap->flags |= MR_TOGGLE_RX;
5324 if (ap->rxconfig & ANEG_CFG_NP)
5325 ap->flags |= MR_NP_RX;
5326 ap->flags |= MR_PAGE_RX;
5327
5328 ap->state = ANEG_STATE_COMPLETE_ACK;
5329 ret = ANEG_TIMER_ENAB;
5330 break;
5331
5332 case ANEG_STATE_COMPLETE_ACK:
5333 if (ap->ability_match != 0 &&
5334 ap->rxconfig == 0) {
5335 ap->state = ANEG_STATE_AN_ENABLE;
5336 break;
5337 }
5338 delta = ap->cur_time - ap->link_time;
5339 if (delta > ANEG_STATE_SETTLE_TIME) {
5340 if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
5341 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
5342 } else {
5343 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
5344 !(ap->flags & MR_NP_RX)) {
5345 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
5346 } else {
5347 ret = ANEG_FAILED;
5348 }
5349 }
5350 }
5351 break;
5352
5353 case ANEG_STATE_IDLE_DETECT_INIT:
5354 ap->link_time = ap->cur_time;
5355 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
5356 tw32_f(MAC_MODE, tp->mac_mode);
5357 udelay(40);
5358
5359 ap->state = ANEG_STATE_IDLE_DETECT;
5360 ret = ANEG_TIMER_ENAB;
5361 break;
5362
5363 case ANEG_STATE_IDLE_DETECT:
5364 if (ap->ability_match != 0 &&
5365 ap->rxconfig == 0) {
5366 ap->state = ANEG_STATE_AN_ENABLE;
5367 break;
5368 }
5369 delta = ap->cur_time - ap->link_time;
5370 if (delta > ANEG_STATE_SETTLE_TIME) {
5371 /* XXX another gem from the Broadcom driver :( */
5372 ap->state = ANEG_STATE_LINK_OK;
5373 }
5374 break;
5375
5376 case ANEG_STATE_LINK_OK:
5377 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
5378 ret = ANEG_DONE;
5379 break;
5380
5381 case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
5382 /* ??? unimplemented */
5383 break;
5384
5385 case ANEG_STATE_NEXT_PAGE_WAIT:
5386 /* ??? unimplemented */
5387 break;
5388
5389 default:
5390 ret = ANEG_FAILED;
5391 break;
855e1111 5392 }
1da177e4
LT		 5393
5394 return ret;
5395}
5396
5be73b47 5397static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags)
1da177e4
LT		 5398{
5399 int res = 0;
5400 struct tg3_fiber_aneginfo aninfo;
5401 int status = ANEG_FAILED;
5402 unsigned int tick;
5403 u32 tmp;
5404
5405 tw32_f(MAC_TX_AUTO_NEG, 0);
5406
5407 tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
5408 tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
5409 udelay(40);
5410
5411 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
5412 udelay(40);
5413
5414 memset(&aninfo, 0, sizeof(aninfo));
5415 aninfo.flags |= MR_AN_ENABLE;
5416 aninfo.state = ANEG_STATE_UNKNOWN;
5417 aninfo.cur_time = 0;
5418 tick = 0;
5419 while (++tick < 195000) {
5420 status = tg3_fiber_aneg_smachine(tp, &aninfo);
5421 if (status == ANEG_DONE || status == ANEG_FAILED)
5422 break;
5423
5424 udelay(1);
5425 }
5426
5427 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
5428 tw32_f(MAC_MODE, tp->mac_mode);
5429 udelay(40);
5430
5be73b47
MC		 5431 *txflags = aninfo.txconfig;
5432 *rxflags = aninfo.flags;
1da177e4
LT		 5433
5434 if (status == ANEG_DONE &&
5435 (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
5436 MR_LP_ADV_FULL_DUPLEX)))
5437 res = 1;
5438
5439 return res;
5440}
5441
5442static void tg3_init_bcm8002(struct tg3 *tp)
5443{
5444 u32 mac_status = tr32(MAC_STATUS);
5445 int i;
5446
5447 /* Reset when initting first time or we have a link. */
63c3a66f 5448 if (tg3_flag(tp, INIT_COMPLETE) &&
1da177e4
LT		 5449 !(mac_status & MAC_STATUS_PCS_SYNCED))
5450 return;
5451
5452 /* Set PLL lock range. */
5453 tg3_writephy(tp, 0x16, 0x8007);
5454
5455 /* SW reset */
5456 tg3_writephy(tp, MII_BMCR, BMCR_RESET);
5457
5458 /* Wait for reset to complete. */
5459 /* XXX schedule_timeout() ... */
5460 for (i = 0; i < 500; i++)
5461 udelay(10);
5462
5463 /* Config mode; select PMA/Ch 1 regs. */
5464 tg3_writephy(tp, 0x10, 0x8411);
5465
5466 /* Enable auto-lock and comdet, select txclk for tx. */
5467 tg3_writephy(tp, 0x11, 0x0a10);
5468
5469 tg3_writephy(tp, 0x18, 0x00a0);
5470 tg3_writephy(tp, 0x16, 0x41ff);
5471
5472 /* Assert and deassert POR. */
5473 tg3_writephy(tp, 0x13, 0x0400);
5474 udelay(40);
5475 tg3_writephy(tp, 0x13, 0x0000);
5476
5477 tg3_writephy(tp, 0x11, 0x0a50);
5478 udelay(40);
5479 tg3_writephy(tp, 0x11, 0x0a10);
5480
5481 /* Wait for signal to stabilize */
5482 /* XXX schedule_timeout() ... */
5483 for (i = 0; i < 15000; i++)
5484 udelay(10);
5485
5486 /* Deselect the channel register so we can read the PHYID
5487 * later.
5488 */
5489 tg3_writephy(tp, 0x10, 0x8011);
5490}
5491
953c96e0 5492static bool tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
1da177e4 5493{
82cd3d11 5494 u16 flowctrl;
953c96e0 5495 bool current_link_up;
1da177e4
LT		 5496 u32 sg_dig_ctrl, sg_dig_status;
5497 u32 serdes_cfg, expected_sg_dig_ctrl;
5498 int workaround, port_a;
1da177e4
LT		 5499
5500 serdes_cfg = 0;
5501 expected_sg_dig_ctrl = 0;
5502 workaround = 0;
5503 port_a = 1;
953c96e0 5504 current_link_up = false;
1da177e4 5505
4153577a
JP		 5506 if (tg3_chip_rev_id(tp) != CHIPREV_ID_5704_A0 &&
5507 tg3_chip_rev_id(tp) != CHIPREV_ID_5704_A1) {
1da177e4
LT		 5508 workaround = 1;
5509 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
5510 port_a = 0;
5511
5512 /* preserve bits 0-11,13,14 for signal pre-emphasis */
5513 /* preserve bits 20-23 for voltage regulator */
5514 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
5515 }
5516
5517 sg_dig_ctrl = tr32(SG_DIG_CTRL);
5518
5519 if (tp->link_config.autoneg != AUTONEG_ENABLE) {
c98f6e3b 5520 if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) {
1da177e4
LT		 5521 if (workaround) {
5522 u32 val = serdes_cfg;
5523
5524 if (port_a)
5525 val |= 0xc010000;
5526 else
5527 val |= 0x4010000;
5528 tw32_f(MAC_SERDES_CFG, val);
5529 }
c98f6e3b
MC		 5530
5531 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
1da177e4
LT		 5532 }
5533 if (mac_status & MAC_STATUS_PCS_SYNCED) {
5534 tg3_setup_flow_control(tp, 0, 0);
953c96e0 5535 current_link_up = true;
1da177e4
LT		 5536 }
5537 goto out;
5538 }
5539
5540 /* Want auto-negotiation. */
c98f6e3b 5541 expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP;
1da177e4 5542
82cd3d11
MC		 5543 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
5544 if (flowctrl & ADVERTISE_1000XPAUSE)
5545 expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP;
5546 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
5547 expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE;
1da177e4
LT		 5548
5549 if (sg_dig_ctrl != expected_sg_dig_ctrl) {
f07e9af3 5550 if ((tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT) &&
3d3ebe74
MC		 5551 tp->serdes_counter &&
5552 ((mac_status & (MAC_STATUS_PCS_SYNCED |
5553 MAC_STATUS_RCVD_CFG)) ==
5554 MAC_STATUS_PCS_SYNCED)) {
5555 tp->serdes_counter--;
953c96e0 5556 current_link_up = true;
3d3ebe74
MC		 5557 goto out;
5558 }
5559restart_autoneg:
1da177e4
LT		 5560 if (workaround)
5561 tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
c98f6e3b 5562 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET);
1da177e4
LT		 5563 udelay(5);
5564 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
5565
3d3ebe74 5566 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
f07e9af3 5567 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
1da177e4
LT		 5568 } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
5569 MAC_STATUS_SIGNAL_DET)) {
3d3ebe74 5570 sg_dig_status = tr32(SG_DIG_STATUS);
1da177e4
LT		 5571 mac_status = tr32(MAC_STATUS);
5572
c98f6e3b 5573 if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) &&
1da177e4 5574 (mac_status & MAC_STATUS_PCS_SYNCED)) {
82cd3d11
MC		 5575 u32 local_adv = 0, remote_adv = 0;
5576
5577 if (sg_dig_ctrl & SG_DIG_PAUSE_CAP)
5578 local_adv |= ADVERTISE_1000XPAUSE;
5579 if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE)
5580 local_adv |= ADVERTISE_1000XPSE_ASYM;
1da177e4 5581
c98f6e3b 5582 if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE)
82cd3d11 5583 remote_adv |= LPA_1000XPAUSE;
c98f6e3b 5584 if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE)
82cd3d11 5585 remote_adv |= LPA_1000XPAUSE_ASYM;
1da177e4 5586
859edb26
MC		 5587 tp->link_config.rmt_adv =
5588 mii_adv_to_ethtool_adv_x(remote_adv);
5589
1da177e4 5590 tg3_setup_flow_control(tp, local_adv, remote_adv);
953c96e0 5591 current_link_up = true;
3d3ebe74 5592 tp->serdes_counter = 0;
f07e9af3 5593 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
c98f6e3b 5594 } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) {
3d3ebe74
MC		 5595 if (tp->serdes_counter)
5596 tp->serdes_counter--;
1da177e4
LT		 5597 else {
5598 if (workaround) {
5599 u32 val = serdes_cfg;
5600
5601 if (port_a)
5602 val |= 0xc010000;
5603 else
5604 val |= 0x4010000;
5605
5606 tw32_f(MAC_SERDES_CFG, val);
5607 }
5608
c98f6e3b 5609 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
1da177e4
LT		 5610 udelay(40);
5611
5612 /* Link parallel detection - link is up */
5613 /* only if we have PCS_SYNC and not */
5614 /* receiving config code words */
5615 mac_status = tr32(MAC_STATUS);
5616 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
5617 !(mac_status & MAC_STATUS_RCVD_CFG)) {
5618 tg3_setup_flow_control(tp, 0, 0);
953c96e0 5619 current_link_up = true;
f07e9af3
MC		 5620 tp->phy_flags |=
5621 TG3_PHYFLG_PARALLEL_DETECT;
3d3ebe74
MC		 5622 tp->serdes_counter =
5623 SERDES_PARALLEL_DET_TIMEOUT;
5624 } else
5625 goto restart_autoneg;
1da177e4
LT		 5626 }
5627 }
3d3ebe74
MC		 5628 } else {
5629 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
f07e9af3 5630 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
1da177e4
LT		 5631 }
5632
5633out:
5634 return current_link_up;
5635}
5636
953c96e0 5637static bool tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
1da177e4 5638{
953c96e0 5639 bool current_link_up = false;
1da177e4 5640
5cf64b8a 5641 if (!(mac_status & MAC_STATUS_PCS_SYNCED))
1da177e4 5642 goto out;
1da177e4
LT		 5643
5644 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
5be73b47 5645 u32 txflags, rxflags;
1da177e4 5646 int i;
6aa20a22 5647
5be73b47
MC		 5648 if (fiber_autoneg(tp, &txflags, &rxflags)) {
5649 u32 local_adv = 0, remote_adv = 0;
1da177e4 5650
5be73b47
MC		 5651 if (txflags & ANEG_CFG_PS1)
5652 local_adv |= ADVERTISE_1000XPAUSE;
5653 if (txflags & ANEG_CFG_PS2)
5654 local_adv |= ADVERTISE_1000XPSE_ASYM;
5655
5656 if (rxflags & MR_LP_ADV_SYM_PAUSE)
5657 remote_adv |= LPA_1000XPAUSE;
5658 if (rxflags & MR_LP_ADV_ASYM_PAUSE)
5659 remote_adv |= LPA_1000XPAUSE_ASYM;
1da177e4 5660
859edb26
MC		 5661 tp->link_config.rmt_adv =
5662 mii_adv_to_ethtool_adv_x(remote_adv);
5663
1da177e4
LT		 5664 tg3_setup_flow_control(tp, local_adv, remote_adv);
5665
953c96e0 5666 current_link_up = true;
1da177e4
LT		 5667 }
5668 for (i = 0; i < 30; i++) {
5669 udelay(20);
5670 tw32_f(MAC_STATUS,
5671 (MAC_STATUS_SYNC_CHANGED |
5672 MAC_STATUS_CFG_CHANGED));
5673 udelay(40);
5674 if ((tr32(MAC_STATUS) &
5675 (MAC_STATUS_SYNC_CHANGED |
5676 MAC_STATUS_CFG_CHANGED)) == 0)
5677 break;
5678 }
5679
5680 mac_status = tr32(MAC_STATUS);
953c96e0 5681 if (!current_link_up &&
1da177e4
LT		 5682 (mac_status & MAC_STATUS_PCS_SYNCED) &&
5683 !(mac_status & MAC_STATUS_RCVD_CFG))
953c96e0 5684 current_link_up = true;
1da177e4 5685 } else {
5be73b47
MC		 5686 tg3_setup_flow_control(tp, 0, 0);
5687
1da177e4 5688 /* Forcing 1000FD link up. */
953c96e0 5689 current_link_up = true;
1da177e4
LT		 5690
5691 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
5692 udelay(40);
e8f3f6ca
MC		 5693
5694 tw32_f(MAC_MODE, tp->mac_mode);
5695 udelay(40);
1da177e4
LT		 5696 }
5697
5698out:
5699 return current_link_up;
5700}
5701
953c96e0 5702static int tg3_setup_fiber_phy(struct tg3 *tp, bool force_reset)
1da177e4
LT		 5703{
5704 u32 orig_pause_cfg;
5705 u16 orig_active_speed;
5706 u8 orig_active_duplex;
5707 u32 mac_status;
953c96e0 5708 bool current_link_up;
1da177e4
LT		 5709 int i;
5710
8d018621 5711 orig_pause_cfg = tp->link_config.active_flowctrl;
1da177e4
LT		 5712 orig_active_speed = tp->link_config.active_speed;
5713 orig_active_duplex = tp->link_config.active_duplex;
5714
63c3a66f 5715 if (!tg3_flag(tp, HW_AUTONEG) &&
f4a46d1f 5716 tp->link_up &&
63c3a66f 5717 tg3_flag(tp, INIT_COMPLETE)) {
1da177e4
LT		 5718 mac_status = tr32(MAC_STATUS);
5719 mac_status &= (MAC_STATUS_PCS_SYNCED |
5720 MAC_STATUS_SIGNAL_DET |
5721 MAC_STATUS_CFG_CHANGED |
5722 MAC_STATUS_RCVD_CFG);
5723 if (mac_status == (MAC_STATUS_PCS_SYNCED |
5724 MAC_STATUS_SIGNAL_DET)) {
5725 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
5726 MAC_STATUS_CFG_CHANGED));
5727 return 0;
5728 }
5729 }
5730
5731 tw32_f(MAC_TX_AUTO_NEG, 0);
5732
5733 tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
5734 tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
5735 tw32_f(MAC_MODE, tp->mac_mode);
5736 udelay(40);
5737
79eb6904 5738 if (tp->phy_id == TG3_PHY_ID_BCM8002)
1da177e4
LT		 5739 tg3_init_bcm8002(tp);
5740
5741 /* Enable link change event even when serdes polling. */
5742 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
5743 udelay(40);
5744
953c96e0 5745 current_link_up = false;
859edb26 5746 tp->link_config.rmt_adv = 0;
1da177e4
LT		 5747 mac_status = tr32(MAC_STATUS);
5748
63c3a66f 5749 if (tg3_flag(tp, HW_AUTONEG))
1da177e4
LT		 5750 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
5751 else
5752 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
5753
898a56f8 5754 tp->napi[0].hw_status->status =
1da177e4 5755 (SD_STATUS_UPDATED |
898a56f8 5756 (tp->napi[0].hw_status->status & ~SD_STATUS_LINK_CHG));
1da177e4
LT		 5757
5758 for (i = 0; i < 100; i++) {
5759 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
5760 MAC_STATUS_CFG_CHANGED));
5761 udelay(5);
5762 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
3d3ebe74
MC		 5763 MAC_STATUS_CFG_CHANGED |
5764 MAC_STATUS_LNKSTATE_CHANGED)) == 0)
1da177e4
LT		 5765 break;
5766 }
5767
5768 mac_status = tr32(MAC_STATUS);
5769 if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
953c96e0 5770 current_link_up = false;
3d3ebe74
MC		 5771 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
5772 tp->serdes_counter == 0) {
1da177e4
LT		 5773 tw32_f(MAC_MODE, (tp->mac_mode |
5774 MAC_MODE_SEND_CONFIGS));
5775 udelay(1);
5776 tw32_f(MAC_MODE, tp->mac_mode);
5777 }
5778 }
5779
953c96e0 5780 if (current_link_up) {
1da177e4
LT		 5781 tp->link_config.active_speed = SPEED_1000;
5782 tp->link_config.active_duplex = DUPLEX_FULL;
5783 tw32(MAC_LED_CTRL, (tp->led_ctrl |
5784 LED_CTRL_LNKLED_OVERRIDE |
5785 LED_CTRL_1000MBPS_ON));
5786 } else {
e740522e
MC		 5787 tp->link_config.active_speed = SPEED_UNKNOWN;
5788 tp->link_config.active_duplex = DUPLEX_UNKNOWN;
1da177e4
LT		 5789 tw32(MAC_LED_CTRL, (tp->led_ctrl |
5790 LED_CTRL_LNKLED_OVERRIDE |
5791 LED_CTRL_TRAFFIC_OVERRIDE));
5792 }
5793
f4a46d1f 5794 if (!tg3_test_and_report_link_chg(tp, current_link_up)) {
8d018621 5795 u32 now_pause_cfg = tp->link_config.active_flowctrl;
1da177e4
LT		 5796 if (orig_pause_cfg != now_pause_cfg ||
5797 orig_active_speed != tp->link_config.active_speed ||
5798 orig_active_duplex != tp->link_config.active_duplex)
5799 tg3_link_report(tp);
5800 }
5801
5802 return 0;
5803}
5804
953c96e0 5805static int tg3_setup_fiber_mii_phy(struct tg3 *tp, bool force_reset)
747e8f8b 5806{
953c96e0 5807 int err = 0;
747e8f8b 5808 u32 bmsr, bmcr;
85730a63
MC		 5809 u16 current_speed = SPEED_UNKNOWN;
5810 u8 current_duplex = DUPLEX_UNKNOWN;
953c96e0 5811 bool current_link_up = false;
85730a63
MC		 5812 u32 local_adv, remote_adv, sgsr;
5813
5814 if ((tg3_asic_rev(tp) == ASIC_REV_5719 ||
5815 tg3_asic_rev(tp) == ASIC_REV_5720) &&
5816 !tg3_readphy(tp, SERDES_TG3_1000X_STATUS, &sgsr) &&
5817 (sgsr & SERDES_TG3_SGMII_MODE)) {
5818
5819 if (force_reset)
5820 tg3_phy_reset(tp);
5821
5822 tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
5823
5824 if (!(sgsr & SERDES_TG3_LINK_UP)) {
5825 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
5826 } else {
953c96e0 5827 current_link_up = true;
85730a63
MC		 5828 if (sgsr & SERDES_TG3_SPEED_1000) {
5829 current_speed = SPEED_1000;
5830 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
5831 } else if (sgsr & SERDES_TG3_SPEED_100) {
5832 current_speed = SPEED_100;
5833 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
5834 } else {
5835 current_speed = SPEED_10;
5836 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
5837 }
5838
5839 if (sgsr & SERDES_TG3_FULL_DUPLEX)
5840 current_duplex = DUPLEX_FULL;
5841 else
5842 current_duplex = DUPLEX_HALF;
5843 }
5844
5845 tw32_f(MAC_MODE, tp->mac_mode);
5846 udelay(40);
5847
5848 tg3_clear_mac_status(tp);
5849
5850 goto fiber_setup_done;
5851 }
747e8f8b
MC		 5852
5853 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
5854 tw32_f(MAC_MODE, tp->mac_mode);
5855 udelay(40);
5856
3310e248 5857 tg3_clear_mac_status(tp);
747e8f8b
MC		 5858
5859 if (force_reset)
5860 tg3_phy_reset(tp);
5861
859edb26 5862 tp->link_config.rmt_adv = 0;
747e8f8b
MC		 5863
5864 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
5865 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4153577a 5866 if (tg3_asic_rev(tp) == ASIC_REV_5714) {
d4d2c558
MC		 5867 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
5868 bmsr |= BMSR_LSTATUS;
5869 else
5870 bmsr &= ~BMSR_LSTATUS;
5871 }
747e8f8b
MC		 5872
5873 err |= tg3_readphy(tp, MII_BMCR, &bmcr);
5874
5875 if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
f07e9af3 5876 (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) {
747e8f8b
MC		 5877 /* do nothing, just check for link up at the end */
5878 } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
28011cf1 5879 u32 adv, newadv;
747e8f8b
MC		 5880
5881 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
28011cf1
MC		 5882 newadv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
5883 ADVERTISE_1000XPAUSE |
5884 ADVERTISE_1000XPSE_ASYM |
5885 ADVERTISE_SLCT);
747e8f8b 5886
28011cf1 5887 newadv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
37f07023 5888 newadv |= ethtool_adv_to_mii_adv_x(tp->link_config.advertising);
747e8f8b 5889
28011cf1
MC		 5890 if ((newadv != adv) || !(bmcr & BMCR_ANENABLE)) {
5891 tg3_writephy(tp, MII_ADVERTISE, newadv);
747e8f8b
MC		 5892 bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
5893 tg3_writephy(tp, MII_BMCR, bmcr);
5894
5895 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3d3ebe74 5896 tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
f07e9af3 5897 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
747e8f8b
MC		 5898
5899 return err;
5900 }
5901 } else {
5902 u32 new_bmcr;
5903
5904 bmcr &= ~BMCR_SPEED1000;
5905 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
5906
5907 if (tp->link_config.duplex == DUPLEX_FULL)
5908 new_bmcr |= BMCR_FULLDPLX;
5909
5910 if (new_bmcr != bmcr) {
5911 /* BMCR_SPEED1000 is a reserved bit that needs
5912 * to be set on write.
5913 */
5914 new_bmcr |= BMCR_SPEED1000;
5915
5916 /* Force a linkdown */
f4a46d1f 5917 if (tp->link_up) {
747e8f8b
MC		 5918 u32 adv;
5919
5920 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
5921 adv &= ~(ADVERTISE_1000XFULL |
5922 ADVERTISE_1000XHALF |
5923 ADVERTISE_SLCT);
5924 tg3_writephy(tp, MII_ADVERTISE, adv);
5925 tg3_writephy(tp, MII_BMCR, bmcr |
5926 BMCR_ANRESTART |
5927 BMCR_ANENABLE);
5928 udelay(10);
f4a46d1f 5929 tg3_carrier_off(tp);
747e8f8b
MC		 5930 }
5931 tg3_writephy(tp, MII_BMCR, new_bmcr);
5932 bmcr = new_bmcr;
5933 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
5934 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4153577a 5935 if (tg3_asic_rev(tp) == ASIC_REV_5714) {
d4d2c558
MC		 5936 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
5937 bmsr |= BMSR_LSTATUS;
5938 else
5939 bmsr &= ~BMSR_LSTATUS;
5940 }
f07e9af3 5941 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
747e8f8b
MC		 5942 }
5943 }
5944
5945 if (bmsr & BMSR_LSTATUS) {
5946 current_speed = SPEED_1000;
953c96e0 5947 current_link_up = true;
747e8f8b
MC		 5948 if (bmcr & BMCR_FULLDPLX)
5949 current_duplex = DUPLEX_FULL;
5950 else
5951 current_duplex = DUPLEX_HALF;
5952
ef167e27
MC		 5953 local_adv = 0;
5954 remote_adv = 0;
5955
747e8f8b 5956 if (bmcr & BMCR_ANENABLE) {
ef167e27 5957 u32 common;
747e8f8b
MC		 5958
5959 err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
5960 err |= tg3_readphy(tp, MII_LPA, &remote_adv);
5961 common = local_adv & remote_adv;
5962 if (common & (ADVERTISE_1000XHALF |
5963 ADVERTISE_1000XFULL)) {
5964 if (common & ADVERTISE_1000XFULL)
5965 current_duplex = DUPLEX_FULL;
5966 else
5967 current_duplex = DUPLEX_HALF;
859edb26
MC		 5968
5969 tp->link_config.rmt_adv =
5970 mii_adv_to_ethtool_adv_x(remote_adv);
63c3a66f 5971 } else if (!tg3_flag(tp, 5780_CLASS)) {
57d8b880 5972 /* Link is up via parallel detect */
859a5887 5973 } else {
953c96e0 5974 current_link_up = false;
859a5887 5975 }
747e8f8b
MC		 5976 }
5977 }
5978
85730a63 5979fiber_setup_done:
953c96e0 5980 if (current_link_up && current_duplex == DUPLEX_FULL)
ef167e27
MC		 5981 tg3_setup_flow_control(tp, local_adv, remote_adv);
5982
747e8f8b
MC		 5983 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
5984 if (tp->link_config.active_duplex == DUPLEX_HALF)
5985 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
5986
5987 tw32_f(MAC_MODE, tp->mac_mode);
5988 udelay(40);
5989
5990 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
5991
5992 tp->link_config.active_speed = current_speed;
5993 tp->link_config.active_duplex = current_duplex;
5994
f4a46d1f 5995 tg3_test_and_report_link_chg(tp, current_link_up);
747e8f8b
MC		 5996 return err;
5997}
5998
5999static void tg3_serdes_parallel_detect(struct tg3 *tp)
6000{
3d3ebe74 6001 if (tp->serdes_counter) {
747e8f8b 6002 /* Give autoneg time to complete. */
3d3ebe74 6003 tp->serdes_counter--;
747e8f8b
MC		 6004 return;
6005 }
c6cdf436 6006
f4a46d1f 6007 if (!tp->link_up &&
747e8f8b
MC		 6008 (tp->link_config.autoneg == AUTONEG_ENABLE)) {
6009 u32 bmcr;
6010
6011 tg3_readphy(tp, MII_BMCR, &bmcr);
6012 if (bmcr & BMCR_ANENABLE) {
6013 u32 phy1, phy2;
6014
6015 /* Select shadow register 0x1f */
f08aa1a8
MC		 6016 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x7c00);
6017 tg3_readphy(tp, MII_TG3_MISC_SHDW, &phy1);
747e8f8b
MC		 6018
6019 /* Select expansion interrupt status register */
f08aa1a8
MC		 6020 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
6021 MII_TG3_DSP_EXP1_INT_STAT);
6022 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
6023 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
747e8f8b
MC		 6024
6025 if ((phy1 & 0x10) && !(phy2 & 0x20)) {
6026 /* We have signal detect and not receiving
6027 * config code words, link is up by parallel
6028 * detection.
6029 */
6030
6031 bmcr &= ~BMCR_ANENABLE;
6032 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
6033 tg3_writephy(tp, MII_BMCR, bmcr);
f07e9af3 6034 tp->phy_flags |= TG3_PHYFLG_PARALLEL_DETECT;
747e8f8b
MC		 6035 }
6036 }
f4a46d1f 6037 } else if (tp->link_up &&
859a5887 6038 (tp->link_config.autoneg == AUTONEG_ENABLE) &&
f07e9af3 6039 (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) {
747e8f8b
MC		 6040 u32 phy2;
6041
6042 /* Select expansion interrupt status register */
f08aa1a8
MC		 6043 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
6044 MII_TG3_DSP_EXP1_INT_STAT);
6045 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
747e8f8b
MC		 6046 if (phy2 & 0x20) {
6047 u32 bmcr;
6048
6049 /* Config code words received, turn on autoneg. */
6050 tg3_readphy(tp, MII_BMCR, &bmcr);
6051 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
6052
f07e9af3 6053 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
747e8f8b
MC		 6054
6055 }
6056 }
6057}
6058
953c96e0 6059static int tg3_setup_phy(struct tg3 *tp, bool force_reset)
1da177e4 6060{
f2096f94 6061 u32 val;
1da177e4
LT		 6062 int err;
6063
f07e9af3 6064 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
1da177e4 6065 err = tg3_setup_fiber_phy(tp, force_reset);
f07e9af3 6066 else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
747e8f8b 6067 err = tg3_setup_fiber_mii_phy(tp, force_reset);
859a5887 6068 else
1da177e4 6069 err = tg3_setup_copper_phy(tp, force_reset);
1da177e4 6070
4153577a 6071 if (tg3_chip_rev(tp) == CHIPREV_5784_AX) {
f2096f94 6072 u32 scale;
aa6c91fe
MC		 6073
6074 val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK;
6075 if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5)
6076 scale = 65;
6077 else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25)
6078 scale = 6;
6079 else
6080 scale = 12;
6081
6082 val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK;
6083 val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT);
6084 tw32(GRC_MISC_CFG, val);
6085 }
6086
f2096f94
MC		 6087 val = (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
6088 (6 << TX_LENGTHS_IPG_SHIFT);
4153577a
JP		 6089 if (tg3_asic_rev(tp) == ASIC_REV_5720 ||
6090 tg3_asic_rev(tp) == ASIC_REV_5762)
f2096f94
MC		 6091 val |= tr32(MAC_TX_LENGTHS) &
6092 (TX_LENGTHS_JMB_FRM_LEN_MSK |
6093 TX_LENGTHS_CNT_DWN_VAL_MSK);
6094
1da177e4
LT		 6095 if (tp->link_config.active_speed == SPEED_1000 &&
6096 tp->link_config.active_duplex == DUPLEX_HALF)
f2096f94
MC		 6097 tw32(MAC_TX_LENGTHS, val |
6098 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT));
1da177e4 6099 else
f2096f94
MC		 6100 tw32(MAC_TX_LENGTHS, val |
6101 (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
1da177e4 6102
63c3a66f 6103 if (!tg3_flag(tp, 5705_PLUS)) {
f4a46d1f 6104 if (tp->link_up) {
1da177e4 6105 tw32(HOSTCC_STAT_COAL_TICKS,
15f9850d 6106 tp->coal.stats_block_coalesce_usecs);
1da177e4
LT		 6107 } else {
6108 tw32(HOSTCC_STAT_COAL_TICKS, 0);
6109 }
6110 }
6111
63c3a66f 6112 if (tg3_flag(tp, ASPM_WORKAROUND)) {
f2096f94 6113 val = tr32(PCIE_PWR_MGMT_THRESH);
f4a46d1f 6114 if (!tp->link_up)
8ed5d97e
MC		 6115 val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
6116 tp->pwrmgmt_thresh;
6117 else
6118 val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
6119 tw32(PCIE_PWR_MGMT_THRESH, val);
6120 }
6121
1da177e4
LT		 6122 return err;
6123}
6124
7d41e49a
MC		 6125/* tp->lock must be held */
6126static u64 tg3_refclk_read(struct tg3 *tp)
6127{
6128 u64 stamp = tr32(TG3_EAV_REF_CLCK_LSB);
6129 return stamp | (u64)tr32(TG3_EAV_REF_CLCK_MSB) << 32;
6130}
6131
be947307
MC		 6132/* tp->lock must be held */
6133static void tg3_refclk_write(struct tg3 *tp, u64 newval)
6134{
92e6457d
NS		 6135 u32 clock_ctl = tr32(TG3_EAV_REF_CLCK_CTL);
6136
6137 tw32(TG3_EAV_REF_CLCK_CTL, clock_ctl | TG3_EAV_REF_CLCK_CTL_STOP);
be947307
MC		 6138 tw32(TG3_EAV_REF_CLCK_LSB, newval & 0xffffffff);
6139 tw32(TG3_EAV_REF_CLCK_MSB, newval >> 32);
92e6457d 6140 tw32_f(TG3_EAV_REF_CLCK_CTL, clock_ctl | TG3_EAV_REF_CLCK_CTL_RESUME);
be947307
MC		 6141}
6142
7d41e49a
MC		 6143static inline void tg3_full_lock(struct tg3 *tp, int irq_sync);
6144static inline void tg3_full_unlock(struct tg3 *tp);
6145static int tg3_get_ts_info(struct net_device *dev, struct ethtool_ts_info *info)
6146{
6147 struct tg3 *tp = netdev_priv(dev);
6148
6149 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE |
6150 SOF_TIMESTAMPING_RX_SOFTWARE |
f233a976
FL		 6151 SOF_TIMESTAMPING_SOFTWARE;
6152
6153 if (tg3_flag(tp, PTP_CAPABLE)) {
32e19272 6154 info->so_timestamping |= SOF_TIMESTAMPING_TX_HARDWARE |
f233a976
FL		 6155 SOF_TIMESTAMPING_RX_HARDWARE |
6156 SOF_TIMESTAMPING_RAW_HARDWARE;
6157 }
7d41e49a
MC		 6158
6159 if (tp->ptp_clock)
6160 info->phc_index = ptp_clock_index(tp->ptp_clock);
6161 else
6162 info->phc_index = -1;
6163
6164 info->tx_types = (1 << HWTSTAMP_TX_OFF) | (1 << HWTSTAMP_TX_ON);
6165
6166 info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) |
6167 (1 << HWTSTAMP_FILTER_PTP_V1_L4_EVENT) |
6168 (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) |
6169 (1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT);
6170 return 0;
6171}
6172
6173static int tg3_ptp_adjfreq(struct ptp_clock_info *ptp, s32 ppb)
6174{
6175 struct tg3 *tp = container_of(ptp, struct tg3, ptp_info);
6176 bool neg_adj = false;
6177 u32 correction = 0;
6178
6179 if (ppb < 0) {
6180 neg_adj = true;
6181 ppb = -ppb;
6182 }
6183
6184 /* Frequency adjustment is performed using hardware with a 24 bit
6185 * accumulator and a programmable correction value. On each clk, the
6186 * correction value gets added to the accumulator and when it
6187 * overflows, the time counter is incremented/decremented.
6188 *
6189 * So conversion from ppb to correction value is
6190 * ppb * (1 << 24) / 1000000000
6191 */
6192 correction = div_u64((u64)ppb * (1 << 24), 1000000000ULL) &
6193 TG3_EAV_REF_CLK_CORRECT_MASK;
6194
6195 tg3_full_lock(tp, 0);
6196
6197 if (correction)
6198 tw32(TG3_EAV_REF_CLK_CORRECT_CTL,
6199 TG3_EAV_REF_CLK_CORRECT_EN |
6200 (neg_adj ? TG3_EAV_REF_CLK_CORRECT_NEG : 0) | correction);
6201 else
6202 tw32(TG3_EAV_REF_CLK_CORRECT_CTL, 0);
6203
6204 tg3_full_unlock(tp);
6205
6206 return 0;
6207}
6208
6209static int tg3_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta)
6210{
6211 struct tg3 *tp = container_of(ptp, struct tg3, ptp_info);
6212
6213 tg3_full_lock(tp, 0);
6214 tp->ptp_adjust += delta;
6215 tg3_full_unlock(tp);
6216
6217 return 0;
6218}
6219
6220static int tg3_ptp_gettime(struct ptp_clock_info *ptp, struct timespec *ts)
6221{
6222 u64 ns;
6223 u32 remainder;
6224 struct tg3 *tp = container_of(ptp, struct tg3, ptp_info);
6225
6226 tg3_full_lock(tp, 0);
6227 ns = tg3_refclk_read(tp);
6228 ns += tp->ptp_adjust;
6229 tg3_full_unlock(tp);
6230
6231 ts->tv_sec = div_u64_rem(ns, 1000000000, &remainder);
6232 ts->tv_nsec = remainder;
6233
6234 return 0;
6235}
6236
6237static int tg3_ptp_settime(struct ptp_clock_info *ptp,
6238 const struct timespec *ts)
6239{
6240 u64 ns;
6241 struct tg3 *tp = container_of(ptp, struct tg3, ptp_info);
6242
6243 ns = timespec_to_ns(ts);
6244
6245 tg3_full_lock(tp, 0);
6246 tg3_refclk_write(tp, ns);
6247 tp->ptp_adjust = 0;
6248 tg3_full_unlock(tp);
6249
6250 return 0;
6251}
6252
6253static int tg3_ptp_enable(struct ptp_clock_info *ptp,
6254 struct ptp_clock_request *rq, int on)
6255{
92e6457d
NS		 6256 struct tg3 *tp = container_of(ptp, struct tg3, ptp_info);
6257 u32 clock_ctl;
6258 int rval = 0;
6259
6260 switch (rq->type) {
6261 case PTP_CLK_REQ_PEROUT:
6262 if (rq->perout.index != 0)
6263 return -EINVAL;
6264
6265 tg3_full_lock(tp, 0);
6266 clock_ctl = tr32(TG3_EAV_REF_CLCK_CTL);
6267 clock_ctl &= ~TG3_EAV_CTL_TSYNC_GPIO_MASK;
6268
6269 if (on) {
6270 u64 nsec;
6271
6272 nsec = rq->perout.start.sec * 1000000000ULL +
6273 rq->perout.start.nsec;
6274
6275 if (rq->perout.period.sec || rq->perout.period.nsec) {
6276 netdev_warn(tp->dev,
6277 "Device supports only a one-shot timesync output, period must be 0\n");
6278 rval = -EINVAL;
6279 goto err_out;
6280 }
6281
6282 if (nsec & (1ULL << 63)) {
6283 netdev_warn(tp->dev,
6284 "Start value (nsec) is over limit. Maximum size of start is only 63 bits\n");
6285 rval = -EINVAL;
6286 goto err_out;
6287 }
6288
6289 tw32(TG3_EAV_WATCHDOG0_LSB, (nsec & 0xffffffff));
6290 tw32(TG3_EAV_WATCHDOG0_MSB,
6291 TG3_EAV_WATCHDOG0_EN |
6292 ((nsec >> 32) & TG3_EAV_WATCHDOG_MSB_MASK));
6293
6294 tw32(TG3_EAV_REF_CLCK_CTL,
6295 clock_ctl | TG3_EAV_CTL_TSYNC_WDOG0);
6296 } else {
6297 tw32(TG3_EAV_WATCHDOG0_MSB, 0);
6298 tw32(TG3_EAV_REF_CLCK_CTL, clock_ctl);
6299 }
6300
6301err_out:
6302 tg3_full_unlock(tp);
6303 return rval;
6304
6305 default:
6306 break;
6307 }
6308
7d41e49a
MC		 6309 return -EOPNOTSUPP;
6310}
6311
6312static const struct ptp_clock_info tg3_ptp_caps = {
6313 .owner = THIS_MODULE,
6314 .name = "tg3 clock",
6315 .max_adj = 250000000,
6316 .n_alarm = 0,
6317 .n_ext_ts = 0,
92e6457d 6318 .n_per_out = 1,
4986b4f0 6319 .n_pins = 0,
7d41e49a
MC		 6320 .pps = 0,
6321 .adjfreq = tg3_ptp_adjfreq,
6322 .adjtime = tg3_ptp_adjtime,
6323 .gettime = tg3_ptp_gettime,
6324 .settime = tg3_ptp_settime,
6325 .enable = tg3_ptp_enable,
6326};
6327
fb4ce8ad
MC		 6328static void tg3_hwclock_to_timestamp(struct tg3 *tp, u64 hwclock,
6329 struct skb_shared_hwtstamps *timestamp)
6330{
6331 memset(timestamp, 0, sizeof(struct skb_shared_hwtstamps));
6332 timestamp->hwtstamp = ns_to_ktime((hwclock & TG3_TSTAMP_MASK) +
6333 tp->ptp_adjust);
6334}
6335
be947307
MC		 6336/* tp->lock must be held */
6337static void tg3_ptp_init(struct tg3 *tp)
6338{
6339 if (!tg3_flag(tp, PTP_CAPABLE))
6340 return;
6341
6342 /* Initialize the hardware clock to the system time. */
6343 tg3_refclk_write(tp, ktime_to_ns(ktime_get_real()));
6344 tp->ptp_adjust = 0;
7d41e49a 6345 tp->ptp_info = tg3_ptp_caps;
be947307
MC		 6346}
6347
6348/* tp->lock must be held */
6349static void tg3_ptp_resume(struct tg3 *tp)
6350{
6351 if (!tg3_flag(tp, PTP_CAPABLE))
6352 return;
6353
6354 tg3_refclk_write(tp, ktime_to_ns(ktime_get_real()) + tp->ptp_adjust);
6355 tp->ptp_adjust = 0;
6356}
6357
6358static void tg3_ptp_fini(struct tg3 *tp)
6359{
6360 if (!tg3_flag(tp, PTP_CAPABLE) || !tp->ptp_clock)
6361 return;
6362
7d41e49a 6363 ptp_clock_unregister(tp->ptp_clock);
be947307
MC		 6364 tp->ptp_clock = NULL;
6365 tp->ptp_adjust = 0;
6366}
6367
66cfd1bd
MC		 6368static inline int tg3_irq_sync(struct tg3 *tp)
6369{
6370 return tp->irq_sync;
6371}
6372
97bd8e49
MC		 6373static inline void tg3_rd32_loop(struct tg3 *tp, u32 *dst, u32 off, u32 len)
6374{
6375 int i;
6376
6377 dst = (u32 *)((u8 *)dst + off);
6378 for (i = 0; i < len; i += sizeof(u32))
6379 *dst++ = tr32(off + i);
6380}
6381
6382static void tg3_dump_legacy_regs(struct tg3 *tp, u32 *regs)
6383{
6384 tg3_rd32_loop(tp, regs, TG3PCI_VENDOR, 0xb0);
6385 tg3_rd32_loop(tp, regs, MAILBOX_INTERRUPT_0, 0x200);
6386 tg3_rd32_loop(tp, regs, MAC_MODE, 0x4f0);
6387 tg3_rd32_loop(tp, regs, SNDDATAI_MODE, 0xe0);
6388 tg3_rd32_loop(tp, regs, SNDDATAC_MODE, 0x04);
6389 tg3_rd32_loop(tp, regs, SNDBDS_MODE, 0x80);
6390 tg3_rd32_loop(tp, regs, SNDBDI_MODE, 0x48);
6391 tg3_rd32_loop(tp, regs, SNDBDC_MODE, 0x04);
6392 tg3_rd32_loop(tp, regs, RCVLPC_MODE, 0x20);
6393 tg3_rd32_loop(tp, regs, RCVLPC_SELLST_BASE, 0x15c);
6394 tg3_rd32_loop(tp, regs, RCVDBDI_MODE, 0x0c);
6395 tg3_rd32_loop(tp, regs, RCVDBDI_JUMBO_BD, 0x3c);
6396 tg3_rd32_loop(tp, regs, RCVDBDI_BD_PROD_IDX_0, 0x44);
6397 tg3_rd32_loop(tp, regs, RCVDCC_MODE, 0x04);
6398 tg3_rd32_loop(tp, regs, RCVBDI_MODE, 0x20);
6399 tg3_rd32_loop(tp, regs, RCVCC_MODE, 0x14);
6400 tg3_rd32_loop(tp, regs, RCVLSC_MODE, 0x08);
6401 tg3_rd32_loop(tp, regs, MBFREE_MODE, 0x08);
6402 tg3_rd32_loop(tp, regs, HOSTCC_MODE, 0x100);
6403
63c3a66f 6404 if (tg3_flag(tp, SUPPORT_MSIX))
97bd8e49
MC		 6405 tg3_rd32_loop(tp, regs, HOSTCC_RXCOL_TICKS_VEC1, 0x180);
6406
6407 tg3_rd32_loop(tp, regs, MEMARB_MODE, 0x10);
6408 tg3_rd32_loop(tp, regs, BUFMGR_MODE, 0x58);
6409 tg3_rd32_loop(tp, regs, RDMAC_MODE, 0x08);
6410 tg3_rd32_loop(tp, regs, WDMAC_MODE, 0x08);
6411 tg3_rd32_loop(tp, regs, RX_CPU_MODE, 0x04);
6412 tg3_rd32_loop(tp, regs, RX_CPU_STATE, 0x04);
6413 tg3_rd32_loop(tp, regs, RX_CPU_PGMCTR, 0x04);
6414 tg3_rd32_loop(tp, regs, RX_CPU_HWBKPT, 0x04);
6415
63c3a66f 6416 if (!tg3_flag(tp, 5705_PLUS)) {
97bd8e49
MC		 6417 tg3_rd32_loop(tp, regs, TX_CPU_MODE, 0x04);
6418 tg3_rd32_loop(tp, regs, TX_CPU_STATE, 0x04);
6419 tg3_rd32_loop(tp, regs, TX_CPU_PGMCTR, 0x04);
6420 }
6421
6422 tg3_rd32_loop(tp, regs, GRCMBOX_INTERRUPT_0, 0x110);
6423 tg3_rd32_loop(tp, regs, FTQ_RESET, 0x120);
6424 tg3_rd32_loop(tp, regs, MSGINT_MODE, 0x0c);
6425 tg3_rd32_loop(tp, regs, DMAC_MODE, 0x04);
6426 tg3_rd32_loop(tp, regs, GRC_MODE, 0x4c);
6427
63c3a66f 6428 if (tg3_flag(tp, NVRAM))
97bd8e49
MC		 6429 tg3_rd32_loop(tp, regs, NVRAM_CMD, 0x24);
6430}
6431
6432static void tg3_dump_state(struct tg3 *tp)
6433{
6434 int i;
6435 u32 *regs;
6436
6437 regs = kzalloc(TG3_REG_BLK_SIZE, GFP_ATOMIC);
b2adaca9 6438 if (!regs)
97bd8e49 6439 return;
97bd8e49 6440
63c3a66f 6441 if (tg3_flag(tp, PCI_EXPRESS)) {
97bd8e49
MC		 6442 /* Read up to but not including private PCI registers */
6443 for (i = 0; i < TG3_PCIE_TLDLPL_PORT; i += sizeof(u32))
6444 regs[i / sizeof(u32)] = tr32(i);
6445 } else
6446 tg3_dump_legacy_regs(tp, regs);
6447
6448 for (i = 0; i < TG3_REG_BLK_SIZE / sizeof(u32); i += 4) {
6449 if (!regs[i + 0] && !regs[i + 1] &&
6450 !regs[i + 2] && !regs[i + 3])
6451 continue;
6452
6453 netdev_err(tp->dev, "0x%08x: 0x%08x, 0x%08x, 0x%08x, 0x%08x\n",
6454 i * 4,
6455 regs[i + 0], regs[i + 1], regs[i + 2], regs[i + 3]);
6456 }
6457
6458 kfree(regs);
6459
6460 for (i = 0; i < tp->irq_cnt; i++) {
6461 struct tg3_napi *tnapi = &tp->napi[i];
6462
6463 /* SW status block */
6464 netdev_err(tp->dev,
6465 "%d: Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n",
6466 i,
6467 tnapi->hw_status->status,
6468 tnapi->hw_status->status_tag,
6469 tnapi->hw_status->rx_jumbo_consumer,
6470 tnapi->hw_status->rx_consumer,
6471 tnapi->hw_status->rx_mini_consumer,
6472 tnapi->hw_status->idx[0].rx_producer,
6473 tnapi->hw_status->idx[0].tx_consumer);
6474
6475 netdev_err(tp->dev,
6476 "%d: NAPI info [%08x:%08x:(%04x:%04x:%04x):%04x:(%04x:%04x:%04x:%04x)]\n",
6477 i,
6478 tnapi->last_tag, tnapi->last_irq_tag,
6479 tnapi->tx_prod, tnapi->tx_cons, tnapi->tx_pending,
6480 tnapi->rx_rcb_ptr,
6481 tnapi->prodring.rx_std_prod_idx,
6482 tnapi->prodring.rx_std_cons_idx,
6483 tnapi->prodring.rx_jmb_prod_idx,
6484 tnapi->prodring.rx_jmb_cons_idx);
6485 }
6486}
6487
df3e6548
MC		 6488/* This is called whenever we suspect that the system chipset is re-
6489 * ordering the sequence of MMIO to the tx send mailbox. The symptom
6490 * is bogus tx completions. We try to recover by setting the
6491 * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
6492 * in the workqueue.
6493 */
6494static void tg3_tx_recover(struct tg3 *tp)
6495{
63c3a66f 6496 BUG_ON(tg3_flag(tp, MBOX_WRITE_REORDER) ||
df3e6548
MC		 6497 tp->write32_tx_mbox == tg3_write_indirect_mbox);
6498
5129c3a3
MC		 6499 netdev_warn(tp->dev,
6500 "The system may be re-ordering memory-mapped I/O "
6501 "cycles to the network device, attempting to recover. "
6502 "Please report the problem to the driver maintainer "
6503 "and include system chipset information.\n");
df3e6548 6504
63c3a66f 6505 tg3_flag_set(tp, TX_RECOVERY_PENDING);
df3e6548
MC		 6506}
6507
f3f3f27e 6508static inline u32 tg3_tx_avail(struct tg3_napi *tnapi)
1b2a7205 6509{
f65aac16
MC		 6510 /* Tell compiler to fetch tx indices from memory. */
6511 barrier();
f3f3f27e
MC		 6512 return tnapi->tx_pending -
6513 ((tnapi->tx_prod - tnapi->tx_cons) & (TG3_TX_RING_SIZE - 1));
1b2a7205
MC		 6514}
6515
1da177e4
LT		 6516/* Tigon3 never reports partial packet sends. So we do not
6517 * need special logic to handle SKBs that have not had all
6518 * of their frags sent yet, like SunGEM does.
6519 */
17375d25 6520static void tg3_tx(struct tg3_napi *tnapi)
1da177e4 6521{
17375d25 6522 struct tg3 *tp = tnapi->tp;
898a56f8 6523 u32 hw_idx = tnapi->hw_status->idx[0].tx_consumer;
f3f3f27e 6524 u32 sw_idx = tnapi->tx_cons;
fe5f5787
MC		 6525 struct netdev_queue *txq;
6526 int index = tnapi - tp->napi;
298376d3 6527 unsigned int pkts_compl = 0, bytes_compl = 0;
fe5f5787 6528
63c3a66f 6529 if (tg3_flag(tp, ENABLE_TSS))
fe5f5787
MC		 6530 index--;
6531
6532 txq = netdev_get_tx_queue(tp->dev, index);
1da177e4
LT		 6533
6534 while (sw_idx != hw_idx) {
df8944cf 6535 struct tg3_tx_ring_info *ri = &tnapi->tx_buffers[sw_idx];
1da177e4 6536 struct sk_buff *skb = ri->skb;
df3e6548
MC		 6537 int i, tx_bug = 0;
6538
6539 if (unlikely(skb == NULL)) {
6540 tg3_tx_recover(tp);
6541 return;
6542 }
1da177e4 6543
fb4ce8ad
MC		 6544 if (tnapi->tx_ring[sw_idx].len_flags & TXD_FLAG_HWTSTAMP) {
6545 struct skb_shared_hwtstamps timestamp;
6546 u64 hwclock = tr32(TG3_TX_TSTAMP_LSB);
6547 hwclock |= (u64)tr32(TG3_TX_TSTAMP_MSB) << 32;
6548
6549 tg3_hwclock_to_timestamp(tp, hwclock, &timestamp);
6550
6551 skb_tstamp_tx(skb, &timestamp);
6552 }
6553
f4188d8a 6554 pci_unmap_single(tp->pdev,
4e5e4f0d 6555 dma_unmap_addr(ri, mapping),
f4188d8a
AD		 6556 skb_headlen(skb),
6557 PCI_DMA_TODEVICE);
1da177e4
LT		 6558
6559 ri->skb = NULL;
6560
e01ee14d
MC		 6561 while (ri->fragmented) {
6562 ri->fragmented = false;
6563 sw_idx = NEXT_TX(sw_idx);
6564 ri = &tnapi->tx_buffers[sw_idx];
6565 }
6566
1da177e4
LT		 6567 sw_idx = NEXT_TX(sw_idx);
6568
6569 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
f3f3f27e 6570 ri = &tnapi->tx_buffers[sw_idx];
df3e6548
MC		 6571 if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
6572 tx_bug = 1;
f4188d8a
AD		 6573
6574 pci_unmap_page(tp->pdev,
4e5e4f0d 6575 dma_unmap_addr(ri, mapping),
9e903e08 6576 skb_frag_size(&skb_shinfo(skb)->frags[i]),
f4188d8a 6577 PCI_DMA_TODEVICE);
e01ee14d
MC		 6578
6579 while (ri->fragmented) {
6580 ri->fragmented = false;
6581 sw_idx = NEXT_TX(sw_idx);
6582 ri = &tnapi->tx_buffers[sw_idx];
6583 }
6584
1da177e4
LT		 6585 sw_idx = NEXT_TX(sw_idx);
6586 }
6587
298376d3
TH		 6588 pkts_compl++;
6589 bytes_compl += skb->len;
6590
497a27b9 6591 dev_kfree_skb_any(skb);
df3e6548
MC		 6592
6593 if (unlikely(tx_bug)) {
6594 tg3_tx_recover(tp);
6595 return;
6596 }
1da177e4
LT		 6597 }
6598
5cb917bc 6599 netdev_tx_completed_queue(txq, pkts_compl, bytes_compl);
298376d3 6600
f3f3f27e 6601 tnapi->tx_cons = sw_idx;
1da177e4 6602
1b2a7205
MC		 6603 /* Need to make the tx_cons update visible to tg3_start_xmit()
6604 * before checking for netif_queue_stopped(). Without the
6605 * memory barrier, there is a small possibility that tg3_start_xmit()
6606 * will miss it and cause the queue to be stopped forever.
6607 */
6608 smp_mb();
6609
fe5f5787 6610 if (unlikely(netif_tx_queue_stopped(txq) &&
f3f3f27e 6611 (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))) {
fe5f5787
MC		 6612 __netif_tx_lock(txq, smp_processor_id());
6613 if (netif_tx_queue_stopped(txq) &&
f3f3f27e 6614 (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))
fe5f5787
MC		 6615 netif_tx_wake_queue(txq);
6616 __netif_tx_unlock(txq);
51b91468 6617 }
1da177e4
LT		 6618}
6619
8d4057a9
ED		 6620static void tg3_frag_free(bool is_frag, void *data)
6621{
6622 if (is_frag)
6623 put_page(virt_to_head_page(data));
6624 else
6625 kfree(data);
6626}
6627
9205fd9c 6628static void tg3_rx_data_free(struct tg3 *tp, struct ring_info *ri, u32 map_sz)
2b2cdb65 6629{
8d4057a9
ED		 6630 unsigned int skb_size = SKB_DATA_ALIGN(map_sz + TG3_RX_OFFSET(tp)) +
6631 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
6632
9205fd9c 6633 if (!ri->data)
2b2cdb65
MC		 6634 return;
6635
4e5e4f0d 6636 pci_unmap_single(tp->pdev, dma_unmap_addr(ri, mapping),
2b2cdb65 6637 map_sz, PCI_DMA_FROMDEVICE);
a1e8b307 6638 tg3_frag_free(skb_size <= PAGE_SIZE, ri->data);
9205fd9c 6639 ri->data = NULL;
2b2cdb65
MC		 6640}
6641
8d4057a9 6642
1da177e4
LT		 6643/* Returns size of skb allocated or < 0 on error.
6644 *
6645 * We only need to fill in the address because the other members
6646 * of the RX descriptor are invariant, see tg3_init_rings.
6647 *
6648 * Note the purposeful assymetry of cpu vs. chip accesses. For
6649 * posting buffers we only dirty the first cache line of the RX
6650 * descriptor (containing the address). Whereas for the RX status
6651 * buffers the cpu only reads the last cacheline of the RX descriptor
6652 * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
6653 */
9205fd9c 6654static int tg3_alloc_rx_data(struct tg3 *tp, struct tg3_rx_prodring_set *tpr,
8d4057a9
ED		 6655 u32 opaque_key, u32 dest_idx_unmasked,
6656 unsigned int *frag_size)
1da177e4
LT		 6657{
6658 struct tg3_rx_buffer_desc *desc;
f94e290e 6659 struct ring_info *map;
9205fd9c 6660 u8 *data;
1da177e4 6661 dma_addr_t mapping;
9205fd9c 6662 int skb_size, data_size, dest_idx;
1da177e4 6663
1da177e4
LT		 6664 switch (opaque_key) {
6665 case RXD_OPAQUE_RING_STD:
2c49a44d 6666 dest_idx = dest_idx_unmasked & tp->rx_std_ring_mask;
21f581a5
MC		 6667 desc = &tpr->rx_std[dest_idx];
6668 map = &tpr->rx_std_buffers[dest_idx];
9205fd9c 6669 data_size = tp->rx_pkt_map_sz;
1da177e4
LT		 6670 break;
6671
6672 case RXD_OPAQUE_RING_JUMBO:
2c49a44d 6673 dest_idx = dest_idx_unmasked & tp->rx_jmb_ring_mask;
79ed5ac7 6674 desc = &tpr->rx_jmb[dest_idx].std;
21f581a5 6675 map = &tpr->rx_jmb_buffers[dest_idx];
9205fd9c 6676 data_size = TG3_RX_JMB_MAP_SZ;
1da177e4
LT		 6677 break;
6678
6679 default:
6680 return -EINVAL;
855e1111 6681 }
1da177e4
LT		 6682
6683 /* Do not overwrite any of the map or rp information
6684 * until we are sure we can commit to a new buffer.
6685 *
6686 * Callers depend upon this behavior and assume that
6687 * we leave everything unchanged if we fail.
6688 */
9205fd9c
ED		 6689 skb_size = SKB_DATA_ALIGN(data_size + TG3_RX_OFFSET(tp)) +
6690 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
a1e8b307
ED		 6691 if (skb_size <= PAGE_SIZE) {
6692 data = netdev_alloc_frag(skb_size);
6693 *frag_size = skb_size;
8d4057a9
ED		 6694 } else {
6695 data = kmalloc(skb_size, GFP_ATOMIC);
6696 *frag_size = 0;
6697 }
9205fd9c 6698 if (!data)
1da177e4
LT		 6699 return -ENOMEM;
6700
9205fd9c
ED		 6701 mapping = pci_map_single(tp->pdev,
6702 data + TG3_RX_OFFSET(tp),
6703 data_size,
1da177e4 6704 PCI_DMA_FROMDEVICE);
8d4057a9 6705 if (unlikely(pci_dma_mapping_error(tp->pdev, mapping))) {
a1e8b307 6706 tg3_frag_free(skb_size <= PAGE_SIZE, data);
a21771dd
MC		 6707 return -EIO;
6708 }
1da177e4 6709
9205fd9c 6710 map->data = data;
4e5e4f0d 6711 dma_unmap_addr_set(map, mapping, mapping);
1da177e4 6712
1da177e4
LT		 6713 desc->addr_hi = ((u64)mapping >> 32);
6714 desc->addr_lo = ((u64)mapping & 0xffffffff);
6715
9205fd9c 6716 return data_size;
1da177e4
LT		 6717}
6718
6719/* We only need to move over in the address because the other
6720 * members of the RX descriptor are invariant. See notes above
9205fd9c 6721 * tg3_alloc_rx_data for full details.
1da177e4 6722 */
a3896167
MC		 6723static void tg3_recycle_rx(struct tg3_napi *tnapi,
6724 struct tg3_rx_prodring_set *dpr,
6725 u32 opaque_key, int src_idx,
6726 u32 dest_idx_unmasked)
1da177e4 6727{
17375d25 6728 struct tg3 *tp = tnapi->tp;
1da177e4
LT		 6729 struct tg3_rx_buffer_desc *src_desc, *dest_desc;
6730 struct ring_info *src_map, *dest_map;
8fea32b9 6731 struct tg3_rx_prodring_set *spr = &tp->napi[0].prodring;
c6cdf436 6732 int dest_idx;
1da177e4
LT		 6733
6734 switch (opaque_key) {
6735 case RXD_OPAQUE_RING_STD:
2c49a44d 6736 dest_idx = dest_idx_unmasked & tp->rx_std_ring_mask;
a3896167
MC		 6737 dest_desc = &dpr->rx_std[dest_idx];
6738 dest_map = &dpr->rx_std_buffers[dest_idx];
6739 src_desc = &spr->rx_std[src_idx];
6740 src_map = &spr->rx_std_buffers[src_idx];
1da177e4
LT		 6741 break;
6742
6743 case RXD_OPAQUE_RING_JUMBO:
2c49a44d 6744 dest_idx = dest_idx_unmasked & tp->rx_jmb_ring_mask;
a3896167
MC		 6745 dest_desc = &dpr->rx_jmb[dest_idx].std;
6746 dest_map = &dpr->rx_jmb_buffers[dest_idx];
6747 src_desc = &spr->rx_jmb[src_idx].std;
6748 src_map = &spr->rx_jmb_buffers[src_idx];
1da177e4
LT		 6749 break;
6750
6751 default:
6752 return;
855e1111 6753 }
1da177e4 6754
9205fd9c 6755 dest_map->data = src_map->data;
4e5e4f0d
FT		 6756 dma_unmap_addr_set(dest_map, mapping,
6757 dma_unmap_addr(src_map, mapping));
1da177e4
LT		 6758 dest_desc->addr_hi = src_desc->addr_hi;
6759 dest_desc->addr_lo = src_desc->addr_lo;
e92967bf
MC		 6760
6761 /* Ensure that the update to the skb happens after the physical
6762 * addresses have been transferred to the new BD location.
6763 */
6764 smp_wmb();
6765
9205fd9c 6766 src_map->data = NULL;
1da177e4
LT		 6767}
6768
1da177e4
LT		 6769/* The RX ring scheme is composed of multiple rings which post fresh
6770 * buffers to the chip, and one special ring the chip uses to report
6771 * status back to the host.
6772 *
6773 * The special ring reports the status of received packets to the
6774 * host. The chip does not write into the original descriptor the
6775 * RX buffer was obtained from. The chip simply takes the original
6776 * descriptor as provided by the host, updates the status and length
6777 * field, then writes this into the next status ring entry.
6778 *
6779 * Each ring the host uses to post buffers to the chip is described
6780 * by a TG3_BDINFO entry in the chips SRAM area. When a packet arrives,
6781 * it is first placed into the on-chip ram. When the packet's length
6782 * is known, it walks down the TG3_BDINFO entries to select the ring.
6783 * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
6784 * which is within the range of the new packet's length is chosen.
6785 *
6786 * The "separate ring for rx status" scheme may sound queer, but it makes
6787 * sense from a cache coherency perspective. If only the host writes
6788 * to the buffer post rings, and only the chip writes to the rx status
6789 * rings, then cache lines never move beyond shared-modified state.
6790 * If both the host and chip were to write into the same ring, cache line
6791 * eviction could occur since both entities want it in an exclusive state.
6792 */
17375d25 6793static int tg3_rx(struct tg3_napi *tnapi, int budget)
1da177e4 6794{
17375d25 6795 struct tg3 *tp = tnapi->tp;
f92905de 6796 u32 work_mask, rx_std_posted = 0;
4361935a 6797 u32 std_prod_idx, jmb_prod_idx;
72334482 6798 u32 sw_idx = tnapi->rx_rcb_ptr;
483ba50b 6799 u16 hw_idx;
1da177e4 6800 int received;
8fea32b9 6801 struct tg3_rx_prodring_set *tpr = &tnapi->prodring;
1da177e4 6802
8d9d7cfc 6803 hw_idx = *(tnapi->rx_rcb_prod_idx);
1da177e4
LT		 6804 /*
6805 * We need to order the read of hw_idx and the read of
6806 * the opaque cookie.
6807 */
6808 rmb();
1da177e4
LT		 6809 work_mask = 0;
6810 received = 0;
4361935a
MC		 6811 std_prod_idx = tpr->rx_std_prod_idx;
6812 jmb_prod_idx = tpr->rx_jmb_prod_idx;
1da177e4 6813 while (sw_idx != hw_idx && budget > 0) {
afc081f8 6814 struct ring_info *ri;
72334482 6815 struct tg3_rx_buffer_desc *desc = &tnapi->rx_rcb[sw_idx];
1da177e4
LT		 6816 unsigned int len;
6817 struct sk_buff *skb;
6818 dma_addr_t dma_addr;
6819 u32 opaque_key, desc_idx, *post_ptr;
9205fd9c 6820 u8 *data;
fb4ce8ad 6821 u64 tstamp = 0;
1da177e4
LT		 6822
6823 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
6824 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
6825 if (opaque_key == RXD_OPAQUE_RING_STD) {
8fea32b9 6826 ri = &tp->napi[0].prodring.rx_std_buffers[desc_idx];
4e5e4f0d 6827 dma_addr = dma_unmap_addr(ri, mapping);
9205fd9c 6828 data = ri->data;
4361935a 6829 post_ptr = &std_prod_idx;
f92905de 6830 rx_std_posted++;
1da177e4 6831 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
8fea32b9 6832 ri = &tp->napi[0].prodring.rx_jmb_buffers[desc_idx];
4e5e4f0d 6833 dma_addr = dma_unmap_addr(ri, mapping);
9205fd9c 6834 data = ri->data;
4361935a 6835 post_ptr = &jmb_prod_idx;
21f581a5 6836 } else
1da177e4 6837 goto next_pkt_nopost;
1da177e4
LT		 6838
6839 work_mask |= opaque_key;
6840
d7b95315 6841 if (desc->err_vlan & RXD_ERR_MASK) {
1da177e4 6842 drop_it:
a3896167 6843 tg3_recycle_rx(tnapi, tpr, opaque_key,
1da177e4
LT		 6844 desc_idx, *post_ptr);
6845 drop_it_no_recycle:
6846 /* Other statistics kept track of by card. */
b0057c51 6847 tp->rx_dropped++;
1da177e4
LT		 6848 goto next_pkt;
6849 }
6850
9205fd9c 6851 prefetch(data + TG3_RX_OFFSET(tp));
ad829268
MC		 6852 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) -
6853 ETH_FCS_LEN;
1da177e4 6854
fb4ce8ad
MC		 6855 if ((desc->type_flags & RXD_FLAG_PTPSTAT_MASK) ==
6856 RXD_FLAG_PTPSTAT_PTPV1 ||
6857 (desc->type_flags & RXD_FLAG_PTPSTAT_MASK) ==
6858 RXD_FLAG_PTPSTAT_PTPV2) {
6859 tstamp = tr32(TG3_RX_TSTAMP_LSB);
6860 tstamp |= (u64)tr32(TG3_RX_TSTAMP_MSB) << 32;
6861 }
6862
d2757fc4 6863 if (len > TG3_RX_COPY_THRESH(tp)) {
1da177e4 6864 int skb_size;
8d4057a9 6865 unsigned int frag_size;
1da177e4 6866
9205fd9c 6867 skb_size = tg3_alloc_rx_data(tp, tpr, opaque_key,
8d4057a9 6868 *post_ptr, &frag_size);
1da177e4
LT		 6869 if (skb_size < 0)
6870 goto drop_it;
6871
287be12e 6872 pci_unmap_single(tp->pdev, dma_addr, skb_size,
1da177e4
LT		 6873 PCI_DMA_FROMDEVICE);
6874
9205fd9c 6875 /* Ensure that the update to the data happens
61e800cf
MC		 6876 * after the usage of the old DMA mapping.
6877 */
6878 smp_wmb();
6879
9205fd9c 6880 ri->data = NULL;
61e800cf 6881
85aec73d
IV		 6882 skb = build_skb(data, frag_size);
6883 if (!skb) {
6884 tg3_frag_free(frag_size != 0, data);
6885 goto drop_it_no_recycle;
6886 }
6887 skb_reserve(skb, TG3_RX_OFFSET(tp));
1da177e4 6888 } else {
a3896167 6889 tg3_recycle_rx(tnapi, tpr, opaque_key,
1da177e4
LT		 6890 desc_idx, *post_ptr);
6891
9205fd9c
ED		 6892 skb = netdev_alloc_skb(tp->dev,
6893 len + TG3_RAW_IP_ALIGN);
6894 if (skb == NULL)
1da177e4
LT		 6895 goto drop_it_no_recycle;
6896
9205fd9c 6897 skb_reserve(skb, TG3_RAW_IP_ALIGN);
1da177e4 6898 pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
9205fd9c
ED		 6899 memcpy(skb->data,
6900 data + TG3_RX_OFFSET(tp),
6901 len);
1da177e4 6902 pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
1da177e4
LT		 6903 }
6904
9205fd9c 6905 skb_put(skb, len);
fb4ce8ad
MC		 6906 if (tstamp)
6907 tg3_hwclock_to_timestamp(tp, tstamp,
6908 skb_hwtstamps(skb));
6909
dc668910 6910 if ((tp->dev->features & NETIF_F_RXCSUM) &&
1da177e4
LT		 6911 (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
6912 (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
6913 >> RXD_TCPCSUM_SHIFT) == 0xffff))
6914 skb->ip_summed = CHECKSUM_UNNECESSARY;
6915 else
bc8acf2c 6916 skb_checksum_none_assert(skb);
1da177e4
LT		 6917
6918 skb->protocol = eth_type_trans(skb, tp->dev);
f7b493e0
MC		 6919
6920 if (len > (tp->dev->mtu + ETH_HLEN) &&
6921 skb->protocol != htons(ETH_P_8021Q)) {
497a27b9 6922 dev_kfree_skb_any(skb);
b0057c51 6923 goto drop_it_no_recycle;
f7b493e0
MC		 6924 }
6925
9dc7a113 6926 if (desc->type_flags & RXD_FLAG_VLAN &&
bf933c80 6927 !(tp->rx_mode & RX_MODE_KEEP_VLAN_TAG))
86a9bad3 6928 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
bf933c80 6929 desc->err_vlan & RXD_VLAN_MASK);
9dc7a113 6930
bf933c80 6931 napi_gro_receive(&tnapi->napi, skb);
1da177e4 6932
1da177e4
LT		 6933 received++;
6934 budget--;
6935
6936next_pkt:
6937 (*post_ptr)++;
f92905de
MC		 6938
6939 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
2c49a44d
MC		 6940 tpr->rx_std_prod_idx = std_prod_idx &
6941 tp->rx_std_ring_mask;
86cfe4ff
MC		 6942 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
6943 tpr->rx_std_prod_idx);
f92905de
MC		 6944 work_mask &= ~RXD_OPAQUE_RING_STD;
6945 rx_std_posted = 0;
6946 }
1da177e4 6947next_pkt_nopost:
483ba50b 6948 sw_idx++;
7cb32cf2 6949 sw_idx &= tp->rx_ret_ring_mask;
52f6d697
MC		 6950
6951 /* Refresh hw_idx to see if there is new work */
6952 if (sw_idx == hw_idx) {
8d9d7cfc 6953 hw_idx = *(tnapi->rx_rcb_prod_idx);
52f6d697
MC		 6954 rmb();
6955 }
1da177e4
LT		 6956 }
6957
6958 /* ACK the status ring. */
72334482
MC		 6959 tnapi->rx_rcb_ptr = sw_idx;
6960 tw32_rx_mbox(tnapi->consmbox, sw_idx);
1da177e4
LT		 6961
6962 /* Refill RX ring(s). */
63c3a66f 6963 if (!tg3_flag(tp, ENABLE_RSS)) {
6541b806
MC		 6964 /* Sync BD data before updating mailbox */
6965 wmb();
6966
b196c7e4 6967 if (work_mask & RXD_OPAQUE_RING_STD) {
2c49a44d
MC		 6968 tpr->rx_std_prod_idx = std_prod_idx &
6969 tp->rx_std_ring_mask;
b196c7e4
MC		 6970 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
6971 tpr->rx_std_prod_idx);
6972 }
6973 if (work_mask & RXD_OPAQUE_RING_JUMBO) {
2c49a44d
MC		 6974 tpr->rx_jmb_prod_idx = jmb_prod_idx &
6975 tp->rx_jmb_ring_mask;
b196c7e4
MC		 6976 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
6977 tpr->rx_jmb_prod_idx);
6978 }
6979 mmiowb();
6980 } else if (work_mask) {
6981 /* rx_std_buffers[] and rx_jmb_buffers[] entries must be
6982 * updated before the producer indices can be updated.
6983 */
6984 smp_wmb();
6985
2c49a44d
MC		 6986 tpr->rx_std_prod_idx = std_prod_idx & tp->rx_std_ring_mask;
6987 tpr->rx_jmb_prod_idx = jmb_prod_idx & tp->rx_jmb_ring_mask;
b196c7e4 6988
7ae52890
MC		 6989 if (tnapi != &tp->napi[1]) {
6990 tp->rx_refill = true;
e4af1af9 6991 napi_schedule(&tp->napi[1].napi);
7ae52890 6992 }
1da177e4 6993 }
1da177e4
LT		 6994
6995 return received;
6996}
6997
35f2d7d0 6998static void tg3_poll_link(struct tg3 *tp)
1da177e4 6999{
1da177e4 7000 /* handle link change and other phy events */
63c3a66f 7001 if (!(tg3_flag(tp, USE_LINKCHG_REG) || tg3_flag(tp, POLL_SERDES))) {
35f2d7d0
MC		 7002 struct tg3_hw_status *sblk = tp->napi[0].hw_status;
7003
1da177e4
LT		 7004 if (sblk->status & SD_STATUS_LINK_CHG) {
7005 sblk->status = SD_STATUS_UPDATED |
35f2d7d0 7006 (sblk->status & ~SD_STATUS_LINK_CHG);
f47c11ee 7007 spin_lock(&tp->lock);
63c3a66f 7008 if (tg3_flag(tp, USE_PHYLIB)) {
dd477003
MC		 7009 tw32_f(MAC_STATUS,
7010 (MAC_STATUS_SYNC_CHANGED |
7011 MAC_STATUS_CFG_CHANGED |
7012 MAC_STATUS_MI_COMPLETION |
7013 MAC_STATUS_LNKSTATE_CHANGED));
7014 udelay(40);
7015 } else
953c96e0 7016 tg3_setup_phy(tp, false);
f47c11ee 7017 spin_unlock(&tp->lock);
1da177e4
LT		 7018 }
7019 }
35f2d7d0
MC		 7020}
7021
f89f38b8
MC		 7022static int tg3_rx_prodring_xfer(struct tg3 *tp,
7023 struct tg3_rx_prodring_set *dpr,
7024 struct tg3_rx_prodring_set *spr)
b196c7e4
MC		 7025{
7026 u32 si, di, cpycnt, src_prod_idx;
f89f38b8 7027 int i, err = 0;
b196c7e4
MC		 7028
7029 while (1) {
7030 src_prod_idx = spr->rx_std_prod_idx;
7031
7032 /* Make sure updates to the rx_std_buffers[] entries and the
7033 * standard producer index are seen in the correct order.
7034 */
7035 smp_rmb();
7036
7037 if (spr->rx_std_cons_idx == src_prod_idx)
7038 break;
7039
7040 if (spr->rx_std_cons_idx < src_prod_idx)
7041 cpycnt = src_prod_idx - spr->rx_std_cons_idx;
7042 else
2c49a44d
MC		 7043 cpycnt = tp->rx_std_ring_mask + 1 -
7044 spr->rx_std_cons_idx;
b196c7e4 7045
2c49a44d
MC		 7046 cpycnt = min(cpycnt,
7047 tp->rx_std_ring_mask + 1 - dpr->rx_std_prod_idx);
b196c7e4
MC		 7048
7049 si = spr->rx_std_cons_idx;
7050 di = dpr->rx_std_prod_idx;
7051
e92967bf 7052 for (i = di; i < di + cpycnt; i++) {
9205fd9c 7053 if (dpr->rx_std_buffers[i].data) {
e92967bf 7054 cpycnt = i - di;
f89f38b8 7055 err = -ENOSPC;
e92967bf
MC		 7056 break;
7057 }
7058 }
7059
7060 if (!cpycnt)
7061 break;
7062
7063 /* Ensure that updates to the rx_std_buffers ring and the
7064 * shadowed hardware producer ring from tg3_recycle_skb() are
7065 * ordered correctly WRT the skb check above.
7066 */
7067 smp_rmb();
7068
b196c7e4
MC		 7069 memcpy(&dpr->rx_std_buffers[di],
7070 &spr->rx_std_buffers[si],
7071 cpycnt * sizeof(struct ring_info));
7072
7073 for (i = 0; i < cpycnt; i++, di++, si++) {
7074 struct tg3_rx_buffer_desc *sbd, *dbd;
7075 sbd = &spr->rx_std[si];
7076 dbd = &dpr->rx_std[di];
7077 dbd->addr_hi = sbd->addr_hi;
7078 dbd->addr_lo = sbd->addr_lo;
7079 }
7080
2c49a44d
MC		 7081 spr->rx_std_cons_idx = (spr->rx_std_cons_idx + cpycnt) &
7082 tp->rx_std_ring_mask;
7083 dpr->rx_std_prod_idx = (dpr->rx_std_prod_idx + cpycnt) &
7084 tp->rx_std_ring_mask;
b196c7e4
MC		 7085 }
7086
7087 while (1) {
7088 src_prod_idx = spr->rx_jmb_prod_idx;
7089
7090 /* Make sure updates to the rx_jmb_buffers[] entries and
7091 * the jumbo producer index are seen in the correct order.
7092 */
7093 smp_rmb();
7094
7095 if (spr->rx_jmb_cons_idx == src_prod_idx)
7096 break;
7097
7098 if (spr->rx_jmb_cons_idx < src_prod_idx)
7099 cpycnt = src_prod_idx - spr->rx_jmb_cons_idx;
7100 else
2c49a44d
MC		 7101 cpycnt = tp->rx_jmb_ring_mask + 1 -
7102 spr->rx_jmb_cons_idx;
b196c7e4
MC		 7103
7104 cpycnt = min(cpycnt,
2c49a44d 7105 tp->rx_jmb_ring_mask + 1 - dpr->rx_jmb_prod_idx);
b196c7e4
MC		 7106
7107 si = spr->rx_jmb_cons_idx;
7108 di = dpr->rx_jmb_prod_idx;
7109
e92967bf 7110 for (i = di; i < di + cpycnt; i++) {
9205fd9c 7111 if (dpr->rx_jmb_buffers[i].data) {
e92967bf 7112 cpycnt = i - di;
f89f38b8 7113 err = -ENOSPC;
e92967bf
MC		 7114 break;
7115 }
7116 }
7117
7118 if (!cpycnt)
7119 break;
7120
7121 /* Ensure that updates to the rx_jmb_buffers ring and the
7122 * shadowed hardware producer ring from tg3_recycle_skb() are
7123 * ordered correctly WRT the skb check above.
7124 */
7125 smp_rmb();
7126
b196c7e4
MC		 7127 memcpy(&dpr->rx_jmb_buffers[di],
7128 &spr->rx_jmb_buffers[si],
7129 cpycnt * sizeof(struct ring_info));
7130
7131 for (i = 0; i < cpycnt; i++, di++, si++) {
7132 struct tg3_rx_buffer_desc *sbd, *dbd;
7133 sbd = &spr->rx_jmb[si].std;
7134 dbd = &dpr->rx_jmb[di].std;
7135 dbd->addr_hi = sbd->addr_hi;
7136 dbd->addr_lo = sbd->addr_lo;
7137 }
7138
2c49a44d
MC		 7139 spr->rx_jmb_cons_idx = (spr->rx_jmb_cons_idx + cpycnt) &
7140 tp->rx_jmb_ring_mask;
7141 dpr->rx_jmb_prod_idx = (dpr->rx_jmb_prod_idx + cpycnt) &
7142 tp->rx_jmb_ring_mask;
b196c7e4 7143 }
f89f38b8
MC		 7144
7145 return err;
b196c7e4
MC		 7146}
7147
35f2d7d0
MC		 7148static int tg3_poll_work(struct tg3_napi *tnapi, int work_done, int budget)
7149{
7150 struct tg3 *tp = tnapi->tp;
1da177e4
LT		 7151
7152 /* run TX completion thread */
f3f3f27e 7153 if (tnapi->hw_status->idx[0].tx_consumer != tnapi->tx_cons) {
17375d25 7154 tg3_tx(tnapi);
63c3a66f 7155 if (unlikely(tg3_flag(tp, TX_RECOVERY_PENDING)))
4fd7ab59 7156 return work_done;
1da177e4
LT		 7157 }
7158
f891ea16
MC		 7159 if (!tnapi->rx_rcb_prod_idx)
7160 return work_done;
7161
1da177e4
LT		 7162 /* run RX thread, within the bounds set by NAPI.
7163 * All RX "locking" is done by ensuring outside
bea3348e 7164 * code synchronizes with tg3->napi.poll()
1da177e4 7165 */
8d9d7cfc 7166 if (*(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
17375d25 7167 work_done += tg3_rx(tnapi, budget - work_done);
1da177e4 7168
63c3a66f 7169 if (tg3_flag(tp, ENABLE_RSS) && tnapi == &tp->napi[1]) {
8fea32b9 7170 struct tg3_rx_prodring_set *dpr = &tp->napi[0].prodring;
f89f38b8 7171 int i, err = 0;
e4af1af9
MC		 7172 u32 std_prod_idx = dpr->rx_std_prod_idx;
7173 u32 jmb_prod_idx = dpr->rx_jmb_prod_idx;
b196c7e4 7174
7ae52890 7175 tp->rx_refill = false;
9102426a 7176 for (i = 1; i <= tp->rxq_cnt; i++)
f89f38b8 7177 err |= tg3_rx_prodring_xfer(tp, dpr,
8fea32b9 7178 &tp->napi[i].prodring);
b196c7e4
MC		 7179
7180 wmb();
7181
e4af1af9
MC		 7182 if (std_prod_idx != dpr->rx_std_prod_idx)
7183 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
7184 dpr->rx_std_prod_idx);
b196c7e4 7185
e4af1af9
MC		 7186 if (jmb_prod_idx != dpr->rx_jmb_prod_idx)
7187 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
7188 dpr->rx_jmb_prod_idx);
b196c7e4
MC		 7189
7190 mmiowb();
f89f38b8
MC		 7191
7192 if (err)
7193 tw32_f(HOSTCC_MODE, tp->coal_now);
b196c7e4
MC		 7194 }
7195
6f535763
DM		 7196 return work_done;
7197}
7198
db219973
MC		 7199static inline void tg3_reset_task_schedule(struct tg3 *tp)
7200{
7201 if (!test_and_set_bit(TG3_FLAG_RESET_TASK_PENDING, tp->tg3_flags))
7202 schedule_work(&tp->reset_task);
7203}
7204
7205static inline void tg3_reset_task_cancel(struct tg3 *tp)
7206{
7207 cancel_work_sync(&tp->reset_task);
7208 tg3_flag_clear(tp, RESET_TASK_PENDING);
c7101359 7209 tg3_flag_clear(tp, TX_RECOVERY_PENDING);
db219973
MC		 7210}
7211
35f2d7d0
MC		 7212static int tg3_poll_msix(struct napi_struct *napi, int budget)
7213{
7214 struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
7215 struct tg3 *tp = tnapi->tp;
7216 int work_done = 0;
7217 struct tg3_hw_status *sblk = tnapi->hw_status;
7218
7219 while (1) {
7220 work_done = tg3_poll_work(tnapi, work_done, budget);
7221
63c3a66f 7222 if (unlikely(tg3_flag(tp, TX_RECOVERY_PENDING)))
35f2d7d0
MC		 7223 goto tx_recovery;
7224
7225 if (unlikely(work_done >= budget))
7226 break;
7227
c6cdf436 7228 /* tp->last_tag is used in tg3_int_reenable() below
35f2d7d0
MC		 7229 * to tell the hw how much work has been processed,
7230 * so we must read it before checking for more work.
7231 */
7232 tnapi->last_tag = sblk->status_tag;
7233 tnapi->last_irq_tag = tnapi->last_tag;
7234 rmb();
7235
7236 /* check for RX/TX work to do */
6d40db7b
MC		 7237 if (likely(sblk->idx[0].tx_consumer == tnapi->tx_cons &&
7238 *(tnapi->rx_rcb_prod_idx) == tnapi->rx_rcb_ptr)) {
7ae52890
MC		 7239
7240 /* This test here is not race free, but will reduce
7241 * the number of interrupts by looping again.
7242 */
7243 if (tnapi == &tp->napi[1] && tp->rx_refill)
7244 continue;
7245
35f2d7d0
MC		 7246 napi_complete(napi);
7247 /* Reenable interrupts. */
7248 tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
7ae52890
MC		 7249
7250 /* This test here is synchronized by napi_schedule()
7251 * and napi_complete() to close the race condition.
7252 */
7253 if (unlikely(tnapi == &tp->napi[1] && tp->rx_refill)) {
7254 tw32(HOSTCC_MODE, tp->coalesce_mode |
7255 HOSTCC_MODE_ENABLE |
7256 tnapi->coal_now);
7257 }
35f2d7d0
MC		 7258 mmiowb();
7259 break;
7260 }
7261 }
7262
7263 return work_done;
7264
7265tx_recovery:
7266 /* work_done is guaranteed to be less than budget. */
7267 napi_complete(napi);
db219973 7268 tg3_reset_task_schedule(tp);
35f2d7d0
MC		 7269 return work_done;
7270}
7271
e64de4e6
MC		 7272static void tg3_process_error(struct tg3 *tp)
7273{
7274 u32 val;
7275 bool real_error = false;
7276
63c3a66f 7277 if (tg3_flag(tp, ERROR_PROCESSED))
e64de4e6
MC		 7278 return;
7279
7280 /* Check Flow Attention register */
7281 val = tr32(HOSTCC_FLOW_ATTN);
7282 if (val & ~HOSTCC_FLOW_ATTN_MBUF_LWM) {
7283 netdev_err(tp->dev, "FLOW Attention error. Resetting chip.\n");
7284 real_error = true;
7285 }
7286
7287 if (tr32(MSGINT_STATUS) & ~MSGINT_STATUS_MSI_REQ) {
7288 netdev_err(tp->dev, "MSI Status error. Resetting chip.\n");
7289 real_error = true;
7290 }
7291
7292 if (tr32(RDMAC_STATUS) || tr32(WDMAC_STATUS)) {
7293 netdev_err(tp->dev, "DMA Status error. Resetting chip.\n");
7294 real_error = true;
7295 }
7296
7297 if (!real_error)
7298 return;
7299
7300 tg3_dump_state(tp);
7301
63c3a66f 7302 tg3_flag_set(tp, ERROR_PROCESSED);
db219973 7303 tg3_reset_task_schedule(tp);
e64de4e6
MC		 7304}
7305
6f535763
DM		 7306static int tg3_poll(struct napi_struct *napi, int budget)
7307{
8ef0442f
MC		 7308 struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
7309 struct tg3 *tp = tnapi->tp;
6f535763 7310 int work_done = 0;
898a56f8 7311 struct tg3_hw_status *sblk = tnapi->hw_status;
6f535763
DM		 7312
7313 while (1) {
e64de4e6
MC		 7314 if (sblk->status & SD_STATUS_ERROR)
7315 tg3_process_error(tp);
7316
35f2d7d0
MC		 7317 tg3_poll_link(tp);
7318
17375d25 7319 work_done = tg3_poll_work(tnapi, work_done, budget);
6f535763 7320
63c3a66f 7321 if (unlikely(tg3_flag(tp, TX_RECOVERY_PENDING)))
6f535763
DM		 7322 goto tx_recovery;
7323
7324 if (unlikely(work_done >= budget))
7325 break;
7326
63c3a66f 7327 if (tg3_flag(tp, TAGGED_STATUS)) {
17375d25 7328 /* tp->last_tag is used in tg3_int_reenable() below
4fd7ab59
MC		 7329 * to tell the hw how much work has been processed,
7330 * so we must read it before checking for more work.
7331 */
898a56f8
MC		 7332 tnapi->last_tag = sblk->status_tag;
7333 tnapi->last_irq_tag = tnapi->last_tag;
4fd7ab59
MC		 7334 rmb();
7335 } else
7336 sblk->status &= ~SD_STATUS_UPDATED;
6f535763 7337
17375d25 7338 if (likely(!tg3_has_work(tnapi))) {
288379f0 7339 napi_complete(napi);
17375d25 7340 tg3_int_reenable(tnapi);
6f535763
DM		 7341 break;
7342 }
1da177e4
LT		 7343 }
7344
bea3348e 7345 return work_done;
6f535763
DM		 7346
7347tx_recovery:
4fd7ab59 7348 /* work_done is guaranteed to be less than budget. */
288379f0 7349 napi_complete(napi);
db219973 7350 tg3_reset_task_schedule(tp);
4fd7ab59 7351 return work_done;
1da177e4
LT		 7352}
7353
66cfd1bd
MC		 7354static void tg3_napi_disable(struct tg3 *tp)
7355{
7356 int i;
7357
7358 for (i = tp->irq_cnt - 1; i >= 0; i--)
7359 napi_disable(&tp->napi[i].napi);
7360}
7361
7362static void tg3_napi_enable(struct tg3 *tp)
7363{
7364 int i;
7365
7366 for (i = 0; i < tp->irq_cnt; i++)
7367 napi_enable(&tp->napi[i].napi);
7368}
7369
7370static void tg3_napi_init(struct tg3 *tp)
7371{
7372 int i;
7373
7374 netif_napi_add(tp->dev, &tp->napi[0].napi, tg3_poll, 64);
7375 for (i = 1; i < tp->irq_cnt; i++)
7376 netif_napi_add(tp->dev, &tp->napi[i].napi, tg3_poll_msix, 64);
7377}
7378
7379static void tg3_napi_fini(struct tg3 *tp)
7380{
7381 int i;
7382
7383 for (i = 0; i < tp->irq_cnt; i++)
7384 netif_napi_del(&tp->napi[i].napi);
7385}
7386
7387static inline void tg3_netif_stop(struct tg3 *tp)
7388{
7389 tp->dev->trans_start = jiffies; /* prevent tx timeout */
7390 tg3_napi_disable(tp);
f4a46d1f 7391 netif_carrier_off(tp->dev);
66cfd1bd
MC		 7392 netif_tx_disable(tp->dev);
7393}
7394
35763066 7395/* tp->lock must be held */
66cfd1bd
MC		 7396static inline void tg3_netif_start(struct tg3 *tp)
7397{
be947307
MC		 7398 tg3_ptp_resume(tp);
7399
66cfd1bd
MC		 7400 /* NOTE: unconditional netif_tx_wake_all_queues is only
7401 * appropriate so long as all callers are assured to
7402 * have free tx slots (such as after tg3_init_hw)
7403 */
7404 netif_tx_wake_all_queues(tp->dev);
7405
f4a46d1f
NNS		 7406 if (tp->link_up)
7407 netif_carrier_on(tp->dev);
7408
66cfd1bd
MC		 7409 tg3_napi_enable(tp);
7410 tp->napi[0].hw_status->status |= SD_STATUS_UPDATED;
7411 tg3_enable_ints(tp);
7412}
7413
f47c11ee
DM		 7414static void tg3_irq_quiesce(struct tg3 *tp)
7415{
4f125f42
MC		 7416 int i;
7417
f47c11ee
DM		 7418 BUG_ON(tp->irq_sync);
7419
7420 tp->irq_sync = 1;
7421 smp_mb();
7422
4f125f42
MC		 7423 for (i = 0; i < tp->irq_cnt; i++)
7424 synchronize_irq(tp->napi[i].irq_vec);
f47c11ee
DM		 7425}
7426
f47c11ee
DM		 7427/* Fully shutdown all tg3 driver activity elsewhere in the system.
7428 * If irq_sync is non-zero, then the IRQ handler must be synchronized
7429 * with as well. Most of the time, this is not necessary except when
7430 * shutting down the device.
7431 */
7432static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
7433{
46966545 7434 spin_lock_bh(&tp->lock);
f47c11ee
DM		 7435 if (irq_sync)
7436 tg3_irq_quiesce(tp);
f47c11ee
DM		 7437}
7438
7439static inline void tg3_full_unlock(struct tg3 *tp)
7440{
f47c11ee
DM		 7441 spin_unlock_bh(&tp->lock);
7442}
7443
fcfa0a32
MC		 7444/* One-shot MSI handler - Chip automatically disables interrupt
7445 * after sending MSI so driver doesn't have to do it.
7446 */
7d12e780 7447static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
fcfa0a32 7448{
09943a18
MC		 7449 struct tg3_napi *tnapi = dev_id;
7450 struct tg3 *tp = tnapi->tp;
fcfa0a32 7451
898a56f8 7452 prefetch(tnapi->hw_status);
0c1d0e2b
MC		 7453 if (tnapi->rx_rcb)
7454 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
fcfa0a32
MC		 7455
7456 if (likely(!tg3_irq_sync(tp)))
09943a18 7457 napi_schedule(&tnapi->napi);
fcfa0a32
MC		 7458
7459 return IRQ_HANDLED;
7460}
7461
88b06bc2
MC		 7462/* MSI ISR - No need to check for interrupt sharing and no need to
7463 * flush status block and interrupt mailbox. PCI ordering rules
7464 * guarantee that MSI will arrive after the status block.
7465 */
7d12e780 7466static irqreturn_t tg3_msi(int irq, void *dev_id)
88b06bc2 7467{
09943a18
MC		 7468 struct tg3_napi *tnapi = dev_id;
7469 struct tg3 *tp = tnapi->tp;
88b06bc2 7470
898a56f8 7471 prefetch(tnapi->hw_status);
0c1d0e2b
MC		 7472 if (tnapi->rx_rcb)
7473 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
88b06bc2 7474 /*
fac9b83e 7475 * Writing any value to intr-mbox-0 clears PCI INTA# and
88b06bc2 7476 * chip-internal interrupt pending events.
fac9b83e 7477 * Writing non-zero to intr-mbox-0 additional tells the
88b06bc2
MC		 7478 * NIC to stop sending us irqs, engaging "in-intr-handler"
7479 * event coalescing.
7480 */
5b39de91 7481 tw32_mailbox(tnapi->int_mbox, 0x00000001);
61487480 7482 if (likely(!tg3_irq_sync(tp)))
09943a18 7483 napi_schedule(&tnapi->napi);
61487480 7484
88b06bc2
MC		 7485 return IRQ_RETVAL(1);
7486}
7487
7d12e780 7488static irqreturn_t tg3_interrupt(int irq, void *dev_id)
1da177e4 7489{
09943a18
MC		 7490 struct tg3_napi *tnapi = dev_id;
7491 struct tg3 *tp = tnapi->tp;
898a56f8 7492 struct tg3_hw_status *sblk = tnapi->hw_status;
1da177e4
LT		 7493 unsigned int handled = 1;
7494
1da177e4
LT		 7495 /* In INTx mode, it is possible for the interrupt to arrive at
7496 * the CPU before the status block posted prior to the interrupt.
7497 * Reading the PCI State register will confirm whether the
7498 * interrupt is ours and will flush the status block.
7499 */
d18edcb2 7500 if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
63c3a66f 7501 if (tg3_flag(tp, CHIP_RESETTING) ||
d18edcb2
MC		 7502 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
7503 handled = 0;
f47c11ee 7504 goto out;
fac9b83e 7505 }
d18edcb2
MC		 7506 }
7507
7508 /*
7509 * Writing any value to intr-mbox-0 clears PCI INTA# and
7510 * chip-internal interrupt pending events.
7511 * Writing non-zero to intr-mbox-0 additional tells the
7512 * NIC to stop sending us irqs, engaging "in-intr-handler"
7513 * event coalescing.
c04cb347
MC		 7514 *
7515 * Flush the mailbox to de-assert the IRQ immediately to prevent
7516 * spurious interrupts. The flush impacts performance but
7517 * excessive spurious interrupts can be worse in some cases.
d18edcb2 7518 */
c04cb347 7519 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
d18edcb2
MC		 7520 if (tg3_irq_sync(tp))
7521 goto out;
7522 sblk->status &= ~SD_STATUS_UPDATED;
17375d25 7523 if (likely(tg3_has_work(tnapi))) {
72334482 7524 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
09943a18 7525 napi_schedule(&tnapi->napi);
d18edcb2
MC		 7526 } else {
7527 /* No work, shared interrupt perhaps? re-enable
7528 * interrupts, and flush that PCI write
7529 */
7530 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
7531 0x00000000);
fac9b83e 7532 }
f47c11ee 7533out:
fac9b83e
DM		 7534 return IRQ_RETVAL(handled);
7535}
7536
7d12e780 7537static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
fac9b83e 7538{
09943a18
MC		 7539 struct tg3_napi *tnapi = dev_id;
7540 struct tg3 *tp = tnapi->tp;
898a56f8 7541 struct tg3_hw_status *sblk = tnapi->hw_status;
fac9b83e
DM		 7542 unsigned int handled = 1;
7543
fac9b83e
DM		 7544 /* In INTx mode, it is possible for the interrupt to arrive at
7545 * the CPU before the status block posted prior to the interrupt.
7546 * Reading the PCI State register will confirm whether the
7547 * interrupt is ours and will flush the status block.
7548 */
898a56f8 7549 if (unlikely(sblk->status_tag == tnapi->last_irq_tag)) {
63c3a66f 7550 if (tg3_flag(tp, CHIP_RESETTING) ||
d18edcb2
MC		 7551 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
7552 handled = 0;
f47c11ee 7553 goto out;
1da177e4 7554 }
d18edcb2
MC		 7555 }
7556
7557 /*
7558 * writing any value to intr-mbox-0 clears PCI INTA# and
7559 * chip-internal interrupt pending events.
7560 * writing non-zero to intr-mbox-0 additional tells the
7561 * NIC to stop sending us irqs, engaging "in-intr-handler"
7562 * event coalescing.
c04cb347
MC		 7563 *
7564 * Flush the mailbox to de-assert the IRQ immediately to prevent
7565 * spurious interrupts. The flush impacts performance but
7566 * excessive spurious interrupts can be worse in some cases.
d18edcb2 7567 */
c04cb347 7568 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
624f8e50
MC		 7569
7570 /*
7571 * In a shared interrupt configuration, sometimes other devices'
7572 * interrupts will scream. We record the current status tag here
7573 * so that the above check can report that the screaming interrupts
7574 * are unhandled. Eventually they will be silenced.
7575 */
898a56f8 7576 tnapi->last_irq_tag = sblk->status_tag;
624f8e50 7577
d18edcb2
MC		 7578 if (tg3_irq_sync(tp))
7579 goto out;
624f8e50 7580
72334482 7581 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
624f8e50 7582
09943a18 7583 napi_schedule(&tnapi->napi);
624f8e50 7584
f47c11ee 7585out:
1da177e4
LT		 7586 return IRQ_RETVAL(handled);
7587}
7588
7938109f 7589/* ISR for interrupt test */
7d12e780 7590static irqreturn_t tg3_test_isr(int irq, void *dev_id)
7938109f 7591{
09943a18
MC		 7592 struct tg3_napi *tnapi = dev_id;
7593 struct tg3 *tp = tnapi->tp;
898a56f8 7594 struct tg3_hw_status *sblk = tnapi->hw_status;
7938109f 7595
f9804ddb
MC		 7596 if ((sblk->status & SD_STATUS_UPDATED) ||
7597 !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
b16250e3 7598 tg3_disable_ints(tp);
7938109f
MC		 7599 return IRQ_RETVAL(1);
7600 }
7601 return IRQ_RETVAL(0);
7602}
7603
1da177e4
LT		 7604#ifdef CONFIG_NET_POLL_CONTROLLER
7605static void tg3_poll_controller(struct net_device *dev)
7606{
4f125f42 7607 int i;
88b06bc2
MC		 7608 struct tg3 *tp = netdev_priv(dev);
7609
9c13cb8b
NNS		 7610 if (tg3_irq_sync(tp))
7611 return;
7612
4f125f42 7613 for (i = 0; i < tp->irq_cnt; i++)
fe234f0e 7614 tg3_interrupt(tp->napi[i].irq_vec, &tp->napi[i]);
1da177e4
LT		 7615}
7616#endif
7617
1da177e4
LT		 7618static void tg3_tx_timeout(struct net_device *dev)
7619{
7620 struct tg3 *tp = netdev_priv(dev);
7621
b0408751 7622 if (netif_msg_tx_err(tp)) {
05dbe005 7623 netdev_err(dev, "transmit timed out, resetting\n");
97bd8e49 7624 tg3_dump_state(tp);
b0408751 7625 }
1da177e4 7626
db219973 7627 tg3_reset_task_schedule(tp);
1da177e4
LT		 7628}
7629
c58ec932
MC		 7630/* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
7631static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
7632{
7633 u32 base = (u32) mapping & 0xffffffff;
7634
37567910 7635 return base + len + 8 < base;
c58ec932
MC		 7636}
7637
0f0d1510
MC		 7638/* Test for TSO DMA buffers that cross into regions which are within MSS bytes
7639 * of any 4GB boundaries: 4G, 8G, etc
7640 */
7641static inline int tg3_4g_tso_overflow_test(struct tg3 *tp, dma_addr_t mapping,
7642 u32 len, u32 mss)
7643{
7644 if (tg3_asic_rev(tp) == ASIC_REV_5762 && mss) {
7645 u32 base = (u32) mapping & 0xffffffff;
7646
7647 return ((base + len + (mss & 0x3fff)) < base);
7648 }
7649 return 0;
7650}
7651
72f2afb8
MC		 7652/* Test for DMA addresses > 40-bit */
7653static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
7654 int len)
7655{
7656#if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
63c3a66f 7657 if (tg3_flag(tp, 40BIT_DMA_BUG))
807540ba 7658 return ((u64) mapping + len) > DMA_BIT_MASK(40);
72f2afb8
MC		 7659 return 0;
7660#else
7661 return 0;
7662#endif
7663}
7664
d1a3b737 7665static inline void tg3_tx_set_bd(struct tg3_tx_buffer_desc *txbd,
92cd3a17
MC		 7666 dma_addr_t mapping, u32 len, u32 flags,
7667 u32 mss, u32 vlan)
2ffcc981 7668{
92cd3a17
MC		 7669 txbd->addr_hi = ((u64) mapping >> 32);
7670 txbd->addr_lo = ((u64) mapping & 0xffffffff);
7671 txbd->len_flags = (len << TXD_LEN_SHIFT) | (flags & 0x0000ffff);
7672 txbd->vlan_tag = (mss << TXD_MSS_SHIFT) | (vlan << TXD_VLAN_TAG_SHIFT);
2ffcc981 7673}
1da177e4 7674
84b67b27 7675static bool tg3_tx_frag_set(struct tg3_napi *tnapi, u32 *entry, u32 *budget,
d1a3b737
MC		 7676 dma_addr_t map, u32 len, u32 flags,
7677 u32 mss, u32 vlan)
7678{
7679 struct tg3 *tp = tnapi->tp;
7680 bool hwbug = false;
7681
7682 if (tg3_flag(tp, SHORT_DMA_BUG) && len <= 8)
3db1cd5c 7683 hwbug = true;
d1a3b737
MC		 7684
7685 if (tg3_4g_overflow_test(map, len))
3db1cd5c 7686 hwbug = true;
d1a3b737 7687
0f0d1510
MC		 7688 if (tg3_4g_tso_overflow_test(tp, map, len, mss))
7689 hwbug = true;
7690
d1a3b737 7691 if (tg3_40bit_overflow_test(tp, map, len))
3db1cd5c 7692 hwbug = true;
d1a3b737 7693
a4cb428d 7694 if (tp->dma_limit) {
b9e45482 7695 u32 prvidx = *entry;
e31aa987 7696 u32 tmp_flag = flags & ~TXD_FLAG_END;
a4cb428d
MC		 7697 while (len > tp->dma_limit && *budget) {
7698 u32 frag_len = tp->dma_limit;
7699 len -= tp->dma_limit;
e31aa987 7700
b9e45482
MC		 7701 /* Avoid the 8byte DMA problem */
7702 if (len <= 8) {
a4cb428d
MC		 7703 len += tp->dma_limit / 2;
7704 frag_len = tp->dma_limit / 2;
e31aa987
MC		 7705 }
7706
b9e45482
MC		 7707 tnapi->tx_buffers[*entry].fragmented = true;
7708
7709 tg3_tx_set_bd(&tnapi->tx_ring[*entry], map,
7710 frag_len, tmp_flag, mss, vlan);
7711 *budget -= 1;
7712 prvidx = *entry;
7713 *entry = NEXT_TX(*entry);
7714
e31aa987
MC		 7715 map += frag_len;
7716 }
7717
7718 if (len) {
7719 if (*budget) {
7720 tg3_tx_set_bd(&tnapi->tx_ring[*entry], map,
7721 len, flags, mss, vlan);
b9e45482 7722 *budget -= 1;
e31aa987
MC		 7723 *entry = NEXT_TX(*entry);
7724 } else {
3db1cd5c 7725 hwbug = true;
b9e45482 7726 tnapi->tx_buffers[prvidx].fragmented = false;
e31aa987
MC		 7727 }
7728 }
7729 } else {
84b67b27
MC		 7730 tg3_tx_set_bd(&tnapi->tx_ring[*entry], map,
7731 len, flags, mss, vlan);
e31aa987
MC		 7732 *entry = NEXT_TX(*entry);
7733 }
d1a3b737
MC		 7734
7735 return hwbug;
7736}
7737
0d681b27 7738static void tg3_tx_skb_unmap(struct tg3_napi *tnapi, u32 entry, int last)
432aa7ed
MC		 7739{
7740 int i;
0d681b27 7741 struct sk_buff *skb;
df8944cf 7742 struct tg3_tx_ring_info *txb = &tnapi->tx_buffers[entry];
432aa7ed 7743
0d681b27
MC		 7744 skb = txb->skb;
7745 txb->skb = NULL;
7746
432aa7ed
MC		 7747 pci_unmap_single(tnapi->tp->pdev,
7748 dma_unmap_addr(txb, mapping),
7749 skb_headlen(skb),
7750 PCI_DMA_TODEVICE);
e01ee14d
MC		 7751
7752 while (txb->fragmented) {
7753 txb->fragmented = false;
7754 entry = NEXT_TX(entry);
7755 txb = &tnapi->tx_buffers[entry];
7756 }
7757
ba1142e4 7758 for (i = 0; i <= last; i++) {
9e903e08 7759 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
432aa7ed
MC		 7760
7761 entry = NEXT_TX(entry);
7762 txb = &tnapi->tx_buffers[entry];
7763
7764 pci_unmap_page(tnapi->tp->pdev,
7765 dma_unmap_addr(txb, mapping),
9e903e08 7766 skb_frag_size(frag), PCI_DMA_TODEVICE);
e01ee14d
MC		 7767
7768 while (txb->fragmented) {
7769 txb->fragmented = false;
7770 entry = NEXT_TX(entry);
7771 txb = &tnapi->tx_buffers[entry];
7772 }
432aa7ed
MC		 7773 }
7774}
7775
72f2afb8 7776/* Workaround 4GB and 40-bit hardware DMA bugs. */
24f4efd4 7777static int tigon3_dma_hwbug_workaround(struct tg3_napi *tnapi,
f7ff1987 7778 struct sk_buff **pskb,
84b67b27 7779 u32 *entry, u32 *budget,
92cd3a17 7780 u32 base_flags, u32 mss, u32 vlan)
1da177e4 7781{
24f4efd4 7782 struct tg3 *tp = tnapi->tp;
f7ff1987 7783 struct sk_buff *new_skb, *skb = *pskb;
c58ec932 7784 dma_addr_t new_addr = 0;
432aa7ed 7785 int ret = 0;
1da177e4 7786
4153577a 7787 if (tg3_asic_rev(tp) != ASIC_REV_5701)
41588ba1
MC		 7788 new_skb = skb_copy(skb, GFP_ATOMIC);
7789 else {
7790 int more_headroom = 4 - ((unsigned long)skb->data & 3);
7791
7792 new_skb = skb_copy_expand(skb,
7793 skb_headroom(skb) + more_headroom,
7794 skb_tailroom(skb), GFP_ATOMIC);
7795 }
7796
1da177e4 7797 if (!new_skb) {
c58ec932
MC		 7798 ret = -1;
7799 } else {
7800 /* New SKB is guaranteed to be linear. */
f4188d8a
AD		 7801 new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len,
7802 PCI_DMA_TODEVICE);
7803 /* Make sure the mapping succeeded */
7804 if (pci_dma_mapping_error(tp->pdev, new_addr)) {
497a27b9 7805 dev_kfree_skb_any(new_skb);
c58ec932 7806 ret = -1;
c58ec932 7807 } else {
b9e45482
MC		 7808 u32 save_entry = *entry;
7809
92cd3a17
MC		 7810 base_flags |= TXD_FLAG_END;
7811
84b67b27
MC		 7812 tnapi->tx_buffers[*entry].skb = new_skb;
7813 dma_unmap_addr_set(&tnapi->tx_buffers[*entry],
432aa7ed
MC		 7814 mapping, new_addr);
7815
84b67b27 7816 if (tg3_tx_frag_set(tnapi, entry, budget, new_addr,
d1a3b737
MC		 7817 new_skb->len, base_flags,
7818 mss, vlan)) {
ba1142e4 7819 tg3_tx_skb_unmap(tnapi, save_entry, -1);
497a27b9 7820 dev_kfree_skb_any(new_skb);
d1a3b737
MC		 7821 ret = -1;
7822 }
f4188d8a 7823 }
1da177e4
LT		 7824 }
7825
497a27b9 7826 dev_kfree_skb_any(skb);
f7ff1987 7827 *pskb = new_skb;
c58ec932 7828 return ret;
1da177e4
LT		 7829}
7830
2ffcc981 7831static netdev_tx_t tg3_start_xmit(struct sk_buff *, struct net_device *);
52c0fd83 7832
4d8fdc95
PS		 7833/* Use GSO to workaround all TSO packets that meet HW bug conditions
7834 * indicated in tg3_tx_frag_set()
52c0fd83 7835 */
4d8fdc95
PS		 7836static int tg3_tso_bug(struct tg3 *tp, struct tg3_napi *tnapi,
7837 struct netdev_queue *txq, struct sk_buff *skb)
52c0fd83
MC		 7838{
7839 struct sk_buff *segs, *nskb;
f3f3f27e 7840 u32 frag_cnt_est = skb_shinfo(skb)->gso_segs * 3;
52c0fd83
MC		 7841
7842 /* Estimate the number of fragments in the worst case */
4d8fdc95
PS		 7843 if (unlikely(tg3_tx_avail(tnapi) <= frag_cnt_est)) {
7844 netif_tx_stop_queue(txq);
f65aac16
MC		 7845
7846 /* netif_tx_stop_queue() must be done before checking
7847 * checking tx index in tg3_tx_avail() below, because in
7848 * tg3_tx(), we update tx index before checking for
7849 * netif_tx_queue_stopped().
7850 */
7851 smp_mb();
4d8fdc95 7852 if (tg3_tx_avail(tnapi) <= frag_cnt_est)
7f62ad5d
MC		 7853 return NETDEV_TX_BUSY;
7854
4d8fdc95 7855 netif_tx_wake_queue(txq);
52c0fd83
MC		 7856 }
7857
4d8fdc95
PS		 7858 segs = skb_gso_segment(skb, tp->dev->features &
7859 ~(NETIF_F_TSO | NETIF_F_TSO6));
40c1deaf 7860 if (IS_ERR(segs) || !segs)
52c0fd83
MC		 7861 goto tg3_tso_bug_end;
7862
7863 do {
7864 nskb = segs;
7865 segs = segs->next;
7866 nskb->next = NULL;
2ffcc981 7867 tg3_start_xmit(nskb, tp->dev);
52c0fd83
MC		 7868 } while (segs);
7869
7870tg3_tso_bug_end:
497a27b9 7871 dev_kfree_skb_any(skb);
52c0fd83
MC		 7872
7873 return NETDEV_TX_OK;
7874}
52c0fd83 7875
d71c0dc4 7876/* hard_start_xmit for all devices */
2ffcc981 7877static netdev_tx_t tg3_start_xmit(struct sk_buff *skb, struct net_device *dev)
1da177e4
LT		 7878{
7879 struct tg3 *tp = netdev_priv(dev);
92cd3a17 7880 u32 len, entry, base_flags, mss, vlan = 0;
84b67b27 7881 u32 budget;
432aa7ed 7882 int i = -1, would_hit_hwbug;
90079ce8 7883 dma_addr_t mapping;
24f4efd4
MC		 7884 struct tg3_napi *tnapi;
7885 struct netdev_queue *txq;
432aa7ed 7886 unsigned int last;
d3f6f3a1
MC		 7887 struct iphdr *iph = NULL;
7888 struct tcphdr *tcph = NULL;
7889 __sum16 tcp_csum = 0, ip_csum = 0;
7890 __be16 ip_tot_len = 0;
f4188d8a 7891
24f4efd4
MC		 7892 txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
7893 tnapi = &tp->napi[skb_get_queue_mapping(skb)];
63c3a66f 7894 if (tg3_flag(tp, ENABLE_TSS))
24f4efd4 7895 tnapi++;
1da177e4 7896
84b67b27
MC		 7897 budget = tg3_tx_avail(tnapi);
7898
00b70504 7899 /* We are running in BH disabled context with netif_tx_lock
bea3348e 7900 * and TX reclaim runs via tp->napi.poll inside of a software
f47c11ee
DM		 7901 * interrupt. Furthermore, IRQ processing runs lockless so we have
7902 * no IRQ context deadlocks to worry about either. Rejoice!
1da177e4 7903 */
84b67b27 7904 if (unlikely(budget <= (skb_shinfo(skb)->nr_frags + 1))) {
24f4efd4
MC		 7905 if (!netif_tx_queue_stopped(txq)) {
7906 netif_tx_stop_queue(txq);
1f064a87
SH		 7907
7908 /* This is a hard error, log it. */
5129c3a3
MC		 7909 netdev_err(dev,
7910 "BUG! Tx Ring full when queue awake!\n");
1f064a87 7911 }
1da177e4
LT		 7912 return NETDEV_TX_BUSY;
7913 }
7914
f3f3f27e 7915 entry = tnapi->tx_prod;
1da177e4 7916 base_flags = 0;
24f4efd4 7917
be98da6a
MC		 7918 mss = skb_shinfo(skb)->gso_size;
7919 if (mss) {
34195c3d 7920 u32 tcp_opt_len, hdr_len;
1da177e4 7921
105dcb59 7922 if (skb_cow_head(skb, 0))
48855432 7923 goto drop;
1da177e4 7924
34195c3d 7925 iph = ip_hdr(skb);
ab6a5bb6 7926 tcp_opt_len = tcp_optlen(skb);
1da177e4 7927
a5a11955 7928 hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb) - ETH_HLEN;
34195c3d 7929
476c1885
VY		 7930 /* HW/FW can not correctly segment packets that have been
7931 * vlan encapsulated.
7932 */
7933 if (skb->protocol == htons(ETH_P_8021Q) ||
7934 skb->protocol == htons(ETH_P_8021AD))
7935 return tg3_tso_bug(tp, tnapi, txq, skb);
7936
a5a11955 7937 if (!skb_is_gso_v6(skb)) {
d71c0dc4
MC		 7938 if (unlikely((ETH_HLEN + hdr_len) > 80) &&
7939 tg3_flag(tp, TSO_BUG))
4d8fdc95 7940 return tg3_tso_bug(tp, tnapi, txq, skb);
d71c0dc4 7941
d3f6f3a1
MC		 7942 ip_csum = iph->check;
7943 ip_tot_len = iph->tot_len;
34195c3d
MC		 7944 iph->check = 0;
7945 iph->tot_len = htons(mss + hdr_len);
7946 }
7947
1da177e4
LT		 7948 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
7949 TXD_FLAG_CPU_POST_DMA);
7950
d3f6f3a1
MC		 7951 tcph = tcp_hdr(skb);
7952 tcp_csum = tcph->check;
7953
63c3a66f
JP		 7954 if (tg3_flag(tp, HW_TSO_1) ||
7955 tg3_flag(tp, HW_TSO_2) ||
7956 tg3_flag(tp, HW_TSO_3)) {
d3f6f3a1 7957 tcph->check = 0;
1da177e4 7958 base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
d3f6f3a1
MC		 7959 } else {
7960 tcph->check = ~csum_tcpudp_magic(iph->saddr, iph->daddr,
7961 0, IPPROTO_TCP, 0);
7962 }
1da177e4 7963
63c3a66f 7964 if (tg3_flag(tp, HW_TSO_3)) {
615774fe
MC		 7965 mss |= (hdr_len & 0xc) << 12;
7966 if (hdr_len & 0x10)
7967 base_flags |= 0x00000010;
7968 base_flags |= (hdr_len & 0x3e0) << 5;
63c3a66f 7969 } else if (tg3_flag(tp, HW_TSO_2))
92c6b8d1 7970 mss |= hdr_len << 9;
63c3a66f 7971 else if (tg3_flag(tp, HW_TSO_1) ||
4153577a 7972 tg3_asic_rev(tp) == ASIC_REV_5705) {
eddc9ec5 7973 if (tcp_opt_len || iph->ihl > 5) {
1da177e4
LT		 7974 int tsflags;
7975
eddc9ec5 7976 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
1da177e4
LT		 7977 mss |= (tsflags << 11);
7978 }
7979 } else {
eddc9ec5 7980 if (tcp_opt_len || iph->ihl > 5) {
1da177e4
LT		 7981 int tsflags;
7982
eddc9ec5 7983 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
1da177e4
LT		 7984 base_flags |= tsflags << 12;
7985 }
7986 }
476c1885
VY		 7987 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
7988 /* HW/FW can not correctly checksum packets that have been
7989 * vlan encapsulated.
7990 */
7991 if (skb->protocol == htons(ETH_P_8021Q) ||
7992 skb->protocol == htons(ETH_P_8021AD)) {
7993 if (skb_checksum_help(skb))
7994 goto drop;
7995 } else {
7996 base_flags |= TXD_FLAG_TCPUDP_CSUM;
7997 }
1da177e4 7998 }
bf933c80 7999
93a700a9
MC		 8000 if (tg3_flag(tp, USE_JUMBO_BDFLAG) &&
8001 !mss && skb->len > VLAN_ETH_FRAME_LEN)
8002 base_flags |= TXD_FLAG_JMB_PKT;
8003
92cd3a17
MC		 8004 if (vlan_tx_tag_present(skb)) {
8005 base_flags |= TXD_FLAG_VLAN;
8006 vlan = vlan_tx_tag_get(skb);
8007 }
1da177e4 8008
fb4ce8ad
MC		 8009 if ((unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) &&
8010 tg3_flag(tp, TX_TSTAMP_EN)) {
8011 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
8012 base_flags |= TXD_FLAG_HWTSTAMP;
8013 }
8014
f4188d8a
AD		 8015 len = skb_headlen(skb);
8016
8017 mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
48855432
ED		 8018 if (pci_dma_mapping_error(tp->pdev, mapping))
8019 goto drop;
8020
90079ce8 8021
f3f3f27e 8022 tnapi->tx_buffers[entry].skb = skb;
4e5e4f0d 8023 dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping);
1da177e4
LT		 8024
8025 would_hit_hwbug = 0;
8026
63c3a66f 8027 if (tg3_flag(tp, 5701_DMA_BUG))
c58ec932 8028 would_hit_hwbug = 1;
1da177e4 8029
84b67b27 8030 if (tg3_tx_frag_set(tnapi, &entry, &budget, mapping, len, base_flags |
d1a3b737 8031 ((skb_shinfo(skb)->nr_frags == 0) ? TXD_FLAG_END : 0),
ba1142e4 8032 mss, vlan)) {
d1a3b737 8033 would_hit_hwbug = 1;
ba1142e4 8034 } else if (skb_shinfo(skb)->nr_frags > 0) {
92cd3a17
MC		 8035 u32 tmp_mss = mss;
8036
8037 if (!tg3_flag(tp, HW_TSO_1) &&
8038 !tg3_flag(tp, HW_TSO_2) &&
8039 !tg3_flag(tp, HW_TSO_3))
8040 tmp_mss = 0;
8041
c5665a53
MC		 8042 /* Now loop through additional data
8043 * fragments, and queue them.
8044 */
1da177e4
LT		 8045 last = skb_shinfo(skb)->nr_frags - 1;
8046 for (i = 0; i <= last; i++) {
8047 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
8048
9e903e08 8049 len = skb_frag_size(frag);
dc234d0b 8050 mapping = skb_frag_dma_map(&tp->pdev->dev, frag, 0,
5d6bcdfe 8051 len, DMA_TO_DEVICE);
1da177e4 8052
f3f3f27e 8053 tnapi->tx_buffers[entry].skb = NULL;
4e5e4f0d 8054 dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
f4188d8a 8055 mapping);
5d6bcdfe 8056 if (dma_mapping_error(&tp->pdev->dev, mapping))
f4188d8a 8057 goto dma_error;
1da177e4 8058
b9e45482
MC		 8059 if (!budget ||
8060 tg3_tx_frag_set(tnapi, &entry, &budget, mapping,
84b67b27
MC		 8061 len, base_flags |
8062 ((i == last) ? TXD_FLAG_END : 0),
b9e45482 8063 tmp_mss, vlan)) {
72f2afb8 8064 would_hit_hwbug = 1;
b9e45482
MC		 8065 break;
8066 }
1da177e4
LT		 8067 }
8068 }
8069
8070 if (would_hit_hwbug) {
0d681b27 8071 tg3_tx_skb_unmap(tnapi, tnapi->tx_prod, i);
1da177e4 8072
d3f6f3a1
MC		 8073 if (mss) {
8074 /* If it's a TSO packet, do GSO instead of
8075 * allocating and copying to a large linear SKB
8076 */
8077 if (ip_tot_len) {
8078 iph->check = ip_csum;
8079 iph->tot_len = ip_tot_len;
8080 }
8081 tcph->check = tcp_csum;
4d8fdc95 8082 return tg3_tso_bug(tp, tnapi, txq, skb);
d3f6f3a1
MC		 8083 }
8084
1da177e4
LT		 8085 /* If the workaround fails due to memory/mapping
8086 * failure, silently drop this packet.
8087 */
84b67b27
MC		 8088 entry = tnapi->tx_prod;
8089 budget = tg3_tx_avail(tnapi);
f7ff1987 8090 if (tigon3_dma_hwbug_workaround(tnapi, &skb, &entry, &budget,
84b67b27 8091 base_flags, mss, vlan))
48855432 8092 goto drop_nofree;
1da177e4
LT		 8093 }
8094
d515b450 8095 skb_tx_timestamp(skb);
5cb917bc 8096 netdev_tx_sent_queue(txq, skb->len);
d515b450 8097
6541b806
MC		 8098 /* Sync BD data before updating mailbox */
8099 wmb();
8100
1da177e4 8101 /* Packets are ready, update Tx producer idx local and on card. */
24f4efd4 8102 tw32_tx_mbox(tnapi->prodmbox, entry);
1da177e4 8103
f3f3f27e
MC		 8104 tnapi->tx_prod = entry;
8105 if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
24f4efd4 8106 netif_tx_stop_queue(txq);
f65aac16
MC		 8107
8108 /* netif_tx_stop_queue() must be done before checking
8109 * checking tx index in tg3_tx_avail() below, because in
8110 * tg3_tx(), we update tx index before checking for
8111 * netif_tx_queue_stopped().
8112 */
8113 smp_mb();
f3f3f27e 8114 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
24f4efd4 8115 netif_tx_wake_queue(txq);
51b91468 8116 }
1da177e4 8117
cdd0db05 8118 mmiowb();
1da177e4 8119 return NETDEV_TX_OK;
f4188d8a
AD		 8120
8121dma_error:
ba1142e4 8122 tg3_tx_skb_unmap(tnapi, tnapi->tx_prod, --i);
432aa7ed 8123 tnapi->tx_buffers[tnapi->tx_prod].skb = NULL;
48855432 8124drop:
497a27b9 8125 dev_kfree_skb_any(skb);
48855432
ED		 8126drop_nofree:
8127 tp->tx_dropped++;
f4188d8a 8128 return NETDEV_TX_OK;
1da177e4
LT		 8129}
8130
6e01b20b
MC		 8131static void tg3_mac_loopback(struct tg3 *tp, bool enable)
8132{
8133 if (enable) {
8134 tp->mac_mode &= ~(MAC_MODE_HALF_DUPLEX |
8135 MAC_MODE_PORT_MODE_MASK);
8136
8137 tp->mac_mode |= MAC_MODE_PORT_INT_LPBACK;
8138
8139 if (!tg3_flag(tp, 5705_PLUS))
8140 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
8141
8142 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
8143 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
8144 else
8145 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
8146 } else {
8147 tp->mac_mode &= ~MAC_MODE_PORT_INT_LPBACK;
8148
8149 if (tg3_flag(tp, 5705_PLUS) ||
8150 (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) ||
4153577a 8151 tg3_asic_rev(tp) == ASIC_REV_5700)
6e01b20b
MC		 8152 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
8153 }
8154
8155 tw32(MAC_MODE, tp->mac_mode);
8156 udelay(40);
8157}
8158
941ec90f 8159static int tg3_phy_lpbk_set(struct tg3 *tp, u32 speed, bool extlpbk)
5e5a7f37 8160{
941ec90f 8161 u32 val, bmcr, mac_mode, ptest = 0;
5e5a7f37
MC		 8162
8163 tg3_phy_toggle_apd(tp, false);
953c96e0 8164 tg3_phy_toggle_automdix(tp, false);
5e5a7f37 8165
941ec90f
MC		 8166 if (extlpbk && tg3_phy_set_extloopbk(tp))
8167 return -EIO;
8168
8169 bmcr = BMCR_FULLDPLX;
5e5a7f37
MC		 8170 switch (speed) {
8171 case SPEED_10:
8172 break;
8173 case SPEED_100:
8174 bmcr |= BMCR_SPEED100;
8175 break;
8176 case SPEED_1000:
8177 default:
8178 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
8179 speed = SPEED_100;
8180 bmcr |= BMCR_SPEED100;
8181 } else {
8182 speed = SPEED_1000;
8183 bmcr |= BMCR_SPEED1000;
8184 }
8185 }
8186
941ec90f
MC		 8187 if (extlpbk) {
8188 if (!(tp->phy_flags & TG3_PHYFLG_IS_FET)) {
8189 tg3_readphy(tp, MII_CTRL1000, &val);
8190 val |= CTL1000_AS_MASTER |
8191 CTL1000_ENABLE_MASTER;
8192 tg3_writephy(tp, MII_CTRL1000, val);
8193 } else {
8194 ptest = MII_TG3_FET_PTEST_TRIM_SEL |
8195 MII_TG3_FET_PTEST_TRIM_2;
8196 tg3_writephy(tp, MII_TG3_FET_PTEST, ptest);
8197 }
8198 } else
8199 bmcr |= BMCR_LOOPBACK;
8200
5e5a7f37
MC		 8201 tg3_writephy(tp, MII_BMCR, bmcr);
8202
8203 /* The write needs to be flushed for the FETs */
8204 if (tp->phy_flags & TG3_PHYFLG_IS_FET)
8205 tg3_readphy(tp, MII_BMCR, &bmcr);
8206
8207 udelay(40);
8208
8209 if ((tp->phy_flags & TG3_PHYFLG_IS_FET) &&
4153577a 8210 tg3_asic_rev(tp) == ASIC_REV_5785) {
941ec90f 8211 tg3_writephy(tp, MII_TG3_FET_PTEST, ptest |
5e5a7f37
MC		 8212 MII_TG3_FET_PTEST_FRC_TX_LINK |
8213 MII_TG3_FET_PTEST_FRC_TX_LOCK);
8214
8215 /* The write needs to be flushed for the AC131 */
8216 tg3_readphy(tp, MII_TG3_FET_PTEST, &val);
8217 }
8218
8219 /* Reset to prevent losing 1st rx packet intermittently */
8220 if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
8221 tg3_flag(tp, 5780_CLASS)) {
8222 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
8223 udelay(10);
8224 tw32_f(MAC_RX_MODE, tp->rx_mode);
8225 }
8226
8227 mac_mode = tp->mac_mode &
8228 ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
8229 if (speed == SPEED_1000)
8230 mac_mode |= MAC_MODE_PORT_MODE_GMII;
8231 else
8232 mac_mode |= MAC_MODE_PORT_MODE_MII;
8233
4153577a 8234 if (tg3_asic_rev(tp) == ASIC_REV_5700) {
5e5a7f37
MC		 8235 u32 masked_phy_id = tp->phy_id & TG3_PHY_ID_MASK;
8236
8237 if (masked_phy_id == TG3_PHY_ID_BCM5401)
8238 mac_mode &= ~MAC_MODE_LINK_POLARITY;
8239 else if (masked_phy_id == TG3_PHY_ID_BCM5411)
8240 mac_mode |= MAC_MODE_LINK_POLARITY;
8241
8242 tg3_writephy(tp, MII_TG3_EXT_CTRL,
8243 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
8244 }
8245
8246 tw32(MAC_MODE, mac_mode);
8247 udelay(40);
941ec90f
MC		 8248
8249 return 0;
5e5a7f37
MC		 8250}
8251
c8f44aff 8252static void tg3_set_loopback(struct net_device *dev, netdev_features_t features)
06c03c02
MB		 8253{
8254 struct tg3 *tp = netdev_priv(dev);
8255
8256 if (features & NETIF_F_LOOPBACK) {
8257 if (tp->mac_mode & MAC_MODE_PORT_INT_LPBACK)
8258 return;
8259
06c03c02 8260 spin_lock_bh(&tp->lock);
6e01b20b 8261 tg3_mac_loopback(tp, true);
06c03c02
MB		 8262 netif_carrier_on(tp->dev);
8263 spin_unlock_bh(&tp->lock);
8264 netdev_info(dev, "Internal MAC loopback mode enabled.\n");
8265 } else {
8266 if (!(tp->mac_mode & MAC_MODE_PORT_INT_LPBACK))
8267 return;
8268
06c03c02 8269 spin_lock_bh(&tp->lock);
6e01b20b 8270 tg3_mac_loopback(tp, false);
06c03c02 8271 /* Force link status check */
953c96e0 8272 tg3_setup_phy(tp, true);
06c03c02
MB		 8273 spin_unlock_bh(&tp->lock);
8274 netdev_info(dev, "Internal MAC loopback mode disabled.\n");
8275 }
8276}
8277
c8f44aff
MM		 8278static netdev_features_t tg3_fix_features(struct net_device *dev,
8279 netdev_features_t features)
dc668910
MM		 8280{
8281 struct tg3 *tp = netdev_priv(dev);
8282
63c3a66f 8283 if (dev->mtu > ETH_DATA_LEN && tg3_flag(tp, 5780_CLASS))
dc668910
MM		 8284 features &= ~NETIF_F_ALL_TSO;
8285
8286 return features;
8287}
8288
c8f44aff 8289static int tg3_set_features(struct net_device *dev, netdev_features_t features)
06c03c02 8290{
c8f44aff 8291 netdev_features_t changed = dev->features ^ features;
06c03c02
MB		 8292
8293 if ((changed & NETIF_F_LOOPBACK) && netif_running(dev))
8294 tg3_set_loopback(dev, features);
8295
8296 return 0;
8297}
8298
21f581a5
MC		 8299static void tg3_rx_prodring_free(struct tg3 *tp,
8300 struct tg3_rx_prodring_set *tpr)
1da177e4 8301{
1da177e4
LT		 8302 int i;
8303
8fea32b9 8304 if (tpr != &tp->napi[0].prodring) {
b196c7e4 8305 for (i = tpr->rx_std_cons_idx; i != tpr->rx_std_prod_idx;
2c49a44d 8306 i = (i + 1) & tp->rx_std_ring_mask)
9205fd9c 8307 tg3_rx_data_free(tp, &tpr->rx_std_buffers[i],
b196c7e4
MC		 8308 tp->rx_pkt_map_sz);
8309
63c3a66f 8310 if (tg3_flag(tp, JUMBO_CAPABLE)) {
b196c7e4
MC		 8311 for (i = tpr->rx_jmb_cons_idx;
8312 i != tpr->rx_jmb_prod_idx;
2c49a44d 8313 i = (i + 1) & tp->rx_jmb_ring_mask) {
9205fd9c 8314 tg3_rx_data_free(tp, &tpr->rx_jmb_buffers[i],
b196c7e4
MC		 8315 TG3_RX_JMB_MAP_SZ);
8316 }
8317 }
8318
2b2cdb65 8319 return;
b196c7e4 8320 }
1da177e4 8321
2c49a44d 8322 for (i = 0; i <= tp->rx_std_ring_mask; i++)
9205fd9c 8323 tg3_rx_data_free(tp, &tpr->rx_std_buffers[i],
2b2cdb65 8324 tp->rx_pkt_map_sz);
1da177e4 8325
63c3a66f 8326 if (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS)) {
2c49a44d 8327 for (i = 0; i <= tp->rx_jmb_ring_mask; i++)
9205fd9c 8328 tg3_rx_data_free(tp, &tpr->rx_jmb_buffers[i],
2b2cdb65 8329 TG3_RX_JMB_MAP_SZ);
1da177e4
LT		 8330 }
8331}
8332
c6cdf436 8333/* Initialize rx rings for packet processing.
1da177e4
LT		 8334 *
8335 * The chip has been shut down and the driver detached from
8336 * the networking, so no interrupts or new tx packets will
8337 * end up in the driver. tp->{tx,}lock are held and thus
8338 * we may not sleep.
8339 */
21f581a5
MC		 8340static int tg3_rx_prodring_alloc(struct tg3 *tp,
8341 struct tg3_rx_prodring_set *tpr)
1da177e4 8342{
287be12e 8343 u32 i, rx_pkt_dma_sz;
1da177e4 8344
b196c7e4
MC		 8345 tpr->rx_std_cons_idx = 0;
8346 tpr->rx_std_prod_idx = 0;
8347 tpr->rx_jmb_cons_idx = 0;
8348 tpr->rx_jmb_prod_idx = 0;
8349
8fea32b9 8350 if (tpr != &tp->napi[0].prodring) {
2c49a44d
MC		 8351 memset(&tpr->rx_std_buffers[0], 0,
8352 TG3_RX_STD_BUFF_RING_SIZE(tp));
48035728 8353 if (tpr->rx_jmb_buffers)
2b2cdb65 8354 memset(&tpr->rx_jmb_buffers[0], 0,
2c49a44d 8355 TG3_RX_JMB_BUFF_RING_SIZE(tp));
2b2cdb65
MC		 8356 goto done;
8357 }
8358
1da177e4 8359 /* Zero out all descriptors. */
2c49a44d 8360 memset(tpr->rx_std, 0, TG3_RX_STD_RING_BYTES(tp));
1da177e4 8361
287be12e 8362 rx_pkt_dma_sz = TG3_RX_STD_DMA_SZ;
63c3a66f 8363 if (tg3_flag(tp, 5780_CLASS) &&
287be12e
MC		 8364 tp->dev->mtu > ETH_DATA_LEN)
8365 rx_pkt_dma_sz = TG3_RX_JMB_DMA_SZ;
8366 tp->rx_pkt_map_sz = TG3_RX_DMA_TO_MAP_SZ(rx_pkt_dma_sz);
7e72aad4 8367
1da177e4
LT		 8368 /* Initialize invariants of the rings, we only set this
8369 * stuff once. This works because the card does not
8370 * write into the rx buffer posting rings.
8371 */
2c49a44d 8372 for (i = 0; i <= tp->rx_std_ring_mask; i++) {
1da177e4
LT		 8373 struct tg3_rx_buffer_desc *rxd;
8374
21f581a5 8375 rxd = &tpr->rx_std[i];
287be12e 8376 rxd->idx_len = rx_pkt_dma_sz << RXD_LEN_SHIFT;
1da177e4
LT		 8377 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
8378 rxd->opaque = (RXD_OPAQUE_RING_STD |
8379 (i << RXD_OPAQUE_INDEX_SHIFT));
8380 }
8381
1da177e4
LT		 8382 /* Now allocate fresh SKBs for each rx ring. */
8383 for (i = 0; i < tp->rx_pending; i++) {
8d4057a9
ED		 8384 unsigned int frag_size;
8385
8386 if (tg3_alloc_rx_data(tp, tpr, RXD_OPAQUE_RING_STD, i,
8387 &frag_size) < 0) {
5129c3a3
MC		 8388 netdev_warn(tp->dev,
8389 "Using a smaller RX standard ring. Only "
8390 "%d out of %d buffers were allocated "
8391 "successfully\n", i, tp->rx_pending);
32d8c572 8392 if (i == 0)
cf7a7298 8393 goto initfail;
32d8c572 8394 tp->rx_pending = i;
1da177e4 8395 break;
32d8c572 8396 }
1da177e4
LT		 8397 }
8398
63c3a66f 8399 if (!tg3_flag(tp, JUMBO_CAPABLE) || tg3_flag(tp, 5780_CLASS))
cf7a7298
MC		 8400 goto done;
8401
2c49a44d 8402 memset(tpr->rx_jmb, 0, TG3_RX_JMB_RING_BYTES(tp));
cf7a7298 8403
63c3a66f 8404 if (!tg3_flag(tp, JUMBO_RING_ENABLE))
0d86df80 8405 goto done;
cf7a7298 8406
2c49a44d 8407 for (i = 0; i <= tp->rx_jmb_ring_mask; i++) {
0d86df80
MC		 8408 struct tg3_rx_buffer_desc *rxd;
8409
8410 rxd = &tpr->rx_jmb[i].std;
8411 rxd->idx_len = TG3_RX_JMB_DMA_SZ << RXD_LEN_SHIFT;
8412 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
8413 RXD_FLAG_JUMBO;
8414 rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
8415 (i << RXD_OPAQUE_INDEX_SHIFT));
8416 }
8417
8418 for (i = 0; i < tp->rx_jumbo_pending; i++) {
8d4057a9
ED		 8419 unsigned int frag_size;
8420
8421 if (tg3_alloc_rx_data(tp, tpr, RXD_OPAQUE_RING_JUMBO, i,
8422 &frag_size) < 0) {
5129c3a3
MC		 8423 netdev_warn(tp->dev,
8424 "Using a smaller RX jumbo ring. Only %d "
8425 "out of %d buffers were allocated "
8426 "successfully\n", i, tp->rx_jumbo_pending);
0d86df80
MC		 8427 if (i == 0)
8428 goto initfail;
8429 tp->rx_jumbo_pending = i;
8430 break;
1da177e4
LT		 8431 }
8432 }
cf7a7298
MC		 8433
8434done:
32d8c572 8435 return 0;
cf7a7298
MC		 8436
8437initfail:
21f581a5 8438 tg3_rx_prodring_free(tp, tpr);
cf7a7298 8439 return -ENOMEM;
1da177e4
LT		 8440}
8441
21f581a5
MC		 8442static void tg3_rx_prodring_fini(struct tg3 *tp,
8443 struct tg3_rx_prodring_set *tpr)
1da177e4 8444{
21f581a5
MC		 8445 kfree(tpr->rx_std_buffers);
8446 tpr->rx_std_buffers = NULL;
8447 kfree(tpr->rx_jmb_buffers);
8448 tpr->rx_jmb_buffers = NULL;
8449 if (tpr->rx_std) {
4bae65c8
MC		 8450 dma_free_coherent(&tp->pdev->dev, TG3_RX_STD_RING_BYTES(tp),
8451 tpr->rx_std, tpr->rx_std_mapping);
21f581a5 8452 tpr->rx_std = NULL;
1da177e4 8453 }
21f581a5 8454 if (tpr->rx_jmb) {
4bae65c8
MC		 8455 dma_free_coherent(&tp->pdev->dev, TG3_RX_JMB_RING_BYTES(tp),
8456 tpr->rx_jmb, tpr->rx_jmb_mapping);
21f581a5 8457 tpr->rx_jmb = NULL;
1da177e4 8458 }
cf7a7298
MC		 8459}
8460
21f581a5
MC		 8461static int tg3_rx_prodring_init(struct tg3 *tp,
8462 struct tg3_rx_prodring_set *tpr)
cf7a7298 8463{
2c49a44d
MC		 8464 tpr->rx_std_buffers = kzalloc(TG3_RX_STD_BUFF_RING_SIZE(tp),
8465 GFP_KERNEL);
21f581a5 8466 if (!tpr->rx_std_buffers)
cf7a7298
MC		 8467 return -ENOMEM;
8468
4bae65c8
MC		 8469 tpr->rx_std = dma_alloc_coherent(&tp->pdev->dev,
8470 TG3_RX_STD_RING_BYTES(tp),
8471 &tpr->rx_std_mapping,
8472 GFP_KERNEL);
21f581a5 8473 if (!tpr->rx_std)
cf7a7298
MC		 8474 goto err_out;
8475
63c3a66f 8476 if (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS)) {
2c49a44d 8477 tpr->rx_jmb_buffers = kzalloc(TG3_RX_JMB_BUFF_RING_SIZE(tp),
21f581a5
MC		 8478 GFP_KERNEL);
8479 if (!tpr->rx_jmb_buffers)
cf7a7298
MC		 8480 goto err_out;
8481
4bae65c8
MC		 8482 tpr->rx_jmb = dma_alloc_coherent(&tp->pdev->dev,
8483 TG3_RX_JMB_RING_BYTES(tp),
8484 &tpr->rx_jmb_mapping,
8485 GFP_KERNEL);
21f581a5 8486 if (!tpr->rx_jmb)
cf7a7298
MC		 8487 goto err_out;
8488 }
8489
8490 return 0;
8491
8492err_out:
21f581a5 8493 tg3_rx_prodring_fini(tp, tpr);
cf7a7298
MC		 8494 return -ENOMEM;
8495}
8496
8497/* Free up pending packets in all rx/tx rings.
8498 *
8499 * The chip has been shut down and the driver detached from
8500 * the networking, so no interrupts or new tx packets will
8501 * end up in the driver. tp->{tx,}lock is not held and we are not
8502 * in an interrupt context and thus may sleep.
8503 */
8504static void tg3_free_rings(struct tg3 *tp)
8505{
f77a6a8e 8506 int i, j;
cf7a7298 8507
f77a6a8e
MC		 8508 for (j = 0; j < tp->irq_cnt; j++) {
8509 struct tg3_napi *tnapi = &tp->napi[j];
cf7a7298 8510
8fea32b9 8511 tg3_rx_prodring_free(tp, &tnapi->prodring);
b28f6428 8512
0c1d0e2b
MC		 8513 if (!tnapi->tx_buffers)
8514 continue;
8515
0d681b27
MC		 8516 for (i = 0; i < TG3_TX_RING_SIZE; i++) {
8517 struct sk_buff *skb = tnapi->tx_buffers[i].skb;
cf7a7298 8518
0d681b27 8519 if (!skb)
f77a6a8e 8520 continue;
cf7a7298 8521
ba1142e4
MC		 8522 tg3_tx_skb_unmap(tnapi, i,
8523 skb_shinfo(skb)->nr_frags - 1);
f77a6a8e
MC		 8524
8525 dev_kfree_skb_any(skb);
8526 }
5cb917bc 8527 netdev_tx_reset_queue(netdev_get_tx_queue(tp->dev, j));
2b2cdb65 8528 }
cf7a7298
MC		 8529}
8530
8531/* Initialize tx/rx rings for packet processing.
8532 *
8533 * The chip has been shut down and the driver detached from
8534 * the networking, so no interrupts or new tx packets will
8535 * end up in the driver. tp->{tx,}lock are held and thus
8536 * we may not sleep.
8537 */
8538static int tg3_init_rings(struct tg3 *tp)
8539{
f77a6a8e 8540 int i;
72334482 8541
cf7a7298
MC		 8542 /* Free up all the SKBs. */
8543 tg3_free_rings(tp);
8544
f77a6a8e
MC		 8545 for (i = 0; i < tp->irq_cnt; i++) {
8546 struct tg3_napi *tnapi = &tp->napi[i];
8547
8548 tnapi->last_tag = 0;
8549 tnapi->last_irq_tag = 0;
8550 tnapi->hw_status->status = 0;
8551 tnapi->hw_status->status_tag = 0;
8552 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
cf7a7298 8553
f77a6a8e
MC		 8554 tnapi->tx_prod = 0;
8555 tnapi->tx_cons = 0;
0c1d0e2b
MC		 8556 if (tnapi->tx_ring)
8557 memset(tnapi->tx_ring, 0, TG3_TX_RING_BYTES);
f77a6a8e
MC		 8558
8559 tnapi->rx_rcb_ptr = 0;
0c1d0e2b
MC		 8560 if (tnapi->rx_rcb)
8561 memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
2b2cdb65 8562
8fea32b9 8563 if (tg3_rx_prodring_alloc(tp, &tnapi->prodring)) {
e4af1af9 8564 tg3_free_rings(tp);
2b2cdb65 8565 return -ENOMEM;
e4af1af9 8566 }
f77a6a8e 8567 }
72334482 8568
2b2cdb65 8569 return 0;
cf7a7298
MC		 8570}
8571
49a359e3 8572static void tg3_mem_tx_release(struct tg3 *tp)
cf7a7298 8573{
f77a6a8e 8574 int i;
898a56f8 8575
49a359e3 8576 for (i = 0; i < tp->irq_max; i++) {
f77a6a8e
MC		 8577 struct tg3_napi *tnapi = &tp->napi[i];
8578
8579 if (tnapi->tx_ring) {
4bae65c8 8580 dma_free_coherent(&tp->pdev->dev, TG3_TX_RING_BYTES,
f77a6a8e
MC		 8581 tnapi->tx_ring, tnapi->tx_desc_mapping);
8582 tnapi->tx_ring = NULL;
8583 }
8584
8585 kfree(tnapi->tx_buffers);
8586 tnapi->tx_buffers = NULL;
49a359e3
MC		 8587 }
8588}
f77a6a8e 8589
49a359e3
MC		 8590static int tg3_mem_tx_acquire(struct tg3 *tp)
8591{
8592 int i;
8593 struct tg3_napi *tnapi = &tp->napi[0];
8594
8595 /* If multivector TSS is enabled, vector 0 does not handle
8596 * tx interrupts. Don't allocate any resources for it.
8597 */
8598 if (tg3_flag(tp, ENABLE_TSS))
8599 tnapi++;
8600
8601 for (i = 0; i < tp->txq_cnt; i++, tnapi++) {
8602 tnapi->tx_buffers = kzalloc(sizeof(struct tg3_tx_ring_info) *
8603 TG3_TX_RING_SIZE, GFP_KERNEL);
8604 if (!tnapi->tx_buffers)
8605 goto err_out;
8606
8607 tnapi->tx_ring = dma_alloc_coherent(&tp->pdev->dev,
8608 TG3_TX_RING_BYTES,
8609 &tnapi->tx_desc_mapping,
8610 GFP_KERNEL);
8611 if (!tnapi->tx_ring)
8612 goto err_out;
8613 }
8614
8615 return 0;
8616
8617err_out:
8618 tg3_mem_tx_release(tp);
8619 return -ENOMEM;
8620}
8621
8622static void tg3_mem_rx_release(struct tg3 *tp)
8623{
8624 int i;
8625
8626 for (i = 0; i < tp->irq_max; i++) {
8627 struct tg3_napi *tnapi = &tp->napi[i];
f77a6a8e 8628
8fea32b9
MC		 8629 tg3_rx_prodring_fini(tp, &tnapi->prodring);
8630
49a359e3
MC		 8631 if (!tnapi->rx_rcb)
8632 continue;
8633
8634 dma_free_coherent(&tp->pdev->dev,
8635 TG3_RX_RCB_RING_BYTES(tp),
8636 tnapi->rx_rcb,
8637 tnapi->rx_rcb_mapping);
8638 tnapi->rx_rcb = NULL;
8639 }
8640}
8641
8642static int tg3_mem_rx_acquire(struct tg3 *tp)
8643{
8644 unsigned int i, limit;
8645
8646 limit = tp->rxq_cnt;
8647
8648 /* If RSS is enabled, we need a (dummy) producer ring
8649 * set on vector zero. This is the true hw prodring.
8650 */
8651 if (tg3_flag(tp, ENABLE_RSS))
8652 limit++;
8653
8654 for (i = 0; i < limit; i++) {
8655 struct tg3_napi *tnapi = &tp->napi[i];
8656
8657 if (tg3_rx_prodring_init(tp, &tnapi->prodring))
8658 goto err_out;
8659
8660 /* If multivector RSS is enabled, vector 0
8661 * does not handle rx or tx interrupts.
8662 * Don't allocate any resources for it.
8663 */
8664 if (!i && tg3_flag(tp, ENABLE_RSS))
8665 continue;
8666
ede23fa8
JP		 8667 tnapi->rx_rcb = dma_zalloc_coherent(&tp->pdev->dev,
8668 TG3_RX_RCB_RING_BYTES(tp),
8669 &tnapi->rx_rcb_mapping,
8670 GFP_KERNEL);
49a359e3
MC		 8671 if (!tnapi->rx_rcb)
8672 goto err_out;
49a359e3
MC		 8673 }
8674
8675 return 0;
8676
8677err_out:
8678 tg3_mem_rx_release(tp);
8679 return -ENOMEM;
8680}
8681
8682/*
8683 * Must not be invoked with interrupt sources disabled and
8684 * the hardware shutdown down.
8685 */
8686static void tg3_free_consistent(struct tg3 *tp)
8687{
8688 int i;
8689
8690 for (i = 0; i < tp->irq_cnt; i++) {
8691 struct tg3_napi *tnapi = &tp->napi[i];
8692
f77a6a8e 8693 if (tnapi->hw_status) {
4bae65c8
MC		 8694 dma_free_coherent(&tp->pdev->dev, TG3_HW_STATUS_SIZE,
8695 tnapi->hw_status,
8696 tnapi->status_mapping);
f77a6a8e
MC		 8697 tnapi->hw_status = NULL;
8698 }
1da177e4 8699 }
f77a6a8e 8700
49a359e3
MC		 8701 tg3_mem_rx_release(tp);
8702 tg3_mem_tx_release(tp);
8703
1da177e4 8704 if (tp->hw_stats) {
4bae65c8
MC		 8705 dma_free_coherent(&tp->pdev->dev, sizeof(struct tg3_hw_stats),
8706 tp->hw_stats, tp->stats_mapping);
1da177e4
LT		 8707 tp->hw_stats = NULL;
8708 }
8709}
8710
8711/*
8712 * Must not be invoked with interrupt sources disabled and
8713 * the hardware shutdown down. Can sleep.
8714 */
8715static int tg3_alloc_consistent(struct tg3 *tp)
8716{
f77a6a8e 8717 int i;
898a56f8 8718
ede23fa8
JP		 8719 tp->hw_stats = dma_zalloc_coherent(&tp->pdev->dev,
8720 sizeof(struct tg3_hw_stats),
8721 &tp->stats_mapping, GFP_KERNEL);
f77a6a8e 8722 if (!tp->hw_stats)
1da177e4
LT		 8723 goto err_out;
8724
f77a6a8e
MC		 8725 for (i = 0; i < tp->irq_cnt; i++) {
8726 struct tg3_napi *tnapi = &tp->napi[i];
8d9d7cfc 8727 struct tg3_hw_status *sblk;
1da177e4 8728
ede23fa8
JP		 8729 tnapi->hw_status = dma_zalloc_coherent(&tp->pdev->dev,
8730 TG3_HW_STATUS_SIZE,
8731 &tnapi->status_mapping,
8732 GFP_KERNEL);
f77a6a8e
MC		 8733 if (!tnapi->hw_status)
8734 goto err_out;
898a56f8 8735
8d9d7cfc
MC		 8736 sblk = tnapi->hw_status;
8737
49a359e3 8738 if (tg3_flag(tp, ENABLE_RSS)) {
86449944 8739 u16 *prodptr = NULL;
8fea32b9 8740
49a359e3
MC		 8741 /*
8742 * When RSS is enabled, the status block format changes
8743 * slightly. The "rx_jumbo_consumer", "reserved",
8744 * and "rx_mini_consumer" members get mapped to the
8745 * other three rx return ring producer indexes.
8746 */
8747 switch (i) {
8748 case 1:
8749 prodptr = &sblk->idx[0].rx_producer;
8750 break;
8751 case 2:
8752 prodptr = &sblk->rx_jumbo_consumer;
8753 break;
8754 case 3:
8755 prodptr = &sblk->reserved;
8756 break;
8757 case 4:
8758 prodptr = &sblk->rx_mini_consumer;
f891ea16
MC		 8759 break;
8760 }
49a359e3
MC		 8761 tnapi->rx_rcb_prod_idx = prodptr;
8762 } else {
8d9d7cfc 8763 tnapi->rx_rcb_prod_idx = &sblk->idx[0].rx_producer;
8d9d7cfc 8764 }
f77a6a8e 8765 }
1da177e4 8766
49a359e3
MC		 8767 if (tg3_mem_tx_acquire(tp) || tg3_mem_rx_acquire(tp))
8768 goto err_out;
8769
1da177e4
LT		 8770 return 0;
8771
8772err_out:
8773 tg3_free_consistent(tp);
8774 return -ENOMEM;
8775}
8776
8777#define MAX_WAIT_CNT 1000
8778
8779/* To stop a block, clear the enable bit and poll till it
8780 * clears. tp->lock is held.
8781 */
953c96e0 8782static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, bool silent)
1da177e4
LT		 8783{
8784 unsigned int i;
8785 u32 val;
8786
63c3a66f 8787 if (tg3_flag(tp, 5705_PLUS)) {
1da177e4
LT		 8788 switch (ofs) {
8789 case RCVLSC_MODE:
8790 case DMAC_MODE:
8791 case MBFREE_MODE:
8792 case BUFMGR_MODE:
8793 case MEMARB_MODE:
8794 /* We can't enable/disable these bits of the
8795 * 5705/5750, just say success.
8796 */
8797 return 0;
8798
8799 default:
8800 break;
855e1111 8801 }
1da177e4
LT		 8802 }
8803
8804 val = tr32(ofs);
8805 val &= ~enable_bit;
8806 tw32_f(ofs, val);
8807
8808 for (i = 0; i < MAX_WAIT_CNT; i++) {
6d446ec3
GS		 8809 if (pci_channel_offline(tp->pdev)) {
8810 dev_err(&tp->pdev->dev,
8811 "tg3_stop_block device offline, "
8812 "ofs=%lx enable_bit=%x\n",
8813 ofs, enable_bit);
8814 return -ENODEV;
8815 }
8816
1da177e4
LT		 8817 udelay(100);
8818 val = tr32(ofs);
8819 if ((val & enable_bit) == 0)
8820 break;
8821 }
8822
b3b7d6be 8823 if (i == MAX_WAIT_CNT && !silent) {
2445e461
MC		 8824 dev_err(&tp->pdev->dev,
8825 "tg3_stop_block timed out, ofs=%lx enable_bit=%x\n",
8826 ofs, enable_bit);
1da177e4
LT		 8827 return -ENODEV;
8828 }
8829
8830 return 0;
8831}
8832
8833/* tp->lock is held. */
953c96e0 8834static int tg3_abort_hw(struct tg3 *tp, bool silent)
1da177e4
LT		 8835{
8836 int i, err;
8837
8838 tg3_disable_ints(tp);
8839
6d446ec3
GS		 8840 if (pci_channel_offline(tp->pdev)) {
8841 tp->rx_mode &= ~(RX_MODE_ENABLE | TX_MODE_ENABLE);
8842 tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
8843 err = -ENODEV;
8844 goto err_no_dev;
8845 }
8846
1da177e4
LT		 8847 tp->rx_mode &= ~RX_MODE_ENABLE;
8848 tw32_f(MAC_RX_MODE, tp->rx_mode);
8849 udelay(10);
8850
b3b7d6be
DM		 8851 err = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
8852 err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
8853 err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
8854 err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
8855 err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
8856 err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
8857
8858 err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
8859 err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
8860 err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
8861 err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
8862 err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
8863 err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
8864 err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
1da177e4
LT		 8865
8866 tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
8867 tw32_f(MAC_MODE, tp->mac_mode);
8868 udelay(40);
8869
8870 tp->tx_mode &= ~TX_MODE_ENABLE;
8871 tw32_f(MAC_TX_MODE, tp->tx_mode);
8872
8873 for (i = 0; i < MAX_WAIT_CNT; i++) {
8874 udelay(100);
8875 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
8876 break;
8877 }
8878 if (i >= MAX_WAIT_CNT) {
ab96b241
MC		 8879 dev_err(&tp->pdev->dev,
8880 "%s timed out, TX_MODE_ENABLE will not clear "
8881 "MAC_TX_MODE=%08x\n", __func__, tr32(MAC_TX_MODE));
e6de8ad1 8882 err |= -ENODEV;
1da177e4
LT		 8883 }
8884
e6de8ad1 8885 err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
b3b7d6be
DM		 8886 err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
8887 err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
1da177e4
LT		 8888
8889 tw32(FTQ_RESET, 0xffffffff);
8890 tw32(FTQ_RESET, 0x00000000);
8891
b3b7d6be
DM		 8892 err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
8893 err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
1da177e4 8894
6d446ec3 8895err_no_dev:
f77a6a8e
MC		 8896 for (i = 0; i < tp->irq_cnt; i++) {
8897 struct tg3_napi *tnapi = &tp->napi[i];
8898 if (tnapi->hw_status)
8899 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
8900 }
1da177e4 8901
1da177e4
LT		 8902 return err;
8903}
8904
ee6a99b5
MC		 8905/* Save PCI command register before chip reset */
8906static void tg3_save_pci_state(struct tg3 *tp)
8907{
8a6eac90 8908 pci_read_config_word(tp->pdev, PCI_COMMAND, &tp->pci_cmd);
ee6a99b5
MC		 8909}
8910
8911/* Restore PCI state after chip reset */
8912static void tg3_restore_pci_state(struct tg3 *tp)
8913{
8914 u32 val;
8915
8916 /* Re-enable indirect register accesses. */
8917 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
8918 tp->misc_host_ctrl);
8919
8920 /* Set MAX PCI retry to zero. */
8921 val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
4153577a 8922 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5704_A0 &&
63c3a66f 8923 tg3_flag(tp, PCIX_MODE))
ee6a99b5 8924 val |= PCISTATE_RETRY_SAME_DMA;
0d3031d9 8925 /* Allow reads and writes to the APE register and memory space. */
63c3a66f 8926 if (tg3_flag(tp, ENABLE_APE))
0d3031d9 8927 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
f92d9dc1
MC		 8928 PCISTATE_ALLOW_APE_SHMEM_WR |
8929 PCISTATE_ALLOW_APE_PSPACE_WR;
ee6a99b5
MC		 8930 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
8931
8a6eac90 8932 pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd);
ee6a99b5 8933
2c55a3d0
MC		 8934 if (!tg3_flag(tp, PCI_EXPRESS)) {
8935 pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
8936 tp->pci_cacheline_sz);
8937 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
8938 tp->pci_lat_timer);
114342f2 8939 }
5f5c51e3 8940
ee6a99b5 8941 /* Make sure PCI-X relaxed ordering bit is clear. */
63c3a66f 8942 if (tg3_flag(tp, PCIX_MODE)) {
9974a356
MC		 8943 u16 pcix_cmd;
8944
8945 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
8946 &pcix_cmd);
8947 pcix_cmd &= ~PCI_X_CMD_ERO;
8948 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
8949 pcix_cmd);
8950 }
ee6a99b5 8951
63c3a66f 8952 if (tg3_flag(tp, 5780_CLASS)) {
ee6a99b5
MC		 8953
8954 /* Chip reset on 5780 will reset MSI enable bit,
8955 * so need to restore it.
8956 */
63c3a66f 8957 if (tg3_flag(tp, USING_MSI)) {
ee6a99b5
MC		 8958 u16 ctrl;
8959
8960 pci_read_config_word(tp->pdev,
8961 tp->msi_cap + PCI_MSI_FLAGS,
8962 &ctrl);
8963 pci_write_config_word(tp->pdev,
8964 tp->msi_cap + PCI_MSI_FLAGS,
8965 ctrl | PCI_MSI_FLAGS_ENABLE);
8966 val = tr32(MSGINT_MODE);
8967 tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
8968 }
8969 }
8970}
8971
f82995b6
NS		 8972static void tg3_override_clk(struct tg3 *tp)
8973{
8974 u32 val;
8975
8976 switch (tg3_asic_rev(tp)) {
8977 case ASIC_REV_5717:
8978 val = tr32(TG3_CPMU_CLCK_ORIDE_ENABLE);
8979 tw32(TG3_CPMU_CLCK_ORIDE_ENABLE, val |
8980 TG3_CPMU_MAC_ORIDE_ENABLE);
8981 break;
8982
8983 case ASIC_REV_5719:
8984 case ASIC_REV_5720:
8985 tw32(TG3_CPMU_CLCK_ORIDE, CPMU_CLCK_ORIDE_MAC_ORIDE_EN);
8986 break;
8987
8988 default:
8989 return;
8990 }
8991}
8992
8993static void tg3_restore_clk(struct tg3 *tp)
8994{
8995 u32 val;
8996
8997 switch (tg3_asic_rev(tp)) {
8998 case ASIC_REV_5717:
8999 val = tr32(TG3_CPMU_CLCK_ORIDE_ENABLE);
9000 tw32(TG3_CPMU_CLCK_ORIDE_ENABLE,
9001 val & ~TG3_CPMU_MAC_ORIDE_ENABLE);
9002 break;
9003
9004 case ASIC_REV_5719:
9005 case ASIC_REV_5720:
9006 val = tr32(TG3_CPMU_CLCK_ORIDE);
9007 tw32(TG3_CPMU_CLCK_ORIDE, val & ~CPMU_CLCK_ORIDE_MAC_ORIDE_EN);
9008 break;
9009
9010 default:
9011 return;
9012 }
9013}
9014
1da177e4
LT		 9015/* tp->lock is held. */
9016static int tg3_chip_reset(struct tg3 *tp)
9017{
9018 u32 val;
1ee582d8 9019 void (*write_op)(struct tg3 *, u32, u32);
4f125f42 9020 int i, err;
1da177e4 9021
8496e85c
RW		 9022 if (!pci_device_is_present(tp->pdev))
9023 return -ENODEV;
9024
f49639e6
DM		 9025 tg3_nvram_lock(tp);
9026
77b483f1
MC		 9027 tg3_ape_lock(tp, TG3_APE_LOCK_GRC);
9028
f49639e6
DM		 9029 /* No matching tg3_nvram_unlock() after this because
9030 * chip reset below will undo the nvram lock.
9031 */
9032 tp->nvram_lock_cnt = 0;
1da177e4 9033
ee6a99b5
MC		 9034 /* GRC_MISC_CFG core clock reset will clear the memory
9035 * enable bit in PCI register 4 and the MSI enable bit
9036 * on some chips, so we save relevant registers here.
9037 */
9038 tg3_save_pci_state(tp);
9039
4153577a 9040 if (tg3_asic_rev(tp) == ASIC_REV_5752 ||
63c3a66f 9041 tg3_flag(tp, 5755_PLUS))
d9ab5ad1
MC		 9042 tw32(GRC_FASTBOOT_PC, 0);
9043
1da177e4
LT		 9044 /*
9045 * We must avoid the readl() that normally takes place.
9046 * It locks machines, causes machine checks, and other
9047 * fun things. So, temporarily disable the 5701
9048 * hardware workaround, while we do the reset.
9049 */
1ee582d8
MC		 9050 write_op = tp->write32;
9051 if (write_op == tg3_write_flush_reg32)
9052 tp->write32 = tg3_write32;
1da177e4 9053
d18edcb2
MC		 9054 /* Prevent the irq handler from reading or writing PCI registers
9055 * during chip reset when the memory enable bit in the PCI command
9056 * register may be cleared. The chip does not generate interrupt
9057 * at this time, but the irq handler may still be called due to irq
9058 * sharing or irqpoll.
9059 */
63c3a66f 9060 tg3_flag_set(tp, CHIP_RESETTING);
f77a6a8e
MC		 9061 for (i = 0; i < tp->irq_cnt; i++) {
9062 struct tg3_napi *tnapi = &tp->napi[i];
9063 if (tnapi->hw_status) {
9064 tnapi->hw_status->status = 0;
9065 tnapi->hw_status->status_tag = 0;
9066 }
9067 tnapi->last_tag = 0;
9068 tnapi->last_irq_tag = 0;
b8fa2f3a 9069 }
d18edcb2 9070 smp_mb();
4f125f42
MC		 9071
9072 for (i = 0; i < tp->irq_cnt; i++)
9073 synchronize_irq(tp->napi[i].irq_vec);
d18edcb2 9074
4153577a 9075 if (tg3_asic_rev(tp) == ASIC_REV_57780) {
255ca311
MC		 9076 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
9077 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
9078 }
9079
1da177e4
LT		 9080 /* do the reset */
9081 val = GRC_MISC_CFG_CORECLK_RESET;
9082
63c3a66f 9083 if (tg3_flag(tp, PCI_EXPRESS)) {
88075d91 9084 /* Force PCIe 1.0a mode */
4153577a 9085 if (tg3_asic_rev(tp) != ASIC_REV_5785 &&
63c3a66f 9086 !tg3_flag(tp, 57765_PLUS) &&
88075d91
MC		 9087 tr32(TG3_PCIE_PHY_TSTCTL) ==
9088 (TG3_PCIE_PHY_TSTCTL_PCIE10 | TG3_PCIE_PHY_TSTCTL_PSCRAM))
9089 tw32(TG3_PCIE_PHY_TSTCTL, TG3_PCIE_PHY_TSTCTL_PSCRAM);
9090
4153577a 9091 if (tg3_chip_rev_id(tp) != CHIPREV_ID_5750_A0) {
1da177e4
LT		 9092 tw32(GRC_MISC_CFG, (1 << 29));
9093 val |= (1 << 29);
9094 }
9095 }
9096
4153577a 9097 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
b5d3772c
MC		 9098 tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET);
9099 tw32(GRC_VCPU_EXT_CTRL,
9100 tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU);
9101 }
9102
f82995b6
NS		 9103 /* Set the clock to the highest frequency to avoid timeouts. With link
9104 * aware mode, the clock speed could be slow and bootcode does not
9105 * complete within the expected time. Override the clock to allow the
9106 * bootcode to finish sooner and then restore it.
9107 */
9108 tg3_override_clk(tp);
9109
f37500d3 9110 /* Manage gphy power for all CPMU absent PCIe devices. */
63c3a66f 9111 if (tg3_flag(tp, 5705_PLUS) && !tg3_flag(tp, CPMU_PRESENT))
1da177e4 9112 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
f37500d3 9113
1da177e4
LT		 9114 tw32(GRC_MISC_CFG, val);
9115
1ee582d8
MC		 9116 /* restore 5701 hardware bug workaround write method */
9117 tp->write32 = write_op;
1da177e4
LT		 9118
9119 /* Unfortunately, we have to delay before the PCI read back.
9120 * Some 575X chips even will not respond to a PCI cfg access
9121 * when the reset command is given to the chip.
9122 *
9123 * How do these hardware designers expect things to work
9124 * properly if the PCI write is posted for a long period
9125 * of time? It is always necessary to have some method by
9126 * which a register read back can occur to push the write
9127 * out which does the reset.
9128 *
9129 * For most tg3 variants the trick below was working.
9130 * Ho hum...
9131 */
9132 udelay(120);
9133
9134 /* Flush PCI posted writes. The normal MMIO registers
9135 * are inaccessible at this time so this is the only
9136 * way to make this reliably (actually, this is no longer
9137 * the case, see above). I tried to use indirect
9138 * register read/write but this upset some 5701 variants.
9139 */
9140 pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
9141
9142 udelay(120);
9143
0f49bfbd 9144 if (tg3_flag(tp, PCI_EXPRESS) && pci_is_pcie(tp->pdev)) {
e7126997
MC		 9145 u16 val16;
9146
4153577a 9147 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5750_A0) {
86449944 9148 int j;
1da177e4
LT		 9149 u32 cfg_val;
9150
9151 /* Wait for link training to complete. */
86449944 9152 for (j = 0; j < 5000; j++)
1da177e4
LT		 9153 udelay(100);
9154
9155 pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
9156 pci_write_config_dword(tp->pdev, 0xc4,
9157 cfg_val | (1 << 15));
9158 }
5e7dfd0f 9159
e7126997 9160 /* Clear the "no snoop" and "relaxed ordering" bits. */
0f49bfbd 9161 val16 = PCI_EXP_DEVCTL_RELAX_EN | PCI_EXP_DEVCTL_NOSNOOP_EN;
e7126997
MC		 9162 /*
9163 * Older PCIe devices only support the 128 byte
9164 * MPS setting. Enforce the restriction.
5e7dfd0f 9165 */
63c3a66f 9166 if (!tg3_flag(tp, CPMU_PRESENT))
0f49bfbd
JL		 9167 val16 |= PCI_EXP_DEVCTL_PAYLOAD;
9168 pcie_capability_clear_word(tp->pdev, PCI_EXP_DEVCTL, val16);
5e7dfd0f 9169
5e7dfd0f 9170 /* Clear error status */
0f49bfbd 9171 pcie_capability_write_word(tp->pdev, PCI_EXP_DEVSTA,
5e7dfd0f
MC		 9172 PCI_EXP_DEVSTA_CED |
9173 PCI_EXP_DEVSTA_NFED |
9174 PCI_EXP_DEVSTA_FED |
9175 PCI_EXP_DEVSTA_URD);
1da177e4
LT		 9176 }
9177
ee6a99b5 9178 tg3_restore_pci_state(tp);
1da177e4 9179
63c3a66f
JP		 9180 tg3_flag_clear(tp, CHIP_RESETTING);
9181 tg3_flag_clear(tp, ERROR_PROCESSED);
d18edcb2 9182
ee6a99b5 9183 val = 0;
63c3a66f 9184 if (tg3_flag(tp, 5780_CLASS))
4cf78e4f 9185 val = tr32(MEMARB_MODE);
ee6a99b5 9186 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
1da177e4 9187
4153577a 9188 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5750_A3) {
1da177e4
LT		 9189 tg3_stop_fw(tp);
9190 tw32(0x5000, 0x400);
9191 }
9192
7e6c63f0
HM		 9193 if (tg3_flag(tp, IS_SSB_CORE)) {
9194 /*
9195 * BCM4785: In order to avoid repercussions from using
9196 * potentially defective internal ROM, stop the Rx RISC CPU,
9197 * which is not required.
9198 */
9199 tg3_stop_fw(tp);
9200 tg3_halt_cpu(tp, RX_CPU_BASE);
9201 }
9202
fb03a43f
NS		 9203 err = tg3_poll_fw(tp);
9204 if (err)
9205 return err;
9206
1da177e4
LT		 9207 tw32(GRC_MODE, tp->grc_mode);
9208
4153577a 9209 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5705_A0) {
ab0049b4 9210 val = tr32(0xc4);
1da177e4
LT		 9211
9212 tw32(0xc4, val | (1 << 15));
9213 }
9214
9215 if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
4153577a 9216 tg3_asic_rev(tp) == ASIC_REV_5705) {
1da177e4 9217 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
4153577a 9218 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5705_A0)
1da177e4
LT		 9219 tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
9220 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
9221 }
9222
f07e9af3 9223 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
9e975cc2 9224 tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
d2394e6b 9225 val = tp->mac_mode;
f07e9af3 9226 } else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) {
9e975cc2 9227 tp->mac_mode = MAC_MODE_PORT_MODE_GMII;
d2394e6b 9228 val = tp->mac_mode;
1da177e4 9229 } else
d2394e6b
MC		 9230 val = 0;
9231
9232 tw32_f(MAC_MODE, val);
1da177e4
LT		 9233 udelay(40);
9234
77b483f1
MC		 9235 tg3_ape_unlock(tp, TG3_APE_LOCK_GRC);
9236
0a9140cf
MC		 9237 tg3_mdio_start(tp);
9238
63c3a66f 9239 if (tg3_flag(tp, PCI_EXPRESS) &&
4153577a
JP		 9240 tg3_chip_rev_id(tp) != CHIPREV_ID_5750_A0 &&
9241 tg3_asic_rev(tp) != ASIC_REV_5785 &&
63c3a66f 9242 !tg3_flag(tp, 57765_PLUS)) {
ab0049b4 9243 val = tr32(0x7c00);
1da177e4
LT		 9244
9245 tw32(0x7c00, val | (1 << 25));
9246 }
9247
f82995b6 9248 tg3_restore_clk(tp);
d78b59f5 9249
1da177e4 9250 /* Reprobe ASF enable state. */
63c3a66f 9251 tg3_flag_clear(tp, ENABLE_ASF);
942d1af0
NS		 9252 tp->phy_flags &= ~(TG3_PHYFLG_1G_ON_VAUX_OK |
9253 TG3_PHYFLG_KEEP_LINK_ON_PWRDN);
9254
63c3a66f 9255 tg3_flag_clear(tp, ASF_NEW_HANDSHAKE);
1da177e4
LT		 9256 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
9257 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
9258 u32 nic_cfg;
9259
9260 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
9261 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
63c3a66f 9262 tg3_flag_set(tp, ENABLE_ASF);
4ba526ce 9263 tp->last_event_jiffies = jiffies;
63c3a66f
JP		 9264 if (tg3_flag(tp, 5750_PLUS))
9265 tg3_flag_set(tp, ASF_NEW_HANDSHAKE);
942d1af0
NS		 9266
9267 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &nic_cfg);
9268 if (nic_cfg & NIC_SRAM_1G_ON_VAUX_OK)
9269 tp->phy_flags |= TG3_PHYFLG_1G_ON_VAUX_OK;
9270 if (nic_cfg & NIC_SRAM_LNK_FLAP_AVOID)
9271 tp->phy_flags |= TG3_PHYFLG_KEEP_LINK_ON_PWRDN;
1da177e4
LT		 9272 }
9273 }
9274
9275 return 0;
9276}
9277
65ec698d
MC		 9278static void tg3_get_nstats(struct tg3 *, struct rtnl_link_stats64 *);
9279static void tg3_get_estats(struct tg3 *, struct tg3_ethtool_stats *);
e565eec3 9280static void __tg3_set_rx_mode(struct net_device *);
92feeabf 9281
1da177e4 9282/* tp->lock is held. */
953c96e0 9283static int tg3_halt(struct tg3 *tp, int kind, bool silent)
1da177e4
LT		 9284{
9285 int err;
9286
9287 tg3_stop_fw(tp);
9288
944d980e 9289 tg3_write_sig_pre_reset(tp, kind);
1da177e4 9290
b3b7d6be 9291 tg3_abort_hw(tp, silent);
1da177e4
LT		 9292 err = tg3_chip_reset(tp);
9293
953c96e0 9294 __tg3_set_mac_addr(tp, false);
daba2a63 9295
944d980e
MC		 9296 tg3_write_sig_legacy(tp, kind);
9297 tg3_write_sig_post_reset(tp, kind);
1da177e4 9298
92feeabf
MC		 9299 if (tp->hw_stats) {
9300 /* Save the stats across chip resets... */
b4017c53 9301 tg3_get_nstats(tp, &tp->net_stats_prev);
92feeabf
MC		 9302 tg3_get_estats(tp, &tp->estats_prev);
9303
9304 /* And make sure the next sample is new data */
9305 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
9306 }
9307
4bc814ab 9308 return err;
1da177e4
LT		 9309}
9310
1da177e4
LT		 9311static int tg3_set_mac_addr(struct net_device *dev, void *p)
9312{
9313 struct tg3 *tp = netdev_priv(dev);
9314 struct sockaddr *addr = p;
953c96e0
JP		 9315 int err = 0;
9316 bool skip_mac_1 = false;
1da177e4 9317
f9804ddb 9318 if (!is_valid_ether_addr(addr->sa_data))
504f9b5a 9319 return -EADDRNOTAVAIL;
f9804ddb 9320
1da177e4
LT		 9321 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
9322
e75f7c90
MC		 9323 if (!netif_running(dev))
9324 return 0;
9325
63c3a66f 9326 if (tg3_flag(tp, ENABLE_ASF)) {
986e0aeb 9327 u32 addr0_high, addr0_low, addr1_high, addr1_low;
58712ef9 9328
986e0aeb
MC		 9329 addr0_high = tr32(MAC_ADDR_0_HIGH);
9330 addr0_low = tr32(MAC_ADDR_0_LOW);
9331 addr1_high = tr32(MAC_ADDR_1_HIGH);
9332 addr1_low = tr32(MAC_ADDR_1_LOW);
9333
9334 /* Skip MAC addr 1 if ASF is using it. */
9335 if ((addr0_high != addr1_high || addr0_low != addr1_low) &&
9336 !(addr1_high == 0 && addr1_low == 0))
953c96e0 9337 skip_mac_1 = true;
58712ef9 9338 }
986e0aeb
MC		 9339 spin_lock_bh(&tp->lock);
9340 __tg3_set_mac_addr(tp, skip_mac_1);
e565eec3 9341 __tg3_set_rx_mode(dev);
986e0aeb 9342 spin_unlock_bh(&tp->lock);
1da177e4 9343
b9ec6c1b 9344 return err;
1da177e4
LT		 9345}
9346
9347/* tp->lock is held. */
9348static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
9349 dma_addr_t mapping, u32 maxlen_flags,
9350 u32 nic_addr)
9351{
9352 tg3_write_mem(tp,
9353 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
9354 ((u64) mapping >> 32));
9355 tg3_write_mem(tp,
9356 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
9357 ((u64) mapping & 0xffffffff));
9358 tg3_write_mem(tp,
9359 (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
9360 maxlen_flags);
9361
63c3a66f 9362 if (!tg3_flag(tp, 5705_PLUS))
1da177e4
LT		 9363 tg3_write_mem(tp,
9364 (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
9365 nic_addr);
9366}
9367
a489b6d9
MC		 9368
9369static void tg3_coal_tx_init(struct tg3 *tp, struct ethtool_coalesce *ec)
15f9850d 9370{
a489b6d9 9371 int i = 0;
b6080e12 9372
63c3a66f 9373 if (!tg3_flag(tp, ENABLE_TSS)) {
b6080e12
MC		 9374 tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
9375 tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
9376 tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
b6080e12
MC		 9377 } else {
9378 tw32(HOSTCC_TXCOL_TICKS, 0);
9379 tw32(HOSTCC_TXMAX_FRAMES, 0);
9380 tw32(HOSTCC_TXCOAL_MAXF_INT, 0);
a489b6d9
MC		 9381
9382 for (; i < tp->txq_cnt; i++) {
9383 u32 reg;
9384
9385 reg = HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18;
9386 tw32(reg, ec->tx_coalesce_usecs);
9387 reg = HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18;
9388 tw32(reg, ec->tx_max_coalesced_frames);
9389 reg = HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18;
9390 tw32(reg, ec->tx_max_coalesced_frames_irq);
9391 }
19cfaecc 9392 }
b6080e12 9393
a489b6d9
MC		 9394 for (; i < tp->irq_max - 1; i++) {
9395 tw32(HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18, 0);
9396 tw32(HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18, 0);
9397 tw32(HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
9398 }
9399}
9400
9401static void tg3_coal_rx_init(struct tg3 *tp, struct ethtool_coalesce *ec)
9402{
9403 int i = 0;
9404 u32 limit = tp->rxq_cnt;
9405
63c3a66f 9406 if (!tg3_flag(tp, ENABLE_RSS)) {
19cfaecc
MC		 9407 tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
9408 tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
9409 tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
a489b6d9 9410 limit--;
19cfaecc 9411 } else {
b6080e12
MC		 9412 tw32(HOSTCC_RXCOL_TICKS, 0);
9413 tw32(HOSTCC_RXMAX_FRAMES, 0);
9414 tw32(HOSTCC_RXCOAL_MAXF_INT, 0);
15f9850d 9415 }
b6080e12 9416
a489b6d9 9417 for (; i < limit; i++) {
b6080e12
MC		 9418 u32 reg;
9419
9420 reg = HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18;
9421 tw32(reg, ec->rx_coalesce_usecs);
b6080e12
MC		 9422 reg = HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18;
9423 tw32(reg, ec->rx_max_coalesced_frames);
b6080e12
MC		 9424 reg = HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18;
9425 tw32(reg, ec->rx_max_coalesced_frames_irq);
b6080e12
MC		 9426 }
9427
9428 for (; i < tp->irq_max - 1; i++) {
9429 tw32(HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18, 0);
b6080e12 9430 tw32(HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18, 0);
b6080e12 9431 tw32(HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
a489b6d9
MC		 9432 }
9433}
19cfaecc 9434
a489b6d9
MC		 9435static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
9436{
9437 tg3_coal_tx_init(tp, ec);
9438 tg3_coal_rx_init(tp, ec);
9439
9440 if (!tg3_flag(tp, 5705_PLUS)) {
9441 u32 val = ec->stats_block_coalesce_usecs;
9442
9443 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
9444 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
9445
f4a46d1f 9446 if (!tp->link_up)
a489b6d9
MC		 9447 val = 0;
9448
9449 tw32(HOSTCC_STAT_COAL_TICKS, val);
b6080e12 9450 }
15f9850d 9451}
1da177e4 9452
328947ff
NS		 9453/* tp->lock is held. */
9454static void tg3_tx_rcbs_disable(struct tg3 *tp)
9455{
9456 u32 txrcb, limit;
9457
9458 /* Disable all transmit rings but the first. */
9459 if (!tg3_flag(tp, 5705_PLUS))
9460 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 16;
9461 else if (tg3_flag(tp, 5717_PLUS))
9462 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 4;
9463 else if (tg3_flag(tp, 57765_CLASS) ||
9464 tg3_asic_rev(tp) == ASIC_REV_5762)
9465 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 2;
9466 else
9467 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
9468
9469 for (txrcb = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
9470 txrcb < limit; txrcb += TG3_BDINFO_SIZE)
9471 tg3_write_mem(tp, txrcb + TG3_BDINFO_MAXLEN_FLAGS,
9472 BDINFO_FLAGS_DISABLED);
9473}
9474
32ba19ef
NS		 9475/* tp->lock is held. */
9476static void tg3_tx_rcbs_init(struct tg3 *tp)
9477{
9478 int i = 0;
9479 u32 txrcb = NIC_SRAM_SEND_RCB;
9480
9481 if (tg3_flag(tp, ENABLE_TSS))
9482 i++;
9483
9484 for (; i < tp->irq_max; i++, txrcb += TG3_BDINFO_SIZE) {
9485 struct tg3_napi *tnapi = &tp->napi[i];
9486
9487 if (!tnapi->tx_ring)
9488 continue;
9489
9490 tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
9491 (TG3_TX_RING_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT),
9492 NIC_SRAM_TX_BUFFER_DESC);
9493 }
9494}
9495
328947ff
NS		 9496/* tp->lock is held. */
9497static void tg3_rx_ret_rcbs_disable(struct tg3 *tp)
9498{
9499 u32 rxrcb, limit;
9500
9501 /* Disable all receive return rings but the first. */
9502 if (tg3_flag(tp, 5717_PLUS))
9503 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 17;
9504 else if (!tg3_flag(tp, 5705_PLUS))
9505 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 16;
9506 else if (tg3_asic_rev(tp) == ASIC_REV_5755 ||
9507 tg3_asic_rev(tp) == ASIC_REV_5762 ||
9508 tg3_flag(tp, 57765_CLASS))
9509 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 4;
9510 else
9511 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
9512
9513 for (rxrcb = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
9514 rxrcb < limit; rxrcb += TG3_BDINFO_SIZE)
9515 tg3_write_mem(tp, rxrcb + TG3_BDINFO_MAXLEN_FLAGS,
9516 BDINFO_FLAGS_DISABLED);
9517}
9518
32ba19ef
NS		 9519/* tp->lock is held. */
9520static void tg3_rx_ret_rcbs_init(struct tg3 *tp)
9521{
9522 int i = 0;
9523 u32 rxrcb = NIC_SRAM_RCV_RET_RCB;
9524
9525 if (tg3_flag(tp, ENABLE_RSS))
9526 i++;
9527
9528 for (; i < tp->irq_max; i++, rxrcb += TG3_BDINFO_SIZE) {
9529 struct tg3_napi *tnapi = &tp->napi[i];
9530
9531 if (!tnapi->rx_rcb)
9532 continue;
9533
9534 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
9535 (tp->rx_ret_ring_mask + 1) <<
9536 BDINFO_FLAGS_MAXLEN_SHIFT, 0);
9537 }
9538}
9539
2d31ecaf
MC		 9540/* tp->lock is held. */
9541static void tg3_rings_reset(struct tg3 *tp)
9542{
9543 int i;
328947ff 9544 u32 stblk;
2d31ecaf
MC		 9545 struct tg3_napi *tnapi = &tp->napi[0];
9546
328947ff 9547 tg3_tx_rcbs_disable(tp);
2d31ecaf 9548
328947ff 9549 tg3_rx_ret_rcbs_disable(tp);
2d31ecaf
MC		 9550
9551 /* Disable interrupts */
9552 tw32_mailbox_f(tp->napi[0].int_mbox, 1);
0e6cf6a9
MC		 9553 tp->napi[0].chk_msi_cnt = 0;
9554 tp->napi[0].last_rx_cons = 0;
9555 tp->napi[0].last_tx_cons = 0;
2d31ecaf
MC		 9556
9557 /* Zero mailbox registers. */
63c3a66f 9558 if (tg3_flag(tp, SUPPORT_MSIX)) {
6fd45cb8 9559 for (i = 1; i < tp->irq_max; i++) {
f77a6a8e
MC		 9560 tp->napi[i].tx_prod = 0;
9561 tp->napi[i].tx_cons = 0;
63c3a66f 9562 if (tg3_flag(tp, ENABLE_TSS))
c2353a32 9563 tw32_mailbox(tp->napi[i].prodmbox, 0);
f77a6a8e
MC		 9564 tw32_rx_mbox(tp->napi[i].consmbox, 0);
9565 tw32_mailbox_f(tp->napi[i].int_mbox, 1);
7f230735 9566 tp->napi[i].chk_msi_cnt = 0;
0e6cf6a9
MC		 9567 tp->napi[i].last_rx_cons = 0;
9568 tp->napi[i].last_tx_cons = 0;
f77a6a8e 9569 }
63c3a66f 9570 if (!tg3_flag(tp, ENABLE_TSS))
c2353a32 9571 tw32_mailbox(tp->napi[0].prodmbox, 0);
f77a6a8e
MC		 9572 } else {
9573 tp->napi[0].tx_prod = 0;
9574 tp->napi[0].tx_cons = 0;
9575 tw32_mailbox(tp->napi[0].prodmbox, 0);
9576 tw32_rx_mbox(tp->napi[0].consmbox, 0);
9577 }
2d31ecaf
MC		 9578
9579 /* Make sure the NIC-based send BD rings are disabled. */
63c3a66f 9580 if (!tg3_flag(tp, 5705_PLUS)) {
2d31ecaf
MC		 9581 u32 mbox = MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW;
9582 for (i = 0; i < 16; i++)
9583 tw32_tx_mbox(mbox + i * 8, 0);
9584 }
9585
2d31ecaf
MC		 9586 /* Clear status block in ram. */
9587 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
9588
9589 /* Set status block DMA address */
9590 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
9591 ((u64) tnapi->status_mapping >> 32));
9592 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
9593 ((u64) tnapi->status_mapping & 0xffffffff));
9594
f77a6a8e 9595 stblk = HOSTCC_STATBLCK_RING1;
2d31ecaf 9596
f77a6a8e
MC		 9597 for (i = 1, tnapi++; i < tp->irq_cnt; i++, tnapi++) {
9598 u64 mapping = (u64)tnapi->status_mapping;
9599 tw32(stblk + TG3_64BIT_REG_HIGH, mapping >> 32);
9600 tw32(stblk + TG3_64BIT_REG_LOW, mapping & 0xffffffff);
32ba19ef 9601 stblk += 8;
f77a6a8e
MC		 9602
9603 /* Clear status block in ram. */
9604 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
f77a6a8e 9605 }
32ba19ef
NS		 9606
9607 tg3_tx_rcbs_init(tp);
9608 tg3_rx_ret_rcbs_init(tp);
2d31ecaf
MC		 9609}
9610
eb07a940
MC		 9611static void tg3_setup_rxbd_thresholds(struct tg3 *tp)
9612{
9613 u32 val, bdcache_maxcnt, host_rep_thresh, nic_rep_thresh;
9614
63c3a66f
JP		 9615 if (!tg3_flag(tp, 5750_PLUS) ||
9616 tg3_flag(tp, 5780_CLASS) ||
4153577a
JP		 9617 tg3_asic_rev(tp) == ASIC_REV_5750 ||
9618 tg3_asic_rev(tp) == ASIC_REV_5752 ||
513aa6ea 9619 tg3_flag(tp, 57765_PLUS))
eb07a940 9620 bdcache_maxcnt = TG3_SRAM_RX_STD_BDCACHE_SIZE_5700;
4153577a
JP		 9621 else if (tg3_asic_rev(tp) == ASIC_REV_5755 ||
9622 tg3_asic_rev(tp) == ASIC_REV_5787)
eb07a940
MC		 9623 bdcache_maxcnt = TG3_SRAM_RX_STD_BDCACHE_SIZE_5755;
9624 else
9625 bdcache_maxcnt = TG3_SRAM_RX_STD_BDCACHE_SIZE_5906;
9626
9627 nic_rep_thresh = min(bdcache_maxcnt / 2, tp->rx_std_max_post);
9628 host_rep_thresh = max_t(u32, tp->rx_pending / 8, 1);
9629
9630 val = min(nic_rep_thresh, host_rep_thresh);
9631 tw32(RCVBDI_STD_THRESH, val);
9632
63c3a66f 9633 if (tg3_flag(tp, 57765_PLUS))
eb07a940
MC		 9634 tw32(STD_REPLENISH_LWM, bdcache_maxcnt);
9635
63c3a66f 9636 if (!tg3_flag(tp, JUMBO_CAPABLE) || tg3_flag(tp, 5780_CLASS))
eb07a940
MC		 9637 return;
9638
513aa6ea 9639 bdcache_maxcnt = TG3_SRAM_RX_JMB_BDCACHE_SIZE_5700;
eb07a940
MC		 9640
9641 host_rep_thresh = max_t(u32, tp->rx_jumbo_pending / 8, 1);
9642
9643 val = min(bdcache_maxcnt / 2, host_rep_thresh);
9644 tw32(RCVBDI_JUMBO_THRESH, val);
9645
63c3a66f 9646 if (tg3_flag(tp, 57765_PLUS))
eb07a940
MC		 9647 tw32(JMB_REPLENISH_LWM, bdcache_maxcnt);
9648}
9649
ccd5ba9d
MC		 9650static inline u32 calc_crc(unsigned char *buf, int len)
9651{
9652 u32 reg;
9653 u32 tmp;
9654 int j, k;
9655
9656 reg = 0xffffffff;
9657
9658 for (j = 0; j < len; j++) {
9659 reg ^= buf[j];
9660
9661 for (k = 0; k < 8; k++) {
9662 tmp = reg & 0x01;
9663
9664 reg >>= 1;
9665
9666 if (tmp)
9667 reg ^= 0xedb88320;
9668 }
9669 }
9670
9671 return ~reg;
9672}
9673
9674static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
9675{
9676 /* accept or reject all multicast frames */
9677 tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
9678 tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
9679 tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
9680 tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
9681}
9682
9683static void __tg3_set_rx_mode(struct net_device *dev)
9684{
9685 struct tg3 *tp = netdev_priv(dev);
9686 u32 rx_mode;
9687
9688 rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
9689 RX_MODE_KEEP_VLAN_TAG);
9690
9691#if !defined(CONFIG_VLAN_8021Q) && !defined(CONFIG_VLAN_8021Q_MODULE)
9692 /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
9693 * flag clear.
9694 */
9695 if (!tg3_flag(tp, ENABLE_ASF))
9696 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
9697#endif
9698
9699 if (dev->flags & IFF_PROMISC) {
9700 /* Promiscuous mode. */
9701 rx_mode |= RX_MODE_PROMISC;
9702 } else if (dev->flags & IFF_ALLMULTI) {
9703 /* Accept all multicast. */
9704 tg3_set_multi(tp, 1);
9705 } else if (netdev_mc_empty(dev)) {
9706 /* Reject all multicast. */
9707 tg3_set_multi(tp, 0);
9708 } else {
9709 /* Accept one or more multicast(s). */
9710 struct netdev_hw_addr *ha;
9711 u32 mc_filter[4] = { 0, };
9712 u32 regidx;
9713 u32 bit;
9714 u32 crc;
9715
9716 netdev_for_each_mc_addr(ha, dev) {
9717 crc = calc_crc(ha->addr, ETH_ALEN);
9718 bit = ~crc & 0x7f;
9719 regidx = (bit & 0x60) >> 5;
9720 bit &= 0x1f;
9721 mc_filter[regidx] |= (1 << bit);
9722 }
9723
9724 tw32(MAC_HASH_REG_0, mc_filter[0]);
9725 tw32(MAC_HASH_REG_1, mc_filter[1]);
9726 tw32(MAC_HASH_REG_2, mc_filter[2]);
9727 tw32(MAC_HASH_REG_3, mc_filter[3]);
9728 }
9729
e565eec3
MC		 9730 if (netdev_uc_count(dev) > TG3_MAX_UCAST_ADDR(tp)) {
9731 rx_mode |= RX_MODE_PROMISC;
9732 } else if (!(dev->flags & IFF_PROMISC)) {
9733 /* Add all entries into to the mac addr filter list */
9734 int i = 0;
9735 struct netdev_hw_addr *ha;
9736
9737 netdev_for_each_uc_addr(ha, dev) {
9738 __tg3_set_one_mac_addr(tp, ha->addr,
9739 i + TG3_UCAST_ADDR_IDX(tp));
9740 i++;
9741 }
9742 }
9743
ccd5ba9d
MC		 9744 if (rx_mode != tp->rx_mode) {
9745 tp->rx_mode = rx_mode;
9746 tw32_f(MAC_RX_MODE, rx_mode);
9747 udelay(10);
9748 }
9749}
9750
9102426a 9751static void tg3_rss_init_dflt_indir_tbl(struct tg3 *tp, u32 qcnt)
90415477
MC		 9752{
9753 int i;
9754
9755 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++)
9102426a 9756 tp->rss_ind_tbl[i] = ethtool_rxfh_indir_default(i, qcnt);
90415477
MC		 9757}
9758
9759static void tg3_rss_check_indir_tbl(struct tg3 *tp)
bcebcc46
MC		 9760{
9761 int i;
9762
9763 if (!tg3_flag(tp, SUPPORT_MSIX))
9764 return;
9765
0b3ba055 9766 if (tp->rxq_cnt == 1) {
bcebcc46 9767 memset(&tp->rss_ind_tbl[0], 0, sizeof(tp->rss_ind_tbl));
90415477
MC		 9768 return;
9769 }
9770
9771 /* Validate table against current IRQ count */
9772 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++) {
0b3ba055 9773 if (tp->rss_ind_tbl[i] >= tp->rxq_cnt)
90415477
MC		 9774 break;
9775 }
9776
9777 if (i != TG3_RSS_INDIR_TBL_SIZE)
9102426a 9778 tg3_rss_init_dflt_indir_tbl(tp, tp->rxq_cnt);
bcebcc46
MC		 9779}
9780
90415477 9781static void tg3_rss_write_indir_tbl(struct tg3 *tp)
bcebcc46
MC		 9782{
9783 int i = 0;
9784 u32 reg = MAC_RSS_INDIR_TBL_0;
9785
9786 while (i < TG3_RSS_INDIR_TBL_SIZE) {
9787 u32 val = tp->rss_ind_tbl[i];
9788 i++;
9789 for (; i % 8; i++) {
9790 val <<= 4;
9791 val |= tp->rss_ind_tbl[i];
9792 }
9793 tw32(reg, val);
9794 reg += 4;
9795 }
9796}
9797
9bc297ea
NS		 9798static inline u32 tg3_lso_rd_dma_workaround_bit(struct tg3 *tp)
9799{
9800 if (tg3_asic_rev(tp) == ASIC_REV_5719)
9801 return TG3_LSO_RD_DMA_TX_LENGTH_WA_5719;
9802 else
9803 return TG3_LSO_RD_DMA_TX_LENGTH_WA_5720;
9804}
9805
1da177e4 9806/* tp->lock is held. */
953c96e0 9807static int tg3_reset_hw(struct tg3 *tp, bool reset_phy)
1da177e4
LT		 9808{
9809 u32 val, rdmac_mode;
9810 int i, err, limit;
8fea32b9 9811 struct tg3_rx_prodring_set *tpr = &tp->napi[0].prodring;
1da177e4
LT		 9812
9813 tg3_disable_ints(tp);
9814
9815 tg3_stop_fw(tp);
9816
9817 tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
9818
63c3a66f 9819 if (tg3_flag(tp, INIT_COMPLETE))
e6de8ad1 9820 tg3_abort_hw(tp, 1);
1da177e4 9821
fdad8de4
NS		 9822 if ((tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN) &&
9823 !(tp->phy_flags & TG3_PHYFLG_USER_CONFIGURED)) {
9824 tg3_phy_pull_config(tp);
400dfbaa 9825 tg3_eee_pull_config(tp, NULL);
fdad8de4
NS		 9826 tp->phy_flags |= TG3_PHYFLG_USER_CONFIGURED;
9827 }
9828
400dfbaa
NS		 9829 /* Enable MAC control of LPI */
9830 if (tp->phy_flags & TG3_PHYFLG_EEE_CAP)
9831 tg3_setup_eee(tp);
9832
603f1173 9833 if (reset_phy)
d4d2c558
MC		 9834 tg3_phy_reset(tp);
9835
1da177e4
LT		 9836 err = tg3_chip_reset(tp);
9837 if (err)
9838 return err;
9839
9840 tg3_write_sig_legacy(tp, RESET_KIND_INIT);
9841
4153577a 9842 if (tg3_chip_rev(tp) == CHIPREV_5784_AX) {
d30cdd28
MC		 9843 val = tr32(TG3_CPMU_CTRL);
9844 val &= ~(CPMU_CTRL_LINK_AWARE_MODE | CPMU_CTRL_LINK_IDLE_MODE);
9845 tw32(TG3_CPMU_CTRL, val);
9acb961e
MC		 9846
9847 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
9848 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
9849 val |= CPMU_LSPD_10MB_MACCLK_6_25;
9850 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
9851
9852 val = tr32(TG3_CPMU_LNK_AWARE_PWRMD);
9853 val &= ~CPMU_LNK_AWARE_MACCLK_MASK;
9854 val |= CPMU_LNK_AWARE_MACCLK_6_25;
9855 tw32(TG3_CPMU_LNK_AWARE_PWRMD, val);
9856
9857 val = tr32(TG3_CPMU_HST_ACC);
9858 val &= ~CPMU_HST_ACC_MACCLK_MASK;
9859 val |= CPMU_HST_ACC_MACCLK_6_25;
9860 tw32(TG3_CPMU_HST_ACC, val);
d30cdd28
MC		 9861 }
9862
4153577a 9863 if (tg3_asic_rev(tp) == ASIC_REV_57780) {
33466d93
MC		 9864 val = tr32(PCIE_PWR_MGMT_THRESH) & ~PCIE_PWR_MGMT_L1_THRESH_MSK;
9865 val |= PCIE_PWR_MGMT_EXT_ASPM_TMR_EN |
9866 PCIE_PWR_MGMT_L1_THRESH_4MS;
9867 tw32(PCIE_PWR_MGMT_THRESH, val);
521e6b90
MC		 9868
9869 val = tr32(TG3_PCIE_EIDLE_DELAY) & ~TG3_PCIE_EIDLE_DELAY_MASK;
9870 tw32(TG3_PCIE_EIDLE_DELAY, val | TG3_PCIE_EIDLE_DELAY_13_CLKS);
9871
9872 tw32(TG3_CORR_ERR_STAT, TG3_CORR_ERR_STAT_CLEAR);
33466d93 9873
f40386c8
MC		 9874 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
9875 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
255ca311
MC		 9876 }
9877
63c3a66f 9878 if (tg3_flag(tp, L1PLLPD_EN)) {
614b0590
MC		 9879 u32 grc_mode = tr32(GRC_MODE);
9880
9881 /* Access the lower 1K of PL PCIE block registers. */
9882 val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
9883 tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL);
9884
9885 val = tr32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1);
9886 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1,
9887 val | TG3_PCIE_PL_LO_PHYCTL1_L1PLLPD_EN);
9888
9889 tw32(GRC_MODE, grc_mode);
9890 }
9891
55086ad9 9892 if (tg3_flag(tp, 57765_CLASS)) {
4153577a 9893 if (tg3_chip_rev_id(tp) == CHIPREV_ID_57765_A0) {
5093eedc 9894 u32 grc_mode = tr32(GRC_MODE);
cea46462 9895
5093eedc
MC		 9896 /* Access the lower 1K of PL PCIE block registers. */
9897 val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
9898 tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL);
cea46462 9899
5093eedc
MC		 9900 val = tr32(TG3_PCIE_TLDLPL_PORT +
9901 TG3_PCIE_PL_LO_PHYCTL5);
9902 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL5,
9903 val | TG3_PCIE_PL_LO_PHYCTL5_DIS_L2CLKREQ);
cea46462 9904
5093eedc
MC		 9905 tw32(GRC_MODE, grc_mode);
9906 }
a977dbe8 9907
4153577a 9908 if (tg3_chip_rev(tp) != CHIPREV_57765_AX) {
d3f677af
MC		 9909 u32 grc_mode;
9910
9911 /* Fix transmit hangs */
9912 val = tr32(TG3_CPMU_PADRNG_CTL);
9913 val |= TG3_CPMU_PADRNG_CTL_RDIV2;
9914 tw32(TG3_CPMU_PADRNG_CTL, val);
9915
9916 grc_mode = tr32(GRC_MODE);
1ff30a59
MC		 9917
9918 /* Access the lower 1K of DL PCIE block registers. */
9919 val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
9920 tw32(GRC_MODE, val | GRC_MODE_PCIE_DL_SEL);
9921
9922 val = tr32(TG3_PCIE_TLDLPL_PORT +
9923 TG3_PCIE_DL_LO_FTSMAX);
9924 val &= ~TG3_PCIE_DL_LO_FTSMAX_MSK;
9925 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_DL_LO_FTSMAX,
9926 val | TG3_PCIE_DL_LO_FTSMAX_VAL);
9927
9928 tw32(GRC_MODE, grc_mode);
9929 }
9930
a977dbe8
MC		 9931 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
9932 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
9933 val |= CPMU_LSPD_10MB_MACCLK_6_25;
9934 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
cea46462
MC		 9935 }
9936
1da177e4
LT		 9937 /* This works around an issue with Athlon chipsets on
9938 * B3 tigon3 silicon. This bit has no effect on any
9939 * other revision. But do not set this on PCI Express
795d01c5 9940 * chips and don't even touch the clocks if the CPMU is present.
1da177e4 9941 */
63c3a66f
JP		 9942 if (!tg3_flag(tp, CPMU_PRESENT)) {
9943 if (!tg3_flag(tp, PCI_EXPRESS))
795d01c5
MC		 9944 tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
9945 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
9946 }
1da177e4 9947
4153577a 9948 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5704_A0 &&
63c3a66f 9949 tg3_flag(tp, PCIX_MODE)) {
1da177e4
LT		 9950 val = tr32(TG3PCI_PCISTATE);
9951 val |= PCISTATE_RETRY_SAME_DMA;
9952 tw32(TG3PCI_PCISTATE, val);
9953 }
9954
63c3a66f 9955 if (tg3_flag(tp, ENABLE_APE)) {
0d3031d9
MC		 9956 /* Allow reads and writes to the
9957 * APE register and memory space.
9958 */
9959 val = tr32(TG3PCI_PCISTATE);
9960 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
f92d9dc1
MC		 9961 PCISTATE_ALLOW_APE_SHMEM_WR |
9962 PCISTATE_ALLOW_APE_PSPACE_WR;
0d3031d9
MC		 9963 tw32(TG3PCI_PCISTATE, val);
9964 }
9965
4153577a 9966 if (tg3_chip_rev(tp) == CHIPREV_5704_BX) {
1da177e4
LT		 9967 /* Enable some hw fixes. */
9968 val = tr32(TG3PCI_MSI_DATA);
9969 val |= (1 << 26) | (1 << 28) | (1 << 29);
9970 tw32(TG3PCI_MSI_DATA, val);
9971 }
9972
9973 /* Descriptor ring init may make accesses to the
9974 * NIC SRAM area to setup the TX descriptors, so we
9975 * can only do this after the hardware has been
9976 * successfully reset.
9977 */
32d8c572
MC		 9978 err = tg3_init_rings(tp);
9979 if (err)
9980 return err;
1da177e4 9981
63c3a66f 9982 if (tg3_flag(tp, 57765_PLUS)) {
cbf9ca6c
MC		 9983 val = tr32(TG3PCI_DMA_RW_CTRL) &
9984 ~DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
4153577a 9985 if (tg3_chip_rev_id(tp) == CHIPREV_ID_57765_A0)
1a319025 9986 val &= ~DMA_RWCTRL_CRDRDR_RDMA_MRRS_MSK;
55086ad9 9987 if (!tg3_flag(tp, 57765_CLASS) &&
4153577a
JP		 9988 tg3_asic_rev(tp) != ASIC_REV_5717 &&
9989 tg3_asic_rev(tp) != ASIC_REV_5762)
0aebff48 9990 val |= DMA_RWCTRL_TAGGED_STAT_WA;
cbf9ca6c 9991 tw32(TG3PCI_DMA_RW_CTRL, val | tp->dma_rwctrl);
4153577a
JP		 9992 } else if (tg3_asic_rev(tp) != ASIC_REV_5784 &&
9993 tg3_asic_rev(tp) != ASIC_REV_5761) {
d30cdd28
MC		 9994 /* This value is determined during the probe time DMA
9995 * engine test, tg3_test_dma.
9996 */
9997 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
9998 }
1da177e4
LT		 9999
10000 tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
10001 GRC_MODE_4X_NIC_SEND_RINGS |
10002 GRC_MODE_NO_TX_PHDR_CSUM |
10003 GRC_MODE_NO_RX_PHDR_CSUM);
10004 tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
d2d746f8
MC		 10005
10006 /* Pseudo-header checksum is done by hardware logic and not
10007 * the offload processers, so make the chip do the pseudo-
10008 * header checksums on receive. For transmit it is more
10009 * convenient to do the pseudo-header checksum in software
10010 * as Linux does that on transmit for us in all cases.
10011 */
10012 tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
1da177e4 10013
fb4ce8ad
MC		 10014 val = GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP;
10015 if (tp->rxptpctl)
10016 tw32(TG3_RX_PTP_CTL,
10017 tp->rxptpctl | TG3_RX_PTP_CTL_HWTS_INTERLOCK);
10018
10019 if (tg3_flag(tp, PTP_CAPABLE))
10020 val |= GRC_MODE_TIME_SYNC_ENABLE;
10021
10022 tw32(GRC_MODE, tp->grc_mode | val);
1da177e4
LT		 10023
10024 /* Setup the timer prescalar register. Clock is always 66Mhz. */
10025 val = tr32(GRC_MISC_CFG);
10026 val &= ~0xff;
10027 val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
10028 tw32(GRC_MISC_CFG, val);
10029
10030 /* Initialize MBUF/DESC pool. */
63c3a66f 10031 if (tg3_flag(tp, 5750_PLUS)) {
1da177e4 10032 /* Do nothing. */
4153577a 10033 } else if (tg3_asic_rev(tp) != ASIC_REV_5705) {
1da177e4 10034 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
4153577a 10035 if (tg3_asic_rev(tp) == ASIC_REV_5704)
1da177e4
LT		 10036 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
10037 else
10038 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
10039 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
10040 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
63c3a66f 10041 } else if (tg3_flag(tp, TSO_CAPABLE)) {
1da177e4
LT		 10042 int fw_len;
10043
077f849d 10044 fw_len = tp->fw_len;
1da177e4
LT		 10045 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
10046 tw32(BUFMGR_MB_POOL_ADDR,
10047 NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
10048 tw32(BUFMGR_MB_POOL_SIZE,
10049 NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
10050 }
1da177e4 10051
0f893dc6 10052 if (tp->dev->mtu <= ETH_DATA_LEN) {
1da177e4
LT		 10053 tw32(BUFMGR_MB_RDMA_LOW_WATER,
10054 tp->bufmgr_config.mbuf_read_dma_low_water);
10055 tw32(BUFMGR_MB_MACRX_LOW_WATER,
10056 tp->bufmgr_config.mbuf_mac_rx_low_water);
10057 tw32(BUFMGR_MB_HIGH_WATER,
10058 tp->bufmgr_config.mbuf_high_water);
10059 } else {
10060 tw32(BUFMGR_MB_RDMA_LOW_WATER,
10061 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
10062 tw32(BUFMGR_MB_MACRX_LOW_WATER,
10063 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
10064 tw32(BUFMGR_MB_HIGH_WATER,
10065 tp->bufmgr_config.mbuf_high_water_jumbo);
10066 }
10067 tw32(BUFMGR_DMA_LOW_WATER,
10068 tp->bufmgr_config.dma_low_water);
10069 tw32(BUFMGR_DMA_HIGH_WATER,
10070 tp->bufmgr_config.dma_high_water);
10071
d309a46e 10072 val = BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE;
4153577a 10073 if (tg3_asic_rev(tp) == ASIC_REV_5719)
d309a46e 10074 val |= BUFMGR_MODE_NO_TX_UNDERRUN;
4153577a 10075 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
94962f7f 10076 tg3_asic_rev(tp) == ASIC_REV_5762 ||
4153577a
JP		 10077 tg3_chip_rev_id(tp) == CHIPREV_ID_5719_A0 ||
10078 tg3_chip_rev_id(tp) == CHIPREV_ID_5720_A0)
4d958473 10079 val |= BUFMGR_MODE_MBLOW_ATTN_ENAB;
d309a46e 10080 tw32(BUFMGR_MODE, val);
1da177e4
LT		 10081 for (i = 0; i < 2000; i++) {
10082 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
10083 break;
10084 udelay(10);
10085 }
10086 if (i >= 2000) {
05dbe005 10087 netdev_err(tp->dev, "%s cannot enable BUFMGR\n", __func__);
1da177e4
LT		 10088 return -ENODEV;
10089 }
10090
4153577a 10091 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5906_A1)
eb07a940 10092 tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2);
b5d3772c 10093
eb07a940 10094 tg3_setup_rxbd_thresholds(tp);
1da177e4
LT		 10095
10096 /* Initialize TG3_BDINFO's at:
10097 * RCVDBDI_STD_BD: standard eth size rx ring
10098 * RCVDBDI_JUMBO_BD: jumbo frame rx ring
10099 * RCVDBDI_MINI_BD: small frame rx ring (??? does not work)
10100 *
10101 * like so:
10102 * TG3_BDINFO_HOST_ADDR: high/low parts of DMA address of ring
10103 * TG3_BDINFO_MAXLEN_FLAGS: (rx max buffer size << 16) |
10104 * ring attribute flags
10105 * TG3_BDINFO_NIC_ADDR: location of descriptors in nic SRAM
10106 *
10107 * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
10108 * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
10109 *
10110 * The size of each ring is fixed in the firmware, but the location is
10111 * configurable.
10112 */
10113 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
21f581a5 10114 ((u64) tpr->rx_std_mapping >> 32));
1da177e4 10115 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
21f581a5 10116 ((u64) tpr->rx_std_mapping & 0xffffffff));
63c3a66f 10117 if (!tg3_flag(tp, 5717_PLUS))
87668d35
MC		 10118 tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
10119 NIC_SRAM_RX_BUFFER_DESC);
1da177e4 10120
fdb72b38 10121 /* Disable the mini ring */
63c3a66f 10122 if (!tg3_flag(tp, 5705_PLUS))
1da177e4
LT		 10123 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
10124 BDINFO_FLAGS_DISABLED);
10125
fdb72b38
MC		 10126 /* Program the jumbo buffer descriptor ring control
10127 * blocks on those devices that have them.
10128 */
4153577a 10129 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5719_A0 ||
63c3a66f 10130 (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS))) {
1da177e4 10131
63c3a66f 10132 if (tg3_flag(tp, JUMBO_RING_ENABLE)) {
1da177e4 10133 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
21f581a5 10134 ((u64) tpr->rx_jmb_mapping >> 32));
1da177e4 10135 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
21f581a5 10136 ((u64) tpr->rx_jmb_mapping & 0xffffffff));
de9f5230
MC		 10137 val = TG3_RX_JMB_RING_SIZE(tp) <<
10138 BDINFO_FLAGS_MAXLEN_SHIFT;
1da177e4 10139 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
de9f5230 10140 val | BDINFO_FLAGS_USE_EXT_RECV);
63c3a66f 10141 if (!tg3_flag(tp, USE_JUMBO_BDFLAG) ||
c65a17f4 10142 tg3_flag(tp, 57765_CLASS) ||
4153577a 10143 tg3_asic_rev(tp) == ASIC_REV_5762)
87668d35
MC		 10144 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
10145 NIC_SRAM_RX_JUMBO_BUFFER_DESC);
1da177e4
LT		 10146 } else {
10147 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
10148 BDINFO_FLAGS_DISABLED);
10149 }
10150
63c3a66f 10151 if (tg3_flag(tp, 57765_PLUS)) {
fa6b2aae 10152 val = TG3_RX_STD_RING_SIZE(tp);
7cb32cf2
MC		 10153 val <<= BDINFO_FLAGS_MAXLEN_SHIFT;
10154 val |= (TG3_RX_STD_DMA_SZ << 2);
10155 } else
04380d40 10156 val = TG3_RX_STD_DMA_SZ << BDINFO_FLAGS_MAXLEN_SHIFT;
fdb72b38 10157 } else
de9f5230 10158 val = TG3_RX_STD_MAX_SIZE_5700 << BDINFO_FLAGS_MAXLEN_SHIFT;
fdb72b38
MC		 10159
10160 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS, val);
1da177e4 10161
411da640 10162 tpr->rx_std_prod_idx = tp->rx_pending;
66711e66 10163 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG, tpr->rx_std_prod_idx);
1da177e4 10164
63c3a66f
JP		 10165 tpr->rx_jmb_prod_idx =
10166 tg3_flag(tp, JUMBO_RING_ENABLE) ? tp->rx_jumbo_pending : 0;
66711e66 10167 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG, tpr->rx_jmb_prod_idx);
1da177e4 10168
2d31ecaf
MC		 10169 tg3_rings_reset(tp);
10170
1da177e4 10171 /* Initialize MAC address and backoff seed. */
953c96e0 10172 __tg3_set_mac_addr(tp, false);
1da177e4
LT		 10173
10174 /* MTU + ethernet header + FCS + optional VLAN tag */
f7b493e0
MC		 10175 tw32(MAC_RX_MTU_SIZE,
10176 tp->dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN);
1da177e4
LT		 10177
10178 /* The slot time is changed by tg3_setup_phy if we
10179 * run at gigabit with half duplex.
10180 */
f2096f94
MC		 10181 val = (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
10182 (6 << TX_LENGTHS_IPG_SHIFT) |
10183 (32 << TX_LENGTHS_SLOT_TIME_SHIFT);
10184
4153577a
JP		 10185 if (tg3_asic_rev(tp) == ASIC_REV_5720 ||
10186 tg3_asic_rev(tp) == ASIC_REV_5762)
f2096f94
MC		 10187 val |= tr32(MAC_TX_LENGTHS) &
10188 (TX_LENGTHS_JMB_FRM_LEN_MSK |
10189 TX_LENGTHS_CNT_DWN_VAL_MSK);
10190
10191 tw32(MAC_TX_LENGTHS, val);
1da177e4
LT		 10192
10193 /* Receive rules. */
10194 tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
10195 tw32(RCVLPC_CONFIG, 0x0181);
10196
10197 /* Calculate RDMAC_MODE setting early, we need it to determine
10198 * the RCVLPC_STATE_ENABLE mask.
10199 */
10200 rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
10201 RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
10202 RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
10203 RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
10204 RDMAC_MODE_LNGREAD_ENAB);
85e94ced 10205
4153577a 10206 if (tg3_asic_rev(tp) == ASIC_REV_5717)
0339e4e3
MC		 10207 rdmac_mode |= RDMAC_MODE_MULT_DMA_RD_DIS;
10208
4153577a
JP		 10209 if (tg3_asic_rev(tp) == ASIC_REV_5784 ||
10210 tg3_asic_rev(tp) == ASIC_REV_5785 ||
10211 tg3_asic_rev(tp) == ASIC_REV_57780)
d30cdd28
MC		 10212 rdmac_mode |= RDMAC_MODE_BD_SBD_CRPT_ENAB |
10213 RDMAC_MODE_MBUF_RBD_CRPT_ENAB |
10214 RDMAC_MODE_MBUF_SBD_CRPT_ENAB;
10215
4153577a
JP		 10216 if (tg3_asic_rev(tp) == ASIC_REV_5705 &&
10217 tg3_chip_rev_id(tp) != CHIPREV_ID_5705_A0) {
63c3a66f 10218 if (tg3_flag(tp, TSO_CAPABLE) &&
4153577a 10219 tg3_asic_rev(tp) == ASIC_REV_5705) {
1da177e4
LT		 10220 rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
10221 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
63c3a66f 10222 !tg3_flag(tp, IS_5788)) {
1da177e4
LT		 10223 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
10224 }
10225 }
10226
63c3a66f 10227 if (tg3_flag(tp, PCI_EXPRESS))
85e94ced
MC		 10228 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
10229
4153577a 10230 if (tg3_asic_rev(tp) == ASIC_REV_57766) {
d3f677af
MC		 10231 tp->dma_limit = 0;
10232 if (tp->dev->mtu <= ETH_DATA_LEN) {
10233 rdmac_mode |= RDMAC_MODE_JMB_2K_MMRR;
10234 tp->dma_limit = TG3_TX_BD_DMA_MAX_2K;
10235 }
10236 }
10237
63c3a66f
JP		 10238 if (tg3_flag(tp, HW_TSO_1) ||
10239 tg3_flag(tp, HW_TSO_2) ||
10240 tg3_flag(tp, HW_TSO_3))
027455ad
MC		 10241 rdmac_mode |= RDMAC_MODE_IPV4_LSO_EN;
10242
108a6c16 10243 if (tg3_flag(tp, 57765_PLUS) ||
4153577a
JP		 10244 tg3_asic_rev(tp) == ASIC_REV_5785 ||
10245 tg3_asic_rev(tp) == ASIC_REV_57780)
027455ad 10246 rdmac_mode |= RDMAC_MODE_IPV6_LSO_EN;
1da177e4 10247
4153577a
JP		 10248 if (tg3_asic_rev(tp) == ASIC_REV_5720 ||
10249 tg3_asic_rev(tp) == ASIC_REV_5762)
f2096f94
MC		 10250 rdmac_mode |= tr32(RDMAC_MODE) & RDMAC_MODE_H2BNC_VLAN_DET;
10251
4153577a
JP		 10252 if (tg3_asic_rev(tp) == ASIC_REV_5761 ||
10253 tg3_asic_rev(tp) == ASIC_REV_5784 ||
10254 tg3_asic_rev(tp) == ASIC_REV_5785 ||
10255 tg3_asic_rev(tp) == ASIC_REV_57780 ||
63c3a66f 10256 tg3_flag(tp, 57765_PLUS)) {
c65a17f4
MC		 10257 u32 tgtreg;
10258
4153577a 10259 if (tg3_asic_rev(tp) == ASIC_REV_5762)
c65a17f4
MC		 10260 tgtreg = TG3_RDMA_RSRVCTRL_REG2;
10261 else
10262 tgtreg = TG3_RDMA_RSRVCTRL_REG;
10263
10264 val = tr32(tgtreg);
4153577a
JP		 10265 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5719_A0 ||
10266 tg3_asic_rev(tp) == ASIC_REV_5762) {
b4495ed8
MC		 10267 val &= ~(TG3_RDMA_RSRVCTRL_TXMRGN_MASK |
10268 TG3_RDMA_RSRVCTRL_FIFO_LWM_MASK |
10269 TG3_RDMA_RSRVCTRL_FIFO_HWM_MASK);
10270 val |= TG3_RDMA_RSRVCTRL_TXMRGN_320B |
10271 TG3_RDMA_RSRVCTRL_FIFO_LWM_1_5K |
10272 TG3_RDMA_RSRVCTRL_FIFO_HWM_1_5K;
b75cc0e4 10273 }
c65a17f4 10274 tw32(tgtreg, val | TG3_RDMA_RSRVCTRL_FIFO_OFLW_FIX);
41a8a7ee
MC		 10275 }
10276
4153577a
JP		 10277 if (tg3_asic_rev(tp) == ASIC_REV_5719 ||
10278 tg3_asic_rev(tp) == ASIC_REV_5720 ||
10279 tg3_asic_rev(tp) == ASIC_REV_5762) {
c65a17f4
MC		 10280 u32 tgtreg;
10281
4153577a 10282 if (tg3_asic_rev(tp) == ASIC_REV_5762)
c65a17f4
MC		 10283 tgtreg = TG3_LSO_RD_DMA_CRPTEN_CTRL2;
10284 else
10285 tgtreg = TG3_LSO_RD_DMA_CRPTEN_CTRL;
10286
10287 val = tr32(tgtreg);
10288 tw32(tgtreg, val |
d309a46e
MC		 10289 TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_BD_4K |
10290 TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_LSO_4K);
10291 }
10292
1da177e4 10293 /* Receive/send statistics. */
63c3a66f 10294 if (tg3_flag(tp, 5750_PLUS)) {
1661394e
MC		 10295 val = tr32(RCVLPC_STATS_ENABLE);
10296 val &= ~RCVLPC_STATSENAB_DACK_FIX;
10297 tw32(RCVLPC_STATS_ENABLE, val);
10298 } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
63c3a66f 10299 tg3_flag(tp, TSO_CAPABLE)) {
1da177e4
LT		 10300 val = tr32(RCVLPC_STATS_ENABLE);
10301 val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
10302 tw32(RCVLPC_STATS_ENABLE, val);
10303 } else {
10304 tw32(RCVLPC_STATS_ENABLE, 0xffffff);
10305 }
10306 tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
10307 tw32(SNDDATAI_STATSENAB, 0xffffff);
10308 tw32(SNDDATAI_STATSCTRL,
10309 (SNDDATAI_SCTRL_ENABLE |
10310 SNDDATAI_SCTRL_FASTUPD));
10311
10312 /* Setup host coalescing engine. */
10313 tw32(HOSTCC_MODE, 0);
10314 for (i = 0; i < 2000; i++) {
10315 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
10316 break;
10317 udelay(10);
10318 }
10319
d244c892 10320 __tg3_set_coalesce(tp, &tp->coal);
1da177e4 10321
63c3a66f 10322 if (!tg3_flag(tp, 5705_PLUS)) {
1da177e4
LT		 10323 /* Status/statistics block address. See tg3_timer,
10324 * the tg3_periodic_fetch_stats call there, and
10325 * tg3_get_stats to see how this works for 5705/5750 chips.
10326 */
1da177e4
LT		 10327 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
10328 ((u64) tp->stats_mapping >> 32));
10329 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
10330 ((u64) tp->stats_mapping & 0xffffffff));
10331 tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
2d31ecaf 10332
1da177e4 10333 tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
2d31ecaf
MC		 10334
10335 /* Clear statistics and status block memory areas */
10336 for (i = NIC_SRAM_STATS_BLK;
10337 i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
10338 i += sizeof(u32)) {
10339 tg3_write_mem(tp, i, 0);
10340 udelay(40);
10341 }
1da177e4
LT		 10342 }
10343
10344 tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
10345
10346 tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
10347 tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
63c3a66f 10348 if (!tg3_flag(tp, 5705_PLUS))
1da177e4
LT		 10349 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
10350
f07e9af3
MC		 10351 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) {
10352 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
c94e3941
MC		 10353 /* reset to prevent losing 1st rx packet intermittently */
10354 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
10355 udelay(10);
10356 }
10357
3bda1258 10358 tp->mac_mode |= MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
9e975cc2
MC		 10359 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE |
10360 MAC_MODE_FHDE_ENABLE;
10361 if (tg3_flag(tp, ENABLE_APE))
10362 tp->mac_mode |= MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
63c3a66f 10363 if (!tg3_flag(tp, 5705_PLUS) &&
f07e9af3 10364 !(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
4153577a 10365 tg3_asic_rev(tp) != ASIC_REV_5700)
e8f3f6ca 10366 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
1da177e4
LT		 10367 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
10368 udelay(40);
10369
314fba34 10370 /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
63c3a66f 10371 * If TG3_FLAG_IS_NIC is zero, we should read the
314fba34
MC		 10372 * register to preserve the GPIO settings for LOMs. The GPIOs,
10373 * whether used as inputs or outputs, are set by boot code after
10374 * reset.
10375 */
63c3a66f 10376 if (!tg3_flag(tp, IS_NIC)) {
314fba34
MC		 10377 u32 gpio_mask;
10378
9d26e213
MC		 10379 gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 |
10380 GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 |
10381 GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2;
3e7d83bc 10382
4153577a 10383 if (tg3_asic_rev(tp) == ASIC_REV_5752)
3e7d83bc
MC		 10384 gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
10385 GRC_LCLCTRL_GPIO_OUTPUT3;
10386
4153577a 10387 if (tg3_asic_rev(tp) == ASIC_REV_5755)
af36e6b6
MC		 10388 gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL;
10389
aaf84465 10390 tp->grc_local_ctrl &= ~gpio_mask;
314fba34
MC		 10391 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
10392
10393 /* GPIO1 must be driven high for eeprom write protect */
63c3a66f 10394 if (tg3_flag(tp, EEPROM_WRITE_PROT))
9d26e213
MC		 10395 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
10396 GRC_LCLCTRL_GPIO_OUTPUT1);
314fba34 10397 }
1da177e4
LT		 10398 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
10399 udelay(100);
10400
c3b5003b 10401 if (tg3_flag(tp, USING_MSIX)) {
baf8a94a 10402 val = tr32(MSGINT_MODE);
c3b5003b
MC		 10403 val |= MSGINT_MODE_ENABLE;
10404 if (tp->irq_cnt > 1)
10405 val |= MSGINT_MODE_MULTIVEC_EN;
5b39de91
MC		 10406 if (!tg3_flag(tp, 1SHOT_MSI))
10407 val |= MSGINT_MODE_ONE_SHOT_DISABLE;
baf8a94a
MC		 10408 tw32(MSGINT_MODE, val);
10409 }
10410
63c3a66f 10411 if (!tg3_flag(tp, 5705_PLUS)) {
1da177e4
LT		 10412 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
10413 udelay(40);
10414 }
10415
10416 val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
10417 WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
10418 WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
10419 WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
10420 WDMAC_MODE_LNGREAD_ENAB);
10421
4153577a
JP		 10422 if (tg3_asic_rev(tp) == ASIC_REV_5705 &&
10423 tg3_chip_rev_id(tp) != CHIPREV_ID_5705_A0) {
63c3a66f 10424 if (tg3_flag(tp, TSO_CAPABLE) &&
4153577a
JP		 10425 (tg3_chip_rev_id(tp) == CHIPREV_ID_5705_A1 ||
10426 tg3_chip_rev_id(tp) == CHIPREV_ID_5705_A2)) {
1da177e4
LT		 10427 /* nothing */
10428 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
63c3a66f 10429 !tg3_flag(tp, IS_5788)) {
1da177e4
LT		 10430 val |= WDMAC_MODE_RX_ACCEL;
10431 }
10432 }
10433
d9ab5ad1 10434 /* Enable host coalescing bug fix */
63c3a66f 10435 if (tg3_flag(tp, 5755_PLUS))
f51f3562 10436 val |= WDMAC_MODE_STATUS_TAG_FIX;
d9ab5ad1 10437
4153577a 10438 if (tg3_asic_rev(tp) == ASIC_REV_5785)
788a035e
MC		 10439 val |= WDMAC_MODE_BURST_ALL_DATA;
10440
1da177e4
LT		 10441 tw32_f(WDMAC_MODE, val);
10442 udelay(40);
10443
63c3a66f 10444 if (tg3_flag(tp, PCIX_MODE)) {
9974a356
MC		 10445 u16 pcix_cmd;
10446
10447 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
10448 &pcix_cmd);
4153577a 10449 if (tg3_asic_rev(tp) == ASIC_REV_5703) {
9974a356
MC		 10450 pcix_cmd &= ~PCI_X_CMD_MAX_READ;
10451 pcix_cmd |= PCI_X_CMD_READ_2K;
4153577a 10452 } else if (tg3_asic_rev(tp) == ASIC_REV_5704) {
9974a356
MC		 10453 pcix_cmd &= ~(PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ);
10454 pcix_cmd |= PCI_X_CMD_READ_2K;
1da177e4 10455 }
9974a356
MC		 10456 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
10457 pcix_cmd);
1da177e4
LT		 10458 }
10459
10460 tw32_f(RDMAC_MODE, rdmac_mode);
10461 udelay(40);
10462
9bc297ea
NS		 10463 if (tg3_asic_rev(tp) == ASIC_REV_5719 ||
10464 tg3_asic_rev(tp) == ASIC_REV_5720) {
091f0ea3
MC		 10465 for (i = 0; i < TG3_NUM_RDMA_CHANNELS; i++) {
10466 if (tr32(TG3_RDMA_LENGTH + (i << 2)) > TG3_MAX_MTU(tp))
10467 break;
10468 }
10469 if (i < TG3_NUM_RDMA_CHANNELS) {
10470 val = tr32(TG3_LSO_RD_DMA_CRPTEN_CTRL);
9bc297ea 10471 val |= tg3_lso_rd_dma_workaround_bit(tp);
091f0ea3 10472 tw32(TG3_LSO_RD_DMA_CRPTEN_CTRL, val);
9bc297ea 10473 tg3_flag_set(tp, 5719_5720_RDMA_BUG);
091f0ea3
MC		 10474 }
10475 }
10476
1da177e4 10477 tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
63c3a66f 10478 if (!tg3_flag(tp, 5705_PLUS))
1da177e4 10479 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
9936bcf6 10480
4153577a 10481 if (tg3_asic_rev(tp) == ASIC_REV_5761)
9936bcf6
MC		 10482 tw32(SNDDATAC_MODE,
10483 SNDDATAC_MODE_ENABLE | SNDDATAC_MODE_CDELAY);
10484 else
10485 tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
10486
1da177e4
LT		 10487 tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
10488 tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
7cb32cf2 10489 val = RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ;
63c3a66f 10490 if (tg3_flag(tp, LRG_PROD_RING_CAP))
7cb32cf2
MC		 10491 val |= RCVDBDI_MODE_LRG_RING_SZ;
10492 tw32(RCVDBDI_MODE, val);
1da177e4 10493 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
63c3a66f
JP		 10494 if (tg3_flag(tp, HW_TSO_1) ||
10495 tg3_flag(tp, HW_TSO_2) ||
10496 tg3_flag(tp, HW_TSO_3))
1da177e4 10497 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
baf8a94a 10498 val = SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE;
63c3a66f 10499 if (tg3_flag(tp, ENABLE_TSS))
baf8a94a
MC		 10500 val |= SNDBDI_MODE_MULTI_TXQ_EN;
10501 tw32(SNDBDI_MODE, val);
1da177e4
LT		 10502 tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
10503
4153577a 10504 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0) {
1da177e4
LT		 10505 err = tg3_load_5701_a0_firmware_fix(tp);
10506 if (err)
10507 return err;
10508 }
10509
c4dab506
NS		 10510 if (tg3_asic_rev(tp) == ASIC_REV_57766) {
10511 /* Ignore any errors for the firmware download. If download
10512 * fails, the device will operate with EEE disabled
10513 */
10514 tg3_load_57766_firmware(tp);
10515 }
10516
63c3a66f 10517 if (tg3_flag(tp, TSO_CAPABLE)) {
1da177e4
LT		 10518 err = tg3_load_tso_firmware(tp);
10519 if (err)
10520 return err;
10521 }
1da177e4
LT		 10522
10523 tp->tx_mode = TX_MODE_ENABLE;
f2096f94 10524
63c3a66f 10525 if (tg3_flag(tp, 5755_PLUS) ||
4153577a 10526 tg3_asic_rev(tp) == ASIC_REV_5906)
b1d05210 10527 tp->tx_mode |= TX_MODE_MBUF_LOCKUP_FIX;
f2096f94 10528
4153577a
JP		 10529 if (tg3_asic_rev(tp) == ASIC_REV_5720 ||
10530 tg3_asic_rev(tp) == ASIC_REV_5762) {
f2096f94
MC		 10531 val = TX_MODE_JMB_FRM_LEN | TX_MODE_CNT_DN_MODE;
10532 tp->tx_mode &= ~val;
10533 tp->tx_mode |= tr32(MAC_TX_MODE) & val;
10534 }
10535
1da177e4
LT		 10536 tw32_f(MAC_TX_MODE, tp->tx_mode);
10537 udelay(100);
10538
63c3a66f 10539 if (tg3_flag(tp, ENABLE_RSS)) {
bcebcc46 10540 tg3_rss_write_indir_tbl(tp);
baf8a94a
MC		 10541
10542 /* Setup the "secret" hash key. */
10543 tw32(MAC_RSS_HASH_KEY_0, 0x5f865437);
10544 tw32(MAC_RSS_HASH_KEY_1, 0xe4ac62cc);
10545 tw32(MAC_RSS_HASH_KEY_2, 0x50103a45);
10546 tw32(MAC_RSS_HASH_KEY_3, 0x36621985);
10547 tw32(MAC_RSS_HASH_KEY_4, 0xbf14c0e8);
10548 tw32(MAC_RSS_HASH_KEY_5, 0x1bc27a1e);
10549 tw32(MAC_RSS_HASH_KEY_6, 0x84f4b556);
10550 tw32(MAC_RSS_HASH_KEY_7, 0x094ea6fe);
10551 tw32(MAC_RSS_HASH_KEY_8, 0x7dda01e7);
10552 tw32(MAC_RSS_HASH_KEY_9, 0xc04d7481);
10553 }
10554
1da177e4 10555 tp->rx_mode = RX_MODE_ENABLE;
63c3a66f 10556 if (tg3_flag(tp, 5755_PLUS))
af36e6b6
MC		 10557 tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;
10558
378b72c8
NS		 10559 if (tg3_asic_rev(tp) == ASIC_REV_5762)
10560 tp->rx_mode |= RX_MODE_IPV4_FRAG_FIX;
10561
63c3a66f 10562 if (tg3_flag(tp, ENABLE_RSS))
baf8a94a
MC		 10563 tp->rx_mode |= RX_MODE_RSS_ENABLE |
10564 RX_MODE_RSS_ITBL_HASH_BITS_7 |
10565 RX_MODE_RSS_IPV6_HASH_EN |
10566 RX_MODE_RSS_TCP_IPV6_HASH_EN |
10567 RX_MODE_RSS_IPV4_HASH_EN |
10568 RX_MODE_RSS_TCP_IPV4_HASH_EN;
10569
1da177e4
LT		 10570 tw32_f(MAC_RX_MODE, tp->rx_mode);
10571 udelay(10);
10572
1da177e4
LT		 10573 tw32(MAC_LED_CTRL, tp->led_ctrl);
10574
10575 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
f07e9af3 10576 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
1da177e4
LT		 10577 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
10578 udelay(10);
10579 }
10580 tw32_f(MAC_RX_MODE, tp->rx_mode);
10581 udelay(10);
10582
f07e9af3 10583 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
4153577a
JP		 10584 if ((tg3_asic_rev(tp) == ASIC_REV_5704) &&
10585 !(tp->phy_flags & TG3_PHYFLG_SERDES_PREEMPHASIS)) {
1da177e4
LT		 10586 /* Set drive transmission level to 1.2V */
10587 /* only if the signal pre-emphasis bit is not set */
10588 val = tr32(MAC_SERDES_CFG);
10589 val &= 0xfffff000;
10590 val |= 0x880;
10591 tw32(MAC_SERDES_CFG, val);
10592 }
4153577a 10593 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5703_A1)
1da177e4
LT		 10594 tw32(MAC_SERDES_CFG, 0x616000);
10595 }
10596
10597 /* Prevent chip from dropping frames when flow control
10598 * is enabled.
10599 */
55086ad9 10600 if (tg3_flag(tp, 57765_CLASS))
666bc831
MC		 10601 val = 1;
10602 else
10603 val = 2;
10604 tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, val);
1da177e4 10605
4153577a 10606 if (tg3_asic_rev(tp) == ASIC_REV_5704 &&
f07e9af3 10607 (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
1da177e4 10608 /* Use hardware link auto-negotiation */
63c3a66f 10609 tg3_flag_set(tp, HW_AUTONEG);
1da177e4
LT		 10610 }
10611
f07e9af3 10612 if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
4153577a 10613 tg3_asic_rev(tp) == ASIC_REV_5714) {
d4d2c558
MC		 10614 u32 tmp;
10615
10616 tmp = tr32(SERDES_RX_CTRL);
10617 tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT);
10618 tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT;
10619 tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT;
10620 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
10621 }
10622
63c3a66f 10623 if (!tg3_flag(tp, USE_PHYLIB)) {
c6700ce2 10624 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
80096068 10625 tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER;
1da177e4 10626
953c96e0 10627 err = tg3_setup_phy(tp, false);
dd477003
MC		 10628 if (err)
10629 return err;
1da177e4 10630
f07e9af3
MC		 10631 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
10632 !(tp->phy_flags & TG3_PHYFLG_IS_FET)) {
dd477003
MC		 10633 u32 tmp;
10634
10635 /* Clear CRC stats. */
10636 if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) {
10637 tg3_writephy(tp, MII_TG3_TEST1,
10638 tmp | MII_TG3_TEST1_CRC_EN);
f08aa1a8 10639 tg3_readphy(tp, MII_TG3_RXR_COUNTERS, &tmp);
dd477003 10640 }
1da177e4
LT		 10641 }
10642 }
10643
10644 __tg3_set_rx_mode(tp->dev);
10645
10646 /* Initialize receive rules. */
10647 tw32(MAC_RCV_RULE_0, 0xc2000000 & RCV_RULE_DISABLE_MASK);
10648 tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
10649 tw32(MAC_RCV_RULE_1, 0x86000004 & RCV_RULE_DISABLE_MASK);
10650 tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
10651
63c3a66f 10652 if (tg3_flag(tp, 5705_PLUS) && !tg3_flag(tp, 5780_CLASS))
1da177e4
LT		 10653 limit = 8;
10654 else
10655 limit = 16;
63c3a66f 10656 if (tg3_flag(tp, ENABLE_ASF))
1da177e4
LT		 10657 limit -= 4;
10658 switch (limit) {
10659 case 16:
10660 tw32(MAC_RCV_RULE_15, 0); tw32(MAC_RCV_VALUE_15, 0);
10661 case 15:
10662 tw32(MAC_RCV_RULE_14, 0); tw32(MAC_RCV_VALUE_14, 0);
10663 case 14:
10664 tw32(MAC_RCV_RULE_13, 0); tw32(MAC_RCV_VALUE_13, 0);
10665 case 13:
10666 tw32(MAC_RCV_RULE_12, 0); tw32(MAC_RCV_VALUE_12, 0);
10667 case 12:
10668 tw32(MAC_RCV_RULE_11, 0); tw32(MAC_RCV_VALUE_11, 0);
10669 case 11:
10670 tw32(MAC_RCV_RULE_10, 0); tw32(MAC_RCV_VALUE_10, 0);
10671 case 10:
10672 tw32(MAC_RCV_RULE_9, 0); tw32(MAC_RCV_VALUE_9, 0);
10673 case 9:
10674 tw32(MAC_RCV_RULE_8, 0); tw32(MAC_RCV_VALUE_8, 0);
10675 case 8:
10676 tw32(MAC_RCV_RULE_7, 0); tw32(MAC_RCV_VALUE_7, 0);
10677 case 7:
10678 tw32(MAC_RCV_RULE_6, 0); tw32(MAC_RCV_VALUE_6, 0);
10679 case 6:
10680 tw32(MAC_RCV_RULE_5, 0); tw32(MAC_RCV_VALUE_5, 0);
10681 case 5:
10682 tw32(MAC_RCV_RULE_4, 0); tw32(MAC_RCV_VALUE_4, 0);
10683 case 4:
10684 /* tw32(MAC_RCV_RULE_3, 0); tw32(MAC_RCV_VALUE_3, 0); */
10685 case 3:
10686 /* tw32(MAC_RCV_RULE_2, 0); tw32(MAC_RCV_VALUE_2, 0); */
10687 case 2:
10688 case 1:
10689
10690 default:
10691 break;
855e1111 10692 }
1da177e4 10693
63c3a66f 10694 if (tg3_flag(tp, ENABLE_APE))
9ce768ea
MC		 10695 /* Write our heartbeat update interval to APE. */
10696 tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_INT_MS,
10697 APE_HOST_HEARTBEAT_INT_DISABLE);
0d3031d9 10698
1da177e4
LT		 10699 tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
10700
1da177e4
LT		 10701 return 0;
10702}
10703
10704/* Called at device open time to get the chip ready for
10705 * packet processing. Invoked with tp->lock held.
10706 */
953c96e0 10707static int tg3_init_hw(struct tg3 *tp, bool reset_phy)
1da177e4 10708{
df465abf
NS		 10709 /* Chip may have been just powered on. If so, the boot code may still
10710 * be running initialization. Wait for it to finish to avoid races in
10711 * accessing the hardware.
10712 */
10713 tg3_enable_register_access(tp);
10714 tg3_poll_fw(tp);
10715
1da177e4
LT		 10716 tg3_switch_clocks(tp);
10717
10718 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
10719
2f751b67 10720 return tg3_reset_hw(tp, reset_phy);
1da177e4
LT		 10721}
10722
aed93e0b
MC		 10723static void tg3_sd_scan_scratchpad(struct tg3 *tp, struct tg3_ocir *ocir)
10724{
10725 int i;
10726
10727 for (i = 0; i < TG3_SD_NUM_RECS; i++, ocir++) {
10728 u32 off = i * TG3_OCIR_LEN, len = TG3_OCIR_LEN;
10729
10730 tg3_ape_scratchpad_read(tp, (u32 *) ocir, off, len);
10731 off += len;
10732
10733 if (ocir->signature != TG3_OCIR_SIG_MAGIC ||
10734 !(ocir->version_flags & TG3_OCIR_FLAG_ACTIVE))
10735 memset(ocir, 0, TG3_OCIR_LEN);
10736 }
10737}
10738
10739/* sysfs attributes for hwmon */
10740static ssize_t tg3_show_temp(struct device *dev,
10741 struct device_attribute *devattr, char *buf)
10742{
aed93e0b 10743 struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr);
a2f4dfba 10744 struct tg3 *tp = dev_get_drvdata(dev);
aed93e0b
MC		 10745 u32 temperature;
10746
10747 spin_lock_bh(&tp->lock);
10748 tg3_ape_scratchpad_read(tp, &temperature, attr->index,
10749 sizeof(temperature));
10750 spin_unlock_bh(&tp->lock);
10751 return sprintf(buf, "%u\n", temperature);
10752}
10753
10754
10755static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, tg3_show_temp, NULL,
10756 TG3_TEMP_SENSOR_OFFSET);
10757static SENSOR_DEVICE_ATTR(temp1_crit, S_IRUGO, tg3_show_temp, NULL,
10758 TG3_TEMP_CAUTION_OFFSET);
10759static SENSOR_DEVICE_ATTR(temp1_max, S_IRUGO, tg3_show_temp, NULL,
10760 TG3_TEMP_MAX_OFFSET);
10761
a2f4dfba 10762static struct attribute *tg3_attrs[] = {
aed93e0b
MC		 10763 &sensor_dev_attr_temp1_input.dev_attr.attr,
10764 &sensor_dev_attr_temp1_crit.dev_attr.attr,
10765 &sensor_dev_attr_temp1_max.dev_attr.attr,
10766 NULL
10767};
a2f4dfba 10768ATTRIBUTE_GROUPS(tg3);
aed93e0b 10769
aed93e0b
MC		 10770static void tg3_hwmon_close(struct tg3 *tp)
10771{
aed93e0b
MC		 10772 if (tp->hwmon_dev) {
10773 hwmon_device_unregister(tp->hwmon_dev);
10774 tp->hwmon_dev = NULL;
aed93e0b 10775 }
aed93e0b
MC		 10776}
10777
10778static void tg3_hwmon_open(struct tg3 *tp)
10779{
a2f4dfba 10780 int i;
aed93e0b
MC		 10781 u32 size = 0;
10782 struct pci_dev *pdev = tp->pdev;
10783 struct tg3_ocir ocirs[TG3_SD_NUM_RECS];
10784
10785 tg3_sd_scan_scratchpad(tp, ocirs);
10786
10787 for (i = 0; i < TG3_SD_NUM_RECS; i++) {
10788 if (!ocirs[i].src_data_length)
10789 continue;
10790
10791 size += ocirs[i].src_hdr_length;
10792 size += ocirs[i].src_data_length;
10793 }
10794
10795 if (!size)
10796 return;
10797
a2f4dfba
GR		 10798 tp->hwmon_dev = hwmon_device_register_with_groups(&pdev->dev, "tg3",
10799 tp, tg3_groups);
aed93e0b
MC		 10800 if (IS_ERR(tp->hwmon_dev)) {
10801 tp->hwmon_dev = NULL;
10802 dev_err(&pdev->dev, "Cannot register hwmon device, aborting\n");
aed93e0b 10803 }
aed93e0b
MC		 10804}
10805
10806
1da177e4
LT		 10807#define TG3_STAT_ADD32(PSTAT, REG) \
10808do { u32 __val = tr32(REG); \
10809 (PSTAT)->low += __val; \
10810 if ((PSTAT)->low < __val) \
10811 (PSTAT)->high += 1; \
10812} while (0)
10813
10814static void tg3_periodic_fetch_stats(struct tg3 *tp)
10815{
10816 struct tg3_hw_stats *sp = tp->hw_stats;
10817
f4a46d1f 10818 if (!tp->link_up)
1da177e4
LT		 10819 return;
10820
10821 TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
10822 TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
10823 TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
10824 TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
10825 TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
10826 TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
10827 TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
10828 TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
10829 TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
10830 TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
10831 TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
10832 TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
10833 TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
9bc297ea 10834 if (unlikely(tg3_flag(tp, 5719_5720_RDMA_BUG) &&
091f0ea3
MC		 10835 (sp->tx_ucast_packets.low + sp->tx_mcast_packets.low +
10836 sp->tx_bcast_packets.low) > TG3_NUM_RDMA_CHANNELS)) {
10837 u32 val;
10838
10839 val = tr32(TG3_LSO_RD_DMA_CRPTEN_CTRL);
9bc297ea 10840 val &= ~tg3_lso_rd_dma_workaround_bit(tp);
091f0ea3 10841 tw32(TG3_LSO_RD_DMA_CRPTEN_CTRL, val);
9bc297ea 10842 tg3_flag_clear(tp, 5719_5720_RDMA_BUG);
091f0ea3 10843 }
1da177e4
LT		 10844
10845 TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
10846 TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
10847 TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
10848 TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
10849 TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
10850 TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
10851 TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
10852 TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
10853 TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
10854 TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
10855 TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
10856 TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
10857 TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
10858 TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
463d305b
MC		 10859
10860 TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT);
4153577a 10861 if (tg3_asic_rev(tp) != ASIC_REV_5717 &&
94962f7f 10862 tg3_asic_rev(tp) != ASIC_REV_5762 &&
4153577a
JP		 10863 tg3_chip_rev_id(tp) != CHIPREV_ID_5719_A0 &&
10864 tg3_chip_rev_id(tp) != CHIPREV_ID_5720_A0) {
4d958473
MC		 10865 TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT);
10866 } else {
10867 u32 val = tr32(HOSTCC_FLOW_ATTN);
10868 val = (val & HOSTCC_FLOW_ATTN_MBUF_LWM) ? 1 : 0;
10869 if (val) {
10870 tw32(HOSTCC_FLOW_ATTN, HOSTCC_FLOW_ATTN_MBUF_LWM);
10871 sp->rx_discards.low += val;
10872 if (sp->rx_discards.low < val)
10873 sp->rx_discards.high += 1;
10874 }
10875 sp->mbuf_lwm_thresh_hit = sp->rx_discards;
10876 }
463d305b 10877 TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT);
1da177e4
LT		 10878}
10879
0e6cf6a9
MC		 10880static void tg3_chk_missed_msi(struct tg3 *tp)
10881{
10882 u32 i;
10883
10884 for (i = 0; i < tp->irq_cnt; i++) {
10885 struct tg3_napi *tnapi = &tp->napi[i];
10886
10887 if (tg3_has_work(tnapi)) {
10888 if (tnapi->last_rx_cons == tnapi->rx_rcb_ptr &&
10889 tnapi->last_tx_cons == tnapi->tx_cons) {
10890 if (tnapi->chk_msi_cnt < 1) {
10891 tnapi->chk_msi_cnt++;
10892 return;
10893 }
7f230735 10894 tg3_msi(0, tnapi);
0e6cf6a9
MC		 10895 }
10896 }
10897 tnapi->chk_msi_cnt = 0;
10898 tnapi->last_rx_cons = tnapi->rx_rcb_ptr;
10899 tnapi->last_tx_cons = tnapi->tx_cons;
10900 }
10901}
10902
1da177e4
LT		 10903static void tg3_timer(unsigned long __opaque)
10904{
10905 struct tg3 *tp = (struct tg3 *) __opaque;
1da177e4 10906
5b190624 10907 if (tp->irq_sync || tg3_flag(tp, RESET_TASK_PENDING))
f475f163
MC		 10908 goto restart_timer;
10909
f47c11ee 10910 spin_lock(&tp->lock);
1da177e4 10911
4153577a 10912 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
55086ad9 10913 tg3_flag(tp, 57765_CLASS))
0e6cf6a9
MC		 10914 tg3_chk_missed_msi(tp);
10915
7e6c63f0
HM		 10916 if (tg3_flag(tp, FLUSH_POSTED_WRITES)) {
10917 /* BCM4785: Flush posted writes from GbE to host memory. */
10918 tr32(HOSTCC_MODE);
10919 }
10920
63c3a66f 10921 if (!tg3_flag(tp, TAGGED_STATUS)) {
fac9b83e
DM		 10922 /* All of this garbage is because when using non-tagged
10923 * IRQ status the mailbox/status_block protocol the chip
10924 * uses with the cpu is race prone.
10925 */
898a56f8 10926 if (tp->napi[0].hw_status->status & SD_STATUS_UPDATED) {
fac9b83e
DM		 10927 tw32(GRC_LOCAL_CTRL,
10928 tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
10929 } else {
10930 tw32(HOSTCC_MODE, tp->coalesce_mode |
fd2ce37f 10931 HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW);
fac9b83e 10932 }
1da177e4 10933
fac9b83e 10934 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
f47c11ee 10935 spin_unlock(&tp->lock);
db219973 10936 tg3_reset_task_schedule(tp);
5b190624 10937 goto restart_timer;
fac9b83e 10938 }
1da177e4
LT		 10939 }
10940
1da177e4
LT		 10941 /* This part only runs once per second. */
10942 if (!--tp->timer_counter) {
63c3a66f 10943 if (tg3_flag(tp, 5705_PLUS))
fac9b83e
DM		 10944 tg3_periodic_fetch_stats(tp);
10945
b0c5943f
MC		 10946 if (tp->setlpicnt && !--tp->setlpicnt)
10947 tg3_phy_eee_enable(tp);
52b02d04 10948
63c3a66f 10949 if (tg3_flag(tp, USE_LINKCHG_REG)) {
1da177e4
LT		 10950 u32 mac_stat;
10951 int phy_event;
10952
10953 mac_stat = tr32(MAC_STATUS);
10954
10955 phy_event = 0;
f07e9af3 10956 if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) {
1da177e4
LT		 10957 if (mac_stat & MAC_STATUS_MI_INTERRUPT)
10958 phy_event = 1;
10959 } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
10960 phy_event = 1;
10961
10962 if (phy_event)
953c96e0 10963 tg3_setup_phy(tp, false);
63c3a66f 10964 } else if (tg3_flag(tp, POLL_SERDES)) {
1da177e4
LT		 10965 u32 mac_stat = tr32(MAC_STATUS);
10966 int need_setup = 0;
10967
f4a46d1f 10968 if (tp->link_up &&
1da177e4
LT		 10969 (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
10970 need_setup = 1;
10971 }
f4a46d1f 10972 if (!tp->link_up &&
1da177e4
LT		 10973 (mac_stat & (MAC_STATUS_PCS_SYNCED |
10974 MAC_STATUS_SIGNAL_DET))) {
10975 need_setup = 1;
10976 }
10977 if (need_setup) {
3d3ebe74
MC		 10978 if (!tp->serdes_counter) {
10979 tw32_f(MAC_MODE,
10980 (tp->mac_mode &
10981 ~MAC_MODE_PORT_MODE_MASK));
10982 udelay(40);
10983 tw32_f(MAC_MODE, tp->mac_mode);
10984 udelay(40);
10985 }
953c96e0 10986 tg3_setup_phy(tp, false);
1da177e4 10987 }
f07e9af3 10988 } else if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
63c3a66f 10989 tg3_flag(tp, 5780_CLASS)) {
747e8f8b 10990 tg3_serdes_parallel_detect(tp);
1743b83c
NS		 10991 } else if (tg3_flag(tp, POLL_CPMU_LINK)) {
10992 u32 cpmu = tr32(TG3_CPMU_STATUS);
10993 bool link_up = !((cpmu & TG3_CPMU_STATUS_LINK_MASK) ==
10994 TG3_CPMU_STATUS_LINK_MASK);
10995
10996 if (link_up != tp->link_up)
10997 tg3_setup_phy(tp, false);
57d8b880 10998 }
1da177e4
LT		 10999
11000 tp->timer_counter = tp->timer_multiplier;
11001 }
11002
130b8e4d
MC		 11003 /* Heartbeat is only sent once every 2 seconds.
11004 *
11005 * The heartbeat is to tell the ASF firmware that the host
11006 * driver is still alive. In the event that the OS crashes,
11007 * ASF needs to reset the hardware to free up the FIFO space
11008 * that may be filled with rx packets destined for the host.
11009 * If the FIFO is full, ASF will no longer function properly.
11010 *
11011 * Unintended resets have been reported on real time kernels
11012 * where the timer doesn't run on time. Netpoll will also have
11013 * same problem.
11014 *
11015 * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware
11016 * to check the ring condition when the heartbeat is expiring
11017 * before doing the reset. This will prevent most unintended
11018 * resets.
11019 */
1da177e4 11020 if (!--tp->asf_counter) {
63c3a66f 11021 if (tg3_flag(tp, ENABLE_ASF) && !tg3_flag(tp, ENABLE_APE)) {
7c5026aa
MC		 11022 tg3_wait_for_event_ack(tp);
11023
bbadf503 11024 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
130b8e4d 11025 FWCMD_NICDRV_ALIVE3);
bbadf503 11026 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
c6cdf436
MC		 11027 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX,
11028 TG3_FW_UPDATE_TIMEOUT_SEC);
4ba526ce
MC		 11029
11030 tg3_generate_fw_event(tp);
1da177e4
LT		 11031 }
11032 tp->asf_counter = tp->asf_multiplier;
11033 }
11034
f47c11ee 11035 spin_unlock(&tp->lock);
1da177e4 11036
f475f163 11037restart_timer:
1da177e4
LT		 11038 tp->timer.expires = jiffies + tp->timer_offset;
11039 add_timer(&tp->timer);
11040}
11041
229b1ad1 11042static void tg3_timer_init(struct tg3 *tp)
21f7638e
MC		 11043{
11044 if (tg3_flag(tp, TAGGED_STATUS) &&
4153577a 11045 tg3_asic_rev(tp) != ASIC_REV_5717 &&
21f7638e
MC		 11046 !tg3_flag(tp, 57765_CLASS))
11047 tp->timer_offset = HZ;
11048 else
11049 tp->timer_offset = HZ / 10;
11050
11051 BUG_ON(tp->timer_offset > HZ);
11052
11053 tp->timer_multiplier = (HZ / tp->timer_offset);
11054 tp->asf_multiplier = (HZ / tp->timer_offset) *
11055 TG3_FW_UPDATE_FREQ_SEC;
11056
11057 init_timer(&tp->timer);
11058 tp->timer.data = (unsigned long) tp;
11059 tp->timer.function = tg3_timer;
11060}
11061
11062static void tg3_timer_start(struct tg3 *tp)
11063{
11064 tp->asf_counter = tp->asf_multiplier;
11065 tp->timer_counter = tp->timer_multiplier;
11066
11067 tp->timer.expires = jiffies + tp->timer_offset;
11068 add_timer(&tp->timer);
11069}
11070
11071static void tg3_timer_stop(struct tg3 *tp)
11072{
11073 del_timer_sync(&tp->timer);
11074}
11075
11076/* Restart hardware after configuration changes, self-test, etc.
11077 * Invoked with tp->lock held.
11078 */
953c96e0 11079static int tg3_restart_hw(struct tg3 *tp, bool reset_phy)
21f7638e
MC		 11080 __releases(tp->lock)
11081 __acquires(tp->lock)
11082{
11083 int err;
11084
11085 err = tg3_init_hw(tp, reset_phy);
11086 if (err) {
11087 netdev_err(tp->dev,
11088 "Failed to re-initialize device, aborting\n");
11089 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
11090 tg3_full_unlock(tp);
11091 tg3_timer_stop(tp);
11092 tp->irq_sync = 0;
11093 tg3_napi_enable(tp);
11094 dev_close(tp->dev);
11095 tg3_full_lock(tp, 0);
11096 }
11097 return err;
11098}
11099
11100static void tg3_reset_task(struct work_struct *work)
11101{
11102 struct tg3 *tp = container_of(work, struct tg3, reset_task);
11103 int err;
11104
11105 tg3_full_lock(tp, 0);
11106
11107 if (!netif_running(tp->dev)) {
11108 tg3_flag_clear(tp, RESET_TASK_PENDING);
11109 tg3_full_unlock(tp);
11110 return;
11111 }
11112
11113 tg3_full_unlock(tp);
11114
11115 tg3_phy_stop(tp);
11116
11117 tg3_netif_stop(tp);
11118
11119 tg3_full_lock(tp, 1);
11120
11121 if (tg3_flag(tp, TX_RECOVERY_PENDING)) {
11122 tp->write32_tx_mbox = tg3_write32_tx_mbox;
11123 tp->write32_rx_mbox = tg3_write_flush_reg32;
11124 tg3_flag_set(tp, MBOX_WRITE_REORDER);
11125 tg3_flag_clear(tp, TX_RECOVERY_PENDING);
11126 }
11127
11128 tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
953c96e0 11129 err = tg3_init_hw(tp, true);
21f7638e
MC		 11130 if (err)
11131 goto out;
11132
11133 tg3_netif_start(tp);
11134
11135out:
11136 tg3_full_unlock(tp);
11137
11138 if (!err)
11139 tg3_phy_start(tp);
11140
11141 tg3_flag_clear(tp, RESET_TASK_PENDING);
11142}
11143
4f125f42 11144static int tg3_request_irq(struct tg3 *tp, int irq_num)
fcfa0a32 11145{
7d12e780 11146 irq_handler_t fn;
fcfa0a32 11147 unsigned long flags;
4f125f42
MC		 11148 char *name;
11149 struct tg3_napi *tnapi = &tp->napi[irq_num];
11150
11151 if (tp->irq_cnt == 1)
11152 name = tp->dev->name;
11153 else {
11154 name = &tnapi->irq_lbl[0];
21e315e1
NS		 11155 if (tnapi->tx_buffers && tnapi->rx_rcb)
11156 snprintf(name, IFNAMSIZ,
11157 "%s-txrx-%d", tp->dev->name, irq_num);
11158 else if (tnapi->tx_buffers)
11159 snprintf(name, IFNAMSIZ,
11160 "%s-tx-%d", tp->dev->name, irq_num);
11161 else if (tnapi->rx_rcb)
11162 snprintf(name, IFNAMSIZ,
11163 "%s-rx-%d", tp->dev->name, irq_num);
11164 else
11165 snprintf(name, IFNAMSIZ,
11166 "%s-%d", tp->dev->name, irq_num);
4f125f42
MC		 11167 name[IFNAMSIZ-1] = 0;
11168 }
fcfa0a32 11169
63c3a66f 11170 if (tg3_flag(tp, USING_MSI) || tg3_flag(tp, USING_MSIX)) {
fcfa0a32 11171 fn = tg3_msi;
63c3a66f 11172 if (tg3_flag(tp, 1SHOT_MSI))
fcfa0a32 11173 fn = tg3_msi_1shot;
ab392d2d 11174 flags = 0;
fcfa0a32
MC		 11175 } else {
11176 fn = tg3_interrupt;
63c3a66f 11177 if (tg3_flag(tp, TAGGED_STATUS))
fcfa0a32 11178 fn = tg3_interrupt_tagged;
ab392d2d 11179 flags = IRQF_SHARED;
fcfa0a32 11180 }
4f125f42
MC		 11181
11182 return request_irq(tnapi->irq_vec, fn, flags, name, tnapi);
fcfa0a32
MC		 11183}
11184
7938109f
MC		 11185static int tg3_test_interrupt(struct tg3 *tp)
11186{
09943a18 11187 struct tg3_napi *tnapi = &tp->napi[0];
7938109f 11188 struct net_device *dev = tp->dev;
b16250e3 11189 int err, i, intr_ok = 0;
f6eb9b1f 11190 u32 val;
7938109f 11191
d4bc3927
MC		 11192 if (!netif_running(dev))
11193 return -ENODEV;
11194
7938109f
MC		 11195 tg3_disable_ints(tp);
11196
4f125f42 11197 free_irq(tnapi->irq_vec, tnapi);
7938109f 11198
f6eb9b1f
MC		 11199 /*
11200 * Turn off MSI one shot mode. Otherwise this test has no
11201 * observable way to know whether the interrupt was delivered.
11202 */
3aa1cdf8 11203 if (tg3_flag(tp, 57765_PLUS)) {
f6eb9b1f
MC		 11204 val = tr32(MSGINT_MODE) | MSGINT_MODE_ONE_SHOT_DISABLE;
11205 tw32(MSGINT_MODE, val);
11206 }
11207
4f125f42 11208 err = request_irq(tnapi->irq_vec, tg3_test_isr,
f274fd9a 11209 IRQF_SHARED, dev->name, tnapi);
7938109f
MC		 11210 if (err)
11211 return err;
11212
898a56f8 11213 tnapi->hw_status->status &= ~SD_STATUS_UPDATED;
7938109f
MC		 11214 tg3_enable_ints(tp);
11215
11216 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
fd2ce37f 11217 tnapi->coal_now);
7938109f
MC		 11218
11219 for (i = 0; i < 5; i++) {
b16250e3
MC		 11220 u32 int_mbox, misc_host_ctrl;
11221
898a56f8 11222 int_mbox = tr32_mailbox(tnapi->int_mbox);
b16250e3
MC		 11223 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
11224
11225 if ((int_mbox != 0) ||
11226 (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) {
11227 intr_ok = 1;
7938109f 11228 break;
b16250e3
MC		 11229 }
11230
3aa1cdf8
MC		 11231 if (tg3_flag(tp, 57765_PLUS) &&
11232 tnapi->hw_status->status_tag != tnapi->last_tag)
11233 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
11234
7938109f
MC		 11235 msleep(10);
11236 }
11237
11238 tg3_disable_ints(tp);
11239
4f125f42 11240 free_irq(tnapi->irq_vec, tnapi);
6aa20a22 11241
4f125f42 11242 err = tg3_request_irq(tp, 0);
7938109f
MC		 11243
11244 if (err)
11245 return err;
11246
f6eb9b1f
MC		 11247 if (intr_ok) {
11248 /* Reenable MSI one shot mode. */
5b39de91 11249 if (tg3_flag(tp, 57765_PLUS) && tg3_flag(tp, 1SHOT_MSI)) {
f6eb9b1f
MC		 11250 val = tr32(MSGINT_MODE) & ~MSGINT_MODE_ONE_SHOT_DISABLE;
11251 tw32(MSGINT_MODE, val);
11252 }
7938109f 11253 return 0;
f6eb9b1f 11254 }
7938109f
MC		 11255
11256 return -EIO;
11257}
11258
11259/* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
11260 * successfully restored
11261 */
11262static int tg3_test_msi(struct tg3 *tp)
11263{
7938109f
MC		 11264 int err;
11265 u16 pci_cmd;
11266
63c3a66f 11267 if (!tg3_flag(tp, USING_MSI))
7938109f
MC		 11268 return 0;
11269
11270 /* Turn off SERR reporting in case MSI terminates with Master
11271 * Abort.
11272 */
11273 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
11274 pci_write_config_word(tp->pdev, PCI_COMMAND,
11275 pci_cmd & ~PCI_COMMAND_SERR);
11276
11277 err = tg3_test_interrupt(tp);
11278
11279 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
11280
11281 if (!err)
11282 return 0;
11283
11284 /* other failures */
11285 if (err != -EIO)
11286 return err;
11287
11288 /* MSI test failed, go back to INTx mode */
5129c3a3
MC		 11289 netdev_warn(tp->dev, "No interrupt was generated using MSI. Switching "
11290 "to INTx mode. Please report this failure to the PCI "
11291 "maintainer and include system chipset information\n");
7938109f 11292
4f125f42 11293 free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
09943a18 11294
7938109f
MC		 11295 pci_disable_msi(tp->pdev);
11296
63c3a66f 11297 tg3_flag_clear(tp, USING_MSI);
dc8bf1b1 11298 tp->napi[0].irq_vec = tp->pdev->irq;
7938109f 11299
4f125f42 11300 err = tg3_request_irq(tp, 0);
7938109f
MC		 11301 if (err)
11302 return err;
11303
11304 /* Need to reset the chip because the MSI cycle may have terminated
11305 * with Master Abort.
11306 */
f47c11ee 11307 tg3_full_lock(tp, 1);
7938109f 11308
944d980e 11309 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
953c96e0 11310 err = tg3_init_hw(tp, true);
7938109f 11311
f47c11ee 11312 tg3_full_unlock(tp);
7938109f
MC		 11313
11314 if (err)
4f125f42 11315 free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
7938109f
MC		 11316
11317 return err;
11318}
11319
9e9fd12d
MC		 11320static int tg3_request_firmware(struct tg3 *tp)
11321{
77997ea3 11322 const struct tg3_firmware_hdr *fw_hdr;
9e9fd12d
MC		 11323
11324 if (request_firmware(&tp->fw, tp->fw_needed, &tp->pdev->dev)) {
05dbe005
JP		 11325 netdev_err(tp->dev, "Failed to load firmware \"%s\"\n",
11326 tp->fw_needed);
9e9fd12d
MC		 11327 return -ENOENT;
11328 }
11329
77997ea3 11330 fw_hdr = (struct tg3_firmware_hdr *)tp->fw->data;
9e9fd12d
MC		 11331
11332 /* Firmware blob starts with version numbers, followed by
11333 * start address and _full_ length including BSS sections
11334 * (which must be longer than the actual data, of course
11335 */
11336
77997ea3
NS		 11337 tp->fw_len = be32_to_cpu(fw_hdr->len); /* includes bss */
11338 if (tp->fw_len < (tp->fw->size - TG3_FW_HDR_LEN)) {
05dbe005
JP		 11339 netdev_err(tp->dev, "bogus length %d in \"%s\"\n",
11340 tp->fw_len, tp->fw_needed);
9e9fd12d
MC		 11341 release_firmware(tp->fw);
11342 tp->fw = NULL;
11343 return -EINVAL;
11344 }
11345
11346 /* We no longer need firmware; we have it. */
11347 tp->fw_needed = NULL;
11348 return 0;
11349}
11350
9102426a 11351static u32 tg3_irq_count(struct tg3 *tp)
679563f4 11352{
9102426a 11353 u32 irq_cnt = max(tp->rxq_cnt, tp->txq_cnt);
679563f4 11354
9102426a 11355 if (irq_cnt > 1) {
c3b5003b
MC		 11356 /* We want as many rx rings enabled as there are cpus.
11357 * In multiqueue MSI-X mode, the first MSI-X vector
11358 * only deals with link interrupts, etc, so we add
11359 * one to the number of vectors we are requesting.
11360 */
9102426a 11361 irq_cnt = min_t(unsigned, irq_cnt + 1, tp->irq_max);
c3b5003b 11362 }
679563f4 11363
9102426a
MC		 11364 return irq_cnt;
11365}
11366
11367static bool tg3_enable_msix(struct tg3 *tp)
11368{
11369 int i, rc;
86449944 11370 struct msix_entry msix_ent[TG3_IRQ_MAX_VECS];
9102426a 11371
0968169c
MC		 11372 tp->txq_cnt = tp->txq_req;
11373 tp->rxq_cnt = tp->rxq_req;
11374 if (!tp->rxq_cnt)
11375 tp->rxq_cnt = netif_get_num_default_rss_queues();
9102426a
MC		 11376 if (tp->rxq_cnt > tp->rxq_max)
11377 tp->rxq_cnt = tp->rxq_max;
cf6d6ea6
MC		 11378
11379 /* Disable multiple TX rings by default. Simple round-robin hardware
11380 * scheduling of the TX rings can cause starvation of rings with
11381 * small packets when other rings have TSO or jumbo packets.
11382 */
11383 if (!tp->txq_req)
11384 tp->txq_cnt = 1;
9102426a
MC		 11385
11386 tp->irq_cnt = tg3_irq_count(tp);
11387
679563f4
MC		 11388 for (i = 0; i < tp->irq_max; i++) {
11389 msix_ent[i].entry = i;
11390 msix_ent[i].vector = 0;
11391 }
11392
6f1f411a 11393 rc = pci_enable_msix_range(tp->pdev, msix_ent, 1, tp->irq_cnt);
2430b031
MC		 11394 if (rc < 0) {
11395 return false;
6f1f411a 11396 } else if (rc < tp->irq_cnt) {
05dbe005
JP		 11397 netdev_notice(tp->dev, "Requested %d MSI-X vectors, received %d\n",
11398 tp->irq_cnt, rc);
679563f4 11399 tp->irq_cnt = rc;
49a359e3 11400 tp->rxq_cnt = max(rc - 1, 1);
9102426a
MC		 11401 if (tp->txq_cnt)
11402 tp->txq_cnt = min(tp->rxq_cnt, tp->txq_max);
679563f4
MC		 11403 }
11404
11405 for (i = 0; i < tp->irq_max; i++)
11406 tp->napi[i].irq_vec = msix_ent[i].vector;
11407
49a359e3 11408 if (netif_set_real_num_rx_queues(tp->dev, tp->rxq_cnt)) {
2ddaad39
BH		 11409 pci_disable_msix(tp->pdev);
11410 return false;
11411 }
b92b9040 11412
9102426a
MC		 11413 if (tp->irq_cnt == 1)
11414 return true;
d78b59f5 11415
9102426a
MC		 11416 tg3_flag_set(tp, ENABLE_RSS);
11417
11418 if (tp->txq_cnt > 1)
11419 tg3_flag_set(tp, ENABLE_TSS);
11420
11421 netif_set_real_num_tx_queues(tp->dev, tp->txq_cnt);
2430b031 11422
679563f4
MC		 11423 return true;
11424}
11425
07b0173c
MC		 11426static void tg3_ints_init(struct tg3 *tp)
11427{
63c3a66f
JP		 11428 if ((tg3_flag(tp, SUPPORT_MSI) || tg3_flag(tp, SUPPORT_MSIX)) &&
11429 !tg3_flag(tp, TAGGED_STATUS)) {
07b0173c
MC		 11430 /* All MSI supporting chips should support tagged
11431 * status. Assert that this is the case.
11432 */
5129c3a3
MC		 11433 netdev_warn(tp->dev,
11434 "MSI without TAGGED_STATUS? Not using MSI\n");
679563f4 11435 goto defcfg;
07b0173c 11436 }
4f125f42 11437
63c3a66f
JP		 11438 if (tg3_flag(tp, SUPPORT_MSIX) && tg3_enable_msix(tp))
11439 tg3_flag_set(tp, USING_MSIX);
11440 else if (tg3_flag(tp, SUPPORT_MSI) && pci_enable_msi(tp->pdev) == 0)
11441 tg3_flag_set(tp, USING_MSI);
679563f4 11442
63c3a66f 11443 if (tg3_flag(tp, USING_MSI) || tg3_flag(tp, USING_MSIX)) {
679563f4 11444 u32 msi_mode = tr32(MSGINT_MODE);
63c3a66f 11445 if (tg3_flag(tp, USING_MSIX) && tp->irq_cnt > 1)
baf8a94a 11446 msi_mode |= MSGINT_MODE_MULTIVEC_EN;
5b39de91
MC		 11447 if (!tg3_flag(tp, 1SHOT_MSI))
11448 msi_mode |= MSGINT_MODE_ONE_SHOT_DISABLE;
679563f4
MC		 11449 tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
11450 }
11451defcfg:
63c3a66f 11452 if (!tg3_flag(tp, USING_MSIX)) {
679563f4
MC		 11453 tp->irq_cnt = 1;
11454 tp->napi[0].irq_vec = tp->pdev->irq;
49a359e3
MC		 11455 }
11456
11457 if (tp->irq_cnt == 1) {
11458 tp->txq_cnt = 1;
11459 tp->rxq_cnt = 1;
2ddaad39 11460 netif_set_real_num_tx_queues(tp->dev, 1);
85407885 11461 netif_set_real_num_rx_queues(tp->dev, 1);
679563f4 11462 }
07b0173c
MC		 11463}
11464
11465static void tg3_ints_fini(struct tg3 *tp)
11466{
63c3a66f 11467 if (tg3_flag(tp, USING_MSIX))
679563f4 11468 pci_disable_msix(tp->pdev);
63c3a66f 11469 else if (tg3_flag(tp, USING_MSI))
679563f4 11470 pci_disable_msi(tp->pdev);
63c3a66f
JP		 11471 tg3_flag_clear(tp, USING_MSI);
11472 tg3_flag_clear(tp, USING_MSIX);
11473 tg3_flag_clear(tp, ENABLE_RSS);
11474 tg3_flag_clear(tp, ENABLE_TSS);
07b0173c
MC		 11475}
11476
be947307
MC		 11477static int tg3_start(struct tg3 *tp, bool reset_phy, bool test_irq,
11478 bool init)
1da177e4 11479{
d8f4cd38 11480 struct net_device *dev = tp->dev;
4f125f42 11481 int i, err;
1da177e4 11482
679563f4
MC		 11483 /*
11484 * Setup interrupts first so we know how
11485 * many NAPI resources to allocate
11486 */
11487 tg3_ints_init(tp);
11488
90415477 11489 tg3_rss_check_indir_tbl(tp);
bcebcc46 11490
1da177e4
LT		 11491 /* The placement of this call is tied
11492 * to the setup and use of Host TX descriptors.
11493 */
11494 err = tg3_alloc_consistent(tp);
11495 if (err)
4a5f46f2 11496 goto out_ints_fini;
88b06bc2 11497
66cfd1bd
MC		 11498 tg3_napi_init(tp);
11499
fed97810 11500 tg3_napi_enable(tp);
1da177e4 11501
4f125f42
MC		 11502 for (i = 0; i < tp->irq_cnt; i++) {
11503 struct tg3_napi *tnapi = &tp->napi[i];
11504 err = tg3_request_irq(tp, i);
11505 if (err) {
5bc09186
MC		 11506 for (i--; i >= 0; i--) {
11507 tnapi = &tp->napi[i];
4f125f42 11508 free_irq(tnapi->irq_vec, tnapi);
5bc09186 11509 }
4a5f46f2 11510 goto out_napi_fini;
4f125f42
MC		 11511 }
11512 }
1da177e4 11513
f47c11ee 11514 tg3_full_lock(tp, 0);
1da177e4 11515
2e460fc0
NS		 11516 if (init)
11517 tg3_ape_driver_state_change(tp, RESET_KIND_INIT);
11518
d8f4cd38 11519 err = tg3_init_hw(tp, reset_phy);
1da177e4 11520 if (err) {
944d980e 11521 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4 11522 tg3_free_rings(tp);
1da177e4
LT		 11523 }
11524
f47c11ee 11525 tg3_full_unlock(tp);
1da177e4 11526
07b0173c 11527 if (err)
4a5f46f2 11528 goto out_free_irq;
1da177e4 11529
d8f4cd38 11530 if (test_irq && tg3_flag(tp, USING_MSI)) {
7938109f 11531 err = tg3_test_msi(tp);
fac9b83e 11532
7938109f 11533 if (err) {
f47c11ee 11534 tg3_full_lock(tp, 0);
944d980e 11535 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7938109f 11536 tg3_free_rings(tp);
f47c11ee 11537 tg3_full_unlock(tp);
7938109f 11538
4a5f46f2 11539 goto out_napi_fini;
7938109f 11540 }
fcfa0a32 11541
63c3a66f 11542 if (!tg3_flag(tp, 57765_PLUS) && tg3_flag(tp, USING_MSI)) {
f6eb9b1f 11543 u32 val = tr32(PCIE_TRANSACTION_CFG);
fcfa0a32 11544
f6eb9b1f
MC		 11545 tw32(PCIE_TRANSACTION_CFG,
11546 val | PCIE_TRANS_CFG_1SHOT_MSI);
fcfa0a32 11547 }
7938109f
MC		 11548 }
11549
b02fd9e3
MC		 11550 tg3_phy_start(tp);
11551
aed93e0b
MC		 11552 tg3_hwmon_open(tp);
11553
f47c11ee 11554 tg3_full_lock(tp, 0);
1da177e4 11555
21f7638e 11556 tg3_timer_start(tp);
63c3a66f 11557 tg3_flag_set(tp, INIT_COMPLETE);
1da177e4
LT		 11558 tg3_enable_ints(tp);
11559
be947307
MC		 11560 if (init)
11561 tg3_ptp_init(tp);
11562 else
11563 tg3_ptp_resume(tp);
11564
11565
f47c11ee 11566 tg3_full_unlock(tp);
1da177e4 11567
fe5f5787 11568 netif_tx_start_all_queues(dev);
1da177e4 11569
06c03c02
MB		 11570 /*
11571 * Reset loopback feature if it was turned on while the device was down
11572 * make sure that it's installed properly now.
11573 */
11574 if (dev->features & NETIF_F_LOOPBACK)
11575 tg3_set_loopback(dev, dev->features);
11576
1da177e4 11577 return 0;
07b0173c 11578
4a5f46f2 11579out_free_irq:
4f125f42
MC		 11580 for (i = tp->irq_cnt - 1; i >= 0; i--) {
11581 struct tg3_napi *tnapi = &tp->napi[i];
11582 free_irq(tnapi->irq_vec, tnapi);
11583 }
07b0173c 11584
4a5f46f2 11585out_napi_fini:
fed97810 11586 tg3_napi_disable(tp);
66cfd1bd 11587 tg3_napi_fini(tp);
07b0173c 11588 tg3_free_consistent(tp);
679563f4 11589
4a5f46f2 11590out_ints_fini:
679563f4 11591 tg3_ints_fini(tp);
d8f4cd38 11592
07b0173c 11593 return err;
1da177e4
LT		 11594}
11595
65138594 11596static void tg3_stop(struct tg3 *tp)
1da177e4 11597{
4f125f42 11598 int i;
1da177e4 11599
db219973 11600 tg3_reset_task_cancel(tp);
bd473da3 11601 tg3_netif_stop(tp);
1da177e4 11602
21f7638e 11603 tg3_timer_stop(tp);
1da177e4 11604
aed93e0b
MC		 11605 tg3_hwmon_close(tp);
11606
24bb4fb6
MC		 11607 tg3_phy_stop(tp);
11608
f47c11ee 11609 tg3_full_lock(tp, 1);
1da177e4
LT		 11610
11611 tg3_disable_ints(tp);
11612
944d980e 11613 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4 11614 tg3_free_rings(tp);
63c3a66f 11615 tg3_flag_clear(tp, INIT_COMPLETE);
1da177e4 11616
f47c11ee 11617 tg3_full_unlock(tp);
1da177e4 11618
4f125f42
MC		 11619 for (i = tp->irq_cnt - 1; i >= 0; i--) {
11620 struct tg3_napi *tnapi = &tp->napi[i];
11621 free_irq(tnapi->irq_vec, tnapi);
11622 }
07b0173c
MC		 11623
11624 tg3_ints_fini(tp);
1da177e4 11625
66cfd1bd
MC		 11626 tg3_napi_fini(tp);
11627
1da177e4 11628 tg3_free_consistent(tp);
65138594
MC		 11629}
11630
d8f4cd38
MC		 11631static int tg3_open(struct net_device *dev)
11632{
11633 struct tg3 *tp = netdev_priv(dev);
11634 int err;
11635
0486a063
IV		 11636 if (tp->pcierr_recovery) {
11637 netdev_err(dev, "Failed to open device. PCI error recovery "
11638 "in progress\n");
11639 return -EAGAIN;
11640 }
11641
d8f4cd38
MC		 11642 if (tp->fw_needed) {
11643 err = tg3_request_firmware(tp);
c4dab506
NS		 11644 if (tg3_asic_rev(tp) == ASIC_REV_57766) {
11645 if (err) {
11646 netdev_warn(tp->dev, "EEE capability disabled\n");
11647 tp->phy_flags &= ~TG3_PHYFLG_EEE_CAP;
11648 } else if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP)) {
11649 netdev_warn(tp->dev, "EEE capability restored\n");
11650 tp->phy_flags |= TG3_PHYFLG_EEE_CAP;
11651 }
11652 } else if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0) {
d8f4cd38
MC		 11653 if (err)
11654 return err;
11655 } else if (err) {
11656 netdev_warn(tp->dev, "TSO capability disabled\n");
11657 tg3_flag_clear(tp, TSO_CAPABLE);
11658 } else if (!tg3_flag(tp, TSO_CAPABLE)) {
11659 netdev_notice(tp->dev, "TSO capability restored\n");
11660 tg3_flag_set(tp, TSO_CAPABLE);
11661 }
11662 }
11663
f4a46d1f 11664 tg3_carrier_off(tp);
d8f4cd38
MC		 11665
11666 err = tg3_power_up(tp);
11667 if (err)
11668 return err;
11669
11670 tg3_full_lock(tp, 0);
11671
11672 tg3_disable_ints(tp);
11673 tg3_flag_clear(tp, INIT_COMPLETE);
11674
11675 tg3_full_unlock(tp);
11676
942d1af0
NS		 11677 err = tg3_start(tp,
11678 !(tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN),
11679 true, true);
d8f4cd38
MC		 11680 if (err) {
11681 tg3_frob_aux_power(tp, false);
11682 pci_set_power_state(tp->pdev, PCI_D3hot);
11683 }
be947307 11684
7d41e49a
MC		 11685 if (tg3_flag(tp, PTP_CAPABLE)) {
11686 tp->ptp_clock = ptp_clock_register(&tp->ptp_info,
11687 &tp->pdev->dev);
11688 if (IS_ERR(tp->ptp_clock))
11689 tp->ptp_clock = NULL;
11690 }
11691
07b0173c 11692 return err;
1da177e4
LT		 11693}
11694
1da177e4
LT		 11695static int tg3_close(struct net_device *dev)
11696{
11697 struct tg3 *tp = netdev_priv(dev);
11698
0486a063
IV		 11699 if (tp->pcierr_recovery) {
11700 netdev_err(dev, "Failed to close device. PCI error recovery "
11701 "in progress\n");
11702 return -EAGAIN;
11703 }
11704
be947307
MC		 11705 tg3_ptp_fini(tp);
11706
65138594 11707 tg3_stop(tp);
1da177e4 11708
92feeabf
MC		 11709 /* Clear stats across close / open calls */
11710 memset(&tp->net_stats_prev, 0, sizeof(tp->net_stats_prev));
11711 memset(&tp->estats_prev, 0, sizeof(tp->estats_prev));
1da177e4 11712
8496e85c
RW		 11713 if (pci_device_is_present(tp->pdev)) {
11714 tg3_power_down_prepare(tp);
bc1c7567 11715
8496e85c
RW		 11716 tg3_carrier_off(tp);
11717 }
1da177e4
LT		 11718 return 0;
11719}
11720
511d2224 11721static inline u64 get_stat64(tg3_stat64_t *val)
816f8b86
SB		 11722{
11723 return ((u64)val->high << 32) | ((u64)val->low);
11724}
11725
65ec698d 11726static u64 tg3_calc_crc_errors(struct tg3 *tp)
1da177e4
LT		 11727{
11728 struct tg3_hw_stats *hw_stats = tp->hw_stats;
11729
f07e9af3 11730 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
4153577a
JP		 11731 (tg3_asic_rev(tp) == ASIC_REV_5700 ||
11732 tg3_asic_rev(tp) == ASIC_REV_5701)) {
1da177e4
LT		 11733 u32 val;
11734
569a5df8
MC		 11735 if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) {
11736 tg3_writephy(tp, MII_TG3_TEST1,
11737 val | MII_TG3_TEST1_CRC_EN);
f08aa1a8 11738 tg3_readphy(tp, MII_TG3_RXR_COUNTERS, &val);
1da177e4
LT		 11739 } else
11740 val = 0;
1da177e4
LT		 11741
11742 tp->phy_crc_errors += val;
11743
11744 return tp->phy_crc_errors;
11745 }
11746
11747 return get_stat64(&hw_stats->rx_fcs_errors);
11748}
11749
11750#define ESTAT_ADD(member) \
11751 estats->member = old_estats->member + \
511d2224 11752 get_stat64(&hw_stats->member)
1da177e4 11753
65ec698d 11754static void tg3_get_estats(struct tg3 *tp, struct tg3_ethtool_stats *estats)
1da177e4 11755{
1da177e4
LT		 11756 struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
11757 struct tg3_hw_stats *hw_stats = tp->hw_stats;
11758
1da177e4
LT		 11759 ESTAT_ADD(rx_octets);
11760 ESTAT_ADD(rx_fragments);
11761 ESTAT_ADD(rx_ucast_packets);
11762 ESTAT_ADD(rx_mcast_packets);
11763 ESTAT_ADD(rx_bcast_packets);
11764 ESTAT_ADD(rx_fcs_errors);
11765 ESTAT_ADD(rx_align_errors);
11766 ESTAT_ADD(rx_xon_pause_rcvd);
11767 ESTAT_ADD(rx_xoff_pause_rcvd);
11768 ESTAT_ADD(rx_mac_ctrl_rcvd);
11769 ESTAT_ADD(rx_xoff_entered);
11770 ESTAT_ADD(rx_frame_too_long_errors);
11771 ESTAT_ADD(rx_jabbers);
11772 ESTAT_ADD(rx_undersize_packets);
11773 ESTAT_ADD(rx_in_length_errors);
11774 ESTAT_ADD(rx_out_length_errors);
11775 ESTAT_ADD(rx_64_or_less_octet_packets);
11776 ESTAT_ADD(rx_65_to_127_octet_packets);
11777 ESTAT_ADD(rx_128_to_255_octet_packets);
11778 ESTAT_ADD(rx_256_to_511_octet_packets);
11779 ESTAT_ADD(rx_512_to_1023_octet_packets);
11780 ESTAT_ADD(rx_1024_to_1522_octet_packets);
11781 ESTAT_ADD(rx_1523_to_2047_octet_packets);
11782 ESTAT_ADD(rx_2048_to_4095_octet_packets);
11783 ESTAT_ADD(rx_4096_to_8191_octet_packets);
11784 ESTAT_ADD(rx_8192_to_9022_octet_packets);
11785
11786 ESTAT_ADD(tx_octets);
11787 ESTAT_ADD(tx_collisions);
11788 ESTAT_ADD(tx_xon_sent);
11789 ESTAT_ADD(tx_xoff_sent);
11790 ESTAT_ADD(tx_flow_control);
11791 ESTAT_ADD(tx_mac_errors);
11792 ESTAT_ADD(tx_single_collisions);
11793 ESTAT_ADD(tx_mult_collisions);
11794 ESTAT_ADD(tx_deferred);
11795 ESTAT_ADD(tx_excessive_collisions);
11796 ESTAT_ADD(tx_late_collisions);
11797 ESTAT_ADD(tx_collide_2times);
11798 ESTAT_ADD(tx_collide_3times);
11799 ESTAT_ADD(tx_collide_4times);
11800 ESTAT_ADD(tx_collide_5times);
11801 ESTAT_ADD(tx_collide_6times);
11802 ESTAT_ADD(tx_collide_7times);
11803 ESTAT_ADD(tx_collide_8times);
11804 ESTAT_ADD(tx_collide_9times);
11805 ESTAT_ADD(tx_collide_10times);
11806 ESTAT_ADD(tx_collide_11times);
11807 ESTAT_ADD(tx_collide_12times);
11808 ESTAT_ADD(tx_collide_13times);
11809 ESTAT_ADD(tx_collide_14times);
11810 ESTAT_ADD(tx_collide_15times);
11811 ESTAT_ADD(tx_ucast_packets);
11812 ESTAT_ADD(tx_mcast_packets);
11813 ESTAT_ADD(tx_bcast_packets);
11814 ESTAT_ADD(tx_carrier_sense_errors);
11815 ESTAT_ADD(tx_discards);
11816 ESTAT_ADD(tx_errors);
11817
11818 ESTAT_ADD(dma_writeq_full);
11819 ESTAT_ADD(dma_write_prioq_full);
11820 ESTAT_ADD(rxbds_empty);
11821 ESTAT_ADD(rx_discards);
11822 ESTAT_ADD(rx_errors);
11823 ESTAT_ADD(rx_threshold_hit);
11824
11825 ESTAT_ADD(dma_readq_full);
11826 ESTAT_ADD(dma_read_prioq_full);
11827 ESTAT_ADD(tx_comp_queue_full);
11828
11829 ESTAT_ADD(ring_set_send_prod_index);
11830 ESTAT_ADD(ring_status_update);
11831 ESTAT_ADD(nic_irqs);
11832 ESTAT_ADD(nic_avoided_irqs);
11833 ESTAT_ADD(nic_tx_threshold_hit);
11834
4452d099 11835 ESTAT_ADD(mbuf_lwm_thresh_hit);
1da177e4
LT		 11836}
11837
65ec698d 11838static void tg3_get_nstats(struct tg3 *tp, struct rtnl_link_stats64 *stats)
1da177e4 11839{
511d2224 11840 struct rtnl_link_stats64 *old_stats = &tp->net_stats_prev;
1da177e4
LT		 11841 struct tg3_hw_stats *hw_stats = tp->hw_stats;
11842
1da177e4
LT		 11843 stats->rx_packets = old_stats->rx_packets +
11844 get_stat64(&hw_stats->rx_ucast_packets) +
11845 get_stat64(&hw_stats->rx_mcast_packets) +
11846 get_stat64(&hw_stats->rx_bcast_packets);
6aa20a22 11847
1da177e4
LT		 11848 stats->tx_packets = old_stats->tx_packets +
11849 get_stat64(&hw_stats->tx_ucast_packets) +
11850 get_stat64(&hw_stats->tx_mcast_packets) +
11851 get_stat64(&hw_stats->tx_bcast_packets);
11852
11853 stats->rx_bytes = old_stats->rx_bytes +
11854 get_stat64(&hw_stats->rx_octets);
11855 stats->tx_bytes = old_stats->tx_bytes +
11856 get_stat64(&hw_stats->tx_octets);
11857
11858 stats->rx_errors = old_stats->rx_errors +
4f63b877 11859 get_stat64(&hw_stats->rx_errors);
1da177e4
LT		 11860 stats->tx_errors = old_stats->tx_errors +
11861 get_stat64(&hw_stats->tx_errors) +
11862 get_stat64(&hw_stats->tx_mac_errors) +
11863 get_stat64(&hw_stats->tx_carrier_sense_errors) +
11864 get_stat64(&hw_stats->tx_discards);
11865
11866 stats->multicast = old_stats->multicast +
11867 get_stat64(&hw_stats->rx_mcast_packets);
11868 stats->collisions = old_stats->collisions +
11869 get_stat64(&hw_stats->tx_collisions);
11870
11871 stats->rx_length_errors = old_stats->rx_length_errors +
11872 get_stat64(&hw_stats->rx_frame_too_long_errors) +
11873 get_stat64(&hw_stats->rx_undersize_packets);
11874
1da177e4
LT		 11875 stats->rx_frame_errors = old_stats->rx_frame_errors +
11876 get_stat64(&hw_stats->rx_align_errors);
11877 stats->tx_aborted_errors = old_stats->tx_aborted_errors +
11878 get_stat64(&hw_stats->tx_discards);
11879 stats->tx_carrier_errors = old_stats->tx_carrier_errors +
11880 get_stat64(&hw_stats->tx_carrier_sense_errors);
11881
11882 stats->rx_crc_errors = old_stats->rx_crc_errors +
65ec698d 11883 tg3_calc_crc_errors(tp);
1da177e4 11884
4f63b877
JL		 11885 stats->rx_missed_errors = old_stats->rx_missed_errors +
11886 get_stat64(&hw_stats->rx_discards);
11887
b0057c51 11888 stats->rx_dropped = tp->rx_dropped;
48855432 11889 stats->tx_dropped = tp->tx_dropped;
1da177e4
LT		 11890}
11891
1da177e4
LT		 11892static int tg3_get_regs_len(struct net_device *dev)
11893{
97bd8e49 11894 return TG3_REG_BLK_SIZE;
1da177e4
LT		 11895}
11896
11897static void tg3_get_regs(struct net_device *dev,
11898 struct ethtool_regs *regs, void *_p)
11899{
1da177e4 11900 struct tg3 *tp = netdev_priv(dev);
1da177e4
LT		 11901
11902 regs->version = 0;
11903
97bd8e49 11904 memset(_p, 0, TG3_REG_BLK_SIZE);
1da177e4 11905
80096068 11906 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
bc1c7567
MC		 11907 return;
11908
f47c11ee 11909 tg3_full_lock(tp, 0);
1da177e4 11910
97bd8e49 11911 tg3_dump_legacy_regs(tp, (u32 *)_p);
1da177e4 11912
f47c11ee 11913 tg3_full_unlock(tp);
1da177e4
LT		 11914}
11915
11916static int tg3_get_eeprom_len(struct net_device *dev)
11917{
11918 struct tg3 *tp = netdev_priv(dev);
11919
11920 return tp->nvram_size;
11921}
11922
1da177e4
LT		 11923static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
11924{
11925 struct tg3 *tp = netdev_priv(dev);
506724c4 11926 int ret, cpmu_restore = 0;
1da177e4 11927 u8 *pd;
506724c4 11928 u32 i, offset, len, b_offset, b_count, cpmu_val = 0;
a9dc529d 11929 __be32 val;
1da177e4 11930
63c3a66f 11931 if (tg3_flag(tp, NO_NVRAM))
df259d8c
MC		 11932 return -EINVAL;
11933
1da177e4
LT		 11934 offset = eeprom->offset;
11935 len = eeprom->len;
11936 eeprom->len = 0;
11937
11938 eeprom->magic = TG3_EEPROM_MAGIC;
11939
506724c4
PS		 11940 /* Override clock, link aware and link idle modes */
11941 if (tg3_flag(tp, CPMU_PRESENT)) {
11942 cpmu_val = tr32(TG3_CPMU_CTRL);
11943 if (cpmu_val & (CPMU_CTRL_LINK_AWARE_MODE |
11944 CPMU_CTRL_LINK_IDLE_MODE)) {
11945 tw32(TG3_CPMU_CTRL, cpmu_val &
11946 ~(CPMU_CTRL_LINK_AWARE_MODE |
11947 CPMU_CTRL_LINK_IDLE_MODE));
11948 cpmu_restore = 1;
11949 }
11950 }
11951 tg3_override_clk(tp);
11952
1da177e4
LT		 11953 if (offset & 3) {
11954 /* adjustments to start on required 4 byte boundary */
11955 b_offset = offset & 3;
11956 b_count = 4 - b_offset;
11957 if (b_count > len) {
11958 /* i.e. offset=1 len=2 */
11959 b_count = len;
11960 }
a9dc529d 11961 ret = tg3_nvram_read_be32(tp, offset-b_offset, &val);
1da177e4 11962 if (ret)
506724c4 11963 goto eeprom_done;
be98da6a 11964 memcpy(data, ((char *)&val) + b_offset, b_count);
1da177e4
LT		 11965 len -= b_count;
11966 offset += b_count;
c6cdf436 11967 eeprom->len += b_count;
1da177e4
LT		 11968 }
11969
25985edc 11970 /* read bytes up to the last 4 byte boundary */
1da177e4
LT		 11971 pd = &data[eeprom->len];
11972 for (i = 0; i < (len - (len & 3)); i += 4) {
a9dc529d 11973 ret = tg3_nvram_read_be32(tp, offset + i, &val);
1da177e4 11974 if (ret) {
506724c4
PS		 11975 if (i)
11976 i -= 4;
1da177e4 11977 eeprom->len += i;
506724c4 11978 goto eeprom_done;
1da177e4 11979 }
1da177e4 11980 memcpy(pd + i, &val, 4);
506724c4
PS		 11981 if (need_resched()) {
11982 if (signal_pending(current)) {
11983 eeprom->len += i;
11984 ret = -EINTR;
11985 goto eeprom_done;
11986 }
11987 cond_resched();
11988 }
1da177e4
LT		 11989 }
11990 eeprom->len += i;
11991
11992 if (len & 3) {
11993 /* read last bytes not ending on 4 byte boundary */
11994 pd = &data[eeprom->len];
11995 b_count = len & 3;
11996 b_offset = offset + len - b_count;
a9dc529d 11997 ret = tg3_nvram_read_be32(tp, b_offset, &val);
1da177e4 11998 if (ret)
506724c4 11999 goto eeprom_done;
b9fc7dc5 12000 memcpy(pd, &val, b_count);
1da177e4
LT		 12001 eeprom->len += b_count;
12002 }
506724c4
PS		 12003 ret = 0;
12004
12005eeprom_done:
12006 /* Restore clock, link aware and link idle modes */
12007 tg3_restore_clk(tp);
12008 if (cpmu_restore)
12009 tw32(TG3_CPMU_CTRL, cpmu_val);
12010
12011 return ret;
1da177e4
LT		 12012}
12013
1da177e4
LT		 12014static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
12015{
12016 struct tg3 *tp = netdev_priv(dev);
12017 int ret;
b9fc7dc5 12018 u32 offset, len, b_offset, odd_len;
1da177e4 12019 u8 *buf;
a9dc529d 12020 __be32 start, end;
1da177e4 12021
63c3a66f 12022 if (tg3_flag(tp, NO_NVRAM) ||
df259d8c 12023 eeprom->magic != TG3_EEPROM_MAGIC)
1da177e4
LT		 12024 return -EINVAL;
12025
12026 offset = eeprom->offset;
12027 len = eeprom->len;
12028
12029 if ((b_offset = (offset & 3))) {
12030 /* adjustments to start on required 4 byte boundary */
a9dc529d 12031 ret = tg3_nvram_read_be32(tp, offset-b_offset, &start);
1da177e4
LT		 12032 if (ret)
12033 return ret;
1da177e4
LT		 12034 len += b_offset;
12035 offset &= ~3;
1c8594b4
MC		 12036 if (len < 4)
12037 len = 4;
1da177e4
LT		 12038 }
12039
12040 odd_len = 0;
1c8594b4 12041 if (len & 3) {
1da177e4
LT		 12042 /* adjustments to end on required 4 byte boundary */
12043 odd_len = 1;
12044 len = (len + 3) & ~3;
a9dc529d 12045 ret = tg3_nvram_read_be32(tp, offset+len-4, &end);
1da177e4
LT		 12046 if (ret)
12047 return ret;
1da177e4
LT		 12048 }
12049
12050 buf = data;
12051 if (b_offset || odd_len) {
12052 buf = kmalloc(len, GFP_KERNEL);
ab0049b4 12053 if (!buf)
1da177e4
LT		 12054 return -ENOMEM;
12055 if (b_offset)
12056 memcpy(buf, &start, 4);
12057 if (odd_len)
12058 memcpy(buf+len-4, &end, 4);
12059 memcpy(buf + b_offset, data, eeprom->len);
12060 }
12061
12062 ret = tg3_nvram_write_block(tp, offset, len, buf);
12063
12064 if (buf != data)
12065 kfree(buf);
12066
12067 return ret;
12068}
12069
12070static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
12071{
b02fd9e3
MC		 12072 struct tg3 *tp = netdev_priv(dev);
12073
63c3a66f 12074 if (tg3_flag(tp, USE_PHYLIB)) {
3f0e3ad7 12075 struct phy_device *phydev;
f07e9af3 12076 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
b02fd9e3 12077 return -EAGAIN;
ead2402c 12078 phydev = tp->mdio_bus->phy_map[tp->phy_addr];
3f0e3ad7 12079 return phy_ethtool_gset(phydev, cmd);
b02fd9e3 12080 }
6aa20a22 12081
1da177e4
LT		 12082 cmd->supported = (SUPPORTED_Autoneg);
12083
f07e9af3 12084 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
1da177e4
LT		 12085 cmd->supported |= (SUPPORTED_1000baseT_Half |
12086 SUPPORTED_1000baseT_Full);
12087
f07e9af3 12088 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
1da177e4
LT		 12089 cmd->supported |= (SUPPORTED_100baseT_Half |
12090 SUPPORTED_100baseT_Full |
12091 SUPPORTED_10baseT_Half |
12092 SUPPORTED_10baseT_Full |
3bebab59 12093 SUPPORTED_TP);
ef348144
KK		 12094 cmd->port = PORT_TP;
12095 } else {
1da177e4 12096 cmd->supported |= SUPPORTED_FIBRE;
ef348144
KK		 12097 cmd->port = PORT_FIBRE;
12098 }
6aa20a22 12099
1da177e4 12100 cmd->advertising = tp->link_config.advertising;
5bb09778
MC		 12101 if (tg3_flag(tp, PAUSE_AUTONEG)) {
12102 if (tp->link_config.flowctrl & FLOW_CTRL_RX) {
12103 if (tp->link_config.flowctrl & FLOW_CTRL_TX) {
12104 cmd->advertising |= ADVERTISED_Pause;
12105 } else {
12106 cmd->advertising |= ADVERTISED_Pause |
12107 ADVERTISED_Asym_Pause;
12108 }
12109 } else if (tp->link_config.flowctrl & FLOW_CTRL_TX) {
12110 cmd->advertising |= ADVERTISED_Asym_Pause;
12111 }
12112 }
f4a46d1f 12113 if (netif_running(dev) && tp->link_up) {
70739497 12114 ethtool_cmd_speed_set(cmd, tp->link_config.active_speed);
1da177e4 12115 cmd->duplex = tp->link_config.active_duplex;
859edb26 12116 cmd->lp_advertising = tp->link_config.rmt_adv;
e348c5e7
MC		 12117 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
12118 if (tp->phy_flags & TG3_PHYFLG_MDIX_STATE)
12119 cmd->eth_tp_mdix = ETH_TP_MDI_X;
12120 else
12121 cmd->eth_tp_mdix = ETH_TP_MDI;
12122 }
64c22182 12123 } else {
e740522e
MC		 12124 ethtool_cmd_speed_set(cmd, SPEED_UNKNOWN);
12125 cmd->duplex = DUPLEX_UNKNOWN;
e348c5e7 12126 cmd->eth_tp_mdix = ETH_TP_MDI_INVALID;
1da177e4 12127 }
882e9793 12128 cmd->phy_address = tp->phy_addr;
7e5856bd 12129 cmd->transceiver = XCVR_INTERNAL;
1da177e4
LT		 12130 cmd->autoneg = tp->link_config.autoneg;
12131 cmd->maxtxpkt = 0;
12132 cmd->maxrxpkt = 0;
12133 return 0;
12134}
6aa20a22 12135
1da177e4
LT		 12136static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
12137{
12138 struct tg3 *tp = netdev_priv(dev);
25db0338 12139 u32 speed = ethtool_cmd_speed(cmd);
6aa20a22 12140
63c3a66f 12141 if (tg3_flag(tp, USE_PHYLIB)) {
3f0e3ad7 12142 struct phy_device *phydev;
f07e9af3 12143 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
b02fd9e3 12144 return -EAGAIN;
ead2402c 12145 phydev = tp->mdio_bus->phy_map[tp->phy_addr];
3f0e3ad7 12146 return phy_ethtool_sset(phydev, cmd);
b02fd9e3
MC		 12147 }
12148
7e5856bd
MC		 12149 if (cmd->autoneg != AUTONEG_ENABLE &&
12150 cmd->autoneg != AUTONEG_DISABLE)
37ff238d 12151 return -EINVAL;
7e5856bd
MC		 12152
12153 if (cmd->autoneg == AUTONEG_DISABLE &&
12154 cmd->duplex != DUPLEX_FULL &&
12155 cmd->duplex != DUPLEX_HALF)
37ff238d 12156 return -EINVAL;
1da177e4 12157
7e5856bd
MC		 12158 if (cmd->autoneg == AUTONEG_ENABLE) {
12159 u32 mask = ADVERTISED_Autoneg |
12160 ADVERTISED_Pause |
12161 ADVERTISED_Asym_Pause;
12162
f07e9af3 12163 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
7e5856bd
MC		 12164 mask |= ADVERTISED_1000baseT_Half |
12165 ADVERTISED_1000baseT_Full;
12166
f07e9af3 12167 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
7e5856bd
MC		 12168 mask |= ADVERTISED_100baseT_Half |
12169 ADVERTISED_100baseT_Full |
12170 ADVERTISED_10baseT_Half |
12171 ADVERTISED_10baseT_Full |
12172 ADVERTISED_TP;
12173 else
12174 mask |= ADVERTISED_FIBRE;
12175
12176 if (cmd->advertising & ~mask)
12177 return -EINVAL;
12178
12179 mask &= (ADVERTISED_1000baseT_Half |
12180 ADVERTISED_1000baseT_Full |
12181 ADVERTISED_100baseT_Half |
12182 ADVERTISED_100baseT_Full |
12183 ADVERTISED_10baseT_Half |
12184 ADVERTISED_10baseT_Full);
12185
12186 cmd->advertising &= mask;
12187 } else {
f07e9af3 12188 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES) {
25db0338 12189 if (speed != SPEED_1000)
7e5856bd
MC		 12190 return -EINVAL;
12191
12192 if (cmd->duplex != DUPLEX_FULL)
12193 return -EINVAL;
12194 } else {
25db0338
DD		 12195 if (speed != SPEED_100 &&
12196 speed != SPEED_10)
7e5856bd
MC		 12197 return -EINVAL;
12198 }
12199 }
12200
f47c11ee 12201 tg3_full_lock(tp, 0);
1da177e4
LT		 12202
12203 tp->link_config.autoneg = cmd->autoneg;
12204 if (cmd->autoneg == AUTONEG_ENABLE) {
405d8e5c
AG		 12205 tp->link_config.advertising = (cmd->advertising |
12206 ADVERTISED_Autoneg);
e740522e
MC		 12207 tp->link_config.speed = SPEED_UNKNOWN;
12208 tp->link_config.duplex = DUPLEX_UNKNOWN;
1da177e4
LT		 12209 } else {
12210 tp->link_config.advertising = 0;
25db0338 12211 tp->link_config.speed = speed;
1da177e4 12212 tp->link_config.duplex = cmd->duplex;
b02fd9e3 12213 }
6aa20a22 12214
fdad8de4
NS		 12215 tp->phy_flags |= TG3_PHYFLG_USER_CONFIGURED;
12216
ce20f161
NS		 12217 tg3_warn_mgmt_link_flap(tp);
12218
1da177e4 12219 if (netif_running(dev))
953c96e0 12220 tg3_setup_phy(tp, true);
1da177e4 12221
f47c11ee 12222 tg3_full_unlock(tp);
6aa20a22 12223
1da177e4
LT		 12224 return 0;
12225}
6aa20a22 12226
1da177e4
LT		 12227static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
12228{
12229 struct tg3 *tp = netdev_priv(dev);
6aa20a22 12230
68aad78c
RJ		 12231 strlcpy(info->driver, DRV_MODULE_NAME, sizeof(info->driver));
12232 strlcpy(info->version, DRV_MODULE_VERSION, sizeof(info->version));
12233 strlcpy(info->fw_version, tp->fw_ver, sizeof(info->fw_version));
12234 strlcpy(info->bus_info, pci_name(tp->pdev), sizeof(info->bus_info));
1da177e4 12235}
6aa20a22 12236
1da177e4
LT		 12237static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
12238{
12239 struct tg3 *tp = netdev_priv(dev);
6aa20a22 12240
63c3a66f 12241 if (tg3_flag(tp, WOL_CAP) && device_can_wakeup(&tp->pdev->dev))
a85feb8c
GZ		 12242 wol->supported = WAKE_MAGIC;
12243 else
12244 wol->supported = 0;
1da177e4 12245 wol->wolopts = 0;
63c3a66f 12246 if (tg3_flag(tp, WOL_ENABLE) && device_can_wakeup(&tp->pdev->dev))
1da177e4
LT		 12247 wol->wolopts = WAKE_MAGIC;
12248 memset(&wol->sopass, 0, sizeof(wol->sopass));
12249}
6aa20a22 12250
1da177e4
LT		 12251static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
12252{
12253 struct tg3 *tp = netdev_priv(dev);
12dac075 12254 struct device *dp = &tp->pdev->dev;
6aa20a22 12255
1da177e4
LT		 12256 if (wol->wolopts & ~WAKE_MAGIC)
12257 return -EINVAL;
12258 if ((wol->wolopts & WAKE_MAGIC) &&
63c3a66f 12259 !(tg3_flag(tp, WOL_CAP) && device_can_wakeup(dp)))
1da177e4 12260 return -EINVAL;
6aa20a22 12261
f2dc0d18
RW		 12262 device_set_wakeup_enable(dp, wol->wolopts & WAKE_MAGIC);
12263
f2dc0d18 12264 if (device_may_wakeup(dp))
63c3a66f 12265 tg3_flag_set(tp, WOL_ENABLE);
f2dc0d18 12266 else
63c3a66f 12267 tg3_flag_clear(tp, WOL_ENABLE);
6aa20a22 12268
1da177e4
LT		 12269 return 0;
12270}
6aa20a22 12271
1da177e4
LT		 12272static u32 tg3_get_msglevel(struct net_device *dev)
12273{
12274 struct tg3 *tp = netdev_priv(dev);
12275 return tp->msg_enable;
12276}
6aa20a22 12277
1da177e4
LT		 12278static void tg3_set_msglevel(struct net_device *dev, u32 value)
12279{
12280 struct tg3 *tp = netdev_priv(dev);
12281 tp->msg_enable = value;
12282}
6aa20a22 12283
1da177e4
LT		 12284static int tg3_nway_reset(struct net_device *dev)
12285{
12286 struct tg3 *tp = netdev_priv(dev);
1da177e4 12287 int r;
6aa20a22 12288
1da177e4
LT		 12289 if (!netif_running(dev))
12290 return -EAGAIN;
12291
f07e9af3 12292 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
c94e3941
MC		 12293 return -EINVAL;
12294
ce20f161
NS		 12295 tg3_warn_mgmt_link_flap(tp);
12296
63c3a66f 12297 if (tg3_flag(tp, USE_PHYLIB)) {
f07e9af3 12298 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
b02fd9e3 12299 return -EAGAIN;
ead2402c 12300 r = phy_start_aneg(tp->mdio_bus->phy_map[tp->phy_addr]);
b02fd9e3
MC		 12301 } else {
12302 u32 bmcr;
12303
12304 spin_lock_bh(&tp->lock);
12305 r = -EINVAL;
12306 tg3_readphy(tp, MII_BMCR, &bmcr);
12307 if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
12308 ((bmcr & BMCR_ANENABLE) ||
f07e9af3 12309 (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT))) {
b02fd9e3
MC		 12310 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
12311 BMCR_ANENABLE);
12312 r = 0;
12313 }
12314 spin_unlock_bh(&tp->lock);
1da177e4 12315 }
6aa20a22 12316
1da177e4
LT		 12317 return r;
12318}
6aa20a22 12319
1da177e4
LT		 12320static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
12321{
12322 struct tg3 *tp = netdev_priv(dev);
6aa20a22 12323
2c49a44d 12324 ering->rx_max_pending = tp->rx_std_ring_mask;
63c3a66f 12325 if (tg3_flag(tp, JUMBO_RING_ENABLE))
2c49a44d 12326 ering->rx_jumbo_max_pending = tp->rx_jmb_ring_mask;
4f81c32b
MC		 12327 else
12328 ering->rx_jumbo_max_pending = 0;
12329
12330 ering->tx_max_pending = TG3_TX_RING_SIZE - 1;
1da177e4
LT		 12331
12332 ering->rx_pending = tp->rx_pending;
63c3a66f 12333 if (tg3_flag(tp, JUMBO_RING_ENABLE))
4f81c32b
MC		 12334 ering->rx_jumbo_pending = tp->rx_jumbo_pending;
12335 else
12336 ering->rx_jumbo_pending = 0;
12337
f3f3f27e 12338 ering->tx_pending = tp->napi[0].tx_pending;
1da177e4 12339}
6aa20a22 12340
1da177e4
LT		 12341static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
12342{
12343 struct tg3 *tp = netdev_priv(dev);
646c9edd 12344 int i, irq_sync = 0, err = 0;
6aa20a22 12345
2c49a44d
MC		 12346 if ((ering->rx_pending > tp->rx_std_ring_mask) ||
12347 (ering->rx_jumbo_pending > tp->rx_jmb_ring_mask) ||
bc3a9254
MC		 12348 (ering->tx_pending > TG3_TX_RING_SIZE - 1) ||
12349 (ering->tx_pending <= MAX_SKB_FRAGS) ||
63c3a66f 12350 (tg3_flag(tp, TSO_BUG) &&
bc3a9254 12351 (ering->tx_pending <= (MAX_SKB_FRAGS * 3))))
1da177e4 12352 return -EINVAL;
6aa20a22 12353
bbe832c0 12354 if (netif_running(dev)) {
b02fd9e3 12355 tg3_phy_stop(tp);
1da177e4 12356 tg3_netif_stop(tp);
bbe832c0
MC		 12357 irq_sync = 1;
12358 }
1da177e4 12359
bbe832c0 12360 tg3_full_lock(tp, irq_sync);
6aa20a22 12361
1da177e4
LT		 12362 tp->rx_pending = ering->rx_pending;
12363
63c3a66f 12364 if (tg3_flag(tp, MAX_RXPEND_64) &&
1da177e4
LT		 12365 tp->rx_pending > 63)
12366 tp->rx_pending = 63;
ba67b510
IV		 12367
12368 if (tg3_flag(tp, JUMBO_RING_ENABLE))
12369 tp->rx_jumbo_pending = ering->rx_jumbo_pending;
646c9edd 12370
6fd45cb8 12371 for (i = 0; i < tp->irq_max; i++)
646c9edd 12372 tp->napi[i].tx_pending = ering->tx_pending;
1da177e4
LT		 12373
12374 if (netif_running(dev)) {
944d980e 12375 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
953c96e0 12376 err = tg3_restart_hw(tp, false);
b9ec6c1b
MC		 12377 if (!err)
12378 tg3_netif_start(tp);
1da177e4
LT		 12379 }
12380
f47c11ee 12381 tg3_full_unlock(tp);
6aa20a22 12382
b02fd9e3
MC		 12383 if (irq_sync && !err)
12384 tg3_phy_start(tp);
12385
b9ec6c1b 12386 return err;
1da177e4 12387}
6aa20a22 12388
1da177e4
LT		 12389static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
12390{
12391 struct tg3 *tp = netdev_priv(dev);
6aa20a22 12392
63c3a66f 12393 epause->autoneg = !!tg3_flag(tp, PAUSE_AUTONEG);
8d018621 12394
4a2db503 12395 if (tp->link_config.flowctrl & FLOW_CTRL_RX)
8d018621
MC		 12396 epause->rx_pause = 1;
12397 else
12398 epause->rx_pause = 0;
12399
4a2db503 12400 if (tp->link_config.flowctrl & FLOW_CTRL_TX)
8d018621
MC		 12401 epause->tx_pause = 1;
12402 else
12403 epause->tx_pause = 0;
1da177e4 12404}
6aa20a22 12405
1da177e4
LT		 12406static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
12407{
12408 struct tg3 *tp = netdev_priv(dev);
b02fd9e3 12409 int err = 0;
6aa20a22 12410
ce20f161
NS		 12411 if (tp->link_config.autoneg == AUTONEG_ENABLE)
12412 tg3_warn_mgmt_link_flap(tp);
12413
63c3a66f 12414 if (tg3_flag(tp, USE_PHYLIB)) {
2712168f
MC		 12415 u32 newadv;
12416 struct phy_device *phydev;
1da177e4 12417
ead2402c 12418 phydev = tp->mdio_bus->phy_map[tp->phy_addr];
f47c11ee 12419
2712168f
MC		 12420 if (!(phydev->supported & SUPPORTED_Pause) ||
12421 (!(phydev->supported & SUPPORTED_Asym_Pause) &&
2259dca3 12422 (epause->rx_pause != epause->tx_pause)))
2712168f 12423 return -EINVAL;
1da177e4 12424
2712168f
MC		 12425 tp->link_config.flowctrl = 0;
12426 if (epause->rx_pause) {
12427 tp->link_config.flowctrl |= FLOW_CTRL_RX;
12428
12429 if (epause->tx_pause) {
12430 tp->link_config.flowctrl |= FLOW_CTRL_TX;
12431 newadv = ADVERTISED_Pause;
b02fd9e3 12432 } else
2712168f
MC		 12433 newadv = ADVERTISED_Pause |
12434 ADVERTISED_Asym_Pause;
12435 } else if (epause->tx_pause) {
12436 tp->link_config.flowctrl |= FLOW_CTRL_TX;
12437 newadv = ADVERTISED_Asym_Pause;
12438 } else
12439 newadv = 0;
12440
12441 if (epause->autoneg)
63c3a66f 12442 tg3_flag_set(tp, PAUSE_AUTONEG);
2712168f 12443 else
63c3a66f 12444 tg3_flag_clear(tp, PAUSE_AUTONEG);
2712168f 12445
f07e9af3 12446 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
2712168f
MC		 12447 u32 oldadv = phydev->advertising &
12448 (ADVERTISED_Pause | ADVERTISED_Asym_Pause);
12449 if (oldadv != newadv) {
12450 phydev->advertising &=
12451 ~(ADVERTISED_Pause |
12452 ADVERTISED_Asym_Pause);
12453 phydev->advertising |= newadv;
12454 if (phydev->autoneg) {
12455 /*
12456 * Always renegotiate the link to
12457 * inform our link partner of our
12458 * flow control settings, even if the
12459 * flow control is forced. Let
12460 * tg3_adjust_link() do the final
12461 * flow control setup.
12462 */
12463 return phy_start_aneg(phydev);
b02fd9e3 12464 }
b02fd9e3 12465 }
b02fd9e3 12466
2712168f 12467 if (!epause->autoneg)
b02fd9e3 12468 tg3_setup_flow_control(tp, 0, 0);
2712168f 12469 } else {
c6700ce2 12470 tp->link_config.advertising &=
2712168f
MC		 12471 ~(ADVERTISED_Pause |
12472 ADVERTISED_Asym_Pause);
c6700ce2 12473 tp->link_config.advertising |= newadv;
b02fd9e3
MC		 12474 }
12475 } else {
12476 int irq_sync = 0;
12477
12478 if (netif_running(dev)) {
12479 tg3_netif_stop(tp);
12480 irq_sync = 1;
12481 }
12482
12483 tg3_full_lock(tp, irq_sync);
12484
12485 if (epause->autoneg)
63c3a66f 12486 tg3_flag_set(tp, PAUSE_AUTONEG);
b02fd9e3 12487 else
63c3a66f 12488 tg3_flag_clear(tp, PAUSE_AUTONEG);
b02fd9e3 12489 if (epause->rx_pause)
e18ce346 12490 tp->link_config.flowctrl |= FLOW_CTRL_RX;
b02fd9e3 12491 else
e18ce346 12492 tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
b02fd9e3 12493 if (epause->tx_pause)
e18ce346 12494 tp->link_config.flowctrl |= FLOW_CTRL_TX;
b02fd9e3 12495 else
e18ce346 12496 tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
b02fd9e3
MC		 12497
12498 if (netif_running(dev)) {
12499 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
953c96e0 12500 err = tg3_restart_hw(tp, false);
b02fd9e3
MC		 12501 if (!err)
12502 tg3_netif_start(tp);
12503 }
12504
12505 tg3_full_unlock(tp);
12506 }
6aa20a22 12507
fdad8de4
NS		 12508 tp->phy_flags |= TG3_PHYFLG_USER_CONFIGURED;
12509
b9ec6c1b 12510 return err;
1da177e4 12511}
6aa20a22 12512
de6f31eb 12513static int tg3_get_sset_count(struct net_device *dev, int sset)
1da177e4 12514{
b9f2c044
JG		 12515 switch (sset) {
12516 case ETH_SS_TEST:
12517 return TG3_NUM_TEST;
12518 case ETH_SS_STATS:
12519 return TG3_NUM_STATS;
12520 default:
12521 return -EOPNOTSUPP;
12522 }
4cafd3f5
MC		 12523}
12524
90415477
MC		 12525static int tg3_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *info,
12526 u32 *rules __always_unused)
12527{
12528 struct tg3 *tp = netdev_priv(dev);
12529
12530 if (!tg3_flag(tp, SUPPORT_MSIX))
12531 return -EOPNOTSUPP;
12532
12533 switch (info->cmd) {
12534 case ETHTOOL_GRXRINGS:
12535 if (netif_running(tp->dev))
9102426a 12536 info->data = tp->rxq_cnt;
90415477
MC		 12537 else {
12538 info->data = num_online_cpus();
9102426a
MC		 12539 if (info->data > TG3_RSS_MAX_NUM_QS)
12540 info->data = TG3_RSS_MAX_NUM_QS;
90415477
MC		 12541 }
12542
12543 /* The first interrupt vector only
12544 * handles link interrupts.
12545 */
12546 info->data -= 1;
12547 return 0;
12548
12549 default:
12550 return -EOPNOTSUPP;
12551 }
12552}
12553
12554static u32 tg3_get_rxfh_indir_size(struct net_device *dev)
12555{
12556 u32 size = 0;
12557 struct tg3 *tp = netdev_priv(dev);
12558
12559 if (tg3_flag(tp, SUPPORT_MSIX))
12560 size = TG3_RSS_INDIR_TBL_SIZE;
12561
12562 return size;
12563}
12564
fe62d001 12565static int tg3_get_rxfh(struct net_device *dev, u32 *indir, u8 *key)
90415477
MC		 12566{
12567 struct tg3 *tp = netdev_priv(dev);
12568 int i;
12569
12570 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++)
12571 indir[i] = tp->rss_ind_tbl[i];
12572
12573 return 0;
12574}
12575
fe62d001 12576static int tg3_set_rxfh(struct net_device *dev, const u32 *indir, const u8 *key)
90415477
MC		 12577{
12578 struct tg3 *tp = netdev_priv(dev);
12579 size_t i;
12580
12581 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++)
12582 tp->rss_ind_tbl[i] = indir[i];
12583
12584 if (!netif_running(dev) || !tg3_flag(tp, ENABLE_RSS))
12585 return 0;
12586
12587 /* It is legal to write the indirection
12588 * table while the device is running.
12589 */
12590 tg3_full_lock(tp, 0);
12591 tg3_rss_write_indir_tbl(tp);
12592 tg3_full_unlock(tp);
12593
12594 return 0;
12595}
12596
0968169c
MC		 12597static void tg3_get_channels(struct net_device *dev,
12598 struct ethtool_channels *channel)
12599{
12600 struct tg3 *tp = netdev_priv(dev);
12601 u32 deflt_qs = netif_get_num_default_rss_queues();
12602
12603 channel->max_rx = tp->rxq_max;
12604 channel->max_tx = tp->txq_max;
12605
12606 if (netif_running(dev)) {
12607 channel->rx_count = tp->rxq_cnt;
12608 channel->tx_count = tp->txq_cnt;
12609 } else {
12610 if (tp->rxq_req)
12611 channel->rx_count = tp->rxq_req;
12612 else
12613 channel->rx_count = min(deflt_qs, tp->rxq_max);
12614
12615 if (tp->txq_req)
12616 channel->tx_count = tp->txq_req;
12617 else
12618 channel->tx_count = min(deflt_qs, tp->txq_max);
12619 }
12620}
12621
12622static int tg3_set_channels(struct net_device *dev,
12623 struct ethtool_channels *channel)
12624{
12625 struct tg3 *tp = netdev_priv(dev);
12626
12627 if (!tg3_flag(tp, SUPPORT_MSIX))
12628 return -EOPNOTSUPP;
12629
12630 if (channel->rx_count > tp->rxq_max ||
12631 channel->tx_count > tp->txq_max)
12632 return -EINVAL;
12633
12634 tp->rxq_req = channel->rx_count;
12635 tp->txq_req = channel->tx_count;
12636
12637 if (!netif_running(dev))
12638 return 0;
12639
12640 tg3_stop(tp);
12641
f4a46d1f 12642 tg3_carrier_off(tp);
0968169c 12643
be947307 12644 tg3_start(tp, true, false, false);
0968169c
MC		 12645
12646 return 0;
12647}
12648
de6f31eb 12649static void tg3_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
1da177e4
LT		 12650{
12651 switch (stringset) {
12652 case ETH_SS_STATS:
12653 memcpy(buf, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
12654 break;
4cafd3f5
MC		 12655 case ETH_SS_TEST:
12656 memcpy(buf, &ethtool_test_keys, sizeof(ethtool_test_keys));
12657 break;
1da177e4
LT		 12658 default:
12659 WARN_ON(1); /* we need a WARN() */
12660 break;
12661 }
12662}
12663
81b8709c 12664static int tg3_set_phys_id(struct net_device *dev,
12665 enum ethtool_phys_id_state state)
4009a93d
MC		 12666{
12667 struct tg3 *tp = netdev_priv(dev);
4009a93d
MC		 12668
12669 if (!netif_running(tp->dev))
12670 return -EAGAIN;
12671
81b8709c 12672 switch (state) {
12673 case ETHTOOL_ID_ACTIVE:
fce55922 12674 return 1; /* cycle on/off once per second */
4009a93d 12675
81b8709c 12676 case ETHTOOL_ID_ON:
12677 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
12678 LED_CTRL_1000MBPS_ON |
12679 LED_CTRL_100MBPS_ON |
12680 LED_CTRL_10MBPS_ON |
12681 LED_CTRL_TRAFFIC_OVERRIDE |
12682 LED_CTRL_TRAFFIC_BLINK |
12683 LED_CTRL_TRAFFIC_LED);
12684 break;
6aa20a22 12685
81b8709c 12686 case ETHTOOL_ID_OFF:
12687 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
12688 LED_CTRL_TRAFFIC_OVERRIDE);
12689 break;
4009a93d 12690
81b8709c 12691 case ETHTOOL_ID_INACTIVE:
12692 tw32(MAC_LED_CTRL, tp->led_ctrl);
12693 break;
4009a93d 12694 }
81b8709c 12695
4009a93d
MC		 12696 return 0;
12697}
12698
de6f31eb 12699static void tg3_get_ethtool_stats(struct net_device *dev,
1da177e4
LT		 12700 struct ethtool_stats *estats, u64 *tmp_stats)
12701{
12702 struct tg3 *tp = netdev_priv(dev);
0e6c9da3 12703
b546e46f
MC		 12704 if (tp->hw_stats)
12705 tg3_get_estats(tp, (struct tg3_ethtool_stats *)tmp_stats);
12706 else
12707 memset(tmp_stats, 0, sizeof(struct tg3_ethtool_stats));
1da177e4
LT		 12708}
12709
535a490e 12710static __be32 *tg3_vpd_readblock(struct tg3 *tp, u32 *vpdlen)
c3e94500
MC		 12711{
12712 int i;
12713 __be32 *buf;
12714 u32 offset = 0, len = 0;
12715 u32 magic, val;
12716
63c3a66f 12717 if (tg3_flag(tp, NO_NVRAM) || tg3_nvram_read(tp, 0, &magic))
c3e94500
MC		 12718 return NULL;
12719
12720 if (magic == TG3_EEPROM_MAGIC) {
12721 for (offset = TG3_NVM_DIR_START;
12722 offset < TG3_NVM_DIR_END;
12723 offset += TG3_NVM_DIRENT_SIZE) {
12724 if (tg3_nvram_read(tp, offset, &val))
12725 return NULL;
12726
12727 if ((val >> TG3_NVM_DIRTYPE_SHIFT) ==
12728 TG3_NVM_DIRTYPE_EXTVPD)
12729 break;
12730 }
12731
12732 if (offset != TG3_NVM_DIR_END) {
12733 len = (val & TG3_NVM_DIRTYPE_LENMSK) * 4;
12734 if (tg3_nvram_read(tp, offset + 4, &offset))
12735 return NULL;
12736
12737 offset = tg3_nvram_logical_addr(tp, offset);
12738 }
12739 }
12740
12741 if (!offset || !len) {
12742 offset = TG3_NVM_VPD_OFF;
12743 len = TG3_NVM_VPD_LEN;
12744 }
12745
12746 buf = kmalloc(len, GFP_KERNEL);
12747 if (buf == NULL)
12748 return NULL;
12749
12750 if (magic == TG3_EEPROM_MAGIC) {
12751 for (i = 0; i < len; i += 4) {
12752 /* The data is in little-endian format in NVRAM.
12753 * Use the big-endian read routines to preserve
12754 * the byte order as it exists in NVRAM.
12755 */
12756 if (tg3_nvram_read_be32(tp, offset + i, &buf[i/4]))
12757 goto error;
12758 }
12759 } else {
12760 u8 *ptr;
12761 ssize_t cnt;
12762 unsigned int pos = 0;
12763
12764 ptr = (u8 *)&buf[0];
12765 for (i = 0; pos < len && i < 3; i++, pos += cnt, ptr += cnt) {
12766 cnt = pci_read_vpd(tp->pdev, pos,
12767 len - pos, ptr);
12768 if (cnt == -ETIMEDOUT || cnt == -EINTR)
12769 cnt = 0;
12770 else if (cnt < 0)
12771 goto error;
12772 }
12773 if (pos != len)
12774 goto error;
12775 }
12776
535a490e
MC		 12777 *vpdlen = len;
12778
c3e94500
MC		 12779 return buf;
12780
12781error:
12782 kfree(buf);
12783 return NULL;
12784}
12785
566f86ad 12786#define NVRAM_TEST_SIZE 0x100
a5767dec
MC		 12787#define NVRAM_SELFBOOT_FORMAT1_0_SIZE 0x14
12788#define NVRAM_SELFBOOT_FORMAT1_2_SIZE 0x18
12789#define NVRAM_SELFBOOT_FORMAT1_3_SIZE 0x1c
727a6d9f
MC		 12790#define NVRAM_SELFBOOT_FORMAT1_4_SIZE 0x20
12791#define NVRAM_SELFBOOT_FORMAT1_5_SIZE 0x24
bda18faf 12792#define NVRAM_SELFBOOT_FORMAT1_6_SIZE 0x50
b16250e3
MC		 12793#define NVRAM_SELFBOOT_HW_SIZE 0x20
12794#define NVRAM_SELFBOOT_DATA_SIZE 0x1c
566f86ad
MC		 12795
12796static int tg3_test_nvram(struct tg3 *tp)
12797{
535a490e 12798 u32 csum, magic, len;
a9dc529d 12799 __be32 *buf;
ab0049b4 12800 int i, j, k, err = 0, size;
566f86ad 12801
63c3a66f 12802 if (tg3_flag(tp, NO_NVRAM))
df259d8c
MC		 12803 return 0;
12804
e4f34110 12805 if (tg3_nvram_read(tp, 0, &magic) != 0)
1b27777a
MC		 12806 return -EIO;
12807
1b27777a
MC		 12808 if (magic == TG3_EEPROM_MAGIC)
12809 size = NVRAM_TEST_SIZE;
b16250e3 12810 else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) {
a5767dec
MC		 12811 if ((magic & TG3_EEPROM_SB_FORMAT_MASK) ==
12812 TG3_EEPROM_SB_FORMAT_1) {
12813 switch (magic & TG3_EEPROM_SB_REVISION_MASK) {
12814 case TG3_EEPROM_SB_REVISION_0:
12815 size = NVRAM_SELFBOOT_FORMAT1_0_SIZE;
12816 break;
12817 case TG3_EEPROM_SB_REVISION_2:
12818 size = NVRAM_SELFBOOT_FORMAT1_2_SIZE;
12819 break;
12820 case TG3_EEPROM_SB_REVISION_3:
12821 size = NVRAM_SELFBOOT_FORMAT1_3_SIZE;
12822 break;
727a6d9f
MC		 12823 case TG3_EEPROM_SB_REVISION_4:
12824 size = NVRAM_SELFBOOT_FORMAT1_4_SIZE;
12825 break;
12826 case TG3_EEPROM_SB_REVISION_5:
12827 size = NVRAM_SELFBOOT_FORMAT1_5_SIZE;
12828 break;
12829 case TG3_EEPROM_SB_REVISION_6:
12830 size = NVRAM_SELFBOOT_FORMAT1_6_SIZE;
12831 break;
a5767dec 12832 default:
727a6d9f 12833 return -EIO;
a5767dec
MC		 12834 }
12835 } else
1b27777a 12836 return 0;
b16250e3
MC		 12837 } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
12838 size = NVRAM_SELFBOOT_HW_SIZE;
12839 else
1b27777a
MC		 12840 return -EIO;
12841
12842 buf = kmalloc(size, GFP_KERNEL);
566f86ad
MC		 12843 if (buf == NULL)
12844 return -ENOMEM;
12845
1b27777a
MC		 12846 err = -EIO;
12847 for (i = 0, j = 0; i < size; i += 4, j++) {
a9dc529d
MC		 12848 err = tg3_nvram_read_be32(tp, i, &buf[j]);
12849 if (err)
566f86ad 12850 break;
566f86ad 12851 }
1b27777a 12852 if (i < size)
566f86ad
MC		 12853 goto out;
12854
1b27777a 12855 /* Selfboot format */
a9dc529d 12856 magic = be32_to_cpu(buf[0]);
b9fc7dc5 12857 if ((magic & TG3_EEPROM_MAGIC_FW_MSK) ==
b16250e3 12858 TG3_EEPROM_MAGIC_FW) {
1b27777a
MC		 12859 u8 *buf8 = (u8 *) buf, csum8 = 0;
12860
b9fc7dc5 12861 if ((magic & TG3_EEPROM_SB_REVISION_MASK) ==
a5767dec
MC		 12862 TG3_EEPROM_SB_REVISION_2) {
12863 /* For rev 2, the csum doesn't include the MBA. */
12864 for (i = 0; i < TG3_EEPROM_SB_F1R2_MBA_OFF; i++)
12865 csum8 += buf8[i];
12866 for (i = TG3_EEPROM_SB_F1R2_MBA_OFF + 4; i < size; i++)
12867 csum8 += buf8[i];
12868 } else {
12869 for (i = 0; i < size; i++)
12870 csum8 += buf8[i];
12871 }
1b27777a 12872
ad96b485
AB		 12873 if (csum8 == 0) {
12874 err = 0;
12875 goto out;
12876 }
12877
12878 err = -EIO;
12879 goto out;
1b27777a 12880 }
566f86ad 12881
b9fc7dc5 12882 if ((magic & TG3_EEPROM_MAGIC_HW_MSK) ==
b16250e3
MC		 12883 TG3_EEPROM_MAGIC_HW) {
12884 u8 data[NVRAM_SELFBOOT_DATA_SIZE];
a9dc529d 12885 u8 parity[NVRAM_SELFBOOT_DATA_SIZE];
b16250e3 12886 u8 *buf8 = (u8 *) buf;
b16250e3
MC		 12887
12888 /* Separate the parity bits and the data bytes. */
12889 for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) {
12890 if ((i == 0) || (i == 8)) {
12891 int l;
12892 u8 msk;
12893
12894 for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1)
12895 parity[k++] = buf8[i] & msk;
12896 i++;
859a5887 12897 } else if (i == 16) {
b16250e3
MC		 12898 int l;
12899 u8 msk;
12900
12901 for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1)
12902 parity[k++] = buf8[i] & msk;
12903 i++;
12904
12905 for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1)
12906 parity[k++] = buf8[i] & msk;
12907 i++;
12908 }
12909 data[j++] = buf8[i];
12910 }
12911
12912 err = -EIO;
12913 for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) {
12914 u8 hw8 = hweight8(data[i]);
12915
12916 if ((hw8 & 0x1) && parity[i])
12917 goto out;
12918 else if (!(hw8 & 0x1) && !parity[i])
12919 goto out;
12920 }
12921 err = 0;
12922 goto out;
12923 }
12924
01c3a392
MC		 12925 err = -EIO;
12926
566f86ad
MC		 12927 /* Bootstrap checksum at offset 0x10 */
12928 csum = calc_crc((unsigned char *) buf, 0x10);
01c3a392 12929 if (csum != le32_to_cpu(buf[0x10/4]))
566f86ad
MC		 12930 goto out;
12931
12932 /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
12933 csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
01c3a392 12934 if (csum != le32_to_cpu(buf[0xfc/4]))
a9dc529d 12935 goto out;
566f86ad 12936
c3e94500
MC		 12937 kfree(buf);
12938
535a490e 12939 buf = tg3_vpd_readblock(tp, &len);
c3e94500
MC		 12940 if (!buf)
12941 return -ENOMEM;
d4894f3e 12942
535a490e 12943 i = pci_vpd_find_tag((u8 *)buf, 0, len, PCI_VPD_LRDT_RO_DATA);
d4894f3e
MC		 12944 if (i > 0) {
12945 j = pci_vpd_lrdt_size(&((u8 *)buf)[i]);
12946 if (j < 0)
12947 goto out;
12948
535a490e 12949 if (i + PCI_VPD_LRDT_TAG_SIZE + j > len)
d4894f3e
MC		 12950 goto out;
12951
12952 i += PCI_VPD_LRDT_TAG_SIZE;
12953 j = pci_vpd_find_info_keyword((u8 *)buf, i, j,
12954 PCI_VPD_RO_KEYWORD_CHKSUM);
12955 if (j > 0) {
12956 u8 csum8 = 0;
12957
12958 j += PCI_VPD_INFO_FLD_HDR_SIZE;
12959
12960 for (i = 0; i <= j; i++)
12961 csum8 += ((u8 *)buf)[i];
12962
12963 if (csum8)
12964 goto out;
12965 }
12966 }
12967
566f86ad
MC		 12968 err = 0;
12969
12970out:
12971 kfree(buf);
12972 return err;
12973}
12974
ca43007a
MC		 12975#define TG3_SERDES_TIMEOUT_SEC 2
12976#define TG3_COPPER_TIMEOUT_SEC 6
12977
12978static int tg3_test_link(struct tg3 *tp)
12979{
12980 int i, max;
12981
12982 if (!netif_running(tp->dev))
12983 return -ENODEV;
12984
f07e9af3 12985 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
ca43007a
MC		 12986 max = TG3_SERDES_TIMEOUT_SEC;
12987 else
12988 max = TG3_COPPER_TIMEOUT_SEC;
12989
12990 for (i = 0; i < max; i++) {
f4a46d1f 12991 if (tp->link_up)
ca43007a
MC		 12992 return 0;
12993
12994 if (msleep_interruptible(1000))
12995 break;
12996 }
12997
12998 return -EIO;
12999}
13000
a71116d1 13001/* Only test the commonly used registers */
30ca3e37 13002static int tg3_test_registers(struct tg3 *tp)
a71116d1 13003{
b16250e3 13004 int i, is_5705, is_5750;
a71116d1
MC		 13005 u32 offset, read_mask, write_mask, val, save_val, read_val;
13006 static struct {
13007 u16 offset;
13008 u16 flags;
13009#define TG3_FL_5705 0x1
13010#define TG3_FL_NOT_5705 0x2
13011#define TG3_FL_NOT_5788 0x4
b16250e3 13012#define TG3_FL_NOT_5750 0x8
a71116d1
MC		 13013 u32 read_mask;
13014 u32 write_mask;
13015 } reg_tbl[] = {
13016 /* MAC Control Registers */
13017 { MAC_MODE, TG3_FL_NOT_5705,
13018 0x00000000, 0x00ef6f8c },
13019 { MAC_MODE, TG3_FL_5705,
13020 0x00000000, 0x01ef6b8c },
13021 { MAC_STATUS, TG3_FL_NOT_5705,
13022 0x03800107, 0x00000000 },
13023 { MAC_STATUS, TG3_FL_5705,
13024 0x03800100, 0x00000000 },
13025 { MAC_ADDR_0_HIGH, 0x0000,
13026 0x00000000, 0x0000ffff },
13027 { MAC_ADDR_0_LOW, 0x0000,
c6cdf436 13028 0x00000000, 0xffffffff },
a71116d1
MC		 13029 { MAC_RX_MTU_SIZE, 0x0000,
13030 0x00000000, 0x0000ffff },
13031 { MAC_TX_MODE, 0x0000,
13032 0x00000000, 0x00000070 },
13033 { MAC_TX_LENGTHS, 0x0000,
13034 0x00000000, 0x00003fff },
13035 { MAC_RX_MODE, TG3_FL_NOT_5705,
13036 0x00000000, 0x000007fc },
13037 { MAC_RX_MODE, TG3_FL_5705,
13038 0x00000000, 0x000007dc },
13039 { MAC_HASH_REG_0, 0x0000,
13040 0x00000000, 0xffffffff },
13041 { MAC_HASH_REG_1, 0x0000,
13042 0x00000000, 0xffffffff },
13043 { MAC_HASH_REG_2, 0x0000,
13044 0x00000000, 0xffffffff },
13045 { MAC_HASH_REG_3, 0x0000,
13046 0x00000000, 0xffffffff },
13047
13048 /* Receive Data and Receive BD Initiator Control Registers. */
13049 { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
13050 0x00000000, 0xffffffff },
13051 { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
13052 0x00000000, 0xffffffff },
13053 { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
13054 0x00000000, 0x00000003 },
13055 { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
13056 0x00000000, 0xffffffff },
13057 { RCVDBDI_STD_BD+0, 0x0000,
13058 0x00000000, 0xffffffff },
13059 { RCVDBDI_STD_BD+4, 0x0000,
13060 0x00000000, 0xffffffff },
13061 { RCVDBDI_STD_BD+8, 0x0000,
13062 0x00000000, 0xffff0002 },
13063 { RCVDBDI_STD_BD+0xc, 0x0000,
13064 0x00000000, 0xffffffff },
6aa20a22 13065
a71116d1
MC		 13066 /* Receive BD Initiator Control Registers. */
13067 { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
13068 0x00000000, 0xffffffff },
13069 { RCVBDI_STD_THRESH, TG3_FL_5705,
13070 0x00000000, 0x000003ff },
13071 { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
13072 0x00000000, 0xffffffff },
6aa20a22 13073
a71116d1
MC		 13074 /* Host Coalescing Control Registers. */
13075 { HOSTCC_MODE, TG3_FL_NOT_5705,
13076 0x00000000, 0x00000004 },
13077 { HOSTCC_MODE, TG3_FL_5705,
13078 0x00000000, 0x000000f6 },
13079 { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
13080 0x00000000, 0xffffffff },
13081 { HOSTCC_RXCOL_TICKS, TG3_FL_5705,
13082 0x00000000, 0x000003ff },
13083 { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
13084 0x00000000, 0xffffffff },
13085 { HOSTCC_TXCOL_TICKS, TG3_FL_5705,
13086 0x00000000, 0x000003ff },
13087 { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
13088 0x00000000, 0xffffffff },
13089 { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
13090 0x00000000, 0x000000ff },
13091 { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
13092 0x00000000, 0xffffffff },
13093 { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
13094 0x00000000, 0x000000ff },
13095 { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
13096 0x00000000, 0xffffffff },
13097 { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
13098 0x00000000, 0xffffffff },
13099 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
13100 0x00000000, 0xffffffff },
13101 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
13102 0x00000000, 0x000000ff },
13103 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
13104 0x00000000, 0xffffffff },
13105 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
13106 0x00000000, 0x000000ff },
13107 { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
13108 0x00000000, 0xffffffff },
13109 { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
13110 0x00000000, 0xffffffff },
13111 { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
13112 0x00000000, 0xffffffff },
13113 { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
13114 0x00000000, 0xffffffff },
13115 { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
13116 0x00000000, 0xffffffff },
13117 { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
13118 0xffffffff, 0x00000000 },
13119 { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
13120 0xffffffff, 0x00000000 },
13121
13122 /* Buffer Manager Control Registers. */
b16250e3 13123 { BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750,
a71116d1 13124 0x00000000, 0x007fff80 },
b16250e3 13125 { BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750,
a71116d1
MC		 13126 0x00000000, 0x007fffff },
13127 { BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
13128 0x00000000, 0x0000003f },
13129 { BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
13130 0x00000000, 0x000001ff },
13131 { BUFMGR_MB_HIGH_WATER, 0x0000,
13132 0x00000000, 0x000001ff },
13133 { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
13134 0xffffffff, 0x00000000 },
13135 { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
13136 0xffffffff, 0x00000000 },
6aa20a22 13137
a71116d1
MC		 13138 /* Mailbox Registers */
13139 { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
13140 0x00000000, 0x000001ff },
13141 { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
13142 0x00000000, 0x000001ff },
13143 { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
13144 0x00000000, 0x000007ff },
13145 { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
13146 0x00000000, 0x000001ff },
13147
13148 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
13149 };
13150
b16250e3 13151 is_5705 = is_5750 = 0;
63c3a66f 13152 if (tg3_flag(tp, 5705_PLUS)) {
a71116d1 13153 is_5705 = 1;
63c3a66f 13154 if (tg3_flag(tp, 5750_PLUS))
b16250e3
MC		 13155 is_5750 = 1;
13156 }
a71116d1
MC		 13157
13158 for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
13159 if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
13160 continue;
13161
13162 if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
13163 continue;
13164
63c3a66f 13165 if (tg3_flag(tp, IS_5788) &&
a71116d1
MC		 13166 (reg_tbl[i].flags & TG3_FL_NOT_5788))
13167 continue;
13168
b16250e3
MC		 13169 if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750))
13170 continue;
13171
a71116d1
MC		 13172 offset = (u32) reg_tbl[i].offset;
13173 read_mask = reg_tbl[i].read_mask;
13174 write_mask = reg_tbl[i].write_mask;
13175
13176 /* Save the original register content */
13177 save_val = tr32(offset);
13178
13179 /* Determine the read-only value. */
13180 read_val = save_val & read_mask;
13181
13182 /* Write zero to the register, then make sure the read-only bits
13183 * are not changed and the read/write bits are all zeros.
13184 */
13185 tw32(offset, 0);
13186
13187 val = tr32(offset);
13188
13189 /* Test the read-only and read/write bits. */
13190 if (((val & read_mask) != read_val) || (val & write_mask))
13191 goto out;
13192
13193 /* Write ones to all the bits defined by RdMask and WrMask, then
13194 * make sure the read-only bits are not changed and the
13195 * read/write bits are all ones.
13196 */
13197 tw32(offset, read_mask | write_mask);
13198
13199 val = tr32(offset);
13200
13201 /* Test the read-only bits. */
13202 if ((val & read_mask) != read_val)
13203 goto out;
13204
13205 /* Test the read/write bits. */
13206 if ((val & write_mask) != write_mask)
13207 goto out;
13208
13209 tw32(offset, save_val);
13210 }
13211
13212 return 0;
13213
13214out:
9f88f29f 13215 if (netif_msg_hw(tp))
2445e461
MC		 13216 netdev_err(tp->dev,
13217 "Register test failed at offset %x\n", offset);
a71116d1
MC		 13218 tw32(offset, save_val);
13219 return -EIO;
13220}
13221
7942e1db
MC		 13222static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
13223{
f71e1309 13224 static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
7942e1db
MC		 13225 int i;
13226 u32 j;
13227
e9edda69 13228 for (i = 0; i < ARRAY_SIZE(test_pattern); i++) {
7942e1db
MC		 13229 for (j = 0; j < len; j += 4) {
13230 u32 val;
13231
13232 tg3_write_mem(tp, offset + j, test_pattern[i]);
13233 tg3_read_mem(tp, offset + j, &val);
13234 if (val != test_pattern[i])
13235 return -EIO;
13236 }
13237 }
13238 return 0;
13239}
13240
13241static int tg3_test_memory(struct tg3 *tp)
13242{
13243 static struct mem_entry {
13244 u32 offset;
13245 u32 len;
13246 } mem_tbl_570x[] = {
38690194 13247 { 0x00000000, 0x00b50},
7942e1db
MC		 13248 { 0x00002000, 0x1c000},
13249 { 0xffffffff, 0x00000}
13250 }, mem_tbl_5705[] = {
13251 { 0x00000100, 0x0000c},
13252 { 0x00000200, 0x00008},
7942e1db
MC		 13253 { 0x00004000, 0x00800},
13254 { 0x00006000, 0x01000},
13255 { 0x00008000, 0x02000},
13256 { 0x00010000, 0x0e000},
13257 { 0xffffffff, 0x00000}
79f4d13a
MC		 13258 }, mem_tbl_5755[] = {
13259 { 0x00000200, 0x00008},
13260 { 0x00004000, 0x00800},
13261 { 0x00006000, 0x00800},
13262 { 0x00008000, 0x02000},
13263 { 0x00010000, 0x0c000},
13264 { 0xffffffff, 0x00000}
b16250e3
MC		 13265 }, mem_tbl_5906[] = {
13266 { 0x00000200, 0x00008},
13267 { 0x00004000, 0x00400},
13268 { 0x00006000, 0x00400},
13269 { 0x00008000, 0x01000},
13270 { 0x00010000, 0x01000},
13271 { 0xffffffff, 0x00000}
8b5a6c42
MC		 13272 }, mem_tbl_5717[] = {
13273 { 0x00000200, 0x00008},
13274 { 0x00010000, 0x0a000},
13275 { 0x00020000, 0x13c00},
13276 { 0xffffffff, 0x00000}
13277 }, mem_tbl_57765[] = {
13278 { 0x00000200, 0x00008},
13279 { 0x00004000, 0x00800},
13280 { 0x00006000, 0x09800},
13281 { 0x00010000, 0x0a000},
13282 { 0xffffffff, 0x00000}
7942e1db
MC		 13283 };
13284 struct mem_entry *mem_tbl;
13285 int err = 0;
13286 int i;
13287
63c3a66f 13288 if (tg3_flag(tp, 5717_PLUS))
8b5a6c42 13289 mem_tbl = mem_tbl_5717;
c65a17f4 13290 else if (tg3_flag(tp, 57765_CLASS) ||
4153577a 13291 tg3_asic_rev(tp) == ASIC_REV_5762)
8b5a6c42 13292 mem_tbl = mem_tbl_57765;
63c3a66f 13293 else if (tg3_flag(tp, 5755_PLUS))
321d32a0 13294 mem_tbl = mem_tbl_5755;
4153577a 13295 else if (tg3_asic_rev(tp) == ASIC_REV_5906)
321d32a0 13296 mem_tbl = mem_tbl_5906;
63c3a66f 13297 else if (tg3_flag(tp, 5705_PLUS))
321d32a0
MC		 13298 mem_tbl = mem_tbl_5705;
13299 else
7942e1db
MC		 13300 mem_tbl = mem_tbl_570x;
13301
13302 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
be98da6a
MC		 13303 err = tg3_do_mem_test(tp, mem_tbl[i].offset, mem_tbl[i].len);
13304 if (err)
7942e1db
MC		 13305 break;
13306 }
6aa20a22 13307
7942e1db
MC		 13308 return err;
13309}
13310
bb158d69
MC		 13311#define TG3_TSO_MSS 500
13312
13313#define TG3_TSO_IP_HDR_LEN 20
13314#define TG3_TSO_TCP_HDR_LEN 20
13315#define TG3_TSO_TCP_OPT_LEN 12
13316
13317static const u8 tg3_tso_header[] = {
133180x08, 0x00,
133190x45, 0x00, 0x00, 0x00,
133200x00, 0x00, 0x40, 0x00,
133210x40, 0x06, 0x00, 0x00,
133220x0a, 0x00, 0x00, 0x01,
133230x0a, 0x00, 0x00, 0x02,
133240x0d, 0x00, 0xe0, 0x00,
133250x00, 0x00, 0x01, 0x00,
133260x00, 0x00, 0x02, 0x00,
133270x80, 0x10, 0x10, 0x00,
133280x14, 0x09, 0x00, 0x00,
133290x01, 0x01, 0x08, 0x0a,
133300x11, 0x11, 0x11, 0x11,
133310x11, 0x11, 0x11, 0x11,
13332};
9f40dead 13333
28a45957 13334static int tg3_run_loopback(struct tg3 *tp, u32 pktsz, bool tso_loopback)
c76949a6 13335{
5e5a7f37 13336 u32 rx_start_idx, rx_idx, tx_idx, opaque_key;
bb158d69 13337 u32 base_flags = 0, mss = 0, desc_idx, coal_now, data_off, val;
84b67b27 13338 u32 budget;
9205fd9c
ED		 13339 struct sk_buff *skb;
13340 u8 *tx_data, *rx_data;
c76949a6
MC		 13341 dma_addr_t map;
13342 int num_pkts, tx_len, rx_len, i, err;
13343 struct tg3_rx_buffer_desc *desc;
898a56f8 13344 struct tg3_napi *tnapi, *rnapi;
8fea32b9 13345 struct tg3_rx_prodring_set *tpr = &tp->napi[0].prodring;
c76949a6 13346
c8873405
MC		 13347 tnapi = &tp->napi[0];
13348 rnapi = &tp->napi[0];
0c1d0e2b 13349 if (tp->irq_cnt > 1) {
63c3a66f 13350 if (tg3_flag(tp, ENABLE_RSS))
1da85aa3 13351 rnapi = &tp->napi[1];
63c3a66f 13352 if (tg3_flag(tp, ENABLE_TSS))
c8873405 13353 tnapi = &tp->napi[1];
0c1d0e2b 13354 }
fd2ce37f 13355 coal_now = tnapi->coal_now | rnapi->coal_now;
898a56f8 13356
c76949a6
MC		 13357 err = -EIO;
13358
4852a861 13359 tx_len = pktsz;
a20e9c62 13360 skb = netdev_alloc_skb(tp->dev, tx_len);
a50bb7b9
JJ		 13361 if (!skb)
13362 return -ENOMEM;
13363
c76949a6 13364 tx_data = skb_put(skb, tx_len);
d458cdf7
JP		 13365 memcpy(tx_data, tp->dev->dev_addr, ETH_ALEN);
13366 memset(tx_data + ETH_ALEN, 0x0, 8);
c76949a6 13367
4852a861 13368 tw32(MAC_RX_MTU_SIZE, tx_len + ETH_FCS_LEN);
c76949a6 13369
28a45957 13370 if (tso_loopback) {
bb158d69
MC		 13371 struct iphdr *iph = (struct iphdr *)&tx_data[ETH_HLEN];
13372
13373 u32 hdr_len = TG3_TSO_IP_HDR_LEN + TG3_TSO_TCP_HDR_LEN +
13374 TG3_TSO_TCP_OPT_LEN;
13375
13376 memcpy(tx_data + ETH_ALEN * 2, tg3_tso_header,
13377 sizeof(tg3_tso_header));
13378 mss = TG3_TSO_MSS;
13379
13380 val = tx_len - ETH_ALEN * 2 - sizeof(tg3_tso_header);
13381 num_pkts = DIV_ROUND_UP(val, TG3_TSO_MSS);
13382
13383 /* Set the total length field in the IP header */
13384 iph->tot_len = htons((u16)(mss + hdr_len));
13385
13386 base_flags = (TXD_FLAG_CPU_PRE_DMA |
13387 TXD_FLAG_CPU_POST_DMA);
13388
63c3a66f
JP		 13389 if (tg3_flag(tp, HW_TSO_1) ||
13390 tg3_flag(tp, HW_TSO_2) ||
13391 tg3_flag(tp, HW_TSO_3)) {
bb158d69
MC		 13392 struct tcphdr *th;
13393 val = ETH_HLEN + TG3_TSO_IP_HDR_LEN;
13394 th = (struct tcphdr *)&tx_data[val];
13395 th->check = 0;
13396 } else
13397 base_flags |= TXD_FLAG_TCPUDP_CSUM;
13398
63c3a66f 13399 if (tg3_flag(tp, HW_TSO_3)) {
bb158d69
MC		 13400 mss |= (hdr_len & 0xc) << 12;
13401 if (hdr_len & 0x10)
13402 base_flags |= 0x00000010;
13403 base_flags |= (hdr_len & 0x3e0) << 5;
63c3a66f 13404 } else if (tg3_flag(tp, HW_TSO_2))
bb158d69 13405 mss |= hdr_len << 9;
63c3a66f 13406 else if (tg3_flag(tp, HW_TSO_1) ||
4153577a 13407 tg3_asic_rev(tp) == ASIC_REV_5705) {
bb158d69
MC		 13408 mss |= (TG3_TSO_TCP_OPT_LEN << 9);
13409 } else {
13410 base_flags |= (TG3_TSO_TCP_OPT_LEN << 10);
13411 }
13412
13413 data_off = ETH_ALEN * 2 + sizeof(tg3_tso_header);
13414 } else {
13415 num_pkts = 1;
13416 data_off = ETH_HLEN;
c441b456
MC		 13417
13418 if (tg3_flag(tp, USE_JUMBO_BDFLAG) &&
13419 tx_len > VLAN_ETH_FRAME_LEN)
13420 base_flags |= TXD_FLAG_JMB_PKT;
bb158d69
MC		 13421 }
13422
13423 for (i = data_off; i < tx_len; i++)
c76949a6
MC		 13424 tx_data[i] = (u8) (i & 0xff);
13425
f4188d8a
AD		 13426 map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE);
13427 if (pci_dma_mapping_error(tp->pdev, map)) {
a21771dd
MC		 13428 dev_kfree_skb(skb);
13429 return -EIO;
13430 }
c76949a6 13431
0d681b27
MC		 13432 val = tnapi->tx_prod;
13433 tnapi->tx_buffers[val].skb = skb;
13434 dma_unmap_addr_set(&tnapi->tx_buffers[val], mapping, map);
13435
c76949a6 13436 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
fd2ce37f 13437 rnapi->coal_now);
c76949a6
MC		 13438
13439 udelay(10);
13440
898a56f8 13441 rx_start_idx = rnapi->hw_status->idx[0].rx_producer;
c76949a6 13442
84b67b27
MC		 13443 budget = tg3_tx_avail(tnapi);
13444 if (tg3_tx_frag_set(tnapi, &val, &budget, map, tx_len,
d1a3b737
MC		 13445 base_flags | TXD_FLAG_END, mss, 0)) {
13446 tnapi->tx_buffers[val].skb = NULL;
13447 dev_kfree_skb(skb);
13448 return -EIO;
13449 }
c76949a6 13450
f3f3f27e 13451 tnapi->tx_prod++;
c76949a6 13452
6541b806
MC		 13453 /* Sync BD data before updating mailbox */
13454 wmb();
13455
f3f3f27e
MC		 13456 tw32_tx_mbox(tnapi->prodmbox, tnapi->tx_prod);
13457 tr32_mailbox(tnapi->prodmbox);
c76949a6
MC		 13458
13459 udelay(10);
13460
303fc921
MC		 13461 /* 350 usec to allow enough time on some 10/100 Mbps devices. */
13462 for (i = 0; i < 35; i++) {
c76949a6 13463 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
fd2ce37f 13464 coal_now);
c76949a6
MC		 13465
13466 udelay(10);
13467
898a56f8
MC		 13468 tx_idx = tnapi->hw_status->idx[0].tx_consumer;
13469 rx_idx = rnapi->hw_status->idx[0].rx_producer;
f3f3f27e 13470 if ((tx_idx == tnapi->tx_prod) &&
c76949a6
MC		 13471 (rx_idx == (rx_start_idx + num_pkts)))
13472 break;
13473 }
13474
ba1142e4 13475 tg3_tx_skb_unmap(tnapi, tnapi->tx_prod - 1, -1);
c76949a6
MC		 13476 dev_kfree_skb(skb);
13477
f3f3f27e 13478 if (tx_idx != tnapi->tx_prod)
c76949a6
MC		 13479 goto out;
13480
13481 if (rx_idx != rx_start_idx + num_pkts)
13482 goto out;
13483
bb158d69
MC		 13484 val = data_off;
13485 while (rx_idx != rx_start_idx) {
13486 desc = &rnapi->rx_rcb[rx_start_idx++];
13487 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
13488 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
c76949a6 13489
bb158d69
MC		 13490 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
13491 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
13492 goto out;
c76949a6 13493
bb158d69
MC		 13494 rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT)
13495 - ETH_FCS_LEN;
c76949a6 13496
28a45957 13497 if (!tso_loopback) {
bb158d69
MC		 13498 if (rx_len != tx_len)
13499 goto out;
4852a861 13500
bb158d69
MC		 13501 if (pktsz <= TG3_RX_STD_DMA_SZ - ETH_FCS_LEN) {
13502 if (opaque_key != RXD_OPAQUE_RING_STD)
13503 goto out;
13504 } else {
13505 if (opaque_key != RXD_OPAQUE_RING_JUMBO)
13506 goto out;
13507 }
13508 } else if ((desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
13509 (desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
54e0a67f 13510 >> RXD_TCPCSUM_SHIFT != 0xffff) {
4852a861 13511 goto out;
bb158d69 13512 }
4852a861 13513
bb158d69 13514 if (opaque_key == RXD_OPAQUE_RING_STD) {
9205fd9c 13515 rx_data = tpr->rx_std_buffers[desc_idx].data;
bb158d69
MC		 13516 map = dma_unmap_addr(&tpr->rx_std_buffers[desc_idx],
13517 mapping);
13518 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
9205fd9c 13519 rx_data = tpr->rx_jmb_buffers[desc_idx].data;
bb158d69
MC		 13520 map = dma_unmap_addr(&tpr->rx_jmb_buffers[desc_idx],
13521 mapping);
13522 } else
13523 goto out;
c76949a6 13524
bb158d69
MC		 13525 pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len,
13526 PCI_DMA_FROMDEVICE);
c76949a6 13527
9205fd9c 13528 rx_data += TG3_RX_OFFSET(tp);
bb158d69 13529 for (i = data_off; i < rx_len; i++, val++) {
9205fd9c 13530 if (*(rx_data + i) != (u8) (val & 0xff))
bb158d69
MC		 13531 goto out;
13532 }
c76949a6 13533 }
bb158d69 13534
c76949a6 13535 err = 0;
6aa20a22 13536
9205fd9c 13537 /* tg3_free_rings will unmap and free the rx_data */
c76949a6
MC		 13538out:
13539 return err;
13540}
13541
00c266b7
MC		 13542#define TG3_STD_LOOPBACK_FAILED 1
13543#define TG3_JMB_LOOPBACK_FAILED 2
bb158d69 13544#define TG3_TSO_LOOPBACK_FAILED 4
28a45957
MC		 13545#define TG3_LOOPBACK_FAILED \
13546 (TG3_STD_LOOPBACK_FAILED | \
13547 TG3_JMB_LOOPBACK_FAILED | \
13548 TG3_TSO_LOOPBACK_FAILED)
00c266b7 13549
941ec90f 13550static int tg3_test_loopback(struct tg3 *tp, u64 *data, bool do_extlpbk)
9f40dead 13551{
28a45957 13552 int err = -EIO;
2215e24c 13553 u32 eee_cap;
c441b456
MC		 13554 u32 jmb_pkt_sz = 9000;
13555
13556 if (tp->dma_limit)
13557 jmb_pkt_sz = tp->dma_limit - ETH_HLEN;
9f40dead 13558
ab789046
MC		 13559 eee_cap = tp->phy_flags & TG3_PHYFLG_EEE_CAP;
13560 tp->phy_flags &= ~TG3_PHYFLG_EEE_CAP;
13561
28a45957 13562 if (!netif_running(tp->dev)) {
93df8b8f
NNS		 13563 data[TG3_MAC_LOOPB_TEST] = TG3_LOOPBACK_FAILED;
13564 data[TG3_PHY_LOOPB_TEST] = TG3_LOOPBACK_FAILED;
941ec90f 13565 if (do_extlpbk)
93df8b8f 13566 data[TG3_EXT_LOOPB_TEST] = TG3_LOOPBACK_FAILED;
28a45957
MC		 13567 goto done;
13568 }
13569
953c96e0 13570 err = tg3_reset_hw(tp, true);
ab789046 13571 if (err) {
93df8b8f
NNS		 13572 data[TG3_MAC_LOOPB_TEST] = TG3_LOOPBACK_FAILED;
13573 data[TG3_PHY_LOOPB_TEST] = TG3_LOOPBACK_FAILED;
941ec90f 13574 if (do_extlpbk)
93df8b8f 13575 data[TG3_EXT_LOOPB_TEST] = TG3_LOOPBACK_FAILED;
ab789046
MC		 13576 goto done;
13577 }
9f40dead 13578
63c3a66f 13579 if (tg3_flag(tp, ENABLE_RSS)) {
4a85f098
MC		 13580 int i;
13581
13582 /* Reroute all rx packets to the 1st queue */
13583 for (i = MAC_RSS_INDIR_TBL_0;
13584 i < MAC_RSS_INDIR_TBL_0 + TG3_RSS_INDIR_TBL_SIZE; i += 4)
13585 tw32(i, 0x0);
13586 }
13587
6e01b20b
MC		 13588 /* HW errata - mac loopback fails in some cases on 5780.
13589 * Normal traffic and PHY loopback are not affected by
13590 * errata. Also, the MAC loopback test is deprecated for
13591 * all newer ASIC revisions.
13592 */
4153577a 13593 if (tg3_asic_rev(tp) != ASIC_REV_5780 &&
6e01b20b
MC		 13594 !tg3_flag(tp, CPMU_PRESENT)) {
13595 tg3_mac_loopback(tp, true);
9936bcf6 13596
28a45957 13597 if (tg3_run_loopback(tp, ETH_FRAME_LEN, false))
93df8b8f 13598 data[TG3_MAC_LOOPB_TEST] |= TG3_STD_LOOPBACK_FAILED;
6e01b20b
MC		 13599
13600 if (tg3_flag(tp, JUMBO_RING_ENABLE) &&
c441b456 13601 tg3_run_loopback(tp, jmb_pkt_sz + ETH_HLEN, false))
93df8b8f 13602 data[TG3_MAC_LOOPB_TEST] |= TG3_JMB_LOOPBACK_FAILED;
6e01b20b
MC		 13603
13604 tg3_mac_loopback(tp, false);
13605 }
4852a861 13606
f07e9af3 13607 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
63c3a66f 13608 !tg3_flag(tp, USE_PHYLIB)) {
5e5a7f37
MC		 13609 int i;
13610
941ec90f 13611 tg3_phy_lpbk_set(tp, 0, false);
5e5a7f37
MC		 13612
13613 /* Wait for link */
13614 for (i = 0; i < 100; i++) {
13615 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
13616 break;
13617 mdelay(1);
13618 }
13619
28a45957 13620 if (tg3_run_loopback(tp, ETH_FRAME_LEN, false))
93df8b8f 13621 data[TG3_PHY_LOOPB_TEST] |= TG3_STD_LOOPBACK_FAILED;
63c3a66f 13622 if (tg3_flag(tp, TSO_CAPABLE) &&
28a45957 13623 tg3_run_loopback(tp, ETH_FRAME_LEN, true))
93df8b8f 13624 data[TG3_PHY_LOOPB_TEST] |= TG3_TSO_LOOPBACK_FAILED;
63c3a66f 13625 if (tg3_flag(tp, JUMBO_RING_ENABLE) &&
c441b456 13626 tg3_run_loopback(tp, jmb_pkt_sz + ETH_HLEN, false))
93df8b8f 13627 data[TG3_PHY_LOOPB_TEST] |= TG3_JMB_LOOPBACK_FAILED;
9f40dead 13628
941ec90f
MC		 13629 if (do_extlpbk) {
13630 tg3_phy_lpbk_set(tp, 0, true);
13631
13632 /* All link indications report up, but the hardware
13633 * isn't really ready for about 20 msec. Double it
13634 * to be sure.
13635 */
13636 mdelay(40);
13637
13638 if (tg3_run_loopback(tp, ETH_FRAME_LEN, false))
93df8b8f
NNS		 13639 data[TG3_EXT_LOOPB_TEST] |=
13640 TG3_STD_LOOPBACK_FAILED;
941ec90f
MC		 13641 if (tg3_flag(tp, TSO_CAPABLE) &&
13642 tg3_run_loopback(tp, ETH_FRAME_LEN, true))
93df8b8f
NNS		 13643 data[TG3_EXT_LOOPB_TEST] |=
13644 TG3_TSO_LOOPBACK_FAILED;
941ec90f 13645 if (tg3_flag(tp, JUMBO_RING_ENABLE) &&
c441b456 13646 tg3_run_loopback(tp, jmb_pkt_sz + ETH_HLEN, false))
93df8b8f
NNS		 13647 data[TG3_EXT_LOOPB_TEST] |=
13648 TG3_JMB_LOOPBACK_FAILED;
941ec90f
MC		 13649 }
13650
5e5a7f37
MC		 13651 /* Re-enable gphy autopowerdown. */
13652 if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD)
13653 tg3_phy_toggle_apd(tp, true);
13654 }
6833c043 13655
93df8b8f
NNS		 13656 err = (data[TG3_MAC_LOOPB_TEST] | data[TG3_PHY_LOOPB_TEST] |
13657 data[TG3_EXT_LOOPB_TEST]) ? -EIO : 0;
28a45957 13658
ab789046
MC		 13659done:
13660 tp->phy_flags |= eee_cap;
13661
9f40dead
MC		 13662 return err;
13663}
13664
4cafd3f5
MC		 13665static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
13666 u64 *data)
13667{
566f86ad 13668 struct tg3 *tp = netdev_priv(dev);
941ec90f 13669 bool doextlpbk = etest->flags & ETH_TEST_FL_EXTERNAL_LB;
566f86ad 13670
2e460fc0
NS		 13671 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
13672 if (tg3_power_up(tp)) {
13673 etest->flags |= ETH_TEST_FL_FAILED;
13674 memset(data, 1, sizeof(u64) * TG3_NUM_TEST);
13675 return;
13676 }
13677 tg3_ape_driver_state_change(tp, RESET_KIND_INIT);
bed9829f 13678 }
bc1c7567 13679
566f86ad
MC		 13680 memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
13681
13682 if (tg3_test_nvram(tp) != 0) {
13683 etest->flags |= ETH_TEST_FL_FAILED;
93df8b8f 13684 data[TG3_NVRAM_TEST] = 1;
566f86ad 13685 }
941ec90f 13686 if (!doextlpbk && tg3_test_link(tp)) {
ca43007a 13687 etest->flags |= ETH_TEST_FL_FAILED;
93df8b8f 13688 data[TG3_LINK_TEST] = 1;
ca43007a 13689 }
a71116d1 13690 if (etest->flags & ETH_TEST_FL_OFFLINE) {
b02fd9e3 13691 int err, err2 = 0, irq_sync = 0;
bbe832c0
MC		 13692
13693 if (netif_running(dev)) {
b02fd9e3 13694 tg3_phy_stop(tp);
a71116d1 13695 tg3_netif_stop(tp);
bbe832c0
MC		 13696 irq_sync = 1;
13697 }
a71116d1 13698
bbe832c0 13699 tg3_full_lock(tp, irq_sync);
a71116d1 13700 tg3_halt(tp, RESET_KIND_SUSPEND, 1);
ec41c7df 13701 err = tg3_nvram_lock(tp);
a71116d1 13702 tg3_halt_cpu(tp, RX_CPU_BASE);
63c3a66f 13703 if (!tg3_flag(tp, 5705_PLUS))
a71116d1 13704 tg3_halt_cpu(tp, TX_CPU_BASE);
ec41c7df
MC		 13705 if (!err)
13706 tg3_nvram_unlock(tp);
a71116d1 13707
f07e9af3 13708 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
d9ab5ad1
MC		 13709 tg3_phy_reset(tp);
13710
a71116d1
MC		 13711 if (tg3_test_registers(tp) != 0) {
13712 etest->flags |= ETH_TEST_FL_FAILED;
93df8b8f 13713 data[TG3_REGISTER_TEST] = 1;
a71116d1 13714 }
28a45957 13715
7942e1db
MC		 13716 if (tg3_test_memory(tp) != 0) {
13717 etest->flags |= ETH_TEST_FL_FAILED;
93df8b8f 13718 data[TG3_MEMORY_TEST] = 1;
7942e1db 13719 }
28a45957 13720
941ec90f
MC		 13721 if (doextlpbk)
13722 etest->flags |= ETH_TEST_FL_EXTERNAL_LB_DONE;
13723
93df8b8f 13724 if (tg3_test_loopback(tp, data, doextlpbk))
c76949a6 13725 etest->flags |= ETH_TEST_FL_FAILED;
a71116d1 13726
f47c11ee
DM		 13727 tg3_full_unlock(tp);
13728
d4bc3927
MC		 13729 if (tg3_test_interrupt(tp) != 0) {
13730 etest->flags |= ETH_TEST_FL_FAILED;
93df8b8f 13731 data[TG3_INTERRUPT_TEST] = 1;
d4bc3927 13732 }
f47c11ee
DM		 13733
13734 tg3_full_lock(tp, 0);
d4bc3927 13735
a71116d1
MC		 13736 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
13737 if (netif_running(dev)) {
63c3a66f 13738 tg3_flag_set(tp, INIT_COMPLETE);
953c96e0 13739 err2 = tg3_restart_hw(tp, true);
b02fd9e3 13740 if (!err2)
b9ec6c1b 13741 tg3_netif_start(tp);
a71116d1 13742 }
f47c11ee
DM		 13743
13744 tg3_full_unlock(tp);
b02fd9e3
MC		 13745
13746 if (irq_sync && !err2)
13747 tg3_phy_start(tp);
a71116d1 13748 }
80096068 13749 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
5137a2ee 13750 tg3_power_down_prepare(tp);
bc1c7567 13751
4cafd3f5
MC		 13752}
13753
7260899b 13754static int tg3_hwtstamp_set(struct net_device *dev, struct ifreq *ifr)
0a633ac2
MC		 13755{
13756 struct tg3 *tp = netdev_priv(dev);
13757 struct hwtstamp_config stmpconf;
13758
13759 if (!tg3_flag(tp, PTP_CAPABLE))
7260899b 13760 return -EOPNOTSUPP;
0a633ac2
MC		 13761
13762 if (copy_from_user(&stmpconf, ifr->ifr_data, sizeof(stmpconf)))
13763 return -EFAULT;
13764
13765 if (stmpconf.flags)
13766 return -EINVAL;
13767
58b187c6
BH		 13768 if (stmpconf.tx_type != HWTSTAMP_TX_ON &&
13769 stmpconf.tx_type != HWTSTAMP_TX_OFF)
0a633ac2 13770 return -ERANGE;
0a633ac2
MC		 13771
13772 switch (stmpconf.rx_filter) {
13773 case HWTSTAMP_FILTER_NONE:
13774 tp->rxptpctl = 0;
13775 break;
13776 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
13777 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V1_EN |
13778 TG3_RX_PTP_CTL_ALL_V1_EVENTS;
13779 break;
13780 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
13781 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V1_EN |
13782 TG3_RX_PTP_CTL_SYNC_EVNT;
13783 break;
13784 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
13785 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V1_EN |
13786 TG3_RX_PTP_CTL_DELAY_REQ;
13787 break;
13788 case HWTSTAMP_FILTER_PTP_V2_EVENT:
13789 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_EN |
13790 TG3_RX_PTP_CTL_ALL_V2_EVENTS;
13791 break;
13792 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
13793 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L2_EN |
13794 TG3_RX_PTP_CTL_ALL_V2_EVENTS;
13795 break;
13796 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
13797 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L4_EN |
13798 TG3_RX_PTP_CTL_ALL_V2_EVENTS;
13799 break;
13800 case HWTSTAMP_FILTER_PTP_V2_SYNC:
13801 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_EN |
13802 TG3_RX_PTP_CTL_SYNC_EVNT;
13803 break;
13804 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
13805 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L2_EN |
13806 TG3_RX_PTP_CTL_SYNC_EVNT;
13807 break;
13808 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
13809 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L4_EN |
13810 TG3_RX_PTP_CTL_SYNC_EVNT;
13811 break;
13812 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
13813 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_EN |
13814 TG3_RX_PTP_CTL_DELAY_REQ;
13815 break;
13816 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
13817 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L2_EN |
13818 TG3_RX_PTP_CTL_DELAY_REQ;
13819 break;
13820 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
13821 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L4_EN |
13822 TG3_RX_PTP_CTL_DELAY_REQ;
13823 break;
13824 default:
13825 return -ERANGE;
13826 }
13827
13828 if (netif_running(dev) && tp->rxptpctl)
13829 tw32(TG3_RX_PTP_CTL,
13830 tp->rxptpctl | TG3_RX_PTP_CTL_HWTS_INTERLOCK);
13831
58b187c6
BH		 13832 if (stmpconf.tx_type == HWTSTAMP_TX_ON)
13833 tg3_flag_set(tp, TX_TSTAMP_EN);
13834 else
13835 tg3_flag_clear(tp, TX_TSTAMP_EN);
13836
0a633ac2
MC		 13837 return copy_to_user(ifr->ifr_data, &stmpconf, sizeof(stmpconf)) ?
13838 -EFAULT : 0;
13839}
13840
7260899b
BH		 13841static int tg3_hwtstamp_get(struct net_device *dev, struct ifreq *ifr)
13842{
13843 struct tg3 *tp = netdev_priv(dev);
13844 struct hwtstamp_config stmpconf;
13845
13846 if (!tg3_flag(tp, PTP_CAPABLE))
13847 return -EOPNOTSUPP;
13848
13849 stmpconf.flags = 0;
13850 stmpconf.tx_type = (tg3_flag(tp, TX_TSTAMP_EN) ?
13851 HWTSTAMP_TX_ON : HWTSTAMP_TX_OFF);
13852
13853 switch (tp->rxptpctl) {
13854 case 0:
13855 stmpconf.rx_filter = HWTSTAMP_FILTER_NONE;
13856 break;
13857 case TG3_RX_PTP_CTL_RX_PTP_V1_EN | TG3_RX_PTP_CTL_ALL_V1_EVENTS:
13858 stmpconf.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
13859 break;
13860 case TG3_RX_PTP_CTL_RX_PTP_V1_EN | TG3_RX_PTP_CTL_SYNC_EVNT:
13861 stmpconf.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_SYNC;
13862 break;
13863 case TG3_RX_PTP_CTL_RX_PTP_V1_EN | TG3_RX_PTP_CTL_DELAY_REQ:
13864 stmpconf.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ;
13865 break;
13866 case TG3_RX_PTP_CTL_RX_PTP_V2_EN | TG3_RX_PTP_CTL_ALL_V2_EVENTS:
13867 stmpconf.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
13868 break;
13869 case TG3_RX_PTP_CTL_RX_PTP_V2_L2_EN | TG3_RX_PTP_CTL_ALL_V2_EVENTS:
13870 stmpconf.rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_EVENT;
13871 break;
13872 case TG3_RX_PTP_CTL_RX_PTP_V2_L4_EN | TG3_RX_PTP_CTL_ALL_V2_EVENTS:
13873 stmpconf.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT;
13874 break;
13875 case TG3_RX_PTP_CTL_RX_PTP_V2_EN | TG3_RX_PTP_CTL_SYNC_EVNT:
13876 stmpconf.rx_filter = HWTSTAMP_FILTER_PTP_V2_SYNC;
13877 break;
13878 case TG3_RX_PTP_CTL_RX_PTP_V2_L2_EN | TG3_RX_PTP_CTL_SYNC_EVNT:
13879 stmpconf.rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_SYNC;
13880 break;
13881 case TG3_RX_PTP_CTL_RX_PTP_V2_L4_EN | TG3_RX_PTP_CTL_SYNC_EVNT:
13882 stmpconf.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_SYNC;
13883 break;
13884 case TG3_RX_PTP_CTL_RX_PTP_V2_EN | TG3_RX_PTP_CTL_DELAY_REQ:
13885 stmpconf.rx_filter = HWTSTAMP_FILTER_PTP_V2_DELAY_REQ;
13886 break;
13887 case TG3_RX_PTP_CTL_RX_PTP_V2_L2_EN | TG3_RX_PTP_CTL_DELAY_REQ:
13888 stmpconf.rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ;
13889 break;
13890 case TG3_RX_PTP_CTL_RX_PTP_V2_L4_EN | TG3_RX_PTP_CTL_DELAY_REQ:
13891 stmpconf.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ;
13892 break;
13893 default:
13894 WARN_ON_ONCE(1);
13895 return -ERANGE;
13896 }
13897
13898 return copy_to_user(ifr->ifr_data, &stmpconf, sizeof(stmpconf)) ?
13899 -EFAULT : 0;
13900}
13901
1da177e4
LT		 13902static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
13903{
13904 struct mii_ioctl_data *data = if_mii(ifr);
13905 struct tg3 *tp = netdev_priv(dev);
13906 int err;
13907
63c3a66f 13908 if (tg3_flag(tp, USE_PHYLIB)) {
3f0e3ad7 13909 struct phy_device *phydev;
f07e9af3 13910 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
b02fd9e3 13911 return -EAGAIN;
ead2402c 13912 phydev = tp->mdio_bus->phy_map[tp->phy_addr];
28b04113 13913 return phy_mii_ioctl(phydev, ifr, cmd);
b02fd9e3
MC		 13914 }
13915
33f401ae 13916 switch (cmd) {
1da177e4 13917 case SIOCGMIIPHY:
882e9793 13918 data->phy_id = tp->phy_addr;
1da177e4
LT		 13919
13920 /* fallthru */
13921 case SIOCGMIIREG: {
13922 u32 mii_regval;
13923
f07e9af3 13924 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
1da177e4
LT		 13925 break; /* We have no PHY */
13926
34eea5ac 13927 if (!netif_running(dev))
bc1c7567
MC		 13928 return -EAGAIN;
13929
f47c11ee 13930 spin_lock_bh(&tp->lock);
5c358045
HM		 13931 err = __tg3_readphy(tp, data->phy_id & 0x1f,
13932 data->reg_num & 0x1f, &mii_regval);
f47c11ee 13933 spin_unlock_bh(&tp->lock);
1da177e4
LT		 13934
13935 data->val_out = mii_regval;
13936
13937 return err;
13938 }
13939
13940 case SIOCSMIIREG:
f07e9af3 13941 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
1da177e4
LT		 13942 break; /* We have no PHY */
13943
34eea5ac 13944 if (!netif_running(dev))
bc1c7567
MC		 13945 return -EAGAIN;
13946
f47c11ee 13947 spin_lock_bh(&tp->lock);
5c358045
HM		 13948 err = __tg3_writephy(tp, data->phy_id & 0x1f,
13949 data->reg_num & 0x1f, data->val_in);
f47c11ee 13950 spin_unlock_bh(&tp->lock);
1da177e4
LT		 13951
13952 return err;
13953
0a633ac2 13954 case SIOCSHWTSTAMP:
7260899b
BH		 13955 return tg3_hwtstamp_set(dev, ifr);
13956
13957 case SIOCGHWTSTAMP:
13958 return tg3_hwtstamp_get(dev, ifr);
0a633ac2 13959
1da177e4
LT		 13960 default:
13961 /* do nothing */
13962 break;
13963 }
13964 return -EOPNOTSUPP;
13965}
13966
15f9850d
DM		 13967static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
13968{
13969 struct tg3 *tp = netdev_priv(dev);
13970
13971 memcpy(ec, &tp->coal, sizeof(*ec));
13972 return 0;
13973}
13974
d244c892
MC		 13975static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
13976{
13977 struct tg3 *tp = netdev_priv(dev);
13978 u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0;
13979 u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0;
13980
63c3a66f 13981 if (!tg3_flag(tp, 5705_PLUS)) {
d244c892
MC		 13982 max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT;
13983 max_txcoal_tick_int = MAX_TXCOAL_TICK_INT;
13984 max_stat_coal_ticks = MAX_STAT_COAL_TICKS;
13985 min_stat_coal_ticks = MIN_STAT_COAL_TICKS;
13986 }
13987
13988 if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) ||
13989 (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) ||
13990 (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) ||
13991 (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) ||
13992 (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) ||
13993 (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) ||
13994 (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) ||
13995 (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) ||
13996 (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) ||
13997 (ec->stats_block_coalesce_usecs < min_stat_coal_ticks))
13998 return -EINVAL;
13999
14000 /* No rx interrupts will be generated if both are zero */
14001 if ((ec->rx_coalesce_usecs == 0) &&
14002 (ec->rx_max_coalesced_frames == 0))
14003 return -EINVAL;
14004
14005 /* No tx interrupts will be generated if both are zero */
14006 if ((ec->tx_coalesce_usecs == 0) &&
14007 (ec->tx_max_coalesced_frames == 0))
14008 return -EINVAL;
14009
14010 /* Only copy relevant parameters, ignore all others. */
14011 tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs;
14012 tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs;
14013 tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
14014 tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames;
14015 tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;
14016 tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;
14017 tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;
14018 tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;
14019 tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs;
14020
14021 if (netif_running(dev)) {
14022 tg3_full_lock(tp, 0);
14023 __tg3_set_coalesce(tp, &tp->coal);
14024 tg3_full_unlock(tp);
14025 }
14026 return 0;
14027}
14028
1cbf9eb8
NS		 14029static int tg3_set_eee(struct net_device *dev, struct ethtool_eee *edata)
14030{
14031 struct tg3 *tp = netdev_priv(dev);
14032
14033 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP)) {
14034 netdev_warn(tp->dev, "Board does not support EEE!\n");
14035 return -EOPNOTSUPP;
14036 }
14037
14038 if (edata->advertised != tp->eee.advertised) {
14039 netdev_warn(tp->dev,
14040 "Direct manipulation of EEE advertisement is not supported\n");
14041 return -EINVAL;
14042 }
14043
14044 if (edata->tx_lpi_timer > TG3_CPMU_DBTMR1_LNKIDLE_MAX) {
14045 netdev_warn(tp->dev,
14046 "Maximal Tx Lpi timer supported is %#x(u)\n",
14047 TG3_CPMU_DBTMR1_LNKIDLE_MAX);
14048 return -EINVAL;
14049 }
14050
14051 tp->eee = *edata;
14052
14053 tp->phy_flags |= TG3_PHYFLG_USER_CONFIGURED;
14054 tg3_warn_mgmt_link_flap(tp);
14055
14056 if (netif_running(tp->dev)) {
14057 tg3_full_lock(tp, 0);
14058 tg3_setup_eee(tp);
14059 tg3_phy_reset(tp);
14060 tg3_full_unlock(tp);
14061 }
14062
14063 return 0;
14064}
14065
14066static int tg3_get_eee(struct net_device *dev, struct ethtool_eee *edata)
14067{
14068 struct tg3 *tp = netdev_priv(dev);
14069
14070 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP)) {
14071 netdev_warn(tp->dev,
14072 "Board does not support EEE!\n");
14073 return -EOPNOTSUPP;
14074 }
14075
14076 *edata = tp->eee;
14077 return 0;
14078}
14079
7282d491 14080static const struct ethtool_ops tg3_ethtool_ops = {
1da177e4
LT		 14081 .get_settings = tg3_get_settings,
14082 .set_settings = tg3_set_settings,
14083 .get_drvinfo = tg3_get_drvinfo,
14084 .get_regs_len = tg3_get_regs_len,
14085 .get_regs = tg3_get_regs,
14086 .get_wol = tg3_get_wol,
14087 .set_wol = tg3_set_wol,
14088 .get_msglevel = tg3_get_msglevel,
14089 .set_msglevel = tg3_set_msglevel,
14090 .nway_reset = tg3_nway_reset,
14091 .get_link = ethtool_op_get_link,
14092 .get_eeprom_len = tg3_get_eeprom_len,
14093 .get_eeprom = tg3_get_eeprom,
14094 .set_eeprom = tg3_set_eeprom,
14095 .get_ringparam = tg3_get_ringparam,
14096 .set_ringparam = tg3_set_ringparam,
14097 .get_pauseparam = tg3_get_pauseparam,
14098 .set_pauseparam = tg3_set_pauseparam,
4cafd3f5 14099 .self_test = tg3_self_test,
1da177e4 14100 .get_strings = tg3_get_strings,
81b8709c 14101 .set_phys_id = tg3_set_phys_id,
1da177e4 14102 .get_ethtool_stats = tg3_get_ethtool_stats,
15f9850d 14103 .get_coalesce = tg3_get_coalesce,
d244c892 14104 .set_coalesce = tg3_set_coalesce,
b9f2c044 14105 .get_sset_count = tg3_get_sset_count,
90415477
MC		 14106 .get_rxnfc = tg3_get_rxnfc,
14107 .get_rxfh_indir_size = tg3_get_rxfh_indir_size,
fe62d001
BH		 14108 .get_rxfh = tg3_get_rxfh,
14109 .set_rxfh = tg3_set_rxfh,
0968169c
MC		 14110 .get_channels = tg3_get_channels,
14111 .set_channels = tg3_set_channels,
7d41e49a 14112 .get_ts_info = tg3_get_ts_info,
1cbf9eb8
NS		 14113 .get_eee = tg3_get_eee,
14114 .set_eee = tg3_set_eee,
1da177e4
LT		 14115};
14116
b4017c53
DM		 14117static struct rtnl_link_stats64 *tg3_get_stats64(struct net_device *dev,
14118 struct rtnl_link_stats64 *stats)
14119{
14120 struct tg3 *tp = netdev_priv(dev);
14121
0f566b20
MC		 14122 spin_lock_bh(&tp->lock);
14123 if (!tp->hw_stats) {
7b31b4de 14124 *stats = tp->net_stats_prev;
0f566b20 14125 spin_unlock_bh(&tp->lock);
7b31b4de 14126 return stats;
0f566b20 14127 }
b4017c53 14128
b4017c53
DM		 14129 tg3_get_nstats(tp, stats);
14130 spin_unlock_bh(&tp->lock);
14131
14132 return stats;
14133}
14134
ccd5ba9d
MC		 14135static void tg3_set_rx_mode(struct net_device *dev)
14136{
14137 struct tg3 *tp = netdev_priv(dev);
14138
14139 if (!netif_running(dev))
14140 return;
14141
14142 tg3_full_lock(tp, 0);
14143 __tg3_set_rx_mode(dev);
14144 tg3_full_unlock(tp);
14145}
14146
faf1627a
MC		 14147static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
14148 int new_mtu)
14149{
14150 dev->mtu = new_mtu;
14151
14152 if (new_mtu > ETH_DATA_LEN) {
14153 if (tg3_flag(tp, 5780_CLASS)) {
14154 netdev_update_features(dev);
14155 tg3_flag_clear(tp, TSO_CAPABLE);
14156 } else {
14157 tg3_flag_set(tp, JUMBO_RING_ENABLE);
14158 }
14159 } else {
14160 if (tg3_flag(tp, 5780_CLASS)) {
14161 tg3_flag_set(tp, TSO_CAPABLE);
14162 netdev_update_features(dev);
14163 }
14164 tg3_flag_clear(tp, JUMBO_RING_ENABLE);
14165 }
14166}
14167
14168static int tg3_change_mtu(struct net_device *dev, int new_mtu)
14169{
14170 struct tg3 *tp = netdev_priv(dev);
953c96e0
JP		 14171 int err;
14172 bool reset_phy = false;
faf1627a
MC		 14173
14174 if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
14175 return -EINVAL;
14176
14177 if (!netif_running(dev)) {
14178 /* We'll just catch it later when the
14179 * device is up'd.
14180 */
14181 tg3_set_mtu(dev, tp, new_mtu);
14182 return 0;
14183 }
14184
14185 tg3_phy_stop(tp);
14186
14187 tg3_netif_stop(tp);
14188
c6993dfd
NS		 14189 tg3_set_mtu(dev, tp, new_mtu);
14190
faf1627a
MC		 14191 tg3_full_lock(tp, 1);
14192
14193 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
14194
2fae5e36
MC		 14195 /* Reset PHY, otherwise the read DMA engine will be in a mode that
14196 * breaks all requests to 256 bytes.
14197 */
4153577a 14198 if (tg3_asic_rev(tp) == ASIC_REV_57766)
953c96e0 14199 reset_phy = true;
2fae5e36
MC		 14200
14201 err = tg3_restart_hw(tp, reset_phy);
faf1627a
MC		 14202
14203 if (!err)
14204 tg3_netif_start(tp);
14205
14206 tg3_full_unlock(tp);
14207
14208 if (!err)
14209 tg3_phy_start(tp);
14210
14211 return err;
14212}
14213
14214static const struct net_device_ops tg3_netdev_ops = {
14215 .ndo_open = tg3_open,
14216 .ndo_stop = tg3_close,
14217 .ndo_start_xmit = tg3_start_xmit,
14218 .ndo_get_stats64 = tg3_get_stats64,
14219 .ndo_validate_addr = eth_validate_addr,
14220 .ndo_set_rx_mode = tg3_set_rx_mode,
14221 .ndo_set_mac_address = tg3_set_mac_addr,
14222 .ndo_do_ioctl = tg3_ioctl,
14223 .ndo_tx_timeout = tg3_tx_timeout,
14224 .ndo_change_mtu = tg3_change_mtu,
14225 .ndo_fix_features = tg3_fix_features,
14226 .ndo_set_features = tg3_set_features,
14227#ifdef CONFIG_NET_POLL_CONTROLLER
14228 .ndo_poll_controller = tg3_poll_controller,
14229#endif
14230};
14231
229b1ad1 14232static void tg3_get_eeprom_size(struct tg3 *tp)
1da177e4 14233{
1b27777a 14234 u32 cursize, val, magic;
1da177e4
LT		 14235
14236 tp->nvram_size = EEPROM_CHIP_SIZE;
14237
e4f34110 14238 if (tg3_nvram_read(tp, 0, &magic) != 0)
1da177e4
LT		 14239 return;
14240
b16250e3
MC		 14241 if ((magic != TG3_EEPROM_MAGIC) &&
14242 ((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) &&
14243 ((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW))
1da177e4
LT		 14244 return;
14245
14246 /*
14247 * Size the chip by reading offsets at increasing powers of two.
14248 * When we encounter our validation signature, we know the addressing
14249 * has wrapped around, and thus have our chip size.
14250 */
1b27777a 14251 cursize = 0x10;
1da177e4
LT		 14252
14253 while (cursize < tp->nvram_size) {
e4f34110 14254 if (tg3_nvram_read(tp, cursize, &val) != 0)
1da177e4
LT		 14255 return;
14256
1820180b 14257 if (val == magic)
1da177e4
LT		 14258 break;
14259
14260 cursize <<= 1;
14261 }
14262
14263 tp->nvram_size = cursize;
14264}
6aa20a22 14265
229b1ad1 14266static void tg3_get_nvram_size(struct tg3 *tp)
1da177e4
LT		 14267{
14268 u32 val;
14269
63c3a66f 14270 if (tg3_flag(tp, NO_NVRAM) || tg3_nvram_read(tp, 0, &val) != 0)
1b27777a
MC		 14271 return;
14272
14273 /* Selfboot format */
1820180b 14274 if (val != TG3_EEPROM_MAGIC) {
1b27777a
MC		 14275 tg3_get_eeprom_size(tp);
14276 return;
14277 }
14278
6d348f2c 14279 if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
1da177e4 14280 if (val != 0) {
6d348f2c
MC		 14281 /* This is confusing. We want to operate on the
14282 * 16-bit value at offset 0xf2. The tg3_nvram_read()
14283 * call will read from NVRAM and byteswap the data
14284 * according to the byteswapping settings for all
14285 * other register accesses. This ensures the data we
14286 * want will always reside in the lower 16-bits.
14287 * However, the data in NVRAM is in LE format, which
14288 * means the data from the NVRAM read will always be
14289 * opposite the endianness of the CPU. The 16-bit
14290 * byteswap then brings the data to CPU endianness.
14291 */
14292 tp->nvram_size = swab16((u16)(val & 0x0000ffff)) * 1024;
1da177e4
LT		 14293 return;
14294 }
14295 }
fd1122a2 14296 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
1da177e4
LT		 14297}
14298
229b1ad1 14299static void tg3_get_nvram_info(struct tg3 *tp)
1da177e4
LT		 14300{
14301 u32 nvcfg1;
14302
14303 nvcfg1 = tr32(NVRAM_CFG1);
14304 if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
63c3a66f 14305 tg3_flag_set(tp, FLASH);
8590a603 14306 } else {
1da177e4
LT		 14307 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
14308 tw32(NVRAM_CFG1, nvcfg1);
14309 }
14310
4153577a 14311 if (tg3_asic_rev(tp) == ASIC_REV_5750 ||
63c3a66f 14312 tg3_flag(tp, 5780_CLASS)) {
1da177e4 14313 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
8590a603
MC		 14314 case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
14315 tp->nvram_jedecnum = JEDEC_ATMEL;
14316 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
63c3a66f 14317 tg3_flag_set(tp, NVRAM_BUFFERED);
8590a603
MC		 14318 break;
14319 case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
14320 tp->nvram_jedecnum = JEDEC_ATMEL;
14321 tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
14322 break;
14323 case FLASH_VENDOR_ATMEL_EEPROM:
14324 tp->nvram_jedecnum = JEDEC_ATMEL;
14325 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
63c3a66f 14326 tg3_flag_set(tp, NVRAM_BUFFERED);
8590a603
MC		 14327 break;
14328 case FLASH_VENDOR_ST:
14329 tp->nvram_jedecnum = JEDEC_ST;
14330 tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
63c3a66f 14331 tg3_flag_set(tp, NVRAM_BUFFERED);
8590a603
MC		 14332 break;
14333 case FLASH_VENDOR_SAIFUN:
14334 tp->nvram_jedecnum = JEDEC_SAIFUN;
14335 tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
14336 break;
14337 case FLASH_VENDOR_SST_SMALL:
14338 case FLASH_VENDOR_SST_LARGE:
14339 tp->nvram_jedecnum = JEDEC_SST;
14340 tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
14341 break;
1da177e4 14342 }
8590a603 14343 } else {
1da177e4
LT		 14344 tp->nvram_jedecnum = JEDEC_ATMEL;
14345 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
63c3a66f 14346 tg3_flag_set(tp, NVRAM_BUFFERED);
1da177e4
LT		 14347 }
14348}
14349
229b1ad1 14350static void tg3_nvram_get_pagesize(struct tg3 *tp, u32 nvmcfg1)
a1b950d5
MC		 14351{
14352 switch (nvmcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
14353 case FLASH_5752PAGE_SIZE_256:
14354 tp->nvram_pagesize = 256;
14355 break;
14356 case FLASH_5752PAGE_SIZE_512:
14357 tp->nvram_pagesize = 512;
14358 break;
14359 case FLASH_5752PAGE_SIZE_1K:
14360 tp->nvram_pagesize = 1024;
14361 break;
14362 case FLASH_5752PAGE_SIZE_2K:
14363 tp->nvram_pagesize = 2048;
14364 break;
14365 case FLASH_5752PAGE_SIZE_4K:
14366 tp->nvram_pagesize = 4096;
14367 break;
14368 case FLASH_5752PAGE_SIZE_264:
14369 tp->nvram_pagesize = 264;
14370 break;
14371 case FLASH_5752PAGE_SIZE_528:
14372 tp->nvram_pagesize = 528;
14373 break;
14374 }
14375}
14376
229b1ad1 14377static void tg3_get_5752_nvram_info(struct tg3 *tp)
361b4ac2
MC		 14378{
14379 u32 nvcfg1;
14380
14381 nvcfg1 = tr32(NVRAM_CFG1);
14382
e6af301b
MC		 14383 /* NVRAM protection for TPM */
14384 if (nvcfg1 & (1 << 27))
63c3a66f 14385 tg3_flag_set(tp, PROTECTED_NVRAM);
e6af301b 14386
361b4ac2 14387 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
8590a603
MC		 14388 case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
14389 case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
14390 tp->nvram_jedecnum = JEDEC_ATMEL;
63c3a66f 14391 tg3_flag_set(tp, NVRAM_BUFFERED);
8590a603
MC		 14392 break;
14393 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
14394 tp->nvram_jedecnum = JEDEC_ATMEL;
63c3a66f
JP		 14395 tg3_flag_set(tp, NVRAM_BUFFERED);
14396 tg3_flag_set(tp, FLASH);
8590a603
MC		 14397 break;
14398 case FLASH_5752VENDOR_ST_M45PE10:
14399 case FLASH_5752VENDOR_ST_M45PE20:
14400 case FLASH_5752VENDOR_ST_M45PE40:
14401 tp->nvram_jedecnum = JEDEC_ST;
63c3a66f
JP		 14402 tg3_flag_set(tp, NVRAM_BUFFERED);
14403 tg3_flag_set(tp, FLASH);
8590a603 14404 break;
361b4ac2
MC		 14405 }
14406
63c3a66f 14407 if (tg3_flag(tp, FLASH)) {
a1b950d5 14408 tg3_nvram_get_pagesize(tp, nvcfg1);
8590a603 14409 } else {
361b4ac2
MC		 14410 /* For eeprom, set pagesize to maximum eeprom size */
14411 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
14412
14413 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
14414 tw32(NVRAM_CFG1, nvcfg1);
14415 }
14416}
14417
229b1ad1 14418static void tg3_get_5755_nvram_info(struct tg3 *tp)
d3c7b886 14419{
989a9d23 14420 u32 nvcfg1, protect = 0;
d3c7b886
MC		 14421
14422 nvcfg1 = tr32(NVRAM_CFG1);
14423
14424 /* NVRAM protection for TPM */
989a9d23 14425 if (nvcfg1 & (1 << 27)) {
63c3a66f 14426 tg3_flag_set(tp, PROTECTED_NVRAM);
989a9d23
MC		 14427 protect = 1;
14428 }
d3c7b886 14429
989a9d23
MC		 14430 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
14431 switch (nvcfg1) {
8590a603
MC		 14432 case FLASH_5755VENDOR_ATMEL_FLASH_1:
14433 case FLASH_5755VENDOR_ATMEL_FLASH_2:
14434 case FLASH_5755VENDOR_ATMEL_FLASH_3:
14435 case FLASH_5755VENDOR_ATMEL_FLASH_5:
14436 tp->nvram_jedecnum = JEDEC_ATMEL;
63c3a66f
JP		 14437 tg3_flag_set(tp, NVRAM_BUFFERED);
14438 tg3_flag_set(tp, FLASH);
8590a603
MC		 14439 tp->nvram_pagesize = 264;
14440 if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1 ||
14441 nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_5)
14442 tp->nvram_size = (protect ? 0x3e200 :
14443 TG3_NVRAM_SIZE_512KB);
14444 else if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_2)
14445 tp->nvram_size = (protect ? 0x1f200 :
14446 TG3_NVRAM_SIZE_256KB);
14447 else
14448 tp->nvram_size = (protect ? 0x1f200 :
14449 TG3_NVRAM_SIZE_128KB);
14450 break;
14451 case FLASH_5752VENDOR_ST_M45PE10:
14452 case FLASH_5752VENDOR_ST_M45PE20:
14453 case FLASH_5752VENDOR_ST_M45PE40:
14454 tp->nvram_jedecnum = JEDEC_ST;
63c3a66f
JP		 14455 tg3_flag_set(tp, NVRAM_BUFFERED);
14456 tg3_flag_set(tp, FLASH);
8590a603
MC		 14457 tp->nvram_pagesize = 256;
14458 if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE10)
14459 tp->nvram_size = (protect ?
14460 TG3_NVRAM_SIZE_64KB :
14461 TG3_NVRAM_SIZE_128KB);
14462 else if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE20)
14463 tp->nvram_size = (protect ?
14464 TG3_NVRAM_SIZE_64KB :
14465 TG3_NVRAM_SIZE_256KB);
14466 else
14467 tp->nvram_size = (protect ?
14468 TG3_NVRAM_SIZE_128KB :
14469 TG3_NVRAM_SIZE_512KB);
14470 break;
d3c7b886
MC		 14471 }
14472}
14473
229b1ad1 14474static void tg3_get_5787_nvram_info(struct tg3 *tp)
1b27777a
MC		 14475{
14476 u32 nvcfg1;
14477
14478 nvcfg1 = tr32(NVRAM_CFG1);
14479
14480 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
8590a603
MC		 14481 case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ:
14482 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
14483 case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ:
14484 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
14485 tp->nvram_jedecnum = JEDEC_ATMEL;
63c3a66f 14486 tg3_flag_set(tp, NVRAM_BUFFERED);
8590a603 14487 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
1b27777a 14488
8590a603
MC		 14489 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
14490 tw32(NVRAM_CFG1, nvcfg1);
14491 break;
14492 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
14493 case FLASH_5755VENDOR_ATMEL_FLASH_1:
14494 case FLASH_5755VENDOR_ATMEL_FLASH_2:
14495 case FLASH_5755VENDOR_ATMEL_FLASH_3:
14496 tp->nvram_jedecnum = JEDEC_ATMEL;
63c3a66f
JP		 14497 tg3_flag_set(tp, NVRAM_BUFFERED);
14498 tg3_flag_set(tp, FLASH);
8590a603
MC		 14499 tp->nvram_pagesize = 264;
14500 break;
14501 case FLASH_5752VENDOR_ST_M45PE10:
14502 case FLASH_5752VENDOR_ST_M45PE20:
14503 case FLASH_5752VENDOR_ST_M45PE40:
14504 tp->nvram_jedecnum = JEDEC_ST;
63c3a66f
JP		 14505 tg3_flag_set(tp, NVRAM_BUFFERED);
14506 tg3_flag_set(tp, FLASH);
8590a603
MC		 14507 tp->nvram_pagesize = 256;
14508 break;
1b27777a
MC		 14509 }
14510}
14511
229b1ad1 14512static void tg3_get_5761_nvram_info(struct tg3 *tp)
6b91fa02
MC		 14513{
14514 u32 nvcfg1, protect = 0;
14515
14516 nvcfg1 = tr32(NVRAM_CFG1);
14517
14518 /* NVRAM protection for TPM */
14519 if (nvcfg1 & (1 << 27)) {
63c3a66f 14520 tg3_flag_set(tp, PROTECTED_NVRAM);
6b91fa02
MC		 14521 protect = 1;
14522 }
14523
14524 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
14525 switch (nvcfg1) {
8590a603
MC		 14526 case FLASH_5761VENDOR_ATMEL_ADB021D:
14527 case FLASH_5761VENDOR_ATMEL_ADB041D:
14528 case FLASH_5761VENDOR_ATMEL_ADB081D:
14529 case FLASH_5761VENDOR_ATMEL_ADB161D:
14530 case FLASH_5761VENDOR_ATMEL_MDB021D:
14531 case FLASH_5761VENDOR_ATMEL_MDB041D:
14532 case FLASH_5761VENDOR_ATMEL_MDB081D:
14533 case FLASH_5761VENDOR_ATMEL_MDB161D:
14534 tp->nvram_jedecnum = JEDEC_ATMEL;
63c3a66f
JP		 14535 tg3_flag_set(tp, NVRAM_BUFFERED);
14536 tg3_flag_set(tp, FLASH);
14537 tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS);
8590a603
MC		 14538 tp->nvram_pagesize = 256;
14539 break;
14540 case FLASH_5761VENDOR_ST_A_M45PE20:
14541 case FLASH_5761VENDOR_ST_A_M45PE40:
14542 case FLASH_5761VENDOR_ST_A_M45PE80:
14543 case FLASH_5761VENDOR_ST_A_M45PE16:
14544 case FLASH_5761VENDOR_ST_M_M45PE20:
14545 case FLASH_5761VENDOR_ST_M_M45PE40:
14546 case FLASH_5761VENDOR_ST_M_M45PE80:
14547 case FLASH_5761VENDOR_ST_M_M45PE16:
14548 tp->nvram_jedecnum = JEDEC_ST;
63c3a66f
JP		 14549 tg3_flag_set(tp, NVRAM_BUFFERED);
14550 tg3_flag_set(tp, FLASH);
8590a603
MC		 14551 tp->nvram_pagesize = 256;
14552 break;
6b91fa02
MC		 14553 }
14554
14555 if (protect) {
14556 tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT);
14557 } else {
14558 switch (nvcfg1) {
8590a603
MC		 14559 case FLASH_5761VENDOR_ATMEL_ADB161D:
14560 case FLASH_5761VENDOR_ATMEL_MDB161D:
14561 case FLASH_5761VENDOR_ST_A_M45PE16:
14562 case FLASH_5761VENDOR_ST_M_M45PE16:
14563 tp->nvram_size = TG3_NVRAM_SIZE_2MB;
14564 break;
14565 case FLASH_5761VENDOR_ATMEL_ADB081D:
14566 case FLASH_5761VENDOR_ATMEL_MDB081D:
14567 case FLASH_5761VENDOR_ST_A_M45PE80:
14568 case FLASH_5761VENDOR_ST_M_M45PE80:
14569 tp->nvram_size = TG3_NVRAM_SIZE_1MB;
14570 break;
14571 case FLASH_5761VENDOR_ATMEL_ADB041D:
14572 case FLASH_5761VENDOR_ATMEL_MDB041D:
14573 case FLASH_5761VENDOR_ST_A_M45PE40:
14574 case FLASH_5761VENDOR_ST_M_M45PE40:
14575 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
14576 break;
14577 case FLASH_5761VENDOR_ATMEL_ADB021D:
14578 case FLASH_5761VENDOR_ATMEL_MDB021D:
14579 case FLASH_5761VENDOR_ST_A_M45PE20:
14580 case FLASH_5761VENDOR_ST_M_M45PE20:
14581 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
14582 break;
6b91fa02
MC		 14583 }
14584 }
14585}
14586
229b1ad1 14587static void tg3_get_5906_nvram_info(struct tg3 *tp)
b5d3772c
MC		 14588{
14589 tp->nvram_jedecnum = JEDEC_ATMEL;
63c3a66f 14590 tg3_flag_set(tp, NVRAM_BUFFERED);
b5d3772c
MC		 14591 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
14592}
14593
229b1ad1 14594static void tg3_get_57780_nvram_info(struct tg3 *tp)
321d32a0
MC		 14595{
14596 u32 nvcfg1;
14597
14598 nvcfg1 = tr32(NVRAM_CFG1);
14599
14600 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
14601 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
14602 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
14603 tp->nvram_jedecnum = JEDEC_ATMEL;
63c3a66f 14604 tg3_flag_set(tp, NVRAM_BUFFERED);
321d32a0
MC		 14605 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
14606
14607 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
14608 tw32(NVRAM_CFG1, nvcfg1);
14609 return;
14610 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
14611 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
14612 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
14613 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
14614 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
14615 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
14616 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
14617 tp->nvram_jedecnum = JEDEC_ATMEL;
63c3a66f
JP		 14618 tg3_flag_set(tp, NVRAM_BUFFERED);
14619 tg3_flag_set(tp, FLASH);
321d32a0
MC		 14620
14621 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
14622 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
14623 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
14624 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
14625 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
14626 break;
14627 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
14628 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
14629 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
14630 break;
14631 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
14632 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
14633 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
14634 break;
14635 }
14636 break;
14637 case FLASH_5752VENDOR_ST_M45PE10:
14638 case FLASH_5752VENDOR_ST_M45PE20:
14639 case FLASH_5752VENDOR_ST_M45PE40:
14640 tp->nvram_jedecnum = JEDEC_ST;
63c3a66f
JP		 14641 tg3_flag_set(tp, NVRAM_BUFFERED);
14642 tg3_flag_set(tp, FLASH);
321d32a0
MC		 14643
14644 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
14645 case FLASH_5752VENDOR_ST_M45PE10:
14646 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
14647 break;
14648 case FLASH_5752VENDOR_ST_M45PE20:
14649 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
14650 break;
14651 case FLASH_5752VENDOR_ST_M45PE40:
14652 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
14653 break;
14654 }
14655 break;
14656 default:
63c3a66f 14657 tg3_flag_set(tp, NO_NVRAM);
321d32a0
MC		 14658 return;
14659 }
14660
a1b950d5
MC		 14661 tg3_nvram_get_pagesize(tp, nvcfg1);
14662 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
63c3a66f 14663 tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS);
a1b950d5
MC		 14664}
14665
14666
229b1ad1 14667static void tg3_get_5717_nvram_info(struct tg3 *tp)
a1b950d5
MC		 14668{
14669 u32 nvcfg1;
14670
14671 nvcfg1 = tr32(NVRAM_CFG1);
14672
14673 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
14674 case FLASH_5717VENDOR_ATMEL_EEPROM:
14675 case FLASH_5717VENDOR_MICRO_EEPROM:
14676 tp->nvram_jedecnum = JEDEC_ATMEL;
63c3a66f 14677 tg3_flag_set(tp, NVRAM_BUFFERED);
a1b950d5
MC		 14678 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
14679
14680 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
14681 tw32(NVRAM_CFG1, nvcfg1);
14682 return;
14683 case FLASH_5717VENDOR_ATMEL_MDB011D:
14684 case FLASH_5717VENDOR_ATMEL_ADB011B:
14685 case FLASH_5717VENDOR_ATMEL_ADB011D:
14686 case FLASH_5717VENDOR_ATMEL_MDB021D:
14687 case FLASH_5717VENDOR_ATMEL_ADB021B:
14688 case FLASH_5717VENDOR_ATMEL_ADB021D:
14689 case FLASH_5717VENDOR_ATMEL_45USPT:
14690 tp->nvram_jedecnum = JEDEC_ATMEL;
63c3a66f
JP		 14691 tg3_flag_set(tp, NVRAM_BUFFERED);
14692 tg3_flag_set(tp, FLASH);
a1b950d5
MC		 14693
14694 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
14695 case FLASH_5717VENDOR_ATMEL_MDB021D:
66ee33bf
MC		 14696 /* Detect size with tg3_nvram_get_size() */
14697 break;
a1b950d5
MC		 14698 case FLASH_5717VENDOR_ATMEL_ADB021B:
14699 case FLASH_5717VENDOR_ATMEL_ADB021D:
14700 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
14701 break;
14702 default:
14703 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
14704 break;
14705 }
321d32a0 14706 break;
a1b950d5
MC		 14707 case FLASH_5717VENDOR_ST_M_M25PE10:
14708 case FLASH_5717VENDOR_ST_A_M25PE10:
14709 case FLASH_5717VENDOR_ST_M_M45PE10:
14710 case FLASH_5717VENDOR_ST_A_M45PE10:
14711 case FLASH_5717VENDOR_ST_M_M25PE20:
14712 case FLASH_5717VENDOR_ST_A_M25PE20:
14713 case FLASH_5717VENDOR_ST_M_M45PE20:
14714 case FLASH_5717VENDOR_ST_A_M45PE20:
14715 case FLASH_5717VENDOR_ST_25USPT:
14716 case FLASH_5717VENDOR_ST_45USPT:
14717 tp->nvram_jedecnum = JEDEC_ST;
63c3a66f
JP		 14718 tg3_flag_set(tp, NVRAM_BUFFERED);
14719 tg3_flag_set(tp, FLASH);
a1b950d5
MC		 14720
14721 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
14722 case FLASH_5717VENDOR_ST_M_M25PE20:
a1b950d5 14723 case FLASH_5717VENDOR_ST_M_M45PE20:
66ee33bf
MC		 14724 /* Detect size with tg3_nvram_get_size() */
14725 break;
14726 case FLASH_5717VENDOR_ST_A_M25PE20:
a1b950d5
MC		 14727 case FLASH_5717VENDOR_ST_A_M45PE20:
14728 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
14729 break;
14730 default:
14731 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
14732 break;
14733 }
321d32a0 14734 break;
a1b950d5 14735 default:
63c3a66f 14736 tg3_flag_set(tp, NO_NVRAM);
a1b950d5 14737 return;
321d32a0 14738 }
a1b950d5
MC		 14739
14740 tg3_nvram_get_pagesize(tp, nvcfg1);
14741 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
63c3a66f 14742 tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS);
321d32a0
MC		 14743}
14744
229b1ad1 14745static void tg3_get_5720_nvram_info(struct tg3 *tp)
9b91b5f1
MC		 14746{
14747 u32 nvcfg1, nvmpinstrp;
14748
14749 nvcfg1 = tr32(NVRAM_CFG1);
14750 nvmpinstrp = nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK;
14751
4153577a 14752 if (tg3_asic_rev(tp) == ASIC_REV_5762) {
c86a8560
MC		 14753 if (!(nvcfg1 & NVRAM_CFG1_5762VENDOR_MASK)) {
14754 tg3_flag_set(tp, NO_NVRAM);
14755 return;
14756 }
14757
14758 switch (nvmpinstrp) {
14759 case FLASH_5762_EEPROM_HD:
14760 nvmpinstrp = FLASH_5720_EEPROM_HD;
17e1a42f 14761 break;
c86a8560
MC		 14762 case FLASH_5762_EEPROM_LD:
14763 nvmpinstrp = FLASH_5720_EEPROM_LD;
17e1a42f 14764 break;
f6334bb8
MC		 14765 case FLASH_5720VENDOR_M_ST_M45PE20:
14766 /* This pinstrap supports multiple sizes, so force it
14767 * to read the actual size from location 0xf0.
14768 */
14769 nvmpinstrp = FLASH_5720VENDOR_ST_45USPT;
14770 break;
c86a8560
MC		 14771 }
14772 }
14773
9b91b5f1
MC		 14774 switch (nvmpinstrp) {
14775 case FLASH_5720_EEPROM_HD:
14776 case FLASH_5720_EEPROM_LD:
14777 tp->nvram_jedecnum = JEDEC_ATMEL;
63c3a66f 14778 tg3_flag_set(tp, NVRAM_BUFFERED);
9b91b5f1
MC		 14779
14780 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
14781 tw32(NVRAM_CFG1, nvcfg1);
14782 if (nvmpinstrp == FLASH_5720_EEPROM_HD)
14783 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
14784 else
14785 tp->nvram_pagesize = ATMEL_AT24C02_CHIP_SIZE;
14786 return;
14787 case FLASH_5720VENDOR_M_ATMEL_DB011D:
14788 case FLASH_5720VENDOR_A_ATMEL_DB011B:
14789 case FLASH_5720VENDOR_A_ATMEL_DB011D:
14790 case FLASH_5720VENDOR_M_ATMEL_DB021D:
14791 case FLASH_5720VENDOR_A_ATMEL_DB021B:
14792 case FLASH_5720VENDOR_A_ATMEL_DB021D:
14793 case FLASH_5720VENDOR_M_ATMEL_DB041D:
14794 case FLASH_5720VENDOR_A_ATMEL_DB041B:
14795 case FLASH_5720VENDOR_A_ATMEL_DB041D:
14796 case FLASH_5720VENDOR_M_ATMEL_DB081D:
14797 case FLASH_5720VENDOR_A_ATMEL_DB081D:
14798 case FLASH_5720VENDOR_ATMEL_45USPT:
14799 tp->nvram_jedecnum = JEDEC_ATMEL;
63c3a66f
JP		 14800 tg3_flag_set(tp, NVRAM_BUFFERED);
14801 tg3_flag_set(tp, FLASH);
9b91b5f1
MC		 14802
14803 switch (nvmpinstrp) {
14804 case FLASH_5720VENDOR_M_ATMEL_DB021D:
14805 case FLASH_5720VENDOR_A_ATMEL_DB021B:
14806 case FLASH_5720VENDOR_A_ATMEL_DB021D:
14807 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
14808 break;
14809 case FLASH_5720VENDOR_M_ATMEL_DB041D:
14810 case FLASH_5720VENDOR_A_ATMEL_DB041B:
14811 case FLASH_5720VENDOR_A_ATMEL_DB041D:
14812 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
14813 break;
14814 case FLASH_5720VENDOR_M_ATMEL_DB081D:
14815 case FLASH_5720VENDOR_A_ATMEL_DB081D:
14816 tp->nvram_size = TG3_NVRAM_SIZE_1MB;
14817 break;
14818 default:
4153577a 14819 if (tg3_asic_rev(tp) != ASIC_REV_5762)
c5d0b72e 14820 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
9b91b5f1
MC		 14821 break;
14822 }
14823 break;
14824 case FLASH_5720VENDOR_M_ST_M25PE10:
14825 case FLASH_5720VENDOR_M_ST_M45PE10:
14826 case FLASH_5720VENDOR_A_ST_M25PE10:
14827 case FLASH_5720VENDOR_A_ST_M45PE10:
14828 case FLASH_5720VENDOR_M_ST_M25PE20:
14829 case FLASH_5720VENDOR_M_ST_M45PE20:
14830 case FLASH_5720VENDOR_A_ST_M25PE20:
14831 case FLASH_5720VENDOR_A_ST_M45PE20:
14832 case FLASH_5720VENDOR_M_ST_M25PE40:
14833 case FLASH_5720VENDOR_M_ST_M45PE40:
14834 case FLASH_5720VENDOR_A_ST_M25PE40:
14835 case FLASH_5720VENDOR_A_ST_M45PE40:
14836 case FLASH_5720VENDOR_M_ST_M25PE80:
14837 case FLASH_5720VENDOR_M_ST_M45PE80:
14838 case FLASH_5720VENDOR_A_ST_M25PE80:
14839 case FLASH_5720VENDOR_A_ST_M45PE80:
14840 case FLASH_5720VENDOR_ST_25USPT:
14841 case FLASH_5720VENDOR_ST_45USPT:
14842 tp->nvram_jedecnum = JEDEC_ST;
63c3a66f
JP		 14843 tg3_flag_set(tp, NVRAM_BUFFERED);
14844 tg3_flag_set(tp, FLASH);
9b91b5f1
MC		 14845
14846 switch (nvmpinstrp) {
14847 case FLASH_5720VENDOR_M_ST_M25PE20:
14848 case FLASH_5720VENDOR_M_ST_M45PE20:
14849 case FLASH_5720VENDOR_A_ST_M25PE20:
14850 case FLASH_5720VENDOR_A_ST_M45PE20:
14851 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
14852 break;
14853 case FLASH_5720VENDOR_M_ST_M25PE40:
14854 case FLASH_5720VENDOR_M_ST_M45PE40:
14855 case FLASH_5720VENDOR_A_ST_M25PE40:
14856 case FLASH_5720VENDOR_A_ST_M45PE40:
14857 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
14858 break;
14859 case FLASH_5720VENDOR_M_ST_M25PE80:
14860 case FLASH_5720VENDOR_M_ST_M45PE80:
14861 case FLASH_5720VENDOR_A_ST_M25PE80:
14862 case FLASH_5720VENDOR_A_ST_M45PE80:
14863 tp->nvram_size = TG3_NVRAM_SIZE_1MB;
14864 break;
14865 default:
4153577a 14866 if (tg3_asic_rev(tp) != ASIC_REV_5762)
c5d0b72e 14867 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
9b91b5f1
MC		 14868 break;
14869 }
14870 break;
14871 default:
63c3a66f 14872 tg3_flag_set(tp, NO_NVRAM);
9b91b5f1
MC		 14873 return;
14874 }
14875
14876 tg3_nvram_get_pagesize(tp, nvcfg1);
14877 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
63c3a66f 14878 tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS);
c86a8560 14879
4153577a 14880 if (tg3_asic_rev(tp) == ASIC_REV_5762) {
c86a8560
MC		 14881 u32 val;
14882
14883 if (tg3_nvram_read(tp, 0, &val))
14884 return;
14885
14886 if (val != TG3_EEPROM_MAGIC &&
14887 (val & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW)
14888 tg3_flag_set(tp, NO_NVRAM);
14889 }
9b91b5f1
MC		 14890}
14891
1da177e4 14892/* Chips other than 5700/5701 use the NVRAM for fetching info. */
229b1ad1 14893static void tg3_nvram_init(struct tg3 *tp)
1da177e4 14894{
7e6c63f0
HM		 14895 if (tg3_flag(tp, IS_SSB_CORE)) {
14896 /* No NVRAM and EEPROM on the SSB Broadcom GigE core. */
14897 tg3_flag_clear(tp, NVRAM);
14898 tg3_flag_clear(tp, NVRAM_BUFFERED);
14899 tg3_flag_set(tp, NO_NVRAM);
14900 return;
14901 }
14902
1da177e4
LT		 14903 tw32_f(GRC_EEPROM_ADDR,
14904 (EEPROM_ADDR_FSM_RESET |
14905 (EEPROM_DEFAULT_CLOCK_PERIOD <<
14906 EEPROM_ADDR_CLKPERD_SHIFT)));
14907
9d57f01c 14908 msleep(1);
1da177e4
LT		 14909
14910 /* Enable seeprom accesses. */
14911 tw32_f(GRC_LOCAL_CTRL,
14912 tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
14913 udelay(100);
14914
4153577a
JP		 14915 if (tg3_asic_rev(tp) != ASIC_REV_5700 &&
14916 tg3_asic_rev(tp) != ASIC_REV_5701) {
63c3a66f 14917 tg3_flag_set(tp, NVRAM);
1da177e4 14918
ec41c7df 14919 if (tg3_nvram_lock(tp)) {
5129c3a3
MC		 14920 netdev_warn(tp->dev,
14921 "Cannot get nvram lock, %s failed\n",
05dbe005 14922 __func__);
ec41c7df
MC		 14923 return;
14924 }
e6af301b 14925 tg3_enable_nvram_access(tp);
1da177e4 14926
989a9d23
MC		 14927 tp->nvram_size = 0;
14928
4153577a 14929 if (tg3_asic_rev(tp) == ASIC_REV_5752)
361b4ac2 14930 tg3_get_5752_nvram_info(tp);
4153577a 14931 else if (tg3_asic_rev(tp) == ASIC_REV_5755)
d3c7b886 14932 tg3_get_5755_nvram_info(tp);
4153577a
JP		 14933 else if (tg3_asic_rev(tp) == ASIC_REV_5787 ||
14934 tg3_asic_rev(tp) == ASIC_REV_5784 ||
14935 tg3_asic_rev(tp) == ASIC_REV_5785)
1b27777a 14936 tg3_get_5787_nvram_info(tp);
4153577a 14937 else if (tg3_asic_rev(tp) == ASIC_REV_5761)
6b91fa02 14938 tg3_get_5761_nvram_info(tp);
4153577a 14939 else if (tg3_asic_rev(tp) == ASIC_REV_5906)
b5d3772c 14940 tg3_get_5906_nvram_info(tp);
4153577a 14941 else if (tg3_asic_rev(tp) == ASIC_REV_57780 ||
55086ad9 14942 tg3_flag(tp, 57765_CLASS))
321d32a0 14943 tg3_get_57780_nvram_info(tp);
4153577a
JP		 14944 else if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
14945 tg3_asic_rev(tp) == ASIC_REV_5719)
a1b950d5 14946 tg3_get_5717_nvram_info(tp);
4153577a
JP		 14947 else if (tg3_asic_rev(tp) == ASIC_REV_5720 ||
14948 tg3_asic_rev(tp) == ASIC_REV_5762)
9b91b5f1 14949 tg3_get_5720_nvram_info(tp);
361b4ac2
MC		 14950 else
14951 tg3_get_nvram_info(tp);
14952
989a9d23
MC		 14953 if (tp->nvram_size == 0)
14954 tg3_get_nvram_size(tp);
1da177e4 14955
e6af301b 14956 tg3_disable_nvram_access(tp);
381291b7 14957 tg3_nvram_unlock(tp);
1da177e4
LT		 14958
14959 } else {
63c3a66f
JP		 14960 tg3_flag_clear(tp, NVRAM);
14961 tg3_flag_clear(tp, NVRAM_BUFFERED);
1da177e4
LT		 14962
14963 tg3_get_eeprom_size(tp);
14964 }
14965}
14966
1da177e4
LT		 14967struct subsys_tbl_ent {
14968 u16 subsys_vendor, subsys_devid;
14969 u32 phy_id;
14970};
14971
229b1ad1 14972static struct subsys_tbl_ent subsys_id_to_phy_id[] = {
1da177e4 14973 /* Broadcom boards. */
24daf2b0 14974 { TG3PCI_SUBVENDOR_ID_BROADCOM,
79eb6904 14975 TG3PCI_SUBDEVICE_ID_BROADCOM_95700A6, TG3_PHY_ID_BCM5401 },
24daf2b0 14976 { TG3PCI_SUBVENDOR_ID_BROADCOM,
79eb6904 14977 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A5, TG3_PHY_ID_BCM5701 },
24daf2b0 14978 { TG3PCI_SUBVENDOR_ID_BROADCOM,
79eb6904 14979 TG3PCI_SUBDEVICE_ID_BROADCOM_95700T6, TG3_PHY_ID_BCM8002 },
24daf2b0
MC		 14980 { TG3PCI_SUBVENDOR_ID_BROADCOM,
14981 TG3PCI_SUBDEVICE_ID_BROADCOM_95700A9, 0 },
14982 { TG3PCI_SUBVENDOR_ID_BROADCOM,
79eb6904 14983 TG3PCI_SUBDEVICE_ID_BROADCOM_95701T1, TG3_PHY_ID_BCM5701 },
24daf2b0 14984 { TG3PCI_SUBVENDOR_ID_BROADCOM,
79eb6904 14985 TG3PCI_SUBDEVICE_ID_BROADCOM_95701T8, TG3_PHY_ID_BCM5701 },
24daf2b0
MC		 14986 { TG3PCI_SUBVENDOR_ID_BROADCOM,
14987 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A7, 0 },
14988 { TG3PCI_SUBVENDOR_ID_BROADCOM,
79eb6904 14989 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A10, TG3_PHY_ID_BCM5701 },
24daf2b0 14990 { TG3PCI_SUBVENDOR_ID_BROADCOM,
79eb6904 14991 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A12, TG3_PHY_ID_BCM5701 },
24daf2b0 14992 { TG3PCI_SUBVENDOR_ID_BROADCOM,
79eb6904 14993 TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX1, TG3_PHY_ID_BCM5703 },
24daf2b0 14994 { TG3PCI_SUBVENDOR_ID_BROADCOM,
79eb6904 14995 TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX2, TG3_PHY_ID_BCM5703 },
1da177e4
LT		 14996
14997 /* 3com boards. */
24daf2b0 14998 { TG3PCI_SUBVENDOR_ID_3COM,
79eb6904 14999 TG3PCI_SUBDEVICE_ID_3COM_3C996T, TG3_PHY_ID_BCM5401 },
24daf2b0 15000 { TG3PCI_SUBVENDOR_ID_3COM,
79eb6904 15001 TG3PCI_SUBDEVICE_ID_3COM_3C996BT, TG3_PHY_ID_BCM5701 },
24daf2b0
MC		 15002 { TG3PCI_SUBVENDOR_ID_3COM,
15003 TG3PCI_SUBDEVICE_ID_3COM_3C996SX, 0 },
15004 { TG3PCI_SUBVENDOR_ID_3COM,
79eb6904 15005 TG3PCI_SUBDEVICE_ID_3COM_3C1000T, TG3_PHY_ID_BCM5701 },
24daf2b0 15006 { TG3PCI_SUBVENDOR_ID_3COM,
79eb6904 15007 TG3PCI_SUBDEVICE_ID_3COM_3C940BR01, TG3_PHY_ID_BCM5701 },
1da177e4
LT		 15008
15009 /* DELL boards. */
24daf2b0 15010 { TG3PCI_SUBVENDOR_ID_DELL,
79eb6904 15011 TG3PCI_SUBDEVICE_ID_DELL_VIPER, TG3_PHY_ID_BCM5401 },
24daf2b0 15012 { TG3PCI_SUBVENDOR_ID_DELL,
79eb6904 15013 TG3PCI_SUBDEVICE_ID_DELL_JAGUAR, TG3_PHY_ID_BCM5401 },
24daf2b0 15014 { TG3PCI_SUBVENDOR_ID_DELL,
79eb6904 15015 TG3PCI_SUBDEVICE_ID_DELL_MERLOT, TG3_PHY_ID_BCM5411 },
24daf2b0 15016 { TG3PCI_SUBVENDOR_ID_DELL,
79eb6904 15017 TG3PCI_SUBDEVICE_ID_DELL_SLIM_MERLOT, TG3_PHY_ID_BCM5411 },
1da177e4
LT		 15018
15019 /* Compaq boards. */
24daf2b0 15020 { TG3PCI_SUBVENDOR_ID_COMPAQ,
79eb6904 15021 TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE, TG3_PHY_ID_BCM5701 },
24daf2b0 15022 { TG3PCI_SUBVENDOR_ID_COMPAQ,
79eb6904 15023 TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE_2, TG3_PHY_ID_BCM5701 },
24daf2b0
MC		 15024 { TG3PCI_SUBVENDOR_ID_COMPAQ,
15025 TG3PCI_SUBDEVICE_ID_COMPAQ_CHANGELING, 0 },
15026 { TG3PCI_SUBVENDOR_ID_COMPAQ,
79eb6904 15027 TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780, TG3_PHY_ID_BCM5701 },
24daf2b0 15028 { TG3PCI_SUBVENDOR_ID_COMPAQ,
79eb6904 15029 TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780_2, TG3_PHY_ID_BCM5701 },
1da177e4
LT		 15030
15031 /* IBM boards. */
24daf2b0
MC		 15032 { TG3PCI_SUBVENDOR_ID_IBM,
15033 TG3PCI_SUBDEVICE_ID_IBM_5703SAX2, 0 }
1da177e4
LT		 15034};
15035
229b1ad1 15036static struct subsys_tbl_ent *tg3_lookup_by_subsys(struct tg3 *tp)
1da177e4
LT		 15037{
15038 int i;
15039
15040 for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
15041 if ((subsys_id_to_phy_id[i].subsys_vendor ==
15042 tp->pdev->subsystem_vendor) &&
15043 (subsys_id_to_phy_id[i].subsys_devid ==
15044 tp->pdev->subsystem_device))
15045 return &subsys_id_to_phy_id[i];
15046 }
15047 return NULL;
15048}
15049
229b1ad1 15050static void tg3_get_eeprom_hw_cfg(struct tg3 *tp)
1da177e4 15051{
1da177e4 15052 u32 val;
f49639e6 15053
79eb6904 15054 tp->phy_id = TG3_PHY_ID_INVALID;
7d0c41ef
MC		 15055 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
15056
a85feb8c 15057 /* Assume an onboard device and WOL capable by default. */
63c3a66f
JP		 15058 tg3_flag_set(tp, EEPROM_WRITE_PROT);
15059 tg3_flag_set(tp, WOL_CAP);
72b845e0 15060
4153577a 15061 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
9d26e213 15062 if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) {
63c3a66f
JP		 15063 tg3_flag_clear(tp, EEPROM_WRITE_PROT);
15064 tg3_flag_set(tp, IS_NIC);
9d26e213 15065 }
0527ba35
MC		 15066 val = tr32(VCPU_CFGSHDW);
15067 if (val & VCPU_CFGSHDW_ASPM_DBNC)
63c3a66f 15068 tg3_flag_set(tp, ASPM_WORKAROUND);
0527ba35 15069 if ((val & VCPU_CFGSHDW_WOL_ENABLE) &&
6fdbab9d 15070 (val & VCPU_CFGSHDW_WOL_MAGPKT)) {
63c3a66f 15071 tg3_flag_set(tp, WOL_ENABLE);
6fdbab9d
RW		 15072 device_set_wakeup_enable(&tp->pdev->dev, true);
15073 }
05ac4cb7 15074 goto done;
b5d3772c
MC		 15075 }
15076
1da177e4
LT		 15077 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
15078 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
15079 u32 nic_cfg, led_cfg;
7c786065
NS		 15080 u32 cfg2 = 0, cfg4 = 0, cfg5 = 0;
15081 u32 nic_phy_id, ver, eeprom_phy_id;
7d0c41ef 15082 int eeprom_phy_serdes = 0;
1da177e4
LT		 15083
15084 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
15085 tp->nic_sram_data_cfg = nic_cfg;
15086
15087 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
15088 ver >>= NIC_SRAM_DATA_VER_SHIFT;
4153577a
JP		 15089 if (tg3_asic_rev(tp) != ASIC_REV_5700 &&
15090 tg3_asic_rev(tp) != ASIC_REV_5701 &&
15091 tg3_asic_rev(tp) != ASIC_REV_5703 &&
1da177e4
LT		 15092 (ver > 0) && (ver < 0x100))
15093 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
15094
4153577a 15095 if (tg3_asic_rev(tp) == ASIC_REV_5785)
a9daf367
MC		 15096 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_4, &cfg4);
15097
7c786065
NS		 15098 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
15099 tg3_asic_rev(tp) == ASIC_REV_5719 ||
15100 tg3_asic_rev(tp) == ASIC_REV_5720)
15101 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_5, &cfg5);
15102
1da177e4
LT		 15103 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
15104 NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
15105 eeprom_phy_serdes = 1;
15106
15107 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
15108 if (nic_phy_id != 0) {
15109 u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
15110 u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
15111
15112 eeprom_phy_id = (id1 >> 16) << 10;
15113 eeprom_phy_id |= (id2 & 0xfc00) << 16;
15114 eeprom_phy_id |= (id2 & 0x03ff) << 0;
15115 } else
15116 eeprom_phy_id = 0;
15117
7d0c41ef 15118 tp->phy_id = eeprom_phy_id;
747e8f8b 15119 if (eeprom_phy_serdes) {
63c3a66f 15120 if (!tg3_flag(tp, 5705_PLUS))
f07e9af3 15121 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
a50d0796 15122 else
f07e9af3 15123 tp->phy_flags |= TG3_PHYFLG_MII_SERDES;
747e8f8b 15124 }
7d0c41ef 15125
63c3a66f 15126 if (tg3_flag(tp, 5750_PLUS))
1da177e4
LT		 15127 led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
15128 SHASTA_EXT_LED_MODE_MASK);
cbf46853 15129 else
1da177e4
LT		 15130 led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
15131
15132 switch (led_cfg) {
15133 default:
15134 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
15135 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
15136 break;
15137
15138 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
15139 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
15140 break;
15141
15142 case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
15143 tp->led_ctrl = LED_CTRL_MODE_MAC;
9ba27794
MC		 15144
15145 /* Default to PHY_1_MODE if 0 (MAC_MODE) is
15146 * read on some older 5700/5701 bootcode.
15147 */
4153577a
JP		 15148 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
15149 tg3_asic_rev(tp) == ASIC_REV_5701)
9ba27794
MC		 15150 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
15151
1da177e4
LT		 15152 break;
15153
15154 case SHASTA_EXT_LED_SHARED:
15155 tp->led_ctrl = LED_CTRL_MODE_SHARED;
4153577a
JP		 15156 if (tg3_chip_rev_id(tp) != CHIPREV_ID_5750_A0 &&
15157 tg3_chip_rev_id(tp) != CHIPREV_ID_5750_A1)
1da177e4
LT		 15158 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
15159 LED_CTRL_MODE_PHY_2);
89f67978
NS		 15160
15161 if (tg3_flag(tp, 5717_PLUS) ||
15162 tg3_asic_rev(tp) == ASIC_REV_5762)
15163 tp->led_ctrl |= LED_CTRL_BLINK_RATE_OVERRIDE |
15164 LED_CTRL_BLINK_RATE_MASK;
15165
1da177e4
LT		 15166 break;
15167
15168 case SHASTA_EXT_LED_MAC:
15169 tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
15170 break;
15171
15172 case SHASTA_EXT_LED_COMBO:
15173 tp->led_ctrl = LED_CTRL_MODE_COMBO;
4153577a 15174 if (tg3_chip_rev_id(tp) != CHIPREV_ID_5750_A0)
1da177e4
LT		 15175 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
15176 LED_CTRL_MODE_PHY_2);
15177 break;
15178
855e1111 15179 }
1da177e4 15180
4153577a
JP		 15181 if ((tg3_asic_rev(tp) == ASIC_REV_5700 ||
15182 tg3_asic_rev(tp) == ASIC_REV_5701) &&
1da177e4
LT		 15183 tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
15184 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
15185
4153577a 15186 if (tg3_chip_rev(tp) == CHIPREV_5784_AX)
b2a5c19c 15187 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
5f60891b 15188
9d26e213 15189 if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) {
63c3a66f 15190 tg3_flag_set(tp, EEPROM_WRITE_PROT);
9d26e213
MC		 15191 if ((tp->pdev->subsystem_vendor ==
15192 PCI_VENDOR_ID_ARIMA) &&
15193 (tp->pdev->subsystem_device == 0x205a ||
15194 tp->pdev->subsystem_device == 0x2063))
63c3a66f 15195 tg3_flag_clear(tp, EEPROM_WRITE_PROT);
9d26e213 15196 } else {
63c3a66f
JP		 15197 tg3_flag_clear(tp, EEPROM_WRITE_PROT);
15198 tg3_flag_set(tp, IS_NIC);
9d26e213 15199 }
1da177e4
LT		 15200
15201 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
63c3a66f
JP		 15202 tg3_flag_set(tp, ENABLE_ASF);
15203 if (tg3_flag(tp, 5750_PLUS))
15204 tg3_flag_set(tp, ASF_NEW_HANDSHAKE);
1da177e4 15205 }
b2b98d4a
MC		 15206
15207 if ((nic_cfg & NIC_SRAM_DATA_CFG_APE_ENABLE) &&
63c3a66f
JP		 15208 tg3_flag(tp, 5750_PLUS))
15209 tg3_flag_set(tp, ENABLE_APE);
b2b98d4a 15210
f07e9af3 15211 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES &&
a85feb8c 15212 !(nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL))
63c3a66f 15213 tg3_flag_clear(tp, WOL_CAP);
1da177e4 15214
63c3a66f 15215 if (tg3_flag(tp, WOL_CAP) &&
6fdbab9d 15216 (nic_cfg & NIC_SRAM_DATA_CFG_WOL_ENABLE)) {
63c3a66f 15217 tg3_flag_set(tp, WOL_ENABLE);
6fdbab9d
RW		 15218 device_set_wakeup_enable(&tp->pdev->dev, true);
15219 }
0527ba35 15220
1da177e4 15221 if (cfg2 & (1 << 17))
f07e9af3 15222 tp->phy_flags |= TG3_PHYFLG_CAPACITIVE_COUPLING;
1da177e4
LT		 15223
15224 /* serdes signal pre-emphasis in register 0x590 set by */
15225 /* bootcode if bit 18 is set */
15226 if (cfg2 & (1 << 18))
f07e9af3 15227 tp->phy_flags |= TG3_PHYFLG_SERDES_PREEMPHASIS;
8ed5d97e 15228
63c3a66f 15229 if ((tg3_flag(tp, 57765_PLUS) ||
4153577a
JP		 15230 (tg3_asic_rev(tp) == ASIC_REV_5784 &&
15231 tg3_chip_rev(tp) != CHIPREV_5784_AX)) &&
6833c043 15232 (cfg2 & NIC_SRAM_DATA_CFG_2_APD_EN))
f07e9af3 15233 tp->phy_flags |= TG3_PHYFLG_ENABLE_APD;
6833c043 15234
942d1af0 15235 if (tg3_flag(tp, PCI_EXPRESS)) {
8ed5d97e
MC		 15236 u32 cfg3;
15237
15238 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3);
942d1af0
NS		 15239 if (tg3_asic_rev(tp) != ASIC_REV_5785 &&
15240 !tg3_flag(tp, 57765_PLUS) &&
15241 (cfg3 & NIC_SRAM_ASPM_DEBOUNCE))
63c3a66f 15242 tg3_flag_set(tp, ASPM_WORKAROUND);
942d1af0
NS		 15243 if (cfg3 & NIC_SRAM_LNK_FLAP_AVOID)
15244 tp->phy_flags |= TG3_PHYFLG_KEEP_LINK_ON_PWRDN;
15245 if (cfg3 & NIC_SRAM_1G_ON_VAUX_OK)
15246 tp->phy_flags |= TG3_PHYFLG_1G_ON_VAUX_OK;
8ed5d97e 15247 }
a9daf367 15248
14417063 15249 if (cfg4 & NIC_SRAM_RGMII_INBAND_DISABLE)
63c3a66f 15250 tg3_flag_set(tp, RGMII_INBAND_DISABLE);
a9daf367 15251 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_RX_EN)
63c3a66f 15252 tg3_flag_set(tp, RGMII_EXT_IBND_RX_EN);
a9daf367 15253 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_TX_EN)
63c3a66f 15254 tg3_flag_set(tp, RGMII_EXT_IBND_TX_EN);
7c786065
NS		 15255
15256 if (cfg5 & NIC_SRAM_DISABLE_1G_HALF_ADV)
15257 tp->phy_flags |= TG3_PHYFLG_DISABLE_1G_HD_ADV;
1da177e4 15258 }
05ac4cb7 15259done:
63c3a66f 15260 if (tg3_flag(tp, WOL_CAP))
43067ed8 15261 device_set_wakeup_enable(&tp->pdev->dev,
63c3a66f 15262 tg3_flag(tp, WOL_ENABLE));
43067ed8
RW		 15263 else
15264 device_set_wakeup_capable(&tp->pdev->dev, false);
7d0c41ef
MC		 15265}
15266
c86a8560
MC		 15267static int tg3_ape_otp_read(struct tg3 *tp, u32 offset, u32 *val)
15268{
15269 int i, err;
15270 u32 val2, off = offset * 8;
15271
15272 err = tg3_nvram_lock(tp);
15273 if (err)
15274 return err;
15275
15276 tg3_ape_write32(tp, TG3_APE_OTP_ADDR, off | APE_OTP_ADDR_CPU_ENABLE);
15277 tg3_ape_write32(tp, TG3_APE_OTP_CTRL, APE_OTP_CTRL_PROG_EN |
15278 APE_OTP_CTRL_CMD_RD | APE_OTP_CTRL_START);
15279 tg3_ape_read32(tp, TG3_APE_OTP_CTRL);
15280 udelay(10);
15281
15282 for (i = 0; i < 100; i++) {
15283 val2 = tg3_ape_read32(tp, TG3_APE_OTP_STATUS);
15284 if (val2 & APE_OTP_STATUS_CMD_DONE) {
15285 *val = tg3_ape_read32(tp, TG3_APE_OTP_RD_DATA);
15286 break;
15287 }
15288 udelay(10);
15289 }
15290
15291 tg3_ape_write32(tp, TG3_APE_OTP_CTRL, 0);
15292
15293 tg3_nvram_unlock(tp);
15294 if (val2 & APE_OTP_STATUS_CMD_DONE)
15295 return 0;
15296
15297 return -EBUSY;
15298}
15299
229b1ad1 15300static int tg3_issue_otp_command(struct tg3 *tp, u32 cmd)
b2a5c19c
MC		 15301{
15302 int i;
15303 u32 val;
15304
15305 tw32(OTP_CTRL, cmd | OTP_CTRL_OTP_CMD_START);
15306 tw32(OTP_CTRL, cmd);
15307
15308 /* Wait for up to 1 ms for command to execute. */
15309 for (i = 0; i < 100; i++) {
15310 val = tr32(OTP_STATUS);
15311 if (val & OTP_STATUS_CMD_DONE)
15312 break;
15313 udelay(10);
15314 }
15315
15316 return (val & OTP_STATUS_CMD_DONE) ? 0 : -EBUSY;
15317}
15318
15319/* Read the gphy configuration from the OTP region of the chip. The gphy
15320 * configuration is a 32-bit value that straddles the alignment boundary.
15321 * We do two 32-bit reads and then shift and merge the results.
15322 */
229b1ad1 15323static u32 tg3_read_otp_phycfg(struct tg3 *tp)
b2a5c19c
MC		 15324{
15325 u32 bhalf_otp, thalf_otp;
15326
15327 tw32(OTP_MODE, OTP_MODE_OTP_THRU_GRC);
15328
15329 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_INIT))
15330 return 0;
15331
15332 tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC1);
15333
15334 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
15335 return 0;
15336
15337 thalf_otp = tr32(OTP_READ_DATA);
15338
15339 tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC2);
15340
15341 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
15342 return 0;
15343
15344 bhalf_otp = tr32(OTP_READ_DATA);
15345
15346 return ((thalf_otp & 0x0000ffff) << 16) | (bhalf_otp >> 16);
15347}
15348
229b1ad1 15349static void tg3_phy_init_link_config(struct tg3 *tp)
e256f8a3 15350{
202ff1c2 15351 u32 adv = ADVERTISED_Autoneg;
e256f8a3 15352
7c786065
NS		 15353 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
15354 if (!(tp->phy_flags & TG3_PHYFLG_DISABLE_1G_HD_ADV))
15355 adv |= ADVERTISED_1000baseT_Half;
15356 adv |= ADVERTISED_1000baseT_Full;
15357 }
e256f8a3
MC		 15358
15359 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
15360 adv |= ADVERTISED_100baseT_Half |
15361 ADVERTISED_100baseT_Full |
15362 ADVERTISED_10baseT_Half |
15363 ADVERTISED_10baseT_Full |
15364 ADVERTISED_TP;
15365 else
15366 adv |= ADVERTISED_FIBRE;
15367
15368 tp->link_config.advertising = adv;
e740522e
MC		 15369 tp->link_config.speed = SPEED_UNKNOWN;
15370 tp->link_config.duplex = DUPLEX_UNKNOWN;
e256f8a3 15371 tp->link_config.autoneg = AUTONEG_ENABLE;
e740522e
MC		 15372 tp->link_config.active_speed = SPEED_UNKNOWN;
15373 tp->link_config.active_duplex = DUPLEX_UNKNOWN;
34655ad6
MC		 15374
15375 tp->old_link = -1;
e256f8a3
MC		 15376}
15377
229b1ad1 15378static int tg3_phy_probe(struct tg3 *tp)
7d0c41ef
MC		 15379{
15380 u32 hw_phy_id_1, hw_phy_id_2;
15381 u32 hw_phy_id, hw_phy_id_masked;
15382 int err;
1da177e4 15383
e256f8a3 15384 /* flow control autonegotiation is default behavior */
63c3a66f 15385 tg3_flag_set(tp, PAUSE_AUTONEG);
e256f8a3
MC		 15386 tp->link_config.flowctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
15387
8151ad57
MC		 15388 if (tg3_flag(tp, ENABLE_APE)) {
15389 switch (tp->pci_fn) {
15390 case 0:
15391 tp->phy_ape_lock = TG3_APE_LOCK_PHY0;
15392 break;
15393 case 1:
15394 tp->phy_ape_lock = TG3_APE_LOCK_PHY1;
15395 break;
15396 case 2:
15397 tp->phy_ape_lock = TG3_APE_LOCK_PHY2;
15398 break;
15399 case 3:
15400 tp->phy_ape_lock = TG3_APE_LOCK_PHY3;
15401 break;
15402 }
15403 }
15404
942d1af0
NS		 15405 if (!tg3_flag(tp, ENABLE_ASF) &&
15406 !(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) &&
15407 !(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
15408 tp->phy_flags &= ~(TG3_PHYFLG_1G_ON_VAUX_OK |
15409 TG3_PHYFLG_KEEP_LINK_ON_PWRDN);
15410
63c3a66f 15411 if (tg3_flag(tp, USE_PHYLIB))
b02fd9e3
MC		 15412 return tg3_phy_init(tp);
15413
1da177e4 15414 /* Reading the PHY ID register can conflict with ASF
877d0310 15415 * firmware access to the PHY hardware.
1da177e4
LT		 15416 */
15417 err = 0;
63c3a66f 15418 if (tg3_flag(tp, ENABLE_ASF) || tg3_flag(tp, ENABLE_APE)) {
79eb6904 15419 hw_phy_id = hw_phy_id_masked = TG3_PHY_ID_INVALID;
1da177e4
LT		 15420 } else {
15421 /* Now read the physical PHY_ID from the chip and verify
15422 * that it is sane. If it doesn't look good, we fall back
15423 * to either the hard-coded table based PHY_ID and failing
15424 * that the value found in the eeprom area.
15425 */
15426 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
15427 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
15428
15429 hw_phy_id = (hw_phy_id_1 & 0xffff) << 10;
15430 hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
15431 hw_phy_id |= (hw_phy_id_2 & 0x03ff) << 0;
15432
79eb6904 15433 hw_phy_id_masked = hw_phy_id & TG3_PHY_ID_MASK;
1da177e4
LT		 15434 }
15435
79eb6904 15436 if (!err && TG3_KNOWN_PHY_ID(hw_phy_id_masked)) {
1da177e4 15437 tp->phy_id = hw_phy_id;
79eb6904 15438 if (hw_phy_id_masked == TG3_PHY_ID_BCM8002)
f07e9af3 15439 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
da6b2d01 15440 else
f07e9af3 15441 tp->phy_flags &= ~TG3_PHYFLG_PHY_SERDES;
1da177e4 15442 } else {
79eb6904 15443 if (tp->phy_id != TG3_PHY_ID_INVALID) {
7d0c41ef
MC		 15444 /* Do nothing, phy ID already set up in
15445 * tg3_get_eeprom_hw_cfg().
15446 */
1da177e4
LT		 15447 } else {
15448 struct subsys_tbl_ent *p;
15449
15450 /* No eeprom signature? Try the hardcoded
15451 * subsys device table.
15452 */
24daf2b0 15453 p = tg3_lookup_by_subsys(tp);
7e6c63f0
HM		 15454 if (p) {
15455 tp->phy_id = p->phy_id;
15456 } else if (!tg3_flag(tp, IS_SSB_CORE)) {
15457 /* For now we saw the IDs 0xbc050cd0,
15458 * 0xbc050f80 and 0xbc050c30 on devices
15459 * connected to an BCM4785 and there are
15460 * probably more. Just assume that the phy is
15461 * supported when it is connected to a SSB core
15462 * for now.
15463 */
1da177e4 15464 return -ENODEV;
7e6c63f0 15465 }
1da177e4 15466
1da177e4 15467 if (!tp->phy_id ||
79eb6904 15468 tp->phy_id == TG3_PHY_ID_BCM8002)
f07e9af3 15469 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
1da177e4
LT		 15470 }
15471 }
15472
a6b68dab 15473 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) &&
4153577a
JP		 15474 (tg3_asic_rev(tp) == ASIC_REV_5719 ||
15475 tg3_asic_rev(tp) == ASIC_REV_5720 ||
c4dab506 15476 tg3_asic_rev(tp) == ASIC_REV_57766 ||
4153577a
JP		 15477 tg3_asic_rev(tp) == ASIC_REV_5762 ||
15478 (tg3_asic_rev(tp) == ASIC_REV_5717 &&
15479 tg3_chip_rev_id(tp) != CHIPREV_ID_5717_A0) ||
15480 (tg3_asic_rev(tp) == ASIC_REV_57765 &&
9e2ecbeb 15481 tg3_chip_rev_id(tp) != CHIPREV_ID_57765_A0))) {
52b02d04
MC		 15482 tp->phy_flags |= TG3_PHYFLG_EEE_CAP;
15483
9e2ecbeb
NS		 15484 tp->eee.supported = SUPPORTED_100baseT_Full |
15485 SUPPORTED_1000baseT_Full;
15486 tp->eee.advertised = ADVERTISED_100baseT_Full |
15487 ADVERTISED_1000baseT_Full;
15488 tp->eee.eee_enabled = 1;
15489 tp->eee.tx_lpi_enabled = 1;
15490 tp->eee.tx_lpi_timer = TG3_CPMU_DBTMR1_LNKIDLE_2047US;
15491 }
15492
e256f8a3
MC		 15493 tg3_phy_init_link_config(tp);
15494
942d1af0
NS		 15495 if (!(tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN) &&
15496 !(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) &&
63c3a66f
JP		 15497 !tg3_flag(tp, ENABLE_APE) &&
15498 !tg3_flag(tp, ENABLE_ASF)) {
e2bf73e7 15499 u32 bmsr, dummy;
1da177e4
LT		 15500
15501 tg3_readphy(tp, MII_BMSR, &bmsr);
15502 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
15503 (bmsr & BMSR_LSTATUS))
15504 goto skip_phy_reset;
6aa20a22 15505
1da177e4
LT		 15506 err = tg3_phy_reset(tp);
15507 if (err)
15508 return err;
15509
42b64a45 15510 tg3_phy_set_wirespeed(tp);
1da177e4 15511
e2bf73e7 15512 if (!tg3_phy_copper_an_config_ok(tp, &dummy)) {
42b64a45
MC		 15513 tg3_phy_autoneg_cfg(tp, tp->link_config.advertising,
15514 tp->link_config.flowctrl);
1da177e4
LT		 15515
15516 tg3_writephy(tp, MII_BMCR,
15517 BMCR_ANENABLE | BMCR_ANRESTART);
15518 }
1da177e4
LT		 15519 }
15520
15521skip_phy_reset:
79eb6904 15522 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
1da177e4
LT		 15523 err = tg3_init_5401phy_dsp(tp);
15524 if (err)
15525 return err;
1da177e4 15526
1da177e4
LT		 15527 err = tg3_init_5401phy_dsp(tp);
15528 }
15529
1da177e4
LT		 15530 return err;
15531}
15532
229b1ad1 15533static void tg3_read_vpd(struct tg3 *tp)
1da177e4 15534{
a4a8bb15 15535 u8 *vpd_data;
4181b2c8 15536 unsigned int block_end, rosize, len;
535a490e 15537 u32 vpdlen;
184b8904 15538 int j, i = 0;
a4a8bb15 15539
535a490e 15540 vpd_data = (u8 *)tg3_vpd_readblock(tp, &vpdlen);
a4a8bb15
MC		 15541 if (!vpd_data)
15542 goto out_no_vpd;
1da177e4 15543
535a490e 15544 i = pci_vpd_find_tag(vpd_data, 0, vpdlen, PCI_VPD_LRDT_RO_DATA);
4181b2c8
MC		 15545 if (i < 0)
15546 goto out_not_found;
1da177e4 15547
4181b2c8
MC		 15548 rosize = pci_vpd_lrdt_size(&vpd_data[i]);
15549 block_end = i + PCI_VPD_LRDT_TAG_SIZE + rosize;
15550 i += PCI_VPD_LRDT_TAG_SIZE;
1da177e4 15551
535a490e 15552 if (block_end > vpdlen)
4181b2c8 15553 goto out_not_found;
af2c6a4a 15554
184b8904
MC		 15555 j = pci_vpd_find_info_keyword(vpd_data, i, rosize,
15556 PCI_VPD_RO_KEYWORD_MFR_ID);
15557 if (j > 0) {
15558 len = pci_vpd_info_field_size(&vpd_data[j]);
15559
15560 j += PCI_VPD_INFO_FLD_HDR_SIZE;
15561 if (j + len > block_end || len != 4 ||
15562 memcmp(&vpd_data[j], "1028", 4))
15563 goto partno;
15564
15565 j = pci_vpd_find_info_keyword(vpd_data, i, rosize,
15566 PCI_VPD_RO_KEYWORD_VENDOR0);
15567 if (j < 0)
15568 goto partno;
15569
15570 len = pci_vpd_info_field_size(&vpd_data[j]);
15571
15572 j += PCI_VPD_INFO_FLD_HDR_SIZE;
15573 if (j + len > block_end)
15574 goto partno;
15575
715230a4
KC		 15576 if (len >= sizeof(tp->fw_ver))
15577 len = sizeof(tp->fw_ver) - 1;
15578 memset(tp->fw_ver, 0, sizeof(tp->fw_ver));
15579 snprintf(tp->fw_ver, sizeof(tp->fw_ver), "%.*s bc ", len,
15580 &vpd_data[j]);
184b8904
MC		 15581 }
15582
15583partno:
4181b2c8
MC		 15584 i = pci_vpd_find_info_keyword(vpd_data, i, rosize,
15585 PCI_VPD_RO_KEYWORD_PARTNO);
15586 if (i < 0)
15587 goto out_not_found;
af2c6a4a 15588
4181b2c8 15589 len = pci_vpd_info_field_size(&vpd_data[i]);
1da177e4 15590
4181b2c8
MC		 15591 i += PCI_VPD_INFO_FLD_HDR_SIZE;
15592 if (len > TG3_BPN_SIZE ||
535a490e 15593 (len + i) > vpdlen)
4181b2c8 15594 goto out_not_found;
1da177e4 15595
4181b2c8 15596 memcpy(tp->board_part_number, &vpd_data[i], len);
1da177e4 15597
1da177e4 15598out_not_found:
a4a8bb15 15599 kfree(vpd_data);
37a949c5 15600 if (tp->board_part_number[0])
a4a8bb15
MC		 15601 return;
15602
15603out_no_vpd:
4153577a 15604 if (tg3_asic_rev(tp) == ASIC_REV_5717) {
79d49695
MC		 15605 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 ||
15606 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717_C)
37a949c5
MC		 15607 strcpy(tp->board_part_number, "BCM5717");
15608 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718)
15609 strcpy(tp->board_part_number, "BCM5718");
15610 else
15611 goto nomatch;
4153577a 15612 } else if (tg3_asic_rev(tp) == ASIC_REV_57780) {
37a949c5
MC		 15613 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57780)
15614 strcpy(tp->board_part_number, "BCM57780");
15615 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57760)
15616 strcpy(tp->board_part_number, "BCM57760");
15617 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790)
15618 strcpy(tp->board_part_number, "BCM57790");
15619 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57788)
15620 strcpy(tp->board_part_number, "BCM57788");
15621 else
15622 goto nomatch;
4153577a 15623 } else if (tg3_asic_rev(tp) == ASIC_REV_57765) {
37a949c5
MC		 15624 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761)
15625 strcpy(tp->board_part_number, "BCM57761");
15626 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765)
15627 strcpy(tp->board_part_number, "BCM57765");
15628 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781)
15629 strcpy(tp->board_part_number, "BCM57781");
15630 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785)
15631 strcpy(tp->board_part_number, "BCM57785");
15632 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791)
15633 strcpy(tp->board_part_number, "BCM57791");
15634 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795)
15635 strcpy(tp->board_part_number, "BCM57795");
15636 else
15637 goto nomatch;
4153577a 15638 } else if (tg3_asic_rev(tp) == ASIC_REV_57766) {
55086ad9
MC		 15639 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57762)
15640 strcpy(tp->board_part_number, "BCM57762");
15641 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57766)
15642 strcpy(tp->board_part_number, "BCM57766");
15643 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57782)
15644 strcpy(tp->board_part_number, "BCM57782");
15645 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57786)
15646 strcpy(tp->board_part_number, "BCM57786");
15647 else
15648 goto nomatch;
4153577a 15649 } else if (tg3_asic_rev(tp) == ASIC_REV_5906) {
b5d3772c 15650 strcpy(tp->board_part_number, "BCM95906");
37a949c5
MC		 15651 } else {
15652nomatch:
b5d3772c 15653 strcpy(tp->board_part_number, "none");
37a949c5 15654 }
1da177e4
LT		 15655}
15656
229b1ad1 15657static int tg3_fw_img_is_valid(struct tg3 *tp, u32 offset)
9c8a620e
MC		 15658{
15659 u32 val;
15660
e4f34110 15661 if (tg3_nvram_read(tp, offset, &val) ||
9c8a620e 15662 (val & 0xfc000000) != 0x0c000000 ||
e4f34110 15663 tg3_nvram_read(tp, offset + 4, &val) ||
9c8a620e
MC		 15664 val != 0)
15665 return 0;
15666
15667 return 1;
15668}
15669
229b1ad1 15670static void tg3_read_bc_ver(struct tg3 *tp)
acd9c119 15671{
ff3a7cb2 15672 u32 val, offset, start, ver_offset;
75f9936e 15673 int i, dst_off;
ff3a7cb2 15674 bool newver = false;
acd9c119
MC		 15675
15676 if (tg3_nvram_read(tp, 0xc, &offset) ||
15677 tg3_nvram_read(tp, 0x4, &start))
15678 return;
15679
15680 offset = tg3_nvram_logical_addr(tp, offset);
15681
ff3a7cb2 15682 if (tg3_nvram_read(tp, offset, &val))
acd9c119
MC		 15683 return;
15684
ff3a7cb2
MC		 15685 if ((val & 0xfc000000) == 0x0c000000) {
15686 if (tg3_nvram_read(tp, offset + 4, &val))
acd9c119
MC		 15687 return;
15688
ff3a7cb2
MC		 15689 if (val == 0)
15690 newver = true;
15691 }
15692
75f9936e
MC		 15693 dst_off = strlen(tp->fw_ver);
15694
ff3a7cb2 15695 if (newver) {
75f9936e
MC		 15696 if (TG3_VER_SIZE - dst_off < 16 ||
15697 tg3_nvram_read(tp, offset + 8, &ver_offset))
ff3a7cb2
MC		 15698 return;
15699
15700 offset = offset + ver_offset - start;
15701 for (i = 0; i < 16; i += 4) {
15702 __be32 v;
15703 if (tg3_nvram_read_be32(tp, offset + i, &v))
15704 return;
15705
75f9936e 15706 memcpy(tp->fw_ver + dst_off + i, &v, sizeof(v));
ff3a7cb2
MC		 15707 }
15708 } else {
15709 u32 major, minor;
15710
15711 if (tg3_nvram_read(tp, TG3_NVM_PTREV_BCVER, &ver_offset))
15712 return;
15713
15714 major = (ver_offset & TG3_NVM_BCVER_MAJMSK) >>
15715 TG3_NVM_BCVER_MAJSFT;
15716 minor = ver_offset & TG3_NVM_BCVER_MINMSK;
75f9936e
MC		 15717 snprintf(&tp->fw_ver[dst_off], TG3_VER_SIZE - dst_off,
15718 "v%d.%02d", major, minor);
acd9c119
MC		 15719 }
15720}
15721
229b1ad1 15722static void tg3_read_hwsb_ver(struct tg3 *tp)
a6f6cb1c
MC		 15723{
15724 u32 val, major, minor;
15725
15726 /* Use native endian representation */
15727 if (tg3_nvram_read(tp, TG3_NVM_HWSB_CFG1, &val))
15728 return;
15729
15730 major = (val & TG3_NVM_HWSB_CFG1_MAJMSK) >>
15731 TG3_NVM_HWSB_CFG1_MAJSFT;
15732 minor = (val & TG3_NVM_HWSB_CFG1_MINMSK) >>
15733 TG3_NVM_HWSB_CFG1_MINSFT;
15734
15735 snprintf(&tp->fw_ver[0], 32, "sb v%d.%02d", major, minor);
15736}
15737
229b1ad1 15738static void tg3_read_sb_ver(struct tg3 *tp, u32 val)
dfe00d7d
MC		 15739{
15740 u32 offset, major, minor, build;
15741
75f9936e 15742 strncat(tp->fw_ver, "sb", TG3_VER_SIZE - strlen(tp->fw_ver) - 1);
dfe00d7d
MC		 15743
15744 if ((val & TG3_EEPROM_SB_FORMAT_MASK) != TG3_EEPROM_SB_FORMAT_1)
15745 return;
15746
15747 switch (val & TG3_EEPROM_SB_REVISION_MASK) {
15748 case TG3_EEPROM_SB_REVISION_0:
15749 offset = TG3_EEPROM_SB_F1R0_EDH_OFF;
15750 break;
15751 case TG3_EEPROM_SB_REVISION_2:
15752 offset = TG3_EEPROM_SB_F1R2_EDH_OFF;
15753 break;
15754 case TG3_EEPROM_SB_REVISION_3:
15755 offset = TG3_EEPROM_SB_F1R3_EDH_OFF;
15756 break;
a4153d40
MC		 15757 case TG3_EEPROM_SB_REVISION_4:
15758 offset = TG3_EEPROM_SB_F1R4_EDH_OFF;
15759 break;
15760 case TG3_EEPROM_SB_REVISION_5:
15761 offset = TG3_EEPROM_SB_F1R5_EDH_OFF;
15762 break;
bba226ac
MC		 15763 case TG3_EEPROM_SB_REVISION_6:
15764 offset = TG3_EEPROM_SB_F1R6_EDH_OFF;
15765 break;
dfe00d7d
MC		 15766 default:
15767 return;
15768 }
15769
e4f34110 15770 if (tg3_nvram_read(tp, offset, &val))
dfe00d7d
MC		 15771 return;
15772
15773 build = (val & TG3_EEPROM_SB_EDH_BLD_MASK) >>
15774 TG3_EEPROM_SB_EDH_BLD_SHFT;
15775 major = (val & TG3_EEPROM_SB_EDH_MAJ_MASK) >>
15776 TG3_EEPROM_SB_EDH_MAJ_SHFT;
15777 minor = val & TG3_EEPROM_SB_EDH_MIN_MASK;
15778
15779 if (minor > 99 || build > 26)
15780 return;
15781
75f9936e
MC		 15782 offset = strlen(tp->fw_ver);
15783 snprintf(&tp->fw_ver[offset], TG3_VER_SIZE - offset,
15784 " v%d.%02d", major, minor);
dfe00d7d
MC		 15785
15786 if (build > 0) {
75f9936e
MC		 15787 offset = strlen(tp->fw_ver);
15788 if (offset < TG3_VER_SIZE - 1)
15789 tp->fw_ver[offset] = 'a' + build - 1;
dfe00d7d
MC		 15790 }
15791}
15792
229b1ad1 15793static void tg3_read_mgmtfw_ver(struct tg3 *tp)
c4e6575c
MC		 15794{
15795 u32 val, offset, start;
acd9c119 15796 int i, vlen;
9c8a620e
MC		 15797
15798 for (offset = TG3_NVM_DIR_START;
15799 offset < TG3_NVM_DIR_END;
15800 offset += TG3_NVM_DIRENT_SIZE) {
e4f34110 15801 if (tg3_nvram_read(tp, offset, &val))
c4e6575c
MC		 15802 return;
15803
9c8a620e
MC		 15804 if ((val >> TG3_NVM_DIRTYPE_SHIFT) == TG3_NVM_DIRTYPE_ASFINI)
15805 break;
15806 }
15807
15808 if (offset == TG3_NVM_DIR_END)
15809 return;
15810
63c3a66f 15811 if (!tg3_flag(tp, 5705_PLUS))
9c8a620e 15812 start = 0x08000000;
e4f34110 15813 else if (tg3_nvram_read(tp, offset - 4, &start))
9c8a620e
MC		 15814 return;
15815
e4f34110 15816 if (tg3_nvram_read(tp, offset + 4, &offset) ||
9c8a620e 15817 !tg3_fw_img_is_valid(tp, offset) ||
e4f34110 15818 tg3_nvram_read(tp, offset + 8, &val))
9c8a620e
MC		 15819 return;
15820
15821 offset += val - start;
15822
acd9c119 15823 vlen = strlen(tp->fw_ver);
9c8a620e 15824
acd9c119
MC		 15825 tp->fw_ver[vlen++] = ',';
15826 tp->fw_ver[vlen++] = ' ';
9c8a620e
MC		 15827
15828 for (i = 0; i < 4; i++) {
a9dc529d
MC		 15829 __be32 v;
15830 if (tg3_nvram_read_be32(tp, offset, &v))
c4e6575c
MC		 15831 return;
15832
b9fc7dc5 15833 offset += sizeof(v);
c4e6575c 15834
acd9c119
MC		 15835 if (vlen > TG3_VER_SIZE - sizeof(v)) {
15836 memcpy(&tp->fw_ver[vlen], &v, TG3_VER_SIZE - vlen);
9c8a620e 15837 break;
c4e6575c 15838 }
9c8a620e 15839
acd9c119
MC		 15840 memcpy(&tp->fw_ver[vlen], &v, sizeof(v));
15841 vlen += sizeof(v);
c4e6575c 15842 }
acd9c119
MC		 15843}
15844
229b1ad1 15845static void tg3_probe_ncsi(struct tg3 *tp)
7fd76445 15846{
7fd76445 15847 u32 apedata;
7fd76445
MC		 15848
15849 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
15850 if (apedata != APE_SEG_SIG_MAGIC)
15851 return;
15852
15853 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
15854 if (!(apedata & APE_FW_STATUS_READY))
15855 return;
15856
165f4d1c
MC		 15857 if (tg3_ape_read32(tp, TG3_APE_FW_FEATURES) & TG3_APE_FW_FEATURE_NCSI)
15858 tg3_flag_set(tp, APE_HAS_NCSI);
15859}
15860
229b1ad1 15861static void tg3_read_dash_ver(struct tg3 *tp)
165f4d1c
MC		 15862{
15863 int vlen;
15864 u32 apedata;
15865 char *fwtype;
15866
7fd76445
MC		 15867 apedata = tg3_ape_read32(tp, TG3_APE_FW_VERSION);
15868
165f4d1c 15869 if (tg3_flag(tp, APE_HAS_NCSI))
ecc79648 15870 fwtype = "NCSI";
c86a8560
MC		 15871 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5725)
15872 fwtype = "SMASH";
165f4d1c 15873 else
ecc79648
MC		 15874 fwtype = "DASH";
15875
7fd76445
MC		 15876 vlen = strlen(tp->fw_ver);
15877
ecc79648
MC		 15878 snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " %s v%d.%d.%d.%d",
15879 fwtype,
7fd76445
MC		 15880 (apedata & APE_FW_VERSION_MAJMSK) >> APE_FW_VERSION_MAJSFT,
15881 (apedata & APE_FW_VERSION_MINMSK) >> APE_FW_VERSION_MINSFT,
15882 (apedata & APE_FW_VERSION_REVMSK) >> APE_FW_VERSION_REVSFT,
15883 (apedata & APE_FW_VERSION_BLDMSK));
15884}
15885
c86a8560
MC		 15886static void tg3_read_otp_ver(struct tg3 *tp)
15887{
15888 u32 val, val2;
15889
4153577a 15890 if (tg3_asic_rev(tp) != ASIC_REV_5762)
c86a8560
MC		 15891 return;
15892
15893 if (!tg3_ape_otp_read(tp, OTP_ADDRESS_MAGIC0, &val) &&
15894 !tg3_ape_otp_read(tp, OTP_ADDRESS_MAGIC0 + 4, &val2) &&
15895 TG3_OTP_MAGIC0_VALID(val)) {
15896 u64 val64 = (u64) val << 32 | val2;
15897 u32 ver = 0;
15898 int i, vlen;
15899
15900 for (i = 0; i < 7; i++) {
15901 if ((val64 & 0xff) == 0)
15902 break;
15903 ver = val64 & 0xff;
15904 val64 >>= 8;
15905 }
15906 vlen = strlen(tp->fw_ver);
15907 snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " .%02d", ver);
15908 }
15909}
15910
229b1ad1 15911static void tg3_read_fw_ver(struct tg3 *tp)
acd9c119
MC		 15912{
15913 u32 val;
75f9936e 15914 bool vpd_vers = false;
acd9c119 15915
75f9936e
MC		 15916 if (tp->fw_ver[0] != 0)
15917 vpd_vers = true;
df259d8c 15918
63c3a66f 15919 if (tg3_flag(tp, NO_NVRAM)) {
75f9936e 15920 strcat(tp->fw_ver, "sb");
c86a8560 15921 tg3_read_otp_ver(tp);
df259d8c
MC		 15922 return;
15923 }
15924
acd9c119
MC		 15925 if (tg3_nvram_read(tp, 0, &val))
15926 return;
15927
15928 if (val == TG3_EEPROM_MAGIC)
15929 tg3_read_bc_ver(tp);
15930 else if ((val & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW)
15931 tg3_read_sb_ver(tp, val);
a6f6cb1c
MC		 15932 else if ((val & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
15933 tg3_read_hwsb_ver(tp);
acd9c119 15934
165f4d1c
MC		 15935 if (tg3_flag(tp, ENABLE_ASF)) {
15936 if (tg3_flag(tp, ENABLE_APE)) {
15937 tg3_probe_ncsi(tp);
15938 if (!vpd_vers)
15939 tg3_read_dash_ver(tp);
15940 } else if (!vpd_vers) {
15941 tg3_read_mgmtfw_ver(tp);
15942 }
c9cab24e 15943 }
9c8a620e
MC		 15944
15945 tp->fw_ver[TG3_VER_SIZE - 1] = 0;
c4e6575c
MC		 15946}
15947
7cb32cf2
MC		 15948static inline u32 tg3_rx_ret_ring_size(struct tg3 *tp)
15949{
63c3a66f 15950 if (tg3_flag(tp, LRG_PROD_RING_CAP))
de9f5230 15951 return TG3_RX_RET_MAX_SIZE_5717;
63c3a66f 15952 else if (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS))
de9f5230 15953 return TG3_RX_RET_MAX_SIZE_5700;
7cb32cf2 15954 else
de9f5230 15955 return TG3_RX_RET_MAX_SIZE_5705;
7cb32cf2
MC		 15956}
15957
9baa3c34 15958static const struct pci_device_id tg3_write_reorder_chipsets[] = {
895950c2
JP		 15959 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C) },
15960 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE) },
15961 { PCI_DEVICE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8385_0) },
15962 { },
15963};
15964
229b1ad1 15965static struct pci_dev *tg3_find_peer(struct tg3 *tp)
16c7fa7d
MC		 15966{
15967 struct pci_dev *peer;
15968 unsigned int func, devnr = tp->pdev->devfn & ~7;
15969
15970 for (func = 0; func < 8; func++) {
15971 peer = pci_get_slot(tp->pdev->bus, devnr | func);
15972 if (peer && peer != tp->pdev)
15973 break;
15974 pci_dev_put(peer);
15975 }
15976 /* 5704 can be configured in single-port mode, set peer to
15977 * tp->pdev in that case.
15978 */
15979 if (!peer) {
15980 peer = tp->pdev;
15981 return peer;
15982 }
15983
15984 /*
15985 * We don't need to keep the refcount elevated; there's no way
15986 * to remove one half of this device without removing the other
15987 */
15988 pci_dev_put(peer);
15989
15990 return peer;
15991}
15992
229b1ad1 15993static void tg3_detect_asic_rev(struct tg3 *tp, u32 misc_ctrl_reg)
42b123b1
MC		 15994{
15995 tp->pci_chip_rev_id = misc_ctrl_reg >> MISC_HOST_CTRL_CHIPREV_SHIFT;
4153577a 15996 if (tg3_asic_rev(tp) == ASIC_REV_USE_PROD_ID_REG) {
42b123b1
MC		 15997 u32 reg;
15998
15999 /* All devices that use the alternate
16000 * ASIC REV location have a CPMU.
16001 */
16002 tg3_flag_set(tp, CPMU_PRESENT);
16003
16004 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 ||
79d49695 16005 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717_C ||
42b123b1
MC		 16006 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 ||
16007 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5719 ||
c65a17f4 16008 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5720 ||
68273712
NS		 16009 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57767 ||
16010 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57764 ||
c65a17f4
MC		 16011 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5762 ||
16012 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5725 ||
68273712
NS		 16013 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5727 ||
16014 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57787)
42b123b1
MC		 16015 reg = TG3PCI_GEN2_PRODID_ASICREV;
16016 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781 ||
16017 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785 ||
16018 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761 ||
16019 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765 ||
16020 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791 ||
16021 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795 ||
16022 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57762 ||
16023 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57766 ||
16024 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57782 ||
16025 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57786)
16026 reg = TG3PCI_GEN15_PRODID_ASICREV;
16027 else
16028 reg = TG3PCI_PRODID_ASICREV;
16029
16030 pci_read_config_dword(tp->pdev, reg, &tp->pci_chip_rev_id);
16031 }
16032
16033 /* Wrong chip ID in 5752 A0. This code can be removed later
16034 * as A0 is not in production.
16035 */
4153577a 16036 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5752_A0_HW)
42b123b1
MC		 16037 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
16038
4153577a 16039 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5717_C0)
79d49695
MC		 16040 tp->pci_chip_rev_id = CHIPREV_ID_5720_A0;
16041
4153577a
JP		 16042 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
16043 tg3_asic_rev(tp) == ASIC_REV_5719 ||
16044 tg3_asic_rev(tp) == ASIC_REV_5720)
42b123b1
MC		 16045 tg3_flag_set(tp, 5717_PLUS);
16046
4153577a
JP		 16047 if (tg3_asic_rev(tp) == ASIC_REV_57765 ||
16048 tg3_asic_rev(tp) == ASIC_REV_57766)
42b123b1
MC		 16049 tg3_flag_set(tp, 57765_CLASS);
16050
c65a17f4 16051 if (tg3_flag(tp, 57765_CLASS) || tg3_flag(tp, 5717_PLUS) ||
4153577a 16052 tg3_asic_rev(tp) == ASIC_REV_5762)
42b123b1
MC		 16053 tg3_flag_set(tp, 57765_PLUS);
16054
16055 /* Intentionally exclude ASIC_REV_5906 */
4153577a
JP		 16056 if (tg3_asic_rev(tp) == ASIC_REV_5755 ||
16057 tg3_asic_rev(tp) == ASIC_REV_5787 ||
16058 tg3_asic_rev(tp) == ASIC_REV_5784 ||
16059 tg3_asic_rev(tp) == ASIC_REV_5761 ||
16060 tg3_asic_rev(tp) == ASIC_REV_5785 ||
16061 tg3_asic_rev(tp) == ASIC_REV_57780 ||
42b123b1
MC		 16062 tg3_flag(tp, 57765_PLUS))
16063 tg3_flag_set(tp, 5755_PLUS);
16064
4153577a
JP		 16065 if (tg3_asic_rev(tp) == ASIC_REV_5780 ||
16066 tg3_asic_rev(tp) == ASIC_REV_5714)
42b123b1
MC		 16067 tg3_flag_set(tp, 5780_CLASS);
16068
4153577a
JP		 16069 if (tg3_asic_rev(tp) == ASIC_REV_5750 ||
16070 tg3_asic_rev(tp) == ASIC_REV_5752 ||
16071 tg3_asic_rev(tp) == ASIC_REV_5906 ||
42b123b1
MC		 16072 tg3_flag(tp, 5755_PLUS) ||
16073 tg3_flag(tp, 5780_CLASS))
16074 tg3_flag_set(tp, 5750_PLUS);
16075
4153577a 16076 if (tg3_asic_rev(tp) == ASIC_REV_5705 ||
42b123b1
MC		 16077 tg3_flag(tp, 5750_PLUS))
16078 tg3_flag_set(tp, 5705_PLUS);
16079}
16080
3d567e0e
NNS		 16081static bool tg3_10_100_only_device(struct tg3 *tp,
16082 const struct pci_device_id *ent)
16083{
16084 u32 grc_misc_cfg = tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK;
16085
4153577a
JP		 16086 if ((tg3_asic_rev(tp) == ASIC_REV_5703 &&
16087 (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
3d567e0e
NNS		 16088 (tp->phy_flags & TG3_PHYFLG_IS_FET))
16089 return true;
16090
16091 if (ent->driver_data & TG3_DRV_DATA_FLAG_10_100_ONLY) {
4153577a 16092 if (tg3_asic_rev(tp) == ASIC_REV_5705) {
3d567e0e
NNS		 16093 if (ent->driver_data & TG3_DRV_DATA_FLAG_5705_10_100)
16094 return true;
16095 } else {
16096 return true;
16097 }
16098 }
16099
16100 return false;
16101}
16102
1dd06ae8 16103static int tg3_get_invariants(struct tg3 *tp, const struct pci_device_id *ent)
1da177e4 16104{
1da177e4 16105 u32 misc_ctrl_reg;
1da177e4
LT		 16106 u32 pci_state_reg, grc_misc_cfg;
16107 u32 val;
16108 u16 pci_cmd;
5e7dfd0f 16109 int err;
1da177e4 16110
1da177e4
LT		 16111 /* Force memory write invalidate off. If we leave it on,
16112 * then on 5700_BX chips we have to enable a workaround.
16113 * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
16114 * to match the cacheline size. The Broadcom driver have this
16115 * workaround but turns MWI off all the times so never uses
16116 * it. This seems to suggest that the workaround is insufficient.
16117 */
16118 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
16119 pci_cmd &= ~PCI_COMMAND_INVALIDATE;
16120 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
16121
16821285
MC		 16122 /* Important! -- Make sure register accesses are byteswapped
16123 * correctly. Also, for those chips that require it, make
16124 * sure that indirect register accesses are enabled before
16125 * the first operation.
1da177e4
LT		 16126 */
16127 pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
16128 &misc_ctrl_reg);
16821285
MC		 16129 tp->misc_host_ctrl |= (misc_ctrl_reg &
16130 MISC_HOST_CTRL_CHIPREV);
16131 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
16132 tp->misc_host_ctrl);
1da177e4 16133
42b123b1 16134 tg3_detect_asic_rev(tp, misc_ctrl_reg);
ff645bec 16135
6892914f
MC		 16136 /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
16137 * we need to disable memory and use config. cycles
16138 * only to access all registers. The 5702/03 chips
16139 * can mistakenly decode the special cycles from the
16140 * ICH chipsets as memory write cycles, causing corruption
16141 * of register and memory space. Only certain ICH bridges
16142 * will drive special cycles with non-zero data during the
16143 * address phase which can fall within the 5703's address
16144 * range. This is not an ICH bug as the PCI spec allows
16145 * non-zero address during special cycles. However, only
16146 * these ICH bridges are known to drive non-zero addresses
16147 * during special cycles.
16148 *
16149 * Since special cycles do not cross PCI bridges, we only
16150 * enable this workaround if the 5703 is on the secondary
16151 * bus of these ICH bridges.
16152 */
4153577a
JP		 16153 if ((tg3_chip_rev_id(tp) == CHIPREV_ID_5703_A1) ||
16154 (tg3_chip_rev_id(tp) == CHIPREV_ID_5703_A2)) {
6892914f
MC		 16155 static struct tg3_dev_id {
16156 u32 vendor;
16157 u32 device;
16158 u32 rev;
16159 } ich_chipsets[] = {
16160 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8,
16161 PCI_ANY_ID },
16162 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8,
16163 PCI_ANY_ID },
16164 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11,
16165 0xa },
16166 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6,
16167 PCI_ANY_ID },
16168 { },
16169 };
16170 struct tg3_dev_id *pci_id = &ich_chipsets[0];
16171 struct pci_dev *bridge = NULL;
16172
16173 while (pci_id->vendor != 0) {
16174 bridge = pci_get_device(pci_id->vendor, pci_id->device,
16175 bridge);
16176 if (!bridge) {
16177 pci_id++;
16178 continue;
16179 }
16180 if (pci_id->rev != PCI_ANY_ID) {
44c10138 16181 if (bridge->revision > pci_id->rev)
6892914f
MC		 16182 continue;
16183 }
16184 if (bridge->subordinate &&
16185 (bridge->subordinate->number ==
16186 tp->pdev->bus->number)) {
63c3a66f 16187 tg3_flag_set(tp, ICH_WORKAROUND);
6892914f
MC		 16188 pci_dev_put(bridge);
16189 break;
16190 }
16191 }
16192 }
16193
4153577a 16194 if (tg3_asic_rev(tp) == ASIC_REV_5701) {
41588ba1
MC		 16195 static struct tg3_dev_id {
16196 u32 vendor;
16197 u32 device;
16198 } bridge_chipsets[] = {
16199 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0 },
16200 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1 },
16201 { },
16202 };
16203 struct tg3_dev_id *pci_id = &bridge_chipsets[0];
16204 struct pci_dev *bridge = NULL;
16205
16206 while (pci_id->vendor != 0) {
16207 bridge = pci_get_device(pci_id->vendor,
16208 pci_id->device,
16209 bridge);
16210 if (!bridge) {
16211 pci_id++;
16212 continue;
16213 }
16214 if (bridge->subordinate &&
16215 (bridge->subordinate->number <=
16216 tp->pdev->bus->number) &&
b918c62e 16217 (bridge->subordinate->busn_res.end >=
41588ba1 16218 tp->pdev->bus->number)) {
63c3a66f 16219 tg3_flag_set(tp, 5701_DMA_BUG);
41588ba1
MC		 16220 pci_dev_put(bridge);
16221 break;
16222 }
16223 }
16224 }
16225
4a29cc2e
MC		 16226 /* The EPB bridge inside 5714, 5715, and 5780 cannot support
16227 * DMA addresses > 40-bit. This bridge may have other additional
16228 * 57xx devices behind it in some 4-port NIC designs for example.
16229 * Any tg3 device found behind the bridge will also need the 40-bit
16230 * DMA workaround.
16231 */
42b123b1 16232 if (tg3_flag(tp, 5780_CLASS)) {
63c3a66f 16233 tg3_flag_set(tp, 40BIT_DMA_BUG);
0f847584 16234 tp->msi_cap = tp->pdev->msi_cap;
859a5887 16235 } else {
4a29cc2e
MC		 16236 struct pci_dev *bridge = NULL;
16237
16238 do {
16239 bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
16240 PCI_DEVICE_ID_SERVERWORKS_EPB,
16241 bridge);
16242 if (bridge && bridge->subordinate &&
16243 (bridge->subordinate->number <=
16244 tp->pdev->bus->number) &&
b918c62e 16245 (bridge->subordinate->busn_res.end >=
4a29cc2e 16246 tp->pdev->bus->number)) {
63c3a66f 16247 tg3_flag_set(tp, 40BIT_DMA_BUG);
4a29cc2e
MC		 16248 pci_dev_put(bridge);
16249 break;
16250 }
16251 } while (bridge);
16252 }
4cf78e4f 16253
4153577a
JP		 16254 if (tg3_asic_rev(tp) == ASIC_REV_5704 ||
16255 tg3_asic_rev(tp) == ASIC_REV_5714)
7544b097
MC		 16256 tp->pdev_peer = tg3_find_peer(tp);
16257
507399f1 16258 /* Determine TSO capabilities */
4153577a 16259 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5719_A0)
4d163b75 16260 ; /* Do nothing. HW bug. */
63c3a66f
JP		 16261 else if (tg3_flag(tp, 57765_PLUS))
16262 tg3_flag_set(tp, HW_TSO_3);
16263 else if (tg3_flag(tp, 5755_PLUS) ||
4153577a 16264 tg3_asic_rev(tp) == ASIC_REV_5906)
63c3a66f
JP		 16265 tg3_flag_set(tp, HW_TSO_2);
16266 else if (tg3_flag(tp, 5750_PLUS)) {
16267 tg3_flag_set(tp, HW_TSO_1);
16268 tg3_flag_set(tp, TSO_BUG);
4153577a
JP		 16269 if (tg3_asic_rev(tp) == ASIC_REV_5750 &&
16270 tg3_chip_rev_id(tp) >= CHIPREV_ID_5750_C2)
63c3a66f 16271 tg3_flag_clear(tp, TSO_BUG);
4153577a
JP		 16272 } else if (tg3_asic_rev(tp) != ASIC_REV_5700 &&
16273 tg3_asic_rev(tp) != ASIC_REV_5701 &&
16274 tg3_chip_rev_id(tp) != CHIPREV_ID_5705_A0) {
1caf13eb
MC		 16275 tg3_flag_set(tp, FW_TSO);
16276 tg3_flag_set(tp, TSO_BUG);
4153577a 16277 if (tg3_asic_rev(tp) == ASIC_REV_5705)
507399f1
MC		 16278 tp->fw_needed = FIRMWARE_TG3TSO5;
16279 else
16280 tp->fw_needed = FIRMWARE_TG3TSO;
16281 }
16282
dabc5c67 16283 /* Selectively allow TSO based on operating conditions */
6ff6f81d
MC		 16284 if (tg3_flag(tp, HW_TSO_1) ||
16285 tg3_flag(tp, HW_TSO_2) ||
16286 tg3_flag(tp, HW_TSO_3) ||
1caf13eb 16287 tg3_flag(tp, FW_TSO)) {
cf9ecf4b
MC		 16288 /* For firmware TSO, assume ASF is disabled.
16289 * We'll disable TSO later if we discover ASF
16290 * is enabled in tg3_get_eeprom_hw_cfg().
16291 */
dabc5c67 16292 tg3_flag_set(tp, TSO_CAPABLE);
cf9ecf4b 16293 } else {
dabc5c67
MC		 16294 tg3_flag_clear(tp, TSO_CAPABLE);
16295 tg3_flag_clear(tp, TSO_BUG);
16296 tp->fw_needed = NULL;
16297 }
16298
4153577a 16299 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0)
dabc5c67
MC		 16300 tp->fw_needed = FIRMWARE_TG3;
16301
c4dab506
NS		 16302 if (tg3_asic_rev(tp) == ASIC_REV_57766)
16303 tp->fw_needed = FIRMWARE_TG357766;
16304
507399f1
MC		 16305 tp->irq_max = 1;
16306
63c3a66f
JP		 16307 if (tg3_flag(tp, 5750_PLUS)) {
16308 tg3_flag_set(tp, SUPPORT_MSI);
4153577a
JP		 16309 if (tg3_chip_rev(tp) == CHIPREV_5750_AX ||
16310 tg3_chip_rev(tp) == CHIPREV_5750_BX ||
16311 (tg3_asic_rev(tp) == ASIC_REV_5714 &&
16312 tg3_chip_rev_id(tp) <= CHIPREV_ID_5714_A2 &&
7544b097 16313 tp->pdev_peer == tp->pdev))
63c3a66f 16314 tg3_flag_clear(tp, SUPPORT_MSI);
7544b097 16315
63c3a66f 16316 if (tg3_flag(tp, 5755_PLUS) ||
4153577a 16317 tg3_asic_rev(tp) == ASIC_REV_5906) {
63c3a66f 16318 tg3_flag_set(tp, 1SHOT_MSI);
52c0fd83 16319 }
4f125f42 16320
63c3a66f
JP		 16321 if (tg3_flag(tp, 57765_PLUS)) {
16322 tg3_flag_set(tp, SUPPORT_MSIX);
507399f1
MC		 16323 tp->irq_max = TG3_IRQ_MAX_VECS;
16324 }
f6eb9b1f 16325 }
0e1406dd 16326
9102426a
MC		 16327 tp->txq_max = 1;
16328 tp->rxq_max = 1;
16329 if (tp->irq_max > 1) {
16330 tp->rxq_max = TG3_RSS_MAX_NUM_QS;
16331 tg3_rss_init_dflt_indir_tbl(tp, TG3_RSS_MAX_NUM_QS);
16332
4153577a
JP		 16333 if (tg3_asic_rev(tp) == ASIC_REV_5719 ||
16334 tg3_asic_rev(tp) == ASIC_REV_5720)
9102426a
MC		 16335 tp->txq_max = tp->irq_max - 1;
16336 }
16337
b7abee6e 16338 if (tg3_flag(tp, 5755_PLUS) ||
4153577a 16339 tg3_asic_rev(tp) == ASIC_REV_5906)
63c3a66f 16340 tg3_flag_set(tp, SHORT_DMA_BUG);
f6eb9b1f 16341
4153577a 16342 if (tg3_asic_rev(tp) == ASIC_REV_5719)
a4cb428d 16343 tp->dma_limit = TG3_TX_BD_DMA_MAX_4K;
e31aa987 16344
4153577a
JP		 16345 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
16346 tg3_asic_rev(tp) == ASIC_REV_5719 ||
16347 tg3_asic_rev(tp) == ASIC_REV_5720 ||
16348 tg3_asic_rev(tp) == ASIC_REV_5762)
63c3a66f 16349 tg3_flag_set(tp, LRG_PROD_RING_CAP);
de9f5230 16350
63c3a66f 16351 if (tg3_flag(tp, 57765_PLUS) &&
4153577a 16352 tg3_chip_rev_id(tp) != CHIPREV_ID_5719_A0)
63c3a66f 16353 tg3_flag_set(tp, USE_JUMBO_BDFLAG);
b703df6f 16354
63c3a66f
JP		 16355 if (!tg3_flag(tp, 5705_PLUS) ||
16356 tg3_flag(tp, 5780_CLASS) ||
16357 tg3_flag(tp, USE_JUMBO_BDFLAG))
16358 tg3_flag_set(tp, JUMBO_CAPABLE);
0f893dc6 16359
52f4490c
MC		 16360 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
16361 &pci_state_reg);
16362
708ebb3a 16363 if (pci_is_pcie(tp->pdev)) {
5e7dfd0f
MC		 16364 u16 lnkctl;
16365
63c3a66f 16366 tg3_flag_set(tp, PCI_EXPRESS);
5f5c51e3 16367
0f49bfbd 16368 pcie_capability_read_word(tp->pdev, PCI_EXP_LNKCTL, &lnkctl);
5e7dfd0f 16369 if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN) {
4153577a 16370 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
63c3a66f 16371 tg3_flag_clear(tp, HW_TSO_2);
dabc5c67 16372 tg3_flag_clear(tp, TSO_CAPABLE);
7196cd6c 16373 }
4153577a
JP		 16374 if (tg3_asic_rev(tp) == ASIC_REV_5784 ||
16375 tg3_asic_rev(tp) == ASIC_REV_5761 ||
16376 tg3_chip_rev_id(tp) == CHIPREV_ID_57780_A0 ||
16377 tg3_chip_rev_id(tp) == CHIPREV_ID_57780_A1)
63c3a66f 16378 tg3_flag_set(tp, CLKREQ_BUG);
4153577a 16379 } else if (tg3_chip_rev_id(tp) == CHIPREV_ID_5717_A0) {
63c3a66f 16380 tg3_flag_set(tp, L1PLLPD_EN);
c7835a77 16381 }
4153577a 16382 } else if (tg3_asic_rev(tp) == ASIC_REV_5785) {
708ebb3a
JM		 16383 /* BCM5785 devices are effectively PCIe devices, and should
16384 * follow PCIe codepaths, but do not have a PCIe capabilities
16385 * section.
93a700a9 16386 */
63c3a66f
JP		 16387 tg3_flag_set(tp, PCI_EXPRESS);
16388 } else if (!tg3_flag(tp, 5705_PLUS) ||
16389 tg3_flag(tp, 5780_CLASS)) {
52f4490c
MC		 16390 tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX);
16391 if (!tp->pcix_cap) {
2445e461
MC		 16392 dev_err(&tp->pdev->dev,
16393 "Cannot find PCI-X capability, aborting\n");
52f4490c
MC		 16394 return -EIO;
16395 }
16396
16397 if (!(pci_state_reg & PCISTATE_CONV_PCI_MODE))
63c3a66f 16398 tg3_flag_set(tp, PCIX_MODE);
52f4490c 16399 }
1da177e4 16400
399de50b
MC		 16401 /* If we have an AMD 762 or VIA K8T800 chipset, write
16402 * reordering to the mailbox registers done by the host
16403 * controller can cause major troubles. We read back from
16404 * every mailbox register write to force the writes to be
16405 * posted to the chip in order.
16406 */
4143470c 16407 if (pci_dev_present(tg3_write_reorder_chipsets) &&
63c3a66f
JP		 16408 !tg3_flag(tp, PCI_EXPRESS))
16409 tg3_flag_set(tp, MBOX_WRITE_REORDER);
399de50b 16410
69fc4053
MC		 16411 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
16412 &tp->pci_cacheline_sz);
16413 pci_read_config_byte(tp->pdev, PCI_LATENCY_TIMER,
16414 &tp->pci_lat_timer);
4153577a 16415 if (tg3_asic_rev(tp) == ASIC_REV_5703 &&
1da177e4
LT		 16416 tp->pci_lat_timer < 64) {
16417 tp->pci_lat_timer = 64;
69fc4053
MC		 16418 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
16419 tp->pci_lat_timer);
1da177e4
LT		 16420 }
16421
16821285
MC		 16422 /* Important! -- It is critical that the PCI-X hw workaround
16423 * situation is decided before the first MMIO register access.
16424 */
4153577a 16425 if (tg3_chip_rev(tp) == CHIPREV_5700_BX) {
52f4490c
MC		 16426 /* 5700 BX chips need to have their TX producer index
16427 * mailboxes written twice to workaround a bug.
16428 */
63c3a66f 16429 tg3_flag_set(tp, TXD_MBOX_HWBUG);
1da177e4 16430
52f4490c 16431 /* If we are in PCI-X mode, enable register write workaround.
1da177e4
LT		 16432 *
16433 * The workaround is to use indirect register accesses
16434 * for all chip writes not to mailbox registers.
16435 */
63c3a66f 16436 if (tg3_flag(tp, PCIX_MODE)) {
1da177e4 16437 u32 pm_reg;
1da177e4 16438
63c3a66f 16439 tg3_flag_set(tp, PCIX_TARGET_HWBUG);
1da177e4
LT		 16440
16441 /* The chip can have it's power management PCI config
16442 * space registers clobbered due to this bug.
16443 * So explicitly force the chip into D0 here.
16444 */
9974a356 16445 pci_read_config_dword(tp->pdev,
0319f30e 16446 tp->pdev->pm_cap + PCI_PM_CTRL,
1da177e4
LT		 16447 &pm_reg);
16448 pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
16449 pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
9974a356 16450 pci_write_config_dword(tp->pdev,
0319f30e 16451 tp->pdev->pm_cap + PCI_PM_CTRL,
1da177e4
LT		 16452 pm_reg);
16453
16454 /* Also, force SERR#/PERR# in PCI command. */
16455 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
16456 pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
16457 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
16458 }
16459 }
16460
1da177e4 16461 if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
63c3a66f 16462 tg3_flag_set(tp, PCI_HIGH_SPEED);
1da177e4 16463 if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
63c3a66f 16464 tg3_flag_set(tp, PCI_32BIT);
1da177e4
LT		 16465
16466 /* Chip-specific fixup from Broadcom driver */
4153577a 16467 if ((tg3_chip_rev_id(tp) == CHIPREV_ID_5704_A0) &&
1da177e4
LT		 16468 (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
16469 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
16470 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
16471 }
16472
1ee582d8 16473 /* Default fast path register access methods */
20094930 16474 tp->read32 = tg3_read32;
1ee582d8 16475 tp->write32 = tg3_write32;
09ee929c 16476 tp->read32_mbox = tg3_read32;
20094930 16477 tp->write32_mbox = tg3_write32;
1ee582d8
MC		 16478 tp->write32_tx_mbox = tg3_write32;
16479 tp->write32_rx_mbox = tg3_write32;
16480
16481 /* Various workaround register access methods */
63c3a66f 16482 if (tg3_flag(tp, PCIX_TARGET_HWBUG))
1ee582d8 16483 tp->write32 = tg3_write_indirect_reg32;
4153577a 16484 else if (tg3_asic_rev(tp) == ASIC_REV_5701 ||
63c3a66f 16485 (tg3_flag(tp, PCI_EXPRESS) &&
4153577a 16486 tg3_chip_rev_id(tp) == CHIPREV_ID_5750_A0)) {
98efd8a6
MC		 16487 /*
16488 * Back to back register writes can cause problems on these
16489 * chips, the workaround is to read back all reg writes
16490 * except those to mailbox regs.
16491 *
16492 * See tg3_write_indirect_reg32().
16493 */
1ee582d8 16494 tp->write32 = tg3_write_flush_reg32;
98efd8a6
MC		 16495 }
16496
63c3a66f 16497 if (tg3_flag(tp, TXD_MBOX_HWBUG) || tg3_flag(tp, MBOX_WRITE_REORDER)) {
1ee582d8 16498 tp->write32_tx_mbox = tg3_write32_tx_mbox;
63c3a66f 16499 if (tg3_flag(tp, MBOX_WRITE_REORDER))
1ee582d8
MC		 16500 tp->write32_rx_mbox = tg3_write_flush_reg32;
16501 }
20094930 16502
63c3a66f 16503 if (tg3_flag(tp, ICH_WORKAROUND)) {
6892914f
MC		 16504 tp->read32 = tg3_read_indirect_reg32;
16505 tp->write32 = tg3_write_indirect_reg32;
16506 tp->read32_mbox = tg3_read_indirect_mbox;
16507 tp->write32_mbox = tg3_write_indirect_mbox;
16508 tp->write32_tx_mbox = tg3_write_indirect_mbox;
16509 tp->write32_rx_mbox = tg3_write_indirect_mbox;
16510
16511 iounmap(tp->regs);
22abe310 16512 tp->regs = NULL;
6892914f
MC		 16513
16514 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
16515 pci_cmd &= ~PCI_COMMAND_MEMORY;
16516 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
16517 }
4153577a 16518 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
b5d3772c
MC		 16519 tp->read32_mbox = tg3_read32_mbox_5906;
16520 tp->write32_mbox = tg3_write32_mbox_5906;
16521 tp->write32_tx_mbox = tg3_write32_mbox_5906;
16522 tp->write32_rx_mbox = tg3_write32_mbox_5906;
16523 }
6892914f 16524
bbadf503 16525 if (tp->write32 == tg3_write_indirect_reg32 ||
63c3a66f 16526 (tg3_flag(tp, PCIX_MODE) &&
4153577a
JP		 16527 (tg3_asic_rev(tp) == ASIC_REV_5700 ||
16528 tg3_asic_rev(tp) == ASIC_REV_5701)))
63c3a66f 16529 tg3_flag_set(tp, SRAM_USE_CONFIG);
bbadf503 16530
16821285
MC		 16531 /* The memory arbiter has to be enabled in order for SRAM accesses
16532 * to succeed. Normally on powerup the tg3 chip firmware will make
16533 * sure it is enabled, but other entities such as system netboot
16534 * code might disable it.
16535 */
16536 val = tr32(MEMARB_MODE);
16537 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
16538
9dc5e342 16539 tp->pci_fn = PCI_FUNC(tp->pdev->devfn) & 3;
4153577a 16540 if (tg3_asic_rev(tp) == ASIC_REV_5704 ||
9dc5e342
MC		 16541 tg3_flag(tp, 5780_CLASS)) {
16542 if (tg3_flag(tp, PCIX_MODE)) {
16543 pci_read_config_dword(tp->pdev,
16544 tp->pcix_cap + PCI_X_STATUS,
16545 &val);
16546 tp->pci_fn = val & 0x7;
16547 }
4153577a
JP		 16548 } else if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
16549 tg3_asic_rev(tp) == ASIC_REV_5719 ||
16550 tg3_asic_rev(tp) == ASIC_REV_5720) {
9dc5e342 16551 tg3_read_mem(tp, NIC_SRAM_CPMU_STATUS, &val);
857001f0
MC		 16552 if ((val & NIC_SRAM_CPMUSTAT_SIG_MSK) != NIC_SRAM_CPMUSTAT_SIG)
16553 val = tr32(TG3_CPMU_STATUS);
16554
4153577a 16555 if (tg3_asic_rev(tp) == ASIC_REV_5717)
857001f0
MC		 16556 tp->pci_fn = (val & TG3_CPMU_STATUS_FMSK_5717) ? 1 : 0;
16557 else
9dc5e342
MC		 16558 tp->pci_fn = (val & TG3_CPMU_STATUS_FMSK_5719) >>
16559 TG3_CPMU_STATUS_FSHFT_5719;
69f11c99
MC		 16560 }
16561
7e6c63f0
HM		 16562 if (tg3_flag(tp, FLUSH_POSTED_WRITES)) {
16563 tp->write32_tx_mbox = tg3_write_flush_reg32;
16564 tp->write32_rx_mbox = tg3_write_flush_reg32;
16565 }
16566
7d0c41ef 16567 /* Get eeprom hw config before calling tg3_set_power_state().
63c3a66f 16568 * In particular, the TG3_FLAG_IS_NIC flag must be
7d0c41ef
MC		 16569 * determined before calling tg3_set_power_state() so that
16570 * we know whether or not to switch out of Vaux power.
16571 * When the flag is set, it means that GPIO1 is used for eeprom
16572 * write protect and also implies that it is a LOM where GPIOs
16573 * are not used to switch power.
6aa20a22 16574 */
7d0c41ef
MC		 16575 tg3_get_eeprom_hw_cfg(tp);
16576
1caf13eb 16577 if (tg3_flag(tp, FW_TSO) && tg3_flag(tp, ENABLE_ASF)) {
cf9ecf4b
MC		 16578 tg3_flag_clear(tp, TSO_CAPABLE);
16579 tg3_flag_clear(tp, TSO_BUG);
16580 tp->fw_needed = NULL;
16581 }
16582
63c3a66f 16583 if (tg3_flag(tp, ENABLE_APE)) {
0d3031d9
MC		 16584 /* Allow reads and writes to the
16585 * APE register and memory space.
16586 */
16587 pci_state_reg |= PCISTATE_ALLOW_APE_CTLSPC_WR |
f92d9dc1
MC		 16588 PCISTATE_ALLOW_APE_SHMEM_WR |
16589 PCISTATE_ALLOW_APE_PSPACE_WR;
0d3031d9
MC		 16590 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE,
16591 pci_state_reg);
c9cab24e
MC		 16592
16593 tg3_ape_lock_init(tp);
0d3031d9
MC		 16594 }
16595
16821285
MC		 16596 /* Set up tp->grc_local_ctrl before calling
16597 * tg3_pwrsrc_switch_to_vmain(). GPIO1 driven high
16598 * will bring 5700's external PHY out of reset.
314fba34
MC		 16599 * It is also used as eeprom write protect on LOMs.
16600 */
16601 tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
4153577a 16602 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
63c3a66f 16603 tg3_flag(tp, EEPROM_WRITE_PROT))
314fba34
MC		 16604 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
16605 GRC_LCLCTRL_GPIO_OUTPUT1);
3e7d83bc
MC		 16606 /* Unused GPIO3 must be driven as output on 5752 because there
16607 * are no pull-up resistors on unused GPIO pins.
16608 */
4153577a 16609 else if (tg3_asic_rev(tp) == ASIC_REV_5752)
3e7d83bc 16610 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
314fba34 16611
4153577a
JP		 16612 if (tg3_asic_rev(tp) == ASIC_REV_5755 ||
16613 tg3_asic_rev(tp) == ASIC_REV_57780 ||
55086ad9 16614 tg3_flag(tp, 57765_CLASS))
af36e6b6
MC		 16615 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
16616
8d519ab2
MC		 16617 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
16618 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
5f0c4a3c
MC		 16619 /* Turn off the debug UART. */
16620 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
63c3a66f 16621 if (tg3_flag(tp, IS_NIC))
5f0c4a3c
MC		 16622 /* Keep VMain power. */
16623 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
16624 GRC_LCLCTRL_GPIO_OUTPUT0;
16625 }
16626
4153577a 16627 if (tg3_asic_rev(tp) == ASIC_REV_5762)
c86a8560
MC		 16628 tp->grc_local_ctrl |=
16629 tr32(GRC_LOCAL_CTRL) & GRC_LCLCTRL_GPIO_UART_SEL;
16630
16821285
MC		 16631 /* Switch out of Vaux if it is a NIC */
16632 tg3_pwrsrc_switch_to_vmain(tp);
1da177e4 16633
1da177e4
LT		 16634 /* Derive initial jumbo mode from MTU assigned in
16635 * ether_setup() via the alloc_etherdev() call
16636 */
63c3a66f
JP		 16637 if (tp->dev->mtu > ETH_DATA_LEN && !tg3_flag(tp, 5780_CLASS))
16638 tg3_flag_set(tp, JUMBO_RING_ENABLE);
1da177e4
LT		 16639
16640 /* Determine WakeOnLan speed to use. */
4153577a
JP		 16641 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
16642 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0 ||
16643 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B0 ||
16644 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B2) {
63c3a66f 16645 tg3_flag_clear(tp, WOL_SPEED_100MB);
1da177e4 16646 } else {
63c3a66f 16647 tg3_flag_set(tp, WOL_SPEED_100MB);
1da177e4
LT		 16648 }
16649
4153577a 16650 if (tg3_asic_rev(tp) == ASIC_REV_5906)
f07e9af3 16651 tp->phy_flags |= TG3_PHYFLG_IS_FET;
7f97a4bd 16652
1da177e4 16653 /* A few boards don't want Ethernet@WireSpeed phy feature */
4153577a
JP		 16654 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
16655 (tg3_asic_rev(tp) == ASIC_REV_5705 &&
16656 (tg3_chip_rev_id(tp) != CHIPREV_ID_5705_A0) &&
16657 (tg3_chip_rev_id(tp) != CHIPREV_ID_5705_A1)) ||
f07e9af3
MC		 16658 (tp->phy_flags & TG3_PHYFLG_IS_FET) ||
16659 (tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
16660 tp->phy_flags |= TG3_PHYFLG_NO_ETH_WIRE_SPEED;
1da177e4 16661
4153577a
JP		 16662 if (tg3_chip_rev(tp) == CHIPREV_5703_AX ||
16663 tg3_chip_rev(tp) == CHIPREV_5704_AX)
f07e9af3 16664 tp->phy_flags |= TG3_PHYFLG_ADC_BUG;
4153577a 16665 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5704_A0)
f07e9af3 16666 tp->phy_flags |= TG3_PHYFLG_5704_A0_BUG;
1da177e4 16667
63c3a66f 16668 if (tg3_flag(tp, 5705_PLUS) &&
f07e9af3 16669 !(tp->phy_flags & TG3_PHYFLG_IS_FET) &&
4153577a
JP		 16670 tg3_asic_rev(tp) != ASIC_REV_5785 &&
16671 tg3_asic_rev(tp) != ASIC_REV_57780 &&
63c3a66f 16672 !tg3_flag(tp, 57765_PLUS)) {
4153577a
JP		 16673 if (tg3_asic_rev(tp) == ASIC_REV_5755 ||
16674 tg3_asic_rev(tp) == ASIC_REV_5787 ||
16675 tg3_asic_rev(tp) == ASIC_REV_5784 ||
16676 tg3_asic_rev(tp) == ASIC_REV_5761) {
d4011ada
MC		 16677 if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 &&
16678 tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722)
f07e9af3 16679 tp->phy_flags |= TG3_PHYFLG_JITTER_BUG;
c1d2a196 16680 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M)
f07e9af3 16681 tp->phy_flags |= TG3_PHYFLG_ADJUST_TRIM;
321d32a0 16682 } else
f07e9af3 16683 tp->phy_flags |= TG3_PHYFLG_BER_BUG;
c424cb24 16684 }
1da177e4 16685
4153577a
JP		 16686 if (tg3_asic_rev(tp) == ASIC_REV_5784 &&
16687 tg3_chip_rev(tp) != CHIPREV_5784_AX) {
b2a5c19c
MC		 16688 tp->phy_otp = tg3_read_otp_phycfg(tp);
16689 if (tp->phy_otp == 0)
16690 tp->phy_otp = TG3_OTP_DEFAULT;
16691 }
16692
63c3a66f 16693 if (tg3_flag(tp, CPMU_PRESENT))
8ef21428
MC		 16694 tp->mi_mode = MAC_MI_MODE_500KHZ_CONST;
16695 else
16696 tp->mi_mode = MAC_MI_MODE_BASE;
16697
1da177e4 16698 tp->coalesce_mode = 0;
4153577a
JP		 16699 if (tg3_chip_rev(tp) != CHIPREV_5700_AX &&
16700 tg3_chip_rev(tp) != CHIPREV_5700_BX)
1da177e4
LT		 16701 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
16702
4d958473 16703 /* Set these bits to enable statistics workaround. */
4153577a 16704 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
94962f7f 16705 tg3_asic_rev(tp) == ASIC_REV_5762 ||
4153577a
JP		 16706 tg3_chip_rev_id(tp) == CHIPREV_ID_5719_A0 ||
16707 tg3_chip_rev_id(tp) == CHIPREV_ID_5720_A0) {
4d958473
MC		 16708 tp->coalesce_mode |= HOSTCC_MODE_ATTN;
16709 tp->grc_mode |= GRC_MODE_IRQ_ON_FLOW_ATTN;
16710 }
16711
4153577a
JP		 16712 if (tg3_asic_rev(tp) == ASIC_REV_5785 ||
16713 tg3_asic_rev(tp) == ASIC_REV_57780)
63c3a66f 16714 tg3_flag_set(tp, USE_PHYLIB);
57e6983c 16715
158d7abd
MC		 16716 err = tg3_mdio_init(tp);
16717 if (err)
16718 return err;
1da177e4
LT		 16719
16720 /* Initialize data/descriptor byte/word swapping. */
16721 val = tr32(GRC_MODE);
4153577a
JP		 16722 if (tg3_asic_rev(tp) == ASIC_REV_5720 ||
16723 tg3_asic_rev(tp) == ASIC_REV_5762)
f2096f94
MC		 16724 val &= (GRC_MODE_BYTE_SWAP_B2HRX_DATA |
16725 GRC_MODE_WORD_SWAP_B2HRX_DATA |
16726 GRC_MODE_B2HRX_ENABLE |
16727 GRC_MODE_HTX2B_ENABLE |
16728 GRC_MODE_HOST_STACKUP);
16729 else
16730 val &= GRC_MODE_HOST_STACKUP;
16731
1da177e4
LT		 16732 tw32(GRC_MODE, val | tp->grc_mode);
16733
16734 tg3_switch_clocks(tp);
16735
16736 /* Clear this out for sanity. */
16737 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
16738
388d3335
NG		 16739 /* Clear TG3PCI_REG_BASE_ADDR to prevent hangs. */
16740 tw32(TG3PCI_REG_BASE_ADDR, 0);
16741
1da177e4
LT		 16742 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
16743 &pci_state_reg);
16744 if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
63c3a66f 16745 !tg3_flag(tp, PCIX_TARGET_HWBUG)) {
4153577a
JP		 16746 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0 ||
16747 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B0 ||
16748 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B2 ||
16749 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B5) {
1da177e4
LT		 16750 void __iomem *sram_base;
16751
16752 /* Write some dummy words into the SRAM status block
16753 * area, see if it reads back correctly. If the return
16754 * value is bad, force enable the PCIX workaround.
16755 */
16756 sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
16757
16758 writel(0x00000000, sram_base);
16759 writel(0x00000000, sram_base + 4);
16760 writel(0xffffffff, sram_base + 4);
16761 if (readl(sram_base) != 0x00000000)
63c3a66f 16762 tg3_flag_set(tp, PCIX_TARGET_HWBUG);
1da177e4
LT		 16763 }
16764 }
16765
16766 udelay(50);
16767 tg3_nvram_init(tp);
16768
c4dab506
NS		 16769 /* If the device has an NVRAM, no need to load patch firmware */
16770 if (tg3_asic_rev(tp) == ASIC_REV_57766 &&
16771 !tg3_flag(tp, NO_NVRAM))
16772 tp->fw_needed = NULL;
16773
1da177e4
LT		 16774 grc_misc_cfg = tr32(GRC_MISC_CFG);
16775 grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
16776
4153577a 16777 if (tg3_asic_rev(tp) == ASIC_REV_5705 &&
1da177e4
LT		 16778 (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
16779 grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
63c3a66f 16780 tg3_flag_set(tp, IS_5788);
1da177e4 16781
63c3a66f 16782 if (!tg3_flag(tp, IS_5788) &&
4153577a 16783 tg3_asic_rev(tp) != ASIC_REV_5700)
63c3a66f
JP		 16784 tg3_flag_set(tp, TAGGED_STATUS);
16785 if (tg3_flag(tp, TAGGED_STATUS)) {
fac9b83e
DM		 16786 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
16787 HOSTCC_MODE_CLRTICK_TXBD);
16788
16789 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
16790 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
16791 tp->misc_host_ctrl);
16792 }
16793
3bda1258 16794 /* Preserve the APE MAC_MODE bits */
63c3a66f 16795 if (tg3_flag(tp, ENABLE_APE))
d2394e6b 16796 tp->mac_mode = MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
3bda1258 16797 else
6e01b20b 16798 tp->mac_mode = 0;
3bda1258 16799
3d567e0e 16800 if (tg3_10_100_only_device(tp, ent))
f07e9af3 16801 tp->phy_flags |= TG3_PHYFLG_10_100_ONLY;
1da177e4
LT		 16802
16803 err = tg3_phy_probe(tp);
16804 if (err) {
2445e461 16805 dev_err(&tp->pdev->dev, "phy probe failed, err %d\n", err);
1da177e4 16806 /* ... but do not return immediately ... */
b02fd9e3 16807 tg3_mdio_fini(tp);
1da177e4
LT		 16808 }
16809
184b8904 16810 tg3_read_vpd(tp);
c4e6575c 16811 tg3_read_fw_ver(tp);
1da177e4 16812
f07e9af3
MC		 16813 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
16814 tp->phy_flags &= ~TG3_PHYFLG_USE_MI_INTERRUPT;
1da177e4 16815 } else {
4153577a 16816 if (tg3_asic_rev(tp) == ASIC_REV_5700)
f07e9af3 16817 tp->phy_flags |= TG3_PHYFLG_USE_MI_INTERRUPT;
1da177e4 16818 else
f07e9af3 16819 tp->phy_flags &= ~TG3_PHYFLG_USE_MI_INTERRUPT;
1da177e4
LT		 16820 }
16821
16822 /* 5700 {AX,BX} chips have a broken status block link
16823 * change bit implementation, so we must use the
16824 * status register in those cases.
16825 */
4153577a 16826 if (tg3_asic_rev(tp) == ASIC_REV_5700)
63c3a66f 16827 tg3_flag_set(tp, USE_LINKCHG_REG);
1da177e4 16828 else
63c3a66f 16829 tg3_flag_clear(tp, USE_LINKCHG_REG);
1da177e4
LT		 16830
16831 /* The led_ctrl is set during tg3_phy_probe, here we might
16832 * have to force the link status polling mechanism based
16833 * upon subsystem IDs.
16834 */
16835 if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
4153577a 16836 tg3_asic_rev(tp) == ASIC_REV_5701 &&
f07e9af3
MC		 16837 !(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
16838 tp->phy_flags |= TG3_PHYFLG_USE_MI_INTERRUPT;
63c3a66f 16839 tg3_flag_set(tp, USE_LINKCHG_REG);
1da177e4
LT		 16840 }
16841
16842 /* For all SERDES we poll the MAC status register. */
f07e9af3 16843 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
63c3a66f 16844 tg3_flag_set(tp, POLL_SERDES);
1da177e4 16845 else
63c3a66f 16846 tg3_flag_clear(tp, POLL_SERDES);
1da177e4 16847
1743b83c
NS		 16848 if (tg3_flag(tp, ENABLE_APE) && tg3_flag(tp, ENABLE_ASF))
16849 tg3_flag_set(tp, POLL_CPMU_LINK);
16850
9205fd9c 16851 tp->rx_offset = NET_SKB_PAD + NET_IP_ALIGN;
d2757fc4 16852 tp->rx_copy_thresh = TG3_RX_COPY_THRESHOLD;
4153577a 16853 if (tg3_asic_rev(tp) == ASIC_REV_5701 &&
63c3a66f 16854 tg3_flag(tp, PCIX_MODE)) {
9205fd9c 16855 tp->rx_offset = NET_SKB_PAD;
d2757fc4 16856#ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
9dc7a113 16857 tp->rx_copy_thresh = ~(u16)0;
d2757fc4
MC		 16858#endif
16859 }
1da177e4 16860
2c49a44d
MC		 16861 tp->rx_std_ring_mask = TG3_RX_STD_RING_SIZE(tp) - 1;
16862 tp->rx_jmb_ring_mask = TG3_RX_JMB_RING_SIZE(tp) - 1;
7cb32cf2
MC		 16863 tp->rx_ret_ring_mask = tg3_rx_ret_ring_size(tp) - 1;
16864
2c49a44d 16865 tp->rx_std_max_post = tp->rx_std_ring_mask + 1;
f92905de
MC		 16866
16867 /* Increment the rx prod index on the rx std ring by at most
16868 * 8 for these chips to workaround hw errata.
16869 */
4153577a
JP		 16870 if (tg3_asic_rev(tp) == ASIC_REV_5750 ||
16871 tg3_asic_rev(tp) == ASIC_REV_5752 ||
16872 tg3_asic_rev(tp) == ASIC_REV_5755)
f92905de
MC		 16873 tp->rx_std_max_post = 8;
16874
63c3a66f 16875 if (tg3_flag(tp, ASPM_WORKAROUND))
8ed5d97e
MC		 16876 tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) &
16877 PCIE_PWR_MGMT_L1_THRESH_MSK;
16878
1da177e4
LT		 16879 return err;
16880}
16881
49b6e95f 16882#ifdef CONFIG_SPARC
229b1ad1 16883static int tg3_get_macaddr_sparc(struct tg3 *tp)
1da177e4
LT		 16884{
16885 struct net_device *dev = tp->dev;
16886 struct pci_dev *pdev = tp->pdev;
49b6e95f 16887 struct device_node *dp = pci_device_to_OF_node(pdev);
374d4cac 16888 const unsigned char *addr;
49b6e95f
DM		 16889 int len;
16890
16891 addr = of_get_property(dp, "local-mac-address", &len);
d458cdf7
JP		 16892 if (addr && len == ETH_ALEN) {
16893 memcpy(dev->dev_addr, addr, ETH_ALEN);
49b6e95f 16894 return 0;
1da177e4
LT		 16895 }
16896 return -ENODEV;
16897}
16898
229b1ad1 16899static int tg3_get_default_macaddr_sparc(struct tg3 *tp)
1da177e4
LT		 16900{
16901 struct net_device *dev = tp->dev;
16902
d458cdf7 16903 memcpy(dev->dev_addr, idprom->id_ethaddr, ETH_ALEN);
1da177e4
LT		 16904 return 0;
16905}
16906#endif
16907
229b1ad1 16908static int tg3_get_device_address(struct tg3 *tp)
1da177e4
LT		 16909{
16910 struct net_device *dev = tp->dev;
16911 u32 hi, lo, mac_offset;
008652b3 16912 int addr_ok = 0;
7e6c63f0 16913 int err;
1da177e4 16914
49b6e95f 16915#ifdef CONFIG_SPARC
1da177e4
LT		 16916 if (!tg3_get_macaddr_sparc(tp))
16917 return 0;
16918#endif
16919
7e6c63f0
HM		 16920 if (tg3_flag(tp, IS_SSB_CORE)) {
16921 err = ssb_gige_get_macaddr(tp->pdev, &dev->dev_addr[0]);
16922 if (!err && is_valid_ether_addr(&dev->dev_addr[0]))
16923 return 0;
16924 }
16925
1da177e4 16926 mac_offset = 0x7c;
4153577a 16927 if (tg3_asic_rev(tp) == ASIC_REV_5704 ||
63c3a66f 16928 tg3_flag(tp, 5780_CLASS)) {
1da177e4
LT		 16929 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
16930 mac_offset = 0xcc;
16931 if (tg3_nvram_lock(tp))
16932 tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
16933 else
16934 tg3_nvram_unlock(tp);
63c3a66f 16935 } else if (tg3_flag(tp, 5717_PLUS)) {
69f11c99 16936 if (tp->pci_fn & 1)
a1b950d5 16937 mac_offset = 0xcc;
69f11c99 16938 if (tp->pci_fn > 1)
a50d0796 16939 mac_offset += 0x18c;
4153577a 16940 } else if (tg3_asic_rev(tp) == ASIC_REV_5906)
b5d3772c 16941 mac_offset = 0x10;
1da177e4
LT		 16942
16943 /* First try to get it from MAC address mailbox. */
16944 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
16945 if ((hi >> 16) == 0x484b) {
16946 dev->dev_addr[0] = (hi >> 8) & 0xff;
16947 dev->dev_addr[1] = (hi >> 0) & 0xff;
16948
16949 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
16950 dev->dev_addr[2] = (lo >> 24) & 0xff;
16951 dev->dev_addr[3] = (lo >> 16) & 0xff;
16952 dev->dev_addr[4] = (lo >> 8) & 0xff;
16953 dev->dev_addr[5] = (lo >> 0) & 0xff;
1da177e4 16954
008652b3
MC		 16955 /* Some old bootcode may report a 0 MAC address in SRAM */
16956 addr_ok = is_valid_ether_addr(&dev->dev_addr[0]);
16957 }
16958 if (!addr_ok) {
16959 /* Next, try NVRAM. */
63c3a66f 16960 if (!tg3_flag(tp, NO_NVRAM) &&
df259d8c 16961 !tg3_nvram_read_be32(tp, mac_offset + 0, &hi) &&
6d348f2c 16962 !tg3_nvram_read_be32(tp, mac_offset + 4, &lo)) {
62cedd11
MC		 16963 memcpy(&dev->dev_addr[0], ((char *)&hi) + 2, 2);
16964 memcpy(&dev->dev_addr[2], (char *)&lo, sizeof(lo));
008652b3
MC		 16965 }
16966 /* Finally just fetch it out of the MAC control regs. */
16967 else {
16968 hi = tr32(MAC_ADDR_0_HIGH);
16969 lo = tr32(MAC_ADDR_0_LOW);
16970
16971 dev->dev_addr[5] = lo & 0xff;
16972 dev->dev_addr[4] = (lo >> 8) & 0xff;
16973 dev->dev_addr[3] = (lo >> 16) & 0xff;
16974 dev->dev_addr[2] = (lo >> 24) & 0xff;
16975 dev->dev_addr[1] = hi & 0xff;
16976 dev->dev_addr[0] = (hi >> 8) & 0xff;
16977 }
1da177e4
LT		 16978 }
16979
16980 if (!is_valid_ether_addr(&dev->dev_addr[0])) {
7582a335 16981#ifdef CONFIG_SPARC
1da177e4
LT		 16982 if (!tg3_get_default_macaddr_sparc(tp))
16983 return 0;
16984#endif
16985 return -EINVAL;
16986 }
16987 return 0;
16988}
16989
59e6b434
DM		 16990#define BOUNDARY_SINGLE_CACHELINE 1
16991#define BOUNDARY_MULTI_CACHELINE 2
16992
229b1ad1 16993static u32 tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
59e6b434
DM		 16994{
16995 int cacheline_size;
16996 u8 byte;
16997 int goal;
16998
16999 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
17000 if (byte == 0)
17001 cacheline_size = 1024;
17002 else
17003 cacheline_size = (int) byte * 4;
17004
17005 /* On 5703 and later chips, the boundary bits have no
17006 * effect.
17007 */
4153577a
JP		 17008 if (tg3_asic_rev(tp) != ASIC_REV_5700 &&
17009 tg3_asic_rev(tp) != ASIC_REV_5701 &&
63c3a66f 17010 !tg3_flag(tp, PCI_EXPRESS))
59e6b434
DM		 17011 goto out;
17012
17013#if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
17014 goal = BOUNDARY_MULTI_CACHELINE;
17015#else
17016#if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
17017 goal = BOUNDARY_SINGLE_CACHELINE;
17018#else
17019 goal = 0;
17020#endif
17021#endif
17022
63c3a66f 17023 if (tg3_flag(tp, 57765_PLUS)) {
cbf9ca6c
MC		 17024 val = goal ? 0 : DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
17025 goto out;
17026 }
17027
59e6b434
DM		 17028 if (!goal)
17029 goto out;
17030
17031 /* PCI controllers on most RISC systems tend to disconnect
17032 * when a device tries to burst across a cache-line boundary.
17033 * Therefore, letting tg3 do so just wastes PCI bandwidth.
17034 *
17035 * Unfortunately, for PCI-E there are only limited
17036 * write-side controls for this, and thus for reads
17037 * we will still get the disconnects. We'll also waste
17038 * these PCI cycles for both read and write for chips
17039 * other than 5700 and 5701 which do not implement the
17040 * boundary bits.
17041 */
63c3a66f 17042 if (tg3_flag(tp, PCIX_MODE) && !tg3_flag(tp, PCI_EXPRESS)) {
59e6b434
DM		 17043 switch (cacheline_size) {
17044 case 16:
17045 case 32:
17046 case 64:
17047 case 128:
17048 if (goal == BOUNDARY_SINGLE_CACHELINE) {
17049 val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
17050 DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
17051 } else {
17052 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
17053 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
17054 }
17055 break;
17056
17057 case 256:
17058 val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
17059 DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
17060 break;
17061
17062 default:
17063 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
17064 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
17065 break;
855e1111 17066 }
63c3a66f 17067 } else if (tg3_flag(tp, PCI_EXPRESS)) {
59e6b434
DM		 17068 switch (cacheline_size) {
17069 case 16:
17070 case 32:
17071 case 64:
17072 if (goal == BOUNDARY_SINGLE_CACHELINE) {
17073 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
17074 val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
17075 break;
17076 }
17077 /* fallthrough */
17078 case 128:
17079 default:
17080 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
17081 val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
17082 break;
855e1111 17083 }
59e6b434
DM		 17084 } else {
17085 switch (cacheline_size) {
17086 case 16:
17087 if (goal == BOUNDARY_SINGLE_CACHELINE) {
17088 val |= (DMA_RWCTRL_READ_BNDRY_16 |
17089 DMA_RWCTRL_WRITE_BNDRY_16);
17090 break;
17091 }
17092 /* fallthrough */
17093 case 32:
17094 if (goal == BOUNDARY_SINGLE_CACHELINE) {
17095 val |= (DMA_RWCTRL_READ_BNDRY_32 |
17096 DMA_RWCTRL_WRITE_BNDRY_32);
17097 break;
17098 }
17099 /* fallthrough */
17100 case 64:
17101 if (goal == BOUNDARY_SINGLE_CACHELINE) {
17102 val |= (DMA_RWCTRL_READ_BNDRY_64 |
17103 DMA_RWCTRL_WRITE_BNDRY_64);
17104 break;
17105 }
17106 /* fallthrough */
17107 case 128:
17108 if (goal == BOUNDARY_SINGLE_CACHELINE) {
17109 val |= (DMA_RWCTRL_READ_BNDRY_128 |
17110 DMA_RWCTRL_WRITE_BNDRY_128);
17111 break;
17112 }
17113 /* fallthrough */
17114 case 256:
17115 val |= (DMA_RWCTRL_READ_BNDRY_256 |
17116 DMA_RWCTRL_WRITE_BNDRY_256);
17117 break;
17118 case 512:
17119 val |= (DMA_RWCTRL_READ_BNDRY_512 |
17120 DMA_RWCTRL_WRITE_BNDRY_512);
17121 break;
17122 case 1024:
17123 default:
17124 val |= (DMA_RWCTRL_READ_BNDRY_1024 |
17125 DMA_RWCTRL_WRITE_BNDRY_1024);
17126 break;
855e1111 17127 }
59e6b434
DM		 17128 }
17129
17130out:
17131 return val;
17132}
17133
229b1ad1 17134static int tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma,
953c96e0 17135 int size, bool to_device)
1da177e4
LT		 17136{
17137 struct tg3_internal_buffer_desc test_desc;
17138 u32 sram_dma_descs;
17139 int i, ret;
17140
17141 sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
17142
17143 tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
17144 tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
17145 tw32(RDMAC_STATUS, 0);
17146 tw32(WDMAC_STATUS, 0);
17147
17148 tw32(BUFMGR_MODE, 0);
17149 tw32(FTQ_RESET, 0);
17150
17151 test_desc.addr_hi = ((u64) buf_dma) >> 32;
17152 test_desc.addr_lo = buf_dma & 0xffffffff;
17153 test_desc.nic_mbuf = 0x00002100;
17154 test_desc.len = size;
17155
17156 /*
17157 * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
17158 * the *second* time the tg3 driver was getting loaded after an
17159 * initial scan.
17160 *
17161 * Broadcom tells me:
17162 * ...the DMA engine is connected to the GRC block and a DMA
17163 * reset may affect the GRC block in some unpredictable way...
17164 * The behavior of resets to individual blocks has not been tested.
17165 *
17166 * Broadcom noted the GRC reset will also reset all sub-components.
17167 */
17168 if (to_device) {
17169 test_desc.cqid_sqid = (13 << 8) | 2;
17170
17171 tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
17172 udelay(40);
17173 } else {
17174 test_desc.cqid_sqid = (16 << 8) | 7;
17175
17176 tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
17177 udelay(40);
17178 }
17179 test_desc.flags = 0x00000005;
17180
17181 for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
17182 u32 val;
17183
17184 val = *(((u32 *)&test_desc) + i);
17185 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
17186 sram_dma_descs + (i * sizeof(u32)));
17187 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
17188 }
17189 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
17190
859a5887 17191 if (to_device)
1da177e4 17192 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
859a5887 17193 else
1da177e4 17194 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
1da177e4
LT		 17195
17196 ret = -ENODEV;
17197 for (i = 0; i < 40; i++) {
17198 u32 val;
17199
17200 if (to_device)
17201 val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
17202 else
17203 val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
17204 if ((val & 0xffff) == sram_dma_descs) {
17205 ret = 0;
17206 break;
17207 }
17208
17209 udelay(100);
17210 }
17211
17212 return ret;
17213}
17214
ded7340d 17215#define TEST_BUFFER_SIZE 0x2000
1da177e4 17216
9baa3c34 17217static const struct pci_device_id tg3_dma_wait_state_chipsets[] = {
895950c2
JP		 17218 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
17219 { },
17220};
17221
229b1ad1 17222static int tg3_test_dma(struct tg3 *tp)
1da177e4
LT		 17223{
17224 dma_addr_t buf_dma;
59e6b434 17225 u32 *buf, saved_dma_rwctrl;
cbf9ca6c 17226 int ret = 0;
1da177e4 17227
4bae65c8
MC		 17228 buf = dma_alloc_coherent(&tp->pdev->dev, TEST_BUFFER_SIZE,
17229 &buf_dma, GFP_KERNEL);
1da177e4
LT		 17230 if (!buf) {
17231 ret = -ENOMEM;
17232 goto out_nofree;
17233 }
17234
17235 tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
17236 (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
17237
59e6b434 17238 tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
1da177e4 17239
63c3a66f 17240 if (tg3_flag(tp, 57765_PLUS))
cbf9ca6c
MC		 17241 goto out;
17242
63c3a66f 17243 if (tg3_flag(tp, PCI_EXPRESS)) {
1da177e4
LT		 17244 /* DMA read watermark not used on PCIE */
17245 tp->dma_rwctrl |= 0x00180000;
63c3a66f 17246 } else if (!tg3_flag(tp, PCIX_MODE)) {
4153577a
JP		 17247 if (tg3_asic_rev(tp) == ASIC_REV_5705 ||
17248 tg3_asic_rev(tp) == ASIC_REV_5750)
1da177e4
LT		 17249 tp->dma_rwctrl |= 0x003f0000;
17250 else
17251 tp->dma_rwctrl |= 0x003f000f;
17252 } else {
4153577a
JP		 17253 if (tg3_asic_rev(tp) == ASIC_REV_5703 ||
17254 tg3_asic_rev(tp) == ASIC_REV_5704) {
1da177e4 17255 u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
49afdeb6 17256 u32 read_water = 0x7;
1da177e4 17257
4a29cc2e
MC		 17258 /* If the 5704 is behind the EPB bridge, we can
17259 * do the less restrictive ONE_DMA workaround for
17260 * better performance.
17261 */
63c3a66f 17262 if (tg3_flag(tp, 40BIT_DMA_BUG) &&
4153577a 17263 tg3_asic_rev(tp) == ASIC_REV_5704)
4a29cc2e
MC		 17264 tp->dma_rwctrl |= 0x8000;
17265 else if (ccval == 0x6 || ccval == 0x7)
1da177e4
LT		 17266 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
17267
4153577a 17268 if (tg3_asic_rev(tp) == ASIC_REV_5703)
49afdeb6 17269 read_water = 4;
59e6b434 17270 /* Set bit 23 to enable PCIX hw bug fix */
49afdeb6
MC		 17271 tp->dma_rwctrl |=
17272 (read_water << DMA_RWCTRL_READ_WATER_SHIFT) |
17273 (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
17274 (1 << 23);
4153577a 17275 } else if (tg3_asic_rev(tp) == ASIC_REV_5780) {
4cf78e4f
MC		 17276 /* 5780 always in PCIX mode */
17277 tp->dma_rwctrl |= 0x00144000;
4153577a 17278 } else if (tg3_asic_rev(tp) == ASIC_REV_5714) {
a4e2b347
MC		 17279 /* 5714 always in PCIX mode */
17280 tp->dma_rwctrl |= 0x00148000;
1da177e4
LT		 17281 } else {
17282 tp->dma_rwctrl |= 0x001b000f;
17283 }
17284 }
7e6c63f0
HM		 17285 if (tg3_flag(tp, ONE_DMA_AT_ONCE))
17286 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
1da177e4 17287
4153577a
JP		 17288 if (tg3_asic_rev(tp) == ASIC_REV_5703 ||
17289 tg3_asic_rev(tp) == ASIC_REV_5704)
1da177e4
LT		 17290 tp->dma_rwctrl &= 0xfffffff0;
17291
4153577a
JP		 17292 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
17293 tg3_asic_rev(tp) == ASIC_REV_5701) {
1da177e4
LT		 17294 /* Remove this if it causes problems for some boards. */
17295 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
17296
17297 /* On 5700/5701 chips, we need to set this bit.
17298 * Otherwise the chip will issue cacheline transactions
17299 * to streamable DMA memory with not all the byte
17300 * enables turned on. This is an error on several
17301 * RISC PCI controllers, in particular sparc64.
17302 *
17303 * On 5703/5704 chips, this bit has been reassigned
17304 * a different meaning. In particular, it is used
17305 * on those chips to enable a PCI-X workaround.
17306 */
17307 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
17308 }
17309
17310 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
17311
1da177e4 17312
4153577a
JP		 17313 if (tg3_asic_rev(tp) != ASIC_REV_5700 &&
17314 tg3_asic_rev(tp) != ASIC_REV_5701)
1da177e4
LT		 17315 goto out;
17316
59e6b434
DM		 17317 /* It is best to perform DMA test with maximum write burst size
17318 * to expose the 5700/5701 write DMA bug.
17319 */
17320 saved_dma_rwctrl = tp->dma_rwctrl;
17321 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
17322 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
17323
1da177e4
LT		 17324 while (1) {
17325 u32 *p = buf, i;
17326
17327 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
17328 p[i] = i;
17329
17330 /* Send the buffer to the chip. */
953c96e0 17331 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, true);
1da177e4 17332 if (ret) {
2445e461
MC		 17333 dev_err(&tp->pdev->dev,
17334 "%s: Buffer write failed. err = %d\n",
17335 __func__, ret);
1da177e4
LT		 17336 break;
17337 }
17338
1da177e4 17339 /* Now read it back. */
953c96e0 17340 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, false);
1da177e4 17341 if (ret) {
5129c3a3
MC		 17342 dev_err(&tp->pdev->dev, "%s: Buffer read failed. "
17343 "err = %d\n", __func__, ret);
1da177e4
LT		 17344 break;
17345 }
17346
17347 /* Verify it. */
17348 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
17349 if (p[i] == i)
17350 continue;
17351
59e6b434
DM		 17352 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
17353 DMA_RWCTRL_WRITE_BNDRY_16) {
17354 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
1da177e4
LT		 17355 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
17356 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
17357 break;
17358 } else {
2445e461
MC		 17359 dev_err(&tp->pdev->dev,
17360 "%s: Buffer corrupted on read back! "
17361 "(%d != %d)\n", __func__, p[i], i);
1da177e4
LT		 17362 ret = -ENODEV;
17363 goto out;
17364 }
17365 }
17366
17367 if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
17368 /* Success. */
17369 ret = 0;
17370 break;
17371 }
17372 }
59e6b434
DM		 17373 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
17374 DMA_RWCTRL_WRITE_BNDRY_16) {
17375 /* DMA test passed without adjusting DMA boundary,
6d1cfbab
MC		 17376 * now look for chipsets that are known to expose the
17377 * DMA bug without failing the test.
59e6b434 17378 */
4143470c 17379 if (pci_dev_present(tg3_dma_wait_state_chipsets)) {
6d1cfbab
MC		 17380 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
17381 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
859a5887 17382 } else {
6d1cfbab
MC		 17383 /* Safe to use the calculated DMA boundary. */
17384 tp->dma_rwctrl = saved_dma_rwctrl;
859a5887 17385 }
6d1cfbab 17386
59e6b434
DM		 17387 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
17388 }
1da177e4
LT		 17389
17390out:
4bae65c8 17391 dma_free_coherent(&tp->pdev->dev, TEST_BUFFER_SIZE, buf, buf_dma);
1da177e4
LT		 17392out_nofree:
17393 return ret;
17394}
17395
229b1ad1 17396static void tg3_init_bufmgr_config(struct tg3 *tp)
1da177e4 17397{
63c3a66f 17398 if (tg3_flag(tp, 57765_PLUS)) {
666bc831
MC		 17399 tp->bufmgr_config.mbuf_read_dma_low_water =
17400 DEFAULT_MB_RDMA_LOW_WATER_5705;
17401 tp->bufmgr_config.mbuf_mac_rx_low_water =
17402 DEFAULT_MB_MACRX_LOW_WATER_57765;
17403 tp->bufmgr_config.mbuf_high_water =
17404 DEFAULT_MB_HIGH_WATER_57765;
17405
17406 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
17407 DEFAULT_MB_RDMA_LOW_WATER_5705;
17408 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
17409 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_57765;
17410 tp->bufmgr_config.mbuf_high_water_jumbo =
17411 DEFAULT_MB_HIGH_WATER_JUMBO_57765;
63c3a66f 17412 } else if (tg3_flag(tp, 5705_PLUS)) {
fdfec172
MC		 17413 tp->bufmgr_config.mbuf_read_dma_low_water =
17414 DEFAULT_MB_RDMA_LOW_WATER_5705;
17415 tp->bufmgr_config.mbuf_mac_rx_low_water =
17416 DEFAULT_MB_MACRX_LOW_WATER_5705;
17417 tp->bufmgr_config.mbuf_high_water =
17418 DEFAULT_MB_HIGH_WATER_5705;
4153577a 17419 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
b5d3772c
MC		 17420 tp->bufmgr_config.mbuf_mac_rx_low_water =
17421 DEFAULT_MB_MACRX_LOW_WATER_5906;
17422 tp->bufmgr_config.mbuf_high_water =
17423 DEFAULT_MB_HIGH_WATER_5906;
17424 }
fdfec172
MC		 17425
17426 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
17427 DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
17428 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
17429 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780;
17430 tp->bufmgr_config.mbuf_high_water_jumbo =
17431 DEFAULT_MB_HIGH_WATER_JUMBO_5780;
17432 } else {
17433 tp->bufmgr_config.mbuf_read_dma_low_water =
17434 DEFAULT_MB_RDMA_LOW_WATER;
17435 tp->bufmgr_config.mbuf_mac_rx_low_water =
17436 DEFAULT_MB_MACRX_LOW_WATER;
17437 tp->bufmgr_config.mbuf_high_water =
17438 DEFAULT_MB_HIGH_WATER;
17439
17440 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
17441 DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
17442 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
17443 DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
17444 tp->bufmgr_config.mbuf_high_water_jumbo =
17445 DEFAULT_MB_HIGH_WATER_JUMBO;
17446 }
1da177e4
LT		 17447
17448 tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
17449 tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
17450}
17451
229b1ad1 17452static char *tg3_phy_string(struct tg3 *tp)
1da177e4 17453{
79eb6904
MC		 17454 switch (tp->phy_id & TG3_PHY_ID_MASK) {
17455 case TG3_PHY_ID_BCM5400: return "5400";
17456 case TG3_PHY_ID_BCM5401: return "5401";
17457 case TG3_PHY_ID_BCM5411: return "5411";
17458 case TG3_PHY_ID_BCM5701: return "5701";
17459 case TG3_PHY_ID_BCM5703: return "5703";
17460 case TG3_PHY_ID_BCM5704: return "5704";
17461 case TG3_PHY_ID_BCM5705: return "5705";
17462 case TG3_PHY_ID_BCM5750: return "5750";
17463 case TG3_PHY_ID_BCM5752: return "5752";
17464 case TG3_PHY_ID_BCM5714: return "5714";
17465 case TG3_PHY_ID_BCM5780: return "5780";
17466 case TG3_PHY_ID_BCM5755: return "5755";
17467 case TG3_PHY_ID_BCM5787: return "5787";
17468 case TG3_PHY_ID_BCM5784: return "5784";
17469 case TG3_PHY_ID_BCM5756: return "5722/5756";
17470 case TG3_PHY_ID_BCM5906: return "5906";
17471 case TG3_PHY_ID_BCM5761: return "5761";
17472 case TG3_PHY_ID_BCM5718C: return "5718C";
17473 case TG3_PHY_ID_BCM5718S: return "5718S";
17474 case TG3_PHY_ID_BCM57765: return "57765";
302b500b 17475 case TG3_PHY_ID_BCM5719C: return "5719C";
6418f2c1 17476 case TG3_PHY_ID_BCM5720C: return "5720C";
c65a17f4 17477 case TG3_PHY_ID_BCM5762: return "5762C";
79eb6904 17478 case TG3_PHY_ID_BCM8002: return "8002/serdes";
1da177e4
LT		 17479 case 0: return "serdes";
17480 default: return "unknown";
855e1111 17481 }
1da177e4
LT		 17482}
17483
229b1ad1 17484static char *tg3_bus_string(struct tg3 *tp, char *str)
f9804ddb 17485{
63c3a66f 17486 if (tg3_flag(tp, PCI_EXPRESS)) {
f9804ddb
MC		 17487 strcpy(str, "PCI Express");
17488 return str;
63c3a66f 17489 } else if (tg3_flag(tp, PCIX_MODE)) {
f9804ddb
MC		 17490 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
17491
17492 strcpy(str, "PCIX:");
17493
17494 if ((clock_ctrl == 7) ||
17495 ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) ==
17496 GRC_MISC_CFG_BOARD_ID_5704CIOBE))
17497 strcat(str, "133MHz");
17498 else if (clock_ctrl == 0)
17499 strcat(str, "33MHz");
17500 else if (clock_ctrl == 2)
17501 strcat(str, "50MHz");
17502 else if (clock_ctrl == 4)
17503 strcat(str, "66MHz");
17504 else if (clock_ctrl == 6)
17505 strcat(str, "100MHz");
f9804ddb
MC		 17506 } else {
17507 strcpy(str, "PCI:");
63c3a66f 17508 if (tg3_flag(tp, PCI_HIGH_SPEED))
f9804ddb
MC		 17509 strcat(str, "66MHz");
17510 else
17511 strcat(str, "33MHz");
17512 }
63c3a66f 17513 if (tg3_flag(tp, PCI_32BIT))
f9804ddb
MC		 17514 strcat(str, ":32-bit");
17515 else
17516 strcat(str, ":64-bit");
17517 return str;
17518}
17519
229b1ad1 17520static void tg3_init_coal(struct tg3 *tp)
15f9850d
DM		 17521{
17522 struct ethtool_coalesce *ec = &tp->coal;
17523
17524 memset(ec, 0, sizeof(*ec));
17525 ec->cmd = ETHTOOL_GCOALESCE;
17526 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
17527 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
17528 ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
17529 ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
17530 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
17531 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
17532 ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
17533 ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
17534 ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
17535
17536 if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
17537 HOSTCC_MODE_CLRTICK_TXBD)) {
17538 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
17539 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
17540 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
17541 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
17542 }
d244c892 17543
63c3a66f 17544 if (tg3_flag(tp, 5705_PLUS)) {
d244c892
MC		 17545 ec->rx_coalesce_usecs_irq = 0;
17546 ec->tx_coalesce_usecs_irq = 0;
17547 ec->stats_block_coalesce_usecs = 0;
17548 }
15f9850d
DM		 17549}
17550
229b1ad1 17551static int tg3_init_one(struct pci_dev *pdev,
1da177e4
LT		 17552 const struct pci_device_id *ent)
17553{
1da177e4
LT		 17554 struct net_device *dev;
17555 struct tg3 *tp;
5865fc1b 17556 int i, err;
646c9edd 17557 u32 sndmbx, rcvmbx, intmbx;
f9804ddb 17558 char str[40];
72f2afb8 17559 u64 dma_mask, persist_dma_mask;
c8f44aff 17560 netdev_features_t features = 0;
1da177e4 17561
05dbe005 17562 printk_once(KERN_INFO "%s\n", version);
1da177e4
LT		 17563
17564 err = pci_enable_device(pdev);
17565 if (err) {
2445e461 17566 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
1da177e4
LT		 17567 return err;
17568 }
17569
1da177e4
LT		 17570 err = pci_request_regions(pdev, DRV_MODULE_NAME);
17571 if (err) {
2445e461 17572 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n");
1da177e4
LT		 17573 goto err_out_disable_pdev;
17574 }
17575
17576 pci_set_master(pdev);
17577
fe5f5787 17578 dev = alloc_etherdev_mq(sizeof(*tp), TG3_IRQ_MAX_VECS);
1da177e4 17579 if (!dev) {
1da177e4 17580 err = -ENOMEM;
5865fc1b 17581 goto err_out_free_res;
1da177e4
LT		 17582 }
17583
1da177e4
LT		 17584 SET_NETDEV_DEV(dev, &pdev->dev);
17585
1da177e4
LT		 17586 tp = netdev_priv(dev);
17587 tp->pdev = pdev;
17588 tp->dev = dev;
1da177e4
LT		 17589 tp->rx_mode = TG3_DEF_RX_MODE;
17590 tp->tx_mode = TG3_DEF_TX_MODE;
9c13cb8b 17591 tp->irq_sync = 1;
0486a063 17592 tp->pcierr_recovery = false;
8ef21428 17593
1da177e4
LT		 17594 if (tg3_debug > 0)
17595 tp->msg_enable = tg3_debug;
17596 else
17597 tp->msg_enable = TG3_DEF_MSG_ENABLE;
17598
7e6c63f0
HM		 17599 if (pdev_is_ssb_gige_core(pdev)) {
17600 tg3_flag_set(tp, IS_SSB_CORE);
17601 if (ssb_gige_must_flush_posted_writes(pdev))
17602 tg3_flag_set(tp, FLUSH_POSTED_WRITES);
17603 if (ssb_gige_one_dma_at_once(pdev))
17604 tg3_flag_set(tp, ONE_DMA_AT_ONCE);
ee002b64
HM		 17605 if (ssb_gige_have_roboswitch(pdev)) {
17606 tg3_flag_set(tp, USE_PHYLIB);
7e6c63f0 17607 tg3_flag_set(tp, ROBOSWITCH);
ee002b64 17608 }
7e6c63f0
HM		 17609 if (ssb_gige_is_rgmii(pdev))
17610 tg3_flag_set(tp, RGMII_MODE);
17611 }
17612
1da177e4
LT		 17613 /* The word/byte swap controls here control register access byte
17614 * swapping. DMA data byte swapping is controlled in the GRC_MODE
17615 * setting below.
17616 */
17617 tp->misc_host_ctrl =
17618 MISC_HOST_CTRL_MASK_PCI_INT |
17619 MISC_HOST_CTRL_WORD_SWAP |
17620 MISC_HOST_CTRL_INDIR_ACCESS |
17621 MISC_HOST_CTRL_PCISTATE_RW;
17622
17623 /* The NONFRM (non-frame) byte/word swap controls take effect
17624 * on descriptor entries, anything which isn't packet data.
17625 *
17626 * The StrongARM chips on the board (one for tx, one for rx)
17627 * are running in big-endian mode.
17628 */
17629 tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
17630 GRC_MODE_WSWAP_NONFRM_DATA);
17631#ifdef __BIG_ENDIAN
17632 tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
17633#endif
17634 spin_lock_init(&tp->lock);
1da177e4 17635 spin_lock_init(&tp->indirect_lock);
c4028958 17636 INIT_WORK(&tp->reset_task, tg3_reset_task);
1da177e4 17637
d5fe488a 17638 tp->regs = pci_ioremap_bar(pdev, BAR_0);
ab0049b4 17639 if (!tp->regs) {
ab96b241 17640 dev_err(&pdev->dev, "Cannot map device registers, aborting\n");
1da177e4
LT		 17641 err = -ENOMEM;
17642 goto err_out_free_dev;
17643 }
17644
c9cab24e
MC		 17645 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
17646 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761E ||
17647 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S ||
17648 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761SE ||
17649 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 ||
79d49695 17650 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717_C ||
c9cab24e
MC		 17651 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 ||
17652 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5719 ||
c65a17f4 17653 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5720 ||
68273712
NS		 17654 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57767 ||
17655 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57764 ||
c65a17f4
MC		 17656 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5762 ||
17657 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5725 ||
68273712
NS		 17658 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5727 ||
17659 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57787) {
c9cab24e
MC		 17660 tg3_flag_set(tp, ENABLE_APE);
17661 tp->aperegs = pci_ioremap_bar(pdev, BAR_2);
17662 if (!tp->aperegs) {
17663 dev_err(&pdev->dev,
17664 "Cannot map APE registers, aborting\n");
17665 err = -ENOMEM;
17666 goto err_out_iounmap;
17667 }
17668 }
17669
1da177e4
LT		 17670 tp->rx_pending = TG3_DEF_RX_RING_PENDING;
17671 tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
1da177e4 17672
1da177e4 17673 dev->ethtool_ops = &tg3_ethtool_ops;
1da177e4 17674 dev->watchdog_timeo = TG3_TX_TIMEOUT;
2ffcc981 17675 dev->netdev_ops = &tg3_netdev_ops;
1da177e4 17676 dev->irq = pdev->irq;
1da177e4 17677
3d567e0e 17678 err = tg3_get_invariants(tp, ent);
1da177e4 17679 if (err) {
ab96b241
MC		 17680 dev_err(&pdev->dev,
17681 "Problem fetching invariants of chip, aborting\n");
c9cab24e 17682 goto err_out_apeunmap;
1da177e4
LT		 17683 }
17684
4a29cc2e
MC		 17685 /* The EPB bridge inside 5714, 5715, and 5780 and any
17686 * device behind the EPB cannot support DMA addresses > 40-bit.
72f2afb8
MC		 17687 * On 64-bit systems with IOMMU, use 40-bit dma_mask.
17688 * On 64-bit systems without IOMMU, use 64-bit dma_mask and
17689 * do DMA address check in tg3_start_xmit().
17690 */
63c3a66f 17691 if (tg3_flag(tp, IS_5788))
284901a9 17692 persist_dma_mask = dma_mask = DMA_BIT_MASK(32);
63c3a66f 17693 else if (tg3_flag(tp, 40BIT_DMA_BUG)) {
50cf156a 17694 persist_dma_mask = dma_mask = DMA_BIT_MASK(40);
72f2afb8 17695#ifdef CONFIG_HIGHMEM
6a35528a 17696 dma_mask = DMA_BIT_MASK(64);
72f2afb8 17697#endif
4a29cc2e 17698 } else
6a35528a 17699 persist_dma_mask = dma_mask = DMA_BIT_MASK(64);
72f2afb8
MC		 17700
17701 /* Configure DMA attributes. */
284901a9 17702 if (dma_mask > DMA_BIT_MASK(32)) {
72f2afb8
MC		 17703 err = pci_set_dma_mask(pdev, dma_mask);
17704 if (!err) {
0da0606f 17705 features |= NETIF_F_HIGHDMA;
72f2afb8
MC		 17706 err = pci_set_consistent_dma_mask(pdev,
17707 persist_dma_mask);
17708 if (err < 0) {
ab96b241
MC		 17709 dev_err(&pdev->dev, "Unable to obtain 64 bit "
17710 "DMA for consistent allocations\n");
c9cab24e 17711 goto err_out_apeunmap;
72f2afb8
MC		 17712 }
17713 }
17714 }
284901a9
YH		 17715 if (err || dma_mask == DMA_BIT_MASK(32)) {
17716 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
72f2afb8 17717 if (err) {
ab96b241
MC		 17718 dev_err(&pdev->dev,
17719 "No usable DMA configuration, aborting\n");
c9cab24e 17720 goto err_out_apeunmap;
72f2afb8
MC		 17721 }
17722 }
17723
fdfec172 17724 tg3_init_bufmgr_config(tp);
1da177e4 17725
0da0606f
MC		 17726 /* 5700 B0 chips do not support checksumming correctly due
17727 * to hardware bugs.
17728 */
4153577a 17729 if (tg3_chip_rev_id(tp) != CHIPREV_ID_5700_B0) {
0da0606f
MC		 17730 features |= NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_RXCSUM;
17731
17732 if (tg3_flag(tp, 5755_PLUS))
17733 features |= NETIF_F_IPV6_CSUM;
17734 }
17735
4e3a7aaa
MC		 17736 /* TSO is on by default on chips that support hardware TSO.
17737 * Firmware TSO on older chips gives lower performance, so it
17738 * is off by default, but can be enabled using ethtool.
17739 */
63c3a66f
JP		 17740 if ((tg3_flag(tp, HW_TSO_1) ||
17741 tg3_flag(tp, HW_TSO_2) ||
17742 tg3_flag(tp, HW_TSO_3)) &&
0da0606f
MC		 17743 (features & NETIF_F_IP_CSUM))
17744 features |= NETIF_F_TSO;
63c3a66f 17745 if (tg3_flag(tp, HW_TSO_2) || tg3_flag(tp, HW_TSO_3)) {
0da0606f
MC		 17746 if (features & NETIF_F_IPV6_CSUM)
17747 features |= NETIF_F_TSO6;
63c3a66f 17748 if (tg3_flag(tp, HW_TSO_3) ||
4153577a
JP		 17749 tg3_asic_rev(tp) == ASIC_REV_5761 ||
17750 (tg3_asic_rev(tp) == ASIC_REV_5784 &&
17751 tg3_chip_rev(tp) != CHIPREV_5784_AX) ||
17752 tg3_asic_rev(tp) == ASIC_REV_5785 ||
17753 tg3_asic_rev(tp) == ASIC_REV_57780)
0da0606f 17754 features |= NETIF_F_TSO_ECN;
b0026624 17755 }
1da177e4 17756
51dfe7b9
VY		 17757 dev->features |= features | NETIF_F_HW_VLAN_CTAG_TX |
17758 NETIF_F_HW_VLAN_CTAG_RX;
d542fe27
MC		 17759 dev->vlan_features |= features;
17760
06c03c02
MB		 17761 /*
17762 * Add loopback capability only for a subset of devices that support
17763 * MAC-LOOPBACK. Eventually this need to be enhanced to allow INT-PHY
17764 * loopback for the remaining devices.
17765 */
4153577a 17766 if (tg3_asic_rev(tp) != ASIC_REV_5780 &&
06c03c02
MB		 17767 !tg3_flag(tp, CPMU_PRESENT))
17768 /* Add the loopback capability */
0da0606f
MC		 17769 features |= NETIF_F_LOOPBACK;
17770
0da0606f 17771 dev->hw_features |= features;
e565eec3 17772 dev->priv_flags |= IFF_UNICAST_FLT;
06c03c02 17773
4153577a 17774 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5705_A1 &&
63c3a66f 17775 !tg3_flag(tp, TSO_CAPABLE) &&
1da177e4 17776 !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
63c3a66f 17777 tg3_flag_set(tp, MAX_RXPEND_64);
1da177e4
LT		 17778 tp->rx_pending = 63;
17779 }
17780
1da177e4
LT		 17781 err = tg3_get_device_address(tp);
17782 if (err) {
ab96b241
MC		 17783 dev_err(&pdev->dev,
17784 "Could not obtain valid ethernet address, aborting\n");
c9cab24e 17785 goto err_out_apeunmap;
c88864df
MC		 17786 }
17787
1da177e4
LT		 17788 /*
17789 * Reset chip in case UNDI or EFI driver did not shutdown
17790 * DMA self test will enable WDMAC and we'll see (spurious)
17791 * pending DMA on the PCI bus at that point.
17792 */
17793 if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
17794 (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
1da177e4 17795 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
944d980e 17796 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4
LT		 17797 }
17798
17799 err = tg3_test_dma(tp);
17800 if (err) {
ab96b241 17801 dev_err(&pdev->dev, "DMA engine test failed, aborting\n");
c88864df 17802 goto err_out_apeunmap;
1da177e4
LT		 17803 }
17804
78f90dcf
MC		 17805 intmbx = MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW;
17806 rcvmbx = MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW;
17807 sndmbx = MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW;
6fd45cb8 17808 for (i = 0; i < tp->irq_max; i++) {
78f90dcf
MC		 17809 struct tg3_napi *tnapi = &tp->napi[i];
17810
17811 tnapi->tp = tp;
17812 tnapi->tx_pending = TG3_DEF_TX_RING_PENDING;
17813
17814 tnapi->int_mbox = intmbx;
93a700a9 17815 if (i <= 4)
78f90dcf
MC		 17816 intmbx += 0x8;
17817 else
17818 intmbx += 0x4;
17819
17820 tnapi->consmbox = rcvmbx;
17821 tnapi->prodmbox = sndmbx;
17822
66cfd1bd 17823 if (i)
78f90dcf 17824 tnapi->coal_now = HOSTCC_MODE_COAL_VEC1_NOW << (i - 1);
66cfd1bd 17825 else
78f90dcf 17826 tnapi->coal_now = HOSTCC_MODE_NOW;
78f90dcf 17827
63c3a66f 17828 if (!tg3_flag(tp, SUPPORT_MSIX))
78f90dcf
MC		 17829 break;
17830
17831 /*
17832 * If we support MSIX, we'll be using RSS. If we're using
17833 * RSS, the first vector only handles link interrupts and the
17834 * remaining vectors handle rx and tx interrupts. Reuse the
17835 * mailbox values for the next iteration. The values we setup
17836 * above are still useful for the single vectored mode.
17837 */
17838 if (!i)
17839 continue;
17840
17841 rcvmbx += 0x8;
17842
17843 if (sndmbx & 0x4)
17844 sndmbx -= 0x4;
17845 else
17846 sndmbx += 0xc;
17847 }
17848
15f9850d
DM		 17849 tg3_init_coal(tp);
17850
c49a1561
MC		 17851 pci_set_drvdata(pdev, dev);
17852
4153577a
JP		 17853 if (tg3_asic_rev(tp) == ASIC_REV_5719 ||
17854 tg3_asic_rev(tp) == ASIC_REV_5720 ||
17855 tg3_asic_rev(tp) == ASIC_REV_5762)
fb4ce8ad
MC		 17856 tg3_flag_set(tp, PTP_CAPABLE);
17857
21f7638e
MC		 17858 tg3_timer_init(tp);
17859
402e1398
MC		 17860 tg3_carrier_off(tp);
17861
1da177e4
LT		 17862 err = register_netdev(dev);
17863 if (err) {
ab96b241 17864 dev_err(&pdev->dev, "Cannot register net device, aborting\n");
0d3031d9 17865 goto err_out_apeunmap;
1da177e4
LT		 17866 }
17867
05dbe005
JP		 17868 netdev_info(dev, "Tigon3 [partno(%s) rev %04x] (%s) MAC address %pM\n",
17869 tp->board_part_number,
4153577a 17870 tg3_chip_rev_id(tp),
05dbe005
JP		 17871 tg3_bus_string(tp, str),
17872 dev->dev_addr);
1da177e4 17873
f07e9af3 17874 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
3f0e3ad7 17875 struct phy_device *phydev;
ead2402c 17876 phydev = tp->mdio_bus->phy_map[tp->phy_addr];
5129c3a3
MC		 17877 netdev_info(dev,
17878 "attached PHY driver [%s] (mii_bus:phy_addr=%s)\n",
05dbe005 17879 phydev->drv->name, dev_name(&phydev->dev));
f07e9af3
MC		 17880 } else {
17881 char *ethtype;
17882
17883 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
17884 ethtype = "10/100Base-TX";
17885 else if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
17886 ethtype = "1000Base-SX";
17887 else
17888 ethtype = "10/100/1000Base-T";
17889
5129c3a3 17890 netdev_info(dev, "attached PHY is %s (%s Ethernet) "
47007831
MC		 17891 "(WireSpeed[%d], EEE[%d])\n",
17892 tg3_phy_string(tp), ethtype,
17893 (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED) == 0,
17894 (tp->phy_flags & TG3_PHYFLG_EEE_CAP) != 0);
f07e9af3 17895 }
05dbe005
JP		 17896
17897 netdev_info(dev, "RXcsums[%d] LinkChgREG[%d] MIirq[%d] ASF[%d] TSOcap[%d]\n",
dc668910 17898 (dev->features & NETIF_F_RXCSUM) != 0,
63c3a66f 17899 tg3_flag(tp, USE_LINKCHG_REG) != 0,
f07e9af3 17900 (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) != 0,
63c3a66f
JP		 17901 tg3_flag(tp, ENABLE_ASF) != 0,
17902 tg3_flag(tp, TSO_CAPABLE) != 0);
05dbe005
JP		 17903 netdev_info(dev, "dma_rwctrl[%08x] dma_mask[%d-bit]\n",
17904 tp->dma_rwctrl,
17905 pdev->dma_mask == DMA_BIT_MASK(32) ? 32 :
17906 ((u64)pdev->dma_mask) == DMA_BIT_MASK(40) ? 40 : 64);
1da177e4 17907
b45aa2f6
MC		 17908 pci_save_state(pdev);
17909
1da177e4
LT		 17910 return 0;
17911
0d3031d9
MC		 17912err_out_apeunmap:
17913 if (tp->aperegs) {
17914 iounmap(tp->aperegs);
17915 tp->aperegs = NULL;
17916 }
17917
1da177e4 17918err_out_iounmap:
6892914f
MC		 17919 if (tp->regs) {
17920 iounmap(tp->regs);
22abe310 17921 tp->regs = NULL;
6892914f 17922 }
1da177e4
LT		 17923
17924err_out_free_dev:
17925 free_netdev(dev);
17926
17927err_out_free_res:
17928 pci_release_regions(pdev);
17929
17930err_out_disable_pdev:
c80dc13d
GS		 17931 if (pci_is_enabled(pdev))
17932 pci_disable_device(pdev);
1da177e4
LT		 17933 return err;
17934}
17935
229b1ad1 17936static void tg3_remove_one(struct pci_dev *pdev)
1da177e4
LT		 17937{
17938 struct net_device *dev = pci_get_drvdata(pdev);
17939
17940 if (dev) {
17941 struct tg3 *tp = netdev_priv(dev);
17942
e3c5530b 17943 release_firmware(tp->fw);
077f849d 17944
db219973 17945 tg3_reset_task_cancel(tp);
158d7abd 17946
e730c823 17947 if (tg3_flag(tp, USE_PHYLIB)) {
b02fd9e3 17948 tg3_phy_fini(tp);
158d7abd 17949 tg3_mdio_fini(tp);
b02fd9e3 17950 }
158d7abd 17951
1da177e4 17952 unregister_netdev(dev);
0d3031d9
MC		 17953 if (tp->aperegs) {
17954 iounmap(tp->aperegs);
17955 tp->aperegs = NULL;
17956 }
6892914f
MC		 17957 if (tp->regs) {
17958 iounmap(tp->regs);
22abe310 17959 tp->regs = NULL;
6892914f 17960 }
1da177e4
LT		 17961 free_netdev(dev);
17962 pci_release_regions(pdev);
17963 pci_disable_device(pdev);
1da177e4
LT		 17964 }
17965}
17966
aa6027ca 17967#ifdef CONFIG_PM_SLEEP
c866b7ea 17968static int tg3_suspend(struct device *device)
1da177e4 17969{
c866b7ea 17970 struct pci_dev *pdev = to_pci_dev(device);
1da177e4
LT		 17971 struct net_device *dev = pci_get_drvdata(pdev);
17972 struct tg3 *tp = netdev_priv(dev);
8496e85c
RW		 17973 int err = 0;
17974
17975 rtnl_lock();
1da177e4
LT		 17976
17977 if (!netif_running(dev))
8496e85c 17978 goto unlock;
1da177e4 17979
db219973 17980 tg3_reset_task_cancel(tp);
b02fd9e3 17981 tg3_phy_stop(tp);
1da177e4
LT		 17982 tg3_netif_stop(tp);
17983
21f7638e 17984 tg3_timer_stop(tp);
1da177e4 17985
f47c11ee 17986 tg3_full_lock(tp, 1);
1da177e4 17987 tg3_disable_ints(tp);
f47c11ee 17988 tg3_full_unlock(tp);
1da177e4
LT		 17989
17990 netif_device_detach(dev);
17991
f47c11ee 17992 tg3_full_lock(tp, 0);
944d980e 17993 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
63c3a66f 17994 tg3_flag_clear(tp, INIT_COMPLETE);
f47c11ee 17995 tg3_full_unlock(tp);
1da177e4 17996
c866b7ea 17997 err = tg3_power_down_prepare(tp);
1da177e4 17998 if (err) {
b02fd9e3
MC		 17999 int err2;
18000
f47c11ee 18001 tg3_full_lock(tp, 0);
1da177e4 18002
63c3a66f 18003 tg3_flag_set(tp, INIT_COMPLETE);
953c96e0 18004 err2 = tg3_restart_hw(tp, true);
b02fd9e3 18005 if (err2)
b9ec6c1b 18006 goto out;
1da177e4 18007
21f7638e 18008 tg3_timer_start(tp);
1da177e4
LT		 18009
18010 netif_device_attach(dev);
18011 tg3_netif_start(tp);
18012
b9ec6c1b 18013out:
f47c11ee 18014 tg3_full_unlock(tp);
b02fd9e3
MC		 18015
18016 if (!err2)
18017 tg3_phy_start(tp);
1da177e4
LT		 18018 }
18019
8496e85c
RW		 18020unlock:
18021 rtnl_unlock();
1da177e4
LT		 18022 return err;
18023}
18024
c866b7ea 18025static int tg3_resume(struct device *device)
1da177e4 18026{
c866b7ea 18027 struct pci_dev *pdev = to_pci_dev(device);
1da177e4
LT		 18028 struct net_device *dev = pci_get_drvdata(pdev);
18029 struct tg3 *tp = netdev_priv(dev);
8496e85c
RW		 18030 int err = 0;
18031
18032 rtnl_lock();
1da177e4
LT		 18033
18034 if (!netif_running(dev))
8496e85c 18035 goto unlock;
1da177e4 18036
1da177e4
LT		 18037 netif_device_attach(dev);
18038
f47c11ee 18039 tg3_full_lock(tp, 0);
1da177e4 18040
2e460fc0
NS		 18041 tg3_ape_driver_state_change(tp, RESET_KIND_INIT);
18042
63c3a66f 18043 tg3_flag_set(tp, INIT_COMPLETE);
942d1af0
NS		 18044 err = tg3_restart_hw(tp,
18045 !(tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN));
b9ec6c1b
MC		 18046 if (err)
18047 goto out;
1da177e4 18048
21f7638e 18049 tg3_timer_start(tp);
1da177e4 18050
1da177e4
LT		 18051 tg3_netif_start(tp);
18052
b9ec6c1b 18053out:
f47c11ee 18054 tg3_full_unlock(tp);
1da177e4 18055
b02fd9e3
MC		 18056 if (!err)
18057 tg3_phy_start(tp);
18058
8496e85c
RW		 18059unlock:
18060 rtnl_unlock();
b9ec6c1b 18061 return err;
1da177e4 18062}
42df36a6 18063#endif /* CONFIG_PM_SLEEP */
1da177e4 18064
c866b7ea
RW		 18065static SIMPLE_DEV_PM_OPS(tg3_pm_ops, tg3_suspend, tg3_resume);
18066
4c305fa2
NS		 18067static void tg3_shutdown(struct pci_dev *pdev)
18068{
18069 struct net_device *dev = pci_get_drvdata(pdev);
18070 struct tg3 *tp = netdev_priv(dev);
18071
18072 rtnl_lock();
18073 netif_device_detach(dev);
18074
18075 if (netif_running(dev))
18076 dev_close(dev);
18077
18078 if (system_state == SYSTEM_POWER_OFF)
18079 tg3_power_down(tp);
18080
18081 rtnl_unlock();
18082}
18083
b45aa2f6
MC		 18084/**
18085 * tg3_io_error_detected - called when PCI error is detected
18086 * @pdev: Pointer to PCI device
18087 * @state: The current pci connection state
18088 *
18089 * This function is called after a PCI bus error affecting
18090 * this device has been detected.
18091 */
18092static pci_ers_result_t tg3_io_error_detected(struct pci_dev *pdev,
18093 pci_channel_state_t state)
18094{
18095 struct net_device *netdev = pci_get_drvdata(pdev);
18096 struct tg3 *tp = netdev_priv(netdev);
18097 pci_ers_result_t err = PCI_ERS_RESULT_NEED_RESET;
18098
18099 netdev_info(netdev, "PCI I/O error detected\n");
18100
18101 rtnl_lock();
18102
0486a063
IV		 18103 tp->pcierr_recovery = true;
18104
d8af4dfd
GS		 18105 /* We probably don't have netdev yet */
18106 if (!netdev || !netif_running(netdev))
b45aa2f6
MC		 18107 goto done;
18108
18109 tg3_phy_stop(tp);
18110
18111 tg3_netif_stop(tp);
18112
21f7638e 18113 tg3_timer_stop(tp);
b45aa2f6
MC		 18114
18115 /* Want to make sure that the reset task doesn't run */
db219973 18116 tg3_reset_task_cancel(tp);
b45aa2f6
MC		 18117
18118 netif_device_detach(netdev);
18119
18120 /* Clean up software state, even if MMIO is blocked */
18121 tg3_full_lock(tp, 0);
18122 tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
18123 tg3_full_unlock(tp);
18124
18125done:
72bb72b0 18126 if (state == pci_channel_io_perm_failure) {
68293099
DB		 18127 if (netdev) {
18128 tg3_napi_enable(tp);
18129 dev_close(netdev);
18130 }
b45aa2f6 18131 err = PCI_ERS_RESULT_DISCONNECT;
72bb72b0 18132 } else {
b45aa2f6 18133 pci_disable_device(pdev);
72bb72b0 18134 }
b45aa2f6
MC		 18135
18136 rtnl_unlock();
18137
18138 return err;
18139}
18140
18141/**
18142 * tg3_io_slot_reset - called after the pci bus has been reset.
18143 * @pdev: Pointer to PCI device
18144 *
18145 * Restart the card from scratch, as if from a cold-boot.
18146 * At this point, the card has exprienced a hard reset,
18147 * followed by fixups by BIOS, and has its config space
18148 * set up identically to what it was at cold boot.
18149 */
18150static pci_ers_result_t tg3_io_slot_reset(struct pci_dev *pdev)
18151{
18152 struct net_device *netdev = pci_get_drvdata(pdev);
18153 struct tg3 *tp = netdev_priv(netdev);
18154 pci_ers_result_t rc = PCI_ERS_RESULT_DISCONNECT;
18155 int err;
18156
18157 rtnl_lock();
18158
18159 if (pci_enable_device(pdev)) {
68293099
DB		 18160 dev_err(&pdev->dev,
18161 "Cannot re-enable PCI device after reset.\n");
b45aa2f6
MC		 18162 goto done;
18163 }
18164
18165 pci_set_master(pdev);
18166 pci_restore_state(pdev);
18167 pci_save_state(pdev);
18168
68293099 18169 if (!netdev || !netif_running(netdev)) {
b45aa2f6
MC		 18170 rc = PCI_ERS_RESULT_RECOVERED;
18171 goto done;
18172 }
18173
18174 err = tg3_power_up(tp);
bed9829f 18175 if (err)
b45aa2f6 18176 goto done;
b45aa2f6
MC		 18177
18178 rc = PCI_ERS_RESULT_RECOVERED;
18179
18180done:
68293099 18181 if (rc != PCI_ERS_RESULT_RECOVERED && netdev && netif_running(netdev)) {
72bb72b0
MC		 18182 tg3_napi_enable(tp);
18183 dev_close(netdev);
18184 }
b45aa2f6
MC		 18185 rtnl_unlock();
18186
18187 return rc;
18188}
18189
18190/**
18191 * tg3_io_resume - called when traffic can start flowing again.
18192 * @pdev: Pointer to PCI device
18193 *
18194 * This callback is called when the error recovery driver tells
18195 * us that its OK to resume normal operation.
18196 */
18197static void tg3_io_resume(struct pci_dev *pdev)
18198{
18199 struct net_device *netdev = pci_get_drvdata(pdev);
18200 struct tg3 *tp = netdev_priv(netdev);
18201 int err;
18202
18203 rtnl_lock();
18204
18205 if (!netif_running(netdev))
18206 goto done;
18207
18208 tg3_full_lock(tp, 0);
2e460fc0 18209 tg3_ape_driver_state_change(tp, RESET_KIND_INIT);
63c3a66f 18210 tg3_flag_set(tp, INIT_COMPLETE);
953c96e0 18211 err = tg3_restart_hw(tp, true);
b45aa2f6 18212 if (err) {
35763066 18213 tg3_full_unlock(tp);
b45aa2f6
MC		 18214 netdev_err(netdev, "Cannot restart hardware after reset.\n");
18215 goto done;
18216 }
18217
18218 netif_device_attach(netdev);
18219
21f7638e 18220 tg3_timer_start(tp);
b45aa2f6
MC		 18221
18222 tg3_netif_start(tp);
18223
35763066
NNS		 18224 tg3_full_unlock(tp);
18225
b45aa2f6
MC		 18226 tg3_phy_start(tp);
18227
18228done:
0486a063 18229 tp->pcierr_recovery = false;
b45aa2f6
MC		 18230 rtnl_unlock();
18231}
18232
3646f0e5 18233static const struct pci_error_handlers tg3_err_handler = {
b45aa2f6
MC		 18234 .error_detected = tg3_io_error_detected,
18235 .slot_reset = tg3_io_slot_reset,
18236 .resume = tg3_io_resume
18237};
18238
1da177e4
LT		 18239static struct pci_driver tg3_driver = {
18240 .name = DRV_MODULE_NAME,
18241 .id_table = tg3_pci_tbl,
18242 .probe = tg3_init_one,
229b1ad1 18243 .remove = tg3_remove_one,
b45aa2f6 18244 .err_handler = &tg3_err_handler,
42df36a6 18245 .driver.pm = &tg3_pm_ops,
4c305fa2 18246 .shutdown = tg3_shutdown,
1da177e4
LT		 18247};
18248
8dbb0dc2 18249module_pci_driver(tg3_driver);
Linux kernel - Deliverables
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