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ipv4: fix nexthop attlen check in fib_nh_match
[deliverable/linux.git] / drivers / net / ethernet / broadcom / tg3.c
CommitLineData
1da177e4
LT		 1/*
2 * tg3.c: Broadcom Tigon3 ethernet driver.
3 *
4 * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
5 * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
6 * Copyright (C) 2004 Sun Microsystems Inc.
de750e4c 7 * Copyright (C) 2005-2014 Broadcom Corporation.
1da177e4
LT		 8 *
9 * Firmware is:
49cabf49
MC		 10 * Derived from proprietary unpublished source code,
11 * Copyright (C) 2000-2003 Broadcom Corporation.
12 *
13 * Permission is hereby granted for the distribution of this firmware
14 * data in hexadecimal or equivalent format, provided this copyright
15 * notice is accompanying it.
1da177e4
LT		 16 */
17
1da177e4
LT		 18
19#include <linux/module.h>
20#include <linux/moduleparam.h>
6867c843 21#include <linux/stringify.h>
1da177e4
LT		 22#include <linux/kernel.h>
23#include <linux/types.h>
24#include <linux/compiler.h>
25#include <linux/slab.h>
26#include <linux/delay.h>
14c85021 27#include <linux/in.h>
a6b7a407 28#include <linux/interrupt.h>
1da177e4
LT		 29#include <linux/ioport.h>
30#include <linux/pci.h>
31#include <linux/netdevice.h>
32#include <linux/etherdevice.h>
33#include <linux/skbuff.h>
34#include <linux/ethtool.h>
3110f5f5 35#include <linux/mdio.h>
1da177e4 36#include <linux/mii.h>
158d7abd 37#include <linux/phy.h>
a9daf367 38#include <linux/brcmphy.h>
e565eec3 39#include <linux/if.h>
1da177e4
LT		 40#include <linux/if_vlan.h>
41#include <linux/ip.h>
42#include <linux/tcp.h>
43#include <linux/workqueue.h>
61487480 44#include <linux/prefetch.h>
f9a5f7d3 45#include <linux/dma-mapping.h>
077f849d 46#include <linux/firmware.h>
7e6c63f0 47#include <linux/ssb/ssb_driver_gige.h>
aed93e0b
MC		 48#include <linux/hwmon.h>
49#include <linux/hwmon-sysfs.h>
1da177e4
LT		 50
51#include <net/checksum.h>
c9bdd4b5 52#include <net/ip.h>
1da177e4 53
27fd9de8 54#include <linux/io.h>
1da177e4 55#include <asm/byteorder.h>
27fd9de8 56#include <linux/uaccess.h>
1da177e4 57
be947307
MC		 58#include <uapi/linux/net_tstamp.h>
59#include <linux/ptp_clock_kernel.h>
60
49b6e95f 61#ifdef CONFIG_SPARC
1da177e4 62#include <asm/idprom.h>
49b6e95f 63#include <asm/prom.h>
1da177e4
LT		 64#endif
65
63532394
MC		 66#define BAR_0 0
67#define BAR_2 2
68
1da177e4
LT		 69#include "tg3.h"
70
63c3a66f
JP		 71/* Functions & macros to verify TG3_FLAGS types */
72
73static inline int _tg3_flag(enum TG3_FLAGS flag, unsigned long *bits)
74{
75 return test_bit(flag, bits);
76}
77
78static inline void _tg3_flag_set(enum TG3_FLAGS flag, unsigned long *bits)
79{
80 set_bit(flag, bits);
81}
82
83static inline void _tg3_flag_clear(enum TG3_FLAGS flag, unsigned long *bits)
84{
85 clear_bit(flag, bits);
86}
87
88#define tg3_flag(tp, flag) \
89 _tg3_flag(TG3_FLAG_##flag, (tp)->tg3_flags)
90#define tg3_flag_set(tp, flag) \
91 _tg3_flag_set(TG3_FLAG_##flag, (tp)->tg3_flags)
92#define tg3_flag_clear(tp, flag) \
93 _tg3_flag_clear(TG3_FLAG_##flag, (tp)->tg3_flags)
94
1da177e4 95#define DRV_MODULE_NAME "tg3"
6867c843 96#define TG3_MAJ_NUM 3
de750e4c 97#define TG3_MIN_NUM 137
6867c843
MC		 98#define DRV_MODULE_VERSION \
99 __stringify(TG3_MAJ_NUM) "." __stringify(TG3_MIN_NUM)
de750e4c 100#define DRV_MODULE_RELDATE "May 11, 2014"
1da177e4 101
fd6d3f0e
MC		 102#define RESET_KIND_SHUTDOWN 0
103#define RESET_KIND_INIT 1
104#define RESET_KIND_SUSPEND 2
105
1da177e4
LT		 106#define TG3_DEF_RX_MODE 0
107#define TG3_DEF_TX_MODE 0
108#define TG3_DEF_MSG_ENABLE \
109 (NETIF_MSG_DRV | \
110 NETIF_MSG_PROBE | \
111 NETIF_MSG_LINK | \
112 NETIF_MSG_TIMER | \
113 NETIF_MSG_IFDOWN | \
114 NETIF_MSG_IFUP | \
115 NETIF_MSG_RX_ERR | \
116 NETIF_MSG_TX_ERR)
117
520b2756
MC		 118#define TG3_GRC_LCLCTL_PWRSW_DELAY 100
119
1da177e4
LT		 120/* length of time before we decide the hardware is borked,
121 * and dev->tx_timeout() should be called to fix the problem
122 */
63c3a66f 123
1da177e4
LT		 124#define TG3_TX_TIMEOUT (5 * HZ)
125
126/* hardware minimum and maximum for a single frame's data payload */
127#define TG3_MIN_MTU 60
128#define TG3_MAX_MTU(tp) \
63c3a66f 129 (tg3_flag(tp, JUMBO_CAPABLE) ? 9000 : 1500)
1da177e4
LT		 130
131/* These numbers seem to be hard coded in the NIC firmware somehow.
132 * You can't change the ring sizes, but you can change where you place
133 * them in the NIC onboard memory.
134 */
7cb32cf2 135#define TG3_RX_STD_RING_SIZE(tp) \
63c3a66f 136 (tg3_flag(tp, LRG_PROD_RING_CAP) ? \
de9f5230 137 TG3_RX_STD_MAX_SIZE_5717 : TG3_RX_STD_MAX_SIZE_5700)
1da177e4 138#define TG3_DEF_RX_RING_PENDING 200
7cb32cf2 139#define TG3_RX_JMB_RING_SIZE(tp) \
63c3a66f 140 (tg3_flag(tp, LRG_PROD_RING_CAP) ? \
de9f5230 141 TG3_RX_JMB_MAX_SIZE_5717 : TG3_RX_JMB_MAX_SIZE_5700)
1da177e4
LT		 142#define TG3_DEF_RX_JUMBO_RING_PENDING 100
143
144/* Do not place this n-ring entries value into the tp struct itself,
145 * we really want to expose these constants to GCC so that modulo et
146 * al. operations are done with shifts and masks instead of with
147 * hw multiply/modulo instructions. Another solution would be to
148 * replace things like '% foo' with '& (foo - 1)'.
149 */
1da177e4
LT		 150
151#define TG3_TX_RING_SIZE 512
152#define TG3_DEF_TX_RING_PENDING (TG3_TX_RING_SIZE - 1)
153
2c49a44d
MC		 154#define TG3_RX_STD_RING_BYTES(tp) \
155 (sizeof(struct tg3_rx_buffer_desc) * TG3_RX_STD_RING_SIZE(tp))
156#define TG3_RX_JMB_RING_BYTES(tp) \
157 (sizeof(struct tg3_ext_rx_buffer_desc) * TG3_RX_JMB_RING_SIZE(tp))
158#define TG3_RX_RCB_RING_BYTES(tp) \
7cb32cf2 159 (sizeof(struct tg3_rx_buffer_desc) * (tp->rx_ret_ring_mask + 1))
1da177e4
LT		 160#define TG3_TX_RING_BYTES (sizeof(struct tg3_tx_buffer_desc) * \
161 TG3_TX_RING_SIZE)
1da177e4
LT		 162#define NEXT_TX(N) (((N) + 1) & (TG3_TX_RING_SIZE - 1))
163
287be12e
MC		 164#define TG3_DMA_BYTE_ENAB 64
165
166#define TG3_RX_STD_DMA_SZ 1536
167#define TG3_RX_JMB_DMA_SZ 9046
168
169#define TG3_RX_DMA_TO_MAP_SZ(x) ((x) + TG3_DMA_BYTE_ENAB)
170
171#define TG3_RX_STD_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_STD_DMA_SZ)
172#define TG3_RX_JMB_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_JMB_DMA_SZ)
1da177e4 173
2c49a44d
MC		 174#define TG3_RX_STD_BUFF_RING_SIZE(tp) \
175 (sizeof(struct ring_info) * TG3_RX_STD_RING_SIZE(tp))
2b2cdb65 176
2c49a44d
MC		 177#define TG3_RX_JMB_BUFF_RING_SIZE(tp) \
178 (sizeof(struct ring_info) * TG3_RX_JMB_RING_SIZE(tp))
2b2cdb65 179
d2757fc4
MC		 180/* Due to a hardware bug, the 5701 can only DMA to memory addresses
181 * that are at least dword aligned when used in PCIX mode. The driver
182 * works around this bug by double copying the packet. This workaround
183 * is built into the normal double copy length check for efficiency.
184 *
185 * However, the double copy is only necessary on those architectures
186 * where unaligned memory accesses are inefficient. For those architectures
187 * where unaligned memory accesses incur little penalty, we can reintegrate
188 * the 5701 in the normal rx path. Doing so saves a device structure
189 * dereference by hardcoding the double copy threshold in place.
190 */
191#define TG3_RX_COPY_THRESHOLD 256
192#if NET_IP_ALIGN == 0 || defined(CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS)
193 #define TG3_RX_COPY_THRESH(tp) TG3_RX_COPY_THRESHOLD
194#else
195 #define TG3_RX_COPY_THRESH(tp) ((tp)->rx_copy_thresh)
196#endif
197
81389f57
MC		 198#if (NET_IP_ALIGN != 0)
199#define TG3_RX_OFFSET(tp) ((tp)->rx_offset)
200#else
9205fd9c 201#define TG3_RX_OFFSET(tp) (NET_SKB_PAD)
81389f57
MC		 202#endif
203
1da177e4 204/* minimum number of free TX descriptors required to wake up TX process */
f3f3f27e 205#define TG3_TX_WAKEUP_THRESH(tnapi) ((tnapi)->tx_pending / 4)
55086ad9 206#define TG3_TX_BD_DMA_MAX_2K 2048
a4cb428d 207#define TG3_TX_BD_DMA_MAX_4K 4096
1da177e4 208
ad829268
MC		 209#define TG3_RAW_IP_ALIGN 2
210
e565eec3
MC		 211#define TG3_MAX_UCAST_ADDR(tp) (tg3_flag((tp), ENABLE_ASF) ? 2 : 3)
212#define TG3_UCAST_ADDR_IDX(tp) (tg3_flag((tp), ENABLE_ASF) ? 2 : 1)
213
c6cdf436 214#define TG3_FW_UPDATE_TIMEOUT_SEC 5
21f7638e 215#define TG3_FW_UPDATE_FREQ_SEC (TG3_FW_UPDATE_TIMEOUT_SEC / 2)
c6cdf436 216
077f849d 217#define FIRMWARE_TG3 "tigon/tg3.bin"
c4dab506 218#define FIRMWARE_TG357766 "tigon/tg357766.bin"
077f849d
JSR		 219#define FIRMWARE_TG3TSO "tigon/tg3_tso.bin"
220#define FIRMWARE_TG3TSO5 "tigon/tg3_tso5.bin"
221
229b1ad1 222static char version[] =
05dbe005 223 DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")";
1da177e4
LT		 224
225MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
226MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
227MODULE_LICENSE("GPL");
228MODULE_VERSION(DRV_MODULE_VERSION);
077f849d
JSR		 229MODULE_FIRMWARE(FIRMWARE_TG3);
230MODULE_FIRMWARE(FIRMWARE_TG3TSO);
231MODULE_FIRMWARE(FIRMWARE_TG3TSO5);
232
1da177e4
LT		 233static int tg3_debug = -1; /* -1 == use TG3_DEF_MSG_ENABLE as value */
234module_param(tg3_debug, int, 0);
235MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
236
3d567e0e
NNS		 237#define TG3_DRV_DATA_FLAG_10_100_ONLY 0x0001
238#define TG3_DRV_DATA_FLAG_5705_10_100 0x0002
239
9baa3c34 240static const struct pci_device_id tg3_pci_tbl[] = {
13185217
HK		 241 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
242 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
243 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
244 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
245 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
246 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
247 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
248 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
249 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
250 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
251 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
252 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
253 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
254 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
255 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
256 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
257 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
258 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
3d567e0e
NNS		 259 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901),
260 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY |
261 TG3_DRV_DATA_FLAG_5705_10_100},
262 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2),
263 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY |
264 TG3_DRV_DATA_FLAG_5705_10_100},
13185217 265 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
3d567e0e
NNS		 266 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F),
267 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY |
268 TG3_DRV_DATA_FLAG_5705_10_100},
13185217 269 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
126a3368 270 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
7e6c63f0 271 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750)},
13185217 272 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
13185217 273 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
3d567e0e
NNS		 274 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F),
275 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
13185217
HK		 276 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
277 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
278 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
279 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
3d567e0e
NNS		 280 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F),
281 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
13185217
HK		 282 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
283 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
284 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
285 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
126a3368 286 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
13185217
HK		 287 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
288 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
3d567e0e
NNS		 289 {PCI_DEVICE_SUB(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5787M,
290 PCI_VENDOR_ID_LENOVO,
291 TG3PCI_SUBDEVICE_ID_LENOVO_5787M),
292 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
13185217 293 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
3d567e0e
NNS		 294 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F),
295 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
13185217
HK		 296 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
297 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
298 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
299 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
300 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
301 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
302 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
b5d3772c
MC		 303 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
304 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
d30cdd28
MC		 305 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)},
306 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)},
6c7af27c 307 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)},
9936bcf6
MC		 308 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)},
309 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)},
c88e668b
MC		 310 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761S)},
311 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761SE)},
2befdcea
MC		 312 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_G)},
313 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_F)},
3d567e0e
NNS		 314 {PCI_DEVICE_SUB(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780,
315 PCI_VENDOR_ID_AI, TG3PCI_SUBDEVICE_ID_ACER_57780_A),
316 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
317 {PCI_DEVICE_SUB(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780,
318 PCI_VENDOR_ID_AI, TG3PCI_SUBDEVICE_ID_ACER_57780_B),
319 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
321d32a0
MC		 320 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780)},
321 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57760)},
3d567e0e
NNS		 322 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57790),
323 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
5e7ccf20 324 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57788)},
5001e2f6 325 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5717)},
79d49695 326 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5717_C)},
5001e2f6 327 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5718)},
b0f75221
MC		 328 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57781)},
329 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57785)},
330 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57761)},
331 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57765)},
3d567e0e
NNS		 332 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57791),
333 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
334 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57795),
335 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
302b500b 336 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5719)},
ba1f3c76 337 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5720)},
02eca3f5 338 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57762)},
d3f677af 339 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57766)},
c86a8560
MC		 340 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5762)},
341 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5725)},
342 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5727)},
68273712
NS		 343 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57764)},
344 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57767)},
345 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57787)},
346 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57782)},
347 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57786)},
13185217
HK		 348 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
349 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
350 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
351 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
352 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
353 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
354 {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
1dcb14d9 355 {PCI_DEVICE(0x10cf, 0x11a2)}, /* Fujitsu 1000base-SX with BCM5703SKHB */
13185217 356 {}
1da177e4
LT		 357};
358
359MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
360
50da859d 361static const struct {
1da177e4 362 const char string[ETH_GSTRING_LEN];
48fa55a0 363} ethtool_stats_keys[] = {
1da177e4
LT		 364 { "rx_octets" },
365 { "rx_fragments" },
366 { "rx_ucast_packets" },
367 { "rx_mcast_packets" },
368 { "rx_bcast_packets" },
369 { "rx_fcs_errors" },
370 { "rx_align_errors" },
371 { "rx_xon_pause_rcvd" },
372 { "rx_xoff_pause_rcvd" },
373 { "rx_mac_ctrl_rcvd" },
374 { "rx_xoff_entered" },
375 { "rx_frame_too_long_errors" },
376 { "rx_jabbers" },
377 { "rx_undersize_packets" },
378 { "rx_in_length_errors" },
379 { "rx_out_length_errors" },
380 { "rx_64_or_less_octet_packets" },
381 { "rx_65_to_127_octet_packets" },
382 { "rx_128_to_255_octet_packets" },
383 { "rx_256_to_511_octet_packets" },
384 { "rx_512_to_1023_octet_packets" },
385 { "rx_1024_to_1522_octet_packets" },
386 { "rx_1523_to_2047_octet_packets" },
387 { "rx_2048_to_4095_octet_packets" },
388 { "rx_4096_to_8191_octet_packets" },
389 { "rx_8192_to_9022_octet_packets" },
390
391 { "tx_octets" },
392 { "tx_collisions" },
393
394 { "tx_xon_sent" },
395 { "tx_xoff_sent" },
396 { "tx_flow_control" },
397 { "tx_mac_errors" },
398 { "tx_single_collisions" },
399 { "tx_mult_collisions" },
400 { "tx_deferred" },
401 { "tx_excessive_collisions" },
402 { "tx_late_collisions" },
403 { "tx_collide_2times" },
404 { "tx_collide_3times" },
405 { "tx_collide_4times" },
406 { "tx_collide_5times" },
407 { "tx_collide_6times" },
408 { "tx_collide_7times" },
409 { "tx_collide_8times" },
410 { "tx_collide_9times" },
411 { "tx_collide_10times" },
412 { "tx_collide_11times" },
413 { "tx_collide_12times" },
414 { "tx_collide_13times" },
415 { "tx_collide_14times" },
416 { "tx_collide_15times" },
417 { "tx_ucast_packets" },
418 { "tx_mcast_packets" },
419 { "tx_bcast_packets" },
420 { "tx_carrier_sense_errors" },
421 { "tx_discards" },
422 { "tx_errors" },
423
424 { "dma_writeq_full" },
425 { "dma_write_prioq_full" },
426 { "rxbds_empty" },
427 { "rx_discards" },
428 { "rx_errors" },
429 { "rx_threshold_hit" },
430
431 { "dma_readq_full" },
432 { "dma_read_prioq_full" },
433 { "tx_comp_queue_full" },
434
435 { "ring_set_send_prod_index" },
436 { "ring_status_update" },
437 { "nic_irqs" },
438 { "nic_avoided_irqs" },
4452d099
MC		 439 { "nic_tx_threshold_hit" },
440
441 { "mbuf_lwm_thresh_hit" },
1da177e4
LT		 442};
443
48fa55a0 444#define TG3_NUM_STATS ARRAY_SIZE(ethtool_stats_keys)
93df8b8f
NNS		 445#define TG3_NVRAM_TEST 0
446#define TG3_LINK_TEST 1
447#define TG3_REGISTER_TEST 2
448#define TG3_MEMORY_TEST 3
449#define TG3_MAC_LOOPB_TEST 4
450#define TG3_PHY_LOOPB_TEST 5
451#define TG3_EXT_LOOPB_TEST 6
452#define TG3_INTERRUPT_TEST 7
48fa55a0
MC		 453
454
50da859d 455static const struct {
4cafd3f5 456 const char string[ETH_GSTRING_LEN];
48fa55a0 457} ethtool_test_keys[] = {
93df8b8f
NNS		 458 [TG3_NVRAM_TEST] = { "nvram test (online) " },
459 [TG3_LINK_TEST] = { "link test (online) " },
460 [TG3_REGISTER_TEST] = { "register test (offline)" },
461 [TG3_MEMORY_TEST] = { "memory test (offline)" },
462 [TG3_MAC_LOOPB_TEST] = { "mac loopback test (offline)" },
463 [TG3_PHY_LOOPB_TEST] = { "phy loopback test (offline)" },
464 [TG3_EXT_LOOPB_TEST] = { "ext loopback test (offline)" },
465 [TG3_INTERRUPT_TEST] = { "interrupt test (offline)" },
4cafd3f5
MC		 466};
467
48fa55a0
MC		 468#define TG3_NUM_TEST ARRAY_SIZE(ethtool_test_keys)
469
470
b401e9e2
MC		 471static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
472{
473 writel(val, tp->regs + off);
474}
475
476static u32 tg3_read32(struct tg3 *tp, u32 off)
477{
de6f31eb 478 return readl(tp->regs + off);
b401e9e2
MC		 479}
480
0d3031d9
MC		 481static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val)
482{
483 writel(val, tp->aperegs + off);
484}
485
486static u32 tg3_ape_read32(struct tg3 *tp, u32 off)
487{
de6f31eb 488 return readl(tp->aperegs + off);
0d3031d9
MC		 489}
490
1da177e4
LT		 491static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
492{
6892914f
MC		 493 unsigned long flags;
494
495 spin_lock_irqsave(&tp->indirect_lock, flags);
1ee582d8
MC		 496 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
497 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
6892914f 498 spin_unlock_irqrestore(&tp->indirect_lock, flags);
1ee582d8
MC		 499}
500
501static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
502{
503 writel(val, tp->regs + off);
504 readl(tp->regs + off);
1da177e4
LT		 505}
506
6892914f 507static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
1da177e4 508{
6892914f
MC		 509 unsigned long flags;
510 u32 val;
511
512 spin_lock_irqsave(&tp->indirect_lock, flags);
513 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
514 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
515 spin_unlock_irqrestore(&tp->indirect_lock, flags);
516 return val;
517}
518
519static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
520{
521 unsigned long flags;
522
523 if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
524 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
525 TG3_64BIT_REG_LOW, val);
526 return;
527 }
66711e66 528 if (off == TG3_RX_STD_PROD_IDX_REG) {
6892914f
MC		 529 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
530 TG3_64BIT_REG_LOW, val);
531 return;
1da177e4 532 }
6892914f
MC		 533
534 spin_lock_irqsave(&tp->indirect_lock, flags);
535 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
536 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
537 spin_unlock_irqrestore(&tp->indirect_lock, flags);
538
539 /* In indirect mode when disabling interrupts, we also need
540 * to clear the interrupt bit in the GRC local ctrl register.
541 */
542 if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
543 (val == 0x1)) {
544 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
545 tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
546 }
547}
548
549static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
550{
551 unsigned long flags;
552 u32 val;
553
554 spin_lock_irqsave(&tp->indirect_lock, flags);
555 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
556 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
557 spin_unlock_irqrestore(&tp->indirect_lock, flags);
558 return val;
559}
560
b401e9e2
MC		 561/* usec_wait specifies the wait time in usec when writing to certain registers
562 * where it is unsafe to read back the register without some delay.
563 * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
564 * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
565 */
566static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
6892914f 567{
63c3a66f 568 if (tg3_flag(tp, PCIX_TARGET_HWBUG) || tg3_flag(tp, ICH_WORKAROUND))
b401e9e2
MC		 569 /* Non-posted methods */
570 tp->write32(tp, off, val);
571 else {
572 /* Posted method */
573 tg3_write32(tp, off, val);
574 if (usec_wait)
575 udelay(usec_wait);
576 tp->read32(tp, off);
577 }
578 /* Wait again after the read for the posted method to guarantee that
579 * the wait time is met.
580 */
581 if (usec_wait)
582 udelay(usec_wait);
1da177e4
LT		 583}
584
09ee929c
MC		 585static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
586{
587 tp->write32_mbox(tp, off, val);
7e6c63f0
HM		 588 if (tg3_flag(tp, FLUSH_POSTED_WRITES) ||
589 (!tg3_flag(tp, MBOX_WRITE_REORDER) &&
590 !tg3_flag(tp, ICH_WORKAROUND)))
6892914f 591 tp->read32_mbox(tp, off);
09ee929c
MC		 592}
593
20094930 594static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
1da177e4
LT		 595{
596 void __iomem *mbox = tp->regs + off;
597 writel(val, mbox);
63c3a66f 598 if (tg3_flag(tp, TXD_MBOX_HWBUG))
1da177e4 599 writel(val, mbox);
7e6c63f0
HM		 600 if (tg3_flag(tp, MBOX_WRITE_REORDER) ||
601 tg3_flag(tp, FLUSH_POSTED_WRITES))
1da177e4
LT		 602 readl(mbox);
603}
604
b5d3772c
MC		 605static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
606{
de6f31eb 607 return readl(tp->regs + off + GRCMBOX_BASE);
b5d3772c
MC		 608}
609
610static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
611{
612 writel(val, tp->regs + off + GRCMBOX_BASE);
613}
614
c6cdf436 615#define tw32_mailbox(reg, val) tp->write32_mbox(tp, reg, val)
09ee929c 616#define tw32_mailbox_f(reg, val) tw32_mailbox_flush(tp, (reg), (val))
c6cdf436
MC		 617#define tw32_rx_mbox(reg, val) tp->write32_rx_mbox(tp, reg, val)
618#define tw32_tx_mbox(reg, val) tp->write32_tx_mbox(tp, reg, val)
619#define tr32_mailbox(reg) tp->read32_mbox(tp, reg)
20094930 620
c6cdf436
MC		 621#define tw32(reg, val) tp->write32(tp, reg, val)
622#define tw32_f(reg, val) _tw32_flush(tp, (reg), (val), 0)
623#define tw32_wait_f(reg, val, us) _tw32_flush(tp, (reg), (val), (us))
624#define tr32(reg) tp->read32(tp, reg)
1da177e4
LT		 625
626static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
627{
6892914f
MC		 628 unsigned long flags;
629
4153577a 630 if (tg3_asic_rev(tp) == ASIC_REV_5906 &&
b5d3772c
MC		 631 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
632 return;
633
6892914f 634 spin_lock_irqsave(&tp->indirect_lock, flags);
63c3a66f 635 if (tg3_flag(tp, SRAM_USE_CONFIG)) {
bbadf503
MC		 636 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
637 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
1da177e4 638
bbadf503
MC		 639 /* Always leave this as zero. */
640 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
641 } else {
642 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
643 tw32_f(TG3PCI_MEM_WIN_DATA, val);
28fbef78 644
bbadf503
MC		 645 /* Always leave this as zero. */
646 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
647 }
648 spin_unlock_irqrestore(&tp->indirect_lock, flags);
758a6139
DM		 649}
650
1da177e4
LT		 651static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
652{
6892914f
MC		 653 unsigned long flags;
654
4153577a 655 if (tg3_asic_rev(tp) == ASIC_REV_5906 &&
b5d3772c
MC		 656 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
657 *val = 0;
658 return;
659 }
660
6892914f 661 spin_lock_irqsave(&tp->indirect_lock, flags);
63c3a66f 662 if (tg3_flag(tp, SRAM_USE_CONFIG)) {
bbadf503
MC		 663 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
664 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
1da177e4 665
bbadf503
MC		 666 /* Always leave this as zero. */
667 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
668 } else {
669 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
670 *val = tr32(TG3PCI_MEM_WIN_DATA);
671
672 /* Always leave this as zero. */
673 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
674 }
6892914f 675 spin_unlock_irqrestore(&tp->indirect_lock, flags);
1da177e4
LT		 676}
677
0d3031d9
MC		 678static void tg3_ape_lock_init(struct tg3 *tp)
679{
680 int i;
6f5c8f83 681 u32 regbase, bit;
f92d9dc1 682
4153577a 683 if (tg3_asic_rev(tp) == ASIC_REV_5761)
f92d9dc1
MC		 684 regbase = TG3_APE_LOCK_GRANT;
685 else
686 regbase = TG3_APE_PER_LOCK_GRANT;
0d3031d9
MC		 687
688 /* Make sure the driver hasn't any stale locks. */
78f94dc7
MC		 689 for (i = TG3_APE_LOCK_PHY0; i <= TG3_APE_LOCK_GPIO; i++) {
690 switch (i) {
691 case TG3_APE_LOCK_PHY0:
692 case TG3_APE_LOCK_PHY1:
693 case TG3_APE_LOCK_PHY2:
694 case TG3_APE_LOCK_PHY3:
695 bit = APE_LOCK_GRANT_DRIVER;
696 break;
697 default:
698 if (!tp->pci_fn)
699 bit = APE_LOCK_GRANT_DRIVER;
700 else
701 bit = 1 << tp->pci_fn;
702 }
703 tg3_ape_write32(tp, regbase + 4 * i, bit);
6f5c8f83
MC		 704 }
705
0d3031d9
MC		 706}
707
708static int tg3_ape_lock(struct tg3 *tp, int locknum)
709{
710 int i, off;
711 int ret = 0;
6f5c8f83 712 u32 status, req, gnt, bit;
0d3031d9 713
63c3a66f 714 if (!tg3_flag(tp, ENABLE_APE))
0d3031d9
MC		 715 return 0;
716
717 switch (locknum) {
6f5c8f83 718 case TG3_APE_LOCK_GPIO:
4153577a 719 if (tg3_asic_rev(tp) == ASIC_REV_5761)
6f5c8f83 720 return 0;
33f401ae
MC		 721 case TG3_APE_LOCK_GRC:
722 case TG3_APE_LOCK_MEM:
78f94dc7
MC		 723 if (!tp->pci_fn)
724 bit = APE_LOCK_REQ_DRIVER;
725 else
726 bit = 1 << tp->pci_fn;
33f401ae 727 break;
8151ad57
MC		 728 case TG3_APE_LOCK_PHY0:
729 case TG3_APE_LOCK_PHY1:
730 case TG3_APE_LOCK_PHY2:
731 case TG3_APE_LOCK_PHY3:
732 bit = APE_LOCK_REQ_DRIVER;
733 break;
33f401ae
MC		 734 default:
735 return -EINVAL;
0d3031d9
MC		 736 }
737
4153577a 738 if (tg3_asic_rev(tp) == ASIC_REV_5761) {
f92d9dc1
MC		 739 req = TG3_APE_LOCK_REQ;
740 gnt = TG3_APE_LOCK_GRANT;
741 } else {
742 req = TG3_APE_PER_LOCK_REQ;
743 gnt = TG3_APE_PER_LOCK_GRANT;
744 }
745
0d3031d9
MC		 746 off = 4 * locknum;
747
6f5c8f83 748 tg3_ape_write32(tp, req + off, bit);
0d3031d9
MC		 749
750 /* Wait for up to 1 millisecond to acquire lock. */
751 for (i = 0; i < 100; i++) {
f92d9dc1 752 status = tg3_ape_read32(tp, gnt + off);
6f5c8f83 753 if (status == bit)
0d3031d9 754 break;
6d446ec3
GS		 755 if (pci_channel_offline(tp->pdev))
756 break;
757
0d3031d9
MC		 758 udelay(10);
759 }
760
6f5c8f83 761 if (status != bit) {
0d3031d9 762 /* Revoke the lock request. */
6f5c8f83 763 tg3_ape_write32(tp, gnt + off, bit);
0d3031d9
MC		 764 ret = -EBUSY;
765 }
766
767 return ret;
768}
769
770static void tg3_ape_unlock(struct tg3 *tp, int locknum)
771{
6f5c8f83 772 u32 gnt, bit;
0d3031d9 773
63c3a66f 774 if (!tg3_flag(tp, ENABLE_APE))
0d3031d9
MC		 775 return;
776
777 switch (locknum) {
6f5c8f83 778 case TG3_APE_LOCK_GPIO:
4153577a 779 if (tg3_asic_rev(tp) == ASIC_REV_5761)
6f5c8f83 780 return;
33f401ae
MC		 781 case TG3_APE_LOCK_GRC:
782 case TG3_APE_LOCK_MEM:
78f94dc7
MC		 783 if (!tp->pci_fn)
784 bit = APE_LOCK_GRANT_DRIVER;
785 else
786 bit = 1 << tp->pci_fn;
33f401ae 787 break;
8151ad57
MC		 788 case TG3_APE_LOCK_PHY0:
789 case TG3_APE_LOCK_PHY1:
790 case TG3_APE_LOCK_PHY2:
791 case TG3_APE_LOCK_PHY3:
792 bit = APE_LOCK_GRANT_DRIVER;
793 break;
33f401ae
MC		 794 default:
795 return;
0d3031d9
MC		 796 }
797
4153577a 798 if (tg3_asic_rev(tp) == ASIC_REV_5761)
f92d9dc1
MC		 799 gnt = TG3_APE_LOCK_GRANT;
800 else
801 gnt = TG3_APE_PER_LOCK_GRANT;
802
6f5c8f83 803 tg3_ape_write32(tp, gnt + 4 * locknum, bit);
0d3031d9
MC		 804}
805
b65a372b 806static int tg3_ape_event_lock(struct tg3 *tp, u32 timeout_us)
fd6d3f0e 807{
fd6d3f0e
MC		 808 u32 apedata;
809
b65a372b
MC		 810 while (timeout_us) {
811 if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM))
812 return -EBUSY;
813
814 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
815 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
816 break;
817
818 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
819
820 udelay(10);
821 timeout_us -= (timeout_us > 10) ? 10 : timeout_us;
822 }
823
824 return timeout_us ? 0 : -EBUSY;
825}
826
cf8d55ae
MC		 827static int tg3_ape_wait_for_event(struct tg3 *tp, u32 timeout_us)
828{
829 u32 i, apedata;
830
831 for (i = 0; i < timeout_us / 10; i++) {
832 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
833
834 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
835 break;
836
837 udelay(10);
838 }
839
840 return i == timeout_us / 10;
841}
842
86449944
MC		 843static int tg3_ape_scratchpad_read(struct tg3 *tp, u32 *data, u32 base_off,
844 u32 len)
cf8d55ae
MC		 845{
846 int err;
847 u32 i, bufoff, msgoff, maxlen, apedata;
848
849 if (!tg3_flag(tp, APE_HAS_NCSI))
850 return 0;
851
852 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
853 if (apedata != APE_SEG_SIG_MAGIC)
854 return -ENODEV;
855
856 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
857 if (!(apedata & APE_FW_STATUS_READY))
858 return -EAGAIN;
859
860 bufoff = tg3_ape_read32(tp, TG3_APE_SEG_MSG_BUF_OFF) +
861 TG3_APE_SHMEM_BASE;
862 msgoff = bufoff + 2 * sizeof(u32);
863 maxlen = tg3_ape_read32(tp, TG3_APE_SEG_MSG_BUF_LEN);
864
865 while (len) {
866 u32 length;
867
868 /* Cap xfer sizes to scratchpad limits. */
869 length = (len > maxlen) ? maxlen : len;
870 len -= length;
871
872 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
873 if (!(apedata & APE_FW_STATUS_READY))
874 return -EAGAIN;
875
876 /* Wait for up to 1 msec for APE to service previous event. */
877 err = tg3_ape_event_lock(tp, 1000);
878 if (err)
879 return err;
880
881 apedata = APE_EVENT_STATUS_DRIVER_EVNT |
882 APE_EVENT_STATUS_SCRTCHPD_READ |
883 APE_EVENT_STATUS_EVENT_PENDING;
884 tg3_ape_write32(tp, TG3_APE_EVENT_STATUS, apedata);
885
886 tg3_ape_write32(tp, bufoff, base_off);
887 tg3_ape_write32(tp, bufoff + sizeof(u32), length);
888
889 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
890 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
891
892 base_off += length;
893
894 if (tg3_ape_wait_for_event(tp, 30000))
895 return -EAGAIN;
896
897 for (i = 0; length; i += 4, length -= 4) {
898 u32 val = tg3_ape_read32(tp, msgoff + i);
899 memcpy(data, &val, sizeof(u32));
900 data++;
901 }
902 }
903
904 return 0;
905}
906
b65a372b
MC		 907static int tg3_ape_send_event(struct tg3 *tp, u32 event)
908{
909 int err;
910 u32 apedata;
fd6d3f0e
MC		 911
912 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
913 if (apedata != APE_SEG_SIG_MAGIC)
b65a372b 914 return -EAGAIN;
fd6d3f0e
MC		 915
916 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
917 if (!(apedata & APE_FW_STATUS_READY))
b65a372b 918 return -EAGAIN;
fd6d3f0e
MC		 919
920 /* Wait for up to 1 millisecond for APE to service previous event. */
b65a372b
MC		 921 err = tg3_ape_event_lock(tp, 1000);
922 if (err)
923 return err;
fd6d3f0e 924
b65a372b
MC		 925 tg3_ape_write32(tp, TG3_APE_EVENT_STATUS,
926 event | APE_EVENT_STATUS_EVENT_PENDING);
fd6d3f0e 927
b65a372b
MC		 928 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
929 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
fd6d3f0e 930
b65a372b 931 return 0;
fd6d3f0e
MC		 932}
933
934static void tg3_ape_driver_state_change(struct tg3 *tp, int kind)
935{
936 u32 event;
937 u32 apedata;
938
939 if (!tg3_flag(tp, ENABLE_APE))
940 return;
941
942 switch (kind) {
943 case RESET_KIND_INIT:
944 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG,
945 APE_HOST_SEG_SIG_MAGIC);
946 tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN,
947 APE_HOST_SEG_LEN_MAGIC);
948 apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT);
949 tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata);
950 tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID,
951 APE_HOST_DRIVER_ID_MAGIC(TG3_MAJ_NUM, TG3_MIN_NUM));
952 tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR,
953 APE_HOST_BEHAV_NO_PHYLOCK);
954 tg3_ape_write32(tp, TG3_APE_HOST_DRVR_STATE,
955 TG3_APE_HOST_DRVR_STATE_START);
956
957 event = APE_EVENT_STATUS_STATE_START;
958 break;
959 case RESET_KIND_SHUTDOWN:
960 /* With the interface we are currently using,
961 * APE does not track driver state. Wiping
962 * out the HOST SEGMENT SIGNATURE forces
963 * the APE to assume OS absent status.
964 */
965 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, 0x0);
966
967 if (device_may_wakeup(&tp->pdev->dev) &&
968 tg3_flag(tp, WOL_ENABLE)) {
969 tg3_ape_write32(tp, TG3_APE_HOST_WOL_SPEED,
970 TG3_APE_HOST_WOL_SPEED_AUTO);
971 apedata = TG3_APE_HOST_DRVR_STATE_WOL;
972 } else
973 apedata = TG3_APE_HOST_DRVR_STATE_UNLOAD;
974
975 tg3_ape_write32(tp, TG3_APE_HOST_DRVR_STATE, apedata);
976
977 event = APE_EVENT_STATUS_STATE_UNLOAD;
978 break;
fd6d3f0e
MC		 979 default:
980 return;
981 }
982
983 event |= APE_EVENT_STATUS_DRIVER_EVNT | APE_EVENT_STATUS_STATE_CHNGE;
984
985 tg3_ape_send_event(tp, event);
986}
987
1da177e4
LT		 988static void tg3_disable_ints(struct tg3 *tp)
989{
89aeb3bc
MC		 990 int i;
991
1da177e4
LT		 992 tw32(TG3PCI_MISC_HOST_CTRL,
993 (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
89aeb3bc
MC		 994 for (i = 0; i < tp->irq_max; i++)
995 tw32_mailbox_f(tp->napi[i].int_mbox, 0x00000001);
1da177e4
LT		 996}
997
1da177e4
LT		 998static void tg3_enable_ints(struct tg3 *tp)
999{
89aeb3bc 1000 int i;
89aeb3bc 1001
bbe832c0
MC		 1002 tp->irq_sync = 0;
1003 wmb();
1004
1da177e4
LT		 1005 tw32(TG3PCI_MISC_HOST_CTRL,
1006 (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
89aeb3bc 1007
f89f38b8 1008 tp->coal_now = tp->coalesce_mode | HOSTCC_MODE_ENABLE;
89aeb3bc
MC		 1009 for (i = 0; i < tp->irq_cnt; i++) {
1010 struct tg3_napi *tnapi = &tp->napi[i];
c6cdf436 1011
898a56f8 1012 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
63c3a66f 1013 if (tg3_flag(tp, 1SHOT_MSI))
89aeb3bc 1014 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
f19af9c2 1015
f89f38b8 1016 tp->coal_now |= tnapi->coal_now;
89aeb3bc 1017 }
f19af9c2
MC		 1018
1019 /* Force an initial interrupt */
63c3a66f 1020 if (!tg3_flag(tp, TAGGED_STATUS) &&
f19af9c2
MC		 1021 (tp->napi[0].hw_status->status & SD_STATUS_UPDATED))
1022 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
1023 else
f89f38b8
MC		 1024 tw32(HOSTCC_MODE, tp->coal_now);
1025
1026 tp->coal_now &= ~(tp->napi[0].coal_now | tp->napi[1].coal_now);
1da177e4
LT		 1027}
1028
17375d25 1029static inline unsigned int tg3_has_work(struct tg3_napi *tnapi)
04237ddd 1030{
17375d25 1031 struct tg3 *tp = tnapi->tp;
898a56f8 1032 struct tg3_hw_status *sblk = tnapi->hw_status;
04237ddd
MC		 1033 unsigned int work_exists = 0;
1034
1035 /* check for phy events */
63c3a66f 1036 if (!(tg3_flag(tp, USE_LINKCHG_REG) || tg3_flag(tp, POLL_SERDES))) {
04237ddd
MC		 1037 if (sblk->status & SD_STATUS_LINK_CHG)
1038 work_exists = 1;
1039 }
f891ea16
MC		 1040
1041 /* check for TX work to do */
1042 if (sblk->idx[0].tx_consumer != tnapi->tx_cons)
1043 work_exists = 1;
1044
1045 /* check for RX work to do */
1046 if (tnapi->rx_rcb_prod_idx &&
8d9d7cfc 1047 *(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
04237ddd
MC		 1048 work_exists = 1;
1049
1050 return work_exists;
1051}
1052
17375d25 1053/* tg3_int_reenable
04237ddd
MC		 1054 * similar to tg3_enable_ints, but it accurately determines whether there
1055 * is new work pending and can return without flushing the PIO write
6aa20a22 1056 * which reenables interrupts
1da177e4 1057 */
17375d25 1058static void tg3_int_reenable(struct tg3_napi *tnapi)
1da177e4 1059{
17375d25
MC		 1060 struct tg3 *tp = tnapi->tp;
1061
898a56f8 1062 tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
1da177e4
LT		 1063 mmiowb();
1064
fac9b83e
DM		 1065 /* When doing tagged status, this work check is unnecessary.
1066 * The last_tag we write above tells the chip which piece of
1067 * work we've completed.
1068 */
63c3a66f 1069 if (!tg3_flag(tp, TAGGED_STATUS) && tg3_has_work(tnapi))
04237ddd 1070 tw32(HOSTCC_MODE, tp->coalesce_mode |
fd2ce37f 1071 HOSTCC_MODE_ENABLE | tnapi->coal_now);
1da177e4
LT		 1072}
1073
1da177e4
LT		 1074static void tg3_switch_clocks(struct tg3 *tp)
1075{
f6eb9b1f 1076 u32 clock_ctrl;
1da177e4
LT		 1077 u32 orig_clock_ctrl;
1078
63c3a66f 1079 if (tg3_flag(tp, CPMU_PRESENT) || tg3_flag(tp, 5780_CLASS))
4cf78e4f
MC		 1080 return;
1081
f6eb9b1f
MC		 1082 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
1083
1da177e4
LT		 1084 orig_clock_ctrl = clock_ctrl;
1085 clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
1086 CLOCK_CTRL_CLKRUN_OENABLE |
1087 0x1f);
1088 tp->pci_clock_ctrl = clock_ctrl;
1089
63c3a66f 1090 if (tg3_flag(tp, 5705_PLUS)) {
1da177e4 1091 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
b401e9e2
MC		 1092 tw32_wait_f(TG3PCI_CLOCK_CTRL,
1093 clock_ctrl | CLOCK_CTRL_625_CORE, 40);
1da177e4
LT		 1094 }
1095 } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
b401e9e2
MC		 1096 tw32_wait_f(TG3PCI_CLOCK_CTRL,
1097 clock_ctrl |
1098 (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
1099 40);
1100 tw32_wait_f(TG3PCI_CLOCK_CTRL,
1101 clock_ctrl | (CLOCK_CTRL_ALTCLK),
1102 40);
1da177e4 1103 }
b401e9e2 1104 tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
1da177e4
LT		 1105}
1106
1107#define PHY_BUSY_LOOPS 5000
1108
5c358045
HM		 1109static int __tg3_readphy(struct tg3 *tp, unsigned int phy_addr, int reg,
1110 u32 *val)
1da177e4
LT		 1111{
1112 u32 frame_val;
1113 unsigned int loops;
1114 int ret;
1115
1116 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
1117 tw32_f(MAC_MI_MODE,
1118 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
1119 udelay(80);
1120 }
1121
8151ad57
MC		 1122 tg3_ape_lock(tp, tp->phy_ape_lock);
1123
1da177e4
LT		 1124 *val = 0x0;
1125
5c358045 1126 frame_val = ((phy_addr << MI_COM_PHY_ADDR_SHIFT) &
1da177e4
LT		 1127 MI_COM_PHY_ADDR_MASK);
1128 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
1129 MI_COM_REG_ADDR_MASK);
1130 frame_val |= (MI_COM_CMD_READ | MI_COM_START);
6aa20a22 1131
1da177e4
LT		 1132 tw32_f(MAC_MI_COM, frame_val);
1133
1134 loops = PHY_BUSY_LOOPS;
1135 while (loops != 0) {
1136 udelay(10);
1137 frame_val = tr32(MAC_MI_COM);
1138
1139 if ((frame_val & MI_COM_BUSY) == 0) {
1140 udelay(5);
1141 frame_val = tr32(MAC_MI_COM);
1142 break;
1143 }
1144 loops -= 1;
1145 }
1146
1147 ret = -EBUSY;
1148 if (loops != 0) {
1149 *val = frame_val & MI_COM_DATA_MASK;
1150 ret = 0;
1151 }
1152
1153 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
1154 tw32_f(MAC_MI_MODE, tp->mi_mode);
1155 udelay(80);
1156 }
1157
8151ad57
MC		 1158 tg3_ape_unlock(tp, tp->phy_ape_lock);
1159
1da177e4
LT		 1160 return ret;
1161}
1162
5c358045
HM		 1163static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
1164{
1165 return __tg3_readphy(tp, tp->phy_addr, reg, val);
1166}
1167
1168static int __tg3_writephy(struct tg3 *tp, unsigned int phy_addr, int reg,
1169 u32 val)
1da177e4
LT		 1170{
1171 u32 frame_val;
1172 unsigned int loops;
1173 int ret;
1174
f07e9af3 1175 if ((tp->phy_flags & TG3_PHYFLG_IS_FET) &&
221c5637 1176 (reg == MII_CTRL1000 || reg == MII_TG3_AUX_CTRL))
b5d3772c
MC		 1177 return 0;
1178
1da177e4
LT		 1179 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
1180 tw32_f(MAC_MI_MODE,
1181 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
1182 udelay(80);
1183 }
1184
8151ad57
MC		 1185 tg3_ape_lock(tp, tp->phy_ape_lock);
1186
5c358045 1187 frame_val = ((phy_addr << MI_COM_PHY_ADDR_SHIFT) &
1da177e4
LT		 1188 MI_COM_PHY_ADDR_MASK);
1189 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
1190 MI_COM_REG_ADDR_MASK);
1191 frame_val |= (val & MI_COM_DATA_MASK);
1192 frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
6aa20a22 1193
1da177e4
LT		 1194 tw32_f(MAC_MI_COM, frame_val);
1195
1196 loops = PHY_BUSY_LOOPS;
1197 while (loops != 0) {
1198 udelay(10);
1199 frame_val = tr32(MAC_MI_COM);
1200 if ((frame_val & MI_COM_BUSY) == 0) {
1201 udelay(5);
1202 frame_val = tr32(MAC_MI_COM);
1203 break;
1204 }
1205 loops -= 1;
1206 }
1207
1208 ret = -EBUSY;
1209 if (loops != 0)
1210 ret = 0;
1211
1212 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
1213 tw32_f(MAC_MI_MODE, tp->mi_mode);
1214 udelay(80);
1215 }
1216
8151ad57
MC		 1217 tg3_ape_unlock(tp, tp->phy_ape_lock);
1218
1da177e4
LT		 1219 return ret;
1220}
1221
5c358045
HM		 1222static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
1223{
1224 return __tg3_writephy(tp, tp->phy_addr, reg, val);
1225}
1226
b0988c15
MC		 1227static int tg3_phy_cl45_write(struct tg3 *tp, u32 devad, u32 addr, u32 val)
1228{
1229 int err;
1230
1231 err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad);
1232 if (err)
1233 goto done;
1234
1235 err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr);
1236 if (err)
1237 goto done;
1238
1239 err = tg3_writephy(tp, MII_TG3_MMD_CTRL,
1240 MII_TG3_MMD_CTRL_DATA_NOINC | devad);
1241 if (err)
1242 goto done;
1243
1244 err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, val);
1245
1246done:
1247 return err;
1248}
1249
1250static int tg3_phy_cl45_read(struct tg3 *tp, u32 devad, u32 addr, u32 *val)
1251{
1252 int err;
1253
1254 err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad);
1255 if (err)
1256 goto done;
1257
1258 err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr);
1259 if (err)
1260 goto done;
1261
1262 err = tg3_writephy(tp, MII_TG3_MMD_CTRL,
1263 MII_TG3_MMD_CTRL_DATA_NOINC | devad);
1264 if (err)
1265 goto done;
1266
1267 err = tg3_readphy(tp, MII_TG3_MMD_ADDRESS, val);
1268
1269done:
1270 return err;
1271}
1272
1273static int tg3_phydsp_read(struct tg3 *tp, u32 reg, u32 *val)
1274{
1275 int err;
1276
1277 err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1278 if (!err)
1279 err = tg3_readphy(tp, MII_TG3_DSP_RW_PORT, val);
1280
1281 return err;
1282}
1283
1284static int tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
1285{
1286 int err;
1287
1288 err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1289 if (!err)
1290 err = tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
1291
1292 return err;
1293}
1294
15ee95c3
MC		 1295static int tg3_phy_auxctl_read(struct tg3 *tp, int reg, u32 *val)
1296{
1297 int err;
1298
1299 err = tg3_writephy(tp, MII_TG3_AUX_CTRL,
1300 (reg << MII_TG3_AUXCTL_MISC_RDSEL_SHIFT) |
1301 MII_TG3_AUXCTL_SHDWSEL_MISC);
1302 if (!err)
1303 err = tg3_readphy(tp, MII_TG3_AUX_CTRL, val);
1304
1305 return err;
1306}
1307
b4bd2929
MC		 1308static int tg3_phy_auxctl_write(struct tg3 *tp, int reg, u32 set)
1309{
1310 if (reg == MII_TG3_AUXCTL_SHDWSEL_MISC)
1311 set |= MII_TG3_AUXCTL_MISC_WREN;
1312
1313 return tg3_writephy(tp, MII_TG3_AUX_CTRL, set | reg);
1314}
1315
daf3ec68
NNS		 1316static int tg3_phy_toggle_auxctl_smdsp(struct tg3 *tp, bool enable)
1317{
1318 u32 val;
1319 int err;
1d36ba45 1320
daf3ec68 1321 err = tg3_phy_auxctl_read(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, &val);
1d36ba45 1322
daf3ec68
NNS		 1323 if (err)
1324 return err;
daf3ec68 1325
7c10ee32 1326 if (enable)
daf3ec68
NNS		 1327 val |= MII_TG3_AUXCTL_ACTL_SMDSP_ENA;
1328 else
1329 val &= ~MII_TG3_AUXCTL_ACTL_SMDSP_ENA;
1330
1331 err = tg3_phy_auxctl_write((tp), MII_TG3_AUXCTL_SHDWSEL_AUXCTL,
1332 val | MII_TG3_AUXCTL_ACTL_TX_6DB);
1333
1334 return err;
1335}
1d36ba45 1336
3ab71071
NS		 1337static int tg3_phy_shdw_write(struct tg3 *tp, int reg, u32 val)
1338{
1339 return tg3_writephy(tp, MII_TG3_MISC_SHDW,
1340 reg | val | MII_TG3_MISC_SHDW_WREN);
1341}
1342
95e2869a
MC		 1343static int tg3_bmcr_reset(struct tg3 *tp)
1344{
1345 u32 phy_control;
1346 int limit, err;
1347
1348 /* OK, reset it, and poll the BMCR_RESET bit until it
1349 * clears or we time out.
1350 */
1351 phy_control = BMCR_RESET;
1352 err = tg3_writephy(tp, MII_BMCR, phy_control);
1353 if (err != 0)
1354 return -EBUSY;
1355
1356 limit = 5000;
1357 while (limit--) {
1358 err = tg3_readphy(tp, MII_BMCR, &phy_control);
1359 if (err != 0)
1360 return -EBUSY;
1361
1362 if ((phy_control & BMCR_RESET) == 0) {
1363 udelay(40);
1364 break;
1365 }
1366 udelay(10);
1367 }
d4675b52 1368 if (limit < 0)
95e2869a
MC		 1369 return -EBUSY;
1370
1371 return 0;
1372}
1373
158d7abd
MC		 1374static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg)
1375{
3d16543d 1376 struct tg3 *tp = bp->priv;
158d7abd
MC		 1377 u32 val;
1378
24bb4fb6 1379 spin_lock_bh(&tp->lock);
158d7abd 1380
ead2402c 1381 if (__tg3_readphy(tp, mii_id, reg, &val))
24bb4fb6
MC		 1382 val = -EIO;
1383
1384 spin_unlock_bh(&tp->lock);
158d7abd
MC		 1385
1386 return val;
1387}
1388
1389static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val)
1390{
3d16543d 1391 struct tg3 *tp = bp->priv;
24bb4fb6 1392 u32 ret = 0;
158d7abd 1393
24bb4fb6 1394 spin_lock_bh(&tp->lock);
158d7abd 1395
ead2402c 1396 if (__tg3_writephy(tp, mii_id, reg, val))
24bb4fb6 1397 ret = -EIO;
158d7abd 1398
24bb4fb6
MC		 1399 spin_unlock_bh(&tp->lock);
1400
1401 return ret;
158d7abd
MC		 1402}
1403
9c61d6bc 1404static void tg3_mdio_config_5785(struct tg3 *tp)
a9daf367
MC		 1405{
1406 u32 val;
fcb389df 1407 struct phy_device *phydev;
a9daf367 1408
ead2402c 1409 phydev = tp->mdio_bus->phy_map[tp->phy_addr];
fcb389df 1410 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
6a443a0f
MC		 1411 case PHY_ID_BCM50610:
1412 case PHY_ID_BCM50610M:
fcb389df
MC		 1413 val = MAC_PHYCFG2_50610_LED_MODES;
1414 break;
6a443a0f 1415 case PHY_ID_BCMAC131:
fcb389df
MC		 1416 val = MAC_PHYCFG2_AC131_LED_MODES;
1417 break;
6a443a0f 1418 case PHY_ID_RTL8211C:
fcb389df
MC		 1419 val = MAC_PHYCFG2_RTL8211C_LED_MODES;
1420 break;
6a443a0f 1421 case PHY_ID_RTL8201E:
fcb389df
MC		 1422 val = MAC_PHYCFG2_RTL8201E_LED_MODES;
1423 break;
1424 default:
a9daf367 1425 return;
fcb389df
MC		 1426 }
1427
1428 if (phydev->interface != PHY_INTERFACE_MODE_RGMII) {
1429 tw32(MAC_PHYCFG2, val);
1430
1431 val = tr32(MAC_PHYCFG1);
bb85fbb6
MC		 1432 val &= ~(MAC_PHYCFG1_RGMII_INT |
1433 MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK);
1434 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT;
fcb389df
MC		 1435 tw32(MAC_PHYCFG1, val);
1436
1437 return;
1438 }
1439
63c3a66f 1440 if (!tg3_flag(tp, RGMII_INBAND_DISABLE))
fcb389df
MC		 1441 val |= MAC_PHYCFG2_EMODE_MASK_MASK |
1442 MAC_PHYCFG2_FMODE_MASK_MASK |
1443 MAC_PHYCFG2_GMODE_MASK_MASK |
1444 MAC_PHYCFG2_ACT_MASK_MASK |
1445 MAC_PHYCFG2_QUAL_MASK_MASK |
1446 MAC_PHYCFG2_INBAND_ENABLE;
1447
1448 tw32(MAC_PHYCFG2, val);
a9daf367 1449
bb85fbb6
MC		 1450 val = tr32(MAC_PHYCFG1);
1451 val &= ~(MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK |
1452 MAC_PHYCFG1_RGMII_EXT_RX_DEC | MAC_PHYCFG1_RGMII_SND_STAT_EN);
63c3a66f
JP		 1453 if (!tg3_flag(tp, RGMII_INBAND_DISABLE)) {
1454 if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN))
a9daf367 1455 val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC;
63c3a66f 1456 if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN))
a9daf367
MC		 1457 val |= MAC_PHYCFG1_RGMII_SND_STAT_EN;
1458 }
bb85fbb6
MC		 1459 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT |
1460 MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV;
1461 tw32(MAC_PHYCFG1, val);
a9daf367 1462
a9daf367
MC		 1463 val = tr32(MAC_EXT_RGMII_MODE);
1464 val &= ~(MAC_RGMII_MODE_RX_INT_B |
1465 MAC_RGMII_MODE_RX_QUALITY |
1466 MAC_RGMII_MODE_RX_ACTIVITY |
1467 MAC_RGMII_MODE_RX_ENG_DET |
1468 MAC_RGMII_MODE_TX_ENABLE |
1469 MAC_RGMII_MODE_TX_LOWPWR |
1470 MAC_RGMII_MODE_TX_RESET);
63c3a66f
JP		 1471 if (!tg3_flag(tp, RGMII_INBAND_DISABLE)) {
1472 if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN))
a9daf367
MC		 1473 val |= MAC_RGMII_MODE_RX_INT_B |
1474 MAC_RGMII_MODE_RX_QUALITY |
1475 MAC_RGMII_MODE_RX_ACTIVITY |
1476 MAC_RGMII_MODE_RX_ENG_DET;
63c3a66f 1477 if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN))
a9daf367
MC		 1478 val |= MAC_RGMII_MODE_TX_ENABLE |
1479 MAC_RGMII_MODE_TX_LOWPWR |
1480 MAC_RGMII_MODE_TX_RESET;
1481 }
1482 tw32(MAC_EXT_RGMII_MODE, val);
1483}
1484
158d7abd
MC		 1485static void tg3_mdio_start(struct tg3 *tp)
1486{
158d7abd
MC		 1487 tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL;
1488 tw32_f(MAC_MI_MODE, tp->mi_mode);
1489 udelay(80);
a9daf367 1490
63c3a66f 1491 if (tg3_flag(tp, MDIOBUS_INITED) &&
4153577a 1492 tg3_asic_rev(tp) == ASIC_REV_5785)
9ea4818d
MC		 1493 tg3_mdio_config_5785(tp);
1494}
1495
1496static int tg3_mdio_init(struct tg3 *tp)
1497{
1498 int i;
1499 u32 reg;
1500 struct phy_device *phydev;
1501
63c3a66f 1502 if (tg3_flag(tp, 5717_PLUS)) {
9c7df915 1503 u32 is_serdes;
882e9793 1504
69f11c99 1505 tp->phy_addr = tp->pci_fn + 1;
882e9793 1506
4153577a 1507 if (tg3_chip_rev_id(tp) != CHIPREV_ID_5717_A0)
d1ec96af
MC		 1508 is_serdes = tr32(SG_DIG_STATUS) & SG_DIG_IS_SERDES;
1509 else
1510 is_serdes = tr32(TG3_CPMU_PHY_STRAP) &
1511 TG3_CPMU_PHY_STRAP_IS_SERDES;
882e9793
MC		 1512 if (is_serdes)
1513 tp->phy_addr += 7;
ee002b64
HM		 1514 } else if (tg3_flag(tp, IS_SSB_CORE) && tg3_flag(tp, ROBOSWITCH)) {
1515 int addr;
1516
1517 addr = ssb_gige_get_phyaddr(tp->pdev);
1518 if (addr < 0)
1519 return addr;
1520 tp->phy_addr = addr;
882e9793 1521 } else
3f0e3ad7 1522 tp->phy_addr = TG3_PHY_MII_ADDR;
882e9793 1523
158d7abd
MC		 1524 tg3_mdio_start(tp);
1525
63c3a66f 1526 if (!tg3_flag(tp, USE_PHYLIB) || tg3_flag(tp, MDIOBUS_INITED))
158d7abd
MC		 1527 return 0;
1528
298cf9be
LB		 1529 tp->mdio_bus = mdiobus_alloc();
1530 if (tp->mdio_bus == NULL)
1531 return -ENOMEM;
158d7abd 1532
298cf9be
LB		 1533 tp->mdio_bus->name = "tg3 mdio bus";
1534 snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x",
158d7abd 1535 (tp->pdev->bus->number << 8) | tp->pdev->devfn);
298cf9be
LB		 1536 tp->mdio_bus->priv = tp;
1537 tp->mdio_bus->parent = &tp->pdev->dev;
1538 tp->mdio_bus->read = &tg3_mdio_read;
1539 tp->mdio_bus->write = &tg3_mdio_write;
ead2402c 1540 tp->mdio_bus->phy_mask = ~(1 << tp->phy_addr);
298cf9be 1541 tp->mdio_bus->irq = &tp->mdio_irq[0];
158d7abd
MC		 1542
1543 for (i = 0; i < PHY_MAX_ADDR; i++)
298cf9be 1544 tp->mdio_bus->irq[i] = PHY_POLL;
158d7abd
MC		 1545
1546 /* The bus registration will look for all the PHYs on the mdio bus.
1547 * Unfortunately, it does not ensure the PHY is powered up before
1548 * accessing the PHY ID registers. A chip reset is the
1549 * quickest way to bring the device back to an operational state..
1550 */
1551 if (tg3_readphy(tp, MII_BMCR, &reg) || (reg & BMCR_PDOWN))
1552 tg3_bmcr_reset(tp);
1553
298cf9be 1554 i = mdiobus_register(tp->mdio_bus);
a9daf367 1555 if (i) {
ab96b241 1556 dev_warn(&tp->pdev->dev, "mdiobus_reg failed (0x%x)\n", i);
9c61d6bc 1557 mdiobus_free(tp->mdio_bus);
a9daf367
MC		 1558 return i;
1559 }
158d7abd 1560
ead2402c 1561 phydev = tp->mdio_bus->phy_map[tp->phy_addr];
a9daf367 1562
9c61d6bc 1563 if (!phydev || !phydev->drv) {
ab96b241 1564 dev_warn(&tp->pdev->dev, "No PHY devices\n");
9c61d6bc
MC		 1565 mdiobus_unregister(tp->mdio_bus);
1566 mdiobus_free(tp->mdio_bus);
1567 return -ENODEV;
1568 }
1569
1570 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
6a443a0f 1571 case PHY_ID_BCM57780:
321d32a0 1572 phydev->interface = PHY_INTERFACE_MODE_GMII;
c704dc23 1573 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
321d32a0 1574 break;
6a443a0f
MC		 1575 case PHY_ID_BCM50610:
1576 case PHY_ID_BCM50610M:
32e5a8d6 1577 phydev->dev_flags |= PHY_BRCM_CLEAR_RGMII_MODE |
c704dc23 1578 PHY_BRCM_RX_REFCLK_UNUSED |
52fae083 1579 PHY_BRCM_DIS_TXCRXC_NOENRGY |
c704dc23 1580 PHY_BRCM_AUTO_PWRDWN_ENABLE;
63c3a66f 1581 if (tg3_flag(tp, RGMII_INBAND_DISABLE))
a9daf367 1582 phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE;
63c3a66f 1583 if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN))
a9daf367 1584 phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE;
63c3a66f 1585 if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN))
a9daf367 1586 phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE;
fcb389df 1587 /* fallthru */
6a443a0f 1588 case PHY_ID_RTL8211C:
fcb389df 1589 phydev->interface = PHY_INTERFACE_MODE_RGMII;
a9daf367 1590 break;
6a443a0f
MC		 1591 case PHY_ID_RTL8201E:
1592 case PHY_ID_BCMAC131:
a9daf367 1593 phydev->interface = PHY_INTERFACE_MODE_MII;
cdd4e09d 1594 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
f07e9af3 1595 tp->phy_flags |= TG3_PHYFLG_IS_FET;
a9daf367
MC		 1596 break;
1597 }
1598
63c3a66f 1599 tg3_flag_set(tp, MDIOBUS_INITED);
9c61d6bc 1600
4153577a 1601 if (tg3_asic_rev(tp) == ASIC_REV_5785)
9c61d6bc 1602 tg3_mdio_config_5785(tp);
a9daf367
MC		 1603
1604 return 0;
158d7abd
MC		 1605}
1606
1607static void tg3_mdio_fini(struct tg3 *tp)
1608{
63c3a66f
JP		 1609 if (tg3_flag(tp, MDIOBUS_INITED)) {
1610 tg3_flag_clear(tp, MDIOBUS_INITED);
298cf9be
LB		 1611 mdiobus_unregister(tp->mdio_bus);
1612 mdiobus_free(tp->mdio_bus);
158d7abd
MC		 1613 }
1614}
1615
4ba526ce
MC		 1616/* tp->lock is held. */
1617static inline void tg3_generate_fw_event(struct tg3 *tp)
1618{
1619 u32 val;
1620
1621 val = tr32(GRC_RX_CPU_EVENT);
1622 val |= GRC_RX_CPU_DRIVER_EVENT;
1623 tw32_f(GRC_RX_CPU_EVENT, val);
1624
1625 tp->last_event_jiffies = jiffies;
1626}
1627
1628#define TG3_FW_EVENT_TIMEOUT_USEC 2500
1629
95e2869a
MC		 1630/* tp->lock is held. */
1631static void tg3_wait_for_event_ack(struct tg3 *tp)
1632{
1633 int i;
4ba526ce
MC		 1634 unsigned int delay_cnt;
1635 long time_remain;
1636
1637 /* If enough time has passed, no wait is necessary. */
1638 time_remain = (long)(tp->last_event_jiffies + 1 +
1639 usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) -
1640 (long)jiffies;
1641 if (time_remain < 0)
1642 return;
1643
1644 /* Check if we can shorten the wait time. */
1645 delay_cnt = jiffies_to_usecs(time_remain);
1646 if (delay_cnt > TG3_FW_EVENT_TIMEOUT_USEC)
1647 delay_cnt = TG3_FW_EVENT_TIMEOUT_USEC;
1648 delay_cnt = (delay_cnt >> 3) + 1;
95e2869a 1649
4ba526ce 1650 for (i = 0; i < delay_cnt; i++) {
95e2869a
MC		 1651 if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT))
1652 break;
6d446ec3
GS		 1653 if (pci_channel_offline(tp->pdev))
1654 break;
1655
4ba526ce 1656 udelay(8);
95e2869a
MC		 1657 }
1658}
1659
1660/* tp->lock is held. */
b28f389d 1661static void tg3_phy_gather_ump_data(struct tg3 *tp, u32 *data)
95e2869a 1662{
b28f389d 1663 u32 reg, val;
95e2869a
MC		 1664
1665 val = 0;
1666 if (!tg3_readphy(tp, MII_BMCR, &reg))
1667 val = reg << 16;
1668 if (!tg3_readphy(tp, MII_BMSR, &reg))
1669 val |= (reg & 0xffff);
b28f389d 1670 *data++ = val;
95e2869a
MC		 1671
1672 val = 0;
1673 if (!tg3_readphy(tp, MII_ADVERTISE, &reg))
1674 val = reg << 16;
1675 if (!tg3_readphy(tp, MII_LPA, &reg))
1676 val |= (reg & 0xffff);
b28f389d 1677 *data++ = val;
95e2869a
MC		 1678
1679 val = 0;
f07e9af3 1680 if (!(tp->phy_flags & TG3_PHYFLG_MII_SERDES)) {
95e2869a
MC		 1681 if (!tg3_readphy(tp, MII_CTRL1000, &reg))
1682 val = reg << 16;
1683 if (!tg3_readphy(tp, MII_STAT1000, &reg))
1684 val |= (reg & 0xffff);
1685 }
b28f389d 1686 *data++ = val;
95e2869a
MC		 1687
1688 if (!tg3_readphy(tp, MII_PHYADDR, &reg))
1689 val = reg << 16;
1690 else
1691 val = 0;
b28f389d
MC		 1692 *data++ = val;
1693}
1694
1695/* tp->lock is held. */
1696static void tg3_ump_link_report(struct tg3 *tp)
1697{
1698 u32 data[4];
1699
1700 if (!tg3_flag(tp, 5780_CLASS) || !tg3_flag(tp, ENABLE_ASF))
1701 return;
1702
1703 tg3_phy_gather_ump_data(tp, data);
1704
1705 tg3_wait_for_event_ack(tp);
1706
1707 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE);
1708 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14);
1709 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0x0, data[0]);
1710 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0x4, data[1]);
1711 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0x8, data[2]);
1712 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0xc, data[3]);
95e2869a 1713
4ba526ce 1714 tg3_generate_fw_event(tp);
95e2869a
MC		 1715}
1716
8d5a89b3
MC		 1717/* tp->lock is held. */
1718static void tg3_stop_fw(struct tg3 *tp)
1719{
1720 if (tg3_flag(tp, ENABLE_ASF) && !tg3_flag(tp, ENABLE_APE)) {
1721 /* Wait for RX cpu to ACK the previous event. */
1722 tg3_wait_for_event_ack(tp);
1723
1724 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
1725
1726 tg3_generate_fw_event(tp);
1727
1728 /* Wait for RX cpu to ACK this event. */
1729 tg3_wait_for_event_ack(tp);
1730 }
1731}
1732
fd6d3f0e
MC		 1733/* tp->lock is held. */
1734static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
1735{
1736 tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
1737 NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
1738
1739 if (tg3_flag(tp, ASF_NEW_HANDSHAKE)) {
1740 switch (kind) {
1741 case RESET_KIND_INIT:
1742 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1743 DRV_STATE_START);
1744 break;
1745
1746 case RESET_KIND_SHUTDOWN:
1747 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1748 DRV_STATE_UNLOAD);
1749 break;
1750
1751 case RESET_KIND_SUSPEND:
1752 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1753 DRV_STATE_SUSPEND);
1754 break;
1755
1756 default:
1757 break;
1758 }
1759 }
fd6d3f0e
MC		 1760}
1761
1762/* tp->lock is held. */
1763static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
1764{
1765 if (tg3_flag(tp, ASF_NEW_HANDSHAKE)) {
1766 switch (kind) {
1767 case RESET_KIND_INIT:
1768 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1769 DRV_STATE_START_DONE);
1770 break;
1771
1772 case RESET_KIND_SHUTDOWN:
1773 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1774 DRV_STATE_UNLOAD_DONE);
1775 break;
1776
1777 default:
1778 break;
1779 }
1780 }
fd6d3f0e
MC		 1781}
1782
1783/* tp->lock is held. */
1784static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
1785{
1786 if (tg3_flag(tp, ENABLE_ASF)) {
1787 switch (kind) {
1788 case RESET_KIND_INIT:
1789 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1790 DRV_STATE_START);
1791 break;
1792
1793 case RESET_KIND_SHUTDOWN:
1794 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1795 DRV_STATE_UNLOAD);
1796 break;
1797
1798 case RESET_KIND_SUSPEND:
1799 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1800 DRV_STATE_SUSPEND);
1801 break;
1802
1803 default:
1804 break;
1805 }
1806 }
1807}
1808
1809static int tg3_poll_fw(struct tg3 *tp)
1810{
1811 int i;
1812 u32 val;
1813
df465abf
NS		 1814 if (tg3_flag(tp, NO_FWARE_REPORTED))
1815 return 0;
1816
7e6c63f0
HM		 1817 if (tg3_flag(tp, IS_SSB_CORE)) {
1818 /* We don't use firmware. */
1819 return 0;
1820 }
1821
4153577a 1822 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
fd6d3f0e
MC		 1823 /* Wait up to 20ms for init done. */
1824 for (i = 0; i < 200; i++) {
1825 if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
1826 return 0;
6d446ec3
GS		 1827 if (pci_channel_offline(tp->pdev))
1828 return -ENODEV;
1829
fd6d3f0e
MC		 1830 udelay(100);
1831 }
1832 return -ENODEV;
1833 }
1834
1835 /* Wait for firmware initialization to complete. */
1836 for (i = 0; i < 100000; i++) {
1837 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
1838 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
1839 break;
6d446ec3
GS		 1840 if (pci_channel_offline(tp->pdev)) {
1841 if (!tg3_flag(tp, NO_FWARE_REPORTED)) {
1842 tg3_flag_set(tp, NO_FWARE_REPORTED);
1843 netdev_info(tp->dev, "No firmware running\n");
1844 }
1845
1846 break;
1847 }
1848
fd6d3f0e
MC		 1849 udelay(10);
1850 }
1851
1852 /* Chip might not be fitted with firmware. Some Sun onboard
1853 * parts are configured like that. So don't signal the timeout
1854 * of the above loop as an error, but do report the lack of
1855 * running firmware once.
1856 */
1857 if (i >= 100000 && !tg3_flag(tp, NO_FWARE_REPORTED)) {
1858 tg3_flag_set(tp, NO_FWARE_REPORTED);
1859
1860 netdev_info(tp->dev, "No firmware running\n");
1861 }
1862
4153577a 1863 if (tg3_chip_rev_id(tp) == CHIPREV_ID_57765_A0) {
fd6d3f0e
MC		 1864 /* The 57765 A0 needs a little more
1865 * time to do some important work.
1866 */
1867 mdelay(10);
1868 }
1869
1870 return 0;
1871}
1872
95e2869a
MC		 1873static void tg3_link_report(struct tg3 *tp)
1874{
1875 if (!netif_carrier_ok(tp->dev)) {
05dbe005 1876 netif_info(tp, link, tp->dev, "Link is down\n");
95e2869a
MC		 1877 tg3_ump_link_report(tp);
1878 } else if (netif_msg_link(tp)) {
05dbe005
JP		 1879 netdev_info(tp->dev, "Link is up at %d Mbps, %s duplex\n",
1880 (tp->link_config.active_speed == SPEED_1000 ?
1881 1000 :
1882 (tp->link_config.active_speed == SPEED_100 ?
1883 100 : 10)),
1884 (tp->link_config.active_duplex == DUPLEX_FULL ?
1885 "full" : "half"));
1886
1887 netdev_info(tp->dev, "Flow control is %s for TX and %s for RX\n",
1888 (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ?
1889 "on" : "off",
1890 (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ?
1891 "on" : "off");
47007831
MC		 1892
1893 if (tp->phy_flags & TG3_PHYFLG_EEE_CAP)
1894 netdev_info(tp->dev, "EEE is %s\n",
1895 tp->setlpicnt ? "enabled" : "disabled");
1896
95e2869a
MC		 1897 tg3_ump_link_report(tp);
1898 }
84421b99
NS		 1899
1900 tp->link_up = netif_carrier_ok(tp->dev);
95e2869a
MC		 1901}
1902
fdad8de4
NS		 1903static u32 tg3_decode_flowctrl_1000T(u32 adv)
1904{
1905 u32 flowctrl = 0;
1906
1907 if (adv & ADVERTISE_PAUSE_CAP) {
1908 flowctrl |= FLOW_CTRL_RX;
1909 if (!(adv & ADVERTISE_PAUSE_ASYM))
1910 flowctrl |= FLOW_CTRL_TX;
1911 } else if (adv & ADVERTISE_PAUSE_ASYM)
1912 flowctrl |= FLOW_CTRL_TX;
1913
1914 return flowctrl;
1915}
1916
95e2869a
MC		 1917static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl)
1918{
1919 u16 miireg;
1920
e18ce346 1921 if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
95e2869a 1922 miireg = ADVERTISE_1000XPAUSE;
e18ce346 1923 else if (flow_ctrl & FLOW_CTRL_TX)
95e2869a 1924 miireg = ADVERTISE_1000XPSE_ASYM;
e18ce346 1925 else if (flow_ctrl & FLOW_CTRL_RX)
95e2869a
MC		 1926 miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1927 else
1928 miireg = 0;
1929
1930 return miireg;
1931}
1932
fdad8de4
NS		 1933static u32 tg3_decode_flowctrl_1000X(u32 adv)
1934{
1935 u32 flowctrl = 0;
1936
1937 if (adv & ADVERTISE_1000XPAUSE) {
1938 flowctrl |= FLOW_CTRL_RX;
1939 if (!(adv & ADVERTISE_1000XPSE_ASYM))
1940 flowctrl |= FLOW_CTRL_TX;
1941 } else if (adv & ADVERTISE_1000XPSE_ASYM)
1942 flowctrl |= FLOW_CTRL_TX;
1943
1944 return flowctrl;
1945}
1946
95e2869a
MC		 1947static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv)
1948{
1949 u8 cap = 0;
1950
f3791cdf
MC		 1951 if (lcladv & rmtadv & ADVERTISE_1000XPAUSE) {
1952 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1953 } else if (lcladv & rmtadv & ADVERTISE_1000XPSE_ASYM) {
1954 if (lcladv & ADVERTISE_1000XPAUSE)
1955 cap = FLOW_CTRL_RX;
1956 if (rmtadv & ADVERTISE_1000XPAUSE)
e18ce346 1957 cap = FLOW_CTRL_TX;
95e2869a
MC		 1958 }
1959
1960 return cap;
1961}
1962
f51f3562 1963static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv)
95e2869a 1964{
b02fd9e3 1965 u8 autoneg;
f51f3562 1966 u8 flowctrl = 0;
95e2869a
MC		 1967 u32 old_rx_mode = tp->rx_mode;
1968 u32 old_tx_mode = tp->tx_mode;
1969
63c3a66f 1970 if (tg3_flag(tp, USE_PHYLIB))
ead2402c 1971 autoneg = tp->mdio_bus->phy_map[tp->phy_addr]->autoneg;
b02fd9e3
MC		 1972 else
1973 autoneg = tp->link_config.autoneg;
1974
63c3a66f 1975 if (autoneg == AUTONEG_ENABLE && tg3_flag(tp, PAUSE_AUTONEG)) {
f07e9af3 1976 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
f51f3562 1977 flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv);
95e2869a 1978 else
bc02ff95 1979 flowctrl = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
f51f3562
MC		 1980 } else
1981 flowctrl = tp->link_config.flowctrl;
95e2869a 1982
f51f3562 1983 tp->link_config.active_flowctrl = flowctrl;
95e2869a 1984
e18ce346 1985 if (flowctrl & FLOW_CTRL_RX)
95e2869a
MC		 1986 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1987 else
1988 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1989
f51f3562 1990 if (old_rx_mode != tp->rx_mode)
95e2869a 1991 tw32_f(MAC_RX_MODE, tp->rx_mode);
95e2869a 1992
e18ce346 1993 if (flowctrl & FLOW_CTRL_TX)
95e2869a
MC		 1994 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1995 else
1996 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1997
f51f3562 1998 if (old_tx_mode != tp->tx_mode)
95e2869a 1999 tw32_f(MAC_TX_MODE, tp->tx_mode);
95e2869a
MC		 2000}
2001
b02fd9e3
MC		 2002static void tg3_adjust_link(struct net_device *dev)
2003{
2004 u8 oldflowctrl, linkmesg = 0;
2005 u32 mac_mode, lcl_adv, rmt_adv;
2006 struct tg3 *tp = netdev_priv(dev);
ead2402c 2007 struct phy_device *phydev = tp->mdio_bus->phy_map[tp->phy_addr];
b02fd9e3 2008
24bb4fb6 2009 spin_lock_bh(&tp->lock);
b02fd9e3
MC		 2010
2011 mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK |
2012 MAC_MODE_HALF_DUPLEX);
2013
2014 oldflowctrl = tp->link_config.active_flowctrl;
2015
2016 if (phydev->link) {
2017 lcl_adv = 0;
2018 rmt_adv = 0;
2019
2020 if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10)
2021 mac_mode |= MAC_MODE_PORT_MODE_MII;
c3df0748 2022 else if (phydev->speed == SPEED_1000 ||
4153577a 2023 tg3_asic_rev(tp) != ASIC_REV_5785)
b02fd9e3 2024 mac_mode |= MAC_MODE_PORT_MODE_GMII;
c3df0748
MC		 2025 else
2026 mac_mode |= MAC_MODE_PORT_MODE_MII;
b02fd9e3
MC		 2027
2028 if (phydev->duplex == DUPLEX_HALF)
2029 mac_mode |= MAC_MODE_HALF_DUPLEX;
2030 else {
f88788f0 2031 lcl_adv = mii_advertise_flowctrl(
b02fd9e3
MC		 2032 tp->link_config.flowctrl);
2033
2034 if (phydev->pause)
2035 rmt_adv = LPA_PAUSE_CAP;
2036 if (phydev->asym_pause)
2037 rmt_adv |= LPA_PAUSE_ASYM;
2038 }
2039
2040 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
2041 } else
2042 mac_mode |= MAC_MODE_PORT_MODE_GMII;
2043
2044 if (mac_mode != tp->mac_mode) {
2045 tp->mac_mode = mac_mode;
2046 tw32_f(MAC_MODE, tp->mac_mode);
2047 udelay(40);
2048 }
2049
4153577a 2050 if (tg3_asic_rev(tp) == ASIC_REV_5785) {
fcb389df
MC		 2051 if (phydev->speed == SPEED_10)
2052 tw32(MAC_MI_STAT,
2053 MAC_MI_STAT_10MBPS_MODE |
2054 MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
2055 else
2056 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
2057 }
2058
b02fd9e3
MC		 2059 if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF)
2060 tw32(MAC_TX_LENGTHS,
2061 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
2062 (6 << TX_LENGTHS_IPG_SHIFT) |
2063 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
2064 else
2065 tw32(MAC_TX_LENGTHS,
2066 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
2067 (6 << TX_LENGTHS_IPG_SHIFT) |
2068 (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
2069
34655ad6 2070 if (phydev->link != tp->old_link ||
b02fd9e3
MC		 2071 phydev->speed != tp->link_config.active_speed ||
2072 phydev->duplex != tp->link_config.active_duplex ||
2073 oldflowctrl != tp->link_config.active_flowctrl)
c6cdf436 2074 linkmesg = 1;
b02fd9e3 2075
34655ad6 2076 tp->old_link = phydev->link;
b02fd9e3
MC		 2077 tp->link_config.active_speed = phydev->speed;
2078 tp->link_config.active_duplex = phydev->duplex;
2079
24bb4fb6 2080 spin_unlock_bh(&tp->lock);
b02fd9e3
MC		 2081
2082 if (linkmesg)
2083 tg3_link_report(tp);
2084}
2085
2086static int tg3_phy_init(struct tg3 *tp)
2087{
2088 struct phy_device *phydev;
2089
f07e9af3 2090 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)
b02fd9e3
MC		 2091 return 0;
2092
2093 /* Bring the PHY back to a known state. */
2094 tg3_bmcr_reset(tp);
2095
ead2402c 2096 phydev = tp->mdio_bus->phy_map[tp->phy_addr];
b02fd9e3
MC		 2097
2098 /* Attach the MAC to the PHY. */
f9a8f83b
FF		 2099 phydev = phy_connect(tp->dev, dev_name(&phydev->dev),
2100 tg3_adjust_link, phydev->interface);
b02fd9e3 2101 if (IS_ERR(phydev)) {
ab96b241 2102 dev_err(&tp->pdev->dev, "Could not attach to PHY\n");
b02fd9e3
MC		 2103 return PTR_ERR(phydev);
2104 }
2105
b02fd9e3 2106 /* Mask with MAC supported features. */
9c61d6bc
MC		 2107 switch (phydev->interface) {
2108 case PHY_INTERFACE_MODE_GMII:
2109 case PHY_INTERFACE_MODE_RGMII:
f07e9af3 2110 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
321d32a0
MC		 2111 phydev->supported &= (PHY_GBIT_FEATURES |
2112 SUPPORTED_Pause |
2113 SUPPORTED_Asym_Pause);
2114 break;
2115 }
2116 /* fallthru */
9c61d6bc
MC		 2117 case PHY_INTERFACE_MODE_MII:
2118 phydev->supported &= (PHY_BASIC_FEATURES |
2119 SUPPORTED_Pause |
2120 SUPPORTED_Asym_Pause);
2121 break;
2122 default:
ead2402c 2123 phy_disconnect(tp->mdio_bus->phy_map[tp->phy_addr]);
9c61d6bc
MC		 2124 return -EINVAL;
2125 }
2126
f07e9af3 2127 tp->phy_flags |= TG3_PHYFLG_IS_CONNECTED;
b02fd9e3
MC		 2128
2129 phydev->advertising = phydev->supported;
2130
b02fd9e3
MC		 2131 return 0;
2132}
2133
2134static void tg3_phy_start(struct tg3 *tp)
2135{
2136 struct phy_device *phydev;
2137
f07e9af3 2138 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
b02fd9e3
MC		 2139 return;
2140
ead2402c 2141 phydev = tp->mdio_bus->phy_map[tp->phy_addr];
b02fd9e3 2142
80096068
MC		 2143 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
2144 tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER;
c6700ce2
MC		 2145 phydev->speed = tp->link_config.speed;
2146 phydev->duplex = tp->link_config.duplex;
2147 phydev->autoneg = tp->link_config.autoneg;
2148 phydev->advertising = tp->link_config.advertising;
b02fd9e3
MC		 2149 }
2150
2151 phy_start(phydev);
2152
2153 phy_start_aneg(phydev);
2154}
2155
2156static void tg3_phy_stop(struct tg3 *tp)
2157{
f07e9af3 2158 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
b02fd9e3
MC		 2159 return;
2160
ead2402c 2161 phy_stop(tp->mdio_bus->phy_map[tp->phy_addr]);
b02fd9e3
MC		 2162}
2163
2164static void tg3_phy_fini(struct tg3 *tp)
2165{
f07e9af3 2166 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
ead2402c 2167 phy_disconnect(tp->mdio_bus->phy_map[tp->phy_addr]);
f07e9af3 2168 tp->phy_flags &= ~TG3_PHYFLG_IS_CONNECTED;
b02fd9e3
MC		 2169 }
2170}
2171
941ec90f
MC		 2172static int tg3_phy_set_extloopbk(struct tg3 *tp)
2173{
2174 int err;
2175 u32 val;
2176
2177 if (tp->phy_flags & TG3_PHYFLG_IS_FET)
2178 return 0;
2179
2180 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
2181 /* Cannot do read-modify-write on 5401 */
2182 err = tg3_phy_auxctl_write(tp,
2183 MII_TG3_AUXCTL_SHDWSEL_AUXCTL,
2184 MII_TG3_AUXCTL_ACTL_EXTLOOPBK |
2185 0x4c20);
2186 goto done;
2187 }
2188
2189 err = tg3_phy_auxctl_read(tp,
2190 MII_TG3_AUXCTL_SHDWSEL_AUXCTL, &val);
2191 if (err)
2192 return err;
2193
2194 val |= MII_TG3_AUXCTL_ACTL_EXTLOOPBK;
2195 err = tg3_phy_auxctl_write(tp,
2196 MII_TG3_AUXCTL_SHDWSEL_AUXCTL, val);
2197
2198done:
2199 return err;
2200}
2201
7f97a4bd
MC		 2202static void tg3_phy_fet_toggle_apd(struct tg3 *tp, bool enable)
2203{
2204 u32 phytest;
2205
2206 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
2207 u32 phy;
2208
2209 tg3_writephy(tp, MII_TG3_FET_TEST,
2210 phytest | MII_TG3_FET_SHADOW_EN);
2211 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXSTAT2, &phy)) {
2212 if (enable)
2213 phy |= MII_TG3_FET_SHDW_AUXSTAT2_APD;
2214 else
2215 phy &= ~MII_TG3_FET_SHDW_AUXSTAT2_APD;
2216 tg3_writephy(tp, MII_TG3_FET_SHDW_AUXSTAT2, phy);
2217 }
2218 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
2219 }
2220}
2221
6833c043
MC		 2222static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable)
2223{
2224 u32 reg;
2225
63c3a66f
JP		 2226 if (!tg3_flag(tp, 5705_PLUS) ||
2227 (tg3_flag(tp, 5717_PLUS) &&
f07e9af3 2228 (tp->phy_flags & TG3_PHYFLG_MII_SERDES)))
6833c043
MC		 2229 return;
2230
f07e9af3 2231 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
7f97a4bd
MC		 2232 tg3_phy_fet_toggle_apd(tp, enable);
2233 return;
2234 }
2235
3ab71071 2236 reg = MII_TG3_MISC_SHDW_SCR5_LPED |
6833c043
MC		 2237 MII_TG3_MISC_SHDW_SCR5_DLPTLM |
2238 MII_TG3_MISC_SHDW_SCR5_SDTL |
2239 MII_TG3_MISC_SHDW_SCR5_C125OE;
4153577a 2240 if (tg3_asic_rev(tp) != ASIC_REV_5784 || !enable)
6833c043
MC		 2241 reg |= MII_TG3_MISC_SHDW_SCR5_DLLAPD;
2242
3ab71071 2243 tg3_phy_shdw_write(tp, MII_TG3_MISC_SHDW_SCR5_SEL, reg);
6833c043
MC		 2244
2245
3ab71071 2246 reg = MII_TG3_MISC_SHDW_APD_WKTM_84MS;
6833c043
MC		 2247 if (enable)
2248 reg |= MII_TG3_MISC_SHDW_APD_ENABLE;
2249
3ab71071 2250 tg3_phy_shdw_write(tp, MII_TG3_MISC_SHDW_APD_SEL, reg);
6833c043
MC		 2251}
2252
953c96e0 2253static void tg3_phy_toggle_automdix(struct tg3 *tp, bool enable)
9ef8ca99
MC		 2254{
2255 u32 phy;
2256
63c3a66f 2257 if (!tg3_flag(tp, 5705_PLUS) ||
f07e9af3 2258 (tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
9ef8ca99
MC		 2259 return;
2260
f07e9af3 2261 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
9ef8ca99
MC		 2262 u32 ephy;
2263
535ef6e1
MC		 2264 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &ephy)) {
2265 u32 reg = MII_TG3_FET_SHDW_MISCCTRL;
2266
2267 tg3_writephy(tp, MII_TG3_FET_TEST,
2268 ephy | MII_TG3_FET_SHADOW_EN);
2269 if (!tg3_readphy(tp, reg, &phy)) {
9ef8ca99 2270 if (enable)
535ef6e1 2271 phy |= MII_TG3_FET_SHDW_MISCCTRL_MDIX;
9ef8ca99 2272 else
535ef6e1
MC		 2273 phy &= ~MII_TG3_FET_SHDW_MISCCTRL_MDIX;
2274 tg3_writephy(tp, reg, phy);
9ef8ca99 2275 }
535ef6e1 2276 tg3_writephy(tp, MII_TG3_FET_TEST, ephy);
9ef8ca99
MC		 2277 }
2278 } else {
15ee95c3
MC		 2279 int ret;
2280
2281 ret = tg3_phy_auxctl_read(tp,
2282 MII_TG3_AUXCTL_SHDWSEL_MISC, &phy);
2283 if (!ret) {
9ef8ca99
MC		 2284 if (enable)
2285 phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
2286 else
2287 phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
b4bd2929
MC		 2288 tg3_phy_auxctl_write(tp,
2289 MII_TG3_AUXCTL_SHDWSEL_MISC, phy);
9ef8ca99
MC		 2290 }
2291 }
2292}
2293
1da177e4
LT		 2294static void tg3_phy_set_wirespeed(struct tg3 *tp)
2295{
15ee95c3 2296 int ret;
1da177e4
LT		 2297 u32 val;
2298
f07e9af3 2299 if (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED)
1da177e4
LT		 2300 return;
2301
15ee95c3
MC		 2302 ret = tg3_phy_auxctl_read(tp, MII_TG3_AUXCTL_SHDWSEL_MISC, &val);
2303 if (!ret)
b4bd2929
MC		 2304 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_MISC,
2305 val | MII_TG3_AUXCTL_MISC_WIRESPD_EN);
1da177e4
LT		 2306}
2307
b2a5c19c
MC		 2308static void tg3_phy_apply_otp(struct tg3 *tp)
2309{
2310 u32 otp, phy;
2311
2312 if (!tp->phy_otp)
2313 return;
2314
2315 otp = tp->phy_otp;
2316
daf3ec68 2317 if (tg3_phy_toggle_auxctl_smdsp(tp, true))
1d36ba45 2318 return;
b2a5c19c
MC		 2319
2320 phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT);
2321 phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT;
2322 tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy);
2323
2324 phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) |
2325 ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT);
2326 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy);
2327
2328 phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT);
2329 phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ;
2330 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy);
2331
2332 phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT);
2333 tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy);
2334
2335 phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT);
2336 tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy);
2337
2338 phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) |
2339 ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT);
2340 tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy);
2341
daf3ec68 2342 tg3_phy_toggle_auxctl_smdsp(tp, false);
b2a5c19c
MC		 2343}
2344
400dfbaa
NS		 2345static void tg3_eee_pull_config(struct tg3 *tp, struct ethtool_eee *eee)
2346{
2347 u32 val;
2348 struct ethtool_eee *dest = &tp->eee;
2349
2350 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP))
2351 return;
2352
2353 if (eee)
2354 dest = eee;
2355
2356 if (tg3_phy_cl45_read(tp, MDIO_MMD_AN, TG3_CL45_D7_EEERES_STAT, &val))
2357 return;
2358
2359 /* Pull eee_active */
2360 if (val == TG3_CL45_D7_EEERES_STAT_LP_1000T ||
2361 val == TG3_CL45_D7_EEERES_STAT_LP_100TX) {
2362 dest->eee_active = 1;
2363 } else
2364 dest->eee_active = 0;
2365
2366 /* Pull lp advertised settings */
2367 if (tg3_phy_cl45_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_LPABLE, &val))
2368 return;
2369 dest->lp_advertised = mmd_eee_adv_to_ethtool_adv_t(val);
2370
2371 /* Pull advertised and eee_enabled settings */
2372 if (tg3_phy_cl45_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, &val))
2373 return;
2374 dest->eee_enabled = !!val;
2375 dest->advertised = mmd_eee_adv_to_ethtool_adv_t(val);
2376
2377 /* Pull tx_lpi_enabled */
2378 val = tr32(TG3_CPMU_EEE_MODE);
2379 dest->tx_lpi_enabled = !!(val & TG3_CPMU_EEEMD_LPI_IN_TX);
2380
2381 /* Pull lpi timer value */
2382 dest->tx_lpi_timer = tr32(TG3_CPMU_EEE_DBTMR1) & 0xffff;
2383}
2384
953c96e0 2385static void tg3_phy_eee_adjust(struct tg3 *tp, bool current_link_up)
52b02d04
MC		 2386{
2387 u32 val;
2388
2389 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP))
2390 return;
2391
2392 tp->setlpicnt = 0;
2393
2394 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
953c96e0 2395 current_link_up &&
a6b68dab
MC		 2396 tp->link_config.active_duplex == DUPLEX_FULL &&
2397 (tp->link_config.active_speed == SPEED_100 ||
2398 tp->link_config.active_speed == SPEED_1000)) {
52b02d04
MC		 2399 u32 eeectl;
2400
2401 if (tp->link_config.active_speed == SPEED_1000)
2402 eeectl = TG3_CPMU_EEE_CTRL_EXIT_16_5_US;
2403 else
2404 eeectl = TG3_CPMU_EEE_CTRL_EXIT_36_US;
2405
2406 tw32(TG3_CPMU_EEE_CTRL, eeectl);
2407
400dfbaa
NS		 2408 tg3_eee_pull_config(tp, NULL);
2409 if (tp->eee.eee_active)
52b02d04
MC		 2410 tp->setlpicnt = 2;
2411 }
2412
2413 if (!tp->setlpicnt) {
953c96e0 2414 if (current_link_up &&
daf3ec68 2415 !tg3_phy_toggle_auxctl_smdsp(tp, true)) {
b715ce94 2416 tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, 0x0000);
daf3ec68 2417 tg3_phy_toggle_auxctl_smdsp(tp, false);
b715ce94
MC		 2418 }
2419
52b02d04
MC		 2420 val = tr32(TG3_CPMU_EEE_MODE);
2421 tw32(TG3_CPMU_EEE_MODE, val & ~TG3_CPMU_EEEMD_LPI_ENABLE);
2422 }
2423}
2424
b0c5943f
MC		 2425static void tg3_phy_eee_enable(struct tg3 *tp)
2426{
2427 u32 val;
2428
2429 if (tp->link_config.active_speed == SPEED_1000 &&
4153577a
JP		 2430 (tg3_asic_rev(tp) == ASIC_REV_5717 ||
2431 tg3_asic_rev(tp) == ASIC_REV_5719 ||
55086ad9 2432 tg3_flag(tp, 57765_CLASS)) &&
daf3ec68 2433 !tg3_phy_toggle_auxctl_smdsp(tp, true)) {
b715ce94
MC		 2434 val = MII_TG3_DSP_TAP26_ALNOKO |
2435 MII_TG3_DSP_TAP26_RMRXSTO;
2436 tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, val);
daf3ec68 2437 tg3_phy_toggle_auxctl_smdsp(tp, false);
b0c5943f
MC		 2438 }
2439
2440 val = tr32(TG3_CPMU_EEE_MODE);
2441 tw32(TG3_CPMU_EEE_MODE, val | TG3_CPMU_EEEMD_LPI_ENABLE);
2442}
2443
1da177e4
LT		 2444static int tg3_wait_macro_done(struct tg3 *tp)
2445{
2446 int limit = 100;
2447
2448 while (limit--) {
2449 u32 tmp32;
2450
f08aa1a8 2451 if (!tg3_readphy(tp, MII_TG3_DSP_CONTROL, &tmp32)) {
1da177e4
LT		 2452 if ((tmp32 & 0x1000) == 0)
2453 break;
2454 }
2455 }
d4675b52 2456 if (limit < 0)
1da177e4
LT		 2457 return -EBUSY;
2458
2459 return 0;
2460}
2461
2462static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
2463{
2464 static const u32 test_pat[4][6] = {
2465 { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
2466 { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
2467 { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
2468 { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
2469 };
2470 int chan;
2471
2472 for (chan = 0; chan < 4; chan++) {
2473 int i;
2474
2475 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
2476 (chan * 0x2000) | 0x0200);
f08aa1a8 2477 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002);
1da177e4
LT		 2478
2479 for (i = 0; i < 6; i++)
2480 tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
2481 test_pat[chan][i]);
2482
f08aa1a8 2483 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202);
1da177e4
LT		 2484 if (tg3_wait_macro_done(tp)) {
2485 *resetp = 1;
2486 return -EBUSY;
2487 }
2488
2489 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
2490 (chan * 0x2000) | 0x0200);
f08aa1a8 2491 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0082);
1da177e4
LT		 2492 if (tg3_wait_macro_done(tp)) {
2493 *resetp = 1;
2494 return -EBUSY;
2495 }
2496
f08aa1a8 2497 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0802);
1da177e4
LT		 2498 if (tg3_wait_macro_done(tp)) {
2499 *resetp = 1;
2500 return -EBUSY;
2501 }
2502
2503 for (i = 0; i < 6; i += 2) {
2504 u32 low, high;
2505
2506 if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
2507 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
2508 tg3_wait_macro_done(tp)) {
2509 *resetp = 1;
2510 return -EBUSY;
2511 }
2512 low &= 0x7fff;
2513 high &= 0x000f;
2514 if (low != test_pat[chan][i] ||
2515 high != test_pat[chan][i+1]) {
2516 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
2517 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
2518 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
2519
2520 return -EBUSY;
2521 }
2522 }
2523 }
2524
2525 return 0;
2526}
2527
2528static int tg3_phy_reset_chanpat(struct tg3 *tp)
2529{
2530 int chan;
2531
2532 for (chan = 0; chan < 4; chan++) {
2533 int i;
2534
2535 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
2536 (chan * 0x2000) | 0x0200);
f08aa1a8 2537 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002);
1da177e4
LT		 2538 for (i = 0; i < 6; i++)
2539 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
f08aa1a8 2540 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202);
1da177e4
LT		 2541 if (tg3_wait_macro_done(tp))
2542 return -EBUSY;
2543 }
2544
2545 return 0;
2546}
2547
2548static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
2549{
2550 u32 reg32, phy9_orig;
2551 int retries, do_phy_reset, err;
2552
2553 retries = 10;
2554 do_phy_reset = 1;
2555 do {
2556 if (do_phy_reset) {
2557 err = tg3_bmcr_reset(tp);
2558 if (err)
2559 return err;
2560 do_phy_reset = 0;
2561 }
2562
2563 /* Disable transmitter and interrupt. */
2564 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
2565 continue;
2566
2567 reg32 |= 0x3000;
2568 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
2569
2570 /* Set full-duplex, 1000 mbps. */
2571 tg3_writephy(tp, MII_BMCR,
221c5637 2572 BMCR_FULLDPLX | BMCR_SPEED1000);
1da177e4
LT		 2573
2574 /* Set to master mode. */
221c5637 2575 if (tg3_readphy(tp, MII_CTRL1000, &phy9_orig))
1da177e4
LT		 2576 continue;
2577
221c5637
MC		 2578 tg3_writephy(tp, MII_CTRL1000,
2579 CTL1000_AS_MASTER | CTL1000_ENABLE_MASTER);
1da177e4 2580
daf3ec68 2581 err = tg3_phy_toggle_auxctl_smdsp(tp, true);
1d36ba45
MC		 2582 if (err)
2583 return err;
1da177e4
LT		 2584
2585 /* Block the PHY control access. */
6ee7c0a0 2586 tg3_phydsp_write(tp, 0x8005, 0x0800);
1da177e4
LT		 2587
2588 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
2589 if (!err)
2590 break;
2591 } while (--retries);
2592
2593 err = tg3_phy_reset_chanpat(tp);
2594 if (err)
2595 return err;
2596
6ee7c0a0 2597 tg3_phydsp_write(tp, 0x8005, 0x0000);
1da177e4
LT		 2598
2599 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
f08aa1a8 2600 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0000);
1da177e4 2601
daf3ec68 2602 tg3_phy_toggle_auxctl_smdsp(tp, false);
1da177e4 2603
221c5637 2604 tg3_writephy(tp, MII_CTRL1000, phy9_orig);
1da177e4 2605
c6e27f2f
DC		 2606 err = tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32);
2607 if (err)
2608 return err;
1da177e4 2609
c6e27f2f
DC		 2610 reg32 &= ~0x3000;
2611 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
2612
2613 return 0;
1da177e4
LT		 2614}
2615
f4a46d1f
NNS		 2616static void tg3_carrier_off(struct tg3 *tp)
2617{
2618 netif_carrier_off(tp->dev);
2619 tp->link_up = false;
2620}
2621
ce20f161
NS		 2622static void tg3_warn_mgmt_link_flap(struct tg3 *tp)
2623{
2624 if (tg3_flag(tp, ENABLE_ASF))
2625 netdev_warn(tp->dev,
2626 "Management side-band traffic will be interrupted during phy settings change\n");
2627}
2628
1da177e4
LT		 2629/* This will reset the tigon3 PHY if there is no valid
2630 * link unless the FORCE argument is non-zero.
2631 */
2632static int tg3_phy_reset(struct tg3 *tp)
2633{
f833c4c1 2634 u32 val, cpmuctrl;
1da177e4
LT		 2635 int err;
2636
4153577a 2637 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
60189ddf
MC		 2638 val = tr32(GRC_MISC_CFG);
2639 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
2640 udelay(40);
2641 }
f833c4c1
MC		 2642 err = tg3_readphy(tp, MII_BMSR, &val);
2643 err |= tg3_readphy(tp, MII_BMSR, &val);
1da177e4
LT		 2644 if (err != 0)
2645 return -EBUSY;
2646
f4a46d1f 2647 if (netif_running(tp->dev) && tp->link_up) {
84421b99 2648 netif_carrier_off(tp->dev);
c8e1e82b
MC		 2649 tg3_link_report(tp);
2650 }
2651
4153577a
JP		 2652 if (tg3_asic_rev(tp) == ASIC_REV_5703 ||
2653 tg3_asic_rev(tp) == ASIC_REV_5704 ||
2654 tg3_asic_rev(tp) == ASIC_REV_5705) {
1da177e4
LT		 2655 err = tg3_phy_reset_5703_4_5(tp);
2656 if (err)
2657 return err;
2658 goto out;
2659 }
2660
b2a5c19c 2661 cpmuctrl = 0;
4153577a
JP		 2662 if (tg3_asic_rev(tp) == ASIC_REV_5784 &&
2663 tg3_chip_rev(tp) != CHIPREV_5784_AX) {
b2a5c19c
MC		 2664 cpmuctrl = tr32(TG3_CPMU_CTRL);
2665 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY)
2666 tw32(TG3_CPMU_CTRL,
2667 cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY);
2668 }
2669
1da177e4
LT		 2670 err = tg3_bmcr_reset(tp);
2671 if (err)
2672 return err;
2673
b2a5c19c 2674 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) {
f833c4c1
MC		 2675 val = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz;
2676 tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, val);
b2a5c19c
MC		 2677
2678 tw32(TG3_CPMU_CTRL, cpmuctrl);
2679 }
2680
4153577a
JP		 2681 if (tg3_chip_rev(tp) == CHIPREV_5784_AX ||
2682 tg3_chip_rev(tp) == CHIPREV_5761_AX) {
ce057f01
MC		 2683 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2684 if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) ==
2685 CPMU_LSPD_1000MB_MACCLK_12_5) {
2686 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2687 udelay(40);
2688 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2689 }
2690 }
2691
63c3a66f 2692 if (tg3_flag(tp, 5717_PLUS) &&
f07e9af3 2693 (tp->phy_flags & TG3_PHYFLG_MII_SERDES))
ecf1410b
MC		 2694 return 0;
2695
b2a5c19c
MC		 2696 tg3_phy_apply_otp(tp);
2697
f07e9af3 2698 if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD)
6833c043
MC		 2699 tg3_phy_toggle_apd(tp, true);
2700 else
2701 tg3_phy_toggle_apd(tp, false);
2702
1da177e4 2703out:
1d36ba45 2704 if ((tp->phy_flags & TG3_PHYFLG_ADC_BUG) &&
daf3ec68 2705 !tg3_phy_toggle_auxctl_smdsp(tp, true)) {
6ee7c0a0
MC		 2706 tg3_phydsp_write(tp, 0x201f, 0x2aaa);
2707 tg3_phydsp_write(tp, 0x000a, 0x0323);
daf3ec68 2708 tg3_phy_toggle_auxctl_smdsp(tp, false);
1da177e4 2709 }
1d36ba45 2710
f07e9af3 2711 if (tp->phy_flags & TG3_PHYFLG_5704_A0_BUG) {
f08aa1a8
MC		 2712 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
2713 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
1da177e4 2714 }
1d36ba45 2715
f07e9af3 2716 if (tp->phy_flags & TG3_PHYFLG_BER_BUG) {
daf3ec68 2717 if (!tg3_phy_toggle_auxctl_smdsp(tp, true)) {
1d36ba45
MC		 2718 tg3_phydsp_write(tp, 0x000a, 0x310b);
2719 tg3_phydsp_write(tp, 0x201f, 0x9506);
2720 tg3_phydsp_write(tp, 0x401f, 0x14e2);
daf3ec68 2721 tg3_phy_toggle_auxctl_smdsp(tp, false);
1d36ba45 2722 }
f07e9af3 2723 } else if (tp->phy_flags & TG3_PHYFLG_JITTER_BUG) {
daf3ec68 2724 if (!tg3_phy_toggle_auxctl_smdsp(tp, true)) {
1d36ba45
MC		 2725 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
2726 if (tp->phy_flags & TG3_PHYFLG_ADJUST_TRIM) {
2727 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
2728 tg3_writephy(tp, MII_TG3_TEST1,
2729 MII_TG3_TEST1_TRIM_EN | 0x4);
2730 } else
2731 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
2732
daf3ec68 2733 tg3_phy_toggle_auxctl_smdsp(tp, false);
1d36ba45 2734 }
c424cb24 2735 }
1d36ba45 2736
1da177e4
LT		 2737 /* Set Extended packet length bit (bit 14) on all chips that */
2738 /* support jumbo frames */
79eb6904 2739 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
1da177e4 2740 /* Cannot do read-modify-write on 5401 */
b4bd2929 2741 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, 0x4c20);
63c3a66f 2742 } else if (tg3_flag(tp, JUMBO_CAPABLE)) {
1da177e4 2743 /* Set bit 14 with read-modify-write to preserve other bits */
15ee95c3
MC		 2744 err = tg3_phy_auxctl_read(tp,
2745 MII_TG3_AUXCTL_SHDWSEL_AUXCTL, &val);
2746 if (!err)
b4bd2929
MC		 2747 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL,
2748 val | MII_TG3_AUXCTL_ACTL_EXTPKTLEN);
1da177e4
LT		 2749 }
2750
2751 /* Set phy register 0x10 bit 0 to high fifo elasticity to support
2752 * jumbo frames transmission.
2753 */
63c3a66f 2754 if (tg3_flag(tp, JUMBO_CAPABLE)) {
f833c4c1 2755 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &val))
c6cdf436 2756 tg3_writephy(tp, MII_TG3_EXT_CTRL,
f833c4c1 2757 val | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
1da177e4
LT		 2758 }
2759
4153577a 2760 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
715116a1 2761 /* adjust output voltage */
535ef6e1 2762 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x12);
715116a1
MC		 2763 }
2764
4153577a 2765 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5762_A0)
c65a17f4
MC		 2766 tg3_phydsp_write(tp, 0xffb, 0x4000);
2767
953c96e0 2768 tg3_phy_toggle_automdix(tp, true);
1da177e4
LT		 2769 tg3_phy_set_wirespeed(tp);
2770 return 0;
2771}
2772
3a1e19d3
MC		 2773#define TG3_GPIO_MSG_DRVR_PRES 0x00000001
2774#define TG3_GPIO_MSG_NEED_VAUX 0x00000002
2775#define TG3_GPIO_MSG_MASK (TG3_GPIO_MSG_DRVR_PRES | \
2776 TG3_GPIO_MSG_NEED_VAUX)
2777#define TG3_GPIO_MSG_ALL_DRVR_PRES_MASK \
2778 ((TG3_GPIO_MSG_DRVR_PRES << 0) | \
2779 (TG3_GPIO_MSG_DRVR_PRES << 4) | \
2780 (TG3_GPIO_MSG_DRVR_PRES << 8) | \
2781 (TG3_GPIO_MSG_DRVR_PRES << 12))
2782
2783#define TG3_GPIO_MSG_ALL_NEED_VAUX_MASK \
2784 ((TG3_GPIO_MSG_NEED_VAUX << 0) | \
2785 (TG3_GPIO_MSG_NEED_VAUX << 4) | \
2786 (TG3_GPIO_MSG_NEED_VAUX << 8) | \
2787 (TG3_GPIO_MSG_NEED_VAUX << 12))
2788
2789static inline u32 tg3_set_function_status(struct tg3 *tp, u32 newstat)
2790{
2791 u32 status, shift;
2792
4153577a
JP		 2793 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
2794 tg3_asic_rev(tp) == ASIC_REV_5719)
3a1e19d3
MC		 2795 status = tg3_ape_read32(tp, TG3_APE_GPIO_MSG);
2796 else
2797 status = tr32(TG3_CPMU_DRV_STATUS);
2798
2799 shift = TG3_APE_GPIO_MSG_SHIFT + 4 * tp->pci_fn;
2800 status &= ~(TG3_GPIO_MSG_MASK << shift);
2801 status |= (newstat << shift);
2802
4153577a
JP		 2803 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
2804 tg3_asic_rev(tp) == ASIC_REV_5719)
3a1e19d3
MC		 2805 tg3_ape_write32(tp, TG3_APE_GPIO_MSG, status);
2806 else
2807 tw32(TG3_CPMU_DRV_STATUS, status);
2808
2809 return status >> TG3_APE_GPIO_MSG_SHIFT;
2810}
2811
520b2756
MC		 2812static inline int tg3_pwrsrc_switch_to_vmain(struct tg3 *tp)
2813{
2814 if (!tg3_flag(tp, IS_NIC))
2815 return 0;
2816
4153577a
JP		 2817 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
2818 tg3_asic_rev(tp) == ASIC_REV_5719 ||
2819 tg3_asic_rev(tp) == ASIC_REV_5720) {
3a1e19d3
MC		 2820 if (tg3_ape_lock(tp, TG3_APE_LOCK_GPIO))
2821 return -EIO;
520b2756 2822
3a1e19d3
MC		 2823 tg3_set_function_status(tp, TG3_GPIO_MSG_DRVR_PRES);
2824
2825 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl,
2826 TG3_GRC_LCLCTL_PWRSW_DELAY);
2827
2828 tg3_ape_unlock(tp, TG3_APE_LOCK_GPIO);
2829 } else {
2830 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl,
2831 TG3_GRC_LCLCTL_PWRSW_DELAY);
2832 }
6f5c8f83 2833
520b2756
MC		 2834 return 0;
2835}
2836
2837static void tg3_pwrsrc_die_with_vmain(struct tg3 *tp)
2838{
2839 u32 grc_local_ctrl;
2840
2841 if (!tg3_flag(tp, IS_NIC) ||
4153577a
JP		 2842 tg3_asic_rev(tp) == ASIC_REV_5700 ||
2843 tg3_asic_rev(tp) == ASIC_REV_5701)
520b2756
MC		 2844 return;
2845
2846 grc_local_ctrl = tp->grc_local_ctrl | GRC_LCLCTRL_GPIO_OE1;
2847
2848 tw32_wait_f(GRC_LOCAL_CTRL,
2849 grc_local_ctrl | GRC_LCLCTRL_GPIO_OUTPUT1,
2850 TG3_GRC_LCLCTL_PWRSW_DELAY);
2851
2852 tw32_wait_f(GRC_LOCAL_CTRL,
2853 grc_local_ctrl,
2854 TG3_GRC_LCLCTL_PWRSW_DELAY);
2855
2856 tw32_wait_f(GRC_LOCAL_CTRL,
2857 grc_local_ctrl | GRC_LCLCTRL_GPIO_OUTPUT1,
2858 TG3_GRC_LCLCTL_PWRSW_DELAY);
2859}
2860
2861static void tg3_pwrsrc_switch_to_vaux(struct tg3 *tp)
2862{
2863 if (!tg3_flag(tp, IS_NIC))
2864 return;
2865
4153577a
JP		 2866 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
2867 tg3_asic_rev(tp) == ASIC_REV_5701) {
520b2756
MC		 2868 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2869 (GRC_LCLCTRL_GPIO_OE0 |
2870 GRC_LCLCTRL_GPIO_OE1 |
2871 GRC_LCLCTRL_GPIO_OE2 |
2872 GRC_LCLCTRL_GPIO_OUTPUT0 |
2873 GRC_LCLCTRL_GPIO_OUTPUT1),
2874 TG3_GRC_LCLCTL_PWRSW_DELAY);
2875 } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
2876 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
2877 /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */
2878 u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
2879 GRC_LCLCTRL_GPIO_OE1 |
2880 GRC_LCLCTRL_GPIO_OE2 |
2881 GRC_LCLCTRL_GPIO_OUTPUT0 |
2882 GRC_LCLCTRL_GPIO_OUTPUT1 |
2883 tp->grc_local_ctrl;
2884 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl,
2885 TG3_GRC_LCLCTL_PWRSW_DELAY);
2886
2887 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2;
2888 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl,
2889 TG3_GRC_LCLCTL_PWRSW_DELAY);
2890
2891 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0;
2892 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl,
2893 TG3_GRC_LCLCTL_PWRSW_DELAY);
2894 } else {
2895 u32 no_gpio2;
2896 u32 grc_local_ctrl = 0;
2897
2898 /* Workaround to prevent overdrawing Amps. */
4153577a 2899 if (tg3_asic_rev(tp) == ASIC_REV_5714) {
520b2756
MC		 2900 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
2901 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2902 grc_local_ctrl,
2903 TG3_GRC_LCLCTL_PWRSW_DELAY);
2904 }
2905
2906 /* On 5753 and variants, GPIO2 cannot be used. */
2907 no_gpio2 = tp->nic_sram_data_cfg &
2908 NIC_SRAM_DATA_CFG_NO_GPIO2;
2909
2910 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
2911 GRC_LCLCTRL_GPIO_OE1 |
2912 GRC_LCLCTRL_GPIO_OE2 |
2913 GRC_LCLCTRL_GPIO_OUTPUT1 |
2914 GRC_LCLCTRL_GPIO_OUTPUT2;
2915 if (no_gpio2) {
2916 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
2917 GRC_LCLCTRL_GPIO_OUTPUT2);
2918 }
2919 tw32_wait_f(GRC_LOCAL_CTRL,
2920 tp->grc_local_ctrl | grc_local_ctrl,
2921 TG3_GRC_LCLCTL_PWRSW_DELAY);
2922
2923 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
2924
2925 tw32_wait_f(GRC_LOCAL_CTRL,
2926 tp->grc_local_ctrl | grc_local_ctrl,
2927 TG3_GRC_LCLCTL_PWRSW_DELAY);
2928
2929 if (!no_gpio2) {
2930 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
2931 tw32_wait_f(GRC_LOCAL_CTRL,
2932 tp->grc_local_ctrl | grc_local_ctrl,
2933 TG3_GRC_LCLCTL_PWRSW_DELAY);
2934 }
2935 }
3a1e19d3
MC		 2936}
2937
cd0d7228 2938static void tg3_frob_aux_power_5717(struct tg3 *tp, bool wol_enable)
3a1e19d3
MC		 2939{
2940 u32 msg = 0;
2941
2942 /* Serialize power state transitions */
2943 if (tg3_ape_lock(tp, TG3_APE_LOCK_GPIO))
2944 return;
2945
cd0d7228 2946 if (tg3_flag(tp, ENABLE_ASF) || tg3_flag(tp, ENABLE_APE) || wol_enable)
3a1e19d3
MC		 2947 msg = TG3_GPIO_MSG_NEED_VAUX;
2948
2949 msg = tg3_set_function_status(tp, msg);
2950
2951 if (msg & TG3_GPIO_MSG_ALL_DRVR_PRES_MASK)
2952 goto done;
6f5c8f83 2953
3a1e19d3
MC		 2954 if (msg & TG3_GPIO_MSG_ALL_NEED_VAUX_MASK)
2955 tg3_pwrsrc_switch_to_vaux(tp);
2956 else
2957 tg3_pwrsrc_die_with_vmain(tp);
2958
2959done:
6f5c8f83 2960 tg3_ape_unlock(tp, TG3_APE_LOCK_GPIO);
520b2756
MC		 2961}
2962
cd0d7228 2963static void tg3_frob_aux_power(struct tg3 *tp, bool include_wol)
1da177e4 2964{
683644b7 2965 bool need_vaux = false;
1da177e4 2966
334355aa 2967 /* The GPIOs do something completely different on 57765. */
55086ad9 2968 if (!tg3_flag(tp, IS_NIC) || tg3_flag(tp, 57765_CLASS))
1da177e4
LT		 2969 return;
2970
4153577a
JP		 2971 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
2972 tg3_asic_rev(tp) == ASIC_REV_5719 ||
2973 tg3_asic_rev(tp) == ASIC_REV_5720) {
cd0d7228
MC		 2974 tg3_frob_aux_power_5717(tp, include_wol ?
2975 tg3_flag(tp, WOL_ENABLE) != 0 : 0);
3a1e19d3
MC		 2976 return;
2977 }
2978
2979 if (tp->pdev_peer && tp->pdev_peer != tp->pdev) {
8c2dc7e1
MC		 2980 struct net_device *dev_peer;
2981
2982 dev_peer = pci_get_drvdata(tp->pdev_peer);
683644b7 2983
bc1c7567 2984 /* remove_one() may have been run on the peer. */
683644b7
MC		 2985 if (dev_peer) {
2986 struct tg3 *tp_peer = netdev_priv(dev_peer);
2987
63c3a66f 2988 if (tg3_flag(tp_peer, INIT_COMPLETE))
683644b7
MC		 2989 return;
2990
cd0d7228 2991 if ((include_wol && tg3_flag(tp_peer, WOL_ENABLE)) ||
63c3a66f 2992 tg3_flag(tp_peer, ENABLE_ASF))
683644b7
MC		 2993 need_vaux = true;
2994 }
1da177e4
LT		 2995 }
2996
cd0d7228
MC		 2997 if ((include_wol && tg3_flag(tp, WOL_ENABLE)) ||
2998 tg3_flag(tp, ENABLE_ASF))
683644b7
MC		 2999 need_vaux = true;
3000
520b2756
MC		 3001 if (need_vaux)
3002 tg3_pwrsrc_switch_to_vaux(tp);
3003 else
3004 tg3_pwrsrc_die_with_vmain(tp);
1da177e4
LT		 3005}
3006
e8f3f6ca
MC		 3007static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
3008{
3009 if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
3010 return 1;
79eb6904 3011 else if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411) {
e8f3f6ca
MC		 3012 if (speed != SPEED_10)
3013 return 1;
3014 } else if (speed == SPEED_10)
3015 return 1;
3016
3017 return 0;
3018}
3019
44f3b503
NS		 3020static bool tg3_phy_power_bug(struct tg3 *tp)
3021{
3022 switch (tg3_asic_rev(tp)) {
3023 case ASIC_REV_5700:
3024 case ASIC_REV_5704:
3025 return true;
3026 case ASIC_REV_5780:
3027 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
3028 return true;
3029 return false;
3030 case ASIC_REV_5717:
3031 if (!tp->pci_fn)
3032 return true;
3033 return false;
3034 case ASIC_REV_5719:
3035 case ASIC_REV_5720:
3036 if ((tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
3037 !tp->pci_fn)
3038 return true;
3039 return false;
3040 }
3041
3042 return false;
3043}
3044
989038e2
NS		 3045static bool tg3_phy_led_bug(struct tg3 *tp)
3046{
3047 switch (tg3_asic_rev(tp)) {
3048 case ASIC_REV_5719:
300cf9b9 3049 case ASIC_REV_5720:
989038e2
NS		 3050 if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
3051 !tp->pci_fn)
3052 return true;
3053 return false;
3054 }
3055
3056 return false;
3057}
3058
0a459aac 3059static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power)
15c3b696 3060{
ce057f01
MC		 3061 u32 val;
3062
942d1af0
NS		 3063 if (tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN)
3064 return;
3065
f07e9af3 3066 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
4153577a 3067 if (tg3_asic_rev(tp) == ASIC_REV_5704) {
5129724a
MC		 3068 u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
3069 u32 serdes_cfg = tr32(MAC_SERDES_CFG);
3070
3071 sg_dig_ctrl |=
3072 SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
3073 tw32(SG_DIG_CTRL, sg_dig_ctrl);
3074 tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
3075 }
3f7045c1 3076 return;
5129724a 3077 }
3f7045c1 3078
4153577a 3079 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
60189ddf
MC		 3080 tg3_bmcr_reset(tp);
3081 val = tr32(GRC_MISC_CFG);
3082 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
3083 udelay(40);
3084 return;
f07e9af3 3085 } else if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
0e5f784c
MC		 3086 u32 phytest;
3087 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
3088 u32 phy;
3089
3090 tg3_writephy(tp, MII_ADVERTISE, 0);
3091 tg3_writephy(tp, MII_BMCR,
3092 BMCR_ANENABLE | BMCR_ANRESTART);
3093
3094 tg3_writephy(tp, MII_TG3_FET_TEST,
3095 phytest | MII_TG3_FET_SHADOW_EN);
3096 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXMODE4, &phy)) {
3097 phy |= MII_TG3_FET_SHDW_AUXMODE4_SBPD;
3098 tg3_writephy(tp,
3099 MII_TG3_FET_SHDW_AUXMODE4,
3100 phy);
3101 }
3102 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
3103 }
3104 return;
0a459aac 3105 } else if (do_low_power) {
989038e2
NS		 3106 if (!tg3_phy_led_bug(tp))
3107 tg3_writephy(tp, MII_TG3_EXT_CTRL,
3108 MII_TG3_EXT_CTRL_FORCE_LED_OFF);
0a459aac 3109
b4bd2929
MC		 3110 val = MII_TG3_AUXCTL_PCTL_100TX_LPWR |
3111 MII_TG3_AUXCTL_PCTL_SPR_ISOLATE |
3112 MII_TG3_AUXCTL_PCTL_VREG_11V;
3113 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_PWRCTL, val);
715116a1 3114 }
3f7045c1 3115
15c3b696
MC		 3116 /* The PHY should not be powered down on some chips because
3117 * of bugs.
3118 */
44f3b503 3119 if (tg3_phy_power_bug(tp))
15c3b696 3120 return;
ce057f01 3121
4153577a
JP		 3122 if (tg3_chip_rev(tp) == CHIPREV_5784_AX ||
3123 tg3_chip_rev(tp) == CHIPREV_5761_AX) {
ce057f01
MC		 3124 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
3125 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
3126 val |= CPMU_LSPD_1000MB_MACCLK_12_5;
3127 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
3128 }
3129
15c3b696
MC		 3130 tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
3131}
3132
ffbcfed4
MC		 3133/* tp->lock is held. */
3134static int tg3_nvram_lock(struct tg3 *tp)
3135{
63c3a66f 3136 if (tg3_flag(tp, NVRAM)) {
ffbcfed4
MC		 3137 int i;
3138
3139 if (tp->nvram_lock_cnt == 0) {
3140 tw32(NVRAM_SWARB, SWARB_REQ_SET1);
3141 for (i = 0; i < 8000; i++) {
3142 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
3143 break;
3144 udelay(20);
3145 }
3146 if (i == 8000) {
3147 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
3148 return -ENODEV;
3149 }
3150 }
3151 tp->nvram_lock_cnt++;
3152 }
3153 return 0;
3154}
3155
3156/* tp->lock is held. */
3157static void tg3_nvram_unlock(struct tg3 *tp)
3158{
63c3a66f 3159 if (tg3_flag(tp, NVRAM)) {
ffbcfed4
MC		 3160 if (tp->nvram_lock_cnt > 0)
3161 tp->nvram_lock_cnt--;
3162 if (tp->nvram_lock_cnt == 0)
3163 tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
3164 }
3165}
3166
3167/* tp->lock is held. */
3168static void tg3_enable_nvram_access(struct tg3 *tp)
3169{
63c3a66f 3170 if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM)) {
ffbcfed4
MC		 3171 u32 nvaccess = tr32(NVRAM_ACCESS);
3172
3173 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
3174 }
3175}
3176
3177/* tp->lock is held. */
3178static void tg3_disable_nvram_access(struct tg3 *tp)
3179{
63c3a66f 3180 if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM)) {
ffbcfed4
MC		 3181 u32 nvaccess = tr32(NVRAM_ACCESS);
3182
3183 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
3184 }
3185}
3186
3187static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
3188 u32 offset, u32 *val)
3189{
3190 u32 tmp;
3191 int i;
3192
3193 if (offset > EEPROM_ADDR_ADDR_MASK || (offset % 4) != 0)
3194 return -EINVAL;
3195
3196 tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
3197 EEPROM_ADDR_DEVID_MASK |
3198 EEPROM_ADDR_READ);
3199 tw32(GRC_EEPROM_ADDR,
3200 tmp |
3201 (0 << EEPROM_ADDR_DEVID_SHIFT) |
3202 ((offset << EEPROM_ADDR_ADDR_SHIFT) &
3203 EEPROM_ADDR_ADDR_MASK) |
3204 EEPROM_ADDR_READ | EEPROM_ADDR_START);
3205
3206 for (i = 0; i < 1000; i++) {
3207 tmp = tr32(GRC_EEPROM_ADDR);
3208
3209 if (tmp & EEPROM_ADDR_COMPLETE)
3210 break;
3211 msleep(1);
3212 }
3213 if (!(tmp & EEPROM_ADDR_COMPLETE))
3214 return -EBUSY;
3215
62cedd11
MC		 3216 tmp = tr32(GRC_EEPROM_DATA);
3217
3218 /*
3219 * The data will always be opposite the native endian
3220 * format. Perform a blind byteswap to compensate.
3221 */
3222 *val = swab32(tmp);
3223
ffbcfed4
MC		 3224 return 0;
3225}
3226
66c965f5 3227#define NVRAM_CMD_TIMEOUT 5000
ffbcfed4
MC		 3228
3229static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
3230{
3231 int i;
3232
3233 tw32(NVRAM_CMD, nvram_cmd);
3234 for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
66c965f5 3235 usleep_range(10, 40);
ffbcfed4
MC		 3236 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
3237 udelay(10);
3238 break;
3239 }
3240 }
3241
3242 if (i == NVRAM_CMD_TIMEOUT)
3243 return -EBUSY;
3244
3245 return 0;
3246}
3247
3248static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
3249{
63c3a66f
JP		 3250 if (tg3_flag(tp, NVRAM) &&
3251 tg3_flag(tp, NVRAM_BUFFERED) &&
3252 tg3_flag(tp, FLASH) &&
3253 !tg3_flag(tp, NO_NVRAM_ADDR_TRANS) &&
ffbcfed4
MC		 3254 (tp->nvram_jedecnum == JEDEC_ATMEL))
3255
3256 addr = ((addr / tp->nvram_pagesize) <<
3257 ATMEL_AT45DB0X1B_PAGE_POS) +
3258 (addr % tp->nvram_pagesize);
3259
3260 return addr;
3261}
3262
3263static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
3264{
63c3a66f
JP		 3265 if (tg3_flag(tp, NVRAM) &&
3266 tg3_flag(tp, NVRAM_BUFFERED) &&
3267 tg3_flag(tp, FLASH) &&
3268 !tg3_flag(tp, NO_NVRAM_ADDR_TRANS) &&
ffbcfed4
MC		 3269 (tp->nvram_jedecnum == JEDEC_ATMEL))
3270
3271 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
3272 tp->nvram_pagesize) +
3273 (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
3274
3275 return addr;
3276}
3277
e4f34110
MC		 3278/* NOTE: Data read in from NVRAM is byteswapped according to
3279 * the byteswapping settings for all other register accesses.
3280 * tg3 devices are BE devices, so on a BE machine, the data
3281 * returned will be exactly as it is seen in NVRAM. On a LE
3282 * machine, the 32-bit value will be byteswapped.
3283 */
ffbcfed4
MC		 3284static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
3285{
3286 int ret;
3287
63c3a66f 3288 if (!tg3_flag(tp, NVRAM))
ffbcfed4
MC		 3289 return tg3_nvram_read_using_eeprom(tp, offset, val);
3290
3291 offset = tg3_nvram_phys_addr(tp, offset);
3292
3293 if (offset > NVRAM_ADDR_MSK)
3294 return -EINVAL;
3295
3296 ret = tg3_nvram_lock(tp);
3297 if (ret)
3298 return ret;
3299
3300 tg3_enable_nvram_access(tp);
3301
3302 tw32(NVRAM_ADDR, offset);
3303 ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
3304 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
3305
3306 if (ret == 0)
e4f34110 3307 *val = tr32(NVRAM_RDDATA);
ffbcfed4
MC		 3308
3309 tg3_disable_nvram_access(tp);
3310
3311 tg3_nvram_unlock(tp);
3312
3313 return ret;
3314}
3315
a9dc529d
MC		 3316/* Ensures NVRAM data is in bytestream format. */
3317static int tg3_nvram_read_be32(struct tg3 *tp, u32 offset, __be32 *val)
ffbcfed4
MC		 3318{
3319 u32 v;
a9dc529d 3320 int res = tg3_nvram_read(tp, offset, &v);
ffbcfed4 3321 if (!res)
a9dc529d 3322 *val = cpu_to_be32(v);
ffbcfed4
MC		 3323 return res;
3324}
3325
dbe9b92a
MC		 3326static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
3327 u32 offset, u32 len, u8 *buf)
3328{
3329 int i, j, rc = 0;
3330 u32 val;
3331
3332 for (i = 0; i < len; i += 4) {
3333 u32 addr;
3334 __be32 data;
3335
3336 addr = offset + i;
3337
3338 memcpy(&data, buf + i, 4);
3339
3340 /*
3341 * The SEEPROM interface expects the data to always be opposite
3342 * the native endian format. We accomplish this by reversing
3343 * all the operations that would have been performed on the
3344 * data from a call to tg3_nvram_read_be32().
3345 */
3346 tw32(GRC_EEPROM_DATA, swab32(be32_to_cpu(data)));
3347
3348 val = tr32(GRC_EEPROM_ADDR);
3349 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
3350
3351 val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
3352 EEPROM_ADDR_READ);
3353 tw32(GRC_EEPROM_ADDR, val |
3354 (0 << EEPROM_ADDR_DEVID_SHIFT) |
3355 (addr & EEPROM_ADDR_ADDR_MASK) |
3356 EEPROM_ADDR_START |
3357 EEPROM_ADDR_WRITE);
3358
3359 for (j = 0; j < 1000; j++) {
3360 val = tr32(GRC_EEPROM_ADDR);
3361
3362 if (val & EEPROM_ADDR_COMPLETE)
3363 break;
3364 msleep(1);
3365 }
3366 if (!(val & EEPROM_ADDR_COMPLETE)) {
3367 rc = -EBUSY;
3368 break;
3369 }
3370 }
3371
3372 return rc;
3373}
3374
3375/* offset and length are dword aligned */
3376static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
3377 u8 *buf)
3378{
3379 int ret = 0;
3380 u32 pagesize = tp->nvram_pagesize;
3381 u32 pagemask = pagesize - 1;
3382 u32 nvram_cmd;
3383 u8 *tmp;
3384
3385 tmp = kmalloc(pagesize, GFP_KERNEL);
3386 if (tmp == NULL)
3387 return -ENOMEM;
3388
3389 while (len) {
3390 int j;
3391 u32 phy_addr, page_off, size;
3392
3393 phy_addr = offset & ~pagemask;
3394
3395 for (j = 0; j < pagesize; j += 4) {
3396 ret = tg3_nvram_read_be32(tp, phy_addr + j,
3397 (__be32 *) (tmp + j));
3398 if (ret)
3399 break;
3400 }
3401 if (ret)
3402 break;
3403
3404 page_off = offset & pagemask;
3405 size = pagesize;
3406 if (len < size)
3407 size = len;
3408
3409 len -= size;
3410
3411 memcpy(tmp + page_off, buf, size);
3412
3413 offset = offset + (pagesize - page_off);
3414
3415 tg3_enable_nvram_access(tp);
3416
3417 /*
3418 * Before we can erase the flash page, we need
3419 * to issue a special "write enable" command.
3420 */
3421 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
3422
3423 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
3424 break;
3425
3426 /* Erase the target page */
3427 tw32(NVRAM_ADDR, phy_addr);
3428
3429 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
3430 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
3431
3432 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
3433 break;
3434
3435 /* Issue another write enable to start the write. */
3436 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
3437
3438 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
3439 break;
3440
3441 for (j = 0; j < pagesize; j += 4) {
3442 __be32 data;
3443
3444 data = *((__be32 *) (tmp + j));
3445
3446 tw32(NVRAM_WRDATA, be32_to_cpu(data));
3447
3448 tw32(NVRAM_ADDR, phy_addr + j);
3449
3450 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
3451 NVRAM_CMD_WR;
3452
3453 if (j == 0)
3454 nvram_cmd |= NVRAM_CMD_FIRST;
3455 else if (j == (pagesize - 4))
3456 nvram_cmd |= NVRAM_CMD_LAST;
3457
3458 ret = tg3_nvram_exec_cmd(tp, nvram_cmd);
3459 if (ret)
3460 break;
3461 }
3462 if (ret)
3463 break;
3464 }
3465
3466 nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
3467 tg3_nvram_exec_cmd(tp, nvram_cmd);
3468
3469 kfree(tmp);
3470
3471 return ret;
3472}
3473
3474/* offset and length are dword aligned */
3475static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
3476 u8 *buf)
3477{
3478 int i, ret = 0;
3479
3480 for (i = 0; i < len; i += 4, offset += 4) {
3481 u32 page_off, phy_addr, nvram_cmd;
3482 __be32 data;
3483
3484 memcpy(&data, buf + i, 4);
3485 tw32(NVRAM_WRDATA, be32_to_cpu(data));
3486
3487 page_off = offset % tp->nvram_pagesize;
3488
3489 phy_addr = tg3_nvram_phys_addr(tp, offset);
3490
dbe9b92a
MC		 3491 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
3492
3493 if (page_off == 0 || i == 0)
3494 nvram_cmd |= NVRAM_CMD_FIRST;
3495 if (page_off == (tp->nvram_pagesize - 4))
3496 nvram_cmd |= NVRAM_CMD_LAST;
3497
3498 if (i == (len - 4))
3499 nvram_cmd |= NVRAM_CMD_LAST;
3500
42278224
MC		 3501 if ((nvram_cmd & NVRAM_CMD_FIRST) ||
3502 !tg3_flag(tp, FLASH) ||
3503 !tg3_flag(tp, 57765_PLUS))
3504 tw32(NVRAM_ADDR, phy_addr);
3505
4153577a 3506 if (tg3_asic_rev(tp) != ASIC_REV_5752 &&
dbe9b92a
MC		 3507 !tg3_flag(tp, 5755_PLUS) &&
3508 (tp->nvram_jedecnum == JEDEC_ST) &&
3509 (nvram_cmd & NVRAM_CMD_FIRST)) {
3510 u32 cmd;
3511
3512 cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
3513 ret = tg3_nvram_exec_cmd(tp, cmd);
3514 if (ret)
3515 break;
3516 }
3517 if (!tg3_flag(tp, FLASH)) {
3518 /* We always do complete word writes to eeprom. */
3519 nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
3520 }
3521
3522 ret = tg3_nvram_exec_cmd(tp, nvram_cmd);
3523 if (ret)
3524 break;
3525 }
3526 return ret;
3527}
3528
3529/* offset and length are dword aligned */
3530static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
3531{
3532 int ret;
3533
3534 if (tg3_flag(tp, EEPROM_WRITE_PROT)) {
3535 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
3536 ~GRC_LCLCTRL_GPIO_OUTPUT1);
3537 udelay(40);
3538 }
3539
3540 if (!tg3_flag(tp, NVRAM)) {
3541 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
3542 } else {
3543 u32 grc_mode;
3544
3545 ret = tg3_nvram_lock(tp);
3546 if (ret)
3547 return ret;
3548
3549 tg3_enable_nvram_access(tp);
3550 if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM))
3551 tw32(NVRAM_WRITE1, 0x406);
3552
3553 grc_mode = tr32(GRC_MODE);
3554 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
3555
3556 if (tg3_flag(tp, NVRAM_BUFFERED) || !tg3_flag(tp, FLASH)) {
3557 ret = tg3_nvram_write_block_buffered(tp, offset, len,
3558 buf);
3559 } else {
3560 ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
3561 buf);
3562 }
3563
3564 grc_mode = tr32(GRC_MODE);
3565 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
3566
3567 tg3_disable_nvram_access(tp);
3568 tg3_nvram_unlock(tp);
3569 }
3570
3571 if (tg3_flag(tp, EEPROM_WRITE_PROT)) {
3572 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
3573 udelay(40);
3574 }
3575
3576 return ret;
3577}
3578
997b4f13
MC		 3579#define RX_CPU_SCRATCH_BASE 0x30000
3580#define RX_CPU_SCRATCH_SIZE 0x04000
3581#define TX_CPU_SCRATCH_BASE 0x34000
3582#define TX_CPU_SCRATCH_SIZE 0x04000
3583
3584/* tp->lock is held. */
837c45bb 3585static int tg3_pause_cpu(struct tg3 *tp, u32 cpu_base)
997b4f13
MC		 3586{
3587 int i;
837c45bb 3588 const int iters = 10000;
997b4f13 3589
837c45bb
NS		 3590 for (i = 0; i < iters; i++) {
3591 tw32(cpu_base + CPU_STATE, 0xffffffff);
3592 tw32(cpu_base + CPU_MODE, CPU_MODE_HALT);
3593 if (tr32(cpu_base + CPU_MODE) & CPU_MODE_HALT)
3594 break;
6d446ec3
GS		 3595 if (pci_channel_offline(tp->pdev))
3596 return -EBUSY;
837c45bb
NS		 3597 }
3598
3599 return (i == iters) ? -EBUSY : 0;
3600}
3601
3602/* tp->lock is held. */
3603static int tg3_rxcpu_pause(struct tg3 *tp)
3604{
3605 int rc = tg3_pause_cpu(tp, RX_CPU_BASE);
3606
3607 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
3608 tw32_f(RX_CPU_BASE + CPU_MODE, CPU_MODE_HALT);
3609 udelay(10);
3610
3611 return rc;
3612}
3613
3614/* tp->lock is held. */
3615static int tg3_txcpu_pause(struct tg3 *tp)
3616{
3617 return tg3_pause_cpu(tp, TX_CPU_BASE);
3618}
3619
3620/* tp->lock is held. */
3621static void tg3_resume_cpu(struct tg3 *tp, u32 cpu_base)
3622{
3623 tw32(cpu_base + CPU_STATE, 0xffffffff);
3624 tw32_f(cpu_base + CPU_MODE, 0x00000000);
3625}
3626
3627/* tp->lock is held. */
3628static void tg3_rxcpu_resume(struct tg3 *tp)
3629{
3630 tg3_resume_cpu(tp, RX_CPU_BASE);
3631}
3632
3633/* tp->lock is held. */
3634static int tg3_halt_cpu(struct tg3 *tp, u32 cpu_base)
3635{
3636 int rc;
3637
3638 BUG_ON(cpu_base == TX_CPU_BASE && tg3_flag(tp, 5705_PLUS));
997b4f13 3639
4153577a 3640 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
997b4f13
MC		 3641 u32 val = tr32(GRC_VCPU_EXT_CTRL);
3642
3643 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
3644 return 0;
3645 }
837c45bb
NS		 3646 if (cpu_base == RX_CPU_BASE) {
3647 rc = tg3_rxcpu_pause(tp);
997b4f13 3648 } else {
7e6c63f0
HM		 3649 /*
3650 * There is only an Rx CPU for the 5750 derivative in the
3651 * BCM4785.
3652 */
3653 if (tg3_flag(tp, IS_SSB_CORE))
3654 return 0;
3655
837c45bb 3656 rc = tg3_txcpu_pause(tp);
997b4f13
MC		 3657 }
3658
837c45bb 3659 if (rc) {
997b4f13 3660 netdev_err(tp->dev, "%s timed out, %s CPU\n",
837c45bb 3661 __func__, cpu_base == RX_CPU_BASE ? "RX" : "TX");
997b4f13
MC		 3662 return -ENODEV;
3663 }
3664
3665 /* Clear firmware's nvram arbitration. */
3666 if (tg3_flag(tp, NVRAM))
3667 tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
3668 return 0;
3669}
3670
31f11a95
NS		 3671static int tg3_fw_data_len(struct tg3 *tp,
3672 const struct tg3_firmware_hdr *fw_hdr)
3673{
3674 int fw_len;
3675
3676 /* Non fragmented firmware have one firmware header followed by a
3677 * contiguous chunk of data to be written. The length field in that
3678 * header is not the length of data to be written but the complete
3679 * length of the bss. The data length is determined based on
3680 * tp->fw->size minus headers.
3681 *
3682 * Fragmented firmware have a main header followed by multiple
3683 * fragments. Each fragment is identical to non fragmented firmware
3684 * with a firmware header followed by a contiguous chunk of data. In
3685 * the main header, the length field is unused and set to 0xffffffff.
3686 * In each fragment header the length is the entire size of that
3687 * fragment i.e. fragment data + header length. Data length is
3688 * therefore length field in the header minus TG3_FW_HDR_LEN.
3689 */
3690 if (tp->fw_len == 0xffffffff)
3691 fw_len = be32_to_cpu(fw_hdr->len);
3692 else
3693 fw_len = tp->fw->size;
3694
3695 return (fw_len - TG3_FW_HDR_LEN) / sizeof(u32);
3696}
3697
997b4f13
MC		 3698/* tp->lock is held. */
3699static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base,
3700 u32 cpu_scratch_base, int cpu_scratch_size,
77997ea3 3701 const struct tg3_firmware_hdr *fw_hdr)
997b4f13 3702{
c4dab506 3703 int err, i;
997b4f13 3704 void (*write_op)(struct tg3 *, u32, u32);
31f11a95 3705 int total_len = tp->fw->size;
997b4f13
MC		 3706
3707 if (cpu_base == TX_CPU_BASE && tg3_flag(tp, 5705_PLUS)) {
3708 netdev_err(tp->dev,
3709 "%s: Trying to load TX cpu firmware which is 5705\n",
3710 __func__);
3711 return -EINVAL;
3712 }
3713
c4dab506 3714 if (tg3_flag(tp, 5705_PLUS) && tg3_asic_rev(tp) != ASIC_REV_57766)
997b4f13
MC		 3715 write_op = tg3_write_mem;
3716 else
3717 write_op = tg3_write_indirect_reg32;
3718
c4dab506
NS		 3719 if (tg3_asic_rev(tp) != ASIC_REV_57766) {
3720 /* It is possible that bootcode is still loading at this point.
3721 * Get the nvram lock first before halting the cpu.
3722 */
3723 int lock_err = tg3_nvram_lock(tp);
3724 err = tg3_halt_cpu(tp, cpu_base);
3725 if (!lock_err)
3726 tg3_nvram_unlock(tp);
3727 if (err)
3728 goto out;
997b4f13 3729
c4dab506
NS		 3730 for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
3731 write_op(tp, cpu_scratch_base + i, 0);
3732 tw32(cpu_base + CPU_STATE, 0xffffffff);
3733 tw32(cpu_base + CPU_MODE,
3734 tr32(cpu_base + CPU_MODE) | CPU_MODE_HALT);
3735 } else {
3736 /* Subtract additional main header for fragmented firmware and
3737 * advance to the first fragment
3738 */
3739 total_len -= TG3_FW_HDR_LEN;
3740 fw_hdr++;
3741 }
77997ea3 3742
31f11a95
NS		 3743 do {
3744 u32 *fw_data = (u32 *)(fw_hdr + 1);
3745 for (i = 0; i < tg3_fw_data_len(tp, fw_hdr); i++)
3746 write_op(tp, cpu_scratch_base +
3747 (be32_to_cpu(fw_hdr->base_addr) & 0xffff) +
3748 (i * sizeof(u32)),
3749 be32_to_cpu(fw_data[i]));
3750
3751 total_len -= be32_to_cpu(fw_hdr->len);
3752
3753 /* Advance to next fragment */
3754 fw_hdr = (struct tg3_firmware_hdr *)
3755 ((void *)fw_hdr + be32_to_cpu(fw_hdr->len));
3756 } while (total_len > 0);
997b4f13
MC		 3757
3758 err = 0;
3759
3760out:
3761 return err;
3762}
3763
f4bffb28
NS		 3764/* tp->lock is held. */
3765static int tg3_pause_cpu_and_set_pc(struct tg3 *tp, u32 cpu_base, u32 pc)
3766{
3767 int i;
3768 const int iters = 5;
3769
3770 tw32(cpu_base + CPU_STATE, 0xffffffff);
3771 tw32_f(cpu_base + CPU_PC, pc);
3772
3773 for (i = 0; i < iters; i++) {
3774 if (tr32(cpu_base + CPU_PC) == pc)
3775 break;
3776 tw32(cpu_base + CPU_STATE, 0xffffffff);
3777 tw32(cpu_base + CPU_MODE, CPU_MODE_HALT);
3778 tw32_f(cpu_base + CPU_PC, pc);
3779 udelay(1000);
3780 }
3781
3782 return (i == iters) ? -EBUSY : 0;
3783}
3784
997b4f13
MC		 3785/* tp->lock is held. */
3786static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
3787{
77997ea3 3788 const struct tg3_firmware_hdr *fw_hdr;
f4bffb28 3789 int err;
997b4f13 3790
77997ea3 3791 fw_hdr = (struct tg3_firmware_hdr *)tp->fw->data;
997b4f13
MC		 3792
3793 /* Firmware blob starts with version numbers, followed by
3794 start address and length. We are setting complete length.
3795 length = end_address_of_bss - start_address_of_text.
3796 Remainder is the blob to be loaded contiguously
3797 from start address. */
3798
997b4f13
MC		 3799 err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
3800 RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
77997ea3 3801 fw_hdr);
997b4f13
MC		 3802 if (err)
3803 return err;
3804
3805 err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
3806 TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
77997ea3 3807 fw_hdr);
997b4f13
MC		 3808 if (err)
3809 return err;
3810
3811 /* Now startup only the RX cpu. */
77997ea3
NS		 3812 err = tg3_pause_cpu_and_set_pc(tp, RX_CPU_BASE,
3813 be32_to_cpu(fw_hdr->base_addr));
f4bffb28 3814 if (err) {
997b4f13
MC		 3815 netdev_err(tp->dev, "%s fails to set RX CPU PC, is %08x "
3816 "should be %08x\n", __func__,
77997ea3
NS		 3817 tr32(RX_CPU_BASE + CPU_PC),
3818 be32_to_cpu(fw_hdr->base_addr));
997b4f13
MC		 3819 return -ENODEV;
3820 }
837c45bb
NS		 3821
3822 tg3_rxcpu_resume(tp);
997b4f13
MC		 3823
3824 return 0;
3825}
3826
c4dab506
NS		 3827static int tg3_validate_rxcpu_state(struct tg3 *tp)
3828{
3829 const int iters = 1000;
3830 int i;
3831 u32 val;
3832
3833 /* Wait for boot code to complete initialization and enter service
3834 * loop. It is then safe to download service patches
3835 */
3836 for (i = 0; i < iters; i++) {
3837 if (tr32(RX_CPU_HWBKPT) == TG3_SBROM_IN_SERVICE_LOOP)
3838 break;
3839
3840 udelay(10);
3841 }
3842
3843 if (i == iters) {
3844 netdev_err(tp->dev, "Boot code not ready for service patches\n");
3845 return -EBUSY;
3846 }
3847
3848 val = tg3_read_indirect_reg32(tp, TG3_57766_FW_HANDSHAKE);
3849 if (val & 0xff) {
3850 netdev_warn(tp->dev,
3851 "Other patches exist. Not downloading EEE patch\n");
3852 return -EEXIST;
3853 }
3854
3855 return 0;
3856}
3857
3858/* tp->lock is held. */
3859static void tg3_load_57766_firmware(struct tg3 *tp)
3860{
3861 struct tg3_firmware_hdr *fw_hdr;
3862
3863 if (!tg3_flag(tp, NO_NVRAM))
3864 return;
3865
3866 if (tg3_validate_rxcpu_state(tp))
3867 return;
3868
3869 if (!tp->fw)
3870 return;
3871
3872 /* This firmware blob has a different format than older firmware
3873 * releases as given below. The main difference is we have fragmented
3874 * data to be written to non-contiguous locations.
3875 *
3876 * In the beginning we have a firmware header identical to other
3877 * firmware which consists of version, base addr and length. The length
3878 * here is unused and set to 0xffffffff.
3879 *
3880 * This is followed by a series of firmware fragments which are
3881 * individually identical to previous firmware. i.e. they have the
3882 * firmware header and followed by data for that fragment. The version
3883 * field of the individual fragment header is unused.
3884 */
3885
3886 fw_hdr = (struct tg3_firmware_hdr *)tp->fw->data;
3887 if (be32_to_cpu(fw_hdr->base_addr) != TG3_57766_FW_BASE_ADDR)
3888 return;
3889
3890 if (tg3_rxcpu_pause(tp))
3891 return;
3892
3893 /* tg3_load_firmware_cpu() will always succeed for the 57766 */
3894 tg3_load_firmware_cpu(tp, 0, TG3_57766_FW_BASE_ADDR, 0, fw_hdr);
3895
3896 tg3_rxcpu_resume(tp);
3897}
3898
997b4f13
MC		 3899/* tp->lock is held. */
3900static int tg3_load_tso_firmware(struct tg3 *tp)
3901{
77997ea3 3902 const struct tg3_firmware_hdr *fw_hdr;
997b4f13 3903 unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
f4bffb28 3904 int err;
997b4f13 3905
1caf13eb 3906 if (!tg3_flag(tp, FW_TSO))
997b4f13
MC		 3907 return 0;
3908
77997ea3 3909 fw_hdr = (struct tg3_firmware_hdr *)tp->fw->data;
997b4f13
MC		 3910
3911 /* Firmware blob starts with version numbers, followed by
3912 start address and length. We are setting complete length.
3913 length = end_address_of_bss - start_address_of_text.
3914 Remainder is the blob to be loaded contiguously
3915 from start address. */
3916
997b4f13 3917 cpu_scratch_size = tp->fw_len;
997b4f13 3918
4153577a 3919 if (tg3_asic_rev(tp) == ASIC_REV_5705) {
997b4f13
MC		 3920 cpu_base = RX_CPU_BASE;
3921 cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
3922 } else {
3923 cpu_base = TX_CPU_BASE;
3924 cpu_scratch_base = TX_CPU_SCRATCH_BASE;
3925 cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
3926 }
3927
3928 err = tg3_load_firmware_cpu(tp, cpu_base,
3929 cpu_scratch_base, cpu_scratch_size,
77997ea3 3930 fw_hdr);
997b4f13
MC		 3931 if (err)
3932 return err;
3933
3934 /* Now startup the cpu. */
77997ea3
NS		 3935 err = tg3_pause_cpu_and_set_pc(tp, cpu_base,
3936 be32_to_cpu(fw_hdr->base_addr));
f4bffb28 3937 if (err) {
997b4f13
MC		 3938 netdev_err(tp->dev,
3939 "%s fails to set CPU PC, is %08x should be %08x\n",
77997ea3
NS		 3940 __func__, tr32(cpu_base + CPU_PC),
3941 be32_to_cpu(fw_hdr->base_addr));
997b4f13
MC		 3942 return -ENODEV;
3943 }
837c45bb
NS		 3944
3945 tg3_resume_cpu(tp, cpu_base);
997b4f13
MC		 3946 return 0;
3947}
3948
f022ae62
MC		 3949/* tp->lock is held. */
3950static void __tg3_set_one_mac_addr(struct tg3 *tp, u8 *mac_addr, int index)
3951{
3952 u32 addr_high, addr_low;
3953
3954 addr_high = ((mac_addr[0] << 8) | mac_addr[1]);
3955 addr_low = ((mac_addr[2] << 24) | (mac_addr[3] << 16) |
3956 (mac_addr[4] << 8) | mac_addr[5]);
3957
3958 if (index < 4) {
3959 tw32(MAC_ADDR_0_HIGH + (index * 8), addr_high);
3960 tw32(MAC_ADDR_0_LOW + (index * 8), addr_low);
3961 } else {
3962 index -= 4;
3963 tw32(MAC_EXTADDR_0_HIGH + (index * 8), addr_high);
3964 tw32(MAC_EXTADDR_0_LOW + (index * 8), addr_low);
3965 }
3966}
997b4f13 3967
3f007891 3968/* tp->lock is held. */
953c96e0 3969static void __tg3_set_mac_addr(struct tg3 *tp, bool skip_mac_1)
3f007891 3970{
f022ae62 3971 u32 addr_high;
3f007891
MC		 3972 int i;
3973
3f007891
MC		 3974 for (i = 0; i < 4; i++) {
3975 if (i == 1 && skip_mac_1)
3976 continue;
f022ae62 3977 __tg3_set_one_mac_addr(tp, tp->dev->dev_addr, i);
3f007891
MC		 3978 }
3979
4153577a
JP		 3980 if (tg3_asic_rev(tp) == ASIC_REV_5703 ||
3981 tg3_asic_rev(tp) == ASIC_REV_5704) {
f022ae62
MC		 3982 for (i = 4; i < 16; i++)
3983 __tg3_set_one_mac_addr(tp, tp->dev->dev_addr, i);
3f007891
MC		 3984 }
3985
3986 addr_high = (tp->dev->dev_addr[0] +
3987 tp->dev->dev_addr[1] +
3988 tp->dev->dev_addr[2] +
3989 tp->dev->dev_addr[3] +
3990 tp->dev->dev_addr[4] +
3991 tp->dev->dev_addr[5]) &
3992 TX_BACKOFF_SEED_MASK;
3993 tw32(MAC_TX_BACKOFF_SEED, addr_high);
3994}
3995
c866b7ea 3996static void tg3_enable_register_access(struct tg3 *tp)
1da177e4 3997{
c866b7ea
RW		 3998 /*
3999 * Make sure register accesses (indirect or otherwise) will function
4000 * correctly.
1da177e4
LT		 4001 */
4002 pci_write_config_dword(tp->pdev,
c866b7ea
RW		 4003 TG3PCI_MISC_HOST_CTRL, tp->misc_host_ctrl);
4004}
1da177e4 4005
c866b7ea
RW		 4006static int tg3_power_up(struct tg3 *tp)
4007{
bed9829f 4008 int err;
8c6bda1a 4009
bed9829f 4010 tg3_enable_register_access(tp);
1da177e4 4011
bed9829f
MC		 4012 err = pci_set_power_state(tp->pdev, PCI_D0);
4013 if (!err) {
4014 /* Switch out of Vaux if it is a NIC */
4015 tg3_pwrsrc_switch_to_vmain(tp);
4016 } else {
4017 netdev_err(tp->dev, "Transition to D0 failed\n");
4018 }
1da177e4 4019
bed9829f 4020 return err;
c866b7ea 4021}
1da177e4 4022
953c96e0 4023static int tg3_setup_phy(struct tg3 *, bool);
4b409522 4024
c866b7ea
RW		 4025static int tg3_power_down_prepare(struct tg3 *tp)
4026{
4027 u32 misc_host_ctrl;
4028 bool device_should_wake, do_low_power;
4029
4030 tg3_enable_register_access(tp);
5e7dfd0f
MC		 4031
4032 /* Restore the CLKREQ setting. */
0f49bfbd
JL		 4033 if (tg3_flag(tp, CLKREQ_BUG))
4034 pcie_capability_set_word(tp->pdev, PCI_EXP_LNKCTL,
4035 PCI_EXP_LNKCTL_CLKREQ_EN);
5e7dfd0f 4036
1da177e4
LT		 4037 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
4038 tw32(TG3PCI_MISC_HOST_CTRL,
4039 misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
4040
c866b7ea 4041 device_should_wake = device_may_wakeup(&tp->pdev->dev) &&
63c3a66f 4042 tg3_flag(tp, WOL_ENABLE);
05ac4cb7 4043
63c3a66f 4044 if (tg3_flag(tp, USE_PHYLIB)) {
0a459aac 4045 do_low_power = false;
f07e9af3 4046 if ((tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) &&
80096068 4047 !(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
b02fd9e3 4048 struct phy_device *phydev;
0a459aac 4049 u32 phyid, advertising;
b02fd9e3 4050
ead2402c 4051 phydev = tp->mdio_bus->phy_map[tp->phy_addr];
b02fd9e3 4052
80096068 4053 tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER;
b02fd9e3 4054
c6700ce2
MC		 4055 tp->link_config.speed = phydev->speed;
4056 tp->link_config.duplex = phydev->duplex;
4057 tp->link_config.autoneg = phydev->autoneg;
4058 tp->link_config.advertising = phydev->advertising;
b02fd9e3
MC		 4059
4060 advertising = ADVERTISED_TP |
4061 ADVERTISED_Pause |
4062 ADVERTISED_Autoneg |
4063 ADVERTISED_10baseT_Half;
4064
63c3a66f
JP		 4065 if (tg3_flag(tp, ENABLE_ASF) || device_should_wake) {
4066 if (tg3_flag(tp, WOL_SPEED_100MB))
b02fd9e3
MC		 4067 advertising |=
4068 ADVERTISED_100baseT_Half |
4069 ADVERTISED_100baseT_Full |
4070 ADVERTISED_10baseT_Full;
4071 else
4072 advertising |= ADVERTISED_10baseT_Full;
4073 }
4074
4075 phydev->advertising = advertising;
4076
4077 phy_start_aneg(phydev);
0a459aac
MC		 4078
4079 phyid = phydev->drv->phy_id & phydev->drv->phy_id_mask;
6a443a0f
MC		 4080 if (phyid != PHY_ID_BCMAC131) {
4081 phyid &= PHY_BCM_OUI_MASK;
4082 if (phyid == PHY_BCM_OUI_1 ||
4083 phyid == PHY_BCM_OUI_2 ||
4084 phyid == PHY_BCM_OUI_3)
0a459aac
MC		 4085 do_low_power = true;
4086 }
b02fd9e3 4087 }
dd477003 4088 } else {
2023276e 4089 do_low_power = true;
0a459aac 4090
c6700ce2 4091 if (!(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER))
80096068 4092 tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER;
1da177e4 4093
2855b9fe 4094 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
953c96e0 4095 tg3_setup_phy(tp, false);
1da177e4
LT		 4096 }
4097
4153577a 4098 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
b5d3772c
MC		 4099 u32 val;
4100
4101 val = tr32(GRC_VCPU_EXT_CTRL);
4102 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
63c3a66f 4103 } else if (!tg3_flag(tp, ENABLE_ASF)) {
6921d201
MC		 4104 int i;
4105 u32 val;
4106
4107 for (i = 0; i < 200; i++) {
4108 tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
4109 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
4110 break;
4111 msleep(1);
4112 }
4113 }
63c3a66f 4114 if (tg3_flag(tp, WOL_CAP))
a85feb8c
GZ		 4115 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
4116 WOL_DRV_STATE_SHUTDOWN |
4117 WOL_DRV_WOL |
4118 WOL_SET_MAGIC_PKT);
6921d201 4119
05ac4cb7 4120 if (device_should_wake) {
1da177e4
LT		 4121 u32 mac_mode;
4122
f07e9af3 4123 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
b4bd2929
MC		 4124 if (do_low_power &&
4125 !(tp->phy_flags & TG3_PHYFLG_IS_FET)) {
4126 tg3_phy_auxctl_write(tp,
4127 MII_TG3_AUXCTL_SHDWSEL_PWRCTL,
4128 MII_TG3_AUXCTL_PCTL_WOL_EN |
4129 MII_TG3_AUXCTL_PCTL_100TX_LPWR |
4130 MII_TG3_AUXCTL_PCTL_CL_AB_TXDAC);
dd477003
MC		 4131 udelay(40);
4132 }
1da177e4 4133
f07e9af3 4134 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
3f7045c1 4135 mac_mode = MAC_MODE_PORT_MODE_GMII;
942d1af0
NS		 4136 else if (tp->phy_flags &
4137 TG3_PHYFLG_KEEP_LINK_ON_PWRDN) {
4138 if (tp->link_config.active_speed == SPEED_1000)
4139 mac_mode = MAC_MODE_PORT_MODE_GMII;
4140 else
4141 mac_mode = MAC_MODE_PORT_MODE_MII;
4142 } else
3f7045c1 4143 mac_mode = MAC_MODE_PORT_MODE_MII;
1da177e4 4144
e8f3f6ca 4145 mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
4153577a 4146 if (tg3_asic_rev(tp) == ASIC_REV_5700) {
63c3a66f 4147 u32 speed = tg3_flag(tp, WOL_SPEED_100MB) ?
e8f3f6ca
MC		 4148 SPEED_100 : SPEED_10;
4149 if (tg3_5700_link_polarity(tp, speed))
4150 mac_mode |= MAC_MODE_LINK_POLARITY;
4151 else
4152 mac_mode &= ~MAC_MODE_LINK_POLARITY;
4153 }
1da177e4
LT		 4154 } else {
4155 mac_mode = MAC_MODE_PORT_MODE_TBI;
4156 }
4157
63c3a66f 4158 if (!tg3_flag(tp, 5750_PLUS))
1da177e4
LT		 4159 tw32(MAC_LED_CTRL, tp->led_ctrl);
4160
05ac4cb7 4161 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
63c3a66f
JP		 4162 if ((tg3_flag(tp, 5705_PLUS) && !tg3_flag(tp, 5780_CLASS)) &&
4163 (tg3_flag(tp, ENABLE_ASF) || tg3_flag(tp, ENABLE_APE)))
05ac4cb7 4164 mac_mode |= MAC_MODE_KEEP_FRAME_IN_WOL;
1da177e4 4165
63c3a66f 4166 if (tg3_flag(tp, ENABLE_APE))
d2394e6b
MC		 4167 mac_mode |= MAC_MODE_APE_TX_EN |
4168 MAC_MODE_APE_RX_EN |
4169 MAC_MODE_TDE_ENABLE;
3bda1258 4170
1da177e4
LT		 4171 tw32_f(MAC_MODE, mac_mode);
4172 udelay(100);
4173
4174 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
4175 udelay(10);
4176 }
4177
63c3a66f 4178 if (!tg3_flag(tp, WOL_SPEED_100MB) &&
4153577a
JP		 4179 (tg3_asic_rev(tp) == ASIC_REV_5700 ||
4180 tg3_asic_rev(tp) == ASIC_REV_5701)) {
1da177e4
LT		 4181 u32 base_val;
4182
4183 base_val = tp->pci_clock_ctrl;
4184 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
4185 CLOCK_CTRL_TXCLK_DISABLE);
4186
b401e9e2
MC		 4187 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
4188 CLOCK_CTRL_PWRDOWN_PLL133, 40);
63c3a66f
JP		 4189 } else if (tg3_flag(tp, 5780_CLASS) ||
4190 tg3_flag(tp, CPMU_PRESENT) ||
4153577a 4191 tg3_asic_rev(tp) == ASIC_REV_5906) {
4cf78e4f 4192 /* do nothing */
63c3a66f 4193 } else if (!(tg3_flag(tp, 5750_PLUS) && tg3_flag(tp, ENABLE_ASF))) {
1da177e4
LT		 4194 u32 newbits1, newbits2;
4195
4153577a
JP		 4196 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
4197 tg3_asic_rev(tp) == ASIC_REV_5701) {
1da177e4
LT		 4198 newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
4199 CLOCK_CTRL_TXCLK_DISABLE |
4200 CLOCK_CTRL_ALTCLK);
4201 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
63c3a66f 4202 } else if (tg3_flag(tp, 5705_PLUS)) {
1da177e4
LT		 4203 newbits1 = CLOCK_CTRL_625_CORE;
4204 newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
4205 } else {
4206 newbits1 = CLOCK_CTRL_ALTCLK;
4207 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
4208 }
4209
b401e9e2
MC		 4210 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
4211 40);
1da177e4 4212
b401e9e2
MC		 4213 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
4214 40);
1da177e4 4215
63c3a66f 4216 if (!tg3_flag(tp, 5705_PLUS)) {
1da177e4
LT		 4217 u32 newbits3;
4218
4153577a
JP		 4219 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
4220 tg3_asic_rev(tp) == ASIC_REV_5701) {
1da177e4
LT		 4221 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
4222 CLOCK_CTRL_TXCLK_DISABLE |
4223 CLOCK_CTRL_44MHZ_CORE);
4224 } else {
4225 newbits3 = CLOCK_CTRL_44MHZ_CORE;
4226 }
4227
b401e9e2
MC		 4228 tw32_wait_f(TG3PCI_CLOCK_CTRL,
4229 tp->pci_clock_ctrl | newbits3, 40);
1da177e4
LT		 4230 }
4231 }
4232
63c3a66f 4233 if (!(device_should_wake) && !tg3_flag(tp, ENABLE_ASF))
0a459aac 4234 tg3_power_down_phy(tp, do_low_power);
6921d201 4235
cd0d7228 4236 tg3_frob_aux_power(tp, true);
1da177e4
LT		 4237
4238 /* Workaround for unstable PLL clock */
7e6c63f0 4239 if ((!tg3_flag(tp, IS_SSB_CORE)) &&
4153577a
JP		 4240 ((tg3_chip_rev(tp) == CHIPREV_5750_AX) ||
4241 (tg3_chip_rev(tp) == CHIPREV_5750_BX))) {
1da177e4
LT		 4242 u32 val = tr32(0x7d00);
4243
4244 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
4245 tw32(0x7d00, val);
63c3a66f 4246 if (!tg3_flag(tp, ENABLE_ASF)) {
ec41c7df
MC		 4247 int err;
4248
4249 err = tg3_nvram_lock(tp);
1da177e4 4250 tg3_halt_cpu(tp, RX_CPU_BASE);
ec41c7df
MC		 4251 if (!err)
4252 tg3_nvram_unlock(tp);
6921d201 4253 }
1da177e4
LT		 4254 }
4255
bbadf503
MC		 4256 tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
4257
2e460fc0
NS		 4258 tg3_ape_driver_state_change(tp, RESET_KIND_SHUTDOWN);
4259
c866b7ea
RW		 4260 return 0;
4261}
12dac075 4262
c866b7ea
RW		 4263static void tg3_power_down(struct tg3 *tp)
4264{
63c3a66f 4265 pci_wake_from_d3(tp->pdev, tg3_flag(tp, WOL_ENABLE));
c866b7ea 4266 pci_set_power_state(tp->pdev, PCI_D3hot);
1da177e4
LT		 4267}
4268
1da177e4
LT		 4269static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
4270{
4271 switch (val & MII_TG3_AUX_STAT_SPDMASK) {
4272 case MII_TG3_AUX_STAT_10HALF:
4273 *speed = SPEED_10;
4274 *duplex = DUPLEX_HALF;
4275 break;
4276
4277 case MII_TG3_AUX_STAT_10FULL:
4278 *speed = SPEED_10;
4279 *duplex = DUPLEX_FULL;
4280 break;
4281
4282 case MII_TG3_AUX_STAT_100HALF:
4283 *speed = SPEED_100;
4284 *duplex = DUPLEX_HALF;
4285 break;
4286
4287 case MII_TG3_AUX_STAT_100FULL:
4288 *speed = SPEED_100;
4289 *duplex = DUPLEX_FULL;
4290 break;
4291
4292 case MII_TG3_AUX_STAT_1000HALF:
4293 *speed = SPEED_1000;
4294 *duplex = DUPLEX_HALF;
4295 break;
4296
4297 case MII_TG3_AUX_STAT_1000FULL:
4298 *speed = SPEED_1000;
4299 *duplex = DUPLEX_FULL;
4300 break;
4301
4302 default:
f07e9af3 4303 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
715116a1
MC		 4304 *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
4305 SPEED_10;
4306 *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
4307 DUPLEX_HALF;
4308 break;
4309 }
e740522e
MC		 4310 *speed = SPEED_UNKNOWN;
4311 *duplex = DUPLEX_UNKNOWN;
1da177e4 4312 break;
855e1111 4313 }
1da177e4
LT		 4314}
4315
42b64a45 4316static int tg3_phy_autoneg_cfg(struct tg3 *tp, u32 advertise, u32 flowctrl)
1da177e4 4317{
42b64a45
MC		 4318 int err = 0;
4319 u32 val, new_adv;
1da177e4 4320
42b64a45 4321 new_adv = ADVERTISE_CSMA;
202ff1c2 4322 new_adv |= ethtool_adv_to_mii_adv_t(advertise) & ADVERTISE_ALL;
f88788f0 4323 new_adv |= mii_advertise_flowctrl(flowctrl);
1da177e4 4324
42b64a45
MC		 4325 err = tg3_writephy(tp, MII_ADVERTISE, new_adv);
4326 if (err)
4327 goto done;
ba4d07a8 4328
4f272096
MC		 4329 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
4330 new_adv = ethtool_adv_to_mii_ctrl1000_t(advertise);
ba4d07a8 4331
4153577a
JP		 4332 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0 ||
4333 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B0)
4f272096 4334 new_adv |= CTL1000_AS_MASTER | CTL1000_ENABLE_MASTER;
ba4d07a8 4335
4f272096
MC		 4336 err = tg3_writephy(tp, MII_CTRL1000, new_adv);
4337 if (err)
4338 goto done;
4339 }
1da177e4 4340
42b64a45
MC		 4341 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP))
4342 goto done;
52b02d04 4343
42b64a45
MC		 4344 tw32(TG3_CPMU_EEE_MODE,
4345 tr32(TG3_CPMU_EEE_MODE) & ~TG3_CPMU_EEEMD_LPI_ENABLE);
52b02d04 4346
daf3ec68 4347 err = tg3_phy_toggle_auxctl_smdsp(tp, true);
42b64a45
MC		 4348 if (!err) {
4349 u32 err2;
52b02d04 4350
b715ce94
MC		 4351 val = 0;
4352 /* Advertise 100-BaseTX EEE ability */
4353 if (advertise & ADVERTISED_100baseT_Full)
4354 val |= MDIO_AN_EEE_ADV_100TX;
4355 /* Advertise 1000-BaseT EEE ability */
4356 if (advertise & ADVERTISED_1000baseT_Full)
4357 val |= MDIO_AN_EEE_ADV_1000T;
9e2ecbeb
NS		 4358
4359 if (!tp->eee.eee_enabled) {
4360 val = 0;
4361 tp->eee.advertised = 0;
4362 } else {
4363 tp->eee.advertised = advertise &
4364 (ADVERTISED_100baseT_Full |
4365 ADVERTISED_1000baseT_Full);
4366 }
4367
b715ce94
MC		 4368 err = tg3_phy_cl45_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, val);
4369 if (err)
4370 val = 0;
4371
4153577a 4372 switch (tg3_asic_rev(tp)) {
21a00ab2
MC		 4373 case ASIC_REV_5717:
4374 case ASIC_REV_57765:
55086ad9 4375 case ASIC_REV_57766:
21a00ab2 4376 case ASIC_REV_5719:
b715ce94
MC		 4377 /* If we advertised any eee advertisements above... */
4378 if (val)
4379 val = MII_TG3_DSP_TAP26_ALNOKO |
4380 MII_TG3_DSP_TAP26_RMRXSTO |
4381 MII_TG3_DSP_TAP26_OPCSINPT;
21a00ab2 4382 tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, val);
be671947
MC		 4383 /* Fall through */
4384 case ASIC_REV_5720:
c65a17f4 4385 case ASIC_REV_5762:
be671947
MC		 4386 if (!tg3_phydsp_read(tp, MII_TG3_DSP_CH34TP2, &val))
4387 tg3_phydsp_write(tp, MII_TG3_DSP_CH34TP2, val |
4388 MII_TG3_DSP_CH34TP2_HIBW01);
21a00ab2 4389 }
52b02d04 4390
daf3ec68 4391 err2 = tg3_phy_toggle_auxctl_smdsp(tp, false);
42b64a45
MC		 4392 if (!err)
4393 err = err2;
4394 }
4395
4396done:
4397 return err;
4398}
4399
4400static void tg3_phy_copper_begin(struct tg3 *tp)
4401{
d13ba512
MC		 4402 if (tp->link_config.autoneg == AUTONEG_ENABLE ||
4403 (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
4404 u32 adv, fc;
4405
942d1af0
NS		 4406 if ((tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) &&
4407 !(tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN)) {
d13ba512
MC		 4408 adv = ADVERTISED_10baseT_Half |
4409 ADVERTISED_10baseT_Full;
4410 if (tg3_flag(tp, WOL_SPEED_100MB))
4411 adv |= ADVERTISED_100baseT_Half |
4412 ADVERTISED_100baseT_Full;
7c786065
NS		 4413 if (tp->phy_flags & TG3_PHYFLG_1G_ON_VAUX_OK) {
4414 if (!(tp->phy_flags &
4415 TG3_PHYFLG_DISABLE_1G_HD_ADV))
4416 adv |= ADVERTISED_1000baseT_Half;
4417 adv |= ADVERTISED_1000baseT_Full;
4418 }
d13ba512
MC		 4419
4420 fc = FLOW_CTRL_TX | FLOW_CTRL_RX;
42b64a45 4421 } else {
d13ba512
MC		 4422 adv = tp->link_config.advertising;
4423 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
4424 adv &= ~(ADVERTISED_1000baseT_Half |
4425 ADVERTISED_1000baseT_Full);
4426
4427 fc = tp->link_config.flowctrl;
52b02d04 4428 }
52b02d04 4429
d13ba512 4430 tg3_phy_autoneg_cfg(tp, adv, fc);
52b02d04 4431
942d1af0
NS		 4432 if ((tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) &&
4433 (tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN)) {
4434 /* Normally during power down we want to autonegotiate
4435 * the lowest possible speed for WOL. However, to avoid
4436 * link flap, we leave it untouched.
4437 */
4438 return;
4439 }
4440
d13ba512
MC		 4441 tg3_writephy(tp, MII_BMCR,
4442 BMCR_ANENABLE | BMCR_ANRESTART);
4443 } else {
4444 int i;
1da177e4
LT		 4445 u32 bmcr, orig_bmcr;
4446
4447 tp->link_config.active_speed = tp->link_config.speed;
4448 tp->link_config.active_duplex = tp->link_config.duplex;
4449
7c6cdead
NS		 4450 if (tg3_asic_rev(tp) == ASIC_REV_5714) {
4451 /* With autoneg disabled, 5715 only links up when the
4452 * advertisement register has the configured speed
4453 * enabled.
4454 */
4455 tg3_writephy(tp, MII_ADVERTISE, ADVERTISE_ALL);
4456 }
4457
1da177e4
LT		 4458 bmcr = 0;
4459 switch (tp->link_config.speed) {
4460 default:
4461 case SPEED_10:
4462 break;
4463
4464 case SPEED_100:
4465 bmcr |= BMCR_SPEED100;
4466 break;
4467
4468 case SPEED_1000:
221c5637 4469 bmcr |= BMCR_SPEED1000;
1da177e4 4470 break;
855e1111 4471 }
1da177e4
LT		 4472
4473 if (tp->link_config.duplex == DUPLEX_FULL)
4474 bmcr |= BMCR_FULLDPLX;
4475
4476 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
4477 (bmcr != orig_bmcr)) {
4478 tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
4479 for (i = 0; i < 1500; i++) {
4480 u32 tmp;
4481
4482 udelay(10);
4483 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
4484 tg3_readphy(tp, MII_BMSR, &tmp))
4485 continue;
4486 if (!(tmp & BMSR_LSTATUS)) {
4487 udelay(40);
4488 break;
4489 }
4490 }
4491 tg3_writephy(tp, MII_BMCR, bmcr);
4492 udelay(40);
4493 }
1da177e4
LT		 4494 }
4495}
4496
fdad8de4
NS		 4497static int tg3_phy_pull_config(struct tg3 *tp)
4498{
4499 int err;
4500 u32 val;
4501
4502 err = tg3_readphy(tp, MII_BMCR, &val);
4503 if (err)
4504 goto done;
4505
4506 if (!(val & BMCR_ANENABLE)) {
4507 tp->link_config.autoneg = AUTONEG_DISABLE;
4508 tp->link_config.advertising = 0;
4509 tg3_flag_clear(tp, PAUSE_AUTONEG);
4510
4511 err = -EIO;
4512
4513 switch (val & (BMCR_SPEED1000 | BMCR_SPEED100)) {
4514 case 0:
4515 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
4516 goto done;
4517
4518 tp->link_config.speed = SPEED_10;
4519 break;
4520 case BMCR_SPEED100:
4521 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
4522 goto done;
4523
4524 tp->link_config.speed = SPEED_100;
4525 break;
4526 case BMCR_SPEED1000:
4527 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
4528 tp->link_config.speed = SPEED_1000;
4529 break;
4530 }
4531 /* Fall through */
4532 default:
4533 goto done;
4534 }
4535
4536 if (val & BMCR_FULLDPLX)
4537 tp->link_config.duplex = DUPLEX_FULL;
4538 else
4539 tp->link_config.duplex = DUPLEX_HALF;
4540
4541 tp->link_config.flowctrl = FLOW_CTRL_RX | FLOW_CTRL_TX;
4542
4543 err = 0;
4544 goto done;
4545 }
4546
4547 tp->link_config.autoneg = AUTONEG_ENABLE;
4548 tp->link_config.advertising = ADVERTISED_Autoneg;
4549 tg3_flag_set(tp, PAUSE_AUTONEG);
4550
4551 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
4552 u32 adv;
4553
4554 err = tg3_readphy(tp, MII_ADVERTISE, &val);
4555 if (err)
4556 goto done;
4557
4558 adv = mii_adv_to_ethtool_adv_t(val & ADVERTISE_ALL);
4559 tp->link_config.advertising |= adv | ADVERTISED_TP;
4560
4561 tp->link_config.flowctrl = tg3_decode_flowctrl_1000T(val);
4562 } else {
4563 tp->link_config.advertising |= ADVERTISED_FIBRE;
4564 }
4565
4566 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
4567 u32 adv;
4568
4569 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
4570 err = tg3_readphy(tp, MII_CTRL1000, &val);
4571 if (err)
4572 goto done;
4573
4574 adv = mii_ctrl1000_to_ethtool_adv_t(val);
4575 } else {
4576 err = tg3_readphy(tp, MII_ADVERTISE, &val);
4577 if (err)
4578 goto done;
4579
4580 adv = tg3_decode_flowctrl_1000X(val);
4581 tp->link_config.flowctrl = adv;
4582
4583 val &= (ADVERTISE_1000XHALF | ADVERTISE_1000XFULL);
4584 adv = mii_adv_to_ethtool_adv_x(val);
4585 }
4586
4587 tp->link_config.advertising |= adv;
4588 }
4589
4590done:
4591 return err;
4592}
4593
1da177e4
LT		 4594static int tg3_init_5401phy_dsp(struct tg3 *tp)
4595{
4596 int err;
4597
4598 /* Turn off tap power management. */
4599 /* Set Extended packet length bit */
b4bd2929 4600 err = tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, 0x4c20);
1da177e4 4601
6ee7c0a0
MC		 4602 err |= tg3_phydsp_write(tp, 0x0012, 0x1804);
4603 err |= tg3_phydsp_write(tp, 0x0013, 0x1204);
4604 err |= tg3_phydsp_write(tp, 0x8006, 0x0132);
4605 err |= tg3_phydsp_write(tp, 0x8006, 0x0232);
4606 err |= tg3_phydsp_write(tp, 0x201f, 0x0a20);
1da177e4
LT		 4607
4608 udelay(40);
4609
4610 return err;
4611}
4612
ed1ff5c3
NS		 4613static bool tg3_phy_eee_config_ok(struct tg3 *tp)
4614{
5b6c273a 4615 struct ethtool_eee eee;
ed1ff5c3
NS		 4616
4617 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP))
4618 return true;
4619
5b6c273a 4620 tg3_eee_pull_config(tp, &eee);
ed1ff5c3 4621
5b6c273a
NS		 4622 if (tp->eee.eee_enabled) {
4623 if (tp->eee.advertised != eee.advertised ||
4624 tp->eee.tx_lpi_timer != eee.tx_lpi_timer ||
4625 tp->eee.tx_lpi_enabled != eee.tx_lpi_enabled)
4626 return false;
4627 } else {
4628 /* EEE is disabled but we're advertising */
4629 if (eee.advertised)
4630 return false;
4631 }
ed1ff5c3
NS		 4632
4633 return true;
4634}
4635
e2bf73e7 4636static bool tg3_phy_copper_an_config_ok(struct tg3 *tp, u32 *lcladv)
1da177e4 4637{
e2bf73e7 4638 u32 advmsk, tgtadv, advertising;
3600d918 4639
e2bf73e7
MC		 4640 advertising = tp->link_config.advertising;
4641 tgtadv = ethtool_adv_to_mii_adv_t(advertising) & ADVERTISE_ALL;
1da177e4 4642
e2bf73e7
MC		 4643 advmsk = ADVERTISE_ALL;
4644 if (tp->link_config.active_duplex == DUPLEX_FULL) {
f88788f0 4645 tgtadv |= mii_advertise_flowctrl(tp->link_config.flowctrl);
e2bf73e7
MC		 4646 advmsk |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
4647 }
1da177e4 4648
e2bf73e7
MC		 4649 if (tg3_readphy(tp, MII_ADVERTISE, lcladv))
4650 return false;
4651
4652 if ((*lcladv & advmsk) != tgtadv)
4653 return false;
b99d2a57 4654
f07e9af3 4655 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
1da177e4
LT		 4656 u32 tg3_ctrl;
4657
e2bf73e7 4658 tgtadv = ethtool_adv_to_mii_ctrl1000_t(advertising);
3600d918 4659
221c5637 4660 if (tg3_readphy(tp, MII_CTRL1000, &tg3_ctrl))
e2bf73e7 4661 return false;
1da177e4 4662
3198e07f 4663 if (tgtadv &&
4153577a
JP		 4664 (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0 ||
4665 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B0)) {
3198e07f
MC		 4666 tgtadv |= CTL1000_AS_MASTER | CTL1000_ENABLE_MASTER;
4667 tg3_ctrl &= (ADVERTISE_1000HALF | ADVERTISE_1000FULL |
4668 CTL1000_AS_MASTER | CTL1000_ENABLE_MASTER);
4669 } else {
4670 tg3_ctrl &= (ADVERTISE_1000HALF | ADVERTISE_1000FULL);
4671 }
4672
e2bf73e7
MC		 4673 if (tg3_ctrl != tgtadv)
4674 return false;
ef167e27
MC		 4675 }
4676
e2bf73e7 4677 return true;
ef167e27
MC		 4678}
4679
859edb26
MC		 4680static bool tg3_phy_copper_fetch_rmtadv(struct tg3 *tp, u32 *rmtadv)
4681{
4682 u32 lpeth = 0;
4683
4684 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
4685 u32 val;
4686
4687 if (tg3_readphy(tp, MII_STAT1000, &val))
4688 return false;
4689
4690 lpeth = mii_stat1000_to_ethtool_lpa_t(val);
4691 }
4692
4693 if (tg3_readphy(tp, MII_LPA, rmtadv))
4694 return false;
4695
4696 lpeth |= mii_lpa_to_ethtool_lpa_t(*rmtadv);
4697 tp->link_config.rmt_adv = lpeth;
4698
4699 return true;
4700}
4701
953c96e0 4702static bool tg3_test_and_report_link_chg(struct tg3 *tp, bool curr_link_up)
f4a46d1f
NNS		 4703{
4704 if (curr_link_up != tp->link_up) {
4705 if (curr_link_up) {
84421b99 4706 netif_carrier_on(tp->dev);
f4a46d1f 4707 } else {
84421b99 4708 netif_carrier_off(tp->dev);
f4a46d1f
NNS		 4709 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
4710 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4711 }
4712
4713 tg3_link_report(tp);
4714 return true;
4715 }
4716
4717 return false;
4718}
4719
3310e248
MC		 4720static void tg3_clear_mac_status(struct tg3 *tp)
4721{
4722 tw32(MAC_EVENT, 0);
4723
4724 tw32_f(MAC_STATUS,
4725 MAC_STATUS_SYNC_CHANGED |
4726 MAC_STATUS_CFG_CHANGED |
4727 MAC_STATUS_MI_COMPLETION |
4728 MAC_STATUS_LNKSTATE_CHANGED);
4729 udelay(40);
4730}
4731
9e2ecbeb
NS		 4732static void tg3_setup_eee(struct tg3 *tp)
4733{
4734 u32 val;
4735
4736 val = TG3_CPMU_EEE_LNKIDL_PCIE_NL0 |
4737 TG3_CPMU_EEE_LNKIDL_UART_IDL;
4738 if (tg3_chip_rev_id(tp) == CHIPREV_ID_57765_A0)
4739 val |= TG3_CPMU_EEE_LNKIDL_APE_TX_MT;
4740
4741 tw32_f(TG3_CPMU_EEE_LNKIDL_CTRL, val);
4742
4743 tw32_f(TG3_CPMU_EEE_CTRL,
4744 TG3_CPMU_EEE_CTRL_EXIT_20_1_US);
4745
4746 val = TG3_CPMU_EEEMD_ERLY_L1_XIT_DET |
4747 (tp->eee.tx_lpi_enabled ? TG3_CPMU_EEEMD_LPI_IN_TX : 0) |
4748 TG3_CPMU_EEEMD_LPI_IN_RX |
4749 TG3_CPMU_EEEMD_EEE_ENABLE;
4750
4751 if (tg3_asic_rev(tp) != ASIC_REV_5717)
4752 val |= TG3_CPMU_EEEMD_SND_IDX_DET_EN;
4753
4754 if (tg3_flag(tp, ENABLE_APE))
4755 val |= TG3_CPMU_EEEMD_APE_TX_DET_EN;
4756
4757 tw32_f(TG3_CPMU_EEE_MODE, tp->eee.eee_enabled ? val : 0);
4758
4759 tw32_f(TG3_CPMU_EEE_DBTMR1,
4760 TG3_CPMU_DBTMR1_PCIEXIT_2047US |
4761 (tp->eee.tx_lpi_timer & 0xffff));
4762
4763 tw32_f(TG3_CPMU_EEE_DBTMR2,
4764 TG3_CPMU_DBTMR2_APE_TX_2047US |
4765 TG3_CPMU_DBTMR2_TXIDXEQ_2047US);
4766}
4767
953c96e0 4768static int tg3_setup_copper_phy(struct tg3 *tp, bool force_reset)
1da177e4 4769{
953c96e0 4770 bool current_link_up;
f833c4c1 4771 u32 bmsr, val;
ef167e27 4772 u32 lcl_adv, rmt_adv;
1da177e4
LT		 4773 u16 current_speed;
4774 u8 current_duplex;
4775 int i, err;
4776
3310e248 4777 tg3_clear_mac_status(tp);
1da177e4 4778
8ef21428
MC		 4779 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
4780 tw32_f(MAC_MI_MODE,
4781 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
4782 udelay(80);
4783 }
1da177e4 4784
b4bd2929 4785 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_PWRCTL, 0);
1da177e4
LT		 4786
4787 /* Some third-party PHYs need to be reset on link going
4788 * down.
4789 */
4153577a
JP		 4790 if ((tg3_asic_rev(tp) == ASIC_REV_5703 ||
4791 tg3_asic_rev(tp) == ASIC_REV_5704 ||
4792 tg3_asic_rev(tp) == ASIC_REV_5705) &&
f4a46d1f 4793 tp->link_up) {
1da177e4
LT		 4794 tg3_readphy(tp, MII_BMSR, &bmsr);
4795 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
4796 !(bmsr & BMSR_LSTATUS))
953c96e0 4797 force_reset = true;
1da177e4
LT		 4798 }
4799 if (force_reset)
4800 tg3_phy_reset(tp);
4801
79eb6904 4802 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
1da177e4
LT		 4803 tg3_readphy(tp, MII_BMSR, &bmsr);
4804 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
63c3a66f 4805 !tg3_flag(tp, INIT_COMPLETE))
1da177e4
LT		 4806 bmsr = 0;
4807
4808 if (!(bmsr & BMSR_LSTATUS)) {
4809 err = tg3_init_5401phy_dsp(tp);
4810 if (err)
4811 return err;
4812
4813 tg3_readphy(tp, MII_BMSR, &bmsr);
4814 for (i = 0; i < 1000; i++) {
4815 udelay(10);
4816 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
4817 (bmsr & BMSR_LSTATUS)) {
4818 udelay(40);
4819 break;
4820 }
4821 }
4822
79eb6904
MC		 4823 if ((tp->phy_id & TG3_PHY_ID_REV_MASK) ==
4824 TG3_PHY_REV_BCM5401_B0 &&
1da177e4
LT		 4825 !(bmsr & BMSR_LSTATUS) &&
4826 tp->link_config.active_speed == SPEED_1000) {
4827 err = tg3_phy_reset(tp);
4828 if (!err)
4829 err = tg3_init_5401phy_dsp(tp);
4830 if (err)
4831 return err;
4832 }
4833 }
4153577a
JP		 4834 } else if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0 ||
4835 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B0) {
1da177e4
LT		 4836 /* 5701 {A0,B0} CRC bug workaround */
4837 tg3_writephy(tp, 0x15, 0x0a75);
f08aa1a8
MC		 4838 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68);
4839 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
4840 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68);
1da177e4
LT		 4841 }
4842
4843 /* Clear pending interrupts... */
f833c4c1
MC		 4844 tg3_readphy(tp, MII_TG3_ISTAT, &val);
4845 tg3_readphy(tp, MII_TG3_ISTAT, &val);
1da177e4 4846
f07e9af3 4847 if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT)
1da177e4 4848 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
f07e9af3 4849 else if (!(tp->phy_flags & TG3_PHYFLG_IS_FET))
1da177e4
LT		 4850 tg3_writephy(tp, MII_TG3_IMASK, ~0);
4851
4153577a
JP		 4852 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
4853 tg3_asic_rev(tp) == ASIC_REV_5701) {
1da177e4
LT		 4854 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
4855 tg3_writephy(tp, MII_TG3_EXT_CTRL,
4856 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
4857 else
4858 tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
4859 }
4860
953c96e0 4861 current_link_up = false;
e740522e
MC		 4862 current_speed = SPEED_UNKNOWN;
4863 current_duplex = DUPLEX_UNKNOWN;
e348c5e7 4864 tp->phy_flags &= ~TG3_PHYFLG_MDIX_STATE;
859edb26 4865 tp->link_config.rmt_adv = 0;
1da177e4 4866
f07e9af3 4867 if (tp->phy_flags & TG3_PHYFLG_CAPACITIVE_COUPLING) {
15ee95c3
MC		 4868 err = tg3_phy_auxctl_read(tp,
4869 MII_TG3_AUXCTL_SHDWSEL_MISCTEST,
4870 &val);
4871 if (!err && !(val & (1 << 10))) {
b4bd2929
MC		 4872 tg3_phy_auxctl_write(tp,
4873 MII_TG3_AUXCTL_SHDWSEL_MISCTEST,
4874 val | (1 << 10));
1da177e4
LT		 4875 goto relink;
4876 }
4877 }
4878
4879 bmsr = 0;
4880 for (i = 0; i < 100; i++) {
4881 tg3_readphy(tp, MII_BMSR, &bmsr);
4882 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
4883 (bmsr & BMSR_LSTATUS))
4884 break;
4885 udelay(40);
4886 }
4887
4888 if (bmsr & BMSR_LSTATUS) {
4889 u32 aux_stat, bmcr;
4890
4891 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
4892 for (i = 0; i < 2000; i++) {
4893 udelay(10);
4894 if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
4895 aux_stat)
4896 break;
4897 }
4898
4899 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
4900 &current_speed,
4901 &current_duplex);
4902
4903 bmcr = 0;
4904 for (i = 0; i < 200; i++) {
4905 tg3_readphy(tp, MII_BMCR, &bmcr);
4906 if (tg3_readphy(tp, MII_BMCR, &bmcr))
4907 continue;
4908 if (bmcr && bmcr != 0x7fff)
4909 break;
4910 udelay(10);
4911 }
4912
ef167e27
MC		 4913 lcl_adv = 0;
4914 rmt_adv = 0;
1da177e4 4915
ef167e27
MC		 4916 tp->link_config.active_speed = current_speed;
4917 tp->link_config.active_duplex = current_duplex;
4918
4919 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
ed1ff5c3
NS		 4920 bool eee_config_ok = tg3_phy_eee_config_ok(tp);
4921
ef167e27 4922 if ((bmcr & BMCR_ANENABLE) &&
ed1ff5c3 4923 eee_config_ok &&
e2bf73e7 4924 tg3_phy_copper_an_config_ok(tp, &lcl_adv) &&
859edb26 4925 tg3_phy_copper_fetch_rmtadv(tp, &rmt_adv))
953c96e0 4926 current_link_up = true;
ed1ff5c3
NS		 4927
4928 /* EEE settings changes take effect only after a phy
4929 * reset. If we have skipped a reset due to Link Flap
4930 * Avoidance being enabled, do it now.
4931 */
4932 if (!eee_config_ok &&
4933 (tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN) &&
5b6c273a
NS		 4934 !force_reset) {
4935 tg3_setup_eee(tp);
ed1ff5c3 4936 tg3_phy_reset(tp);
5b6c273a 4937 }
1da177e4
LT		 4938 } else {
4939 if (!(bmcr & BMCR_ANENABLE) &&
4940 tp->link_config.speed == current_speed &&
f0fcd7a9 4941 tp->link_config.duplex == current_duplex) {
953c96e0 4942 current_link_up = true;
1da177e4
LT		 4943 }
4944 }
4945
953c96e0 4946 if (current_link_up &&
e348c5e7
MC		 4947 tp->link_config.active_duplex == DUPLEX_FULL) {
4948 u32 reg, bit;
4949
4950 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
4951 reg = MII_TG3_FET_GEN_STAT;
4952 bit = MII_TG3_FET_GEN_STAT_MDIXSTAT;
4953 } else {
4954 reg = MII_TG3_EXT_STAT;
4955 bit = MII_TG3_EXT_STAT_MDIX;
4956 }
4957
4958 if (!tg3_readphy(tp, reg, &val) && (val & bit))
4959 tp->phy_flags |= TG3_PHYFLG_MDIX_STATE;
4960
ef167e27 4961 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
e348c5e7 4962 }
1da177e4
LT		 4963 }
4964
1da177e4 4965relink:
953c96e0 4966 if (!current_link_up || (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
1da177e4
LT		 4967 tg3_phy_copper_begin(tp);
4968
7e6c63f0 4969 if (tg3_flag(tp, ROBOSWITCH)) {
953c96e0 4970 current_link_up = true;
7e6c63f0
HM		 4971 /* FIXME: when BCM5325 switch is used use 100 MBit/s */
4972 current_speed = SPEED_1000;
4973 current_duplex = DUPLEX_FULL;
4974 tp->link_config.active_speed = current_speed;
4975 tp->link_config.active_duplex = current_duplex;
4976 }
4977
f833c4c1 4978 tg3_readphy(tp, MII_BMSR, &bmsr);
06c03c02
MB		 4979 if ((!tg3_readphy(tp, MII_BMSR, &bmsr) && (bmsr & BMSR_LSTATUS)) ||
4980 (tp->mac_mode & MAC_MODE_PORT_INT_LPBACK))
953c96e0 4981 current_link_up = true;
1da177e4
LT		 4982 }
4983
4984 tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
953c96e0 4985 if (current_link_up) {
1da177e4
LT		 4986 if (tp->link_config.active_speed == SPEED_100 ||
4987 tp->link_config.active_speed == SPEED_10)
4988 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
4989 else
4990 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
f07e9af3 4991 } else if (tp->phy_flags & TG3_PHYFLG_IS_FET)
7f97a4bd
MC		 4992 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
4993 else
1da177e4
LT		 4994 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
4995
7e6c63f0
HM		 4996 /* In order for the 5750 core in BCM4785 chip to work properly
4997 * in RGMII mode, the Led Control Register must be set up.
4998 */
4999 if (tg3_flag(tp, RGMII_MODE)) {
5000 u32 led_ctrl = tr32(MAC_LED_CTRL);
5001 led_ctrl &= ~(LED_CTRL_1000MBPS_ON | LED_CTRL_100MBPS_ON);
5002
5003 if (tp->link_config.active_speed == SPEED_10)
5004 led_ctrl |= LED_CTRL_LNKLED_OVERRIDE;
5005 else if (tp->link_config.active_speed == SPEED_100)
5006 led_ctrl |= (LED_CTRL_LNKLED_OVERRIDE |
5007 LED_CTRL_100MBPS_ON);
5008 else if (tp->link_config.active_speed == SPEED_1000)
5009 led_ctrl |= (LED_CTRL_LNKLED_OVERRIDE |
5010 LED_CTRL_1000MBPS_ON);
5011
5012 tw32(MAC_LED_CTRL, led_ctrl);
5013 udelay(40);
5014 }
5015
1da177e4
LT		 5016 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
5017 if (tp->link_config.active_duplex == DUPLEX_HALF)
5018 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
5019
4153577a 5020 if (tg3_asic_rev(tp) == ASIC_REV_5700) {
953c96e0 5021 if (current_link_up &&
e8f3f6ca 5022 tg3_5700_link_polarity(tp, tp->link_config.active_speed))
1da177e4 5023 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
e8f3f6ca
MC		 5024 else
5025 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
1da177e4
LT		 5026 }
5027
5028 /* ??? Without this setting Netgear GA302T PHY does not
5029 * ??? send/receive packets...
5030 */
79eb6904 5031 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411 &&
4153577a 5032 tg3_chip_rev_id(tp) == CHIPREV_ID_5700_ALTIMA) {
1da177e4
LT		 5033 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
5034 tw32_f(MAC_MI_MODE, tp->mi_mode);
5035 udelay(80);
5036 }
5037
5038 tw32_f(MAC_MODE, tp->mac_mode);
5039 udelay(40);
5040
52b02d04
MC		 5041 tg3_phy_eee_adjust(tp, current_link_up);
5042
63c3a66f 5043 if (tg3_flag(tp, USE_LINKCHG_REG)) {
1da177e4
LT		 5044 /* Polled via timer. */
5045 tw32_f(MAC_EVENT, 0);
5046 } else {
5047 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
5048 }
5049 udelay(40);
5050
4153577a 5051 if (tg3_asic_rev(tp) == ASIC_REV_5700 &&
953c96e0 5052 current_link_up &&
1da177e4 5053 tp->link_config.active_speed == SPEED_1000 &&
63c3a66f 5054 (tg3_flag(tp, PCIX_MODE) || tg3_flag(tp, PCI_HIGH_SPEED))) {
1da177e4
LT		 5055 udelay(120);
5056 tw32_f(MAC_STATUS,
5057 (MAC_STATUS_SYNC_CHANGED |
5058 MAC_STATUS_CFG_CHANGED));
5059 udelay(40);
5060 tg3_write_mem(tp,
5061 NIC_SRAM_FIRMWARE_MBOX,
5062 NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
5063 }
5064
5e7dfd0f 5065 /* Prevent send BD corruption. */
63c3a66f 5066 if (tg3_flag(tp, CLKREQ_BUG)) {
5e7dfd0f
MC		 5067 if (tp->link_config.active_speed == SPEED_100 ||
5068 tp->link_config.active_speed == SPEED_10)
0f49bfbd
JL		 5069 pcie_capability_clear_word(tp->pdev, PCI_EXP_LNKCTL,
5070 PCI_EXP_LNKCTL_CLKREQ_EN);
5e7dfd0f 5071 else
0f49bfbd
JL		 5072 pcie_capability_set_word(tp->pdev, PCI_EXP_LNKCTL,
5073 PCI_EXP_LNKCTL_CLKREQ_EN);
5e7dfd0f
MC		 5074 }
5075
f4a46d1f 5076 tg3_test_and_report_link_chg(tp, current_link_up);
1da177e4
LT		 5077
5078 return 0;
5079}
5080
5081struct tg3_fiber_aneginfo {
5082 int state;
5083#define ANEG_STATE_UNKNOWN 0
5084#define ANEG_STATE_AN_ENABLE 1
5085#define ANEG_STATE_RESTART_INIT 2
5086#define ANEG_STATE_RESTART 3
5087#define ANEG_STATE_DISABLE_LINK_OK 4
5088#define ANEG_STATE_ABILITY_DETECT_INIT 5
5089#define ANEG_STATE_ABILITY_DETECT 6
5090#define ANEG_STATE_ACK_DETECT_INIT 7
5091#define ANEG_STATE_ACK_DETECT 8
5092#define ANEG_STATE_COMPLETE_ACK_INIT 9
5093#define ANEG_STATE_COMPLETE_ACK 10
5094#define ANEG_STATE_IDLE_DETECT_INIT 11
5095#define ANEG_STATE_IDLE_DETECT 12
5096#define ANEG_STATE_LINK_OK 13
5097#define ANEG_STATE_NEXT_PAGE_WAIT_INIT 14
5098#define ANEG_STATE_NEXT_PAGE_WAIT 15
5099
5100 u32 flags;
5101#define MR_AN_ENABLE 0x00000001
5102#define MR_RESTART_AN 0x00000002
5103#define MR_AN_COMPLETE 0x00000004
5104#define MR_PAGE_RX 0x00000008
5105#define MR_NP_LOADED 0x00000010
5106#define MR_TOGGLE_TX 0x00000020
5107#define MR_LP_ADV_FULL_DUPLEX 0x00000040
5108#define MR_LP_ADV_HALF_DUPLEX 0x00000080
5109#define MR_LP_ADV_SYM_PAUSE 0x00000100
5110#define MR_LP_ADV_ASYM_PAUSE 0x00000200
5111#define MR_LP_ADV_REMOTE_FAULT1 0x00000400
5112#define MR_LP_ADV_REMOTE_FAULT2 0x00000800
5113#define MR_LP_ADV_NEXT_PAGE 0x00001000
5114#define MR_TOGGLE_RX 0x00002000
5115#define MR_NP_RX 0x00004000
5116
5117#define MR_LINK_OK 0x80000000
5118
5119 unsigned long link_time, cur_time;
5120
5121 u32 ability_match_cfg;
5122 int ability_match_count;
5123
5124 char ability_match, idle_match, ack_match;
5125
5126 u32 txconfig, rxconfig;
5127#define ANEG_CFG_NP 0x00000080
5128#define ANEG_CFG_ACK 0x00000040
5129#define ANEG_CFG_RF2 0x00000020
5130#define ANEG_CFG_RF1 0x00000010
5131#define ANEG_CFG_PS2 0x00000001
5132#define ANEG_CFG_PS1 0x00008000
5133#define ANEG_CFG_HD 0x00004000
5134#define ANEG_CFG_FD 0x00002000
5135#define ANEG_CFG_INVAL 0x00001f06
5136
5137};
5138#define ANEG_OK 0
5139#define ANEG_DONE 1
5140#define ANEG_TIMER_ENAB 2
5141#define ANEG_FAILED -1
5142
5143#define ANEG_STATE_SETTLE_TIME 10000
5144
5145static int tg3_fiber_aneg_smachine(struct tg3 *tp,
5146 struct tg3_fiber_aneginfo *ap)
5147{
5be73b47 5148 u16 flowctrl;
1da177e4
LT		 5149 unsigned long delta;
5150 u32 rx_cfg_reg;
5151 int ret;
5152
5153 if (ap->state == ANEG_STATE_UNKNOWN) {
5154 ap->rxconfig = 0;
5155 ap->link_time = 0;
5156 ap->cur_time = 0;
5157 ap->ability_match_cfg = 0;
5158 ap->ability_match_count = 0;
5159 ap->ability_match = 0;
5160 ap->idle_match = 0;
5161 ap->ack_match = 0;
5162 }
5163 ap->cur_time++;
5164
5165 if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
5166 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
5167
5168 if (rx_cfg_reg != ap->ability_match_cfg) {
5169 ap->ability_match_cfg = rx_cfg_reg;
5170 ap->ability_match = 0;
5171 ap->ability_match_count = 0;
5172 } else {
5173 if (++ap->ability_match_count > 1) {
5174 ap->ability_match = 1;
5175 ap->ability_match_cfg = rx_cfg_reg;
5176 }
5177 }
5178 if (rx_cfg_reg & ANEG_CFG_ACK)
5179 ap->ack_match = 1;
5180 else
5181 ap->ack_match = 0;
5182
5183 ap->idle_match = 0;
5184 } else {
5185 ap->idle_match = 1;
5186 ap->ability_match_cfg = 0;
5187 ap->ability_match_count = 0;
5188 ap->ability_match = 0;
5189 ap->ack_match = 0;
5190
5191 rx_cfg_reg = 0;
5192 }
5193
5194 ap->rxconfig = rx_cfg_reg;
5195 ret = ANEG_OK;
5196
33f401ae 5197 switch (ap->state) {
1da177e4
LT		 5198 case ANEG_STATE_UNKNOWN:
5199 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
5200 ap->state = ANEG_STATE_AN_ENABLE;
5201
5202 /* fallthru */
5203 case ANEG_STATE_AN_ENABLE:
5204 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
5205 if (ap->flags & MR_AN_ENABLE) {
5206 ap->link_time = 0;
5207 ap->cur_time = 0;
5208 ap->ability_match_cfg = 0;
5209 ap->ability_match_count = 0;
5210 ap->ability_match = 0;
5211 ap->idle_match = 0;
5212 ap->ack_match = 0;
5213
5214 ap->state = ANEG_STATE_RESTART_INIT;
5215 } else {
5216 ap->state = ANEG_STATE_DISABLE_LINK_OK;
5217 }
5218 break;
5219
5220 case ANEG_STATE_RESTART_INIT:
5221 ap->link_time = ap->cur_time;
5222 ap->flags &= ~(MR_NP_LOADED);
5223 ap->txconfig = 0;
5224 tw32(MAC_TX_AUTO_NEG, 0);
5225 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
5226 tw32_f(MAC_MODE, tp->mac_mode);
5227 udelay(40);
5228
5229 ret = ANEG_TIMER_ENAB;
5230 ap->state = ANEG_STATE_RESTART;
5231
5232 /* fallthru */
5233 case ANEG_STATE_RESTART:
5234 delta = ap->cur_time - ap->link_time;
859a5887 5235 if (delta > ANEG_STATE_SETTLE_TIME)
1da177e4 5236 ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
859a5887 5237 else
1da177e4 5238 ret = ANEG_TIMER_ENAB;
1da177e4
LT		 5239 break;
5240
5241 case ANEG_STATE_DISABLE_LINK_OK:
5242 ret = ANEG_DONE;
5243 break;
5244
5245 case ANEG_STATE_ABILITY_DETECT_INIT:
5246 ap->flags &= ~(MR_TOGGLE_TX);
5be73b47
MC		 5247 ap->txconfig = ANEG_CFG_FD;
5248 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
5249 if (flowctrl & ADVERTISE_1000XPAUSE)
5250 ap->txconfig |= ANEG_CFG_PS1;
5251 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
5252 ap->txconfig |= ANEG_CFG_PS2;
1da177e4
LT		 5253 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
5254 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
5255 tw32_f(MAC_MODE, tp->mac_mode);
5256 udelay(40);
5257
5258 ap->state = ANEG_STATE_ABILITY_DETECT;
5259 break;
5260
5261 case ANEG_STATE_ABILITY_DETECT:
859a5887 5262 if (ap->ability_match != 0 && ap->rxconfig != 0)
1da177e4 5263 ap->state = ANEG_STATE_ACK_DETECT_INIT;
1da177e4
LT		 5264 break;
5265
5266 case ANEG_STATE_ACK_DETECT_INIT:
5267 ap->txconfig |= ANEG_CFG_ACK;
5268 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
5269 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
5270 tw32_f(MAC_MODE, tp->mac_mode);
5271 udelay(40);
5272
5273 ap->state = ANEG_STATE_ACK_DETECT;
5274
5275 /* fallthru */
5276 case ANEG_STATE_ACK_DETECT:
5277 if (ap->ack_match != 0) {
5278 if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
5279 (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
5280 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
5281 } else {
5282 ap->state = ANEG_STATE_AN_ENABLE;
5283 }
5284 } else if (ap->ability_match != 0 &&
5285 ap->rxconfig == 0) {
5286 ap->state = ANEG_STATE_AN_ENABLE;
5287 }
5288 break;
5289
5290 case ANEG_STATE_COMPLETE_ACK_INIT:
5291 if (ap->rxconfig & ANEG_CFG_INVAL) {
5292 ret = ANEG_FAILED;
5293 break;
5294 }
5295 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
5296 MR_LP_ADV_HALF_DUPLEX |
5297 MR_LP_ADV_SYM_PAUSE |
5298 MR_LP_ADV_ASYM_PAUSE |
5299 MR_LP_ADV_REMOTE_FAULT1 |
5300 MR_LP_ADV_REMOTE_FAULT2 |
5301 MR_LP_ADV_NEXT_PAGE |
5302 MR_TOGGLE_RX |
5303 MR_NP_RX);
5304 if (ap->rxconfig & ANEG_CFG_FD)
5305 ap->flags |= MR_LP_ADV_FULL_DUPLEX;
5306 if (ap->rxconfig & ANEG_CFG_HD)
5307 ap->flags |= MR_LP_ADV_HALF_DUPLEX;
5308 if (ap->rxconfig & ANEG_CFG_PS1)
5309 ap->flags |= MR_LP_ADV_SYM_PAUSE;
5310 if (ap->rxconfig & ANEG_CFG_PS2)
5311 ap->flags |= MR_LP_ADV_ASYM_PAUSE;
5312 if (ap->rxconfig & ANEG_CFG_RF1)
5313 ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
5314 if (ap->rxconfig & ANEG_CFG_RF2)
5315 ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
5316 if (ap->rxconfig & ANEG_CFG_NP)
5317 ap->flags |= MR_LP_ADV_NEXT_PAGE;
5318
5319 ap->link_time = ap->cur_time;
5320
5321 ap->flags ^= (MR_TOGGLE_TX);
5322 if (ap->rxconfig & 0x0008)
5323 ap->flags |= MR_TOGGLE_RX;
5324 if (ap->rxconfig & ANEG_CFG_NP)
5325 ap->flags |= MR_NP_RX;
5326 ap->flags |= MR_PAGE_RX;
5327
5328 ap->state = ANEG_STATE_COMPLETE_ACK;
5329 ret = ANEG_TIMER_ENAB;
5330 break;
5331
5332 case ANEG_STATE_COMPLETE_ACK:
5333 if (ap->ability_match != 0 &&
5334 ap->rxconfig == 0) {
5335 ap->state = ANEG_STATE_AN_ENABLE;
5336 break;
5337 }
5338 delta = ap->cur_time - ap->link_time;
5339 if (delta > ANEG_STATE_SETTLE_TIME) {
5340 if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
5341 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
5342 } else {
5343 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
5344 !(ap->flags & MR_NP_RX)) {
5345 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
5346 } else {
5347 ret = ANEG_FAILED;
5348 }
5349 }
5350 }
5351 break;
5352
5353 case ANEG_STATE_IDLE_DETECT_INIT:
5354 ap->link_time = ap->cur_time;
5355 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
5356 tw32_f(MAC_MODE, tp->mac_mode);
5357 udelay(40);
5358
5359 ap->state = ANEG_STATE_IDLE_DETECT;
5360 ret = ANEG_TIMER_ENAB;
5361 break;
5362
5363 case ANEG_STATE_IDLE_DETECT:
5364 if (ap->ability_match != 0 &&
5365 ap->rxconfig == 0) {
5366 ap->state = ANEG_STATE_AN_ENABLE;
5367 break;
5368 }
5369 delta = ap->cur_time - ap->link_time;
5370 if (delta > ANEG_STATE_SETTLE_TIME) {
5371 /* XXX another gem from the Broadcom driver :( */
5372 ap->state = ANEG_STATE_LINK_OK;
5373 }
5374 break;
5375
5376 case ANEG_STATE_LINK_OK:
5377 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
5378 ret = ANEG_DONE;
5379 break;
5380
5381 case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
5382 /* ??? unimplemented */
5383 break;
5384
5385 case ANEG_STATE_NEXT_PAGE_WAIT:
5386 /* ??? unimplemented */
5387 break;
5388
5389 default:
5390 ret = ANEG_FAILED;
5391 break;
855e1111 5392 }
1da177e4
LT		 5393
5394 return ret;
5395}
5396
5be73b47 5397static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags)
1da177e4
LT		 5398{
5399 int res = 0;
5400 struct tg3_fiber_aneginfo aninfo;
5401 int status = ANEG_FAILED;
5402 unsigned int tick;
5403 u32 tmp;
5404
5405 tw32_f(MAC_TX_AUTO_NEG, 0);
5406
5407 tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
5408 tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
5409 udelay(40);
5410
5411 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
5412 udelay(40);
5413
5414 memset(&aninfo, 0, sizeof(aninfo));
5415 aninfo.flags |= MR_AN_ENABLE;
5416 aninfo.state = ANEG_STATE_UNKNOWN;
5417 aninfo.cur_time = 0;
5418 tick = 0;
5419 while (++tick < 195000) {
5420 status = tg3_fiber_aneg_smachine(tp, &aninfo);
5421 if (status == ANEG_DONE || status == ANEG_FAILED)
5422 break;
5423
5424 udelay(1);
5425 }
5426
5427 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
5428 tw32_f(MAC_MODE, tp->mac_mode);
5429 udelay(40);
5430
5be73b47
MC		 5431 *txflags = aninfo.txconfig;
5432 *rxflags = aninfo.flags;
1da177e4
LT		 5433
5434 if (status == ANEG_DONE &&
5435 (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
5436 MR_LP_ADV_FULL_DUPLEX)))
5437 res = 1;
5438
5439 return res;
5440}
5441
5442static void tg3_init_bcm8002(struct tg3 *tp)
5443{
5444 u32 mac_status = tr32(MAC_STATUS);
5445 int i;
5446
5447 /* Reset when initting first time or we have a link. */
63c3a66f 5448 if (tg3_flag(tp, INIT_COMPLETE) &&
1da177e4
LT		 5449 !(mac_status & MAC_STATUS_PCS_SYNCED))
5450 return;
5451
5452 /* Set PLL lock range. */
5453 tg3_writephy(tp, 0x16, 0x8007);
5454
5455 /* SW reset */
5456 tg3_writephy(tp, MII_BMCR, BMCR_RESET);
5457
5458 /* Wait for reset to complete. */
5459 /* XXX schedule_timeout() ... */
5460 for (i = 0; i < 500; i++)
5461 udelay(10);
5462
5463 /* Config mode; select PMA/Ch 1 regs. */
5464 tg3_writephy(tp, 0x10, 0x8411);
5465
5466 /* Enable auto-lock and comdet, select txclk for tx. */
5467 tg3_writephy(tp, 0x11, 0x0a10);
5468
5469 tg3_writephy(tp, 0x18, 0x00a0);
5470 tg3_writephy(tp, 0x16, 0x41ff);
5471
5472 /* Assert and deassert POR. */
5473 tg3_writephy(tp, 0x13, 0x0400);
5474 udelay(40);
5475 tg3_writephy(tp, 0x13, 0x0000);
5476
5477 tg3_writephy(tp, 0x11, 0x0a50);
5478 udelay(40);
5479 tg3_writephy(tp, 0x11, 0x0a10);
5480
5481 /* Wait for signal to stabilize */
5482 /* XXX schedule_timeout() ... */
5483 for (i = 0; i < 15000; i++)
5484 udelay(10);
5485
5486 /* Deselect the channel register so we can read the PHYID
5487 * later.
5488 */
5489 tg3_writephy(tp, 0x10, 0x8011);
5490}
5491
953c96e0 5492static bool tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
1da177e4 5493{
82cd3d11 5494 u16 flowctrl;
953c96e0 5495 bool current_link_up;
1da177e4
LT		 5496 u32 sg_dig_ctrl, sg_dig_status;
5497 u32 serdes_cfg, expected_sg_dig_ctrl;
5498 int workaround, port_a;
1da177e4
LT		 5499
5500 serdes_cfg = 0;
5501 expected_sg_dig_ctrl = 0;
5502 workaround = 0;
5503 port_a = 1;
953c96e0 5504 current_link_up = false;
1da177e4 5505
4153577a
JP		 5506 if (tg3_chip_rev_id(tp) != CHIPREV_ID_5704_A0 &&
5507 tg3_chip_rev_id(tp) != CHIPREV_ID_5704_A1) {
1da177e4
LT		 5508 workaround = 1;
5509 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
5510 port_a = 0;
5511
5512 /* preserve bits 0-11,13,14 for signal pre-emphasis */
5513 /* preserve bits 20-23 for voltage regulator */
5514 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
5515 }
5516
5517 sg_dig_ctrl = tr32(SG_DIG_CTRL);
5518
5519 if (tp->link_config.autoneg != AUTONEG_ENABLE) {
c98f6e3b 5520 if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) {
1da177e4
LT		 5521 if (workaround) {
5522 u32 val = serdes_cfg;
5523
5524 if (port_a)
5525 val |= 0xc010000;
5526 else
5527 val |= 0x4010000;
5528 tw32_f(MAC_SERDES_CFG, val);
5529 }
c98f6e3b
MC		 5530
5531 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
1da177e4
LT		 5532 }
5533 if (mac_status & MAC_STATUS_PCS_SYNCED) {
5534 tg3_setup_flow_control(tp, 0, 0);
953c96e0 5535 current_link_up = true;
1da177e4
LT		 5536 }
5537 goto out;
5538 }
5539
5540 /* Want auto-negotiation. */
c98f6e3b 5541 expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP;
1da177e4 5542
82cd3d11
MC		 5543 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
5544 if (flowctrl & ADVERTISE_1000XPAUSE)
5545 expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP;
5546 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
5547 expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE;
1da177e4
LT		 5548
5549 if (sg_dig_ctrl != expected_sg_dig_ctrl) {
f07e9af3 5550 if ((tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT) &&
3d3ebe74
MC		 5551 tp->serdes_counter &&
5552 ((mac_status & (MAC_STATUS_PCS_SYNCED |
5553 MAC_STATUS_RCVD_CFG)) ==
5554 MAC_STATUS_PCS_SYNCED)) {
5555 tp->serdes_counter--;
953c96e0 5556 current_link_up = true;
3d3ebe74
MC		 5557 goto out;
5558 }
5559restart_autoneg:
1da177e4
LT		 5560 if (workaround)
5561 tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
c98f6e3b 5562 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET);
1da177e4
LT		 5563 udelay(5);
5564 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
5565
3d3ebe74 5566 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
f07e9af3 5567 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
1da177e4
LT		 5568 } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
5569 MAC_STATUS_SIGNAL_DET)) {
3d3ebe74 5570 sg_dig_status = tr32(SG_DIG_STATUS);
1da177e4
LT		 5571 mac_status = tr32(MAC_STATUS);
5572
c98f6e3b 5573 if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) &&
1da177e4 5574 (mac_status & MAC_STATUS_PCS_SYNCED)) {
82cd3d11
MC		 5575 u32 local_adv = 0, remote_adv = 0;
5576
5577 if (sg_dig_ctrl & SG_DIG_PAUSE_CAP)
5578 local_adv |= ADVERTISE_1000XPAUSE;
5579 if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE)
5580 local_adv |= ADVERTISE_1000XPSE_ASYM;
1da177e4 5581
c98f6e3b 5582 if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE)
82cd3d11 5583 remote_adv |= LPA_1000XPAUSE;
c98f6e3b 5584 if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE)
82cd3d11 5585 remote_adv |= LPA_1000XPAUSE_ASYM;
1da177e4 5586
859edb26
MC		 5587 tp->link_config.rmt_adv =
5588 mii_adv_to_ethtool_adv_x(remote_adv);
5589
1da177e4 5590 tg3_setup_flow_control(tp, local_adv, remote_adv);
953c96e0 5591 current_link_up = true;
3d3ebe74 5592 tp->serdes_counter = 0;
f07e9af3 5593 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
c98f6e3b 5594 } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) {
3d3ebe74
MC		 5595 if (tp->serdes_counter)
5596 tp->serdes_counter--;
1da177e4
LT		 5597 else {
5598 if (workaround) {
5599 u32 val = serdes_cfg;
5600
5601 if (port_a)
5602 val |= 0xc010000;
5603 else
5604 val |= 0x4010000;
5605
5606 tw32_f(MAC_SERDES_CFG, val);
5607 }
5608
c98f6e3b 5609 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
1da177e4
LT		 5610 udelay(40);
5611
5612 /* Link parallel detection - link is up */
5613 /* only if we have PCS_SYNC and not */
5614 /* receiving config code words */
5615 mac_status = tr32(MAC_STATUS);
5616 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
5617 !(mac_status & MAC_STATUS_RCVD_CFG)) {
5618 tg3_setup_flow_control(tp, 0, 0);
953c96e0 5619 current_link_up = true;
f07e9af3
MC		 5620 tp->phy_flags |=
5621 TG3_PHYFLG_PARALLEL_DETECT;
3d3ebe74
MC		 5622 tp->serdes_counter =
5623 SERDES_PARALLEL_DET_TIMEOUT;
5624 } else
5625 goto restart_autoneg;
1da177e4
LT		 5626 }
5627 }
3d3ebe74
MC		 5628 } else {
5629 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
f07e9af3 5630 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
1da177e4
LT		 5631 }
5632
5633out:
5634 return current_link_up;
5635}
5636
953c96e0 5637static bool tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
1da177e4 5638{
953c96e0 5639 bool current_link_up = false;
1da177e4 5640
5cf64b8a 5641 if (!(mac_status & MAC_STATUS_PCS_SYNCED))
1da177e4 5642 goto out;
1da177e4
LT		 5643
5644 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
5be73b47 5645 u32 txflags, rxflags;
1da177e4 5646 int i;
6aa20a22 5647
5be73b47
MC		 5648 if (fiber_autoneg(tp, &txflags, &rxflags)) {
5649 u32 local_adv = 0, remote_adv = 0;
1da177e4 5650
5be73b47
MC		 5651 if (txflags & ANEG_CFG_PS1)
5652 local_adv |= ADVERTISE_1000XPAUSE;
5653 if (txflags & ANEG_CFG_PS2)
5654 local_adv |= ADVERTISE_1000XPSE_ASYM;
5655
5656 if (rxflags & MR_LP_ADV_SYM_PAUSE)
5657 remote_adv |= LPA_1000XPAUSE;
5658 if (rxflags & MR_LP_ADV_ASYM_PAUSE)
5659 remote_adv |= LPA_1000XPAUSE_ASYM;
1da177e4 5660
859edb26
MC		 5661 tp->link_config.rmt_adv =
5662 mii_adv_to_ethtool_adv_x(remote_adv);
5663
1da177e4
LT		 5664 tg3_setup_flow_control(tp, local_adv, remote_adv);
5665
953c96e0 5666 current_link_up = true;
1da177e4
LT		 5667 }
5668 for (i = 0; i < 30; i++) {
5669 udelay(20);
5670 tw32_f(MAC_STATUS,
5671 (MAC_STATUS_SYNC_CHANGED |
5672 MAC_STATUS_CFG_CHANGED));
5673 udelay(40);
5674 if ((tr32(MAC_STATUS) &
5675 (MAC_STATUS_SYNC_CHANGED |
5676 MAC_STATUS_CFG_CHANGED)) == 0)
5677 break;
5678 }
5679
5680 mac_status = tr32(MAC_STATUS);
953c96e0 5681 if (!current_link_up &&
1da177e4
LT		 5682 (mac_status & MAC_STATUS_PCS_SYNCED) &&
5683 !(mac_status & MAC_STATUS_RCVD_CFG))
953c96e0 5684 current_link_up = true;
1da177e4 5685 } else {
5be73b47
MC		 5686 tg3_setup_flow_control(tp, 0, 0);
5687
1da177e4 5688 /* Forcing 1000FD link up. */
953c96e0 5689 current_link_up = true;
1da177e4
LT		 5690
5691 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
5692 udelay(40);
e8f3f6ca
MC		 5693
5694 tw32_f(MAC_MODE, tp->mac_mode);
5695 udelay(40);
1da177e4
LT		 5696 }
5697
5698out:
5699 return current_link_up;
5700}
5701
953c96e0 5702static int tg3_setup_fiber_phy(struct tg3 *tp, bool force_reset)
1da177e4
LT		 5703{
5704 u32 orig_pause_cfg;
5705 u16 orig_active_speed;
5706 u8 orig_active_duplex;
5707 u32 mac_status;
953c96e0 5708 bool current_link_up;
1da177e4
LT		 5709 int i;
5710
8d018621 5711 orig_pause_cfg = tp->link_config.active_flowctrl;
1da177e4
LT		 5712 orig_active_speed = tp->link_config.active_speed;
5713 orig_active_duplex = tp->link_config.active_duplex;
5714
63c3a66f 5715 if (!tg3_flag(tp, HW_AUTONEG) &&
f4a46d1f 5716 tp->link_up &&
63c3a66f 5717 tg3_flag(tp, INIT_COMPLETE)) {
1da177e4
LT		 5718 mac_status = tr32(MAC_STATUS);
5719 mac_status &= (MAC_STATUS_PCS_SYNCED |
5720 MAC_STATUS_SIGNAL_DET |
5721 MAC_STATUS_CFG_CHANGED |
5722 MAC_STATUS_RCVD_CFG);
5723 if (mac_status == (MAC_STATUS_PCS_SYNCED |
5724 MAC_STATUS_SIGNAL_DET)) {
5725 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
5726 MAC_STATUS_CFG_CHANGED));
5727 return 0;
5728 }
5729 }
5730
5731 tw32_f(MAC_TX_AUTO_NEG, 0);
5732
5733 tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
5734 tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
5735 tw32_f(MAC_MODE, tp->mac_mode);
5736 udelay(40);
5737
79eb6904 5738 if (tp->phy_id == TG3_PHY_ID_BCM8002)
1da177e4
LT		 5739 tg3_init_bcm8002(tp);
5740
5741 /* Enable link change event even when serdes polling. */
5742 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
5743 udelay(40);
5744
953c96e0 5745 current_link_up = false;
859edb26 5746 tp->link_config.rmt_adv = 0;
1da177e4
LT		 5747 mac_status = tr32(MAC_STATUS);
5748
63c3a66f 5749 if (tg3_flag(tp, HW_AUTONEG))
1da177e4
LT		 5750 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
5751 else
5752 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
5753
898a56f8 5754 tp->napi[0].hw_status->status =
1da177e4 5755 (SD_STATUS_UPDATED |
898a56f8 5756 (tp->napi[0].hw_status->status & ~SD_STATUS_LINK_CHG));
1da177e4
LT		 5757
5758 for (i = 0; i < 100; i++) {
5759 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
5760 MAC_STATUS_CFG_CHANGED));
5761 udelay(5);
5762 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
3d3ebe74
MC		 5763 MAC_STATUS_CFG_CHANGED |
5764 MAC_STATUS_LNKSTATE_CHANGED)) == 0)
1da177e4
LT		 5765 break;
5766 }
5767
5768 mac_status = tr32(MAC_STATUS);
5769 if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
953c96e0 5770 current_link_up = false;
3d3ebe74
MC		 5771 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
5772 tp->serdes_counter == 0) {
1da177e4
LT		 5773 tw32_f(MAC_MODE, (tp->mac_mode |
5774 MAC_MODE_SEND_CONFIGS));
5775 udelay(1);
5776 tw32_f(MAC_MODE, tp->mac_mode);
5777 }
5778 }
5779
953c96e0 5780 if (current_link_up) {
1da177e4
LT		 5781 tp->link_config.active_speed = SPEED_1000;
5782 tp->link_config.active_duplex = DUPLEX_FULL;
5783 tw32(MAC_LED_CTRL, (tp->led_ctrl |
5784 LED_CTRL_LNKLED_OVERRIDE |
5785 LED_CTRL_1000MBPS_ON));
5786 } else {
e740522e
MC		 5787 tp->link_config.active_speed = SPEED_UNKNOWN;
5788 tp->link_config.active_duplex = DUPLEX_UNKNOWN;
1da177e4
LT		 5789 tw32(MAC_LED_CTRL, (tp->led_ctrl |
5790 LED_CTRL_LNKLED_OVERRIDE |
5791 LED_CTRL_TRAFFIC_OVERRIDE));
5792 }
5793
f4a46d1f 5794 if (!tg3_test_and_report_link_chg(tp, current_link_up)) {
8d018621 5795 u32 now_pause_cfg = tp->link_config.active_flowctrl;
1da177e4
LT		 5796 if (orig_pause_cfg != now_pause_cfg ||
5797 orig_active_speed != tp->link_config.active_speed ||
5798 orig_active_duplex != tp->link_config.active_duplex)
5799 tg3_link_report(tp);
5800 }
5801
5802 return 0;
5803}
5804
953c96e0 5805static int tg3_setup_fiber_mii_phy(struct tg3 *tp, bool force_reset)
747e8f8b 5806{
953c96e0 5807 int err = 0;
747e8f8b 5808 u32 bmsr, bmcr;
85730a63
MC		 5809 u16 current_speed = SPEED_UNKNOWN;
5810 u8 current_duplex = DUPLEX_UNKNOWN;
953c96e0 5811 bool current_link_up = false;
85730a63
MC		 5812 u32 local_adv, remote_adv, sgsr;
5813
5814 if ((tg3_asic_rev(tp) == ASIC_REV_5719 ||
5815 tg3_asic_rev(tp) == ASIC_REV_5720) &&
5816 !tg3_readphy(tp, SERDES_TG3_1000X_STATUS, &sgsr) &&
5817 (sgsr & SERDES_TG3_SGMII_MODE)) {
5818
5819 if (force_reset)
5820 tg3_phy_reset(tp);
5821
5822 tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
5823
5824 if (!(sgsr & SERDES_TG3_LINK_UP)) {
5825 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
5826 } else {
953c96e0 5827 current_link_up = true;
85730a63
MC		 5828 if (sgsr & SERDES_TG3_SPEED_1000) {
5829 current_speed = SPEED_1000;
5830 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
5831 } else if (sgsr & SERDES_TG3_SPEED_100) {
5832 current_speed = SPEED_100;
5833 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
5834 } else {
5835 current_speed = SPEED_10;
5836 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
5837 }
5838
5839 if (sgsr & SERDES_TG3_FULL_DUPLEX)
5840 current_duplex = DUPLEX_FULL;
5841 else
5842 current_duplex = DUPLEX_HALF;
5843 }
5844
5845 tw32_f(MAC_MODE, tp->mac_mode);
5846 udelay(40);
5847
5848 tg3_clear_mac_status(tp);
5849
5850 goto fiber_setup_done;
5851 }
747e8f8b
MC		 5852
5853 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
5854 tw32_f(MAC_MODE, tp->mac_mode);
5855 udelay(40);
5856
3310e248 5857 tg3_clear_mac_status(tp);
747e8f8b
MC		 5858
5859 if (force_reset)
5860 tg3_phy_reset(tp);
5861
859edb26 5862 tp->link_config.rmt_adv = 0;
747e8f8b
MC		 5863
5864 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
5865 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4153577a 5866 if (tg3_asic_rev(tp) == ASIC_REV_5714) {
d4d2c558
MC		 5867 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
5868 bmsr |= BMSR_LSTATUS;
5869 else
5870 bmsr &= ~BMSR_LSTATUS;
5871 }
747e8f8b
MC		 5872
5873 err |= tg3_readphy(tp, MII_BMCR, &bmcr);
5874
5875 if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
f07e9af3 5876 (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) {
747e8f8b
MC		 5877 /* do nothing, just check for link up at the end */
5878 } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
28011cf1 5879 u32 adv, newadv;
747e8f8b
MC		 5880
5881 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
28011cf1
MC		 5882 newadv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
5883 ADVERTISE_1000XPAUSE |
5884 ADVERTISE_1000XPSE_ASYM |
5885 ADVERTISE_SLCT);
747e8f8b 5886
28011cf1 5887 newadv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
37f07023 5888 newadv |= ethtool_adv_to_mii_adv_x(tp->link_config.advertising);
747e8f8b 5889
28011cf1
MC		 5890 if ((newadv != adv) || !(bmcr & BMCR_ANENABLE)) {
5891 tg3_writephy(tp, MII_ADVERTISE, newadv);
747e8f8b
MC		 5892 bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
5893 tg3_writephy(tp, MII_BMCR, bmcr);
5894
5895 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3d3ebe74 5896 tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
f07e9af3 5897 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
747e8f8b
MC		 5898
5899 return err;
5900 }
5901 } else {
5902 u32 new_bmcr;
5903
5904 bmcr &= ~BMCR_SPEED1000;
5905 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
5906
5907 if (tp->link_config.duplex == DUPLEX_FULL)
5908 new_bmcr |= BMCR_FULLDPLX;
5909
5910 if (new_bmcr != bmcr) {
5911 /* BMCR_SPEED1000 is a reserved bit that needs
5912 * to be set on write.
5913 */
5914 new_bmcr |= BMCR_SPEED1000;
5915
5916 /* Force a linkdown */
f4a46d1f 5917 if (tp->link_up) {
747e8f8b
MC		 5918 u32 adv;
5919
5920 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
5921 adv &= ~(ADVERTISE_1000XFULL |
5922 ADVERTISE_1000XHALF |
5923 ADVERTISE_SLCT);
5924 tg3_writephy(tp, MII_ADVERTISE, adv);
5925 tg3_writephy(tp, MII_BMCR, bmcr |
5926 BMCR_ANRESTART |
5927 BMCR_ANENABLE);
5928 udelay(10);
f4a46d1f 5929 tg3_carrier_off(tp);
747e8f8b
MC		 5930 }
5931 tg3_writephy(tp, MII_BMCR, new_bmcr);
5932 bmcr = new_bmcr;
5933 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
5934 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4153577a 5935 if (tg3_asic_rev(tp) == ASIC_REV_5714) {
d4d2c558
MC		 5936 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
5937 bmsr |= BMSR_LSTATUS;
5938 else
5939 bmsr &= ~BMSR_LSTATUS;
5940 }
f07e9af3 5941 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
747e8f8b
MC		 5942 }
5943 }
5944
5945 if (bmsr & BMSR_LSTATUS) {
5946 current_speed = SPEED_1000;
953c96e0 5947 current_link_up = true;
747e8f8b
MC		 5948 if (bmcr & BMCR_FULLDPLX)
5949 current_duplex = DUPLEX_FULL;
5950 else
5951 current_duplex = DUPLEX_HALF;
5952
ef167e27
MC		 5953 local_adv = 0;
5954 remote_adv = 0;
5955
747e8f8b 5956 if (bmcr & BMCR_ANENABLE) {
ef167e27 5957 u32 common;
747e8f8b
MC		 5958
5959 err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
5960 err |= tg3_readphy(tp, MII_LPA, &remote_adv);
5961 common = local_adv & remote_adv;
5962 if (common & (ADVERTISE_1000XHALF |
5963 ADVERTISE_1000XFULL)) {
5964 if (common & ADVERTISE_1000XFULL)
5965 current_duplex = DUPLEX_FULL;
5966 else
5967 current_duplex = DUPLEX_HALF;
859edb26
MC		 5968
5969 tp->link_config.rmt_adv =
5970 mii_adv_to_ethtool_adv_x(remote_adv);
63c3a66f 5971 } else if (!tg3_flag(tp, 5780_CLASS)) {
57d8b880 5972 /* Link is up via parallel detect */
859a5887 5973 } else {
953c96e0 5974 current_link_up = false;
859a5887 5975 }
747e8f8b
MC		 5976 }
5977 }
5978
85730a63 5979fiber_setup_done:
953c96e0 5980 if (current_link_up && current_duplex == DUPLEX_FULL)
ef167e27
MC		 5981 tg3_setup_flow_control(tp, local_adv, remote_adv);
5982
747e8f8b
MC		 5983 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
5984 if (tp->link_config.active_duplex == DUPLEX_HALF)
5985 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
5986
5987 tw32_f(MAC_MODE, tp->mac_mode);
5988 udelay(40);
5989
5990 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
5991
5992 tp->link_config.active_speed = current_speed;
5993 tp->link_config.active_duplex = current_duplex;
5994
f4a46d1f 5995 tg3_test_and_report_link_chg(tp, current_link_up);
747e8f8b
MC		 5996 return err;
5997}
5998
5999static void tg3_serdes_parallel_detect(struct tg3 *tp)
6000{
3d3ebe74 6001 if (tp->serdes_counter) {
747e8f8b 6002 /* Give autoneg time to complete. */
3d3ebe74 6003 tp->serdes_counter--;
747e8f8b
MC		 6004 return;
6005 }
c6cdf436 6006
f4a46d1f 6007 if (!tp->link_up &&
747e8f8b
MC		 6008 (tp->link_config.autoneg == AUTONEG_ENABLE)) {
6009 u32 bmcr;
6010
6011 tg3_readphy(tp, MII_BMCR, &bmcr);
6012 if (bmcr & BMCR_ANENABLE) {
6013 u32 phy1, phy2;
6014
6015 /* Select shadow register 0x1f */
f08aa1a8
MC		 6016 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x7c00);
6017 tg3_readphy(tp, MII_TG3_MISC_SHDW, &phy1);
747e8f8b
MC		 6018
6019 /* Select expansion interrupt status register */
f08aa1a8
MC		 6020 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
6021 MII_TG3_DSP_EXP1_INT_STAT);
6022 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
6023 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
747e8f8b
MC		 6024
6025 if ((phy1 & 0x10) && !(phy2 & 0x20)) {
6026 /* We have signal detect and not receiving
6027 * config code words, link is up by parallel
6028 * detection.
6029 */
6030
6031 bmcr &= ~BMCR_ANENABLE;
6032 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
6033 tg3_writephy(tp, MII_BMCR, bmcr);
f07e9af3 6034 tp->phy_flags |= TG3_PHYFLG_PARALLEL_DETECT;
747e8f8b
MC		 6035 }
6036 }
f4a46d1f 6037 } else if (tp->link_up &&
859a5887 6038 (tp->link_config.autoneg == AUTONEG_ENABLE) &&
f07e9af3 6039 (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) {
747e8f8b
MC		 6040 u32 phy2;
6041
6042 /* Select expansion interrupt status register */
f08aa1a8
MC		 6043 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
6044 MII_TG3_DSP_EXP1_INT_STAT);
6045 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
747e8f8b
MC		 6046 if (phy2 & 0x20) {
6047 u32 bmcr;
6048
6049 /* Config code words received, turn on autoneg. */
6050 tg3_readphy(tp, MII_BMCR, &bmcr);
6051 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
6052
f07e9af3 6053 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
747e8f8b
MC		 6054
6055 }
6056 }
6057}
6058
953c96e0 6059static int tg3_setup_phy(struct tg3 *tp, bool force_reset)
1da177e4 6060{
f2096f94 6061 u32 val;
1da177e4
LT		 6062 int err;
6063
f07e9af3 6064 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
1da177e4 6065 err = tg3_setup_fiber_phy(tp, force_reset);
f07e9af3 6066 else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
747e8f8b 6067 err = tg3_setup_fiber_mii_phy(tp, force_reset);
859a5887 6068 else
1da177e4 6069 err = tg3_setup_copper_phy(tp, force_reset);
1da177e4 6070
4153577a 6071 if (tg3_chip_rev(tp) == CHIPREV_5784_AX) {
f2096f94 6072 u32 scale;
aa6c91fe
MC		 6073
6074 val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK;
6075 if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5)
6076 scale = 65;
6077 else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25)
6078 scale = 6;
6079 else
6080 scale = 12;
6081
6082 val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK;
6083 val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT);
6084 tw32(GRC_MISC_CFG, val);
6085 }
6086
f2096f94
MC		 6087 val = (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
6088 (6 << TX_LENGTHS_IPG_SHIFT);
4153577a
JP		 6089 if (tg3_asic_rev(tp) == ASIC_REV_5720 ||
6090 tg3_asic_rev(tp) == ASIC_REV_5762)
f2096f94
MC		 6091 val |= tr32(MAC_TX_LENGTHS) &
6092 (TX_LENGTHS_JMB_FRM_LEN_MSK |
6093 TX_LENGTHS_CNT_DWN_VAL_MSK);
6094
1da177e4
LT		 6095 if (tp->link_config.active_speed == SPEED_1000 &&
6096 tp->link_config.active_duplex == DUPLEX_HALF)
f2096f94
MC		 6097 tw32(MAC_TX_LENGTHS, val |
6098 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT));
1da177e4 6099 else
f2096f94
MC		 6100 tw32(MAC_TX_LENGTHS, val |
6101 (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
1da177e4 6102
63c3a66f 6103 if (!tg3_flag(tp, 5705_PLUS)) {
f4a46d1f 6104 if (tp->link_up) {
1da177e4 6105 tw32(HOSTCC_STAT_COAL_TICKS,
15f9850d 6106 tp->coal.stats_block_coalesce_usecs);
1da177e4
LT		 6107 } else {
6108 tw32(HOSTCC_STAT_COAL_TICKS, 0);
6109 }
6110 }
6111
63c3a66f 6112 if (tg3_flag(tp, ASPM_WORKAROUND)) {
f2096f94 6113 val = tr32(PCIE_PWR_MGMT_THRESH);
f4a46d1f 6114 if (!tp->link_up)
8ed5d97e
MC		 6115 val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
6116 tp->pwrmgmt_thresh;
6117 else
6118 val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
6119 tw32(PCIE_PWR_MGMT_THRESH, val);
6120 }
6121
1da177e4
LT		 6122 return err;
6123}
6124
7d41e49a
MC		 6125/* tp->lock must be held */
6126static u64 tg3_refclk_read(struct tg3 *tp)
6127{
6128 u64 stamp = tr32(TG3_EAV_REF_CLCK_LSB);
6129 return stamp | (u64)tr32(TG3_EAV_REF_CLCK_MSB) << 32;
6130}
6131
be947307
MC		 6132/* tp->lock must be held */
6133static void tg3_refclk_write(struct tg3 *tp, u64 newval)
6134{
92e6457d
NS		 6135 u32 clock_ctl = tr32(TG3_EAV_REF_CLCK_CTL);
6136
6137 tw32(TG3_EAV_REF_CLCK_CTL, clock_ctl | TG3_EAV_REF_CLCK_CTL_STOP);
be947307
MC		 6138 tw32(TG3_EAV_REF_CLCK_LSB, newval & 0xffffffff);
6139 tw32(TG3_EAV_REF_CLCK_MSB, newval >> 32);
92e6457d 6140 tw32_f(TG3_EAV_REF_CLCK_CTL, clock_ctl | TG3_EAV_REF_CLCK_CTL_RESUME);
be947307
MC		 6141}
6142
7d41e49a
MC		 6143static inline void tg3_full_lock(struct tg3 *tp, int irq_sync);
6144static inline void tg3_full_unlock(struct tg3 *tp);
6145static int tg3_get_ts_info(struct net_device *dev, struct ethtool_ts_info *info)
6146{
6147 struct tg3 *tp = netdev_priv(dev);
6148
6149 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE |
6150 SOF_TIMESTAMPING_RX_SOFTWARE |
f233a976
FL		 6151 SOF_TIMESTAMPING_SOFTWARE;
6152
6153 if (tg3_flag(tp, PTP_CAPABLE)) {
32e19272 6154 info->so_timestamping |= SOF_TIMESTAMPING_TX_HARDWARE |
f233a976
FL		 6155 SOF_TIMESTAMPING_RX_HARDWARE |
6156 SOF_TIMESTAMPING_RAW_HARDWARE;
6157 }
7d41e49a
MC		 6158
6159 if (tp->ptp_clock)
6160 info->phc_index = ptp_clock_index(tp->ptp_clock);
6161 else
6162 info->phc_index = -1;
6163
6164 info->tx_types = (1 << HWTSTAMP_TX_OFF) | (1 << HWTSTAMP_TX_ON);
6165
6166 info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) |
6167 (1 << HWTSTAMP_FILTER_PTP_V1_L4_EVENT) |
6168 (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) |
6169 (1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT);
6170 return 0;
6171}
6172
6173static int tg3_ptp_adjfreq(struct ptp_clock_info *ptp, s32 ppb)
6174{
6175 struct tg3 *tp = container_of(ptp, struct tg3, ptp_info);
6176 bool neg_adj = false;
6177 u32 correction = 0;
6178
6179 if (ppb < 0) {
6180 neg_adj = true;
6181 ppb = -ppb;
6182 }
6183
6184 /* Frequency adjustment is performed using hardware with a 24 bit
6185 * accumulator and a programmable correction value. On each clk, the
6186 * correction value gets added to the accumulator and when it
6187 * overflows, the time counter is incremented/decremented.
6188 *
6189 * So conversion from ppb to correction value is
6190 * ppb * (1 << 24) / 1000000000
6191 */
6192 correction = div_u64((u64)ppb * (1 << 24), 1000000000ULL) &
6193 TG3_EAV_REF_CLK_CORRECT_MASK;
6194
6195 tg3_full_lock(tp, 0);
6196
6197 if (correction)
6198 tw32(TG3_EAV_REF_CLK_CORRECT_CTL,
6199 TG3_EAV_REF_CLK_CORRECT_EN |
6200 (neg_adj ? TG3_EAV_REF_CLK_CORRECT_NEG : 0) | correction);
6201 else
6202 tw32(TG3_EAV_REF_CLK_CORRECT_CTL, 0);
6203
6204 tg3_full_unlock(tp);
6205
6206 return 0;
6207}
6208
6209static int tg3_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta)
6210{
6211 struct tg3 *tp = container_of(ptp, struct tg3, ptp_info);
6212
6213 tg3_full_lock(tp, 0);
6214 tp->ptp_adjust += delta;
6215 tg3_full_unlock(tp);
6216
6217 return 0;
6218}
6219
6220static int tg3_ptp_gettime(struct ptp_clock_info *ptp, struct timespec *ts)
6221{
6222 u64 ns;
6223 u32 remainder;
6224 struct tg3 *tp = container_of(ptp, struct tg3, ptp_info);
6225
6226 tg3_full_lock(tp, 0);
6227 ns = tg3_refclk_read(tp);
6228 ns += tp->ptp_adjust;
6229 tg3_full_unlock(tp);
6230
6231 ts->tv_sec = div_u64_rem(ns, 1000000000, &remainder);
6232 ts->tv_nsec = remainder;
6233
6234 return 0;
6235}
6236
6237static int tg3_ptp_settime(struct ptp_clock_info *ptp,
6238 const struct timespec *ts)
6239{
6240 u64 ns;
6241 struct tg3 *tp = container_of(ptp, struct tg3, ptp_info);
6242
6243 ns = timespec_to_ns(ts);
6244
6245 tg3_full_lock(tp, 0);
6246 tg3_refclk_write(tp, ns);
6247 tp->ptp_adjust = 0;
6248 tg3_full_unlock(tp);
6249
6250 return 0;
6251}
6252
6253static int tg3_ptp_enable(struct ptp_clock_info *ptp,
6254 struct ptp_clock_request *rq, int on)
6255{
92e6457d
NS		 6256 struct tg3 *tp = container_of(ptp, struct tg3, ptp_info);
6257 u32 clock_ctl;
6258 int rval = 0;
6259
6260 switch (rq->type) {
6261 case PTP_CLK_REQ_PEROUT:
6262 if (rq->perout.index != 0)
6263 return -EINVAL;
6264
6265 tg3_full_lock(tp, 0);
6266 clock_ctl = tr32(TG3_EAV_REF_CLCK_CTL);
6267 clock_ctl &= ~TG3_EAV_CTL_TSYNC_GPIO_MASK;
6268
6269 if (on) {
6270 u64 nsec;
6271
6272 nsec = rq->perout.start.sec * 1000000000ULL +
6273 rq->perout.start.nsec;
6274
6275 if (rq->perout.period.sec || rq->perout.period.nsec) {
6276 netdev_warn(tp->dev,
6277 "Device supports only a one-shot timesync output, period must be 0\n");
6278 rval = -EINVAL;
6279 goto err_out;
6280 }
6281
6282 if (nsec & (1ULL << 63)) {
6283 netdev_warn(tp->dev,
6284 "Start value (nsec) is over limit. Maximum size of start is only 63 bits\n");
6285 rval = -EINVAL;
6286 goto err_out;
6287 }
6288
6289 tw32(TG3_EAV_WATCHDOG0_LSB, (nsec & 0xffffffff));
6290 tw32(TG3_EAV_WATCHDOG0_MSB,
6291 TG3_EAV_WATCHDOG0_EN |
6292 ((nsec >> 32) & TG3_EAV_WATCHDOG_MSB_MASK));
6293
6294 tw32(TG3_EAV_REF_CLCK_CTL,
6295 clock_ctl | TG3_EAV_CTL_TSYNC_WDOG0);
6296 } else {
6297 tw32(TG3_EAV_WATCHDOG0_MSB, 0);
6298 tw32(TG3_EAV_REF_CLCK_CTL, clock_ctl);
6299 }
6300
6301err_out:
6302 tg3_full_unlock(tp);
6303 return rval;
6304
6305 default:
6306 break;
6307 }
6308
7d41e49a
MC		 6309 return -EOPNOTSUPP;
6310}
6311
6312static const struct ptp_clock_info tg3_ptp_caps = {
6313 .owner = THIS_MODULE,
6314 .name = "tg3 clock",
6315 .max_adj = 250000000,
6316 .n_alarm = 0,
6317 .n_ext_ts = 0,
92e6457d 6318 .n_per_out = 1,
4986b4f0 6319 .n_pins = 0,
7d41e49a
MC		 6320 .pps = 0,
6321 .adjfreq = tg3_ptp_adjfreq,
6322 .adjtime = tg3_ptp_adjtime,
6323 .gettime = tg3_ptp_gettime,
6324 .settime = tg3_ptp_settime,
6325 .enable = tg3_ptp_enable,
6326};
6327
fb4ce8ad
MC		 6328static void tg3_hwclock_to_timestamp(struct tg3 *tp, u64 hwclock,
6329 struct skb_shared_hwtstamps *timestamp)
6330{
6331 memset(timestamp, 0, sizeof(struct skb_shared_hwtstamps));
6332 timestamp->hwtstamp = ns_to_ktime((hwclock & TG3_TSTAMP_MASK) +
6333 tp->ptp_adjust);
6334}
6335
be947307
MC		 6336/* tp->lock must be held */
6337static void tg3_ptp_init(struct tg3 *tp)
6338{
6339 if (!tg3_flag(tp, PTP_CAPABLE))
6340 return;
6341
6342 /* Initialize the hardware clock to the system time. */
6343 tg3_refclk_write(tp, ktime_to_ns(ktime_get_real()));
6344 tp->ptp_adjust = 0;
7d41e49a 6345 tp->ptp_info = tg3_ptp_caps;
be947307
MC		 6346}
6347
6348/* tp->lock must be held */
6349static void tg3_ptp_resume(struct tg3 *tp)
6350{
6351 if (!tg3_flag(tp, PTP_CAPABLE))
6352 return;
6353
6354 tg3_refclk_write(tp, ktime_to_ns(ktime_get_real()) + tp->ptp_adjust);
6355 tp->ptp_adjust = 0;
6356}
6357
6358static void tg3_ptp_fini(struct tg3 *tp)
6359{
6360 if (!tg3_flag(tp, PTP_CAPABLE) || !tp->ptp_clock)
6361 return;
6362
7d41e49a 6363 ptp_clock_unregister(tp->ptp_clock);
be947307
MC		 6364 tp->ptp_clock = NULL;
6365 tp->ptp_adjust = 0;
6366}
6367
66cfd1bd
MC		 6368static inline int tg3_irq_sync(struct tg3 *tp)
6369{
6370 return tp->irq_sync;
6371}
6372
97bd8e49
MC		 6373static inline void tg3_rd32_loop(struct tg3 *tp, u32 *dst, u32 off, u32 len)
6374{
6375 int i;
6376
6377 dst = (u32 *)((u8 *)dst + off);
6378 for (i = 0; i < len; i += sizeof(u32))
6379 *dst++ = tr32(off + i);
6380}
6381
6382static void tg3_dump_legacy_regs(struct tg3 *tp, u32 *regs)
6383{
6384 tg3_rd32_loop(tp, regs, TG3PCI_VENDOR, 0xb0);
6385 tg3_rd32_loop(tp, regs, MAILBOX_INTERRUPT_0, 0x200);
6386 tg3_rd32_loop(tp, regs, MAC_MODE, 0x4f0);
6387 tg3_rd32_loop(tp, regs, SNDDATAI_MODE, 0xe0);
6388 tg3_rd32_loop(tp, regs, SNDDATAC_MODE, 0x04);
6389 tg3_rd32_loop(tp, regs, SNDBDS_MODE, 0x80);
6390 tg3_rd32_loop(tp, regs, SNDBDI_MODE, 0x48);
6391 tg3_rd32_loop(tp, regs, SNDBDC_MODE, 0x04);
6392 tg3_rd32_loop(tp, regs, RCVLPC_MODE, 0x20);
6393 tg3_rd32_loop(tp, regs, RCVLPC_SELLST_BASE, 0x15c);
6394 tg3_rd32_loop(tp, regs, RCVDBDI_MODE, 0x0c);
6395 tg3_rd32_loop(tp, regs, RCVDBDI_JUMBO_BD, 0x3c);
6396 tg3_rd32_loop(tp, regs, RCVDBDI_BD_PROD_IDX_0, 0x44);
6397 tg3_rd32_loop(tp, regs, RCVDCC_MODE, 0x04);
6398 tg3_rd32_loop(tp, regs, RCVBDI_MODE, 0x20);
6399 tg3_rd32_loop(tp, regs, RCVCC_MODE, 0x14);
6400 tg3_rd32_loop(tp, regs, RCVLSC_MODE, 0x08);
6401 tg3_rd32_loop(tp, regs, MBFREE_MODE, 0x08);
6402 tg3_rd32_loop(tp, regs, HOSTCC_MODE, 0x100);
6403
63c3a66f 6404 if (tg3_flag(tp, SUPPORT_MSIX))
97bd8e49
MC		 6405 tg3_rd32_loop(tp, regs, HOSTCC_RXCOL_TICKS_VEC1, 0x180);
6406
6407 tg3_rd32_loop(tp, regs, MEMARB_MODE, 0x10);
6408 tg3_rd32_loop(tp, regs, BUFMGR_MODE, 0x58);
6409 tg3_rd32_loop(tp, regs, RDMAC_MODE, 0x08);
6410 tg3_rd32_loop(tp, regs, WDMAC_MODE, 0x08);
6411 tg3_rd32_loop(tp, regs, RX_CPU_MODE, 0x04);
6412 tg3_rd32_loop(tp, regs, RX_CPU_STATE, 0x04);
6413 tg3_rd32_loop(tp, regs, RX_CPU_PGMCTR, 0x04);
6414 tg3_rd32_loop(tp, regs, RX_CPU_HWBKPT, 0x04);
6415
63c3a66f 6416 if (!tg3_flag(tp, 5705_PLUS)) {
97bd8e49
MC		 6417 tg3_rd32_loop(tp, regs, TX_CPU_MODE, 0x04);
6418 tg3_rd32_loop(tp, regs, TX_CPU_STATE, 0x04);
6419 tg3_rd32_loop(tp, regs, TX_CPU_PGMCTR, 0x04);
6420 }
6421
6422 tg3_rd32_loop(tp, regs, GRCMBOX_INTERRUPT_0, 0x110);
6423 tg3_rd32_loop(tp, regs, FTQ_RESET, 0x120);
6424 tg3_rd32_loop(tp, regs, MSGINT_MODE, 0x0c);
6425 tg3_rd32_loop(tp, regs, DMAC_MODE, 0x04);
6426 tg3_rd32_loop(tp, regs, GRC_MODE, 0x4c);
6427
63c3a66f 6428 if (tg3_flag(tp, NVRAM))
97bd8e49
MC		 6429 tg3_rd32_loop(tp, regs, NVRAM_CMD, 0x24);
6430}
6431
6432static void tg3_dump_state(struct tg3 *tp)
6433{
6434 int i;
6435 u32 *regs;
6436
6437 regs = kzalloc(TG3_REG_BLK_SIZE, GFP_ATOMIC);
b2adaca9 6438 if (!regs)
97bd8e49 6439 return;
97bd8e49 6440
63c3a66f 6441 if (tg3_flag(tp, PCI_EXPRESS)) {
97bd8e49
MC		 6442 /* Read up to but not including private PCI registers */
6443 for (i = 0; i < TG3_PCIE_TLDLPL_PORT; i += sizeof(u32))
6444 regs[i / sizeof(u32)] = tr32(i);
6445 } else
6446 tg3_dump_legacy_regs(tp, regs);
6447
6448 for (i = 0; i < TG3_REG_BLK_SIZE / sizeof(u32); i += 4) {
6449 if (!regs[i + 0] && !regs[i + 1] &&
6450 !regs[i + 2] && !regs[i + 3])
6451 continue;
6452
6453 netdev_err(tp->dev, "0x%08x: 0x%08x, 0x%08x, 0x%08x, 0x%08x\n",
6454 i * 4,
6455 regs[i + 0], regs[i + 1], regs[i + 2], regs[i + 3]);
6456 }
6457
6458 kfree(regs);
6459
6460 for (i = 0; i < tp->irq_cnt; i++) {
6461 struct tg3_napi *tnapi = &tp->napi[i];
6462
6463 /* SW status block */
6464 netdev_err(tp->dev,
6465 "%d: Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n",
6466 i,
6467 tnapi->hw_status->status,
6468 tnapi->hw_status->status_tag,
6469 tnapi->hw_status->rx_jumbo_consumer,
6470 tnapi->hw_status->rx_consumer,
6471 tnapi->hw_status->rx_mini_consumer,
6472 tnapi->hw_status->idx[0].rx_producer,
6473 tnapi->hw_status->idx[0].tx_consumer);
6474
6475 netdev_err(tp->dev,
6476 "%d: NAPI info [%08x:%08x:(%04x:%04x:%04x):%04x:(%04x:%04x:%04x:%04x)]\n",
6477 i,
6478 tnapi->last_tag, tnapi->last_irq_tag,
6479 tnapi->tx_prod, tnapi->tx_cons, tnapi->tx_pending,
6480 tnapi->rx_rcb_ptr,
6481 tnapi->prodring.rx_std_prod_idx,
6482 tnapi->prodring.rx_std_cons_idx,
6483 tnapi->prodring.rx_jmb_prod_idx,
6484 tnapi->prodring.rx_jmb_cons_idx);
6485 }
6486}
6487
df3e6548
MC		 6488/* This is called whenever we suspect that the system chipset is re-
6489 * ordering the sequence of MMIO to the tx send mailbox. The symptom
6490 * is bogus tx completions. We try to recover by setting the
6491 * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
6492 * in the workqueue.
6493 */
6494static void tg3_tx_recover(struct tg3 *tp)
6495{
63c3a66f 6496 BUG_ON(tg3_flag(tp, MBOX_WRITE_REORDER) ||
df3e6548
MC		 6497 tp->write32_tx_mbox == tg3_write_indirect_mbox);
6498
5129c3a3
MC		 6499 netdev_warn(tp->dev,
6500 "The system may be re-ordering memory-mapped I/O "
6501 "cycles to the network device, attempting to recover. "
6502 "Please report the problem to the driver maintainer "
6503 "and include system chipset information.\n");
df3e6548 6504
63c3a66f 6505 tg3_flag_set(tp, TX_RECOVERY_PENDING);
df3e6548
MC		 6506}
6507
f3f3f27e 6508static inline u32 tg3_tx_avail(struct tg3_napi *tnapi)
1b2a7205 6509{
f65aac16
MC		 6510 /* Tell compiler to fetch tx indices from memory. */
6511 barrier();
f3f3f27e
MC		 6512 return tnapi->tx_pending -
6513 ((tnapi->tx_prod - tnapi->tx_cons) & (TG3_TX_RING_SIZE - 1));
1b2a7205
MC		 6514}
6515
1da177e4
LT		 6516/* Tigon3 never reports partial packet sends. So we do not
6517 * need special logic to handle SKBs that have not had all
6518 * of their frags sent yet, like SunGEM does.
6519 */
17375d25 6520static void tg3_tx(struct tg3_napi *tnapi)
1da177e4 6521{
17375d25 6522 struct tg3 *tp = tnapi->tp;
898a56f8 6523 u32 hw_idx = tnapi->hw_status->idx[0].tx_consumer;
f3f3f27e 6524 u32 sw_idx = tnapi->tx_cons;
fe5f5787
MC		 6525 struct netdev_queue *txq;
6526 int index = tnapi - tp->napi;
298376d3 6527 unsigned int pkts_compl = 0, bytes_compl = 0;
fe5f5787 6528
63c3a66f 6529 if (tg3_flag(tp, ENABLE_TSS))
fe5f5787
MC		 6530 index--;
6531
6532 txq = netdev_get_tx_queue(tp->dev, index);
1da177e4
LT		 6533
6534 while (sw_idx != hw_idx) {
df8944cf 6535 struct tg3_tx_ring_info *ri = &tnapi->tx_buffers[sw_idx];
1da177e4 6536 struct sk_buff *skb = ri->skb;
df3e6548
MC		 6537 int i, tx_bug = 0;
6538
6539 if (unlikely(skb == NULL)) {
6540 tg3_tx_recover(tp);
6541 return;
6542 }
1da177e4 6543
fb4ce8ad
MC		 6544 if (tnapi->tx_ring[sw_idx].len_flags & TXD_FLAG_HWTSTAMP) {
6545 struct skb_shared_hwtstamps timestamp;
6546 u64 hwclock = tr32(TG3_TX_TSTAMP_LSB);
6547 hwclock |= (u64)tr32(TG3_TX_TSTAMP_MSB) << 32;
6548
6549 tg3_hwclock_to_timestamp(tp, hwclock, &timestamp);
6550
6551 skb_tstamp_tx(skb, &timestamp);
6552 }
6553
f4188d8a 6554 pci_unmap_single(tp->pdev,
4e5e4f0d 6555 dma_unmap_addr(ri, mapping),
f4188d8a
AD		 6556 skb_headlen(skb),
6557 PCI_DMA_TODEVICE);
1da177e4
LT		 6558
6559 ri->skb = NULL;
6560
e01ee14d
MC		 6561 while (ri->fragmented) {
6562 ri->fragmented = false;
6563 sw_idx = NEXT_TX(sw_idx);
6564 ri = &tnapi->tx_buffers[sw_idx];
6565 }
6566
1da177e4
LT		 6567 sw_idx = NEXT_TX(sw_idx);
6568
6569 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
f3f3f27e 6570 ri = &tnapi->tx_buffers[sw_idx];
df3e6548
MC		 6571 if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
6572 tx_bug = 1;
f4188d8a
AD		 6573
6574 pci_unmap_page(tp->pdev,
4e5e4f0d 6575 dma_unmap_addr(ri, mapping),
9e903e08 6576 skb_frag_size(&skb_shinfo(skb)->frags[i]),
f4188d8a 6577 PCI_DMA_TODEVICE);
e01ee14d
MC		 6578
6579 while (ri->fragmented) {
6580 ri->fragmented = false;
6581 sw_idx = NEXT_TX(sw_idx);
6582 ri = &tnapi->tx_buffers[sw_idx];
6583 }
6584
1da177e4
LT		 6585 sw_idx = NEXT_TX(sw_idx);
6586 }
6587
298376d3
TH		 6588 pkts_compl++;
6589 bytes_compl += skb->len;
6590
497a27b9 6591 dev_kfree_skb_any(skb);
df3e6548
MC		 6592
6593 if (unlikely(tx_bug)) {
6594 tg3_tx_recover(tp);
6595 return;
6596 }
1da177e4
LT		 6597 }
6598
5cb917bc 6599 netdev_tx_completed_queue(txq, pkts_compl, bytes_compl);
298376d3 6600
f3f3f27e 6601 tnapi->tx_cons = sw_idx;
1da177e4 6602
1b2a7205
MC		 6603 /* Need to make the tx_cons update visible to tg3_start_xmit()
6604 * before checking for netif_queue_stopped(). Without the
6605 * memory barrier, there is a small possibility that tg3_start_xmit()
6606 * will miss it and cause the queue to be stopped forever.
6607 */
6608 smp_mb();
6609
fe5f5787 6610 if (unlikely(netif_tx_queue_stopped(txq) &&
f3f3f27e 6611 (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))) {
fe5f5787
MC		 6612 __netif_tx_lock(txq, smp_processor_id());
6613 if (netif_tx_queue_stopped(txq) &&
f3f3f27e 6614 (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))
fe5f5787
MC		 6615 netif_tx_wake_queue(txq);
6616 __netif_tx_unlock(txq);
51b91468 6617 }
1da177e4
LT		 6618}
6619
8d4057a9
ED		 6620static void tg3_frag_free(bool is_frag, void *data)
6621{
6622 if (is_frag)
6623 put_page(virt_to_head_page(data));
6624 else
6625 kfree(data);
6626}
6627
9205fd9c 6628static void tg3_rx_data_free(struct tg3 *tp, struct ring_info *ri, u32 map_sz)
2b2cdb65 6629{
8d4057a9
ED		 6630 unsigned int skb_size = SKB_DATA_ALIGN(map_sz + TG3_RX_OFFSET(tp)) +
6631 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
6632
9205fd9c 6633 if (!ri->data)
2b2cdb65
MC		 6634 return;
6635
4e5e4f0d 6636 pci_unmap_single(tp->pdev, dma_unmap_addr(ri, mapping),
2b2cdb65 6637 map_sz, PCI_DMA_FROMDEVICE);
a1e8b307 6638 tg3_frag_free(skb_size <= PAGE_SIZE, ri->data);
9205fd9c 6639 ri->data = NULL;
2b2cdb65
MC		 6640}
6641
8d4057a9 6642
1da177e4
LT		 6643/* Returns size of skb allocated or < 0 on error.
6644 *
6645 * We only need to fill in the address because the other members
6646 * of the RX descriptor are invariant, see tg3_init_rings.
6647 *
6648 * Note the purposeful assymetry of cpu vs. chip accesses. For
6649 * posting buffers we only dirty the first cache line of the RX
6650 * descriptor (containing the address). Whereas for the RX status
6651 * buffers the cpu only reads the last cacheline of the RX descriptor
6652 * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
6653 */
9205fd9c 6654static int tg3_alloc_rx_data(struct tg3 *tp, struct tg3_rx_prodring_set *tpr,
8d4057a9
ED		 6655 u32 opaque_key, u32 dest_idx_unmasked,
6656 unsigned int *frag_size)
1da177e4
LT		 6657{
6658 struct tg3_rx_buffer_desc *desc;
f94e290e 6659 struct ring_info *map;
9205fd9c 6660 u8 *data;
1da177e4 6661 dma_addr_t mapping;
9205fd9c 6662 int skb_size, data_size, dest_idx;
1da177e4 6663
1da177e4
LT		 6664 switch (opaque_key) {
6665 case RXD_OPAQUE_RING_STD:
2c49a44d 6666 dest_idx = dest_idx_unmasked & tp->rx_std_ring_mask;
21f581a5
MC		 6667 desc = &tpr->rx_std[dest_idx];
6668 map = &tpr->rx_std_buffers[dest_idx];
9205fd9c 6669 data_size = tp->rx_pkt_map_sz;
1da177e4
LT		 6670 break;
6671
6672 case RXD_OPAQUE_RING_JUMBO:
2c49a44d 6673 dest_idx = dest_idx_unmasked & tp->rx_jmb_ring_mask;
79ed5ac7 6674 desc = &tpr->rx_jmb[dest_idx].std;
21f581a5 6675 map = &tpr->rx_jmb_buffers[dest_idx];
9205fd9c 6676 data_size = TG3_RX_JMB_MAP_SZ;
1da177e4
LT		 6677 break;
6678
6679 default:
6680 return -EINVAL;
855e1111 6681 }
1da177e4
LT		 6682
6683 /* Do not overwrite any of the map or rp information
6684 * until we are sure we can commit to a new buffer.
6685 *
6686 * Callers depend upon this behavior and assume that
6687 * we leave everything unchanged if we fail.
6688 */
9205fd9c
ED		 6689 skb_size = SKB_DATA_ALIGN(data_size + TG3_RX_OFFSET(tp)) +
6690 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
a1e8b307
ED		 6691 if (skb_size <= PAGE_SIZE) {
6692 data = netdev_alloc_frag(skb_size);
6693 *frag_size = skb_size;
8d4057a9
ED		 6694 } else {
6695 data = kmalloc(skb_size, GFP_ATOMIC);
6696 *frag_size = 0;
6697 }
9205fd9c 6698 if (!data)
1da177e4
LT		 6699 return -ENOMEM;
6700
9205fd9c
ED		 6701 mapping = pci_map_single(tp->pdev,
6702 data + TG3_RX_OFFSET(tp),
6703 data_size,
1da177e4 6704 PCI_DMA_FROMDEVICE);
8d4057a9 6705 if (unlikely(pci_dma_mapping_error(tp->pdev, mapping))) {
a1e8b307 6706 tg3_frag_free(skb_size <= PAGE_SIZE, data);
a21771dd
MC		 6707 return -EIO;
6708 }
1da177e4 6709
9205fd9c 6710 map->data = data;
4e5e4f0d 6711 dma_unmap_addr_set(map, mapping, mapping);
1da177e4 6712
1da177e4
LT		 6713 desc->addr_hi = ((u64)mapping >> 32);
6714 desc->addr_lo = ((u64)mapping & 0xffffffff);
6715
9205fd9c 6716 return data_size;
1da177e4
LT		 6717}
6718
6719/* We only need to move over in the address because the other
6720 * members of the RX descriptor are invariant. See notes above
9205fd9c 6721 * tg3_alloc_rx_data for full details.
1da177e4 6722 */
a3896167
MC		 6723static void tg3_recycle_rx(struct tg3_napi *tnapi,
6724 struct tg3_rx_prodring_set *dpr,
6725 u32 opaque_key, int src_idx,
6726 u32 dest_idx_unmasked)
1da177e4 6727{
17375d25 6728 struct tg3 *tp = tnapi->tp;
1da177e4
LT		 6729 struct tg3_rx_buffer_desc *src_desc, *dest_desc;
6730 struct ring_info *src_map, *dest_map;
8fea32b9 6731 struct tg3_rx_prodring_set *spr = &tp->napi[0].prodring;
c6cdf436 6732 int dest_idx;
1da177e4
LT		 6733
6734 switch (opaque_key) {
6735 case RXD_OPAQUE_RING_STD:
2c49a44d 6736 dest_idx = dest_idx_unmasked & tp->rx_std_ring_mask;
a3896167
MC		 6737 dest_desc = &dpr->rx_std[dest_idx];
6738 dest_map = &dpr->rx_std_buffers[dest_idx];
6739 src_desc = &spr->rx_std[src_idx];
6740 src_map = &spr->rx_std_buffers[src_idx];
1da177e4
LT		 6741 break;
6742
6743 case RXD_OPAQUE_RING_JUMBO:
2c49a44d 6744 dest_idx = dest_idx_unmasked & tp->rx_jmb_ring_mask;
a3896167
MC		 6745 dest_desc = &dpr->rx_jmb[dest_idx].std;
6746 dest_map = &dpr->rx_jmb_buffers[dest_idx];
6747 src_desc = &spr->rx_jmb[src_idx].std;
6748 src_map = &spr->rx_jmb_buffers[src_idx];
1da177e4
LT		 6749 break;
6750
6751 default:
6752 return;
855e1111 6753 }
1da177e4 6754
9205fd9c 6755 dest_map->data = src_map->data;
4e5e4f0d
FT		 6756 dma_unmap_addr_set(dest_map, mapping,
6757 dma_unmap_addr(src_map, mapping));
1da177e4
LT		 6758 dest_desc->addr_hi = src_desc->addr_hi;
6759 dest_desc->addr_lo = src_desc->addr_lo;
e92967bf
MC		 6760
6761 /* Ensure that the update to the skb happens after the physical
6762 * addresses have been transferred to the new BD location.
6763 */
6764 smp_wmb();
6765
9205fd9c 6766 src_map->data = NULL;
1da177e4
LT		 6767}
6768
1da177e4
LT		 6769/* The RX ring scheme is composed of multiple rings which post fresh
6770 * buffers to the chip, and one special ring the chip uses to report
6771 * status back to the host.
6772 *
6773 * The special ring reports the status of received packets to the
6774 * host. The chip does not write into the original descriptor the
6775 * RX buffer was obtained from. The chip simply takes the original
6776 * descriptor as provided by the host, updates the status and length
6777 * field, then writes this into the next status ring entry.
6778 *
6779 * Each ring the host uses to post buffers to the chip is described
6780 * by a TG3_BDINFO entry in the chips SRAM area. When a packet arrives,
6781 * it is first placed into the on-chip ram. When the packet's length
6782 * is known, it walks down the TG3_BDINFO entries to select the ring.
6783 * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
6784 * which is within the range of the new packet's length is chosen.
6785 *
6786 * The "separate ring for rx status" scheme may sound queer, but it makes
6787 * sense from a cache coherency perspective. If only the host writes
6788 * to the buffer post rings, and only the chip writes to the rx status
6789 * rings, then cache lines never move beyond shared-modified state.
6790 * If both the host and chip were to write into the same ring, cache line
6791 * eviction could occur since both entities want it in an exclusive state.
6792 */
17375d25 6793static int tg3_rx(struct tg3_napi *tnapi, int budget)
1da177e4 6794{
17375d25 6795 struct tg3 *tp = tnapi->tp;
f92905de 6796 u32 work_mask, rx_std_posted = 0;
4361935a 6797 u32 std_prod_idx, jmb_prod_idx;
72334482 6798 u32 sw_idx = tnapi->rx_rcb_ptr;
483ba50b 6799 u16 hw_idx;
1da177e4 6800 int received;
8fea32b9 6801 struct tg3_rx_prodring_set *tpr = &tnapi->prodring;
1da177e4 6802
8d9d7cfc 6803 hw_idx = *(tnapi->rx_rcb_prod_idx);
1da177e4
LT		 6804 /*
6805 * We need to order the read of hw_idx and the read of
6806 * the opaque cookie.
6807 */
6808 rmb();
1da177e4
LT		 6809 work_mask = 0;
6810 received = 0;
4361935a
MC		 6811 std_prod_idx = tpr->rx_std_prod_idx;
6812 jmb_prod_idx = tpr->rx_jmb_prod_idx;
1da177e4 6813 while (sw_idx != hw_idx && budget > 0) {
afc081f8 6814 struct ring_info *ri;
72334482 6815 struct tg3_rx_buffer_desc *desc = &tnapi->rx_rcb[sw_idx];
1da177e4
LT		 6816 unsigned int len;
6817 struct sk_buff *skb;
6818 dma_addr_t dma_addr;
6819 u32 opaque_key, desc_idx, *post_ptr;
9205fd9c 6820 u8 *data;
fb4ce8ad 6821 u64 tstamp = 0;
1da177e4
LT		 6822
6823 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
6824 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
6825 if (opaque_key == RXD_OPAQUE_RING_STD) {
8fea32b9 6826 ri = &tp->napi[0].prodring.rx_std_buffers[desc_idx];
4e5e4f0d 6827 dma_addr = dma_unmap_addr(ri, mapping);
9205fd9c 6828 data = ri->data;
4361935a 6829 post_ptr = &std_prod_idx;
f92905de 6830 rx_std_posted++;
1da177e4 6831 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
8fea32b9 6832 ri = &tp->napi[0].prodring.rx_jmb_buffers[desc_idx];
4e5e4f0d 6833 dma_addr = dma_unmap_addr(ri, mapping);
9205fd9c 6834 data = ri->data;
4361935a 6835 post_ptr = &jmb_prod_idx;
21f581a5 6836 } else
1da177e4 6837 goto next_pkt_nopost;
1da177e4
LT		 6838
6839 work_mask |= opaque_key;
6840
d7b95315 6841 if (desc->err_vlan & RXD_ERR_MASK) {
1da177e4 6842 drop_it:
a3896167 6843 tg3_recycle_rx(tnapi, tpr, opaque_key,
1da177e4
LT		 6844 desc_idx, *post_ptr);
6845 drop_it_no_recycle:
6846 /* Other statistics kept track of by card. */
b0057c51 6847 tp->rx_dropped++;
1da177e4
LT		 6848 goto next_pkt;
6849 }
6850
9205fd9c 6851 prefetch(data + TG3_RX_OFFSET(tp));
ad829268
MC		 6852 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) -
6853 ETH_FCS_LEN;
1da177e4 6854
fb4ce8ad
MC		 6855 if ((desc->type_flags & RXD_FLAG_PTPSTAT_MASK) ==
6856 RXD_FLAG_PTPSTAT_PTPV1 ||
6857 (desc->type_flags & RXD_FLAG_PTPSTAT_MASK) ==
6858 RXD_FLAG_PTPSTAT_PTPV2) {
6859 tstamp = tr32(TG3_RX_TSTAMP_LSB);
6860 tstamp |= (u64)tr32(TG3_RX_TSTAMP_MSB) << 32;
6861 }
6862
d2757fc4 6863 if (len > TG3_RX_COPY_THRESH(tp)) {
1da177e4 6864 int skb_size;
8d4057a9 6865 unsigned int frag_size;
1da177e4 6866
9205fd9c 6867 skb_size = tg3_alloc_rx_data(tp, tpr, opaque_key,
8d4057a9 6868 *post_ptr, &frag_size);
1da177e4
LT		 6869 if (skb_size < 0)
6870 goto drop_it;
6871
287be12e 6872 pci_unmap_single(tp->pdev, dma_addr, skb_size,
1da177e4
LT		 6873 PCI_DMA_FROMDEVICE);
6874
9205fd9c 6875 /* Ensure that the update to the data happens
61e800cf
MC		 6876 * after the usage of the old DMA mapping.
6877 */
6878 smp_wmb();
6879
9205fd9c 6880 ri->data = NULL;
61e800cf 6881
85aec73d
IV		 6882 skb = build_skb(data, frag_size);
6883 if (!skb) {
6884 tg3_frag_free(frag_size != 0, data);
6885 goto drop_it_no_recycle;
6886 }
6887 skb_reserve(skb, TG3_RX_OFFSET(tp));
1da177e4 6888 } else {
a3896167 6889 tg3_recycle_rx(tnapi, tpr, opaque_key,
1da177e4
LT		 6890 desc_idx, *post_ptr);
6891
9205fd9c
ED		 6892 skb = netdev_alloc_skb(tp->dev,
6893 len + TG3_RAW_IP_ALIGN);
6894 if (skb == NULL)
1da177e4
LT		 6895 goto drop_it_no_recycle;
6896
9205fd9c 6897 skb_reserve(skb, TG3_RAW_IP_ALIGN);
1da177e4 6898 pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
9205fd9c
ED		 6899 memcpy(skb->data,
6900 data + TG3_RX_OFFSET(tp),
6901 len);
1da177e4 6902 pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
1da177e4
LT		 6903 }
6904
9205fd9c 6905 skb_put(skb, len);
fb4ce8ad
MC		 6906 if (tstamp)
6907 tg3_hwclock_to_timestamp(tp, tstamp,
6908 skb_hwtstamps(skb));
6909
dc668910 6910 if ((tp->dev->features & NETIF_F_RXCSUM) &&
1da177e4
LT		 6911 (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
6912 (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
6913 >> RXD_TCPCSUM_SHIFT) == 0xffff))
6914 skb->ip_summed = CHECKSUM_UNNECESSARY;
6915 else
bc8acf2c 6916 skb_checksum_none_assert(skb);
1da177e4
LT		 6917
6918 skb->protocol = eth_type_trans(skb, tp->dev);
f7b493e0
MC		 6919
6920 if (len > (tp->dev->mtu + ETH_HLEN) &&
7d3083ee
VY		 6921 skb->protocol != htons(ETH_P_8021Q) &&
6922 skb->protocol != htons(ETH_P_8021AD)) {
497a27b9 6923 dev_kfree_skb_any(skb);
b0057c51 6924 goto drop_it_no_recycle;
f7b493e0
MC		 6925 }
6926
9dc7a113 6927 if (desc->type_flags & RXD_FLAG_VLAN &&
bf933c80 6928 !(tp->rx_mode & RX_MODE_KEEP_VLAN_TAG))
86a9bad3 6929 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
bf933c80 6930 desc->err_vlan & RXD_VLAN_MASK);
9dc7a113 6931
bf933c80 6932 napi_gro_receive(&tnapi->napi, skb);
1da177e4 6933
1da177e4
LT		 6934 received++;
6935 budget--;
6936
6937next_pkt:
6938 (*post_ptr)++;
f92905de
MC		 6939
6940 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
2c49a44d
MC		 6941 tpr->rx_std_prod_idx = std_prod_idx &
6942 tp->rx_std_ring_mask;
86cfe4ff
MC		 6943 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
6944 tpr->rx_std_prod_idx);
f92905de
MC		 6945 work_mask &= ~RXD_OPAQUE_RING_STD;
6946 rx_std_posted = 0;
6947 }
1da177e4 6948next_pkt_nopost:
483ba50b 6949 sw_idx++;
7cb32cf2 6950 sw_idx &= tp->rx_ret_ring_mask;
52f6d697
MC		 6951
6952 /* Refresh hw_idx to see if there is new work */
6953 if (sw_idx == hw_idx) {
8d9d7cfc 6954 hw_idx = *(tnapi->rx_rcb_prod_idx);
52f6d697
MC		 6955 rmb();
6956 }
1da177e4
LT		 6957 }
6958
6959 /* ACK the status ring. */
72334482
MC		 6960 tnapi->rx_rcb_ptr = sw_idx;
6961 tw32_rx_mbox(tnapi->consmbox, sw_idx);
1da177e4
LT		 6962
6963 /* Refill RX ring(s). */
63c3a66f 6964 if (!tg3_flag(tp, ENABLE_RSS)) {
6541b806
MC		 6965 /* Sync BD data before updating mailbox */
6966 wmb();
6967
b196c7e4 6968 if (work_mask & RXD_OPAQUE_RING_STD) {
2c49a44d
MC		 6969 tpr->rx_std_prod_idx = std_prod_idx &
6970 tp->rx_std_ring_mask;
b196c7e4
MC		 6971 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
6972 tpr->rx_std_prod_idx);
6973 }
6974 if (work_mask & RXD_OPAQUE_RING_JUMBO) {
2c49a44d
MC		 6975 tpr->rx_jmb_prod_idx = jmb_prod_idx &
6976 tp->rx_jmb_ring_mask;
b196c7e4
MC		 6977 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
6978 tpr->rx_jmb_prod_idx);
6979 }
6980 mmiowb();
6981 } else if (work_mask) {
6982 /* rx_std_buffers[] and rx_jmb_buffers[] entries must be
6983 * updated before the producer indices can be updated.
6984 */
6985 smp_wmb();
6986
2c49a44d
MC		 6987 tpr->rx_std_prod_idx = std_prod_idx & tp->rx_std_ring_mask;
6988 tpr->rx_jmb_prod_idx = jmb_prod_idx & tp->rx_jmb_ring_mask;
b196c7e4 6989
7ae52890
MC		 6990 if (tnapi != &tp->napi[1]) {
6991 tp->rx_refill = true;
e4af1af9 6992 napi_schedule(&tp->napi[1].napi);
7ae52890 6993 }
1da177e4 6994 }
1da177e4
LT		 6995
6996 return received;
6997}
6998
35f2d7d0 6999static void tg3_poll_link(struct tg3 *tp)
1da177e4 7000{
1da177e4 7001 /* handle link change and other phy events */
63c3a66f 7002 if (!(tg3_flag(tp, USE_LINKCHG_REG) || tg3_flag(tp, POLL_SERDES))) {
35f2d7d0
MC		 7003 struct tg3_hw_status *sblk = tp->napi[0].hw_status;
7004
1da177e4
LT		 7005 if (sblk->status & SD_STATUS_LINK_CHG) {
7006 sblk->status = SD_STATUS_UPDATED |
35f2d7d0 7007 (sblk->status & ~SD_STATUS_LINK_CHG);
f47c11ee 7008 spin_lock(&tp->lock);
63c3a66f 7009 if (tg3_flag(tp, USE_PHYLIB)) {
dd477003
MC		 7010 tw32_f(MAC_STATUS,
7011 (MAC_STATUS_SYNC_CHANGED |
7012 MAC_STATUS_CFG_CHANGED |
7013 MAC_STATUS_MI_COMPLETION |
7014 MAC_STATUS_LNKSTATE_CHANGED));
7015 udelay(40);
7016 } else
953c96e0 7017 tg3_setup_phy(tp, false);
f47c11ee 7018 spin_unlock(&tp->lock);
1da177e4
LT		 7019 }
7020 }
35f2d7d0
MC		 7021}
7022
f89f38b8
MC		 7023static int tg3_rx_prodring_xfer(struct tg3 *tp,
7024 struct tg3_rx_prodring_set *dpr,
7025 struct tg3_rx_prodring_set *spr)
b196c7e4
MC		 7026{
7027 u32 si, di, cpycnt, src_prod_idx;
f89f38b8 7028 int i, err = 0;
b196c7e4
MC		 7029
7030 while (1) {
7031 src_prod_idx = spr->rx_std_prod_idx;
7032
7033 /* Make sure updates to the rx_std_buffers[] entries and the
7034 * standard producer index are seen in the correct order.
7035 */
7036 smp_rmb();
7037
7038 if (spr->rx_std_cons_idx == src_prod_idx)
7039 break;
7040
7041 if (spr->rx_std_cons_idx < src_prod_idx)
7042 cpycnt = src_prod_idx - spr->rx_std_cons_idx;
7043 else
2c49a44d
MC		 7044 cpycnt = tp->rx_std_ring_mask + 1 -
7045 spr->rx_std_cons_idx;
b196c7e4 7046
2c49a44d
MC		 7047 cpycnt = min(cpycnt,
7048 tp->rx_std_ring_mask + 1 - dpr->rx_std_prod_idx);
b196c7e4
MC		 7049
7050 si = spr->rx_std_cons_idx;
7051 di = dpr->rx_std_prod_idx;
7052
e92967bf 7053 for (i = di; i < di + cpycnt; i++) {
9205fd9c 7054 if (dpr->rx_std_buffers[i].data) {
e92967bf 7055 cpycnt = i - di;
f89f38b8 7056 err = -ENOSPC;
e92967bf
MC		 7057 break;
7058 }
7059 }
7060
7061 if (!cpycnt)
7062 break;
7063
7064 /* Ensure that updates to the rx_std_buffers ring and the
7065 * shadowed hardware producer ring from tg3_recycle_skb() are
7066 * ordered correctly WRT the skb check above.
7067 */
7068 smp_rmb();
7069
b196c7e4
MC		 7070 memcpy(&dpr->rx_std_buffers[di],
7071 &spr->rx_std_buffers[si],
7072 cpycnt * sizeof(struct ring_info));
7073
7074 for (i = 0; i < cpycnt; i++, di++, si++) {
7075 struct tg3_rx_buffer_desc *sbd, *dbd;
7076 sbd = &spr->rx_std[si];
7077 dbd = &dpr->rx_std[di];
7078 dbd->addr_hi = sbd->addr_hi;
7079 dbd->addr_lo = sbd->addr_lo;
7080 }
7081
2c49a44d
MC		 7082 spr->rx_std_cons_idx = (spr->rx_std_cons_idx + cpycnt) &
7083 tp->rx_std_ring_mask;
7084 dpr->rx_std_prod_idx = (dpr->rx_std_prod_idx + cpycnt) &
7085 tp->rx_std_ring_mask;
b196c7e4
MC		 7086 }
7087
7088 while (1) {
7089 src_prod_idx = spr->rx_jmb_prod_idx;
7090
7091 /* Make sure updates to the rx_jmb_buffers[] entries and
7092 * the jumbo producer index are seen in the correct order.
7093 */
7094 smp_rmb();
7095
7096 if (spr->rx_jmb_cons_idx == src_prod_idx)
7097 break;
7098
7099 if (spr->rx_jmb_cons_idx < src_prod_idx)
7100 cpycnt = src_prod_idx - spr->rx_jmb_cons_idx;
7101 else
2c49a44d
MC		 7102 cpycnt = tp->rx_jmb_ring_mask + 1 -
7103 spr->rx_jmb_cons_idx;
b196c7e4
MC		 7104
7105 cpycnt = min(cpycnt,
2c49a44d 7106 tp->rx_jmb_ring_mask + 1 - dpr->rx_jmb_prod_idx);
b196c7e4
MC		 7107
7108 si = spr->rx_jmb_cons_idx;
7109 di = dpr->rx_jmb_prod_idx;
7110
e92967bf 7111 for (i = di; i < di + cpycnt; i++) {
9205fd9c 7112 if (dpr->rx_jmb_buffers[i].data) {
e92967bf 7113 cpycnt = i - di;
f89f38b8 7114 err = -ENOSPC;
e92967bf
MC		 7115 break;
7116 }
7117 }
7118
7119 if (!cpycnt)
7120 break;
7121
7122 /* Ensure that updates to the rx_jmb_buffers ring and the
7123 * shadowed hardware producer ring from tg3_recycle_skb() are
7124 * ordered correctly WRT the skb check above.
7125 */
7126 smp_rmb();
7127
b196c7e4
MC		 7128 memcpy(&dpr->rx_jmb_buffers[di],
7129 &spr->rx_jmb_buffers[si],
7130 cpycnt * sizeof(struct ring_info));
7131
7132 for (i = 0; i < cpycnt; i++, di++, si++) {
7133 struct tg3_rx_buffer_desc *sbd, *dbd;
7134 sbd = &spr->rx_jmb[si].std;
7135 dbd = &dpr->rx_jmb[di].std;
7136 dbd->addr_hi = sbd->addr_hi;
7137 dbd->addr_lo = sbd->addr_lo;
7138 }
7139
2c49a44d
MC		 7140 spr->rx_jmb_cons_idx = (spr->rx_jmb_cons_idx + cpycnt) &
7141 tp->rx_jmb_ring_mask;
7142 dpr->rx_jmb_prod_idx = (dpr->rx_jmb_prod_idx + cpycnt) &
7143 tp->rx_jmb_ring_mask;
b196c7e4 7144 }
f89f38b8
MC		 7145
7146 return err;
b196c7e4
MC		 7147}
7148
35f2d7d0
MC		 7149static int tg3_poll_work(struct tg3_napi *tnapi, int work_done, int budget)
7150{
7151 struct tg3 *tp = tnapi->tp;
1da177e4
LT		 7152
7153 /* run TX completion thread */
f3f3f27e 7154 if (tnapi->hw_status->idx[0].tx_consumer != tnapi->tx_cons) {
17375d25 7155 tg3_tx(tnapi);
63c3a66f 7156 if (unlikely(tg3_flag(tp, TX_RECOVERY_PENDING)))
4fd7ab59 7157 return work_done;
1da177e4
LT		 7158 }
7159
f891ea16
MC		 7160 if (!tnapi->rx_rcb_prod_idx)
7161 return work_done;
7162
1da177e4
LT		 7163 /* run RX thread, within the bounds set by NAPI.
7164 * All RX "locking" is done by ensuring outside
bea3348e 7165 * code synchronizes with tg3->napi.poll()
1da177e4 7166 */
8d9d7cfc 7167 if (*(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
17375d25 7168 work_done += tg3_rx(tnapi, budget - work_done);
1da177e4 7169
63c3a66f 7170 if (tg3_flag(tp, ENABLE_RSS) && tnapi == &tp->napi[1]) {
8fea32b9 7171 struct tg3_rx_prodring_set *dpr = &tp->napi[0].prodring;
f89f38b8 7172 int i, err = 0;
e4af1af9
MC		 7173 u32 std_prod_idx = dpr->rx_std_prod_idx;
7174 u32 jmb_prod_idx = dpr->rx_jmb_prod_idx;
b196c7e4 7175
7ae52890 7176 tp->rx_refill = false;
9102426a 7177 for (i = 1; i <= tp->rxq_cnt; i++)
f89f38b8 7178 err |= tg3_rx_prodring_xfer(tp, dpr,
8fea32b9 7179 &tp->napi[i].prodring);
b196c7e4
MC		 7180
7181 wmb();
7182
e4af1af9
MC		 7183 if (std_prod_idx != dpr->rx_std_prod_idx)
7184 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
7185 dpr->rx_std_prod_idx);
b196c7e4 7186
e4af1af9
MC		 7187 if (jmb_prod_idx != dpr->rx_jmb_prod_idx)
7188 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
7189 dpr->rx_jmb_prod_idx);
b196c7e4
MC		 7190
7191 mmiowb();
f89f38b8
MC		 7192
7193 if (err)
7194 tw32_f(HOSTCC_MODE, tp->coal_now);
b196c7e4
MC		 7195 }
7196
6f535763
DM		 7197 return work_done;
7198}
7199
db219973
MC		 7200static inline void tg3_reset_task_schedule(struct tg3 *tp)
7201{
7202 if (!test_and_set_bit(TG3_FLAG_RESET_TASK_PENDING, tp->tg3_flags))
7203 schedule_work(&tp->reset_task);
7204}
7205
7206static inline void tg3_reset_task_cancel(struct tg3 *tp)
7207{
7208 cancel_work_sync(&tp->reset_task);
7209 tg3_flag_clear(tp, RESET_TASK_PENDING);
c7101359 7210 tg3_flag_clear(tp, TX_RECOVERY_PENDING);
db219973
MC		 7211}
7212
35f2d7d0
MC		 7213static int tg3_poll_msix(struct napi_struct *napi, int budget)
7214{
7215 struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
7216 struct tg3 *tp = tnapi->tp;
7217 int work_done = 0;
7218 struct tg3_hw_status *sblk = tnapi->hw_status;
7219
7220 while (1) {
7221 work_done = tg3_poll_work(tnapi, work_done, budget);
7222
63c3a66f 7223 if (unlikely(tg3_flag(tp, TX_RECOVERY_PENDING)))
35f2d7d0
MC		 7224 goto tx_recovery;
7225
7226 if (unlikely(work_done >= budget))
7227 break;
7228
c6cdf436 7229 /* tp->last_tag is used in tg3_int_reenable() below
35f2d7d0
MC		 7230 * to tell the hw how much work has been processed,
7231 * so we must read it before checking for more work.
7232 */
7233 tnapi->last_tag = sblk->status_tag;
7234 tnapi->last_irq_tag = tnapi->last_tag;
7235 rmb();
7236
7237 /* check for RX/TX work to do */
6d40db7b
MC		 7238 if (likely(sblk->idx[0].tx_consumer == tnapi->tx_cons &&
7239 *(tnapi->rx_rcb_prod_idx) == tnapi->rx_rcb_ptr)) {
7ae52890
MC		 7240
7241 /* This test here is not race free, but will reduce
7242 * the number of interrupts by looping again.
7243 */
7244 if (tnapi == &tp->napi[1] && tp->rx_refill)
7245 continue;
7246
35f2d7d0
MC		 7247 napi_complete(napi);
7248 /* Reenable interrupts. */
7249 tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
7ae52890
MC		 7250
7251 /* This test here is synchronized by napi_schedule()
7252 * and napi_complete() to close the race condition.
7253 */
7254 if (unlikely(tnapi == &tp->napi[1] && tp->rx_refill)) {
7255 tw32(HOSTCC_MODE, tp->coalesce_mode |
7256 HOSTCC_MODE_ENABLE |
7257 tnapi->coal_now);
7258 }
35f2d7d0
MC		 7259 mmiowb();
7260 break;
7261 }
7262 }
7263
7264 return work_done;
7265
7266tx_recovery:
7267 /* work_done is guaranteed to be less than budget. */
7268 napi_complete(napi);
db219973 7269 tg3_reset_task_schedule(tp);
35f2d7d0
MC		 7270 return work_done;
7271}
7272
e64de4e6
MC		 7273static void tg3_process_error(struct tg3 *tp)
7274{
7275 u32 val;
7276 bool real_error = false;
7277
63c3a66f 7278 if (tg3_flag(tp, ERROR_PROCESSED))
e64de4e6
MC		 7279 return;
7280
7281 /* Check Flow Attention register */
7282 val = tr32(HOSTCC_FLOW_ATTN);
7283 if (val & ~HOSTCC_FLOW_ATTN_MBUF_LWM) {
7284 netdev_err(tp->dev, "FLOW Attention error. Resetting chip.\n");
7285 real_error = true;
7286 }
7287
7288 if (tr32(MSGINT_STATUS) & ~MSGINT_STATUS_MSI_REQ) {
7289 netdev_err(tp->dev, "MSI Status error. Resetting chip.\n");
7290 real_error = true;
7291 }
7292
7293 if (tr32(RDMAC_STATUS) || tr32(WDMAC_STATUS)) {
7294 netdev_err(tp->dev, "DMA Status error. Resetting chip.\n");
7295 real_error = true;
7296 }
7297
7298 if (!real_error)
7299 return;
7300
7301 tg3_dump_state(tp);
7302
63c3a66f 7303 tg3_flag_set(tp, ERROR_PROCESSED);
db219973 7304 tg3_reset_task_schedule(tp);
e64de4e6
MC		 7305}
7306
6f535763
DM		 7307static int tg3_poll(struct napi_struct *napi, int budget)
7308{
8ef0442f
MC		 7309 struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
7310 struct tg3 *tp = tnapi->tp;
6f535763 7311 int work_done = 0;
898a56f8 7312 struct tg3_hw_status *sblk = tnapi->hw_status;
6f535763
DM		 7313
7314 while (1) {
e64de4e6
MC		 7315 if (sblk->status & SD_STATUS_ERROR)
7316 tg3_process_error(tp);
7317
35f2d7d0
MC		 7318 tg3_poll_link(tp);
7319
17375d25 7320 work_done = tg3_poll_work(tnapi, work_done, budget);
6f535763 7321
63c3a66f 7322 if (unlikely(tg3_flag(tp, TX_RECOVERY_PENDING)))
6f535763
DM		 7323 goto tx_recovery;
7324
7325 if (unlikely(work_done >= budget))
7326 break;
7327
63c3a66f 7328 if (tg3_flag(tp, TAGGED_STATUS)) {
17375d25 7329 /* tp->last_tag is used in tg3_int_reenable() below
4fd7ab59
MC		 7330 * to tell the hw how much work has been processed,
7331 * so we must read it before checking for more work.
7332 */
898a56f8
MC		 7333 tnapi->last_tag = sblk->status_tag;
7334 tnapi->last_irq_tag = tnapi->last_tag;
4fd7ab59
MC		 7335 rmb();
7336 } else
7337 sblk->status &= ~SD_STATUS_UPDATED;
6f535763 7338
17375d25 7339 if (likely(!tg3_has_work(tnapi))) {
288379f0 7340 napi_complete(napi);
17375d25 7341 tg3_int_reenable(tnapi);
6f535763
DM		 7342 break;
7343 }
1da177e4
LT		 7344 }
7345
bea3348e 7346 return work_done;
6f535763
DM		 7347
7348tx_recovery:
4fd7ab59 7349 /* work_done is guaranteed to be less than budget. */
288379f0 7350 napi_complete(napi);
db219973 7351 tg3_reset_task_schedule(tp);
4fd7ab59 7352 return work_done;
1da177e4
LT		 7353}
7354
66cfd1bd
MC		 7355static void tg3_napi_disable(struct tg3 *tp)
7356{
7357 int i;
7358
7359 for (i = tp->irq_cnt - 1; i >= 0; i--)
7360 napi_disable(&tp->napi[i].napi);
7361}
7362
7363static void tg3_napi_enable(struct tg3 *tp)
7364{
7365 int i;
7366
7367 for (i = 0; i < tp->irq_cnt; i++)
7368 napi_enable(&tp->napi[i].napi);
7369}
7370
7371static void tg3_napi_init(struct tg3 *tp)
7372{
7373 int i;
7374
7375 netif_napi_add(tp->dev, &tp->napi[0].napi, tg3_poll, 64);
7376 for (i = 1; i < tp->irq_cnt; i++)
7377 netif_napi_add(tp->dev, &tp->napi[i].napi, tg3_poll_msix, 64);
7378}
7379
7380static void tg3_napi_fini(struct tg3 *tp)
7381{
7382 int i;
7383
7384 for (i = 0; i < tp->irq_cnt; i++)
7385 netif_napi_del(&tp->napi[i].napi);
7386}
7387
7388static inline void tg3_netif_stop(struct tg3 *tp)
7389{
7390 tp->dev->trans_start = jiffies; /* prevent tx timeout */
7391 tg3_napi_disable(tp);
f4a46d1f 7392 netif_carrier_off(tp->dev);
66cfd1bd
MC		 7393 netif_tx_disable(tp->dev);
7394}
7395
35763066 7396/* tp->lock must be held */
66cfd1bd
MC		 7397static inline void tg3_netif_start(struct tg3 *tp)
7398{
be947307
MC		 7399 tg3_ptp_resume(tp);
7400
66cfd1bd
MC		 7401 /* NOTE: unconditional netif_tx_wake_all_queues is only
7402 * appropriate so long as all callers are assured to
7403 * have free tx slots (such as after tg3_init_hw)
7404 */
7405 netif_tx_wake_all_queues(tp->dev);
7406
f4a46d1f
NNS		 7407 if (tp->link_up)
7408 netif_carrier_on(tp->dev);
7409
66cfd1bd
MC		 7410 tg3_napi_enable(tp);
7411 tp->napi[0].hw_status->status |= SD_STATUS_UPDATED;
7412 tg3_enable_ints(tp);
7413}
7414
f47c11ee
DM		 7415static void tg3_irq_quiesce(struct tg3 *tp)
7416{
4f125f42
MC		 7417 int i;
7418
f47c11ee
DM		 7419 BUG_ON(tp->irq_sync);
7420
7421 tp->irq_sync = 1;
7422 smp_mb();
7423
4f125f42
MC		 7424 for (i = 0; i < tp->irq_cnt; i++)
7425 synchronize_irq(tp->napi[i].irq_vec);
f47c11ee
DM		 7426}
7427
f47c11ee
DM		 7428/* Fully shutdown all tg3 driver activity elsewhere in the system.
7429 * If irq_sync is non-zero, then the IRQ handler must be synchronized
7430 * with as well. Most of the time, this is not necessary except when
7431 * shutting down the device.
7432 */
7433static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
7434{
46966545 7435 spin_lock_bh(&tp->lock);
f47c11ee
DM		 7436 if (irq_sync)
7437 tg3_irq_quiesce(tp);
f47c11ee
DM		 7438}
7439
7440static inline void tg3_full_unlock(struct tg3 *tp)
7441{
f47c11ee
DM		 7442 spin_unlock_bh(&tp->lock);
7443}
7444
fcfa0a32
MC		 7445/* One-shot MSI handler - Chip automatically disables interrupt
7446 * after sending MSI so driver doesn't have to do it.
7447 */
7d12e780 7448static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
fcfa0a32 7449{
09943a18
MC		 7450 struct tg3_napi *tnapi = dev_id;
7451 struct tg3 *tp = tnapi->tp;
fcfa0a32 7452
898a56f8 7453 prefetch(tnapi->hw_status);
0c1d0e2b
MC		 7454 if (tnapi->rx_rcb)
7455 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
fcfa0a32
MC		 7456
7457 if (likely(!tg3_irq_sync(tp)))
09943a18 7458 napi_schedule(&tnapi->napi);
fcfa0a32
MC		 7459
7460 return IRQ_HANDLED;
7461}
7462
88b06bc2
MC		 7463/* MSI ISR - No need to check for interrupt sharing and no need to
7464 * flush status block and interrupt mailbox. PCI ordering rules
7465 * guarantee that MSI will arrive after the status block.
7466 */
7d12e780 7467static irqreturn_t tg3_msi(int irq, void *dev_id)
88b06bc2 7468{
09943a18
MC		 7469 struct tg3_napi *tnapi = dev_id;
7470 struct tg3 *tp = tnapi->tp;
88b06bc2 7471
898a56f8 7472 prefetch(tnapi->hw_status);
0c1d0e2b
MC		 7473 if (tnapi->rx_rcb)
7474 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
88b06bc2 7475 /*
fac9b83e 7476 * Writing any value to intr-mbox-0 clears PCI INTA# and
88b06bc2 7477 * chip-internal interrupt pending events.
fac9b83e 7478 * Writing non-zero to intr-mbox-0 additional tells the
88b06bc2
MC		 7479 * NIC to stop sending us irqs, engaging "in-intr-handler"
7480 * event coalescing.
7481 */
5b39de91 7482 tw32_mailbox(tnapi->int_mbox, 0x00000001);
61487480 7483 if (likely(!tg3_irq_sync(tp)))
09943a18 7484 napi_schedule(&tnapi->napi);
61487480 7485
88b06bc2
MC		 7486 return IRQ_RETVAL(1);
7487}
7488
7d12e780 7489static irqreturn_t tg3_interrupt(int irq, void *dev_id)
1da177e4 7490{
09943a18
MC		 7491 struct tg3_napi *tnapi = dev_id;
7492 struct tg3 *tp = tnapi->tp;
898a56f8 7493 struct tg3_hw_status *sblk = tnapi->hw_status;
1da177e4
LT		 7494 unsigned int handled = 1;
7495
1da177e4
LT		 7496 /* In INTx mode, it is possible for the interrupt to arrive at
7497 * the CPU before the status block posted prior to the interrupt.
7498 * Reading the PCI State register will confirm whether the
7499 * interrupt is ours and will flush the status block.
7500 */
d18edcb2 7501 if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
63c3a66f 7502 if (tg3_flag(tp, CHIP_RESETTING) ||
d18edcb2
MC		 7503 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
7504 handled = 0;
f47c11ee 7505 goto out;
fac9b83e 7506 }
d18edcb2
MC		 7507 }
7508
7509 /*
7510 * Writing any value to intr-mbox-0 clears PCI INTA# and
7511 * chip-internal interrupt pending events.
7512 * Writing non-zero to intr-mbox-0 additional tells the
7513 * NIC to stop sending us irqs, engaging "in-intr-handler"
7514 * event coalescing.
c04cb347
MC		 7515 *
7516 * Flush the mailbox to de-assert the IRQ immediately to prevent
7517 * spurious interrupts. The flush impacts performance but
7518 * excessive spurious interrupts can be worse in some cases.
d18edcb2 7519 */
c04cb347 7520 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
d18edcb2
MC		 7521 if (tg3_irq_sync(tp))
7522 goto out;
7523 sblk->status &= ~SD_STATUS_UPDATED;
17375d25 7524 if (likely(tg3_has_work(tnapi))) {
72334482 7525 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
09943a18 7526 napi_schedule(&tnapi->napi);
d18edcb2
MC		 7527 } else {
7528 /* No work, shared interrupt perhaps? re-enable
7529 * interrupts, and flush that PCI write
7530 */
7531 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
7532 0x00000000);
fac9b83e 7533 }
f47c11ee 7534out:
fac9b83e
DM		 7535 return IRQ_RETVAL(handled);
7536}
7537
7d12e780 7538static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
fac9b83e 7539{
09943a18
MC		 7540 struct tg3_napi *tnapi = dev_id;
7541 struct tg3 *tp = tnapi->tp;
898a56f8 7542 struct tg3_hw_status *sblk = tnapi->hw_status;
fac9b83e
DM		 7543 unsigned int handled = 1;
7544
fac9b83e
DM		 7545 /* In INTx mode, it is possible for the interrupt to arrive at
7546 * the CPU before the status block posted prior to the interrupt.
7547 * Reading the PCI State register will confirm whether the
7548 * interrupt is ours and will flush the status block.
7549 */
898a56f8 7550 if (unlikely(sblk->status_tag == tnapi->last_irq_tag)) {
63c3a66f 7551 if (tg3_flag(tp, CHIP_RESETTING) ||
d18edcb2
MC		 7552 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
7553 handled = 0;
f47c11ee 7554 goto out;
1da177e4 7555 }
d18edcb2
MC		 7556 }
7557
7558 /*
7559 * writing any value to intr-mbox-0 clears PCI INTA# and
7560 * chip-internal interrupt pending events.
7561 * writing non-zero to intr-mbox-0 additional tells the
7562 * NIC to stop sending us irqs, engaging "in-intr-handler"
7563 * event coalescing.
c04cb347
MC		 7564 *
7565 * Flush the mailbox to de-assert the IRQ immediately to prevent
7566 * spurious interrupts. The flush impacts performance but
7567 * excessive spurious interrupts can be worse in some cases.
d18edcb2 7568 */
c04cb347 7569 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
624f8e50
MC		 7570
7571 /*
7572 * In a shared interrupt configuration, sometimes other devices'
7573 * interrupts will scream. We record the current status tag here
7574 * so that the above check can report that the screaming interrupts
7575 * are unhandled. Eventually they will be silenced.
7576 */
898a56f8 7577 tnapi->last_irq_tag = sblk->status_tag;
624f8e50 7578
d18edcb2
MC		 7579 if (tg3_irq_sync(tp))
7580 goto out;
624f8e50 7581
72334482 7582 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
624f8e50 7583
09943a18 7584 napi_schedule(&tnapi->napi);
624f8e50 7585
f47c11ee 7586out:
1da177e4
LT		 7587 return IRQ_RETVAL(handled);
7588}
7589
7938109f 7590/* ISR for interrupt test */
7d12e780 7591static irqreturn_t tg3_test_isr(int irq, void *dev_id)
7938109f 7592{
09943a18
MC		 7593 struct tg3_napi *tnapi = dev_id;
7594 struct tg3 *tp = tnapi->tp;
898a56f8 7595 struct tg3_hw_status *sblk = tnapi->hw_status;
7938109f 7596
f9804ddb
MC		 7597 if ((sblk->status & SD_STATUS_UPDATED) ||
7598 !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
b16250e3 7599 tg3_disable_ints(tp);
7938109f
MC		 7600 return IRQ_RETVAL(1);
7601 }
7602 return IRQ_RETVAL(0);
7603}
7604
1da177e4
LT		 7605#ifdef CONFIG_NET_POLL_CONTROLLER
7606static void tg3_poll_controller(struct net_device *dev)
7607{
4f125f42 7608 int i;
88b06bc2
MC		 7609 struct tg3 *tp = netdev_priv(dev);
7610
9c13cb8b
NNS		 7611 if (tg3_irq_sync(tp))
7612 return;
7613
4f125f42 7614 for (i = 0; i < tp->irq_cnt; i++)
fe234f0e 7615 tg3_interrupt(tp->napi[i].irq_vec, &tp->napi[i]);
1da177e4
LT		 7616}
7617#endif
7618
1da177e4
LT		 7619static void tg3_tx_timeout(struct net_device *dev)
7620{
7621 struct tg3 *tp = netdev_priv(dev);
7622
b0408751 7623 if (netif_msg_tx_err(tp)) {
05dbe005 7624 netdev_err(dev, "transmit timed out, resetting\n");
97bd8e49 7625 tg3_dump_state(tp);
b0408751 7626 }
1da177e4 7627
db219973 7628 tg3_reset_task_schedule(tp);
1da177e4
LT		 7629}
7630
c58ec932
MC		 7631/* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
7632static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
7633{
7634 u32 base = (u32) mapping & 0xffffffff;
7635
37567910 7636 return base + len + 8 < base;
c58ec932
MC		 7637}
7638
0f0d1510
MC		 7639/* Test for TSO DMA buffers that cross into regions which are within MSS bytes
7640 * of any 4GB boundaries: 4G, 8G, etc
7641 */
7642static inline int tg3_4g_tso_overflow_test(struct tg3 *tp, dma_addr_t mapping,
7643 u32 len, u32 mss)
7644{
7645 if (tg3_asic_rev(tp) == ASIC_REV_5762 && mss) {
7646 u32 base = (u32) mapping & 0xffffffff;
7647
7648 return ((base + len + (mss & 0x3fff)) < base);
7649 }
7650 return 0;
7651}
7652
72f2afb8
MC		 7653/* Test for DMA addresses > 40-bit */
7654static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
7655 int len)
7656{
7657#if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
63c3a66f 7658 if (tg3_flag(tp, 40BIT_DMA_BUG))
807540ba 7659 return ((u64) mapping + len) > DMA_BIT_MASK(40);
72f2afb8
MC		 7660 return 0;
7661#else
7662 return 0;
7663#endif
7664}
7665
d1a3b737 7666static inline void tg3_tx_set_bd(struct tg3_tx_buffer_desc *txbd,
92cd3a17
MC		 7667 dma_addr_t mapping, u32 len, u32 flags,
7668 u32 mss, u32 vlan)
2ffcc981 7669{
92cd3a17
MC		 7670 txbd->addr_hi = ((u64) mapping >> 32);
7671 txbd->addr_lo = ((u64) mapping & 0xffffffff);
7672 txbd->len_flags = (len << TXD_LEN_SHIFT) | (flags & 0x0000ffff);
7673 txbd->vlan_tag = (mss << TXD_MSS_SHIFT) | (vlan << TXD_VLAN_TAG_SHIFT);
2ffcc981 7674}
1da177e4 7675
84b67b27 7676static bool tg3_tx_frag_set(struct tg3_napi *tnapi, u32 *entry, u32 *budget,
d1a3b737
MC		 7677 dma_addr_t map, u32 len, u32 flags,
7678 u32 mss, u32 vlan)
7679{
7680 struct tg3 *tp = tnapi->tp;
7681 bool hwbug = false;
7682
7683 if (tg3_flag(tp, SHORT_DMA_BUG) && len <= 8)
3db1cd5c 7684 hwbug = true;
d1a3b737
MC		 7685
7686 if (tg3_4g_overflow_test(map, len))
3db1cd5c 7687 hwbug = true;
d1a3b737 7688
0f0d1510
MC		 7689 if (tg3_4g_tso_overflow_test(tp, map, len, mss))
7690 hwbug = true;
7691
d1a3b737 7692 if (tg3_40bit_overflow_test(tp, map, len))
3db1cd5c 7693 hwbug = true;
d1a3b737 7694
a4cb428d 7695 if (tp->dma_limit) {
b9e45482 7696 u32 prvidx = *entry;
e31aa987 7697 u32 tmp_flag = flags & ~TXD_FLAG_END;
a4cb428d
MC		 7698 while (len > tp->dma_limit && *budget) {
7699 u32 frag_len = tp->dma_limit;
7700 len -= tp->dma_limit;
e31aa987 7701
b9e45482
MC		 7702 /* Avoid the 8byte DMA problem */
7703 if (len <= 8) {
a4cb428d
MC		 7704 len += tp->dma_limit / 2;
7705 frag_len = tp->dma_limit / 2;
e31aa987
MC		 7706 }
7707
b9e45482
MC		 7708 tnapi->tx_buffers[*entry].fragmented = true;
7709
7710 tg3_tx_set_bd(&tnapi->tx_ring[*entry], map,
7711 frag_len, tmp_flag, mss, vlan);
7712 *budget -= 1;
7713 prvidx = *entry;
7714 *entry = NEXT_TX(*entry);
7715
e31aa987
MC		 7716 map += frag_len;
7717 }
7718
7719 if (len) {
7720 if (*budget) {
7721 tg3_tx_set_bd(&tnapi->tx_ring[*entry], map,
7722 len, flags, mss, vlan);
b9e45482 7723 *budget -= 1;
e31aa987
MC		 7724 *entry = NEXT_TX(*entry);
7725 } else {
3db1cd5c 7726 hwbug = true;
b9e45482 7727 tnapi->tx_buffers[prvidx].fragmented = false;
e31aa987
MC		 7728 }
7729 }
7730 } else {
84b67b27
MC		 7731 tg3_tx_set_bd(&tnapi->tx_ring[*entry], map,
7732 len, flags, mss, vlan);
e31aa987
MC		 7733 *entry = NEXT_TX(*entry);
7734 }
d1a3b737
MC		 7735
7736 return hwbug;
7737}
7738
0d681b27 7739static void tg3_tx_skb_unmap(struct tg3_napi *tnapi, u32 entry, int last)
432aa7ed
MC		 7740{
7741 int i;
0d681b27 7742 struct sk_buff *skb;
df8944cf 7743 struct tg3_tx_ring_info *txb = &tnapi->tx_buffers[entry];
432aa7ed 7744
0d681b27
MC		 7745 skb = txb->skb;
7746 txb->skb = NULL;
7747
432aa7ed
MC		 7748 pci_unmap_single(tnapi->tp->pdev,
7749 dma_unmap_addr(txb, mapping),
7750 skb_headlen(skb),
7751 PCI_DMA_TODEVICE);
e01ee14d
MC		 7752
7753 while (txb->fragmented) {
7754 txb->fragmented = false;
7755 entry = NEXT_TX(entry);
7756 txb = &tnapi->tx_buffers[entry];
7757 }
7758
ba1142e4 7759 for (i = 0; i <= last; i++) {
9e903e08 7760 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
432aa7ed
MC		 7761
7762 entry = NEXT_TX(entry);
7763 txb = &tnapi->tx_buffers[entry];
7764
7765 pci_unmap_page(tnapi->tp->pdev,
7766 dma_unmap_addr(txb, mapping),
9e903e08 7767 skb_frag_size(frag), PCI_DMA_TODEVICE);
e01ee14d
MC		 7768
7769 while (txb->fragmented) {
7770 txb->fragmented = false;
7771 entry = NEXT_TX(entry);
7772 txb = &tnapi->tx_buffers[entry];
7773 }
432aa7ed
MC		 7774 }
7775}
7776
72f2afb8 7777/* Workaround 4GB and 40-bit hardware DMA bugs. */
24f4efd4 7778static int tigon3_dma_hwbug_workaround(struct tg3_napi *tnapi,
f7ff1987 7779 struct sk_buff **pskb,
84b67b27 7780 u32 *entry, u32 *budget,
92cd3a17 7781 u32 base_flags, u32 mss, u32 vlan)
1da177e4 7782{
24f4efd4 7783 struct tg3 *tp = tnapi->tp;
f7ff1987 7784 struct sk_buff *new_skb, *skb = *pskb;
c58ec932 7785 dma_addr_t new_addr = 0;
432aa7ed 7786 int ret = 0;
1da177e4 7787
4153577a 7788 if (tg3_asic_rev(tp) != ASIC_REV_5701)
41588ba1
MC		 7789 new_skb = skb_copy(skb, GFP_ATOMIC);
7790 else {
7791 int more_headroom = 4 - ((unsigned long)skb->data & 3);
7792
7793 new_skb = skb_copy_expand(skb,
7794 skb_headroom(skb) + more_headroom,
7795 skb_tailroom(skb), GFP_ATOMIC);
7796 }
7797
1da177e4 7798 if (!new_skb) {
c58ec932
MC		 7799 ret = -1;
7800 } else {
7801 /* New SKB is guaranteed to be linear. */
f4188d8a
AD		 7802 new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len,
7803 PCI_DMA_TODEVICE);
7804 /* Make sure the mapping succeeded */
7805 if (pci_dma_mapping_error(tp->pdev, new_addr)) {
497a27b9 7806 dev_kfree_skb_any(new_skb);
c58ec932 7807 ret = -1;
c58ec932 7808 } else {
b9e45482
MC		 7809 u32 save_entry = *entry;
7810
92cd3a17
MC		 7811 base_flags |= TXD_FLAG_END;
7812
84b67b27
MC		 7813 tnapi->tx_buffers[*entry].skb = new_skb;
7814 dma_unmap_addr_set(&tnapi->tx_buffers[*entry],
432aa7ed
MC		 7815 mapping, new_addr);
7816
84b67b27 7817 if (tg3_tx_frag_set(tnapi, entry, budget, new_addr,
d1a3b737
MC		 7818 new_skb->len, base_flags,
7819 mss, vlan)) {
ba1142e4 7820 tg3_tx_skb_unmap(tnapi, save_entry, -1);
497a27b9 7821 dev_kfree_skb_any(new_skb);
d1a3b737
MC		 7822 ret = -1;
7823 }
f4188d8a 7824 }
1da177e4
LT		 7825 }
7826
497a27b9 7827 dev_kfree_skb_any(skb);
f7ff1987 7828 *pskb = new_skb;
c58ec932 7829 return ret;
1da177e4
LT		 7830}
7831
2ffcc981 7832static netdev_tx_t tg3_start_xmit(struct sk_buff *, struct net_device *);
52c0fd83 7833
4d8fdc95
PS		 7834/* Use GSO to workaround all TSO packets that meet HW bug conditions
7835 * indicated in tg3_tx_frag_set()
52c0fd83 7836 */
4d8fdc95
PS		 7837static int tg3_tso_bug(struct tg3 *tp, struct tg3_napi *tnapi,
7838 struct netdev_queue *txq, struct sk_buff *skb)
52c0fd83
MC		 7839{
7840 struct sk_buff *segs, *nskb;
f3f3f27e 7841 u32 frag_cnt_est = skb_shinfo(skb)->gso_segs * 3;
52c0fd83
MC		 7842
7843 /* Estimate the number of fragments in the worst case */
4d8fdc95
PS		 7844 if (unlikely(tg3_tx_avail(tnapi) <= frag_cnt_est)) {
7845 netif_tx_stop_queue(txq);
f65aac16
MC		 7846
7847 /* netif_tx_stop_queue() must be done before checking
7848 * checking tx index in tg3_tx_avail() below, because in
7849 * tg3_tx(), we update tx index before checking for
7850 * netif_tx_queue_stopped().
7851 */
7852 smp_mb();
4d8fdc95 7853 if (tg3_tx_avail(tnapi) <= frag_cnt_est)
7f62ad5d
MC		 7854 return NETDEV_TX_BUSY;
7855
4d8fdc95 7856 netif_tx_wake_queue(txq);
52c0fd83
MC		 7857 }
7858
4d8fdc95
PS		 7859 segs = skb_gso_segment(skb, tp->dev->features &
7860 ~(NETIF_F_TSO | NETIF_F_TSO6));
40c1deaf 7861 if (IS_ERR(segs) || !segs)
52c0fd83
MC		 7862 goto tg3_tso_bug_end;
7863
7864 do {
7865 nskb = segs;
7866 segs = segs->next;
7867 nskb->next = NULL;
2ffcc981 7868 tg3_start_xmit(nskb, tp->dev);
52c0fd83
MC		 7869 } while (segs);
7870
7871tg3_tso_bug_end:
497a27b9 7872 dev_kfree_skb_any(skb);
52c0fd83
MC		 7873
7874 return NETDEV_TX_OK;
7875}
52c0fd83 7876
d71c0dc4 7877/* hard_start_xmit for all devices */
2ffcc981 7878static netdev_tx_t tg3_start_xmit(struct sk_buff *skb, struct net_device *dev)
1da177e4
LT		 7879{
7880 struct tg3 *tp = netdev_priv(dev);
92cd3a17 7881 u32 len, entry, base_flags, mss, vlan = 0;
84b67b27 7882 u32 budget;
432aa7ed 7883 int i = -1, would_hit_hwbug;
90079ce8 7884 dma_addr_t mapping;
24f4efd4
MC		 7885 struct tg3_napi *tnapi;
7886 struct netdev_queue *txq;
432aa7ed 7887 unsigned int last;
d3f6f3a1
MC		 7888 struct iphdr *iph = NULL;
7889 struct tcphdr *tcph = NULL;
7890 __sum16 tcp_csum = 0, ip_csum = 0;
7891 __be16 ip_tot_len = 0;
f4188d8a 7892
24f4efd4
MC		 7893 txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
7894 tnapi = &tp->napi[skb_get_queue_mapping(skb)];
63c3a66f 7895 if (tg3_flag(tp, ENABLE_TSS))
24f4efd4 7896 tnapi++;
1da177e4 7897
84b67b27
MC		 7898 budget = tg3_tx_avail(tnapi);
7899
00b70504 7900 /* We are running in BH disabled context with netif_tx_lock
bea3348e 7901 * and TX reclaim runs via tp->napi.poll inside of a software
f47c11ee
DM		 7902 * interrupt. Furthermore, IRQ processing runs lockless so we have
7903 * no IRQ context deadlocks to worry about either. Rejoice!
1da177e4 7904 */
84b67b27 7905 if (unlikely(budget <= (skb_shinfo(skb)->nr_frags + 1))) {
24f4efd4
MC		 7906 if (!netif_tx_queue_stopped(txq)) {
7907 netif_tx_stop_queue(txq);
1f064a87
SH		 7908
7909 /* This is a hard error, log it. */
5129c3a3
MC		 7910 netdev_err(dev,
7911 "BUG! Tx Ring full when queue awake!\n");
1f064a87 7912 }
1da177e4
LT		 7913 return NETDEV_TX_BUSY;
7914 }
7915
f3f3f27e 7916 entry = tnapi->tx_prod;
1da177e4 7917 base_flags = 0;
24f4efd4 7918
be98da6a
MC		 7919 mss = skb_shinfo(skb)->gso_size;
7920 if (mss) {
34195c3d 7921 u32 tcp_opt_len, hdr_len;
1da177e4 7922
105dcb59 7923 if (skb_cow_head(skb, 0))
48855432 7924 goto drop;
1da177e4 7925
34195c3d 7926 iph = ip_hdr(skb);
ab6a5bb6 7927 tcp_opt_len = tcp_optlen(skb);
1da177e4 7928
a5a11955 7929 hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb) - ETH_HLEN;
34195c3d 7930
476c1885
VY		 7931 /* HW/FW can not correctly segment packets that have been
7932 * vlan encapsulated.
7933 */
7934 if (skb->protocol == htons(ETH_P_8021Q) ||
7935 skb->protocol == htons(ETH_P_8021AD))
7936 return tg3_tso_bug(tp, tnapi, txq, skb);
7937
a5a11955 7938 if (!skb_is_gso_v6(skb)) {
d71c0dc4
MC		 7939 if (unlikely((ETH_HLEN + hdr_len) > 80) &&
7940 tg3_flag(tp, TSO_BUG))
4d8fdc95 7941 return tg3_tso_bug(tp, tnapi, txq, skb);
d71c0dc4 7942
d3f6f3a1
MC		 7943 ip_csum = iph->check;
7944 ip_tot_len = iph->tot_len;
34195c3d
MC		 7945 iph->check = 0;
7946 iph->tot_len = htons(mss + hdr_len);
7947 }
7948
1da177e4
LT		 7949 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
7950 TXD_FLAG_CPU_POST_DMA);
7951
d3f6f3a1
MC		 7952 tcph = tcp_hdr(skb);
7953 tcp_csum = tcph->check;
7954
63c3a66f
JP		 7955 if (tg3_flag(tp, HW_TSO_1) ||
7956 tg3_flag(tp, HW_TSO_2) ||
7957 tg3_flag(tp, HW_TSO_3)) {
d3f6f3a1 7958 tcph->check = 0;
1da177e4 7959 base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
d3f6f3a1
MC		 7960 } else {
7961 tcph->check = ~csum_tcpudp_magic(iph->saddr, iph->daddr,
7962 0, IPPROTO_TCP, 0);
7963 }
1da177e4 7964
63c3a66f 7965 if (tg3_flag(tp, HW_TSO_3)) {
615774fe
MC		 7966 mss |= (hdr_len & 0xc) << 12;
7967 if (hdr_len & 0x10)
7968 base_flags |= 0x00000010;
7969 base_flags |= (hdr_len & 0x3e0) << 5;
63c3a66f 7970 } else if (tg3_flag(tp, HW_TSO_2))
92c6b8d1 7971 mss |= hdr_len << 9;
63c3a66f 7972 else if (tg3_flag(tp, HW_TSO_1) ||
4153577a 7973 tg3_asic_rev(tp) == ASIC_REV_5705) {
eddc9ec5 7974 if (tcp_opt_len || iph->ihl > 5) {
1da177e4
LT		 7975 int tsflags;
7976
eddc9ec5 7977 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
1da177e4
LT		 7978 mss |= (tsflags << 11);
7979 }
7980 } else {
eddc9ec5 7981 if (tcp_opt_len || iph->ihl > 5) {
1da177e4
LT		 7982 int tsflags;
7983
eddc9ec5 7984 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
1da177e4
LT		 7985 base_flags |= tsflags << 12;
7986 }
7987 }
476c1885
VY		 7988 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
7989 /* HW/FW can not correctly checksum packets that have been
7990 * vlan encapsulated.
7991 */
7992 if (skb->protocol == htons(ETH_P_8021Q) ||
7993 skb->protocol == htons(ETH_P_8021AD)) {
7994 if (skb_checksum_help(skb))
7995 goto drop;
7996 } else {
7997 base_flags |= TXD_FLAG_TCPUDP_CSUM;
7998 }
1da177e4 7999 }
bf933c80 8000
93a700a9
MC		 8001 if (tg3_flag(tp, USE_JUMBO_BDFLAG) &&
8002 !mss && skb->len > VLAN_ETH_FRAME_LEN)
8003 base_flags |= TXD_FLAG_JMB_PKT;
8004
92cd3a17
MC		 8005 if (vlan_tx_tag_present(skb)) {
8006 base_flags |= TXD_FLAG_VLAN;
8007 vlan = vlan_tx_tag_get(skb);
8008 }
1da177e4 8009
fb4ce8ad
MC		 8010 if ((unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) &&
8011 tg3_flag(tp, TX_TSTAMP_EN)) {
8012 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
8013 base_flags |= TXD_FLAG_HWTSTAMP;
8014 }
8015
f4188d8a
AD		 8016 len = skb_headlen(skb);
8017
8018 mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
48855432
ED		 8019 if (pci_dma_mapping_error(tp->pdev, mapping))
8020 goto drop;
8021
90079ce8 8022
f3f3f27e 8023 tnapi->tx_buffers[entry].skb = skb;
4e5e4f0d 8024 dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping);
1da177e4
LT		 8025
8026 would_hit_hwbug = 0;
8027
63c3a66f 8028 if (tg3_flag(tp, 5701_DMA_BUG))
c58ec932 8029 would_hit_hwbug = 1;
1da177e4 8030
84b67b27 8031 if (tg3_tx_frag_set(tnapi, &entry, &budget, mapping, len, base_flags |
d1a3b737 8032 ((skb_shinfo(skb)->nr_frags == 0) ? TXD_FLAG_END : 0),
ba1142e4 8033 mss, vlan)) {
d1a3b737 8034 would_hit_hwbug = 1;
ba1142e4 8035 } else if (skb_shinfo(skb)->nr_frags > 0) {
92cd3a17
MC		 8036 u32 tmp_mss = mss;
8037
8038 if (!tg3_flag(tp, HW_TSO_1) &&
8039 !tg3_flag(tp, HW_TSO_2) &&
8040 !tg3_flag(tp, HW_TSO_3))
8041 tmp_mss = 0;
8042
c5665a53
MC		 8043 /* Now loop through additional data
8044 * fragments, and queue them.
8045 */
1da177e4
LT		 8046 last = skb_shinfo(skb)->nr_frags - 1;
8047 for (i = 0; i <= last; i++) {
8048 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
8049
9e903e08 8050 len = skb_frag_size(frag);
dc234d0b 8051 mapping = skb_frag_dma_map(&tp->pdev->dev, frag, 0,
5d6bcdfe 8052 len, DMA_TO_DEVICE);
1da177e4 8053
f3f3f27e 8054 tnapi->tx_buffers[entry].skb = NULL;
4e5e4f0d 8055 dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
f4188d8a 8056 mapping);
5d6bcdfe 8057 if (dma_mapping_error(&tp->pdev->dev, mapping))
f4188d8a 8058 goto dma_error;
1da177e4 8059
b9e45482
MC		 8060 if (!budget ||
8061 tg3_tx_frag_set(tnapi, &entry, &budget, mapping,
84b67b27
MC		 8062 len, base_flags |
8063 ((i == last) ? TXD_FLAG_END : 0),
b9e45482 8064 tmp_mss, vlan)) {
72f2afb8 8065 would_hit_hwbug = 1;
b9e45482
MC		 8066 break;
8067 }
1da177e4
LT		 8068 }
8069 }
8070
8071 if (would_hit_hwbug) {
0d681b27 8072 tg3_tx_skb_unmap(tnapi, tnapi->tx_prod, i);
1da177e4 8073
d3f6f3a1
MC		 8074 if (mss) {
8075 /* If it's a TSO packet, do GSO instead of
8076 * allocating and copying to a large linear SKB
8077 */
8078 if (ip_tot_len) {
8079 iph->check = ip_csum;
8080 iph->tot_len = ip_tot_len;
8081 }
8082 tcph->check = tcp_csum;
4d8fdc95 8083 return tg3_tso_bug(tp, tnapi, txq, skb);
d3f6f3a1
MC		 8084 }
8085
1da177e4
LT		 8086 /* If the workaround fails due to memory/mapping
8087 * failure, silently drop this packet.
8088 */
84b67b27
MC		 8089 entry = tnapi->tx_prod;
8090 budget = tg3_tx_avail(tnapi);
f7ff1987 8091 if (tigon3_dma_hwbug_workaround(tnapi, &skb, &entry, &budget,
84b67b27 8092 base_flags, mss, vlan))
48855432 8093 goto drop_nofree;
1da177e4
LT		 8094 }
8095
d515b450 8096 skb_tx_timestamp(skb);
5cb917bc 8097 netdev_tx_sent_queue(txq, skb->len);
d515b450 8098
6541b806
MC		 8099 /* Sync BD data before updating mailbox */
8100 wmb();
8101
1da177e4 8102 /* Packets are ready, update Tx producer idx local and on card. */
24f4efd4 8103 tw32_tx_mbox(tnapi->prodmbox, entry);
1da177e4 8104
f3f3f27e
MC		 8105 tnapi->tx_prod = entry;
8106 if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
24f4efd4 8107 netif_tx_stop_queue(txq);
f65aac16
MC		 8108
8109 /* netif_tx_stop_queue() must be done before checking
8110 * checking tx index in tg3_tx_avail() below, because in
8111 * tg3_tx(), we update tx index before checking for
8112 * netif_tx_queue_stopped().
8113 */
8114 smp_mb();
f3f3f27e 8115 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
24f4efd4 8116 netif_tx_wake_queue(txq);
51b91468 8117 }
1da177e4 8118
cdd0db05 8119 mmiowb();
1da177e4 8120 return NETDEV_TX_OK;
f4188d8a
AD		 8121
8122dma_error:
ba1142e4 8123 tg3_tx_skb_unmap(tnapi, tnapi->tx_prod, --i);
432aa7ed 8124 tnapi->tx_buffers[tnapi->tx_prod].skb = NULL;
48855432 8125drop:
497a27b9 8126 dev_kfree_skb_any(skb);
48855432
ED		 8127drop_nofree:
8128 tp->tx_dropped++;
f4188d8a 8129 return NETDEV_TX_OK;
1da177e4
LT		 8130}
8131
6e01b20b
MC		 8132static void tg3_mac_loopback(struct tg3 *tp, bool enable)
8133{
8134 if (enable) {
8135 tp->mac_mode &= ~(MAC_MODE_HALF_DUPLEX |
8136 MAC_MODE_PORT_MODE_MASK);
8137
8138 tp->mac_mode |= MAC_MODE_PORT_INT_LPBACK;
8139
8140 if (!tg3_flag(tp, 5705_PLUS))
8141 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
8142
8143 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
8144 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
8145 else
8146 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
8147 } else {
8148 tp->mac_mode &= ~MAC_MODE_PORT_INT_LPBACK;
8149
8150 if (tg3_flag(tp, 5705_PLUS) ||
8151 (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) ||
4153577a 8152 tg3_asic_rev(tp) == ASIC_REV_5700)
6e01b20b
MC		 8153 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
8154 }
8155
8156 tw32(MAC_MODE, tp->mac_mode);
8157 udelay(40);
8158}
8159
941ec90f 8160static int tg3_phy_lpbk_set(struct tg3 *tp, u32 speed, bool extlpbk)
5e5a7f37 8161{
941ec90f 8162 u32 val, bmcr, mac_mode, ptest = 0;
5e5a7f37
MC		 8163
8164 tg3_phy_toggle_apd(tp, false);
953c96e0 8165 tg3_phy_toggle_automdix(tp, false);
5e5a7f37 8166
941ec90f
MC		 8167 if (extlpbk && tg3_phy_set_extloopbk(tp))
8168 return -EIO;
8169
8170 bmcr = BMCR_FULLDPLX;
5e5a7f37
MC		 8171 switch (speed) {
8172 case SPEED_10:
8173 break;
8174 case SPEED_100:
8175 bmcr |= BMCR_SPEED100;
8176 break;
8177 case SPEED_1000:
8178 default:
8179 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
8180 speed = SPEED_100;
8181 bmcr |= BMCR_SPEED100;
8182 } else {
8183 speed = SPEED_1000;
8184 bmcr |= BMCR_SPEED1000;
8185 }
8186 }
8187
941ec90f
MC		 8188 if (extlpbk) {
8189 if (!(tp->phy_flags & TG3_PHYFLG_IS_FET)) {
8190 tg3_readphy(tp, MII_CTRL1000, &val);
8191 val |= CTL1000_AS_MASTER |
8192 CTL1000_ENABLE_MASTER;
8193 tg3_writephy(tp, MII_CTRL1000, val);
8194 } else {
8195 ptest = MII_TG3_FET_PTEST_TRIM_SEL |
8196 MII_TG3_FET_PTEST_TRIM_2;
8197 tg3_writephy(tp, MII_TG3_FET_PTEST, ptest);
8198 }
8199 } else
8200 bmcr |= BMCR_LOOPBACK;
8201
5e5a7f37
MC		 8202 tg3_writephy(tp, MII_BMCR, bmcr);
8203
8204 /* The write needs to be flushed for the FETs */
8205 if (tp->phy_flags & TG3_PHYFLG_IS_FET)
8206 tg3_readphy(tp, MII_BMCR, &bmcr);
8207
8208 udelay(40);
8209
8210 if ((tp->phy_flags & TG3_PHYFLG_IS_FET) &&
4153577a 8211 tg3_asic_rev(tp) == ASIC_REV_5785) {
941ec90f 8212 tg3_writephy(tp, MII_TG3_FET_PTEST, ptest |
5e5a7f37
MC		 8213 MII_TG3_FET_PTEST_FRC_TX_LINK |
8214 MII_TG3_FET_PTEST_FRC_TX_LOCK);
8215
8216 /* The write needs to be flushed for the AC131 */
8217 tg3_readphy(tp, MII_TG3_FET_PTEST, &val);
8218 }
8219
8220 /* Reset to prevent losing 1st rx packet intermittently */
8221 if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
8222 tg3_flag(tp, 5780_CLASS)) {
8223 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
8224 udelay(10);
8225 tw32_f(MAC_RX_MODE, tp->rx_mode);
8226 }
8227
8228 mac_mode = tp->mac_mode &
8229 ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
8230 if (speed == SPEED_1000)
8231 mac_mode |= MAC_MODE_PORT_MODE_GMII;
8232 else
8233 mac_mode |= MAC_MODE_PORT_MODE_MII;
8234
4153577a 8235 if (tg3_asic_rev(tp) == ASIC_REV_5700) {
5e5a7f37
MC		 8236 u32 masked_phy_id = tp->phy_id & TG3_PHY_ID_MASK;
8237
8238 if (masked_phy_id == TG3_PHY_ID_BCM5401)
8239 mac_mode &= ~MAC_MODE_LINK_POLARITY;
8240 else if (masked_phy_id == TG3_PHY_ID_BCM5411)
8241 mac_mode |= MAC_MODE_LINK_POLARITY;
8242
8243 tg3_writephy(tp, MII_TG3_EXT_CTRL,
8244 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
8245 }
8246
8247 tw32(MAC_MODE, mac_mode);
8248 udelay(40);
941ec90f
MC		 8249
8250 return 0;
5e5a7f37
MC		 8251}
8252
c8f44aff 8253static void tg3_set_loopback(struct net_device *dev, netdev_features_t features)
06c03c02
MB		 8254{
8255 struct tg3 *tp = netdev_priv(dev);
8256
8257 if (features & NETIF_F_LOOPBACK) {
8258 if (tp->mac_mode & MAC_MODE_PORT_INT_LPBACK)
8259 return;
8260
06c03c02 8261 spin_lock_bh(&tp->lock);
6e01b20b 8262 tg3_mac_loopback(tp, true);
06c03c02
MB		 8263 netif_carrier_on(tp->dev);
8264 spin_unlock_bh(&tp->lock);
8265 netdev_info(dev, "Internal MAC loopback mode enabled.\n");
8266 } else {
8267 if (!(tp->mac_mode & MAC_MODE_PORT_INT_LPBACK))
8268 return;
8269
06c03c02 8270 spin_lock_bh(&tp->lock);
6e01b20b 8271 tg3_mac_loopback(tp, false);
06c03c02 8272 /* Force link status check */
953c96e0 8273 tg3_setup_phy(tp, true);
06c03c02
MB		 8274 spin_unlock_bh(&tp->lock);
8275 netdev_info(dev, "Internal MAC loopback mode disabled.\n");
8276 }
8277}
8278
c8f44aff
MM		 8279static netdev_features_t tg3_fix_features(struct net_device *dev,
8280 netdev_features_t features)
dc668910
MM		 8281{
8282 struct tg3 *tp = netdev_priv(dev);
8283
63c3a66f 8284 if (dev->mtu > ETH_DATA_LEN && tg3_flag(tp, 5780_CLASS))
dc668910
MM		 8285 features &= ~NETIF_F_ALL_TSO;
8286
8287 return features;
8288}
8289
c8f44aff 8290static int tg3_set_features(struct net_device *dev, netdev_features_t features)
06c03c02 8291{
c8f44aff 8292 netdev_features_t changed = dev->features ^ features;
06c03c02
MB		 8293
8294 if ((changed & NETIF_F_LOOPBACK) && netif_running(dev))
8295 tg3_set_loopback(dev, features);
8296
8297 return 0;
8298}
8299
21f581a5
MC		 8300static void tg3_rx_prodring_free(struct tg3 *tp,
8301 struct tg3_rx_prodring_set *tpr)
1da177e4 8302{
1da177e4
LT		 8303 int i;
8304
8fea32b9 8305 if (tpr != &tp->napi[0].prodring) {
b196c7e4 8306 for (i = tpr->rx_std_cons_idx; i != tpr->rx_std_prod_idx;
2c49a44d 8307 i = (i + 1) & tp->rx_std_ring_mask)
9205fd9c 8308 tg3_rx_data_free(tp, &tpr->rx_std_buffers[i],
b196c7e4
MC		 8309 tp->rx_pkt_map_sz);
8310
63c3a66f 8311 if (tg3_flag(tp, JUMBO_CAPABLE)) {
b196c7e4
MC		 8312 for (i = tpr->rx_jmb_cons_idx;
8313 i != tpr->rx_jmb_prod_idx;
2c49a44d 8314 i = (i + 1) & tp->rx_jmb_ring_mask) {
9205fd9c 8315 tg3_rx_data_free(tp, &tpr->rx_jmb_buffers[i],
b196c7e4
MC		 8316 TG3_RX_JMB_MAP_SZ);
8317 }
8318 }
8319
2b2cdb65 8320 return;
b196c7e4 8321 }
1da177e4 8322
2c49a44d 8323 for (i = 0; i <= tp->rx_std_ring_mask; i++)
9205fd9c 8324 tg3_rx_data_free(tp, &tpr->rx_std_buffers[i],
2b2cdb65 8325 tp->rx_pkt_map_sz);
1da177e4 8326
63c3a66f 8327 if (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS)) {
2c49a44d 8328 for (i = 0; i <= tp->rx_jmb_ring_mask; i++)
9205fd9c 8329 tg3_rx_data_free(tp, &tpr->rx_jmb_buffers[i],
2b2cdb65 8330 TG3_RX_JMB_MAP_SZ);
1da177e4
LT		 8331 }
8332}
8333
c6cdf436 8334/* Initialize rx rings for packet processing.
1da177e4
LT		 8335 *
8336 * The chip has been shut down and the driver detached from
8337 * the networking, so no interrupts or new tx packets will
8338 * end up in the driver. tp->{tx,}lock are held and thus
8339 * we may not sleep.
8340 */
21f581a5
MC		 8341static int tg3_rx_prodring_alloc(struct tg3 *tp,
8342 struct tg3_rx_prodring_set *tpr)
1da177e4 8343{
287be12e 8344 u32 i, rx_pkt_dma_sz;
1da177e4 8345
b196c7e4
MC		 8346 tpr->rx_std_cons_idx = 0;
8347 tpr->rx_std_prod_idx = 0;
8348 tpr->rx_jmb_cons_idx = 0;
8349 tpr->rx_jmb_prod_idx = 0;
8350
8fea32b9 8351 if (tpr != &tp->napi[0].prodring) {
2c49a44d
MC		 8352 memset(&tpr->rx_std_buffers[0], 0,
8353 TG3_RX_STD_BUFF_RING_SIZE(tp));
48035728 8354 if (tpr->rx_jmb_buffers)
2b2cdb65 8355 memset(&tpr->rx_jmb_buffers[0], 0,
2c49a44d 8356 TG3_RX_JMB_BUFF_RING_SIZE(tp));
2b2cdb65
MC		 8357 goto done;
8358 }
8359
1da177e4 8360 /* Zero out all descriptors. */
2c49a44d 8361 memset(tpr->rx_std, 0, TG3_RX_STD_RING_BYTES(tp));
1da177e4 8362
287be12e 8363 rx_pkt_dma_sz = TG3_RX_STD_DMA_SZ;
63c3a66f 8364 if (tg3_flag(tp, 5780_CLASS) &&
287be12e
MC		 8365 tp->dev->mtu > ETH_DATA_LEN)
8366 rx_pkt_dma_sz = TG3_RX_JMB_DMA_SZ;
8367 tp->rx_pkt_map_sz = TG3_RX_DMA_TO_MAP_SZ(rx_pkt_dma_sz);
7e72aad4 8368
1da177e4
LT		 8369 /* Initialize invariants of the rings, we only set this
8370 * stuff once. This works because the card does not
8371 * write into the rx buffer posting rings.
8372 */
2c49a44d 8373 for (i = 0; i <= tp->rx_std_ring_mask; i++) {
1da177e4
LT		 8374 struct tg3_rx_buffer_desc *rxd;
8375
21f581a5 8376 rxd = &tpr->rx_std[i];
287be12e 8377 rxd->idx_len = rx_pkt_dma_sz << RXD_LEN_SHIFT;
1da177e4
LT		 8378 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
8379 rxd->opaque = (RXD_OPAQUE_RING_STD |
8380 (i << RXD_OPAQUE_INDEX_SHIFT));
8381 }
8382
1da177e4
LT		 8383 /* Now allocate fresh SKBs for each rx ring. */
8384 for (i = 0; i < tp->rx_pending; i++) {
8d4057a9
ED		 8385 unsigned int frag_size;
8386
8387 if (tg3_alloc_rx_data(tp, tpr, RXD_OPAQUE_RING_STD, i,
8388 &frag_size) < 0) {
5129c3a3
MC		 8389 netdev_warn(tp->dev,
8390 "Using a smaller RX standard ring. Only "
8391 "%d out of %d buffers were allocated "
8392 "successfully\n", i, tp->rx_pending);
32d8c572 8393 if (i == 0)
cf7a7298 8394 goto initfail;
32d8c572 8395 tp->rx_pending = i;
1da177e4 8396 break;
32d8c572 8397 }
1da177e4
LT		 8398 }
8399
63c3a66f 8400 if (!tg3_flag(tp, JUMBO_CAPABLE) || tg3_flag(tp, 5780_CLASS))
cf7a7298
MC		 8401 goto done;
8402
2c49a44d 8403 memset(tpr->rx_jmb, 0, TG3_RX_JMB_RING_BYTES(tp));
cf7a7298 8404
63c3a66f 8405 if (!tg3_flag(tp, JUMBO_RING_ENABLE))
0d86df80 8406 goto done;
cf7a7298 8407
2c49a44d 8408 for (i = 0; i <= tp->rx_jmb_ring_mask; i++) {
0d86df80
MC		 8409 struct tg3_rx_buffer_desc *rxd;
8410
8411 rxd = &tpr->rx_jmb[i].std;
8412 rxd->idx_len = TG3_RX_JMB_DMA_SZ << RXD_LEN_SHIFT;
8413 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
8414 RXD_FLAG_JUMBO;
8415 rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
8416 (i << RXD_OPAQUE_INDEX_SHIFT));
8417 }
8418
8419 for (i = 0; i < tp->rx_jumbo_pending; i++) {
8d4057a9
ED		 8420 unsigned int frag_size;
8421
8422 if (tg3_alloc_rx_data(tp, tpr, RXD_OPAQUE_RING_JUMBO, i,
8423 &frag_size) < 0) {
5129c3a3
MC		 8424 netdev_warn(tp->dev,
8425 "Using a smaller RX jumbo ring. Only %d "
8426 "out of %d buffers were allocated "
8427 "successfully\n", i, tp->rx_jumbo_pending);
0d86df80
MC		 8428 if (i == 0)
8429 goto initfail;
8430 tp->rx_jumbo_pending = i;
8431 break;
1da177e4
LT		 8432 }
8433 }
cf7a7298
MC		 8434
8435done:
32d8c572 8436 return 0;
cf7a7298
MC		 8437
8438initfail:
21f581a5 8439 tg3_rx_prodring_free(tp, tpr);
cf7a7298 8440 return -ENOMEM;
1da177e4
LT		 8441}
8442
21f581a5
MC		 8443static void tg3_rx_prodring_fini(struct tg3 *tp,
8444 struct tg3_rx_prodring_set *tpr)
1da177e4 8445{
21f581a5
MC		 8446 kfree(tpr->rx_std_buffers);
8447 tpr->rx_std_buffers = NULL;
8448 kfree(tpr->rx_jmb_buffers);
8449 tpr->rx_jmb_buffers = NULL;
8450 if (tpr->rx_std) {
4bae65c8
MC		 8451 dma_free_coherent(&tp->pdev->dev, TG3_RX_STD_RING_BYTES(tp),
8452 tpr->rx_std, tpr->rx_std_mapping);
21f581a5 8453 tpr->rx_std = NULL;
1da177e4 8454 }
21f581a5 8455 if (tpr->rx_jmb) {
4bae65c8
MC		 8456 dma_free_coherent(&tp->pdev->dev, TG3_RX_JMB_RING_BYTES(tp),
8457 tpr->rx_jmb, tpr->rx_jmb_mapping);
21f581a5 8458 tpr->rx_jmb = NULL;
1da177e4 8459 }
cf7a7298
MC		 8460}
8461
21f581a5
MC		 8462static int tg3_rx_prodring_init(struct tg3 *tp,
8463 struct tg3_rx_prodring_set *tpr)
cf7a7298 8464{
2c49a44d
MC		 8465 tpr->rx_std_buffers = kzalloc(TG3_RX_STD_BUFF_RING_SIZE(tp),
8466 GFP_KERNEL);
21f581a5 8467 if (!tpr->rx_std_buffers)
cf7a7298
MC		 8468 return -ENOMEM;
8469
4bae65c8
MC		 8470 tpr->rx_std = dma_alloc_coherent(&tp->pdev->dev,
8471 TG3_RX_STD_RING_BYTES(tp),
8472 &tpr->rx_std_mapping,
8473 GFP_KERNEL);
21f581a5 8474 if (!tpr->rx_std)
cf7a7298
MC		 8475 goto err_out;
8476
63c3a66f 8477 if (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS)) {
2c49a44d 8478 tpr->rx_jmb_buffers = kzalloc(TG3_RX_JMB_BUFF_RING_SIZE(tp),
21f581a5
MC		 8479 GFP_KERNEL);
8480 if (!tpr->rx_jmb_buffers)
cf7a7298
MC		 8481 goto err_out;
8482
4bae65c8
MC		 8483 tpr->rx_jmb = dma_alloc_coherent(&tp->pdev->dev,
8484 TG3_RX_JMB_RING_BYTES(tp),
8485 &tpr->rx_jmb_mapping,
8486 GFP_KERNEL);
21f581a5 8487 if (!tpr->rx_jmb)
cf7a7298
MC		 8488 goto err_out;
8489 }
8490
8491 return 0;
8492
8493err_out:
21f581a5 8494 tg3_rx_prodring_fini(tp, tpr);
cf7a7298
MC		 8495 return -ENOMEM;
8496}
8497
8498/* Free up pending packets in all rx/tx rings.
8499 *
8500 * The chip has been shut down and the driver detached from
8501 * the networking, so no interrupts or new tx packets will
8502 * end up in the driver. tp->{tx,}lock is not held and we are not
8503 * in an interrupt context and thus may sleep.
8504 */
8505static void tg3_free_rings(struct tg3 *tp)
8506{
f77a6a8e 8507 int i, j;
cf7a7298 8508
f77a6a8e
MC		 8509 for (j = 0; j < tp->irq_cnt; j++) {
8510 struct tg3_napi *tnapi = &tp->napi[j];
cf7a7298 8511
8fea32b9 8512 tg3_rx_prodring_free(tp, &tnapi->prodring);
b28f6428 8513
0c1d0e2b
MC		 8514 if (!tnapi->tx_buffers)
8515 continue;
8516
0d681b27
MC		 8517 for (i = 0; i < TG3_TX_RING_SIZE; i++) {
8518 struct sk_buff *skb = tnapi->tx_buffers[i].skb;
cf7a7298 8519
0d681b27 8520 if (!skb)
f77a6a8e 8521 continue;
cf7a7298 8522
ba1142e4
MC		 8523 tg3_tx_skb_unmap(tnapi, i,
8524 skb_shinfo(skb)->nr_frags - 1);
f77a6a8e
MC		 8525
8526 dev_kfree_skb_any(skb);
8527 }
5cb917bc 8528 netdev_tx_reset_queue(netdev_get_tx_queue(tp->dev, j));
2b2cdb65 8529 }
cf7a7298
MC		 8530}
8531
8532/* Initialize tx/rx rings for packet processing.
8533 *
8534 * The chip has been shut down and the driver detached from
8535 * the networking, so no interrupts or new tx packets will
8536 * end up in the driver. tp->{tx,}lock are held and thus
8537 * we may not sleep.
8538 */
8539static int tg3_init_rings(struct tg3 *tp)
8540{
f77a6a8e 8541 int i;
72334482 8542
cf7a7298
MC		 8543 /* Free up all the SKBs. */
8544 tg3_free_rings(tp);
8545
f77a6a8e
MC		 8546 for (i = 0; i < tp->irq_cnt; i++) {
8547 struct tg3_napi *tnapi = &tp->napi[i];
8548
8549 tnapi->last_tag = 0;
8550 tnapi->last_irq_tag = 0;
8551 tnapi->hw_status->status = 0;
8552 tnapi->hw_status->status_tag = 0;
8553 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
cf7a7298 8554
f77a6a8e
MC		 8555 tnapi->tx_prod = 0;
8556 tnapi->tx_cons = 0;
0c1d0e2b
MC		 8557 if (tnapi->tx_ring)
8558 memset(tnapi->tx_ring, 0, TG3_TX_RING_BYTES);
f77a6a8e
MC		 8559
8560 tnapi->rx_rcb_ptr = 0;
0c1d0e2b
MC		 8561 if (tnapi->rx_rcb)
8562 memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
2b2cdb65 8563
8fea32b9 8564 if (tg3_rx_prodring_alloc(tp, &tnapi->prodring)) {
e4af1af9 8565 tg3_free_rings(tp);
2b2cdb65 8566 return -ENOMEM;
e4af1af9 8567 }
f77a6a8e 8568 }
72334482 8569
2b2cdb65 8570 return 0;
cf7a7298
MC		 8571}
8572
49a359e3 8573static void tg3_mem_tx_release(struct tg3 *tp)
cf7a7298 8574{
f77a6a8e 8575 int i;
898a56f8 8576
49a359e3 8577 for (i = 0; i < tp->irq_max; i++) {
f77a6a8e
MC		 8578 struct tg3_napi *tnapi = &tp->napi[i];
8579
8580 if (tnapi->tx_ring) {
4bae65c8 8581 dma_free_coherent(&tp->pdev->dev, TG3_TX_RING_BYTES,
f77a6a8e
MC		 8582 tnapi->tx_ring, tnapi->tx_desc_mapping);
8583 tnapi->tx_ring = NULL;
8584 }
8585
8586 kfree(tnapi->tx_buffers);
8587 tnapi->tx_buffers = NULL;
49a359e3
MC		 8588 }
8589}
f77a6a8e 8590
49a359e3
MC		 8591static int tg3_mem_tx_acquire(struct tg3 *tp)
8592{
8593 int i;
8594 struct tg3_napi *tnapi = &tp->napi[0];
8595
8596 /* If multivector TSS is enabled, vector 0 does not handle
8597 * tx interrupts. Don't allocate any resources for it.
8598 */
8599 if (tg3_flag(tp, ENABLE_TSS))
8600 tnapi++;
8601
8602 for (i = 0; i < tp->txq_cnt; i++, tnapi++) {
8603 tnapi->tx_buffers = kzalloc(sizeof(struct tg3_tx_ring_info) *
8604 TG3_TX_RING_SIZE, GFP_KERNEL);
8605 if (!tnapi->tx_buffers)
8606 goto err_out;
8607
8608 tnapi->tx_ring = dma_alloc_coherent(&tp->pdev->dev,
8609 TG3_TX_RING_BYTES,
8610 &tnapi->tx_desc_mapping,
8611 GFP_KERNEL);
8612 if (!tnapi->tx_ring)
8613 goto err_out;
8614 }
8615
8616 return 0;
8617
8618err_out:
8619 tg3_mem_tx_release(tp);
8620 return -ENOMEM;
8621}
8622
8623static void tg3_mem_rx_release(struct tg3 *tp)
8624{
8625 int i;
8626
8627 for (i = 0; i < tp->irq_max; i++) {
8628 struct tg3_napi *tnapi = &tp->napi[i];
f77a6a8e 8629
8fea32b9
MC		 8630 tg3_rx_prodring_fini(tp, &tnapi->prodring);
8631
49a359e3
MC		 8632 if (!tnapi->rx_rcb)
8633 continue;
8634
8635 dma_free_coherent(&tp->pdev->dev,
8636 TG3_RX_RCB_RING_BYTES(tp),
8637 tnapi->rx_rcb,
8638 tnapi->rx_rcb_mapping);
8639 tnapi->rx_rcb = NULL;
8640 }
8641}
8642
8643static int tg3_mem_rx_acquire(struct tg3 *tp)
8644{
8645 unsigned int i, limit;
8646
8647 limit = tp->rxq_cnt;
8648
8649 /* If RSS is enabled, we need a (dummy) producer ring
8650 * set on vector zero. This is the true hw prodring.
8651 */
8652 if (tg3_flag(tp, ENABLE_RSS))
8653 limit++;
8654
8655 for (i = 0; i < limit; i++) {
8656 struct tg3_napi *tnapi = &tp->napi[i];
8657
8658 if (tg3_rx_prodring_init(tp, &tnapi->prodring))
8659 goto err_out;
8660
8661 /* If multivector RSS is enabled, vector 0
8662 * does not handle rx or tx interrupts.
8663 * Don't allocate any resources for it.
8664 */
8665 if (!i && tg3_flag(tp, ENABLE_RSS))
8666 continue;
8667
ede23fa8
JP		 8668 tnapi->rx_rcb = dma_zalloc_coherent(&tp->pdev->dev,
8669 TG3_RX_RCB_RING_BYTES(tp),
8670 &tnapi->rx_rcb_mapping,
8671 GFP_KERNEL);
49a359e3
MC		 8672 if (!tnapi->rx_rcb)
8673 goto err_out;
49a359e3
MC		 8674 }
8675
8676 return 0;
8677
8678err_out:
8679 tg3_mem_rx_release(tp);
8680 return -ENOMEM;
8681}
8682
8683/*
8684 * Must not be invoked with interrupt sources disabled and
8685 * the hardware shutdown down.
8686 */
8687static void tg3_free_consistent(struct tg3 *tp)
8688{
8689 int i;
8690
8691 for (i = 0; i < tp->irq_cnt; i++) {
8692 struct tg3_napi *tnapi = &tp->napi[i];
8693
f77a6a8e 8694 if (tnapi->hw_status) {
4bae65c8
MC		 8695 dma_free_coherent(&tp->pdev->dev, TG3_HW_STATUS_SIZE,
8696 tnapi->hw_status,
8697 tnapi->status_mapping);
f77a6a8e
MC		 8698 tnapi->hw_status = NULL;
8699 }
1da177e4 8700 }
f77a6a8e 8701
49a359e3
MC		 8702 tg3_mem_rx_release(tp);
8703 tg3_mem_tx_release(tp);
8704
1da177e4 8705 if (tp->hw_stats) {
4bae65c8
MC		 8706 dma_free_coherent(&tp->pdev->dev, sizeof(struct tg3_hw_stats),
8707 tp->hw_stats, tp->stats_mapping);
1da177e4
LT		 8708 tp->hw_stats = NULL;
8709 }
8710}
8711
8712/*
8713 * Must not be invoked with interrupt sources disabled and
8714 * the hardware shutdown down. Can sleep.
8715 */
8716static int tg3_alloc_consistent(struct tg3 *tp)
8717{
f77a6a8e 8718 int i;
898a56f8 8719
ede23fa8
JP		 8720 tp->hw_stats = dma_zalloc_coherent(&tp->pdev->dev,
8721 sizeof(struct tg3_hw_stats),
8722 &tp->stats_mapping, GFP_KERNEL);
f77a6a8e 8723 if (!tp->hw_stats)
1da177e4
LT		 8724 goto err_out;
8725
f77a6a8e
MC		 8726 for (i = 0; i < tp->irq_cnt; i++) {
8727 struct tg3_napi *tnapi = &tp->napi[i];
8d9d7cfc 8728 struct tg3_hw_status *sblk;
1da177e4 8729
ede23fa8
JP		 8730 tnapi->hw_status = dma_zalloc_coherent(&tp->pdev->dev,
8731 TG3_HW_STATUS_SIZE,
8732 &tnapi->status_mapping,
8733 GFP_KERNEL);
f77a6a8e
MC		 8734 if (!tnapi->hw_status)
8735 goto err_out;
898a56f8 8736
8d9d7cfc
MC		 8737 sblk = tnapi->hw_status;
8738
49a359e3 8739 if (tg3_flag(tp, ENABLE_RSS)) {
86449944 8740 u16 *prodptr = NULL;
8fea32b9 8741
49a359e3
MC		 8742 /*
8743 * When RSS is enabled, the status block format changes
8744 * slightly. The "rx_jumbo_consumer", "reserved",
8745 * and "rx_mini_consumer" members get mapped to the
8746 * other three rx return ring producer indexes.
8747 */
8748 switch (i) {
8749 case 1:
8750 prodptr = &sblk->idx[0].rx_producer;
8751 break;
8752 case 2:
8753 prodptr = &sblk->rx_jumbo_consumer;
8754 break;
8755 case 3:
8756 prodptr = &sblk->reserved;
8757 break;
8758 case 4:
8759 prodptr = &sblk->rx_mini_consumer;
f891ea16
MC		 8760 break;
8761 }
49a359e3
MC		 8762 tnapi->rx_rcb_prod_idx = prodptr;
8763 } else {
8d9d7cfc 8764 tnapi->rx_rcb_prod_idx = &sblk->idx[0].rx_producer;
8d9d7cfc 8765 }
f77a6a8e 8766 }
1da177e4 8767
49a359e3
MC		 8768 if (tg3_mem_tx_acquire(tp) || tg3_mem_rx_acquire(tp))
8769 goto err_out;
8770
1da177e4
LT		 8771 return 0;
8772
8773err_out:
8774 tg3_free_consistent(tp);
8775 return -ENOMEM;
8776}
8777
8778#define MAX_WAIT_CNT 1000
8779
8780/* To stop a block, clear the enable bit and poll till it
8781 * clears. tp->lock is held.
8782 */
953c96e0 8783static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, bool silent)
1da177e4
LT		 8784{
8785 unsigned int i;
8786 u32 val;
8787
63c3a66f 8788 if (tg3_flag(tp, 5705_PLUS)) {
1da177e4
LT		 8789 switch (ofs) {
8790 case RCVLSC_MODE:
8791 case DMAC_MODE:
8792 case MBFREE_MODE:
8793 case BUFMGR_MODE:
8794 case MEMARB_MODE:
8795 /* We can't enable/disable these bits of the
8796 * 5705/5750, just say success.
8797 */
8798 return 0;
8799
8800 default:
8801 break;
855e1111 8802 }
1da177e4
LT		 8803 }
8804
8805 val = tr32(ofs);
8806 val &= ~enable_bit;
8807 tw32_f(ofs, val);
8808
8809 for (i = 0; i < MAX_WAIT_CNT; i++) {
6d446ec3
GS		 8810 if (pci_channel_offline(tp->pdev)) {
8811 dev_err(&tp->pdev->dev,
8812 "tg3_stop_block device offline, "
8813 "ofs=%lx enable_bit=%x\n",
8814 ofs, enable_bit);
8815 return -ENODEV;
8816 }
8817
1da177e4
LT		 8818 udelay(100);
8819 val = tr32(ofs);
8820 if ((val & enable_bit) == 0)
8821 break;
8822 }
8823
b3b7d6be 8824 if (i == MAX_WAIT_CNT && !silent) {
2445e461
MC		 8825 dev_err(&tp->pdev->dev,
8826 "tg3_stop_block timed out, ofs=%lx enable_bit=%x\n",
8827 ofs, enable_bit);
1da177e4
LT		 8828 return -ENODEV;
8829 }
8830
8831 return 0;
8832}
8833
8834/* tp->lock is held. */
953c96e0 8835static int tg3_abort_hw(struct tg3 *tp, bool silent)
1da177e4
LT		 8836{
8837 int i, err;
8838
8839 tg3_disable_ints(tp);
8840
6d446ec3
GS		 8841 if (pci_channel_offline(tp->pdev)) {
8842 tp->rx_mode &= ~(RX_MODE_ENABLE | TX_MODE_ENABLE);
8843 tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
8844 err = -ENODEV;
8845 goto err_no_dev;
8846 }
8847
1da177e4
LT		 8848 tp->rx_mode &= ~RX_MODE_ENABLE;
8849 tw32_f(MAC_RX_MODE, tp->rx_mode);
8850 udelay(10);
8851
b3b7d6be
DM		 8852 err = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
8853 err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
8854 err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
8855 err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
8856 err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
8857 err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
8858
8859 err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
8860 err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
8861 err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
8862 err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
8863 err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
8864 err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
8865 err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
1da177e4
LT		 8866
8867 tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
8868 tw32_f(MAC_MODE, tp->mac_mode);
8869 udelay(40);
8870
8871 tp->tx_mode &= ~TX_MODE_ENABLE;
8872 tw32_f(MAC_TX_MODE, tp->tx_mode);
8873
8874 for (i = 0; i < MAX_WAIT_CNT; i++) {
8875 udelay(100);
8876 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
8877 break;
8878 }
8879 if (i >= MAX_WAIT_CNT) {
ab96b241
MC		 8880 dev_err(&tp->pdev->dev,
8881 "%s timed out, TX_MODE_ENABLE will not clear "
8882 "MAC_TX_MODE=%08x\n", __func__, tr32(MAC_TX_MODE));
e6de8ad1 8883 err |= -ENODEV;
1da177e4
LT		 8884 }
8885
e6de8ad1 8886 err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
b3b7d6be
DM		 8887 err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
8888 err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
1da177e4
LT		 8889
8890 tw32(FTQ_RESET, 0xffffffff);
8891 tw32(FTQ_RESET, 0x00000000);
8892
b3b7d6be
DM		 8893 err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
8894 err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
1da177e4 8895
6d446ec3 8896err_no_dev:
f77a6a8e
MC		 8897 for (i = 0; i < tp->irq_cnt; i++) {
8898 struct tg3_napi *tnapi = &tp->napi[i];
8899 if (tnapi->hw_status)
8900 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
8901 }
1da177e4 8902
1da177e4
LT		 8903 return err;
8904}
8905
ee6a99b5
MC		 8906/* Save PCI command register before chip reset */
8907static void tg3_save_pci_state(struct tg3 *tp)
8908{
8a6eac90 8909 pci_read_config_word(tp->pdev, PCI_COMMAND, &tp->pci_cmd);
ee6a99b5
MC		 8910}
8911
8912/* Restore PCI state after chip reset */
8913static void tg3_restore_pci_state(struct tg3 *tp)
8914{
8915 u32 val;
8916
8917 /* Re-enable indirect register accesses. */
8918 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
8919 tp->misc_host_ctrl);
8920
8921 /* Set MAX PCI retry to zero. */
8922 val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
4153577a 8923 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5704_A0 &&
63c3a66f 8924 tg3_flag(tp, PCIX_MODE))
ee6a99b5 8925 val |= PCISTATE_RETRY_SAME_DMA;
0d3031d9 8926 /* Allow reads and writes to the APE register and memory space. */
63c3a66f 8927 if (tg3_flag(tp, ENABLE_APE))
0d3031d9 8928 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
f92d9dc1
MC		 8929 PCISTATE_ALLOW_APE_SHMEM_WR |
8930 PCISTATE_ALLOW_APE_PSPACE_WR;
ee6a99b5
MC		 8931 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
8932
8a6eac90 8933 pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd);
ee6a99b5 8934
2c55a3d0
MC		 8935 if (!tg3_flag(tp, PCI_EXPRESS)) {
8936 pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
8937 tp->pci_cacheline_sz);
8938 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
8939 tp->pci_lat_timer);
114342f2 8940 }
5f5c51e3 8941
ee6a99b5 8942 /* Make sure PCI-X relaxed ordering bit is clear. */
63c3a66f 8943 if (tg3_flag(tp, PCIX_MODE)) {
9974a356
MC		 8944 u16 pcix_cmd;
8945
8946 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
8947 &pcix_cmd);
8948 pcix_cmd &= ~PCI_X_CMD_ERO;
8949 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
8950 pcix_cmd);
8951 }
ee6a99b5 8952
63c3a66f 8953 if (tg3_flag(tp, 5780_CLASS)) {
ee6a99b5
MC		 8954
8955 /* Chip reset on 5780 will reset MSI enable bit,
8956 * so need to restore it.
8957 */
63c3a66f 8958 if (tg3_flag(tp, USING_MSI)) {
ee6a99b5
MC		 8959 u16 ctrl;
8960
8961 pci_read_config_word(tp->pdev,
8962 tp->msi_cap + PCI_MSI_FLAGS,
8963 &ctrl);
8964 pci_write_config_word(tp->pdev,
8965 tp->msi_cap + PCI_MSI_FLAGS,
8966 ctrl | PCI_MSI_FLAGS_ENABLE);
8967 val = tr32(MSGINT_MODE);
8968 tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
8969 }
8970 }
8971}
8972
f82995b6
NS		 8973static void tg3_override_clk(struct tg3 *tp)
8974{
8975 u32 val;
8976
8977 switch (tg3_asic_rev(tp)) {
8978 case ASIC_REV_5717:
8979 val = tr32(TG3_CPMU_CLCK_ORIDE_ENABLE);
8980 tw32(TG3_CPMU_CLCK_ORIDE_ENABLE, val |
8981 TG3_CPMU_MAC_ORIDE_ENABLE);
8982 break;
8983
8984 case ASIC_REV_5719:
8985 case ASIC_REV_5720:
8986 tw32(TG3_CPMU_CLCK_ORIDE, CPMU_CLCK_ORIDE_MAC_ORIDE_EN);
8987 break;
8988
8989 default:
8990 return;
8991 }
8992}
8993
8994static void tg3_restore_clk(struct tg3 *tp)
8995{
8996 u32 val;
8997
8998 switch (tg3_asic_rev(tp)) {
8999 case ASIC_REV_5717:
9000 val = tr32(TG3_CPMU_CLCK_ORIDE_ENABLE);
9001 tw32(TG3_CPMU_CLCK_ORIDE_ENABLE,
9002 val & ~TG3_CPMU_MAC_ORIDE_ENABLE);
9003 break;
9004
9005 case ASIC_REV_5719:
9006 case ASIC_REV_5720:
9007 val = tr32(TG3_CPMU_CLCK_ORIDE);
9008 tw32(TG3_CPMU_CLCK_ORIDE, val & ~CPMU_CLCK_ORIDE_MAC_ORIDE_EN);
9009 break;
9010
9011 default:
9012 return;
9013 }
9014}
9015
1da177e4
LT		 9016/* tp->lock is held. */
9017static int tg3_chip_reset(struct tg3 *tp)
9018{
9019 u32 val;
1ee582d8 9020 void (*write_op)(struct tg3 *, u32, u32);
4f125f42 9021 int i, err;
1da177e4 9022
8496e85c
RW		 9023 if (!pci_device_is_present(tp->pdev))
9024 return -ENODEV;
9025
f49639e6
DM		 9026 tg3_nvram_lock(tp);
9027
77b483f1
MC		 9028 tg3_ape_lock(tp, TG3_APE_LOCK_GRC);
9029
f49639e6
DM		 9030 /* No matching tg3_nvram_unlock() after this because
9031 * chip reset below will undo the nvram lock.
9032 */
9033 tp->nvram_lock_cnt = 0;
1da177e4 9034
ee6a99b5
MC		 9035 /* GRC_MISC_CFG core clock reset will clear the memory
9036 * enable bit in PCI register 4 and the MSI enable bit
9037 * on some chips, so we save relevant registers here.
9038 */
9039 tg3_save_pci_state(tp);
9040
4153577a 9041 if (tg3_asic_rev(tp) == ASIC_REV_5752 ||
63c3a66f 9042 tg3_flag(tp, 5755_PLUS))
d9ab5ad1
MC		 9043 tw32(GRC_FASTBOOT_PC, 0);
9044
1da177e4
LT		 9045 /*
9046 * We must avoid the readl() that normally takes place.
9047 * It locks machines, causes machine checks, and other
9048 * fun things. So, temporarily disable the 5701
9049 * hardware workaround, while we do the reset.
9050 */
1ee582d8
MC		 9051 write_op = tp->write32;
9052 if (write_op == tg3_write_flush_reg32)
9053 tp->write32 = tg3_write32;
1da177e4 9054
d18edcb2
MC		 9055 /* Prevent the irq handler from reading or writing PCI registers
9056 * during chip reset when the memory enable bit in the PCI command
9057 * register may be cleared. The chip does not generate interrupt
9058 * at this time, but the irq handler may still be called due to irq
9059 * sharing or irqpoll.
9060 */
63c3a66f 9061 tg3_flag_set(tp, CHIP_RESETTING);
f77a6a8e
MC		 9062 for (i = 0; i < tp->irq_cnt; i++) {
9063 struct tg3_napi *tnapi = &tp->napi[i];
9064 if (tnapi->hw_status) {
9065 tnapi->hw_status->status = 0;
9066 tnapi->hw_status->status_tag = 0;
9067 }
9068 tnapi->last_tag = 0;
9069 tnapi->last_irq_tag = 0;
b8fa2f3a 9070 }
d18edcb2 9071 smp_mb();
4f125f42
MC		 9072
9073 for (i = 0; i < tp->irq_cnt; i++)
9074 synchronize_irq(tp->napi[i].irq_vec);
d18edcb2 9075
4153577a 9076 if (tg3_asic_rev(tp) == ASIC_REV_57780) {
255ca311
MC		 9077 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
9078 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
9079 }
9080
1da177e4
LT		 9081 /* do the reset */
9082 val = GRC_MISC_CFG_CORECLK_RESET;
9083
63c3a66f 9084 if (tg3_flag(tp, PCI_EXPRESS)) {
88075d91 9085 /* Force PCIe 1.0a mode */
4153577a 9086 if (tg3_asic_rev(tp) != ASIC_REV_5785 &&
63c3a66f 9087 !tg3_flag(tp, 57765_PLUS) &&
88075d91
MC		 9088 tr32(TG3_PCIE_PHY_TSTCTL) ==
9089 (TG3_PCIE_PHY_TSTCTL_PCIE10 | TG3_PCIE_PHY_TSTCTL_PSCRAM))
9090 tw32(TG3_PCIE_PHY_TSTCTL, TG3_PCIE_PHY_TSTCTL_PSCRAM);
9091
4153577a 9092 if (tg3_chip_rev_id(tp) != CHIPREV_ID_5750_A0) {
1da177e4
LT		 9093 tw32(GRC_MISC_CFG, (1 << 29));
9094 val |= (1 << 29);
9095 }
9096 }
9097
4153577a 9098 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
b5d3772c
MC		 9099 tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET);
9100 tw32(GRC_VCPU_EXT_CTRL,
9101 tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU);
9102 }
9103
f82995b6
NS		 9104 /* Set the clock to the highest frequency to avoid timeouts. With link
9105 * aware mode, the clock speed could be slow and bootcode does not
9106 * complete within the expected time. Override the clock to allow the
9107 * bootcode to finish sooner and then restore it.
9108 */
9109 tg3_override_clk(tp);
9110
f37500d3 9111 /* Manage gphy power for all CPMU absent PCIe devices. */
63c3a66f 9112 if (tg3_flag(tp, 5705_PLUS) && !tg3_flag(tp, CPMU_PRESENT))
1da177e4 9113 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
f37500d3 9114
1da177e4
LT		 9115 tw32(GRC_MISC_CFG, val);
9116
1ee582d8
MC		 9117 /* restore 5701 hardware bug workaround write method */
9118 tp->write32 = write_op;
1da177e4
LT		 9119
9120 /* Unfortunately, we have to delay before the PCI read back.
9121 * Some 575X chips even will not respond to a PCI cfg access
9122 * when the reset command is given to the chip.
9123 *
9124 * How do these hardware designers expect things to work
9125 * properly if the PCI write is posted for a long period
9126 * of time? It is always necessary to have some method by
9127 * which a register read back can occur to push the write
9128 * out which does the reset.
9129 *
9130 * For most tg3 variants the trick below was working.
9131 * Ho hum...
9132 */
9133 udelay(120);
9134
9135 /* Flush PCI posted writes. The normal MMIO registers
9136 * are inaccessible at this time so this is the only
9137 * way to make this reliably (actually, this is no longer
9138 * the case, see above). I tried to use indirect
9139 * register read/write but this upset some 5701 variants.
9140 */
9141 pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
9142
9143 udelay(120);
9144
0f49bfbd 9145 if (tg3_flag(tp, PCI_EXPRESS) && pci_is_pcie(tp->pdev)) {
e7126997
MC		 9146 u16 val16;
9147
4153577a 9148 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5750_A0) {
86449944 9149 int j;
1da177e4
LT		 9150 u32 cfg_val;
9151
9152 /* Wait for link training to complete. */
86449944 9153 for (j = 0; j < 5000; j++)
1da177e4
LT		 9154 udelay(100);
9155
9156 pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
9157 pci_write_config_dword(tp->pdev, 0xc4,
9158 cfg_val | (1 << 15));
9159 }
5e7dfd0f 9160
e7126997 9161 /* Clear the "no snoop" and "relaxed ordering" bits. */
0f49bfbd 9162 val16 = PCI_EXP_DEVCTL_RELAX_EN | PCI_EXP_DEVCTL_NOSNOOP_EN;
e7126997
MC		 9163 /*
9164 * Older PCIe devices only support the 128 byte
9165 * MPS setting. Enforce the restriction.
5e7dfd0f 9166 */
63c3a66f 9167 if (!tg3_flag(tp, CPMU_PRESENT))
0f49bfbd
JL		 9168 val16 |= PCI_EXP_DEVCTL_PAYLOAD;
9169 pcie_capability_clear_word(tp->pdev, PCI_EXP_DEVCTL, val16);
5e7dfd0f 9170
5e7dfd0f 9171 /* Clear error status */
0f49bfbd 9172 pcie_capability_write_word(tp->pdev, PCI_EXP_DEVSTA,
5e7dfd0f
MC		 9173 PCI_EXP_DEVSTA_CED |
9174 PCI_EXP_DEVSTA_NFED |
9175 PCI_EXP_DEVSTA_FED |
9176 PCI_EXP_DEVSTA_URD);
1da177e4
LT		 9177 }
9178
ee6a99b5 9179 tg3_restore_pci_state(tp);
1da177e4 9180
63c3a66f
JP		 9181 tg3_flag_clear(tp, CHIP_RESETTING);
9182 tg3_flag_clear(tp, ERROR_PROCESSED);
d18edcb2 9183
ee6a99b5 9184 val = 0;
63c3a66f 9185 if (tg3_flag(tp, 5780_CLASS))
4cf78e4f 9186 val = tr32(MEMARB_MODE);
ee6a99b5 9187 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
1da177e4 9188
4153577a 9189 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5750_A3) {
1da177e4
LT		 9190 tg3_stop_fw(tp);
9191 tw32(0x5000, 0x400);
9192 }
9193
7e6c63f0
HM		 9194 if (tg3_flag(tp, IS_SSB_CORE)) {
9195 /*
9196 * BCM4785: In order to avoid repercussions from using
9197 * potentially defective internal ROM, stop the Rx RISC CPU,
9198 * which is not required.
9199 */
9200 tg3_stop_fw(tp);
9201 tg3_halt_cpu(tp, RX_CPU_BASE);
9202 }
9203
fb03a43f
NS		 9204 err = tg3_poll_fw(tp);
9205 if (err)
9206 return err;
9207
1da177e4
LT		 9208 tw32(GRC_MODE, tp->grc_mode);
9209
4153577a 9210 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5705_A0) {
ab0049b4 9211 val = tr32(0xc4);
1da177e4
LT		 9212
9213 tw32(0xc4, val | (1 << 15));
9214 }
9215
9216 if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
4153577a 9217 tg3_asic_rev(tp) == ASIC_REV_5705) {
1da177e4 9218 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
4153577a 9219 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5705_A0)
1da177e4
LT		 9220 tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
9221 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
9222 }
9223
f07e9af3 9224 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
9e975cc2 9225 tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
d2394e6b 9226 val = tp->mac_mode;
f07e9af3 9227 } else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) {
9e975cc2 9228 tp->mac_mode = MAC_MODE_PORT_MODE_GMII;
d2394e6b 9229 val = tp->mac_mode;
1da177e4 9230 } else
d2394e6b
MC		 9231 val = 0;
9232
9233 tw32_f(MAC_MODE, val);
1da177e4
LT		 9234 udelay(40);
9235
77b483f1
MC		 9236 tg3_ape_unlock(tp, TG3_APE_LOCK_GRC);
9237
0a9140cf
MC		 9238 tg3_mdio_start(tp);
9239
63c3a66f 9240 if (tg3_flag(tp, PCI_EXPRESS) &&
4153577a
JP		 9241 tg3_chip_rev_id(tp) != CHIPREV_ID_5750_A0 &&
9242 tg3_asic_rev(tp) != ASIC_REV_5785 &&
63c3a66f 9243 !tg3_flag(tp, 57765_PLUS)) {
ab0049b4 9244 val = tr32(0x7c00);
1da177e4
LT		 9245
9246 tw32(0x7c00, val | (1 << 25));
9247 }
9248
f82995b6 9249 tg3_restore_clk(tp);
d78b59f5 9250
1da177e4 9251 /* Reprobe ASF enable state. */
63c3a66f 9252 tg3_flag_clear(tp, ENABLE_ASF);
942d1af0
NS		 9253 tp->phy_flags &= ~(TG3_PHYFLG_1G_ON_VAUX_OK |
9254 TG3_PHYFLG_KEEP_LINK_ON_PWRDN);
9255
63c3a66f 9256 tg3_flag_clear(tp, ASF_NEW_HANDSHAKE);
1da177e4
LT		 9257 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
9258 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
9259 u32 nic_cfg;
9260
9261 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
9262 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
63c3a66f 9263 tg3_flag_set(tp, ENABLE_ASF);
4ba526ce 9264 tp->last_event_jiffies = jiffies;
63c3a66f
JP		 9265 if (tg3_flag(tp, 5750_PLUS))
9266 tg3_flag_set(tp, ASF_NEW_HANDSHAKE);
942d1af0
NS		 9267
9268 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &nic_cfg);
9269 if (nic_cfg & NIC_SRAM_1G_ON_VAUX_OK)
9270 tp->phy_flags |= TG3_PHYFLG_1G_ON_VAUX_OK;
9271 if (nic_cfg & NIC_SRAM_LNK_FLAP_AVOID)
9272 tp->phy_flags |= TG3_PHYFLG_KEEP_LINK_ON_PWRDN;
1da177e4
LT		 9273 }
9274 }
9275
9276 return 0;
9277}
9278
65ec698d
MC		 9279static void tg3_get_nstats(struct tg3 *, struct rtnl_link_stats64 *);
9280static void tg3_get_estats(struct tg3 *, struct tg3_ethtool_stats *);
e565eec3 9281static void __tg3_set_rx_mode(struct net_device *);
92feeabf 9282
1da177e4 9283/* tp->lock is held. */
953c96e0 9284static int tg3_halt(struct tg3 *tp, int kind, bool silent)
1da177e4
LT		 9285{
9286 int err;
9287
9288 tg3_stop_fw(tp);
9289
944d980e 9290 tg3_write_sig_pre_reset(tp, kind);
1da177e4 9291
b3b7d6be 9292 tg3_abort_hw(tp, silent);
1da177e4
LT		 9293 err = tg3_chip_reset(tp);
9294
953c96e0 9295 __tg3_set_mac_addr(tp, false);
daba2a63 9296
944d980e
MC		 9297 tg3_write_sig_legacy(tp, kind);
9298 tg3_write_sig_post_reset(tp, kind);
1da177e4 9299
92feeabf
MC		 9300 if (tp->hw_stats) {
9301 /* Save the stats across chip resets... */
b4017c53 9302 tg3_get_nstats(tp, &tp->net_stats_prev);
92feeabf
MC		 9303 tg3_get_estats(tp, &tp->estats_prev);
9304
9305 /* And make sure the next sample is new data */
9306 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
9307 }
9308
4bc814ab 9309 return err;
1da177e4
LT		 9310}
9311
1da177e4
LT		 9312static int tg3_set_mac_addr(struct net_device *dev, void *p)
9313{
9314 struct tg3 *tp = netdev_priv(dev);
9315 struct sockaddr *addr = p;
953c96e0
JP		 9316 int err = 0;
9317 bool skip_mac_1 = false;
1da177e4 9318
f9804ddb 9319 if (!is_valid_ether_addr(addr->sa_data))
504f9b5a 9320 return -EADDRNOTAVAIL;
f9804ddb 9321
1da177e4
LT		 9322 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
9323
e75f7c90
MC		 9324 if (!netif_running(dev))
9325 return 0;
9326
63c3a66f 9327 if (tg3_flag(tp, ENABLE_ASF)) {
986e0aeb 9328 u32 addr0_high, addr0_low, addr1_high, addr1_low;
58712ef9 9329
986e0aeb
MC		 9330 addr0_high = tr32(MAC_ADDR_0_HIGH);
9331 addr0_low = tr32(MAC_ADDR_0_LOW);
9332 addr1_high = tr32(MAC_ADDR_1_HIGH);
9333 addr1_low = tr32(MAC_ADDR_1_LOW);
9334
9335 /* Skip MAC addr 1 if ASF is using it. */
9336 if ((addr0_high != addr1_high || addr0_low != addr1_low) &&
9337 !(addr1_high == 0 && addr1_low == 0))
953c96e0 9338 skip_mac_1 = true;
58712ef9 9339 }
986e0aeb
MC		 9340 spin_lock_bh(&tp->lock);
9341 __tg3_set_mac_addr(tp, skip_mac_1);
e565eec3 9342 __tg3_set_rx_mode(dev);
986e0aeb 9343 spin_unlock_bh(&tp->lock);
1da177e4 9344
b9ec6c1b 9345 return err;
1da177e4
LT		 9346}
9347
9348/* tp->lock is held. */
9349static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
9350 dma_addr_t mapping, u32 maxlen_flags,
9351 u32 nic_addr)
9352{
9353 tg3_write_mem(tp,
9354 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
9355 ((u64) mapping >> 32));
9356 tg3_write_mem(tp,
9357 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
9358 ((u64) mapping & 0xffffffff));
9359 tg3_write_mem(tp,
9360 (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
9361 maxlen_flags);
9362
63c3a66f 9363 if (!tg3_flag(tp, 5705_PLUS))
1da177e4
LT		 9364 tg3_write_mem(tp,
9365 (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
9366 nic_addr);
9367}
9368
a489b6d9
MC		 9369
9370static void tg3_coal_tx_init(struct tg3 *tp, struct ethtool_coalesce *ec)
15f9850d 9371{
a489b6d9 9372 int i = 0;
b6080e12 9373
63c3a66f 9374 if (!tg3_flag(tp, ENABLE_TSS)) {
b6080e12
MC		 9375 tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
9376 tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
9377 tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
b6080e12
MC		 9378 } else {
9379 tw32(HOSTCC_TXCOL_TICKS, 0);
9380 tw32(HOSTCC_TXMAX_FRAMES, 0);
9381 tw32(HOSTCC_TXCOAL_MAXF_INT, 0);
a489b6d9
MC		 9382
9383 for (; i < tp->txq_cnt; i++) {
9384 u32 reg;
9385
9386 reg = HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18;
9387 tw32(reg, ec->tx_coalesce_usecs);
9388 reg = HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18;
9389 tw32(reg, ec->tx_max_coalesced_frames);
9390 reg = HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18;
9391 tw32(reg, ec->tx_max_coalesced_frames_irq);
9392 }
19cfaecc 9393 }
b6080e12 9394
a489b6d9
MC		 9395 for (; i < tp->irq_max - 1; i++) {
9396 tw32(HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18, 0);
9397 tw32(HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18, 0);
9398 tw32(HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
9399 }
9400}
9401
9402static void tg3_coal_rx_init(struct tg3 *tp, struct ethtool_coalesce *ec)
9403{
9404 int i = 0;
9405 u32 limit = tp->rxq_cnt;
9406
63c3a66f 9407 if (!tg3_flag(tp, ENABLE_RSS)) {
19cfaecc
MC		 9408 tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
9409 tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
9410 tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
a489b6d9 9411 limit--;
19cfaecc 9412 } else {
b6080e12
MC		 9413 tw32(HOSTCC_RXCOL_TICKS, 0);
9414 tw32(HOSTCC_RXMAX_FRAMES, 0);
9415 tw32(HOSTCC_RXCOAL_MAXF_INT, 0);
15f9850d 9416 }
b6080e12 9417
a489b6d9 9418 for (; i < limit; i++) {
b6080e12
MC		 9419 u32 reg;
9420
9421 reg = HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18;
9422 tw32(reg, ec->rx_coalesce_usecs);
b6080e12
MC		 9423 reg = HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18;
9424 tw32(reg, ec->rx_max_coalesced_frames);
b6080e12
MC		 9425 reg = HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18;
9426 tw32(reg, ec->rx_max_coalesced_frames_irq);
b6080e12
MC		 9427 }
9428
9429 for (; i < tp->irq_max - 1; i++) {
9430 tw32(HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18, 0);
b6080e12 9431 tw32(HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18, 0);
b6080e12 9432 tw32(HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
a489b6d9
MC		 9433 }
9434}
19cfaecc 9435
a489b6d9
MC		 9436static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
9437{
9438 tg3_coal_tx_init(tp, ec);
9439 tg3_coal_rx_init(tp, ec);
9440
9441 if (!tg3_flag(tp, 5705_PLUS)) {
9442 u32 val = ec->stats_block_coalesce_usecs;
9443
9444 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
9445 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
9446
f4a46d1f 9447 if (!tp->link_up)
a489b6d9
MC		 9448 val = 0;
9449
9450 tw32(HOSTCC_STAT_COAL_TICKS, val);
b6080e12 9451 }
15f9850d 9452}
1da177e4 9453
328947ff
NS		 9454/* tp->lock is held. */
9455static void tg3_tx_rcbs_disable(struct tg3 *tp)
9456{
9457 u32 txrcb, limit;
9458
9459 /* Disable all transmit rings but the first. */
9460 if (!tg3_flag(tp, 5705_PLUS))
9461 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 16;
9462 else if (tg3_flag(tp, 5717_PLUS))
9463 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 4;
9464 else if (tg3_flag(tp, 57765_CLASS) ||
9465 tg3_asic_rev(tp) == ASIC_REV_5762)
9466 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 2;
9467 else
9468 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
9469
9470 for (txrcb = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
9471 txrcb < limit; txrcb += TG3_BDINFO_SIZE)
9472 tg3_write_mem(tp, txrcb + TG3_BDINFO_MAXLEN_FLAGS,
9473 BDINFO_FLAGS_DISABLED);
9474}
9475
32ba19ef
NS		 9476/* tp->lock is held. */
9477static void tg3_tx_rcbs_init(struct tg3 *tp)
9478{
9479 int i = 0;
9480 u32 txrcb = NIC_SRAM_SEND_RCB;
9481
9482 if (tg3_flag(tp, ENABLE_TSS))
9483 i++;
9484
9485 for (; i < tp->irq_max; i++, txrcb += TG3_BDINFO_SIZE) {
9486 struct tg3_napi *tnapi = &tp->napi[i];
9487
9488 if (!tnapi->tx_ring)
9489 continue;
9490
9491 tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
9492 (TG3_TX_RING_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT),
9493 NIC_SRAM_TX_BUFFER_DESC);
9494 }
9495}
9496
328947ff
NS		 9497/* tp->lock is held. */
9498static void tg3_rx_ret_rcbs_disable(struct tg3 *tp)
9499{
9500 u32 rxrcb, limit;
9501
9502 /* Disable all receive return rings but the first. */
9503 if (tg3_flag(tp, 5717_PLUS))
9504 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 17;
9505 else if (!tg3_flag(tp, 5705_PLUS))
9506 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 16;
9507 else if (tg3_asic_rev(tp) == ASIC_REV_5755 ||
9508 tg3_asic_rev(tp) == ASIC_REV_5762 ||
9509 tg3_flag(tp, 57765_CLASS))
9510 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 4;
9511 else
9512 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
9513
9514 for (rxrcb = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
9515 rxrcb < limit; rxrcb += TG3_BDINFO_SIZE)
9516 tg3_write_mem(tp, rxrcb + TG3_BDINFO_MAXLEN_FLAGS,
9517 BDINFO_FLAGS_DISABLED);
9518}
9519
32ba19ef
NS		 9520/* tp->lock is held. */
9521static void tg3_rx_ret_rcbs_init(struct tg3 *tp)
9522{
9523 int i = 0;
9524 u32 rxrcb = NIC_SRAM_RCV_RET_RCB;
9525
9526 if (tg3_flag(tp, ENABLE_RSS))
9527 i++;
9528
9529 for (; i < tp->irq_max; i++, rxrcb += TG3_BDINFO_SIZE) {
9530 struct tg3_napi *tnapi = &tp->napi[i];
9531
9532 if (!tnapi->rx_rcb)
9533 continue;
9534
9535 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
9536 (tp->rx_ret_ring_mask + 1) <<
9537 BDINFO_FLAGS_MAXLEN_SHIFT, 0);
9538 }
9539}
9540
2d31ecaf
MC		 9541/* tp->lock is held. */
9542static void tg3_rings_reset(struct tg3 *tp)
9543{
9544 int i;
328947ff 9545 u32 stblk;
2d31ecaf
MC		 9546 struct tg3_napi *tnapi = &tp->napi[0];
9547
328947ff 9548 tg3_tx_rcbs_disable(tp);
2d31ecaf 9549
328947ff 9550 tg3_rx_ret_rcbs_disable(tp);
2d31ecaf
MC		 9551
9552 /* Disable interrupts */
9553 tw32_mailbox_f(tp->napi[0].int_mbox, 1);
0e6cf6a9
MC		 9554 tp->napi[0].chk_msi_cnt = 0;
9555 tp->napi[0].last_rx_cons = 0;
9556 tp->napi[0].last_tx_cons = 0;
2d31ecaf
MC		 9557
9558 /* Zero mailbox registers. */
63c3a66f 9559 if (tg3_flag(tp, SUPPORT_MSIX)) {
6fd45cb8 9560 for (i = 1; i < tp->irq_max; i++) {
f77a6a8e
MC		 9561 tp->napi[i].tx_prod = 0;
9562 tp->napi[i].tx_cons = 0;
63c3a66f 9563 if (tg3_flag(tp, ENABLE_TSS))
c2353a32 9564 tw32_mailbox(tp->napi[i].prodmbox, 0);
f77a6a8e
MC		 9565 tw32_rx_mbox(tp->napi[i].consmbox, 0);
9566 tw32_mailbox_f(tp->napi[i].int_mbox, 1);
7f230735 9567 tp->napi[i].chk_msi_cnt = 0;
0e6cf6a9
MC		 9568 tp->napi[i].last_rx_cons = 0;
9569 tp->napi[i].last_tx_cons = 0;
f77a6a8e 9570 }
63c3a66f 9571 if (!tg3_flag(tp, ENABLE_TSS))
c2353a32 9572 tw32_mailbox(tp->napi[0].prodmbox, 0);
f77a6a8e
MC		 9573 } else {
9574 tp->napi[0].tx_prod = 0;
9575 tp->napi[0].tx_cons = 0;
9576 tw32_mailbox(tp->napi[0].prodmbox, 0);
9577 tw32_rx_mbox(tp->napi[0].consmbox, 0);
9578 }
2d31ecaf
MC		 9579
9580 /* Make sure the NIC-based send BD rings are disabled. */
63c3a66f 9581 if (!tg3_flag(tp, 5705_PLUS)) {
2d31ecaf
MC		 9582 u32 mbox = MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW;
9583 for (i = 0; i < 16; i++)
9584 tw32_tx_mbox(mbox + i * 8, 0);
9585 }
9586
2d31ecaf
MC		 9587 /* Clear status block in ram. */
9588 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
9589
9590 /* Set status block DMA address */
9591 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
9592 ((u64) tnapi->status_mapping >> 32));
9593 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
9594 ((u64) tnapi->status_mapping & 0xffffffff));
9595
f77a6a8e 9596 stblk = HOSTCC_STATBLCK_RING1;
2d31ecaf 9597
f77a6a8e
MC		 9598 for (i = 1, tnapi++; i < tp->irq_cnt; i++, tnapi++) {
9599 u64 mapping = (u64)tnapi->status_mapping;
9600 tw32(stblk + TG3_64BIT_REG_HIGH, mapping >> 32);
9601 tw32(stblk + TG3_64BIT_REG_LOW, mapping & 0xffffffff);
32ba19ef 9602 stblk += 8;
f77a6a8e
MC		 9603
9604 /* Clear status block in ram. */
9605 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
f77a6a8e 9606 }
32ba19ef
NS		 9607
9608 tg3_tx_rcbs_init(tp);
9609 tg3_rx_ret_rcbs_init(tp);
2d31ecaf
MC		 9610}
9611
eb07a940
MC		 9612static void tg3_setup_rxbd_thresholds(struct tg3 *tp)
9613{
9614 u32 val, bdcache_maxcnt, host_rep_thresh, nic_rep_thresh;
9615
63c3a66f
JP		 9616 if (!tg3_flag(tp, 5750_PLUS) ||
9617 tg3_flag(tp, 5780_CLASS) ||
4153577a
JP		 9618 tg3_asic_rev(tp) == ASIC_REV_5750 ||
9619 tg3_asic_rev(tp) == ASIC_REV_5752 ||
513aa6ea 9620 tg3_flag(tp, 57765_PLUS))
eb07a940 9621 bdcache_maxcnt = TG3_SRAM_RX_STD_BDCACHE_SIZE_5700;
4153577a
JP		 9622 else if (tg3_asic_rev(tp) == ASIC_REV_5755 ||
9623 tg3_asic_rev(tp) == ASIC_REV_5787)
eb07a940
MC		 9624 bdcache_maxcnt = TG3_SRAM_RX_STD_BDCACHE_SIZE_5755;
9625 else
9626 bdcache_maxcnt = TG3_SRAM_RX_STD_BDCACHE_SIZE_5906;
9627
9628 nic_rep_thresh = min(bdcache_maxcnt / 2, tp->rx_std_max_post);
9629 host_rep_thresh = max_t(u32, tp->rx_pending / 8, 1);
9630
9631 val = min(nic_rep_thresh, host_rep_thresh);
9632 tw32(RCVBDI_STD_THRESH, val);
9633
63c3a66f 9634 if (tg3_flag(tp, 57765_PLUS))
eb07a940
MC		 9635 tw32(STD_REPLENISH_LWM, bdcache_maxcnt);
9636
63c3a66f 9637 if (!tg3_flag(tp, JUMBO_CAPABLE) || tg3_flag(tp, 5780_CLASS))
eb07a940
MC		 9638 return;
9639
513aa6ea 9640 bdcache_maxcnt = TG3_SRAM_RX_JMB_BDCACHE_SIZE_5700;
eb07a940
MC		 9641
9642 host_rep_thresh = max_t(u32, tp->rx_jumbo_pending / 8, 1);
9643
9644 val = min(bdcache_maxcnt / 2, host_rep_thresh);
9645 tw32(RCVBDI_JUMBO_THRESH, val);
9646
63c3a66f 9647 if (tg3_flag(tp, 57765_PLUS))
eb07a940
MC		 9648 tw32(JMB_REPLENISH_LWM, bdcache_maxcnt);
9649}
9650
ccd5ba9d
MC		 9651static inline u32 calc_crc(unsigned char *buf, int len)
9652{
9653 u32 reg;
9654 u32 tmp;
9655 int j, k;
9656
9657 reg = 0xffffffff;
9658
9659 for (j = 0; j < len; j++) {
9660 reg ^= buf[j];
9661
9662 for (k = 0; k < 8; k++) {
9663 tmp = reg & 0x01;
9664
9665 reg >>= 1;
9666
9667 if (tmp)
9668 reg ^= 0xedb88320;
9669 }
9670 }
9671
9672 return ~reg;
9673}
9674
9675static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
9676{
9677 /* accept or reject all multicast frames */
9678 tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
9679 tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
9680 tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
9681 tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
9682}
9683
9684static void __tg3_set_rx_mode(struct net_device *dev)
9685{
9686 struct tg3 *tp = netdev_priv(dev);
9687 u32 rx_mode;
9688
9689 rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
9690 RX_MODE_KEEP_VLAN_TAG);
9691
9692#if !defined(CONFIG_VLAN_8021Q) && !defined(CONFIG_VLAN_8021Q_MODULE)
9693 /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
9694 * flag clear.
9695 */
9696 if (!tg3_flag(tp, ENABLE_ASF))
9697 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
9698#endif
9699
9700 if (dev->flags & IFF_PROMISC) {
9701 /* Promiscuous mode. */
9702 rx_mode |= RX_MODE_PROMISC;
9703 } else if (dev->flags & IFF_ALLMULTI) {
9704 /* Accept all multicast. */
9705 tg3_set_multi(tp, 1);
9706 } else if (netdev_mc_empty(dev)) {
9707 /* Reject all multicast. */
9708 tg3_set_multi(tp, 0);
9709 } else {
9710 /* Accept one or more multicast(s). */
9711 struct netdev_hw_addr *ha;
9712 u32 mc_filter[4] = { 0, };
9713 u32 regidx;
9714 u32 bit;
9715 u32 crc;
9716
9717 netdev_for_each_mc_addr(ha, dev) {
9718 crc = calc_crc(ha->addr, ETH_ALEN);
9719 bit = ~crc & 0x7f;
9720 regidx = (bit & 0x60) >> 5;
9721 bit &= 0x1f;
9722 mc_filter[regidx] |= (1 << bit);
9723 }
9724
9725 tw32(MAC_HASH_REG_0, mc_filter[0]);
9726 tw32(MAC_HASH_REG_1, mc_filter[1]);
9727 tw32(MAC_HASH_REG_2, mc_filter[2]);
9728 tw32(MAC_HASH_REG_3, mc_filter[3]);
9729 }
9730
e565eec3
MC		 9731 if (netdev_uc_count(dev) > TG3_MAX_UCAST_ADDR(tp)) {
9732 rx_mode |= RX_MODE_PROMISC;
9733 } else if (!(dev->flags & IFF_PROMISC)) {
9734 /* Add all entries into to the mac addr filter list */
9735 int i = 0;
9736 struct netdev_hw_addr *ha;
9737
9738 netdev_for_each_uc_addr(ha, dev) {
9739 __tg3_set_one_mac_addr(tp, ha->addr,
9740 i + TG3_UCAST_ADDR_IDX(tp));
9741 i++;
9742 }
9743 }
9744
ccd5ba9d
MC		 9745 if (rx_mode != tp->rx_mode) {
9746 tp->rx_mode = rx_mode;
9747 tw32_f(MAC_RX_MODE, rx_mode);
9748 udelay(10);
9749 }
9750}
9751
9102426a 9752static void tg3_rss_init_dflt_indir_tbl(struct tg3 *tp, u32 qcnt)
90415477
MC		 9753{
9754 int i;
9755
9756 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++)
9102426a 9757 tp->rss_ind_tbl[i] = ethtool_rxfh_indir_default(i, qcnt);
90415477
MC		 9758}
9759
9760static void tg3_rss_check_indir_tbl(struct tg3 *tp)
bcebcc46
MC		 9761{
9762 int i;
9763
9764 if (!tg3_flag(tp, SUPPORT_MSIX))
9765 return;
9766
0b3ba055 9767 if (tp->rxq_cnt == 1) {
bcebcc46 9768 memset(&tp->rss_ind_tbl[0], 0, sizeof(tp->rss_ind_tbl));
90415477
MC		 9769 return;
9770 }
9771
9772 /* Validate table against current IRQ count */
9773 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++) {
0b3ba055 9774 if (tp->rss_ind_tbl[i] >= tp->rxq_cnt)
90415477
MC		 9775 break;
9776 }
9777
9778 if (i != TG3_RSS_INDIR_TBL_SIZE)
9102426a 9779 tg3_rss_init_dflt_indir_tbl(tp, tp->rxq_cnt);
bcebcc46
MC		 9780}
9781
90415477 9782static void tg3_rss_write_indir_tbl(struct tg3 *tp)
bcebcc46
MC		 9783{
9784 int i = 0;
9785 u32 reg = MAC_RSS_INDIR_TBL_0;
9786
9787 while (i < TG3_RSS_INDIR_TBL_SIZE) {
9788 u32 val = tp->rss_ind_tbl[i];
9789 i++;
9790 for (; i % 8; i++) {
9791 val <<= 4;
9792 val |= tp->rss_ind_tbl[i];
9793 }
9794 tw32(reg, val);
9795 reg += 4;
9796 }
9797}
9798
9bc297ea
NS		 9799static inline u32 tg3_lso_rd_dma_workaround_bit(struct tg3 *tp)
9800{
9801 if (tg3_asic_rev(tp) == ASIC_REV_5719)
9802 return TG3_LSO_RD_DMA_TX_LENGTH_WA_5719;
9803 else
9804 return TG3_LSO_RD_DMA_TX_LENGTH_WA_5720;
9805}
9806
1da177e4 9807/* tp->lock is held. */
953c96e0 9808static int tg3_reset_hw(struct tg3 *tp, bool reset_phy)
1da177e4
LT		 9809{
9810 u32 val, rdmac_mode;
9811 int i, err, limit;
8fea32b9 9812 struct tg3_rx_prodring_set *tpr = &tp->napi[0].prodring;
1da177e4
LT		 9813
9814 tg3_disable_ints(tp);
9815
9816 tg3_stop_fw(tp);
9817
9818 tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
9819
63c3a66f 9820 if (tg3_flag(tp, INIT_COMPLETE))
e6de8ad1 9821 tg3_abort_hw(tp, 1);
1da177e4 9822
fdad8de4
NS		 9823 if ((tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN) &&
9824 !(tp->phy_flags & TG3_PHYFLG_USER_CONFIGURED)) {
9825 tg3_phy_pull_config(tp);
400dfbaa 9826 tg3_eee_pull_config(tp, NULL);
fdad8de4
NS		 9827 tp->phy_flags |= TG3_PHYFLG_USER_CONFIGURED;
9828 }
9829
400dfbaa
NS		 9830 /* Enable MAC control of LPI */
9831 if (tp->phy_flags & TG3_PHYFLG_EEE_CAP)
9832 tg3_setup_eee(tp);
9833
603f1173 9834 if (reset_phy)
d4d2c558
MC		 9835 tg3_phy_reset(tp);
9836
1da177e4
LT		 9837 err = tg3_chip_reset(tp);
9838 if (err)
9839 return err;
9840
9841 tg3_write_sig_legacy(tp, RESET_KIND_INIT);
9842
4153577a 9843 if (tg3_chip_rev(tp) == CHIPREV_5784_AX) {
d30cdd28
MC		 9844 val = tr32(TG3_CPMU_CTRL);
9845 val &= ~(CPMU_CTRL_LINK_AWARE_MODE | CPMU_CTRL_LINK_IDLE_MODE);
9846 tw32(TG3_CPMU_CTRL, val);
9acb961e
MC		 9847
9848 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
9849 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
9850 val |= CPMU_LSPD_10MB_MACCLK_6_25;
9851 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
9852
9853 val = tr32(TG3_CPMU_LNK_AWARE_PWRMD);
9854 val &= ~CPMU_LNK_AWARE_MACCLK_MASK;
9855 val |= CPMU_LNK_AWARE_MACCLK_6_25;
9856 tw32(TG3_CPMU_LNK_AWARE_PWRMD, val);
9857
9858 val = tr32(TG3_CPMU_HST_ACC);
9859 val &= ~CPMU_HST_ACC_MACCLK_MASK;
9860 val |= CPMU_HST_ACC_MACCLK_6_25;
9861 tw32(TG3_CPMU_HST_ACC, val);
d30cdd28
MC		 9862 }
9863
4153577a 9864 if (tg3_asic_rev(tp) == ASIC_REV_57780) {
33466d93
MC		 9865 val = tr32(PCIE_PWR_MGMT_THRESH) & ~PCIE_PWR_MGMT_L1_THRESH_MSK;
9866 val |= PCIE_PWR_MGMT_EXT_ASPM_TMR_EN |
9867 PCIE_PWR_MGMT_L1_THRESH_4MS;
9868 tw32(PCIE_PWR_MGMT_THRESH, val);
521e6b90
MC		 9869
9870 val = tr32(TG3_PCIE_EIDLE_DELAY) & ~TG3_PCIE_EIDLE_DELAY_MASK;
9871 tw32(TG3_PCIE_EIDLE_DELAY, val | TG3_PCIE_EIDLE_DELAY_13_CLKS);
9872
9873 tw32(TG3_CORR_ERR_STAT, TG3_CORR_ERR_STAT_CLEAR);
33466d93 9874
f40386c8
MC		 9875 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
9876 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
255ca311
MC		 9877 }
9878
63c3a66f 9879 if (tg3_flag(tp, L1PLLPD_EN)) {
614b0590
MC		 9880 u32 grc_mode = tr32(GRC_MODE);
9881
9882 /* Access the lower 1K of PL PCIE block registers. */
9883 val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
9884 tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL);
9885
9886 val = tr32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1);
9887 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1,
9888 val | TG3_PCIE_PL_LO_PHYCTL1_L1PLLPD_EN);
9889
9890 tw32(GRC_MODE, grc_mode);
9891 }
9892
55086ad9 9893 if (tg3_flag(tp, 57765_CLASS)) {
4153577a 9894 if (tg3_chip_rev_id(tp) == CHIPREV_ID_57765_A0) {
5093eedc 9895 u32 grc_mode = tr32(GRC_MODE);
cea46462 9896
5093eedc
MC		 9897 /* Access the lower 1K of PL PCIE block registers. */
9898 val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
9899 tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL);
cea46462 9900
5093eedc
MC		 9901 val = tr32(TG3_PCIE_TLDLPL_PORT +
9902 TG3_PCIE_PL_LO_PHYCTL5);
9903 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL5,
9904 val | TG3_PCIE_PL_LO_PHYCTL5_DIS_L2CLKREQ);
cea46462 9905
5093eedc
MC		 9906 tw32(GRC_MODE, grc_mode);
9907 }
a977dbe8 9908
4153577a 9909 if (tg3_chip_rev(tp) != CHIPREV_57765_AX) {
d3f677af
MC		 9910 u32 grc_mode;
9911
9912 /* Fix transmit hangs */
9913 val = tr32(TG3_CPMU_PADRNG_CTL);
9914 val |= TG3_CPMU_PADRNG_CTL_RDIV2;
9915 tw32(TG3_CPMU_PADRNG_CTL, val);
9916
9917 grc_mode = tr32(GRC_MODE);
1ff30a59
MC		 9918
9919 /* Access the lower 1K of DL PCIE block registers. */
9920 val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
9921 tw32(GRC_MODE, val | GRC_MODE_PCIE_DL_SEL);
9922
9923 val = tr32(TG3_PCIE_TLDLPL_PORT +
9924 TG3_PCIE_DL_LO_FTSMAX);
9925 val &= ~TG3_PCIE_DL_LO_FTSMAX_MSK;
9926 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_DL_LO_FTSMAX,
9927 val | TG3_PCIE_DL_LO_FTSMAX_VAL);
9928
9929 tw32(GRC_MODE, grc_mode);
9930 }
9931
a977dbe8
MC		 9932 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
9933 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
9934 val |= CPMU_LSPD_10MB_MACCLK_6_25;
9935 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
cea46462
MC		 9936 }
9937
1da177e4
LT		 9938 /* This works around an issue with Athlon chipsets on
9939 * B3 tigon3 silicon. This bit has no effect on any
9940 * other revision. But do not set this on PCI Express
795d01c5 9941 * chips and don't even touch the clocks if the CPMU is present.
1da177e4 9942 */
63c3a66f
JP		 9943 if (!tg3_flag(tp, CPMU_PRESENT)) {
9944 if (!tg3_flag(tp, PCI_EXPRESS))
795d01c5
MC		 9945 tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
9946 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
9947 }
1da177e4 9948
4153577a 9949 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5704_A0 &&
63c3a66f 9950 tg3_flag(tp, PCIX_MODE)) {
1da177e4
LT		 9951 val = tr32(TG3PCI_PCISTATE);
9952 val |= PCISTATE_RETRY_SAME_DMA;
9953 tw32(TG3PCI_PCISTATE, val);
9954 }
9955
63c3a66f 9956 if (tg3_flag(tp, ENABLE_APE)) {
0d3031d9
MC		 9957 /* Allow reads and writes to the
9958 * APE register and memory space.
9959 */
9960 val = tr32(TG3PCI_PCISTATE);
9961 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
f92d9dc1
MC		 9962 PCISTATE_ALLOW_APE_SHMEM_WR |
9963 PCISTATE_ALLOW_APE_PSPACE_WR;
0d3031d9
MC		 9964 tw32(TG3PCI_PCISTATE, val);
9965 }
9966
4153577a 9967 if (tg3_chip_rev(tp) == CHIPREV_5704_BX) {
1da177e4
LT		 9968 /* Enable some hw fixes. */
9969 val = tr32(TG3PCI_MSI_DATA);
9970 val |= (1 << 26) | (1 << 28) | (1 << 29);
9971 tw32(TG3PCI_MSI_DATA, val);
9972 }
9973
9974 /* Descriptor ring init may make accesses to the
9975 * NIC SRAM area to setup the TX descriptors, so we
9976 * can only do this after the hardware has been
9977 * successfully reset.
9978 */
32d8c572
MC		 9979 err = tg3_init_rings(tp);
9980 if (err)
9981 return err;
1da177e4 9982
63c3a66f 9983 if (tg3_flag(tp, 57765_PLUS)) {
cbf9ca6c
MC		 9984 val = tr32(TG3PCI_DMA_RW_CTRL) &
9985 ~DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
4153577a 9986 if (tg3_chip_rev_id(tp) == CHIPREV_ID_57765_A0)
1a319025 9987 val &= ~DMA_RWCTRL_CRDRDR_RDMA_MRRS_MSK;
55086ad9 9988 if (!tg3_flag(tp, 57765_CLASS) &&
4153577a
JP		 9989 tg3_asic_rev(tp) != ASIC_REV_5717 &&
9990 tg3_asic_rev(tp) != ASIC_REV_5762)
0aebff48 9991 val |= DMA_RWCTRL_TAGGED_STAT_WA;
cbf9ca6c 9992 tw32(TG3PCI_DMA_RW_CTRL, val | tp->dma_rwctrl);
4153577a
JP		 9993 } else if (tg3_asic_rev(tp) != ASIC_REV_5784 &&
9994 tg3_asic_rev(tp) != ASIC_REV_5761) {
d30cdd28
MC		 9995 /* This value is determined during the probe time DMA
9996 * engine test, tg3_test_dma.
9997 */
9998 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
9999 }
1da177e4
LT		 10000
10001 tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
10002 GRC_MODE_4X_NIC_SEND_RINGS |
10003 GRC_MODE_NO_TX_PHDR_CSUM |
10004 GRC_MODE_NO_RX_PHDR_CSUM);
10005 tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
d2d746f8
MC		 10006
10007 /* Pseudo-header checksum is done by hardware logic and not
10008 * the offload processers, so make the chip do the pseudo-
10009 * header checksums on receive. For transmit it is more
10010 * convenient to do the pseudo-header checksum in software
10011 * as Linux does that on transmit for us in all cases.
10012 */
10013 tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
1da177e4 10014
fb4ce8ad
MC		 10015 val = GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP;
10016 if (tp->rxptpctl)
10017 tw32(TG3_RX_PTP_CTL,
10018 tp->rxptpctl | TG3_RX_PTP_CTL_HWTS_INTERLOCK);
10019
10020 if (tg3_flag(tp, PTP_CAPABLE))
10021 val |= GRC_MODE_TIME_SYNC_ENABLE;
10022
10023 tw32(GRC_MODE, tp->grc_mode | val);
1da177e4
LT		 10024
10025 /* Setup the timer prescalar register. Clock is always 66Mhz. */
10026 val = tr32(GRC_MISC_CFG);
10027 val &= ~0xff;
10028 val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
10029 tw32(GRC_MISC_CFG, val);
10030
10031 /* Initialize MBUF/DESC pool. */
63c3a66f 10032 if (tg3_flag(tp, 5750_PLUS)) {
1da177e4 10033 /* Do nothing. */
4153577a 10034 } else if (tg3_asic_rev(tp) != ASIC_REV_5705) {
1da177e4 10035 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
4153577a 10036 if (tg3_asic_rev(tp) == ASIC_REV_5704)
1da177e4
LT		 10037 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
10038 else
10039 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
10040 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
10041 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
63c3a66f 10042 } else if (tg3_flag(tp, TSO_CAPABLE)) {
1da177e4
LT		 10043 int fw_len;
10044
077f849d 10045 fw_len = tp->fw_len;
1da177e4
LT		 10046 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
10047 tw32(BUFMGR_MB_POOL_ADDR,
10048 NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
10049 tw32(BUFMGR_MB_POOL_SIZE,
10050 NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
10051 }
1da177e4 10052
0f893dc6 10053 if (tp->dev->mtu <= ETH_DATA_LEN) {
1da177e4
LT		 10054 tw32(BUFMGR_MB_RDMA_LOW_WATER,
10055 tp->bufmgr_config.mbuf_read_dma_low_water);
10056 tw32(BUFMGR_MB_MACRX_LOW_WATER,
10057 tp->bufmgr_config.mbuf_mac_rx_low_water);
10058 tw32(BUFMGR_MB_HIGH_WATER,
10059 tp->bufmgr_config.mbuf_high_water);
10060 } else {
10061 tw32(BUFMGR_MB_RDMA_LOW_WATER,
10062 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
10063 tw32(BUFMGR_MB_MACRX_LOW_WATER,
10064 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
10065 tw32(BUFMGR_MB_HIGH_WATER,
10066 tp->bufmgr_config.mbuf_high_water_jumbo);
10067 }
10068 tw32(BUFMGR_DMA_LOW_WATER,
10069 tp->bufmgr_config.dma_low_water);
10070 tw32(BUFMGR_DMA_HIGH_WATER,
10071 tp->bufmgr_config.dma_high_water);
10072
d309a46e 10073 val = BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE;
4153577a 10074 if (tg3_asic_rev(tp) == ASIC_REV_5719)
d309a46e 10075 val |= BUFMGR_MODE_NO_TX_UNDERRUN;
4153577a 10076 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
94962f7f 10077 tg3_asic_rev(tp) == ASIC_REV_5762 ||
4153577a
JP		 10078 tg3_chip_rev_id(tp) == CHIPREV_ID_5719_A0 ||
10079 tg3_chip_rev_id(tp) == CHIPREV_ID_5720_A0)
4d958473 10080 val |= BUFMGR_MODE_MBLOW_ATTN_ENAB;
d309a46e 10081 tw32(BUFMGR_MODE, val);
1da177e4
LT		 10082 for (i = 0; i < 2000; i++) {
10083 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
10084 break;
10085 udelay(10);
10086 }
10087 if (i >= 2000) {
05dbe005 10088 netdev_err(tp->dev, "%s cannot enable BUFMGR\n", __func__);
1da177e4
LT		 10089 return -ENODEV;
10090 }
10091
4153577a 10092 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5906_A1)
eb07a940 10093 tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2);
b5d3772c 10094
eb07a940 10095 tg3_setup_rxbd_thresholds(tp);
1da177e4
LT		 10096
10097 /* Initialize TG3_BDINFO's at:
10098 * RCVDBDI_STD_BD: standard eth size rx ring
10099 * RCVDBDI_JUMBO_BD: jumbo frame rx ring
10100 * RCVDBDI_MINI_BD: small frame rx ring (??? does not work)
10101 *
10102 * like so:
10103 * TG3_BDINFO_HOST_ADDR: high/low parts of DMA address of ring
10104 * TG3_BDINFO_MAXLEN_FLAGS: (rx max buffer size << 16) |
10105 * ring attribute flags
10106 * TG3_BDINFO_NIC_ADDR: location of descriptors in nic SRAM
10107 *
10108 * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
10109 * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
10110 *
10111 * The size of each ring is fixed in the firmware, but the location is
10112 * configurable.
10113 */
10114 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
21f581a5 10115 ((u64) tpr->rx_std_mapping >> 32));
1da177e4 10116 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
21f581a5 10117 ((u64) tpr->rx_std_mapping & 0xffffffff));
63c3a66f 10118 if (!tg3_flag(tp, 5717_PLUS))
87668d35
MC		 10119 tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
10120 NIC_SRAM_RX_BUFFER_DESC);
1da177e4 10121
fdb72b38 10122 /* Disable the mini ring */
63c3a66f 10123 if (!tg3_flag(tp, 5705_PLUS))
1da177e4
LT		 10124 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
10125 BDINFO_FLAGS_DISABLED);
10126
fdb72b38
MC		 10127 /* Program the jumbo buffer descriptor ring control
10128 * blocks on those devices that have them.
10129 */
4153577a 10130 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5719_A0 ||
63c3a66f 10131 (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS))) {
1da177e4 10132
63c3a66f 10133 if (tg3_flag(tp, JUMBO_RING_ENABLE)) {
1da177e4 10134 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
21f581a5 10135 ((u64) tpr->rx_jmb_mapping >> 32));
1da177e4 10136 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
21f581a5 10137 ((u64) tpr->rx_jmb_mapping & 0xffffffff));
de9f5230
MC		 10138 val = TG3_RX_JMB_RING_SIZE(tp) <<
10139 BDINFO_FLAGS_MAXLEN_SHIFT;
1da177e4 10140 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
de9f5230 10141 val | BDINFO_FLAGS_USE_EXT_RECV);
63c3a66f 10142 if (!tg3_flag(tp, USE_JUMBO_BDFLAG) ||
c65a17f4 10143 tg3_flag(tp, 57765_CLASS) ||
4153577a 10144 tg3_asic_rev(tp) == ASIC_REV_5762)
87668d35
MC		 10145 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
10146 NIC_SRAM_RX_JUMBO_BUFFER_DESC);
1da177e4
LT		 10147 } else {
10148 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
10149 BDINFO_FLAGS_DISABLED);
10150 }
10151
63c3a66f 10152 if (tg3_flag(tp, 57765_PLUS)) {
fa6b2aae 10153 val = TG3_RX_STD_RING_SIZE(tp);
7cb32cf2
MC		 10154 val <<= BDINFO_FLAGS_MAXLEN_SHIFT;
10155 val |= (TG3_RX_STD_DMA_SZ << 2);
10156 } else
04380d40 10157 val = TG3_RX_STD_DMA_SZ << BDINFO_FLAGS_MAXLEN_SHIFT;
fdb72b38 10158 } else
de9f5230 10159 val = TG3_RX_STD_MAX_SIZE_5700 << BDINFO_FLAGS_MAXLEN_SHIFT;
fdb72b38
MC		 10160
10161 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS, val);
1da177e4 10162
411da640 10163 tpr->rx_std_prod_idx = tp->rx_pending;
66711e66 10164 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG, tpr->rx_std_prod_idx);
1da177e4 10165
63c3a66f
JP		 10166 tpr->rx_jmb_prod_idx =
10167 tg3_flag(tp, JUMBO_RING_ENABLE) ? tp->rx_jumbo_pending : 0;
66711e66 10168 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG, tpr->rx_jmb_prod_idx);
1da177e4 10169
2d31ecaf
MC		 10170 tg3_rings_reset(tp);
10171
1da177e4 10172 /* Initialize MAC address and backoff seed. */
953c96e0 10173 __tg3_set_mac_addr(tp, false);
1da177e4
LT		 10174
10175 /* MTU + ethernet header + FCS + optional VLAN tag */
f7b493e0
MC		 10176 tw32(MAC_RX_MTU_SIZE,
10177 tp->dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN);
1da177e4
LT		 10178
10179 /* The slot time is changed by tg3_setup_phy if we
10180 * run at gigabit with half duplex.
10181 */
f2096f94
MC		 10182 val = (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
10183 (6 << TX_LENGTHS_IPG_SHIFT) |
10184 (32 << TX_LENGTHS_SLOT_TIME_SHIFT);
10185
4153577a
JP		 10186 if (tg3_asic_rev(tp) == ASIC_REV_5720 ||
10187 tg3_asic_rev(tp) == ASIC_REV_5762)
f2096f94
MC		 10188 val |= tr32(MAC_TX_LENGTHS) &
10189 (TX_LENGTHS_JMB_FRM_LEN_MSK |
10190 TX_LENGTHS_CNT_DWN_VAL_MSK);
10191
10192 tw32(MAC_TX_LENGTHS, val);
1da177e4
LT		 10193
10194 /* Receive rules. */
10195 tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
10196 tw32(RCVLPC_CONFIG, 0x0181);
10197
10198 /* Calculate RDMAC_MODE setting early, we need it to determine
10199 * the RCVLPC_STATE_ENABLE mask.
10200 */
10201 rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
10202 RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
10203 RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
10204 RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
10205 RDMAC_MODE_LNGREAD_ENAB);
85e94ced 10206
4153577a 10207 if (tg3_asic_rev(tp) == ASIC_REV_5717)
0339e4e3
MC		 10208 rdmac_mode |= RDMAC_MODE_MULT_DMA_RD_DIS;
10209
4153577a
JP		 10210 if (tg3_asic_rev(tp) == ASIC_REV_5784 ||
10211 tg3_asic_rev(tp) == ASIC_REV_5785 ||
10212 tg3_asic_rev(tp) == ASIC_REV_57780)
d30cdd28
MC		 10213 rdmac_mode |= RDMAC_MODE_BD_SBD_CRPT_ENAB |
10214 RDMAC_MODE_MBUF_RBD_CRPT_ENAB |
10215 RDMAC_MODE_MBUF_SBD_CRPT_ENAB;
10216
4153577a
JP		 10217 if (tg3_asic_rev(tp) == ASIC_REV_5705 &&
10218 tg3_chip_rev_id(tp) != CHIPREV_ID_5705_A0) {
63c3a66f 10219 if (tg3_flag(tp, TSO_CAPABLE) &&
4153577a 10220 tg3_asic_rev(tp) == ASIC_REV_5705) {
1da177e4
LT		 10221 rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
10222 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
63c3a66f 10223 !tg3_flag(tp, IS_5788)) {
1da177e4
LT		 10224 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
10225 }
10226 }
10227
63c3a66f 10228 if (tg3_flag(tp, PCI_EXPRESS))
85e94ced
MC		 10229 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
10230
4153577a 10231 if (tg3_asic_rev(tp) == ASIC_REV_57766) {
d3f677af
MC		 10232 tp->dma_limit = 0;
10233 if (tp->dev->mtu <= ETH_DATA_LEN) {
10234 rdmac_mode |= RDMAC_MODE_JMB_2K_MMRR;
10235 tp->dma_limit = TG3_TX_BD_DMA_MAX_2K;
10236 }
10237 }
10238
63c3a66f
JP		 10239 if (tg3_flag(tp, HW_TSO_1) ||
10240 tg3_flag(tp, HW_TSO_2) ||
10241 tg3_flag(tp, HW_TSO_3))
027455ad
MC		 10242 rdmac_mode |= RDMAC_MODE_IPV4_LSO_EN;
10243
108a6c16 10244 if (tg3_flag(tp, 57765_PLUS) ||
4153577a
JP		 10245 tg3_asic_rev(tp) == ASIC_REV_5785 ||
10246 tg3_asic_rev(tp) == ASIC_REV_57780)
027455ad 10247 rdmac_mode |= RDMAC_MODE_IPV6_LSO_EN;
1da177e4 10248
4153577a
JP		 10249 if (tg3_asic_rev(tp) == ASIC_REV_5720 ||
10250 tg3_asic_rev(tp) == ASIC_REV_5762)
f2096f94
MC		 10251 rdmac_mode |= tr32(RDMAC_MODE) & RDMAC_MODE_H2BNC_VLAN_DET;
10252
4153577a
JP		 10253 if (tg3_asic_rev(tp) == ASIC_REV_5761 ||
10254 tg3_asic_rev(tp) == ASIC_REV_5784 ||
10255 tg3_asic_rev(tp) == ASIC_REV_5785 ||
10256 tg3_asic_rev(tp) == ASIC_REV_57780 ||
63c3a66f 10257 tg3_flag(tp, 57765_PLUS)) {
c65a17f4
MC		 10258 u32 tgtreg;
10259
4153577a 10260 if (tg3_asic_rev(tp) == ASIC_REV_5762)
c65a17f4
MC		 10261 tgtreg = TG3_RDMA_RSRVCTRL_REG2;
10262 else
10263 tgtreg = TG3_RDMA_RSRVCTRL_REG;
10264
10265 val = tr32(tgtreg);
4153577a
JP		 10266 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5719_A0 ||
10267 tg3_asic_rev(tp) == ASIC_REV_5762) {
b4495ed8
MC		 10268 val &= ~(TG3_RDMA_RSRVCTRL_TXMRGN_MASK |
10269 TG3_RDMA_RSRVCTRL_FIFO_LWM_MASK |
10270 TG3_RDMA_RSRVCTRL_FIFO_HWM_MASK);
10271 val |= TG3_RDMA_RSRVCTRL_TXMRGN_320B |
10272 TG3_RDMA_RSRVCTRL_FIFO_LWM_1_5K |
10273 TG3_RDMA_RSRVCTRL_FIFO_HWM_1_5K;
b75cc0e4 10274 }
c65a17f4 10275 tw32(tgtreg, val | TG3_RDMA_RSRVCTRL_FIFO_OFLW_FIX);
41a8a7ee
MC		 10276 }
10277
4153577a
JP		 10278 if (tg3_asic_rev(tp) == ASIC_REV_5719 ||
10279 tg3_asic_rev(tp) == ASIC_REV_5720 ||
10280 tg3_asic_rev(tp) == ASIC_REV_5762) {
c65a17f4
MC		 10281 u32 tgtreg;
10282
4153577a 10283 if (tg3_asic_rev(tp) == ASIC_REV_5762)
c65a17f4
MC		 10284 tgtreg = TG3_LSO_RD_DMA_CRPTEN_CTRL2;
10285 else
10286 tgtreg = TG3_LSO_RD_DMA_CRPTEN_CTRL;
10287
10288 val = tr32(tgtreg);
10289 tw32(tgtreg, val |
d309a46e
MC		 10290 TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_BD_4K |
10291 TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_LSO_4K);
10292 }
10293
1da177e4 10294 /* Receive/send statistics. */
63c3a66f 10295 if (tg3_flag(tp, 5750_PLUS)) {
1661394e
MC		 10296 val = tr32(RCVLPC_STATS_ENABLE);
10297 val &= ~RCVLPC_STATSENAB_DACK_FIX;
10298 tw32(RCVLPC_STATS_ENABLE, val);
10299 } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
63c3a66f 10300 tg3_flag(tp, TSO_CAPABLE)) {
1da177e4
LT		 10301 val = tr32(RCVLPC_STATS_ENABLE);
10302 val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
10303 tw32(RCVLPC_STATS_ENABLE, val);
10304 } else {
10305 tw32(RCVLPC_STATS_ENABLE, 0xffffff);
10306 }
10307 tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
10308 tw32(SNDDATAI_STATSENAB, 0xffffff);
10309 tw32(SNDDATAI_STATSCTRL,
10310 (SNDDATAI_SCTRL_ENABLE |
10311 SNDDATAI_SCTRL_FASTUPD));
10312
10313 /* Setup host coalescing engine. */
10314 tw32(HOSTCC_MODE, 0);
10315 for (i = 0; i < 2000; i++) {
10316 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
10317 break;
10318 udelay(10);
10319 }
10320
d244c892 10321 __tg3_set_coalesce(tp, &tp->coal);
1da177e4 10322
63c3a66f 10323 if (!tg3_flag(tp, 5705_PLUS)) {
1da177e4
LT		 10324 /* Status/statistics block address. See tg3_timer,
10325 * the tg3_periodic_fetch_stats call there, and
10326 * tg3_get_stats to see how this works for 5705/5750 chips.
10327 */
1da177e4
LT		 10328 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
10329 ((u64) tp->stats_mapping >> 32));
10330 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
10331 ((u64) tp->stats_mapping & 0xffffffff));
10332 tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
2d31ecaf 10333
1da177e4 10334 tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
2d31ecaf
MC		 10335
10336 /* Clear statistics and status block memory areas */
10337 for (i = NIC_SRAM_STATS_BLK;
10338 i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
10339 i += sizeof(u32)) {
10340 tg3_write_mem(tp, i, 0);
10341 udelay(40);
10342 }
1da177e4
LT		 10343 }
10344
10345 tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
10346
10347 tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
10348 tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
63c3a66f 10349 if (!tg3_flag(tp, 5705_PLUS))
1da177e4
LT		 10350 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
10351
f07e9af3
MC		 10352 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) {
10353 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
c94e3941
MC		 10354 /* reset to prevent losing 1st rx packet intermittently */
10355 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
10356 udelay(10);
10357 }
10358
3bda1258 10359 tp->mac_mode |= MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
9e975cc2
MC		 10360 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE |
10361 MAC_MODE_FHDE_ENABLE;
10362 if (tg3_flag(tp, ENABLE_APE))
10363 tp->mac_mode |= MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
63c3a66f 10364 if (!tg3_flag(tp, 5705_PLUS) &&
f07e9af3 10365 !(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
4153577a 10366 tg3_asic_rev(tp) != ASIC_REV_5700)
e8f3f6ca 10367 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
1da177e4
LT		 10368 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
10369 udelay(40);
10370
314fba34 10371 /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
63c3a66f 10372 * If TG3_FLAG_IS_NIC is zero, we should read the
314fba34
MC		 10373 * register to preserve the GPIO settings for LOMs. The GPIOs,
10374 * whether used as inputs or outputs, are set by boot code after
10375 * reset.
10376 */
63c3a66f 10377 if (!tg3_flag(tp, IS_NIC)) {
314fba34
MC		 10378 u32 gpio_mask;
10379
9d26e213
MC		 10380 gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 |
10381 GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 |
10382 GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2;
3e7d83bc 10383
4153577a 10384 if (tg3_asic_rev(tp) == ASIC_REV_5752)
3e7d83bc
MC		 10385 gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
10386 GRC_LCLCTRL_GPIO_OUTPUT3;
10387
4153577a 10388 if (tg3_asic_rev(tp) == ASIC_REV_5755)
af36e6b6
MC		 10389 gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL;
10390
aaf84465 10391 tp->grc_local_ctrl &= ~gpio_mask;
314fba34
MC		 10392 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
10393
10394 /* GPIO1 must be driven high for eeprom write protect */
63c3a66f 10395 if (tg3_flag(tp, EEPROM_WRITE_PROT))
9d26e213
MC		 10396 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
10397 GRC_LCLCTRL_GPIO_OUTPUT1);
314fba34 10398 }
1da177e4
LT		 10399 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
10400 udelay(100);
10401
c3b5003b 10402 if (tg3_flag(tp, USING_MSIX)) {
baf8a94a 10403 val = tr32(MSGINT_MODE);
c3b5003b
MC		 10404 val |= MSGINT_MODE_ENABLE;
10405 if (tp->irq_cnt > 1)
10406 val |= MSGINT_MODE_MULTIVEC_EN;
5b39de91
MC		 10407 if (!tg3_flag(tp, 1SHOT_MSI))
10408 val |= MSGINT_MODE_ONE_SHOT_DISABLE;
baf8a94a
MC		 10409 tw32(MSGINT_MODE, val);
10410 }
10411
63c3a66f 10412 if (!tg3_flag(tp, 5705_PLUS)) {
1da177e4
LT		 10413 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
10414 udelay(40);
10415 }
10416
10417 val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
10418 WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
10419 WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
10420 WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
10421 WDMAC_MODE_LNGREAD_ENAB);
10422
4153577a
JP		 10423 if (tg3_asic_rev(tp) == ASIC_REV_5705 &&
10424 tg3_chip_rev_id(tp) != CHIPREV_ID_5705_A0) {
63c3a66f 10425 if (tg3_flag(tp, TSO_CAPABLE) &&
4153577a
JP		 10426 (tg3_chip_rev_id(tp) == CHIPREV_ID_5705_A1 ||
10427 tg3_chip_rev_id(tp) == CHIPREV_ID_5705_A2)) {
1da177e4
LT		 10428 /* nothing */
10429 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
63c3a66f 10430 !tg3_flag(tp, IS_5788)) {
1da177e4
LT		 10431 val |= WDMAC_MODE_RX_ACCEL;
10432 }
10433 }
10434
d9ab5ad1 10435 /* Enable host coalescing bug fix */
63c3a66f 10436 if (tg3_flag(tp, 5755_PLUS))
f51f3562 10437 val |= WDMAC_MODE_STATUS_TAG_FIX;
d9ab5ad1 10438
4153577a 10439 if (tg3_asic_rev(tp) == ASIC_REV_5785)
788a035e
MC		 10440 val |= WDMAC_MODE_BURST_ALL_DATA;
10441
1da177e4
LT		 10442 tw32_f(WDMAC_MODE, val);
10443 udelay(40);
10444
63c3a66f 10445 if (tg3_flag(tp, PCIX_MODE)) {
9974a356
MC		 10446 u16 pcix_cmd;
10447
10448 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
10449 &pcix_cmd);
4153577a 10450 if (tg3_asic_rev(tp) == ASIC_REV_5703) {
9974a356
MC		 10451 pcix_cmd &= ~PCI_X_CMD_MAX_READ;
10452 pcix_cmd |= PCI_X_CMD_READ_2K;
4153577a 10453 } else if (tg3_asic_rev(tp) == ASIC_REV_5704) {
9974a356
MC		 10454 pcix_cmd &= ~(PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ);
10455 pcix_cmd |= PCI_X_CMD_READ_2K;
1da177e4 10456 }
9974a356
MC		 10457 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
10458 pcix_cmd);
1da177e4
LT		 10459 }
10460
10461 tw32_f(RDMAC_MODE, rdmac_mode);
10462 udelay(40);
10463
9bc297ea
NS		 10464 if (tg3_asic_rev(tp) == ASIC_REV_5719 ||
10465 tg3_asic_rev(tp) == ASIC_REV_5720) {
091f0ea3
MC		 10466 for (i = 0; i < TG3_NUM_RDMA_CHANNELS; i++) {
10467 if (tr32(TG3_RDMA_LENGTH + (i << 2)) > TG3_MAX_MTU(tp))
10468 break;
10469 }
10470 if (i < TG3_NUM_RDMA_CHANNELS) {
10471 val = tr32(TG3_LSO_RD_DMA_CRPTEN_CTRL);
9bc297ea 10472 val |= tg3_lso_rd_dma_workaround_bit(tp);
091f0ea3 10473 tw32(TG3_LSO_RD_DMA_CRPTEN_CTRL, val);
9bc297ea 10474 tg3_flag_set(tp, 5719_5720_RDMA_BUG);
091f0ea3
MC		 10475 }
10476 }
10477
1da177e4 10478 tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
63c3a66f 10479 if (!tg3_flag(tp, 5705_PLUS))
1da177e4 10480 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
9936bcf6 10481
4153577a 10482 if (tg3_asic_rev(tp) == ASIC_REV_5761)
9936bcf6
MC		 10483 tw32(SNDDATAC_MODE,
10484 SNDDATAC_MODE_ENABLE | SNDDATAC_MODE_CDELAY);
10485 else
10486 tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
10487
1da177e4
LT		 10488 tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
10489 tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
7cb32cf2 10490 val = RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ;
63c3a66f 10491 if (tg3_flag(tp, LRG_PROD_RING_CAP))
7cb32cf2
MC		 10492 val |= RCVDBDI_MODE_LRG_RING_SZ;
10493 tw32(RCVDBDI_MODE, val);
1da177e4 10494 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
63c3a66f
JP		 10495 if (tg3_flag(tp, HW_TSO_1) ||
10496 tg3_flag(tp, HW_TSO_2) ||
10497 tg3_flag(tp, HW_TSO_3))
1da177e4 10498 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
baf8a94a 10499 val = SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE;
63c3a66f 10500 if (tg3_flag(tp, ENABLE_TSS))
baf8a94a
MC		 10501 val |= SNDBDI_MODE_MULTI_TXQ_EN;
10502 tw32(SNDBDI_MODE, val);
1da177e4
LT		 10503 tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
10504
4153577a 10505 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0) {
1da177e4
LT		 10506 err = tg3_load_5701_a0_firmware_fix(tp);
10507 if (err)
10508 return err;
10509 }
10510
c4dab506
NS		 10511 if (tg3_asic_rev(tp) == ASIC_REV_57766) {
10512 /* Ignore any errors for the firmware download. If download
10513 * fails, the device will operate with EEE disabled
10514 */
10515 tg3_load_57766_firmware(tp);
10516 }
10517
63c3a66f 10518 if (tg3_flag(tp, TSO_CAPABLE)) {
1da177e4
LT		 10519 err = tg3_load_tso_firmware(tp);
10520 if (err)
10521 return err;
10522 }
1da177e4
LT		 10523
10524 tp->tx_mode = TX_MODE_ENABLE;
f2096f94 10525
63c3a66f 10526 if (tg3_flag(tp, 5755_PLUS) ||
4153577a 10527 tg3_asic_rev(tp) == ASIC_REV_5906)
b1d05210 10528 tp->tx_mode |= TX_MODE_MBUF_LOCKUP_FIX;
f2096f94 10529
4153577a
JP		 10530 if (tg3_asic_rev(tp) == ASIC_REV_5720 ||
10531 tg3_asic_rev(tp) == ASIC_REV_5762) {
f2096f94
MC		 10532 val = TX_MODE_JMB_FRM_LEN | TX_MODE_CNT_DN_MODE;
10533 tp->tx_mode &= ~val;
10534 tp->tx_mode |= tr32(MAC_TX_MODE) & val;
10535 }
10536
1da177e4
LT		 10537 tw32_f(MAC_TX_MODE, tp->tx_mode);
10538 udelay(100);
10539
63c3a66f 10540 if (tg3_flag(tp, ENABLE_RSS)) {
bcebcc46 10541 tg3_rss_write_indir_tbl(tp);
baf8a94a
MC		 10542
10543 /* Setup the "secret" hash key. */
10544 tw32(MAC_RSS_HASH_KEY_0, 0x5f865437);
10545 tw32(MAC_RSS_HASH_KEY_1, 0xe4ac62cc);
10546 tw32(MAC_RSS_HASH_KEY_2, 0x50103a45);
10547 tw32(MAC_RSS_HASH_KEY_3, 0x36621985);
10548 tw32(MAC_RSS_HASH_KEY_4, 0xbf14c0e8);
10549 tw32(MAC_RSS_HASH_KEY_5, 0x1bc27a1e);
10550 tw32(MAC_RSS_HASH_KEY_6, 0x84f4b556);
10551 tw32(MAC_RSS_HASH_KEY_7, 0x094ea6fe);
10552 tw32(MAC_RSS_HASH_KEY_8, 0x7dda01e7);
10553 tw32(MAC_RSS_HASH_KEY_9, 0xc04d7481);
10554 }
10555
1da177e4 10556 tp->rx_mode = RX_MODE_ENABLE;
63c3a66f 10557 if (tg3_flag(tp, 5755_PLUS))
af36e6b6
MC		 10558 tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;
10559
378b72c8
NS		 10560 if (tg3_asic_rev(tp) == ASIC_REV_5762)
10561 tp->rx_mode |= RX_MODE_IPV4_FRAG_FIX;
10562
63c3a66f 10563 if (tg3_flag(tp, ENABLE_RSS))
baf8a94a
MC		 10564 tp->rx_mode |= RX_MODE_RSS_ENABLE |
10565 RX_MODE_RSS_ITBL_HASH_BITS_7 |
10566 RX_MODE_RSS_IPV6_HASH_EN |
10567 RX_MODE_RSS_TCP_IPV6_HASH_EN |
10568 RX_MODE_RSS_IPV4_HASH_EN |
10569 RX_MODE_RSS_TCP_IPV4_HASH_EN;
10570
1da177e4
LT		 10571 tw32_f(MAC_RX_MODE, tp->rx_mode);
10572 udelay(10);
10573
1da177e4
LT		 10574 tw32(MAC_LED_CTRL, tp->led_ctrl);
10575
10576 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
f07e9af3 10577 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
1da177e4
LT		 10578 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
10579 udelay(10);
10580 }
10581 tw32_f(MAC_RX_MODE, tp->rx_mode);
10582 udelay(10);
10583
f07e9af3 10584 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
4153577a
JP		 10585 if ((tg3_asic_rev(tp) == ASIC_REV_5704) &&
10586 !(tp->phy_flags & TG3_PHYFLG_SERDES_PREEMPHASIS)) {
1da177e4
LT		 10587 /* Set drive transmission level to 1.2V */
10588 /* only if the signal pre-emphasis bit is not set */
10589 val = tr32(MAC_SERDES_CFG);
10590 val &= 0xfffff000;
10591 val |= 0x880;
10592 tw32(MAC_SERDES_CFG, val);
10593 }
4153577a 10594 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5703_A1)
1da177e4
LT		 10595 tw32(MAC_SERDES_CFG, 0x616000);
10596 }
10597
10598 /* Prevent chip from dropping frames when flow control
10599 * is enabled.
10600 */
55086ad9 10601 if (tg3_flag(tp, 57765_CLASS))
666bc831
MC		 10602 val = 1;
10603 else
10604 val = 2;
10605 tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, val);
1da177e4 10606
4153577a 10607 if (tg3_asic_rev(tp) == ASIC_REV_5704 &&
f07e9af3 10608 (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
1da177e4 10609 /* Use hardware link auto-negotiation */
63c3a66f 10610 tg3_flag_set(tp, HW_AUTONEG);
1da177e4
LT		 10611 }
10612
f07e9af3 10613 if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
4153577a 10614 tg3_asic_rev(tp) == ASIC_REV_5714) {
d4d2c558
MC		 10615 u32 tmp;
10616
10617 tmp = tr32(SERDES_RX_CTRL);
10618 tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT);
10619 tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT;
10620 tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT;
10621 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
10622 }
10623
63c3a66f 10624 if (!tg3_flag(tp, USE_PHYLIB)) {
c6700ce2 10625 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
80096068 10626 tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER;
1da177e4 10627
953c96e0 10628 err = tg3_setup_phy(tp, false);
dd477003
MC		 10629 if (err)
10630 return err;
1da177e4 10631
f07e9af3
MC		 10632 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
10633 !(tp->phy_flags & TG3_PHYFLG_IS_FET)) {
dd477003
MC		 10634 u32 tmp;
10635
10636 /* Clear CRC stats. */
10637 if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) {
10638 tg3_writephy(tp, MII_TG3_TEST1,
10639 tmp | MII_TG3_TEST1_CRC_EN);
f08aa1a8 10640 tg3_readphy(tp, MII_TG3_RXR_COUNTERS, &tmp);
dd477003 10641 }
1da177e4
LT		 10642 }
10643 }
10644
10645 __tg3_set_rx_mode(tp->dev);
10646
10647 /* Initialize receive rules. */
10648 tw32(MAC_RCV_RULE_0, 0xc2000000 & RCV_RULE_DISABLE_MASK);
10649 tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
10650 tw32(MAC_RCV_RULE_1, 0x86000004 & RCV_RULE_DISABLE_MASK);
10651 tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
10652
63c3a66f 10653 if (tg3_flag(tp, 5705_PLUS) && !tg3_flag(tp, 5780_CLASS))
1da177e4
LT		 10654 limit = 8;
10655 else
10656 limit = 16;
63c3a66f 10657 if (tg3_flag(tp, ENABLE_ASF))
1da177e4
LT		 10658 limit -= 4;
10659 switch (limit) {
10660 case 16:
10661 tw32(MAC_RCV_RULE_15, 0); tw32(MAC_RCV_VALUE_15, 0);
10662 case 15:
10663 tw32(MAC_RCV_RULE_14, 0); tw32(MAC_RCV_VALUE_14, 0);
10664 case 14:
10665 tw32(MAC_RCV_RULE_13, 0); tw32(MAC_RCV_VALUE_13, 0);
10666 case 13:
10667 tw32(MAC_RCV_RULE_12, 0); tw32(MAC_RCV_VALUE_12, 0);
10668 case 12:
10669 tw32(MAC_RCV_RULE_11, 0); tw32(MAC_RCV_VALUE_11, 0);
10670 case 11:
10671 tw32(MAC_RCV_RULE_10, 0); tw32(MAC_RCV_VALUE_10, 0);
10672 case 10:
10673 tw32(MAC_RCV_RULE_9, 0); tw32(MAC_RCV_VALUE_9, 0);
10674 case 9:
10675 tw32(MAC_RCV_RULE_8, 0); tw32(MAC_RCV_VALUE_8, 0);
10676 case 8:
10677 tw32(MAC_RCV_RULE_7, 0); tw32(MAC_RCV_VALUE_7, 0);
10678 case 7:
10679 tw32(MAC_RCV_RULE_6, 0); tw32(MAC_RCV_VALUE_6, 0);
10680 case 6:
10681 tw32(MAC_RCV_RULE_5, 0); tw32(MAC_RCV_VALUE_5, 0);
10682 case 5:
10683 tw32(MAC_RCV_RULE_4, 0); tw32(MAC_RCV_VALUE_4, 0);
10684 case 4:
10685 /* tw32(MAC_RCV_RULE_3, 0); tw32(MAC_RCV_VALUE_3, 0); */
10686 case 3:
10687 /* tw32(MAC_RCV_RULE_2, 0); tw32(MAC_RCV_VALUE_2, 0); */
10688 case 2:
10689 case 1:
10690
10691 default:
10692 break;
855e1111 10693 }
1da177e4 10694
63c3a66f 10695 if (tg3_flag(tp, ENABLE_APE))
9ce768ea
MC		 10696 /* Write our heartbeat update interval to APE. */
10697 tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_INT_MS,
10698 APE_HOST_HEARTBEAT_INT_DISABLE);
0d3031d9 10699
1da177e4
LT		 10700 tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
10701
1da177e4
LT		 10702 return 0;
10703}
10704
10705/* Called at device open time to get the chip ready for
10706 * packet processing. Invoked with tp->lock held.
10707 */
953c96e0 10708static int tg3_init_hw(struct tg3 *tp, bool reset_phy)
1da177e4 10709{
df465abf
NS		 10710 /* Chip may have been just powered on. If so, the boot code may still
10711 * be running initialization. Wait for it to finish to avoid races in
10712 * accessing the hardware.
10713 */
10714 tg3_enable_register_access(tp);
10715 tg3_poll_fw(tp);
10716
1da177e4
LT		 10717 tg3_switch_clocks(tp);
10718
10719 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
10720
2f751b67 10721 return tg3_reset_hw(tp, reset_phy);
1da177e4
LT		 10722}
10723
aed93e0b
MC		 10724static void tg3_sd_scan_scratchpad(struct tg3 *tp, struct tg3_ocir *ocir)
10725{
10726 int i;
10727
10728 for (i = 0; i < TG3_SD_NUM_RECS; i++, ocir++) {
10729 u32 off = i * TG3_OCIR_LEN, len = TG3_OCIR_LEN;
10730
10731 tg3_ape_scratchpad_read(tp, (u32 *) ocir, off, len);
10732 off += len;
10733
10734 if (ocir->signature != TG3_OCIR_SIG_MAGIC ||
10735 !(ocir->version_flags & TG3_OCIR_FLAG_ACTIVE))
10736 memset(ocir, 0, TG3_OCIR_LEN);
10737 }
10738}
10739
10740/* sysfs attributes for hwmon */
10741static ssize_t tg3_show_temp(struct device *dev,
10742 struct device_attribute *devattr, char *buf)
10743{
aed93e0b 10744 struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr);
a2f4dfba 10745 struct tg3 *tp = dev_get_drvdata(dev);
aed93e0b
MC		 10746 u32 temperature;
10747
10748 spin_lock_bh(&tp->lock);
10749 tg3_ape_scratchpad_read(tp, &temperature, attr->index,
10750 sizeof(temperature));
10751 spin_unlock_bh(&tp->lock);
10752 return sprintf(buf, "%u\n", temperature);
10753}
10754
10755
10756static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, tg3_show_temp, NULL,
10757 TG3_TEMP_SENSOR_OFFSET);
10758static SENSOR_DEVICE_ATTR(temp1_crit, S_IRUGO, tg3_show_temp, NULL,
10759 TG3_TEMP_CAUTION_OFFSET);
10760static SENSOR_DEVICE_ATTR(temp1_max, S_IRUGO, tg3_show_temp, NULL,
10761 TG3_TEMP_MAX_OFFSET);
10762
a2f4dfba 10763static struct attribute *tg3_attrs[] = {
aed93e0b
MC		 10764 &sensor_dev_attr_temp1_input.dev_attr.attr,
10765 &sensor_dev_attr_temp1_crit.dev_attr.attr,
10766 &sensor_dev_attr_temp1_max.dev_attr.attr,
10767 NULL
10768};
a2f4dfba 10769ATTRIBUTE_GROUPS(tg3);
aed93e0b 10770
aed93e0b
MC		 10771static void tg3_hwmon_close(struct tg3 *tp)
10772{
aed93e0b
MC		 10773 if (tp->hwmon_dev) {
10774 hwmon_device_unregister(tp->hwmon_dev);
10775 tp->hwmon_dev = NULL;
aed93e0b 10776 }
aed93e0b
MC		 10777}
10778
10779static void tg3_hwmon_open(struct tg3 *tp)
10780{
a2f4dfba 10781 int i;
aed93e0b
MC		 10782 u32 size = 0;
10783 struct pci_dev *pdev = tp->pdev;
10784 struct tg3_ocir ocirs[TG3_SD_NUM_RECS];
10785
10786 tg3_sd_scan_scratchpad(tp, ocirs);
10787
10788 for (i = 0; i < TG3_SD_NUM_RECS; i++) {
10789 if (!ocirs[i].src_data_length)
10790 continue;
10791
10792 size += ocirs[i].src_hdr_length;
10793 size += ocirs[i].src_data_length;
10794 }
10795
10796 if (!size)
10797 return;
10798
a2f4dfba
GR		 10799 tp->hwmon_dev = hwmon_device_register_with_groups(&pdev->dev, "tg3",
10800 tp, tg3_groups);
aed93e0b
MC		 10801 if (IS_ERR(tp->hwmon_dev)) {
10802 tp->hwmon_dev = NULL;
10803 dev_err(&pdev->dev, "Cannot register hwmon device, aborting\n");
aed93e0b 10804 }
aed93e0b
MC		 10805}
10806
10807
1da177e4
LT		 10808#define TG3_STAT_ADD32(PSTAT, REG) \
10809do { u32 __val = tr32(REG); \
10810 (PSTAT)->low += __val; \
10811 if ((PSTAT)->low < __val) \
10812 (PSTAT)->high += 1; \
10813} while (0)
10814
10815static void tg3_periodic_fetch_stats(struct tg3 *tp)
10816{
10817 struct tg3_hw_stats *sp = tp->hw_stats;
10818
f4a46d1f 10819 if (!tp->link_up)
1da177e4
LT		 10820 return;
10821
10822 TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
10823 TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
10824 TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
10825 TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
10826 TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
10827 TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
10828 TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
10829 TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
10830 TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
10831 TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
10832 TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
10833 TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
10834 TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
9bc297ea 10835 if (unlikely(tg3_flag(tp, 5719_5720_RDMA_BUG) &&
091f0ea3
MC		 10836 (sp->tx_ucast_packets.low + sp->tx_mcast_packets.low +
10837 sp->tx_bcast_packets.low) > TG3_NUM_RDMA_CHANNELS)) {
10838 u32 val;
10839
10840 val = tr32(TG3_LSO_RD_DMA_CRPTEN_CTRL);
9bc297ea 10841 val &= ~tg3_lso_rd_dma_workaround_bit(tp);
091f0ea3 10842 tw32(TG3_LSO_RD_DMA_CRPTEN_CTRL, val);
9bc297ea 10843 tg3_flag_clear(tp, 5719_5720_RDMA_BUG);
091f0ea3 10844 }
1da177e4
LT		 10845
10846 TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
10847 TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
10848 TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
10849 TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
10850 TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
10851 TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
10852 TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
10853 TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
10854 TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
10855 TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
10856 TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
10857 TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
10858 TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
10859 TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
463d305b
MC		 10860
10861 TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT);
4153577a 10862 if (tg3_asic_rev(tp) != ASIC_REV_5717 &&
94962f7f 10863 tg3_asic_rev(tp) != ASIC_REV_5762 &&
4153577a
JP		 10864 tg3_chip_rev_id(tp) != CHIPREV_ID_5719_A0 &&
10865 tg3_chip_rev_id(tp) != CHIPREV_ID_5720_A0) {
4d958473
MC		 10866 TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT);
10867 } else {
10868 u32 val = tr32(HOSTCC_FLOW_ATTN);
10869 val = (val & HOSTCC_FLOW_ATTN_MBUF_LWM) ? 1 : 0;
10870 if (val) {
10871 tw32(HOSTCC_FLOW_ATTN, HOSTCC_FLOW_ATTN_MBUF_LWM);
10872 sp->rx_discards.low += val;
10873 if (sp->rx_discards.low < val)
10874 sp->rx_discards.high += 1;
10875 }
10876 sp->mbuf_lwm_thresh_hit = sp->rx_discards;
10877 }
463d305b 10878 TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT);
1da177e4
LT		 10879}
10880
0e6cf6a9
MC		 10881static void tg3_chk_missed_msi(struct tg3 *tp)
10882{
10883 u32 i;
10884
10885 for (i = 0; i < tp->irq_cnt; i++) {
10886 struct tg3_napi *tnapi = &tp->napi[i];
10887
10888 if (tg3_has_work(tnapi)) {
10889 if (tnapi->last_rx_cons == tnapi->rx_rcb_ptr &&
10890 tnapi->last_tx_cons == tnapi->tx_cons) {
10891 if (tnapi->chk_msi_cnt < 1) {
10892 tnapi->chk_msi_cnt++;
10893 return;
10894 }
7f230735 10895 tg3_msi(0, tnapi);
0e6cf6a9
MC		 10896 }
10897 }
10898 tnapi->chk_msi_cnt = 0;
10899 tnapi->last_rx_cons = tnapi->rx_rcb_ptr;
10900 tnapi->last_tx_cons = tnapi->tx_cons;
10901 }
10902}
10903
1da177e4
LT		 10904static void tg3_timer(unsigned long __opaque)
10905{
10906 struct tg3 *tp = (struct tg3 *) __opaque;
1da177e4 10907
5b190624 10908 if (tp->irq_sync || tg3_flag(tp, RESET_TASK_PENDING))
f475f163
MC		 10909 goto restart_timer;
10910
f47c11ee 10911 spin_lock(&tp->lock);
1da177e4 10912
4153577a 10913 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
55086ad9 10914 tg3_flag(tp, 57765_CLASS))
0e6cf6a9
MC		 10915 tg3_chk_missed_msi(tp);
10916
7e6c63f0
HM		 10917 if (tg3_flag(tp, FLUSH_POSTED_WRITES)) {
10918 /* BCM4785: Flush posted writes from GbE to host memory. */
10919 tr32(HOSTCC_MODE);
10920 }
10921
63c3a66f 10922 if (!tg3_flag(tp, TAGGED_STATUS)) {
fac9b83e
DM		 10923 /* All of this garbage is because when using non-tagged
10924 * IRQ status the mailbox/status_block protocol the chip
10925 * uses with the cpu is race prone.
10926 */
898a56f8 10927 if (tp->napi[0].hw_status->status & SD_STATUS_UPDATED) {
fac9b83e
DM		 10928 tw32(GRC_LOCAL_CTRL,
10929 tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
10930 } else {
10931 tw32(HOSTCC_MODE, tp->coalesce_mode |
fd2ce37f 10932 HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW);
fac9b83e 10933 }
1da177e4 10934
fac9b83e 10935 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
f47c11ee 10936 spin_unlock(&tp->lock);
db219973 10937 tg3_reset_task_schedule(tp);
5b190624 10938 goto restart_timer;
fac9b83e 10939 }
1da177e4
LT		 10940 }
10941
1da177e4
LT		 10942 /* This part only runs once per second. */
10943 if (!--tp->timer_counter) {
63c3a66f 10944 if (tg3_flag(tp, 5705_PLUS))
fac9b83e
DM		 10945 tg3_periodic_fetch_stats(tp);
10946
b0c5943f
MC		 10947 if (tp->setlpicnt && !--tp->setlpicnt)
10948 tg3_phy_eee_enable(tp);
52b02d04 10949
63c3a66f 10950 if (tg3_flag(tp, USE_LINKCHG_REG)) {
1da177e4
LT		 10951 u32 mac_stat;
10952 int phy_event;
10953
10954 mac_stat = tr32(MAC_STATUS);
10955
10956 phy_event = 0;
f07e9af3 10957 if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) {
1da177e4
LT		 10958 if (mac_stat & MAC_STATUS_MI_INTERRUPT)
10959 phy_event = 1;
10960 } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
10961 phy_event = 1;
10962
10963 if (phy_event)
953c96e0 10964 tg3_setup_phy(tp, false);
63c3a66f 10965 } else if (tg3_flag(tp, POLL_SERDES)) {
1da177e4
LT		 10966 u32 mac_stat = tr32(MAC_STATUS);
10967 int need_setup = 0;
10968
f4a46d1f 10969 if (tp->link_up &&
1da177e4
LT		 10970 (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
10971 need_setup = 1;
10972 }
f4a46d1f 10973 if (!tp->link_up &&
1da177e4
LT		 10974 (mac_stat & (MAC_STATUS_PCS_SYNCED |
10975 MAC_STATUS_SIGNAL_DET))) {
10976 need_setup = 1;
10977 }
10978 if (need_setup) {
3d3ebe74
MC		 10979 if (!tp->serdes_counter) {
10980 tw32_f(MAC_MODE,
10981 (tp->mac_mode &
10982 ~MAC_MODE_PORT_MODE_MASK));
10983 udelay(40);
10984 tw32_f(MAC_MODE, tp->mac_mode);
10985 udelay(40);
10986 }
953c96e0 10987 tg3_setup_phy(tp, false);
1da177e4 10988 }
f07e9af3 10989 } else if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
63c3a66f 10990 tg3_flag(tp, 5780_CLASS)) {
747e8f8b 10991 tg3_serdes_parallel_detect(tp);
1743b83c
NS		 10992 } else if (tg3_flag(tp, POLL_CPMU_LINK)) {
10993 u32 cpmu = tr32(TG3_CPMU_STATUS);
10994 bool link_up = !((cpmu & TG3_CPMU_STATUS_LINK_MASK) ==
10995 TG3_CPMU_STATUS_LINK_MASK);
10996
10997 if (link_up != tp->link_up)
10998 tg3_setup_phy(tp, false);
57d8b880 10999 }
1da177e4
LT		 11000
11001 tp->timer_counter = tp->timer_multiplier;
11002 }
11003
130b8e4d
MC		 11004 /* Heartbeat is only sent once every 2 seconds.
11005 *
11006 * The heartbeat is to tell the ASF firmware that the host
11007 * driver is still alive. In the event that the OS crashes,
11008 * ASF needs to reset the hardware to free up the FIFO space
11009 * that may be filled with rx packets destined for the host.
11010 * If the FIFO is full, ASF will no longer function properly.
11011 *
11012 * Unintended resets have been reported on real time kernels
11013 * where the timer doesn't run on time. Netpoll will also have
11014 * same problem.
11015 *
11016 * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware
11017 * to check the ring condition when the heartbeat is expiring
11018 * before doing the reset. This will prevent most unintended
11019 * resets.
11020 */
1da177e4 11021 if (!--tp->asf_counter) {
63c3a66f 11022 if (tg3_flag(tp, ENABLE_ASF) && !tg3_flag(tp, ENABLE_APE)) {
7c5026aa
MC		 11023 tg3_wait_for_event_ack(tp);
11024
bbadf503 11025 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
130b8e4d 11026 FWCMD_NICDRV_ALIVE3);
bbadf503 11027 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
c6cdf436
MC		 11028 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX,
11029 TG3_FW_UPDATE_TIMEOUT_SEC);
4ba526ce
MC		 11030
11031 tg3_generate_fw_event(tp);
1da177e4
LT		 11032 }
11033 tp->asf_counter = tp->asf_multiplier;
11034 }
11035
f47c11ee 11036 spin_unlock(&tp->lock);
1da177e4 11037
f475f163 11038restart_timer:
1da177e4
LT		 11039 tp->timer.expires = jiffies + tp->timer_offset;
11040 add_timer(&tp->timer);
11041}
11042
229b1ad1 11043static void tg3_timer_init(struct tg3 *tp)
21f7638e
MC		 11044{
11045 if (tg3_flag(tp, TAGGED_STATUS) &&
4153577a 11046 tg3_asic_rev(tp) != ASIC_REV_5717 &&
21f7638e
MC		 11047 !tg3_flag(tp, 57765_CLASS))
11048 tp->timer_offset = HZ;
11049 else
11050 tp->timer_offset = HZ / 10;
11051
11052 BUG_ON(tp->timer_offset > HZ);
11053
11054 tp->timer_multiplier = (HZ / tp->timer_offset);
11055 tp->asf_multiplier = (HZ / tp->timer_offset) *
11056 TG3_FW_UPDATE_FREQ_SEC;
11057
11058 init_timer(&tp->timer);
11059 tp->timer.data = (unsigned long) tp;
11060 tp->timer.function = tg3_timer;
11061}
11062
11063static void tg3_timer_start(struct tg3 *tp)
11064{
11065 tp->asf_counter = tp->asf_multiplier;
11066 tp->timer_counter = tp->timer_multiplier;
11067
11068 tp->timer.expires = jiffies + tp->timer_offset;
11069 add_timer(&tp->timer);
11070}
11071
11072static void tg3_timer_stop(struct tg3 *tp)
11073{
11074 del_timer_sync(&tp->timer);
11075}
11076
11077/* Restart hardware after configuration changes, self-test, etc.
11078 * Invoked with tp->lock held.
11079 */
953c96e0 11080static int tg3_restart_hw(struct tg3 *tp, bool reset_phy)
21f7638e
MC		 11081 __releases(tp->lock)
11082 __acquires(tp->lock)
11083{
11084 int err;
11085
11086 err = tg3_init_hw(tp, reset_phy);
11087 if (err) {
11088 netdev_err(tp->dev,
11089 "Failed to re-initialize device, aborting\n");
11090 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
11091 tg3_full_unlock(tp);
11092 tg3_timer_stop(tp);
11093 tp->irq_sync = 0;
11094 tg3_napi_enable(tp);
11095 dev_close(tp->dev);
11096 tg3_full_lock(tp, 0);
11097 }
11098 return err;
11099}
11100
11101static void tg3_reset_task(struct work_struct *work)
11102{
11103 struct tg3 *tp = container_of(work, struct tg3, reset_task);
11104 int err;
11105
11106 tg3_full_lock(tp, 0);
11107
11108 if (!netif_running(tp->dev)) {
11109 tg3_flag_clear(tp, RESET_TASK_PENDING);
11110 tg3_full_unlock(tp);
11111 return;
11112 }
11113
11114 tg3_full_unlock(tp);
11115
11116 tg3_phy_stop(tp);
11117
11118 tg3_netif_stop(tp);
11119
11120 tg3_full_lock(tp, 1);
11121
11122 if (tg3_flag(tp, TX_RECOVERY_PENDING)) {
11123 tp->write32_tx_mbox = tg3_write32_tx_mbox;
11124 tp->write32_rx_mbox = tg3_write_flush_reg32;
11125 tg3_flag_set(tp, MBOX_WRITE_REORDER);
11126 tg3_flag_clear(tp, TX_RECOVERY_PENDING);
11127 }
11128
11129 tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
953c96e0 11130 err = tg3_init_hw(tp, true);
21f7638e
MC		 11131 if (err)
11132 goto out;
11133
11134 tg3_netif_start(tp);
11135
11136out:
11137 tg3_full_unlock(tp);
11138
11139 if (!err)
11140 tg3_phy_start(tp);
11141
11142 tg3_flag_clear(tp, RESET_TASK_PENDING);
11143}
11144
4f125f42 11145static int tg3_request_irq(struct tg3 *tp, int irq_num)
fcfa0a32 11146{
7d12e780 11147 irq_handler_t fn;
fcfa0a32 11148 unsigned long flags;
4f125f42
MC		 11149 char *name;
11150 struct tg3_napi *tnapi = &tp->napi[irq_num];
11151
11152 if (tp->irq_cnt == 1)
11153 name = tp->dev->name;
11154 else {
11155 name = &tnapi->irq_lbl[0];
21e315e1
NS		 11156 if (tnapi->tx_buffers && tnapi->rx_rcb)
11157 snprintf(name, IFNAMSIZ,
11158 "%s-txrx-%d", tp->dev->name, irq_num);
11159 else if (tnapi->tx_buffers)
11160 snprintf(name, IFNAMSIZ,
11161 "%s-tx-%d", tp->dev->name, irq_num);
11162 else if (tnapi->rx_rcb)
11163 snprintf(name, IFNAMSIZ,
11164 "%s-rx-%d", tp->dev->name, irq_num);
11165 else
11166 snprintf(name, IFNAMSIZ,
11167 "%s-%d", tp->dev->name, irq_num);
4f125f42
MC		 11168 name[IFNAMSIZ-1] = 0;
11169 }
fcfa0a32 11170
63c3a66f 11171 if (tg3_flag(tp, USING_MSI) || tg3_flag(tp, USING_MSIX)) {
fcfa0a32 11172 fn = tg3_msi;
63c3a66f 11173 if (tg3_flag(tp, 1SHOT_MSI))
fcfa0a32 11174 fn = tg3_msi_1shot;
ab392d2d 11175 flags = 0;
fcfa0a32
MC		 11176 } else {
11177 fn = tg3_interrupt;
63c3a66f 11178 if (tg3_flag(tp, TAGGED_STATUS))
fcfa0a32 11179 fn = tg3_interrupt_tagged;
ab392d2d 11180 flags = IRQF_SHARED;
fcfa0a32 11181 }
4f125f42
MC		 11182
11183 return request_irq(tnapi->irq_vec, fn, flags, name, tnapi);
fcfa0a32
MC		 11184}
11185
7938109f
MC		 11186static int tg3_test_interrupt(struct tg3 *tp)
11187{
09943a18 11188 struct tg3_napi *tnapi = &tp->napi[0];
7938109f 11189 struct net_device *dev = tp->dev;
b16250e3 11190 int err, i, intr_ok = 0;
f6eb9b1f 11191 u32 val;
7938109f 11192
d4bc3927
MC		 11193 if (!netif_running(dev))
11194 return -ENODEV;
11195
7938109f
MC		 11196 tg3_disable_ints(tp);
11197
4f125f42 11198 free_irq(tnapi->irq_vec, tnapi);
7938109f 11199
f6eb9b1f
MC		 11200 /*
11201 * Turn off MSI one shot mode. Otherwise this test has no
11202 * observable way to know whether the interrupt was delivered.
11203 */
3aa1cdf8 11204 if (tg3_flag(tp, 57765_PLUS)) {
f6eb9b1f
MC		 11205 val = tr32(MSGINT_MODE) | MSGINT_MODE_ONE_SHOT_DISABLE;
11206 tw32(MSGINT_MODE, val);
11207 }
11208
4f125f42 11209 err = request_irq(tnapi->irq_vec, tg3_test_isr,
f274fd9a 11210 IRQF_SHARED, dev->name, tnapi);
7938109f
MC		 11211 if (err)
11212 return err;
11213
898a56f8 11214 tnapi->hw_status->status &= ~SD_STATUS_UPDATED;
7938109f
MC		 11215 tg3_enable_ints(tp);
11216
11217 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
fd2ce37f 11218 tnapi->coal_now);
7938109f
MC		 11219
11220 for (i = 0; i < 5; i++) {
b16250e3
MC		 11221 u32 int_mbox, misc_host_ctrl;
11222
898a56f8 11223 int_mbox = tr32_mailbox(tnapi->int_mbox);
b16250e3
MC		 11224 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
11225
11226 if ((int_mbox != 0) ||
11227 (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) {
11228 intr_ok = 1;
7938109f 11229 break;
b16250e3
MC		 11230 }
11231
3aa1cdf8
MC		 11232 if (tg3_flag(tp, 57765_PLUS) &&
11233 tnapi->hw_status->status_tag != tnapi->last_tag)
11234 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
11235
7938109f
MC		 11236 msleep(10);
11237 }
11238
11239 tg3_disable_ints(tp);
11240
4f125f42 11241 free_irq(tnapi->irq_vec, tnapi);
6aa20a22 11242
4f125f42 11243 err = tg3_request_irq(tp, 0);
7938109f
MC		 11244
11245 if (err)
11246 return err;
11247
f6eb9b1f
MC		 11248 if (intr_ok) {
11249 /* Reenable MSI one shot mode. */
5b39de91 11250 if (tg3_flag(tp, 57765_PLUS) && tg3_flag(tp, 1SHOT_MSI)) {
f6eb9b1f
MC		 11251 val = tr32(MSGINT_MODE) & ~MSGINT_MODE_ONE_SHOT_DISABLE;
11252 tw32(MSGINT_MODE, val);
11253 }
7938109f 11254 return 0;
f6eb9b1f 11255 }
7938109f
MC		 11256
11257 return -EIO;
11258}
11259
11260/* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
11261 * successfully restored
11262 */
11263static int tg3_test_msi(struct tg3 *tp)
11264{
7938109f
MC		 11265 int err;
11266 u16 pci_cmd;
11267
63c3a66f 11268 if (!tg3_flag(tp, USING_MSI))
7938109f
MC		 11269 return 0;
11270
11271 /* Turn off SERR reporting in case MSI terminates with Master
11272 * Abort.
11273 */
11274 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
11275 pci_write_config_word(tp->pdev, PCI_COMMAND,
11276 pci_cmd & ~PCI_COMMAND_SERR);
11277
11278 err = tg3_test_interrupt(tp);
11279
11280 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
11281
11282 if (!err)
11283 return 0;
11284
11285 /* other failures */
11286 if (err != -EIO)
11287 return err;
11288
11289 /* MSI test failed, go back to INTx mode */
5129c3a3
MC		 11290 netdev_warn(tp->dev, "No interrupt was generated using MSI. Switching "
11291 "to INTx mode. Please report this failure to the PCI "
11292 "maintainer and include system chipset information\n");
7938109f 11293
4f125f42 11294 free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
09943a18 11295
7938109f
MC		 11296 pci_disable_msi(tp->pdev);
11297
63c3a66f 11298 tg3_flag_clear(tp, USING_MSI);
dc8bf1b1 11299 tp->napi[0].irq_vec = tp->pdev->irq;
7938109f 11300
4f125f42 11301 err = tg3_request_irq(tp, 0);
7938109f
MC		 11302 if (err)
11303 return err;
11304
11305 /* Need to reset the chip because the MSI cycle may have terminated
11306 * with Master Abort.
11307 */
f47c11ee 11308 tg3_full_lock(tp, 1);
7938109f 11309
944d980e 11310 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
953c96e0 11311 err = tg3_init_hw(tp, true);
7938109f 11312
f47c11ee 11313 tg3_full_unlock(tp);
7938109f
MC		 11314
11315 if (err)
4f125f42 11316 free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
7938109f
MC		 11317
11318 return err;
11319}
11320
9e9fd12d
MC		 11321static int tg3_request_firmware(struct tg3 *tp)
11322{
77997ea3 11323 const struct tg3_firmware_hdr *fw_hdr;
9e9fd12d
MC		 11324
11325 if (request_firmware(&tp->fw, tp->fw_needed, &tp->pdev->dev)) {
05dbe005
JP		 11326 netdev_err(tp->dev, "Failed to load firmware \"%s\"\n",
11327 tp->fw_needed);
9e9fd12d
MC		 11328 return -ENOENT;
11329 }
11330
77997ea3 11331 fw_hdr = (struct tg3_firmware_hdr *)tp->fw->data;
9e9fd12d
MC		 11332
11333 /* Firmware blob starts with version numbers, followed by
11334 * start address and _full_ length including BSS sections
11335 * (which must be longer than the actual data, of course
11336 */
11337
77997ea3
NS		 11338 tp->fw_len = be32_to_cpu(fw_hdr->len); /* includes bss */
11339 if (tp->fw_len < (tp->fw->size - TG3_FW_HDR_LEN)) {
05dbe005
JP		 11340 netdev_err(tp->dev, "bogus length %d in \"%s\"\n",
11341 tp->fw_len, tp->fw_needed);
9e9fd12d
MC		 11342 release_firmware(tp->fw);
11343 tp->fw = NULL;
11344 return -EINVAL;
11345 }
11346
11347 /* We no longer need firmware; we have it. */
11348 tp->fw_needed = NULL;
11349 return 0;
11350}
11351
9102426a 11352static u32 tg3_irq_count(struct tg3 *tp)
679563f4 11353{
9102426a 11354 u32 irq_cnt = max(tp->rxq_cnt, tp->txq_cnt);
679563f4 11355
9102426a 11356 if (irq_cnt > 1) {
c3b5003b
MC		 11357 /* We want as many rx rings enabled as there are cpus.
11358 * In multiqueue MSI-X mode, the first MSI-X vector
11359 * only deals with link interrupts, etc, so we add
11360 * one to the number of vectors we are requesting.
11361 */
9102426a 11362 irq_cnt = min_t(unsigned, irq_cnt + 1, tp->irq_max);
c3b5003b 11363 }
679563f4 11364
9102426a
MC		 11365 return irq_cnt;
11366}
11367
11368static bool tg3_enable_msix(struct tg3 *tp)
11369{
11370 int i, rc;
86449944 11371 struct msix_entry msix_ent[TG3_IRQ_MAX_VECS];
9102426a 11372
0968169c
MC		 11373 tp->txq_cnt = tp->txq_req;
11374 tp->rxq_cnt = tp->rxq_req;
11375 if (!tp->rxq_cnt)
11376 tp->rxq_cnt = netif_get_num_default_rss_queues();
9102426a
MC		 11377 if (tp->rxq_cnt > tp->rxq_max)
11378 tp->rxq_cnt = tp->rxq_max;
cf6d6ea6
MC		 11379
11380 /* Disable multiple TX rings by default. Simple round-robin hardware
11381 * scheduling of the TX rings can cause starvation of rings with
11382 * small packets when other rings have TSO or jumbo packets.
11383 */
11384 if (!tp->txq_req)
11385 tp->txq_cnt = 1;
9102426a
MC		 11386
11387 tp->irq_cnt = tg3_irq_count(tp);
11388
679563f4
MC		 11389 for (i = 0; i < tp->irq_max; i++) {
11390 msix_ent[i].entry = i;
11391 msix_ent[i].vector = 0;
11392 }
11393
6f1f411a 11394 rc = pci_enable_msix_range(tp->pdev, msix_ent, 1, tp->irq_cnt);
2430b031
MC		 11395 if (rc < 0) {
11396 return false;
6f1f411a 11397 } else if (rc < tp->irq_cnt) {
05dbe005
JP		 11398 netdev_notice(tp->dev, "Requested %d MSI-X vectors, received %d\n",
11399 tp->irq_cnt, rc);
679563f4 11400 tp->irq_cnt = rc;
49a359e3 11401 tp->rxq_cnt = max(rc - 1, 1);
9102426a
MC		 11402 if (tp->txq_cnt)
11403 tp->txq_cnt = min(tp->rxq_cnt, tp->txq_max);
679563f4
MC		 11404 }
11405
11406 for (i = 0; i < tp->irq_max; i++)
11407 tp->napi[i].irq_vec = msix_ent[i].vector;
11408
49a359e3 11409 if (netif_set_real_num_rx_queues(tp->dev, tp->rxq_cnt)) {
2ddaad39
BH		 11410 pci_disable_msix(tp->pdev);
11411 return false;
11412 }
b92b9040 11413
9102426a
MC		 11414 if (tp->irq_cnt == 1)
11415 return true;
d78b59f5 11416
9102426a
MC		 11417 tg3_flag_set(tp, ENABLE_RSS);
11418
11419 if (tp->txq_cnt > 1)
11420 tg3_flag_set(tp, ENABLE_TSS);
11421
11422 netif_set_real_num_tx_queues(tp->dev, tp->txq_cnt);
2430b031 11423
679563f4
MC		 11424 return true;
11425}
11426
07b0173c
MC		 11427static void tg3_ints_init(struct tg3 *tp)
11428{
63c3a66f
JP		 11429 if ((tg3_flag(tp, SUPPORT_MSI) || tg3_flag(tp, SUPPORT_MSIX)) &&
11430 !tg3_flag(tp, TAGGED_STATUS)) {
07b0173c
MC		 11431 /* All MSI supporting chips should support tagged
11432 * status. Assert that this is the case.
11433 */
5129c3a3
MC		 11434 netdev_warn(tp->dev,
11435 "MSI without TAGGED_STATUS? Not using MSI\n");
679563f4 11436 goto defcfg;
07b0173c 11437 }
4f125f42 11438
63c3a66f
JP		 11439 if (tg3_flag(tp, SUPPORT_MSIX) && tg3_enable_msix(tp))
11440 tg3_flag_set(tp, USING_MSIX);
11441 else if (tg3_flag(tp, SUPPORT_MSI) && pci_enable_msi(tp->pdev) == 0)
11442 tg3_flag_set(tp, USING_MSI);
679563f4 11443
63c3a66f 11444 if (tg3_flag(tp, USING_MSI) || tg3_flag(tp, USING_MSIX)) {
679563f4 11445 u32 msi_mode = tr32(MSGINT_MODE);
63c3a66f 11446 if (tg3_flag(tp, USING_MSIX) && tp->irq_cnt > 1)
baf8a94a 11447 msi_mode |= MSGINT_MODE_MULTIVEC_EN;
5b39de91
MC		 11448 if (!tg3_flag(tp, 1SHOT_MSI))
11449 msi_mode |= MSGINT_MODE_ONE_SHOT_DISABLE;
679563f4
MC		 11450 tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
11451 }
11452defcfg:
63c3a66f 11453 if (!tg3_flag(tp, USING_MSIX)) {
679563f4
MC		 11454 tp->irq_cnt = 1;
11455 tp->napi[0].irq_vec = tp->pdev->irq;
49a359e3
MC		 11456 }
11457
11458 if (tp->irq_cnt == 1) {
11459 tp->txq_cnt = 1;
11460 tp->rxq_cnt = 1;
2ddaad39 11461 netif_set_real_num_tx_queues(tp->dev, 1);
85407885 11462 netif_set_real_num_rx_queues(tp->dev, 1);
679563f4 11463 }
07b0173c
MC		 11464}
11465
11466static void tg3_ints_fini(struct tg3 *tp)
11467{
63c3a66f 11468 if (tg3_flag(tp, USING_MSIX))
679563f4 11469 pci_disable_msix(tp->pdev);
63c3a66f 11470 else if (tg3_flag(tp, USING_MSI))
679563f4 11471 pci_disable_msi(tp->pdev);
63c3a66f
JP		 11472 tg3_flag_clear(tp, USING_MSI);
11473 tg3_flag_clear(tp, USING_MSIX);
11474 tg3_flag_clear(tp, ENABLE_RSS);
11475 tg3_flag_clear(tp, ENABLE_TSS);
07b0173c
MC		 11476}
11477
be947307
MC		 11478static int tg3_start(struct tg3 *tp, bool reset_phy, bool test_irq,
11479 bool init)
1da177e4 11480{
d8f4cd38 11481 struct net_device *dev = tp->dev;
4f125f42 11482 int i, err;
1da177e4 11483
679563f4
MC		 11484 /*
11485 * Setup interrupts first so we know how
11486 * many NAPI resources to allocate
11487 */
11488 tg3_ints_init(tp);
11489
90415477 11490 tg3_rss_check_indir_tbl(tp);
bcebcc46 11491
1da177e4
LT		 11492 /* The placement of this call is tied
11493 * to the setup and use of Host TX descriptors.
11494 */
11495 err = tg3_alloc_consistent(tp);
11496 if (err)
4a5f46f2 11497 goto out_ints_fini;
88b06bc2 11498
66cfd1bd
MC		 11499 tg3_napi_init(tp);
11500
fed97810 11501 tg3_napi_enable(tp);
1da177e4 11502
4f125f42
MC		 11503 for (i = 0; i < tp->irq_cnt; i++) {
11504 struct tg3_napi *tnapi = &tp->napi[i];
11505 err = tg3_request_irq(tp, i);
11506 if (err) {
5bc09186
MC		 11507 for (i--; i >= 0; i--) {
11508 tnapi = &tp->napi[i];
4f125f42 11509 free_irq(tnapi->irq_vec, tnapi);
5bc09186 11510 }
4a5f46f2 11511 goto out_napi_fini;
4f125f42
MC		 11512 }
11513 }
1da177e4 11514
f47c11ee 11515 tg3_full_lock(tp, 0);
1da177e4 11516
2e460fc0
NS		 11517 if (init)
11518 tg3_ape_driver_state_change(tp, RESET_KIND_INIT);
11519
d8f4cd38 11520 err = tg3_init_hw(tp, reset_phy);
1da177e4 11521 if (err) {
944d980e 11522 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4 11523 tg3_free_rings(tp);
1da177e4
LT		 11524 }
11525
f47c11ee 11526 tg3_full_unlock(tp);
1da177e4 11527
07b0173c 11528 if (err)
4a5f46f2 11529 goto out_free_irq;
1da177e4 11530
d8f4cd38 11531 if (test_irq && tg3_flag(tp, USING_MSI)) {
7938109f 11532 err = tg3_test_msi(tp);
fac9b83e 11533
7938109f 11534 if (err) {
f47c11ee 11535 tg3_full_lock(tp, 0);
944d980e 11536 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7938109f 11537 tg3_free_rings(tp);
f47c11ee 11538 tg3_full_unlock(tp);
7938109f 11539
4a5f46f2 11540 goto out_napi_fini;
7938109f 11541 }
fcfa0a32 11542
63c3a66f 11543 if (!tg3_flag(tp, 57765_PLUS) && tg3_flag(tp, USING_MSI)) {
f6eb9b1f 11544 u32 val = tr32(PCIE_TRANSACTION_CFG);
fcfa0a32 11545
f6eb9b1f
MC		 11546 tw32(PCIE_TRANSACTION_CFG,
11547 val | PCIE_TRANS_CFG_1SHOT_MSI);
fcfa0a32 11548 }
7938109f
MC		 11549 }
11550
b02fd9e3
MC		 11551 tg3_phy_start(tp);
11552
aed93e0b
MC		 11553 tg3_hwmon_open(tp);
11554
f47c11ee 11555 tg3_full_lock(tp, 0);
1da177e4 11556
21f7638e 11557 tg3_timer_start(tp);
63c3a66f 11558 tg3_flag_set(tp, INIT_COMPLETE);
1da177e4
LT		 11559 tg3_enable_ints(tp);
11560
be947307
MC		 11561 if (init)
11562 tg3_ptp_init(tp);
11563 else
11564 tg3_ptp_resume(tp);
11565
11566
f47c11ee 11567 tg3_full_unlock(tp);
1da177e4 11568
fe5f5787 11569 netif_tx_start_all_queues(dev);
1da177e4 11570
06c03c02
MB		 11571 /*
11572 * Reset loopback feature if it was turned on while the device was down
11573 * make sure that it's installed properly now.
11574 */
11575 if (dev->features & NETIF_F_LOOPBACK)
11576 tg3_set_loopback(dev, dev->features);
11577
1da177e4 11578 return 0;
07b0173c 11579
4a5f46f2 11580out_free_irq:
4f125f42
MC		 11581 for (i = tp->irq_cnt - 1; i >= 0; i--) {
11582 struct tg3_napi *tnapi = &tp->napi[i];
11583 free_irq(tnapi->irq_vec, tnapi);
11584 }
07b0173c 11585
4a5f46f2 11586out_napi_fini:
fed97810 11587 tg3_napi_disable(tp);
66cfd1bd 11588 tg3_napi_fini(tp);
07b0173c 11589 tg3_free_consistent(tp);
679563f4 11590
4a5f46f2 11591out_ints_fini:
679563f4 11592 tg3_ints_fini(tp);
d8f4cd38 11593
07b0173c 11594 return err;
1da177e4
LT		 11595}
11596
65138594 11597static void tg3_stop(struct tg3 *tp)
1da177e4 11598{
4f125f42 11599 int i;
1da177e4 11600
db219973 11601 tg3_reset_task_cancel(tp);
bd473da3 11602 tg3_netif_stop(tp);
1da177e4 11603
21f7638e 11604 tg3_timer_stop(tp);
1da177e4 11605
aed93e0b
MC		 11606 tg3_hwmon_close(tp);
11607
24bb4fb6
MC		 11608 tg3_phy_stop(tp);
11609
f47c11ee 11610 tg3_full_lock(tp, 1);
1da177e4
LT		 11611
11612 tg3_disable_ints(tp);
11613
944d980e 11614 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4 11615 tg3_free_rings(tp);
63c3a66f 11616 tg3_flag_clear(tp, INIT_COMPLETE);
1da177e4 11617
f47c11ee 11618 tg3_full_unlock(tp);
1da177e4 11619
4f125f42
MC		 11620 for (i = tp->irq_cnt - 1; i >= 0; i--) {
11621 struct tg3_napi *tnapi = &tp->napi[i];
11622 free_irq(tnapi->irq_vec, tnapi);
11623 }
07b0173c
MC		 11624
11625 tg3_ints_fini(tp);
1da177e4 11626
66cfd1bd
MC		 11627 tg3_napi_fini(tp);
11628
1da177e4 11629 tg3_free_consistent(tp);
65138594
MC		 11630}
11631
d8f4cd38
MC		 11632static int tg3_open(struct net_device *dev)
11633{
11634 struct tg3 *tp = netdev_priv(dev);
11635 int err;
11636
0486a063
IV		 11637 if (tp->pcierr_recovery) {
11638 netdev_err(dev, "Failed to open device. PCI error recovery "
11639 "in progress\n");
11640 return -EAGAIN;
11641 }
11642
d8f4cd38
MC		 11643 if (tp->fw_needed) {
11644 err = tg3_request_firmware(tp);
c4dab506
NS		 11645 if (tg3_asic_rev(tp) == ASIC_REV_57766) {
11646 if (err) {
11647 netdev_warn(tp->dev, "EEE capability disabled\n");
11648 tp->phy_flags &= ~TG3_PHYFLG_EEE_CAP;
11649 } else if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP)) {
11650 netdev_warn(tp->dev, "EEE capability restored\n");
11651 tp->phy_flags |= TG3_PHYFLG_EEE_CAP;
11652 }
11653 } else if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0) {
d8f4cd38
MC		 11654 if (err)
11655 return err;
11656 } else if (err) {
11657 netdev_warn(tp->dev, "TSO capability disabled\n");
11658 tg3_flag_clear(tp, TSO_CAPABLE);
11659 } else if (!tg3_flag(tp, TSO_CAPABLE)) {
11660 netdev_notice(tp->dev, "TSO capability restored\n");
11661 tg3_flag_set(tp, TSO_CAPABLE);
11662 }
11663 }
11664
f4a46d1f 11665 tg3_carrier_off(tp);
d8f4cd38
MC		 11666
11667 err = tg3_power_up(tp);
11668 if (err)
11669 return err;
11670
11671 tg3_full_lock(tp, 0);
11672
11673 tg3_disable_ints(tp);
11674 tg3_flag_clear(tp, INIT_COMPLETE);
11675
11676 tg3_full_unlock(tp);
11677
942d1af0
NS		 11678 err = tg3_start(tp,
11679 !(tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN),
11680 true, true);
d8f4cd38
MC		 11681 if (err) {
11682 tg3_frob_aux_power(tp, false);
11683 pci_set_power_state(tp->pdev, PCI_D3hot);
11684 }
be947307 11685
7d41e49a
MC		 11686 if (tg3_flag(tp, PTP_CAPABLE)) {
11687 tp->ptp_clock = ptp_clock_register(&tp->ptp_info,
11688 &tp->pdev->dev);
11689 if (IS_ERR(tp->ptp_clock))
11690 tp->ptp_clock = NULL;
11691 }
11692
07b0173c 11693 return err;
1da177e4
LT		 11694}
11695
1da177e4
LT		 11696static int tg3_close(struct net_device *dev)
11697{
11698 struct tg3 *tp = netdev_priv(dev);
11699
0486a063
IV		 11700 if (tp->pcierr_recovery) {
11701 netdev_err(dev, "Failed to close device. PCI error recovery "
11702 "in progress\n");
11703 return -EAGAIN;
11704 }
11705
be947307
MC		 11706 tg3_ptp_fini(tp);
11707
65138594 11708 tg3_stop(tp);
1da177e4 11709
92feeabf
MC		 11710 /* Clear stats across close / open calls */
11711 memset(&tp->net_stats_prev, 0, sizeof(tp->net_stats_prev));
11712 memset(&tp->estats_prev, 0, sizeof(tp->estats_prev));
1da177e4 11713
8496e85c
RW		 11714 if (pci_device_is_present(tp->pdev)) {
11715 tg3_power_down_prepare(tp);
bc1c7567 11716
8496e85c
RW		 11717 tg3_carrier_off(tp);
11718 }
1da177e4
LT		 11719 return 0;
11720}
11721
511d2224 11722static inline u64 get_stat64(tg3_stat64_t *val)
816f8b86
SB		 11723{
11724 return ((u64)val->high << 32) | ((u64)val->low);
11725}
11726
65ec698d 11727static u64 tg3_calc_crc_errors(struct tg3 *tp)
1da177e4
LT		 11728{
11729 struct tg3_hw_stats *hw_stats = tp->hw_stats;
11730
f07e9af3 11731 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
4153577a
JP		 11732 (tg3_asic_rev(tp) == ASIC_REV_5700 ||
11733 tg3_asic_rev(tp) == ASIC_REV_5701)) {
1da177e4
LT		 11734 u32 val;
11735
569a5df8
MC		 11736 if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) {
11737 tg3_writephy(tp, MII_TG3_TEST1,
11738 val | MII_TG3_TEST1_CRC_EN);
f08aa1a8 11739 tg3_readphy(tp, MII_TG3_RXR_COUNTERS, &val);
1da177e4
LT		 11740 } else
11741 val = 0;
1da177e4
LT		 11742
11743 tp->phy_crc_errors += val;
11744
11745 return tp->phy_crc_errors;
11746 }
11747
11748 return get_stat64(&hw_stats->rx_fcs_errors);
11749}
11750
11751#define ESTAT_ADD(member) \
11752 estats->member = old_estats->member + \
511d2224 11753 get_stat64(&hw_stats->member)
1da177e4 11754
65ec698d 11755static void tg3_get_estats(struct tg3 *tp, struct tg3_ethtool_stats *estats)
1da177e4 11756{
1da177e4
LT		 11757 struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
11758 struct tg3_hw_stats *hw_stats = tp->hw_stats;
11759
1da177e4
LT		 11760 ESTAT_ADD(rx_octets);
11761 ESTAT_ADD(rx_fragments);
11762 ESTAT_ADD(rx_ucast_packets);
11763 ESTAT_ADD(rx_mcast_packets);
11764 ESTAT_ADD(rx_bcast_packets);
11765 ESTAT_ADD(rx_fcs_errors);
11766 ESTAT_ADD(rx_align_errors);
11767 ESTAT_ADD(rx_xon_pause_rcvd);
11768 ESTAT_ADD(rx_xoff_pause_rcvd);
11769 ESTAT_ADD(rx_mac_ctrl_rcvd);
11770 ESTAT_ADD(rx_xoff_entered);
11771 ESTAT_ADD(rx_frame_too_long_errors);
11772 ESTAT_ADD(rx_jabbers);
11773 ESTAT_ADD(rx_undersize_packets);
11774 ESTAT_ADD(rx_in_length_errors);
11775 ESTAT_ADD(rx_out_length_errors);
11776 ESTAT_ADD(rx_64_or_less_octet_packets);
11777 ESTAT_ADD(rx_65_to_127_octet_packets);
11778 ESTAT_ADD(rx_128_to_255_octet_packets);
11779 ESTAT_ADD(rx_256_to_511_octet_packets);
11780 ESTAT_ADD(rx_512_to_1023_octet_packets);
11781 ESTAT_ADD(rx_1024_to_1522_octet_packets);
11782 ESTAT_ADD(rx_1523_to_2047_octet_packets);
11783 ESTAT_ADD(rx_2048_to_4095_octet_packets);
11784 ESTAT_ADD(rx_4096_to_8191_octet_packets);
11785 ESTAT_ADD(rx_8192_to_9022_octet_packets);
11786
11787 ESTAT_ADD(tx_octets);
11788 ESTAT_ADD(tx_collisions);
11789 ESTAT_ADD(tx_xon_sent);
11790 ESTAT_ADD(tx_xoff_sent);
11791 ESTAT_ADD(tx_flow_control);
11792 ESTAT_ADD(tx_mac_errors);
11793 ESTAT_ADD(tx_single_collisions);
11794 ESTAT_ADD(tx_mult_collisions);
11795 ESTAT_ADD(tx_deferred);
11796 ESTAT_ADD(tx_excessive_collisions);
11797 ESTAT_ADD(tx_late_collisions);
11798 ESTAT_ADD(tx_collide_2times);
11799 ESTAT_ADD(tx_collide_3times);
11800 ESTAT_ADD(tx_collide_4times);
11801 ESTAT_ADD(tx_collide_5times);
11802 ESTAT_ADD(tx_collide_6times);
11803 ESTAT_ADD(tx_collide_7times);
11804 ESTAT_ADD(tx_collide_8times);
11805 ESTAT_ADD(tx_collide_9times);
11806 ESTAT_ADD(tx_collide_10times);
11807 ESTAT_ADD(tx_collide_11times);
11808 ESTAT_ADD(tx_collide_12times);
11809 ESTAT_ADD(tx_collide_13times);
11810 ESTAT_ADD(tx_collide_14times);
11811 ESTAT_ADD(tx_collide_15times);
11812 ESTAT_ADD(tx_ucast_packets);
11813 ESTAT_ADD(tx_mcast_packets);
11814 ESTAT_ADD(tx_bcast_packets);
11815 ESTAT_ADD(tx_carrier_sense_errors);
11816 ESTAT_ADD(tx_discards);
11817 ESTAT_ADD(tx_errors);
11818
11819 ESTAT_ADD(dma_writeq_full);
11820 ESTAT_ADD(dma_write_prioq_full);
11821 ESTAT_ADD(rxbds_empty);
11822 ESTAT_ADD(rx_discards);
11823 ESTAT_ADD(rx_errors);
11824 ESTAT_ADD(rx_threshold_hit);
11825
11826 ESTAT_ADD(dma_readq_full);
11827 ESTAT_ADD(dma_read_prioq_full);
11828 ESTAT_ADD(tx_comp_queue_full);
11829
11830 ESTAT_ADD(ring_set_send_prod_index);
11831 ESTAT_ADD(ring_status_update);
11832 ESTAT_ADD(nic_irqs);
11833 ESTAT_ADD(nic_avoided_irqs);
11834 ESTAT_ADD(nic_tx_threshold_hit);
11835
4452d099 11836 ESTAT_ADD(mbuf_lwm_thresh_hit);
1da177e4
LT		 11837}
11838
65ec698d 11839static void tg3_get_nstats(struct tg3 *tp, struct rtnl_link_stats64 *stats)
1da177e4 11840{
511d2224 11841 struct rtnl_link_stats64 *old_stats = &tp->net_stats_prev;
1da177e4
LT		 11842 struct tg3_hw_stats *hw_stats = tp->hw_stats;
11843
1da177e4
LT		 11844 stats->rx_packets = old_stats->rx_packets +
11845 get_stat64(&hw_stats->rx_ucast_packets) +
11846 get_stat64(&hw_stats->rx_mcast_packets) +
11847 get_stat64(&hw_stats->rx_bcast_packets);
6aa20a22 11848
1da177e4
LT		 11849 stats->tx_packets = old_stats->tx_packets +
11850 get_stat64(&hw_stats->tx_ucast_packets) +
11851 get_stat64(&hw_stats->tx_mcast_packets) +
11852 get_stat64(&hw_stats->tx_bcast_packets);
11853
11854 stats->rx_bytes = old_stats->rx_bytes +
11855 get_stat64(&hw_stats->rx_octets);
11856 stats->tx_bytes = old_stats->tx_bytes +
11857 get_stat64(&hw_stats->tx_octets);
11858
11859 stats->rx_errors = old_stats->rx_errors +
4f63b877 11860 get_stat64(&hw_stats->rx_errors);
1da177e4
LT		 11861 stats->tx_errors = old_stats->tx_errors +
11862 get_stat64(&hw_stats->tx_errors) +
11863 get_stat64(&hw_stats->tx_mac_errors) +
11864 get_stat64(&hw_stats->tx_carrier_sense_errors) +
11865 get_stat64(&hw_stats->tx_discards);
11866
11867 stats->multicast = old_stats->multicast +
11868 get_stat64(&hw_stats->rx_mcast_packets);
11869 stats->collisions = old_stats->collisions +
11870 get_stat64(&hw_stats->tx_collisions);
11871
11872 stats->rx_length_errors = old_stats->rx_length_errors +
11873 get_stat64(&hw_stats->rx_frame_too_long_errors) +
11874 get_stat64(&hw_stats->rx_undersize_packets);
11875
1da177e4
LT		 11876 stats->rx_frame_errors = old_stats->rx_frame_errors +
11877 get_stat64(&hw_stats->rx_align_errors);
11878 stats->tx_aborted_errors = old_stats->tx_aborted_errors +
11879 get_stat64(&hw_stats->tx_discards);
11880 stats->tx_carrier_errors = old_stats->tx_carrier_errors +
11881 get_stat64(&hw_stats->tx_carrier_sense_errors);
11882
11883 stats->rx_crc_errors = old_stats->rx_crc_errors +
65ec698d 11884 tg3_calc_crc_errors(tp);
1da177e4 11885
4f63b877
JL		 11886 stats->rx_missed_errors = old_stats->rx_missed_errors +
11887 get_stat64(&hw_stats->rx_discards);
11888
b0057c51 11889 stats->rx_dropped = tp->rx_dropped;
48855432 11890 stats->tx_dropped = tp->tx_dropped;
1da177e4
LT		 11891}
11892
1da177e4
LT		 11893static int tg3_get_regs_len(struct net_device *dev)
11894{
97bd8e49 11895 return TG3_REG_BLK_SIZE;
1da177e4
LT		 11896}
11897
11898static void tg3_get_regs(struct net_device *dev,
11899 struct ethtool_regs *regs, void *_p)
11900{
1da177e4 11901 struct tg3 *tp = netdev_priv(dev);
1da177e4
LT		 11902
11903 regs->version = 0;
11904
97bd8e49 11905 memset(_p, 0, TG3_REG_BLK_SIZE);
1da177e4 11906
80096068 11907 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
bc1c7567
MC		 11908 return;
11909
f47c11ee 11910 tg3_full_lock(tp, 0);
1da177e4 11911
97bd8e49 11912 tg3_dump_legacy_regs(tp, (u32 *)_p);
1da177e4 11913
f47c11ee 11914 tg3_full_unlock(tp);
1da177e4
LT		 11915}
11916
11917static int tg3_get_eeprom_len(struct net_device *dev)
11918{
11919 struct tg3 *tp = netdev_priv(dev);
11920
11921 return tp->nvram_size;
11922}
11923
1da177e4
LT		 11924static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
11925{
11926 struct tg3 *tp = netdev_priv(dev);
506724c4 11927 int ret, cpmu_restore = 0;
1da177e4 11928 u8 *pd;
506724c4 11929 u32 i, offset, len, b_offset, b_count, cpmu_val = 0;
a9dc529d 11930 __be32 val;
1da177e4 11931
63c3a66f 11932 if (tg3_flag(tp, NO_NVRAM))
df259d8c
MC		 11933 return -EINVAL;
11934
1da177e4
LT		 11935 offset = eeprom->offset;
11936 len = eeprom->len;
11937 eeprom->len = 0;
11938
11939 eeprom->magic = TG3_EEPROM_MAGIC;
11940
506724c4
PS		 11941 /* Override clock, link aware and link idle modes */
11942 if (tg3_flag(tp, CPMU_PRESENT)) {
11943 cpmu_val = tr32(TG3_CPMU_CTRL);
11944 if (cpmu_val & (CPMU_CTRL_LINK_AWARE_MODE |
11945 CPMU_CTRL_LINK_IDLE_MODE)) {
11946 tw32(TG3_CPMU_CTRL, cpmu_val &
11947 ~(CPMU_CTRL_LINK_AWARE_MODE |
11948 CPMU_CTRL_LINK_IDLE_MODE));
11949 cpmu_restore = 1;
11950 }
11951 }
11952 tg3_override_clk(tp);
11953
1da177e4
LT		 11954 if (offset & 3) {
11955 /* adjustments to start on required 4 byte boundary */
11956 b_offset = offset & 3;
11957 b_count = 4 - b_offset;
11958 if (b_count > len) {
11959 /* i.e. offset=1 len=2 */
11960 b_count = len;
11961 }
a9dc529d 11962 ret = tg3_nvram_read_be32(tp, offset-b_offset, &val);
1da177e4 11963 if (ret)
506724c4 11964 goto eeprom_done;
be98da6a 11965 memcpy(data, ((char *)&val) + b_offset, b_count);
1da177e4
LT		 11966 len -= b_count;
11967 offset += b_count;
c6cdf436 11968 eeprom->len += b_count;
1da177e4
LT		 11969 }
11970
25985edc 11971 /* read bytes up to the last 4 byte boundary */
1da177e4
LT		 11972 pd = &data[eeprom->len];
11973 for (i = 0; i < (len - (len & 3)); i += 4) {
a9dc529d 11974 ret = tg3_nvram_read_be32(tp, offset + i, &val);
1da177e4 11975 if (ret) {
506724c4
PS		 11976 if (i)
11977 i -= 4;
1da177e4 11978 eeprom->len += i;
506724c4 11979 goto eeprom_done;
1da177e4 11980 }
1da177e4 11981 memcpy(pd + i, &val, 4);
506724c4
PS		 11982 if (need_resched()) {
11983 if (signal_pending(current)) {
11984 eeprom->len += i;
11985 ret = -EINTR;
11986 goto eeprom_done;
11987 }
11988 cond_resched();
11989 }
1da177e4
LT		 11990 }
11991 eeprom->len += i;
11992
11993 if (len & 3) {
11994 /* read last bytes not ending on 4 byte boundary */
11995 pd = &data[eeprom->len];
11996 b_count = len & 3;
11997 b_offset = offset + len - b_count;
a9dc529d 11998 ret = tg3_nvram_read_be32(tp, b_offset, &val);
1da177e4 11999 if (ret)
506724c4 12000 goto eeprom_done;
b9fc7dc5 12001 memcpy(pd, &val, b_count);
1da177e4
LT		 12002 eeprom->len += b_count;
12003 }
506724c4
PS		 12004 ret = 0;
12005
12006eeprom_done:
12007 /* Restore clock, link aware and link idle modes */
12008 tg3_restore_clk(tp);
12009 if (cpmu_restore)
12010 tw32(TG3_CPMU_CTRL, cpmu_val);
12011
12012 return ret;
1da177e4
LT		 12013}
12014
1da177e4
LT		 12015static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
12016{
12017 struct tg3 *tp = netdev_priv(dev);
12018 int ret;
b9fc7dc5 12019 u32 offset, len, b_offset, odd_len;
1da177e4 12020 u8 *buf;
a9dc529d 12021 __be32 start, end;
1da177e4 12022
63c3a66f 12023 if (tg3_flag(tp, NO_NVRAM) ||
df259d8c 12024 eeprom->magic != TG3_EEPROM_MAGIC)
1da177e4
LT		 12025 return -EINVAL;
12026
12027 offset = eeprom->offset;
12028 len = eeprom->len;
12029
12030 if ((b_offset = (offset & 3))) {
12031 /* adjustments to start on required 4 byte boundary */
a9dc529d 12032 ret = tg3_nvram_read_be32(tp, offset-b_offset, &start);
1da177e4
LT		 12033 if (ret)
12034 return ret;
1da177e4
LT		 12035 len += b_offset;
12036 offset &= ~3;
1c8594b4
MC		 12037 if (len < 4)
12038 len = 4;
1da177e4
LT		 12039 }
12040
12041 odd_len = 0;
1c8594b4 12042 if (len & 3) {
1da177e4
LT		 12043 /* adjustments to end on required 4 byte boundary */
12044 odd_len = 1;
12045 len = (len + 3) & ~3;
a9dc529d 12046 ret = tg3_nvram_read_be32(tp, offset+len-4, &end);
1da177e4
LT		 12047 if (ret)
12048 return ret;
1da177e4
LT		 12049 }
12050
12051 buf = data;
12052 if (b_offset || odd_len) {
12053 buf = kmalloc(len, GFP_KERNEL);
ab0049b4 12054 if (!buf)
1da177e4
LT		 12055 return -ENOMEM;
12056 if (b_offset)
12057 memcpy(buf, &start, 4);
12058 if (odd_len)
12059 memcpy(buf+len-4, &end, 4);
12060 memcpy(buf + b_offset, data, eeprom->len);
12061 }
12062
12063 ret = tg3_nvram_write_block(tp, offset, len, buf);
12064
12065 if (buf != data)
12066 kfree(buf);
12067
12068 return ret;
12069}
12070
12071static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
12072{
b02fd9e3
MC		 12073 struct tg3 *tp = netdev_priv(dev);
12074
63c3a66f 12075 if (tg3_flag(tp, USE_PHYLIB)) {
3f0e3ad7 12076 struct phy_device *phydev;
f07e9af3 12077 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
b02fd9e3 12078 return -EAGAIN;
ead2402c 12079 phydev = tp->mdio_bus->phy_map[tp->phy_addr];
3f0e3ad7 12080 return phy_ethtool_gset(phydev, cmd);
b02fd9e3 12081 }
6aa20a22 12082
1da177e4
LT		 12083 cmd->supported = (SUPPORTED_Autoneg);
12084
f07e9af3 12085 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
1da177e4
LT		 12086 cmd->supported |= (SUPPORTED_1000baseT_Half |
12087 SUPPORTED_1000baseT_Full);
12088
f07e9af3 12089 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
1da177e4
LT		 12090 cmd->supported |= (SUPPORTED_100baseT_Half |
12091 SUPPORTED_100baseT_Full |
12092 SUPPORTED_10baseT_Half |
12093 SUPPORTED_10baseT_Full |
3bebab59 12094 SUPPORTED_TP);
ef348144
KK		 12095 cmd->port = PORT_TP;
12096 } else {
1da177e4 12097 cmd->supported |= SUPPORTED_FIBRE;
ef348144
KK		 12098 cmd->port = PORT_FIBRE;
12099 }
6aa20a22 12100
1da177e4 12101 cmd->advertising = tp->link_config.advertising;
5bb09778
MC		 12102 if (tg3_flag(tp, PAUSE_AUTONEG)) {
12103 if (tp->link_config.flowctrl & FLOW_CTRL_RX) {
12104 if (tp->link_config.flowctrl & FLOW_CTRL_TX) {
12105 cmd->advertising |= ADVERTISED_Pause;
12106 } else {
12107 cmd->advertising |= ADVERTISED_Pause |
12108 ADVERTISED_Asym_Pause;
12109 }
12110 } else if (tp->link_config.flowctrl & FLOW_CTRL_TX) {
12111 cmd->advertising |= ADVERTISED_Asym_Pause;
12112 }
12113 }
f4a46d1f 12114 if (netif_running(dev) && tp->link_up) {
70739497 12115 ethtool_cmd_speed_set(cmd, tp->link_config.active_speed);
1da177e4 12116 cmd->duplex = tp->link_config.active_duplex;
859edb26 12117 cmd->lp_advertising = tp->link_config.rmt_adv;
e348c5e7
MC		 12118 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
12119 if (tp->phy_flags & TG3_PHYFLG_MDIX_STATE)
12120 cmd->eth_tp_mdix = ETH_TP_MDI_X;
12121 else
12122 cmd->eth_tp_mdix = ETH_TP_MDI;
12123 }
64c22182 12124 } else {
e740522e
MC		 12125 ethtool_cmd_speed_set(cmd, SPEED_UNKNOWN);
12126 cmd->duplex = DUPLEX_UNKNOWN;
e348c5e7 12127 cmd->eth_tp_mdix = ETH_TP_MDI_INVALID;
1da177e4 12128 }
882e9793 12129 cmd->phy_address = tp->phy_addr;
7e5856bd 12130 cmd->transceiver = XCVR_INTERNAL;
1da177e4
LT		 12131 cmd->autoneg = tp->link_config.autoneg;
12132 cmd->maxtxpkt = 0;
12133 cmd->maxrxpkt = 0;
12134 return 0;
12135}
6aa20a22 12136
1da177e4
LT		 12137static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
12138{
12139 struct tg3 *tp = netdev_priv(dev);
25db0338 12140 u32 speed = ethtool_cmd_speed(cmd);
6aa20a22 12141
63c3a66f 12142 if (tg3_flag(tp, USE_PHYLIB)) {
3f0e3ad7 12143 struct phy_device *phydev;
f07e9af3 12144 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
b02fd9e3 12145 return -EAGAIN;
ead2402c 12146 phydev = tp->mdio_bus->phy_map[tp->phy_addr];
3f0e3ad7 12147 return phy_ethtool_sset(phydev, cmd);
b02fd9e3
MC		 12148 }
12149
7e5856bd
MC		 12150 if (cmd->autoneg != AUTONEG_ENABLE &&
12151 cmd->autoneg != AUTONEG_DISABLE)
37ff238d 12152 return -EINVAL;
7e5856bd
MC		 12153
12154 if (cmd->autoneg == AUTONEG_DISABLE &&
12155 cmd->duplex != DUPLEX_FULL &&
12156 cmd->duplex != DUPLEX_HALF)
37ff238d 12157 return -EINVAL;
1da177e4 12158
7e5856bd
MC		 12159 if (cmd->autoneg == AUTONEG_ENABLE) {
12160 u32 mask = ADVERTISED_Autoneg |
12161 ADVERTISED_Pause |
12162 ADVERTISED_Asym_Pause;
12163
f07e9af3 12164 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
7e5856bd
MC		 12165 mask |= ADVERTISED_1000baseT_Half |
12166 ADVERTISED_1000baseT_Full;
12167
f07e9af3 12168 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
7e5856bd
MC		 12169 mask |= ADVERTISED_100baseT_Half |
12170 ADVERTISED_100baseT_Full |
12171 ADVERTISED_10baseT_Half |
12172 ADVERTISED_10baseT_Full |
12173 ADVERTISED_TP;
12174 else
12175 mask |= ADVERTISED_FIBRE;
12176
12177 if (cmd->advertising & ~mask)
12178 return -EINVAL;
12179
12180 mask &= (ADVERTISED_1000baseT_Half |
12181 ADVERTISED_1000baseT_Full |
12182 ADVERTISED_100baseT_Half |
12183 ADVERTISED_100baseT_Full |
12184 ADVERTISED_10baseT_Half |
12185 ADVERTISED_10baseT_Full);
12186
12187 cmd->advertising &= mask;
12188 } else {
f07e9af3 12189 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES) {
25db0338 12190 if (speed != SPEED_1000)
7e5856bd
MC		 12191 return -EINVAL;
12192
12193 if (cmd->duplex != DUPLEX_FULL)
12194 return -EINVAL;
12195 } else {
25db0338
DD		 12196 if (speed != SPEED_100 &&
12197 speed != SPEED_10)
7e5856bd
MC		 12198 return -EINVAL;
12199 }
12200 }
12201
f47c11ee 12202 tg3_full_lock(tp, 0);
1da177e4
LT		 12203
12204 tp->link_config.autoneg = cmd->autoneg;
12205 if (cmd->autoneg == AUTONEG_ENABLE) {
405d8e5c
AG		 12206 tp->link_config.advertising = (cmd->advertising |
12207 ADVERTISED_Autoneg);
e740522e
MC		 12208 tp->link_config.speed = SPEED_UNKNOWN;
12209 tp->link_config.duplex = DUPLEX_UNKNOWN;
1da177e4
LT		 12210 } else {
12211 tp->link_config.advertising = 0;
25db0338 12212 tp->link_config.speed = speed;
1da177e4 12213 tp->link_config.duplex = cmd->duplex;
b02fd9e3 12214 }
6aa20a22 12215
fdad8de4
NS		 12216 tp->phy_flags |= TG3_PHYFLG_USER_CONFIGURED;
12217
ce20f161
NS		 12218 tg3_warn_mgmt_link_flap(tp);
12219
1da177e4 12220 if (netif_running(dev))
953c96e0 12221 tg3_setup_phy(tp, true);
1da177e4 12222
f47c11ee 12223 tg3_full_unlock(tp);
6aa20a22 12224
1da177e4
LT		 12225 return 0;
12226}
6aa20a22 12227
1da177e4
LT		 12228static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
12229{
12230 struct tg3 *tp = netdev_priv(dev);
6aa20a22 12231
68aad78c
RJ		 12232 strlcpy(info->driver, DRV_MODULE_NAME, sizeof(info->driver));
12233 strlcpy(info->version, DRV_MODULE_VERSION, sizeof(info->version));
12234 strlcpy(info->fw_version, tp->fw_ver, sizeof(info->fw_version));
12235 strlcpy(info->bus_info, pci_name(tp->pdev), sizeof(info->bus_info));
1da177e4 12236}
6aa20a22 12237
1da177e4
LT		 12238static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
12239{
12240 struct tg3 *tp = netdev_priv(dev);
6aa20a22 12241
63c3a66f 12242 if (tg3_flag(tp, WOL_CAP) && device_can_wakeup(&tp->pdev->dev))
a85feb8c
GZ		 12243 wol->supported = WAKE_MAGIC;
12244 else
12245 wol->supported = 0;
1da177e4 12246 wol->wolopts = 0;
63c3a66f 12247 if (tg3_flag(tp, WOL_ENABLE) && device_can_wakeup(&tp->pdev->dev))
1da177e4
LT		 12248 wol->wolopts = WAKE_MAGIC;
12249 memset(&wol->sopass, 0, sizeof(wol->sopass));
12250}
6aa20a22 12251
1da177e4
LT		 12252static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
12253{
12254 struct tg3 *tp = netdev_priv(dev);
12dac075 12255 struct device *dp = &tp->pdev->dev;
6aa20a22 12256
1da177e4
LT		 12257 if (wol->wolopts & ~WAKE_MAGIC)
12258 return -EINVAL;
12259 if ((wol->wolopts & WAKE_MAGIC) &&
63c3a66f 12260 !(tg3_flag(tp, WOL_CAP) && device_can_wakeup(dp)))
1da177e4 12261 return -EINVAL;
6aa20a22 12262
f2dc0d18
RW		 12263 device_set_wakeup_enable(dp, wol->wolopts & WAKE_MAGIC);
12264
f2dc0d18 12265 if (device_may_wakeup(dp))
63c3a66f 12266 tg3_flag_set(tp, WOL_ENABLE);
f2dc0d18 12267 else
63c3a66f 12268 tg3_flag_clear(tp, WOL_ENABLE);
6aa20a22 12269
1da177e4
LT		 12270 return 0;
12271}
6aa20a22 12272
1da177e4
LT		 12273static u32 tg3_get_msglevel(struct net_device *dev)
12274{
12275 struct tg3 *tp = netdev_priv(dev);
12276 return tp->msg_enable;
12277}
6aa20a22 12278
1da177e4
LT		 12279static void tg3_set_msglevel(struct net_device *dev, u32 value)
12280{
12281 struct tg3 *tp = netdev_priv(dev);
12282 tp->msg_enable = value;
12283}
6aa20a22 12284
1da177e4
LT		 12285static int tg3_nway_reset(struct net_device *dev)
12286{
12287 struct tg3 *tp = netdev_priv(dev);
1da177e4 12288 int r;
6aa20a22 12289
1da177e4
LT		 12290 if (!netif_running(dev))
12291 return -EAGAIN;
12292
f07e9af3 12293 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
c94e3941
MC		 12294 return -EINVAL;
12295
ce20f161
NS		 12296 tg3_warn_mgmt_link_flap(tp);
12297
63c3a66f 12298 if (tg3_flag(tp, USE_PHYLIB)) {
f07e9af3 12299 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
b02fd9e3 12300 return -EAGAIN;
ead2402c 12301 r = phy_start_aneg(tp->mdio_bus->phy_map[tp->phy_addr]);
b02fd9e3
MC		 12302 } else {
12303 u32 bmcr;
12304
12305 spin_lock_bh(&tp->lock);
12306 r = -EINVAL;
12307 tg3_readphy(tp, MII_BMCR, &bmcr);
12308 if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
12309 ((bmcr & BMCR_ANENABLE) ||
f07e9af3 12310 (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT))) {
b02fd9e3
MC		 12311 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
12312 BMCR_ANENABLE);
12313 r = 0;
12314 }
12315 spin_unlock_bh(&tp->lock);
1da177e4 12316 }
6aa20a22 12317
1da177e4
LT		 12318 return r;
12319}
6aa20a22 12320
1da177e4
LT		 12321static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
12322{
12323 struct tg3 *tp = netdev_priv(dev);
6aa20a22 12324
2c49a44d 12325 ering->rx_max_pending = tp->rx_std_ring_mask;
63c3a66f 12326 if (tg3_flag(tp, JUMBO_RING_ENABLE))
2c49a44d 12327 ering->rx_jumbo_max_pending = tp->rx_jmb_ring_mask;
4f81c32b
MC		 12328 else
12329 ering->rx_jumbo_max_pending = 0;
12330
12331 ering->tx_max_pending = TG3_TX_RING_SIZE - 1;
1da177e4
LT		 12332
12333 ering->rx_pending = tp->rx_pending;
63c3a66f 12334 if (tg3_flag(tp, JUMBO_RING_ENABLE))
4f81c32b
MC		 12335 ering->rx_jumbo_pending = tp->rx_jumbo_pending;
12336 else
12337 ering->rx_jumbo_pending = 0;
12338
f3f3f27e 12339 ering->tx_pending = tp->napi[0].tx_pending;
1da177e4 12340}
6aa20a22 12341
1da177e4
LT		 12342static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
12343{
12344 struct tg3 *tp = netdev_priv(dev);
646c9edd 12345 int i, irq_sync = 0, err = 0;
6aa20a22 12346
2c49a44d
MC		 12347 if ((ering->rx_pending > tp->rx_std_ring_mask) ||
12348 (ering->rx_jumbo_pending > tp->rx_jmb_ring_mask) ||
bc3a9254
MC		 12349 (ering->tx_pending > TG3_TX_RING_SIZE - 1) ||
12350 (ering->tx_pending <= MAX_SKB_FRAGS) ||
63c3a66f 12351 (tg3_flag(tp, TSO_BUG) &&
bc3a9254 12352 (ering->tx_pending <= (MAX_SKB_FRAGS * 3))))
1da177e4 12353 return -EINVAL;
6aa20a22 12354
bbe832c0 12355 if (netif_running(dev)) {
b02fd9e3 12356 tg3_phy_stop(tp);
1da177e4 12357 tg3_netif_stop(tp);
bbe832c0
MC		 12358 irq_sync = 1;
12359 }
1da177e4 12360
bbe832c0 12361 tg3_full_lock(tp, irq_sync);
6aa20a22 12362
1da177e4
LT		 12363 tp->rx_pending = ering->rx_pending;
12364
63c3a66f 12365 if (tg3_flag(tp, MAX_RXPEND_64) &&
1da177e4
LT		 12366 tp->rx_pending > 63)
12367 tp->rx_pending = 63;
ba67b510
IV		 12368
12369 if (tg3_flag(tp, JUMBO_RING_ENABLE))
12370 tp->rx_jumbo_pending = ering->rx_jumbo_pending;
646c9edd 12371
6fd45cb8 12372 for (i = 0; i < tp->irq_max; i++)
646c9edd 12373 tp->napi[i].tx_pending = ering->tx_pending;
1da177e4
LT		 12374
12375 if (netif_running(dev)) {
944d980e 12376 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
953c96e0 12377 err = tg3_restart_hw(tp, false);
b9ec6c1b
MC		 12378 if (!err)
12379 tg3_netif_start(tp);
1da177e4
LT		 12380 }
12381
f47c11ee 12382 tg3_full_unlock(tp);
6aa20a22 12383
b02fd9e3
MC		 12384 if (irq_sync && !err)
12385 tg3_phy_start(tp);
12386
b9ec6c1b 12387 return err;
1da177e4 12388}
6aa20a22 12389
1da177e4
LT		 12390static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
12391{
12392 struct tg3 *tp = netdev_priv(dev);
6aa20a22 12393
63c3a66f 12394 epause->autoneg = !!tg3_flag(tp, PAUSE_AUTONEG);
8d018621 12395
4a2db503 12396 if (tp->link_config.flowctrl & FLOW_CTRL_RX)
8d018621
MC		 12397 epause->rx_pause = 1;
12398 else
12399 epause->rx_pause = 0;
12400
4a2db503 12401 if (tp->link_config.flowctrl & FLOW_CTRL_TX)
8d018621
MC		 12402 epause->tx_pause = 1;
12403 else
12404 epause->tx_pause = 0;
1da177e4 12405}
6aa20a22 12406
1da177e4
LT		 12407static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
12408{
12409 struct tg3 *tp = netdev_priv(dev);
b02fd9e3 12410 int err = 0;
6aa20a22 12411
ce20f161
NS		 12412 if (tp->link_config.autoneg == AUTONEG_ENABLE)
12413 tg3_warn_mgmt_link_flap(tp);
12414
63c3a66f 12415 if (tg3_flag(tp, USE_PHYLIB)) {
2712168f
MC		 12416 u32 newadv;
12417 struct phy_device *phydev;
1da177e4 12418
ead2402c 12419 phydev = tp->mdio_bus->phy_map[tp->phy_addr];
f47c11ee 12420
2712168f
MC		 12421 if (!(phydev->supported & SUPPORTED_Pause) ||
12422 (!(phydev->supported & SUPPORTED_Asym_Pause) &&
2259dca3 12423 (epause->rx_pause != epause->tx_pause)))
2712168f 12424 return -EINVAL;
1da177e4 12425
2712168f
MC		 12426 tp->link_config.flowctrl = 0;
12427 if (epause->rx_pause) {
12428 tp->link_config.flowctrl |= FLOW_CTRL_RX;
12429
12430 if (epause->tx_pause) {
12431 tp->link_config.flowctrl |= FLOW_CTRL_TX;
12432 newadv = ADVERTISED_Pause;
b02fd9e3 12433 } else
2712168f
MC		 12434 newadv = ADVERTISED_Pause |
12435 ADVERTISED_Asym_Pause;
12436 } else if (epause->tx_pause) {
12437 tp->link_config.flowctrl |= FLOW_CTRL_TX;
12438 newadv = ADVERTISED_Asym_Pause;
12439 } else
12440 newadv = 0;
12441
12442 if (epause->autoneg)
63c3a66f 12443 tg3_flag_set(tp, PAUSE_AUTONEG);
2712168f 12444 else
63c3a66f 12445 tg3_flag_clear(tp, PAUSE_AUTONEG);
2712168f 12446
f07e9af3 12447 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
2712168f
MC		 12448 u32 oldadv = phydev->advertising &
12449 (ADVERTISED_Pause | ADVERTISED_Asym_Pause);
12450 if (oldadv != newadv) {
12451 phydev->advertising &=
12452 ~(ADVERTISED_Pause |
12453 ADVERTISED_Asym_Pause);
12454 phydev->advertising |= newadv;
12455 if (phydev->autoneg) {
12456 /*
12457 * Always renegotiate the link to
12458 * inform our link partner of our
12459 * flow control settings, even if the
12460 * flow control is forced. Let
12461 * tg3_adjust_link() do the final
12462 * flow control setup.
12463 */
12464 return phy_start_aneg(phydev);
b02fd9e3 12465 }
b02fd9e3 12466 }
b02fd9e3 12467
2712168f 12468 if (!epause->autoneg)
b02fd9e3 12469 tg3_setup_flow_control(tp, 0, 0);
2712168f 12470 } else {
c6700ce2 12471 tp->link_config.advertising &=
2712168f
MC		 12472 ~(ADVERTISED_Pause |
12473 ADVERTISED_Asym_Pause);
c6700ce2 12474 tp->link_config.advertising |= newadv;
b02fd9e3
MC		 12475 }
12476 } else {
12477 int irq_sync = 0;
12478
12479 if (netif_running(dev)) {
12480 tg3_netif_stop(tp);
12481 irq_sync = 1;
12482 }
12483
12484 tg3_full_lock(tp, irq_sync);
12485
12486 if (epause->autoneg)
63c3a66f 12487 tg3_flag_set(tp, PAUSE_AUTONEG);
b02fd9e3 12488 else
63c3a66f 12489 tg3_flag_clear(tp, PAUSE_AUTONEG);
b02fd9e3 12490 if (epause->rx_pause)
e18ce346 12491 tp->link_config.flowctrl |= FLOW_CTRL_RX;
b02fd9e3 12492 else
e18ce346 12493 tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
b02fd9e3 12494 if (epause->tx_pause)
e18ce346 12495 tp->link_config.flowctrl |= FLOW_CTRL_TX;
b02fd9e3 12496 else
e18ce346 12497 tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
b02fd9e3
MC		 12498
12499 if (netif_running(dev)) {
12500 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
953c96e0 12501 err = tg3_restart_hw(tp, false);
b02fd9e3
MC		 12502 if (!err)
12503 tg3_netif_start(tp);
12504 }
12505
12506 tg3_full_unlock(tp);
12507 }
6aa20a22 12508
fdad8de4
NS		 12509 tp->phy_flags |= TG3_PHYFLG_USER_CONFIGURED;
12510
b9ec6c1b 12511 return err;
1da177e4 12512}
6aa20a22 12513
de6f31eb 12514static int tg3_get_sset_count(struct net_device *dev, int sset)
1da177e4 12515{
b9f2c044
JG		 12516 switch (sset) {
12517 case ETH_SS_TEST:
12518 return TG3_NUM_TEST;
12519 case ETH_SS_STATS:
12520 return TG3_NUM_STATS;
12521 default:
12522 return -EOPNOTSUPP;
12523 }
4cafd3f5
MC		 12524}
12525
90415477
MC		 12526static int tg3_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *info,
12527 u32 *rules __always_unused)
12528{
12529 struct tg3 *tp = netdev_priv(dev);
12530
12531 if (!tg3_flag(tp, SUPPORT_MSIX))
12532 return -EOPNOTSUPP;
12533
12534 switch (info->cmd) {
12535 case ETHTOOL_GRXRINGS:
12536 if (netif_running(tp->dev))
9102426a 12537 info->data = tp->rxq_cnt;
90415477
MC		 12538 else {
12539 info->data = num_online_cpus();
9102426a
MC		 12540 if (info->data > TG3_RSS_MAX_NUM_QS)
12541 info->data = TG3_RSS_MAX_NUM_QS;
90415477
MC		 12542 }
12543
12544 /* The first interrupt vector only
12545 * handles link interrupts.
12546 */
12547 info->data -= 1;
12548 return 0;
12549
12550 default:
12551 return -EOPNOTSUPP;
12552 }
12553}
12554
12555static u32 tg3_get_rxfh_indir_size(struct net_device *dev)
12556{
12557 u32 size = 0;
12558 struct tg3 *tp = netdev_priv(dev);
12559
12560 if (tg3_flag(tp, SUPPORT_MSIX))
12561 size = TG3_RSS_INDIR_TBL_SIZE;
12562
12563 return size;
12564}
12565
fe62d001 12566static int tg3_get_rxfh(struct net_device *dev, u32 *indir, u8 *key)
90415477
MC		 12567{
12568 struct tg3 *tp = netdev_priv(dev);
12569 int i;
12570
12571 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++)
12572 indir[i] = tp->rss_ind_tbl[i];
12573
12574 return 0;
12575}
12576
fe62d001 12577static int tg3_set_rxfh(struct net_device *dev, const u32 *indir, const u8 *key)
90415477
MC		 12578{
12579 struct tg3 *tp = netdev_priv(dev);
12580 size_t i;
12581
12582 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++)
12583 tp->rss_ind_tbl[i] = indir[i];
12584
12585 if (!netif_running(dev) || !tg3_flag(tp, ENABLE_RSS))
12586 return 0;
12587
12588 /* It is legal to write the indirection
12589 * table while the device is running.
12590 */
12591 tg3_full_lock(tp, 0);
12592 tg3_rss_write_indir_tbl(tp);
12593 tg3_full_unlock(tp);
12594
12595 return 0;
12596}
12597
0968169c
MC		 12598static void tg3_get_channels(struct net_device *dev,
12599 struct ethtool_channels *channel)
12600{
12601 struct tg3 *tp = netdev_priv(dev);
12602 u32 deflt_qs = netif_get_num_default_rss_queues();
12603
12604 channel->max_rx = tp->rxq_max;
12605 channel->max_tx = tp->txq_max;
12606
12607 if (netif_running(dev)) {
12608 channel->rx_count = tp->rxq_cnt;
12609 channel->tx_count = tp->txq_cnt;
12610 } else {
12611 if (tp->rxq_req)
12612 channel->rx_count = tp->rxq_req;
12613 else
12614 channel->rx_count = min(deflt_qs, tp->rxq_max);
12615
12616 if (tp->txq_req)
12617 channel->tx_count = tp->txq_req;
12618 else
12619 channel->tx_count = min(deflt_qs, tp->txq_max);
12620 }
12621}
12622
12623static int tg3_set_channels(struct net_device *dev,
12624 struct ethtool_channels *channel)
12625{
12626 struct tg3 *tp = netdev_priv(dev);
12627
12628 if (!tg3_flag(tp, SUPPORT_MSIX))
12629 return -EOPNOTSUPP;
12630
12631 if (channel->rx_count > tp->rxq_max ||
12632 channel->tx_count > tp->txq_max)
12633 return -EINVAL;
12634
12635 tp->rxq_req = channel->rx_count;
12636 tp->txq_req = channel->tx_count;
12637
12638 if (!netif_running(dev))
12639 return 0;
12640
12641 tg3_stop(tp);
12642
f4a46d1f 12643 tg3_carrier_off(tp);
0968169c 12644
be947307 12645 tg3_start(tp, true, false, false);
0968169c
MC		 12646
12647 return 0;
12648}
12649
de6f31eb 12650static void tg3_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
1da177e4
LT		 12651{
12652 switch (stringset) {
12653 case ETH_SS_STATS:
12654 memcpy(buf, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
12655 break;
4cafd3f5
MC		 12656 case ETH_SS_TEST:
12657 memcpy(buf, &ethtool_test_keys, sizeof(ethtool_test_keys));
12658 break;
1da177e4
LT		 12659 default:
12660 WARN_ON(1); /* we need a WARN() */
12661 break;
12662 }
12663}
12664
81b8709c 12665static int tg3_set_phys_id(struct net_device *dev,
12666 enum ethtool_phys_id_state state)
4009a93d
MC		 12667{
12668 struct tg3 *tp = netdev_priv(dev);
4009a93d
MC		 12669
12670 if (!netif_running(tp->dev))
12671 return -EAGAIN;
12672
81b8709c 12673 switch (state) {
12674 case ETHTOOL_ID_ACTIVE:
fce55922 12675 return 1; /* cycle on/off once per second */
4009a93d 12676
81b8709c 12677 case ETHTOOL_ID_ON:
12678 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
12679 LED_CTRL_1000MBPS_ON |
12680 LED_CTRL_100MBPS_ON |
12681 LED_CTRL_10MBPS_ON |
12682 LED_CTRL_TRAFFIC_OVERRIDE |
12683 LED_CTRL_TRAFFIC_BLINK |
12684 LED_CTRL_TRAFFIC_LED);
12685 break;
6aa20a22 12686
81b8709c 12687 case ETHTOOL_ID_OFF:
12688 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
12689 LED_CTRL_TRAFFIC_OVERRIDE);
12690 break;
4009a93d 12691
81b8709c 12692 case ETHTOOL_ID_INACTIVE:
12693 tw32(MAC_LED_CTRL, tp->led_ctrl);
12694 break;
4009a93d 12695 }
81b8709c 12696
4009a93d
MC		 12697 return 0;
12698}
12699
de6f31eb 12700static void tg3_get_ethtool_stats(struct net_device *dev,
1da177e4
LT		 12701 struct ethtool_stats *estats, u64 *tmp_stats)
12702{
12703 struct tg3 *tp = netdev_priv(dev);
0e6c9da3 12704
b546e46f
MC		 12705 if (tp->hw_stats)
12706 tg3_get_estats(tp, (struct tg3_ethtool_stats *)tmp_stats);
12707 else
12708 memset(tmp_stats, 0, sizeof(struct tg3_ethtool_stats));
1da177e4
LT		 12709}
12710
535a490e 12711static __be32 *tg3_vpd_readblock(struct tg3 *tp, u32 *vpdlen)
c3e94500
MC		 12712{
12713 int i;
12714 __be32 *buf;
12715 u32 offset = 0, len = 0;
12716 u32 magic, val;
12717
63c3a66f 12718 if (tg3_flag(tp, NO_NVRAM) || tg3_nvram_read(tp, 0, &magic))
c3e94500
MC		 12719 return NULL;
12720
12721 if (magic == TG3_EEPROM_MAGIC) {
12722 for (offset = TG3_NVM_DIR_START;
12723 offset < TG3_NVM_DIR_END;
12724 offset += TG3_NVM_DIRENT_SIZE) {
12725 if (tg3_nvram_read(tp, offset, &val))
12726 return NULL;
12727
12728 if ((val >> TG3_NVM_DIRTYPE_SHIFT) ==
12729 TG3_NVM_DIRTYPE_EXTVPD)
12730 break;
12731 }
12732
12733 if (offset != TG3_NVM_DIR_END) {
12734 len = (val & TG3_NVM_DIRTYPE_LENMSK) * 4;
12735 if (tg3_nvram_read(tp, offset + 4, &offset))
12736 return NULL;
12737
12738 offset = tg3_nvram_logical_addr(tp, offset);
12739 }
12740 }
12741
12742 if (!offset || !len) {
12743 offset = TG3_NVM_VPD_OFF;
12744 len = TG3_NVM_VPD_LEN;
12745 }
12746
12747 buf = kmalloc(len, GFP_KERNEL);
12748 if (buf == NULL)
12749 return NULL;
12750
12751 if (magic == TG3_EEPROM_MAGIC) {
12752 for (i = 0; i < len; i += 4) {
12753 /* The data is in little-endian format in NVRAM.
12754 * Use the big-endian read routines to preserve
12755 * the byte order as it exists in NVRAM.
12756 */
12757 if (tg3_nvram_read_be32(tp, offset + i, &buf[i/4]))
12758 goto error;
12759 }
12760 } else {
12761 u8 *ptr;
12762 ssize_t cnt;
12763 unsigned int pos = 0;
12764
12765 ptr = (u8 *)&buf[0];
12766 for (i = 0; pos < len && i < 3; i++, pos += cnt, ptr += cnt) {
12767 cnt = pci_read_vpd(tp->pdev, pos,
12768 len - pos, ptr);
12769 if (cnt == -ETIMEDOUT || cnt == -EINTR)
12770 cnt = 0;
12771 else if (cnt < 0)
12772 goto error;
12773 }
12774 if (pos != len)
12775 goto error;
12776 }
12777
535a490e
MC		 12778 *vpdlen = len;
12779
c3e94500
MC		 12780 return buf;
12781
12782error:
12783 kfree(buf);
12784 return NULL;
12785}
12786
566f86ad 12787#define NVRAM_TEST_SIZE 0x100
a5767dec
MC		 12788#define NVRAM_SELFBOOT_FORMAT1_0_SIZE 0x14
12789#define NVRAM_SELFBOOT_FORMAT1_2_SIZE 0x18
12790#define NVRAM_SELFBOOT_FORMAT1_3_SIZE 0x1c
727a6d9f
MC		 12791#define NVRAM_SELFBOOT_FORMAT1_4_SIZE 0x20
12792#define NVRAM_SELFBOOT_FORMAT1_5_SIZE 0x24
bda18faf 12793#define NVRAM_SELFBOOT_FORMAT1_6_SIZE 0x50
b16250e3
MC		 12794#define NVRAM_SELFBOOT_HW_SIZE 0x20
12795#define NVRAM_SELFBOOT_DATA_SIZE 0x1c
566f86ad
MC		 12796
12797static int tg3_test_nvram(struct tg3 *tp)
12798{
535a490e 12799 u32 csum, magic, len;
a9dc529d 12800 __be32 *buf;
ab0049b4 12801 int i, j, k, err = 0, size;
566f86ad 12802
63c3a66f 12803 if (tg3_flag(tp, NO_NVRAM))
df259d8c
MC		 12804 return 0;
12805
e4f34110 12806 if (tg3_nvram_read(tp, 0, &magic) != 0)
1b27777a
MC		 12807 return -EIO;
12808
1b27777a
MC		 12809 if (magic == TG3_EEPROM_MAGIC)
12810 size = NVRAM_TEST_SIZE;
b16250e3 12811 else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) {
a5767dec
MC		 12812 if ((magic & TG3_EEPROM_SB_FORMAT_MASK) ==
12813 TG3_EEPROM_SB_FORMAT_1) {
12814 switch (magic & TG3_EEPROM_SB_REVISION_MASK) {
12815 case TG3_EEPROM_SB_REVISION_0:
12816 size = NVRAM_SELFBOOT_FORMAT1_0_SIZE;
12817 break;
12818 case TG3_EEPROM_SB_REVISION_2:
12819 size = NVRAM_SELFBOOT_FORMAT1_2_SIZE;
12820 break;
12821 case TG3_EEPROM_SB_REVISION_3:
12822 size = NVRAM_SELFBOOT_FORMAT1_3_SIZE;
12823 break;
727a6d9f
MC		 12824 case TG3_EEPROM_SB_REVISION_4:
12825 size = NVRAM_SELFBOOT_FORMAT1_4_SIZE;
12826 break;
12827 case TG3_EEPROM_SB_REVISION_5:
12828 size = NVRAM_SELFBOOT_FORMAT1_5_SIZE;
12829 break;
12830 case TG3_EEPROM_SB_REVISION_6:
12831 size = NVRAM_SELFBOOT_FORMAT1_6_SIZE;
12832 break;
a5767dec 12833 default:
727a6d9f 12834 return -EIO;
a5767dec
MC		 12835 }
12836 } else
1b27777a 12837 return 0;
b16250e3
MC		 12838 } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
12839 size = NVRAM_SELFBOOT_HW_SIZE;
12840 else
1b27777a
MC		 12841 return -EIO;
12842
12843 buf = kmalloc(size, GFP_KERNEL);
566f86ad
MC		 12844 if (buf == NULL)
12845 return -ENOMEM;
12846
1b27777a
MC		 12847 err = -EIO;
12848 for (i = 0, j = 0; i < size; i += 4, j++) {
a9dc529d
MC		 12849 err = tg3_nvram_read_be32(tp, i, &buf[j]);
12850 if (err)
566f86ad 12851 break;
566f86ad 12852 }
1b27777a 12853 if (i < size)
566f86ad
MC		 12854 goto out;
12855
1b27777a 12856 /* Selfboot format */
a9dc529d 12857 magic = be32_to_cpu(buf[0]);
b9fc7dc5 12858 if ((magic & TG3_EEPROM_MAGIC_FW_MSK) ==
b16250e3 12859 TG3_EEPROM_MAGIC_FW) {
1b27777a
MC		 12860 u8 *buf8 = (u8 *) buf, csum8 = 0;
12861
b9fc7dc5 12862 if ((magic & TG3_EEPROM_SB_REVISION_MASK) ==
a5767dec
MC		 12863 TG3_EEPROM_SB_REVISION_2) {
12864 /* For rev 2, the csum doesn't include the MBA. */
12865 for (i = 0; i < TG3_EEPROM_SB_F1R2_MBA_OFF; i++)
12866 csum8 += buf8[i];
12867 for (i = TG3_EEPROM_SB_F1R2_MBA_OFF + 4; i < size; i++)
12868 csum8 += buf8[i];
12869 } else {
12870 for (i = 0; i < size; i++)
12871 csum8 += buf8[i];
12872 }
1b27777a 12873
ad96b485
AB		 12874 if (csum8 == 0) {
12875 err = 0;
12876 goto out;
12877 }
12878
12879 err = -EIO;
12880 goto out;
1b27777a 12881 }
566f86ad 12882
b9fc7dc5 12883 if ((magic & TG3_EEPROM_MAGIC_HW_MSK) ==
b16250e3
MC		 12884 TG3_EEPROM_MAGIC_HW) {
12885 u8 data[NVRAM_SELFBOOT_DATA_SIZE];
a9dc529d 12886 u8 parity[NVRAM_SELFBOOT_DATA_SIZE];
b16250e3 12887 u8 *buf8 = (u8 *) buf;
b16250e3
MC		 12888
12889 /* Separate the parity bits and the data bytes. */
12890 for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) {
12891 if ((i == 0) || (i == 8)) {
12892 int l;
12893 u8 msk;
12894
12895 for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1)
12896 parity[k++] = buf8[i] & msk;
12897 i++;
859a5887 12898 } else if (i == 16) {
b16250e3
MC		 12899 int l;
12900 u8 msk;
12901
12902 for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1)
12903 parity[k++] = buf8[i] & msk;
12904 i++;
12905
12906 for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1)
12907 parity[k++] = buf8[i] & msk;
12908 i++;
12909 }
12910 data[j++] = buf8[i];
12911 }
12912
12913 err = -EIO;
12914 for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) {
12915 u8 hw8 = hweight8(data[i]);
12916
12917 if ((hw8 & 0x1) && parity[i])
12918 goto out;
12919 else if (!(hw8 & 0x1) && !parity[i])
12920 goto out;
12921 }
12922 err = 0;
12923 goto out;
12924 }
12925
01c3a392
MC		 12926 err = -EIO;
12927
566f86ad
MC		 12928 /* Bootstrap checksum at offset 0x10 */
12929 csum = calc_crc((unsigned char *) buf, 0x10);
01c3a392 12930 if (csum != le32_to_cpu(buf[0x10/4]))
566f86ad
MC		 12931 goto out;
12932
12933 /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
12934 csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
01c3a392 12935 if (csum != le32_to_cpu(buf[0xfc/4]))
a9dc529d 12936 goto out;
566f86ad 12937
c3e94500
MC		 12938 kfree(buf);
12939
535a490e 12940 buf = tg3_vpd_readblock(tp, &len);
c3e94500
MC		 12941 if (!buf)
12942 return -ENOMEM;
d4894f3e 12943
535a490e 12944 i = pci_vpd_find_tag((u8 *)buf, 0, len, PCI_VPD_LRDT_RO_DATA);
d4894f3e
MC		 12945 if (i > 0) {
12946 j = pci_vpd_lrdt_size(&((u8 *)buf)[i]);
12947 if (j < 0)
12948 goto out;
12949
535a490e 12950 if (i + PCI_VPD_LRDT_TAG_SIZE + j > len)
d4894f3e
MC		 12951 goto out;
12952
12953 i += PCI_VPD_LRDT_TAG_SIZE;
12954 j = pci_vpd_find_info_keyword((u8 *)buf, i, j,
12955 PCI_VPD_RO_KEYWORD_CHKSUM);
12956 if (j > 0) {
12957 u8 csum8 = 0;
12958
12959 j += PCI_VPD_INFO_FLD_HDR_SIZE;
12960
12961 for (i = 0; i <= j; i++)
12962 csum8 += ((u8 *)buf)[i];
12963
12964 if (csum8)
12965 goto out;
12966 }
12967 }
12968
566f86ad
MC		 12969 err = 0;
12970
12971out:
12972 kfree(buf);
12973 return err;
12974}
12975
ca43007a
MC		 12976#define TG3_SERDES_TIMEOUT_SEC 2
12977#define TG3_COPPER_TIMEOUT_SEC 6
12978
12979static int tg3_test_link(struct tg3 *tp)
12980{
12981 int i, max;
12982
12983 if (!netif_running(tp->dev))
12984 return -ENODEV;
12985
f07e9af3 12986 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
ca43007a
MC		 12987 max = TG3_SERDES_TIMEOUT_SEC;
12988 else
12989 max = TG3_COPPER_TIMEOUT_SEC;
12990
12991 for (i = 0; i < max; i++) {
f4a46d1f 12992 if (tp->link_up)
ca43007a
MC		 12993 return 0;
12994
12995 if (msleep_interruptible(1000))
12996 break;
12997 }
12998
12999 return -EIO;
13000}
13001
a71116d1 13002/* Only test the commonly used registers */
30ca3e37 13003static int tg3_test_registers(struct tg3 *tp)
a71116d1 13004{
b16250e3 13005 int i, is_5705, is_5750;
a71116d1
MC		 13006 u32 offset, read_mask, write_mask, val, save_val, read_val;
13007 static struct {
13008 u16 offset;
13009 u16 flags;
13010#define TG3_FL_5705 0x1
13011#define TG3_FL_NOT_5705 0x2
13012#define TG3_FL_NOT_5788 0x4
b16250e3 13013#define TG3_FL_NOT_5750 0x8
a71116d1
MC		 13014 u32 read_mask;
13015 u32 write_mask;
13016 } reg_tbl[] = {
13017 /* MAC Control Registers */
13018 { MAC_MODE, TG3_FL_NOT_5705,
13019 0x00000000, 0x00ef6f8c },
13020 { MAC_MODE, TG3_FL_5705,
13021 0x00000000, 0x01ef6b8c },
13022 { MAC_STATUS, TG3_FL_NOT_5705,
13023 0x03800107, 0x00000000 },
13024 { MAC_STATUS, TG3_FL_5705,
13025 0x03800100, 0x00000000 },
13026 { MAC_ADDR_0_HIGH, 0x0000,
13027 0x00000000, 0x0000ffff },
13028 { MAC_ADDR_0_LOW, 0x0000,
c6cdf436 13029 0x00000000, 0xffffffff },
a71116d1
MC		 13030 { MAC_RX_MTU_SIZE, 0x0000,
13031 0x00000000, 0x0000ffff },
13032 { MAC_TX_MODE, 0x0000,
13033 0x00000000, 0x00000070 },
13034 { MAC_TX_LENGTHS, 0x0000,
13035 0x00000000, 0x00003fff },
13036 { MAC_RX_MODE, TG3_FL_NOT_5705,
13037 0x00000000, 0x000007fc },
13038 { MAC_RX_MODE, TG3_FL_5705,
13039 0x00000000, 0x000007dc },
13040 { MAC_HASH_REG_0, 0x0000,
13041 0x00000000, 0xffffffff },
13042 { MAC_HASH_REG_1, 0x0000,
13043 0x00000000, 0xffffffff },
13044 { MAC_HASH_REG_2, 0x0000,
13045 0x00000000, 0xffffffff },
13046 { MAC_HASH_REG_3, 0x0000,
13047 0x00000000, 0xffffffff },
13048
13049 /* Receive Data and Receive BD Initiator Control Registers. */
13050 { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
13051 0x00000000, 0xffffffff },
13052 { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
13053 0x00000000, 0xffffffff },
13054 { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
13055 0x00000000, 0x00000003 },
13056 { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
13057 0x00000000, 0xffffffff },
13058 { RCVDBDI_STD_BD+0, 0x0000,
13059 0x00000000, 0xffffffff },
13060 { RCVDBDI_STD_BD+4, 0x0000,
13061 0x00000000, 0xffffffff },
13062 { RCVDBDI_STD_BD+8, 0x0000,
13063 0x00000000, 0xffff0002 },
13064 { RCVDBDI_STD_BD+0xc, 0x0000,
13065 0x00000000, 0xffffffff },
6aa20a22 13066
a71116d1
MC		 13067 /* Receive BD Initiator Control Registers. */
13068 { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
13069 0x00000000, 0xffffffff },
13070 { RCVBDI_STD_THRESH, TG3_FL_5705,
13071 0x00000000, 0x000003ff },
13072 { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
13073 0x00000000, 0xffffffff },
6aa20a22 13074
a71116d1
MC		 13075 /* Host Coalescing Control Registers. */
13076 { HOSTCC_MODE, TG3_FL_NOT_5705,
13077 0x00000000, 0x00000004 },
13078 { HOSTCC_MODE, TG3_FL_5705,
13079 0x00000000, 0x000000f6 },
13080 { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
13081 0x00000000, 0xffffffff },
13082 { HOSTCC_RXCOL_TICKS, TG3_FL_5705,
13083 0x00000000, 0x000003ff },
13084 { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
13085 0x00000000, 0xffffffff },
13086 { HOSTCC_TXCOL_TICKS, TG3_FL_5705,
13087 0x00000000, 0x000003ff },
13088 { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
13089 0x00000000, 0xffffffff },
13090 { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
13091 0x00000000, 0x000000ff },
13092 { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
13093 0x00000000, 0xffffffff },
13094 { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
13095 0x00000000, 0x000000ff },
13096 { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
13097 0x00000000, 0xffffffff },
13098 { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
13099 0x00000000, 0xffffffff },
13100 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
13101 0x00000000, 0xffffffff },
13102 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
13103 0x00000000, 0x000000ff },
13104 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
13105 0x00000000, 0xffffffff },
13106 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
13107 0x00000000, 0x000000ff },
13108 { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
13109 0x00000000, 0xffffffff },
13110 { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
13111 0x00000000, 0xffffffff },
13112 { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
13113 0x00000000, 0xffffffff },
13114 { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
13115 0x00000000, 0xffffffff },
13116 { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
13117 0x00000000, 0xffffffff },
13118 { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
13119 0xffffffff, 0x00000000 },
13120 { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
13121 0xffffffff, 0x00000000 },
13122
13123 /* Buffer Manager Control Registers. */
b16250e3 13124 { BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750,
a71116d1 13125 0x00000000, 0x007fff80 },
b16250e3 13126 { BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750,
a71116d1
MC		 13127 0x00000000, 0x007fffff },
13128 { BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
13129 0x00000000, 0x0000003f },
13130 { BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
13131 0x00000000, 0x000001ff },
13132 { BUFMGR_MB_HIGH_WATER, 0x0000,
13133 0x00000000, 0x000001ff },
13134 { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
13135 0xffffffff, 0x00000000 },
13136 { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
13137 0xffffffff, 0x00000000 },
6aa20a22 13138
a71116d1
MC		 13139 /* Mailbox Registers */
13140 { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
13141 0x00000000, 0x000001ff },
13142 { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
13143 0x00000000, 0x000001ff },
13144 { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
13145 0x00000000, 0x000007ff },
13146 { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
13147 0x00000000, 0x000001ff },
13148
13149 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
13150 };
13151
b16250e3 13152 is_5705 = is_5750 = 0;
63c3a66f 13153 if (tg3_flag(tp, 5705_PLUS)) {
a71116d1 13154 is_5705 = 1;
63c3a66f 13155 if (tg3_flag(tp, 5750_PLUS))
b16250e3
MC		 13156 is_5750 = 1;
13157 }
a71116d1
MC		 13158
13159 for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
13160 if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
13161 continue;
13162
13163 if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
13164 continue;
13165
63c3a66f 13166 if (tg3_flag(tp, IS_5788) &&
a71116d1
MC		 13167 (reg_tbl[i].flags & TG3_FL_NOT_5788))
13168 continue;
13169
b16250e3
MC		 13170 if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750))
13171 continue;
13172
a71116d1
MC		 13173 offset = (u32) reg_tbl[i].offset;
13174 read_mask = reg_tbl[i].read_mask;
13175 write_mask = reg_tbl[i].write_mask;
13176
13177 /* Save the original register content */
13178 save_val = tr32(offset);
13179
13180 /* Determine the read-only value. */
13181 read_val = save_val & read_mask;
13182
13183 /* Write zero to the register, then make sure the read-only bits
13184 * are not changed and the read/write bits are all zeros.
13185 */
13186 tw32(offset, 0);
13187
13188 val = tr32(offset);
13189
13190 /* Test the read-only and read/write bits. */
13191 if (((val & read_mask) != read_val) || (val & write_mask))
13192 goto out;
13193
13194 /* Write ones to all the bits defined by RdMask and WrMask, then
13195 * make sure the read-only bits are not changed and the
13196 * read/write bits are all ones.
13197 */
13198 tw32(offset, read_mask | write_mask);
13199
13200 val = tr32(offset);
13201
13202 /* Test the read-only bits. */
13203 if ((val & read_mask) != read_val)
13204 goto out;
13205
13206 /* Test the read/write bits. */
13207 if ((val & write_mask) != write_mask)
13208 goto out;
13209
13210 tw32(offset, save_val);
13211 }
13212
13213 return 0;
13214
13215out:
9f88f29f 13216 if (netif_msg_hw(tp))
2445e461
MC		 13217 netdev_err(tp->dev,
13218 "Register test failed at offset %x\n", offset);
a71116d1
MC		 13219 tw32(offset, save_val);
13220 return -EIO;
13221}
13222
7942e1db
MC		 13223static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
13224{
f71e1309 13225 static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
7942e1db
MC		 13226 int i;
13227 u32 j;
13228
e9edda69 13229 for (i = 0; i < ARRAY_SIZE(test_pattern); i++) {
7942e1db
MC		 13230 for (j = 0; j < len; j += 4) {
13231 u32 val;
13232
13233 tg3_write_mem(tp, offset + j, test_pattern[i]);
13234 tg3_read_mem(tp, offset + j, &val);
13235 if (val != test_pattern[i])
13236 return -EIO;
13237 }
13238 }
13239 return 0;
13240}
13241
13242static int tg3_test_memory(struct tg3 *tp)
13243{
13244 static struct mem_entry {
13245 u32 offset;
13246 u32 len;
13247 } mem_tbl_570x[] = {
38690194 13248 { 0x00000000, 0x00b50},
7942e1db
MC		 13249 { 0x00002000, 0x1c000},
13250 { 0xffffffff, 0x00000}
13251 }, mem_tbl_5705[] = {
13252 { 0x00000100, 0x0000c},
13253 { 0x00000200, 0x00008},
7942e1db
MC		 13254 { 0x00004000, 0x00800},
13255 { 0x00006000, 0x01000},
13256 { 0x00008000, 0x02000},
13257 { 0x00010000, 0x0e000},
13258 { 0xffffffff, 0x00000}
79f4d13a
MC		 13259 }, mem_tbl_5755[] = {
13260 { 0x00000200, 0x00008},
13261 { 0x00004000, 0x00800},
13262 { 0x00006000, 0x00800},
13263 { 0x00008000, 0x02000},
13264 { 0x00010000, 0x0c000},
13265 { 0xffffffff, 0x00000}
b16250e3
MC		 13266 }, mem_tbl_5906[] = {
13267 { 0x00000200, 0x00008},
13268 { 0x00004000, 0x00400},
13269 { 0x00006000, 0x00400},
13270 { 0x00008000, 0x01000},
13271 { 0x00010000, 0x01000},
13272 { 0xffffffff, 0x00000}
8b5a6c42
MC		 13273 }, mem_tbl_5717[] = {
13274 { 0x00000200, 0x00008},
13275 { 0x00010000, 0x0a000},
13276 { 0x00020000, 0x13c00},
13277 { 0xffffffff, 0x00000}
13278 }, mem_tbl_57765[] = {
13279 { 0x00000200, 0x00008},
13280 { 0x00004000, 0x00800},
13281 { 0x00006000, 0x09800},
13282 { 0x00010000, 0x0a000},
13283 { 0xffffffff, 0x00000}
7942e1db
MC		 13284 };
13285 struct mem_entry *mem_tbl;
13286 int err = 0;
13287 int i;
13288
63c3a66f 13289 if (tg3_flag(tp, 5717_PLUS))
8b5a6c42 13290 mem_tbl = mem_tbl_5717;
c65a17f4 13291 else if (tg3_flag(tp, 57765_CLASS) ||
4153577a 13292 tg3_asic_rev(tp) == ASIC_REV_5762)
8b5a6c42 13293 mem_tbl = mem_tbl_57765;
63c3a66f 13294 else if (tg3_flag(tp, 5755_PLUS))
321d32a0 13295 mem_tbl = mem_tbl_5755;
4153577a 13296 else if (tg3_asic_rev(tp) == ASIC_REV_5906)
321d32a0 13297 mem_tbl = mem_tbl_5906;
63c3a66f 13298 else if (tg3_flag(tp, 5705_PLUS))
321d32a0
MC		 13299 mem_tbl = mem_tbl_5705;
13300 else
7942e1db
MC		 13301 mem_tbl = mem_tbl_570x;
13302
13303 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
be98da6a
MC		 13304 err = tg3_do_mem_test(tp, mem_tbl[i].offset, mem_tbl[i].len);
13305 if (err)
7942e1db
MC		 13306 break;
13307 }
6aa20a22 13308
7942e1db
MC		 13309 return err;
13310}
13311
bb158d69
MC		 13312#define TG3_TSO_MSS 500
13313
13314#define TG3_TSO_IP_HDR_LEN 20
13315#define TG3_TSO_TCP_HDR_LEN 20
13316#define TG3_TSO_TCP_OPT_LEN 12
13317
13318static const u8 tg3_tso_header[] = {
133190x08, 0x00,
133200x45, 0x00, 0x00, 0x00,
133210x00, 0x00, 0x40, 0x00,
133220x40, 0x06, 0x00, 0x00,
133230x0a, 0x00, 0x00, 0x01,
133240x0a, 0x00, 0x00, 0x02,
133250x0d, 0x00, 0xe0, 0x00,
133260x00, 0x00, 0x01, 0x00,
133270x00, 0x00, 0x02, 0x00,
133280x80, 0x10, 0x10, 0x00,
133290x14, 0x09, 0x00, 0x00,
133300x01, 0x01, 0x08, 0x0a,
133310x11, 0x11, 0x11, 0x11,
133320x11, 0x11, 0x11, 0x11,
13333};
9f40dead 13334
28a45957 13335static int tg3_run_loopback(struct tg3 *tp, u32 pktsz, bool tso_loopback)
c76949a6 13336{
5e5a7f37 13337 u32 rx_start_idx, rx_idx, tx_idx, opaque_key;
bb158d69 13338 u32 base_flags = 0, mss = 0, desc_idx, coal_now, data_off, val;
84b67b27 13339 u32 budget;
9205fd9c
ED		 13340 struct sk_buff *skb;
13341 u8 *tx_data, *rx_data;
c76949a6
MC		 13342 dma_addr_t map;
13343 int num_pkts, tx_len, rx_len, i, err;
13344 struct tg3_rx_buffer_desc *desc;
898a56f8 13345 struct tg3_napi *tnapi, *rnapi;
8fea32b9 13346 struct tg3_rx_prodring_set *tpr = &tp->napi[0].prodring;
c76949a6 13347
c8873405
MC		 13348 tnapi = &tp->napi[0];
13349 rnapi = &tp->napi[0];
0c1d0e2b 13350 if (tp->irq_cnt > 1) {
63c3a66f 13351 if (tg3_flag(tp, ENABLE_RSS))
1da85aa3 13352 rnapi = &tp->napi[1];
63c3a66f 13353 if (tg3_flag(tp, ENABLE_TSS))
c8873405 13354 tnapi = &tp->napi[1];
0c1d0e2b 13355 }
fd2ce37f 13356 coal_now = tnapi->coal_now | rnapi->coal_now;
898a56f8 13357
c76949a6
MC		 13358 err = -EIO;
13359
4852a861 13360 tx_len = pktsz;
a20e9c62 13361 skb = netdev_alloc_skb(tp->dev, tx_len);
a50bb7b9
JJ		 13362 if (!skb)
13363 return -ENOMEM;
13364
c76949a6 13365 tx_data = skb_put(skb, tx_len);
d458cdf7
JP		 13366 memcpy(tx_data, tp->dev->dev_addr, ETH_ALEN);
13367 memset(tx_data + ETH_ALEN, 0x0, 8);
c76949a6 13368
4852a861 13369 tw32(MAC_RX_MTU_SIZE, tx_len + ETH_FCS_LEN);
c76949a6 13370
28a45957 13371 if (tso_loopback) {
bb158d69
MC		 13372 struct iphdr *iph = (struct iphdr *)&tx_data[ETH_HLEN];
13373
13374 u32 hdr_len = TG3_TSO_IP_HDR_LEN + TG3_TSO_TCP_HDR_LEN +
13375 TG3_TSO_TCP_OPT_LEN;
13376
13377 memcpy(tx_data + ETH_ALEN * 2, tg3_tso_header,
13378 sizeof(tg3_tso_header));
13379 mss = TG3_TSO_MSS;
13380
13381 val = tx_len - ETH_ALEN * 2 - sizeof(tg3_tso_header);
13382 num_pkts = DIV_ROUND_UP(val, TG3_TSO_MSS);
13383
13384 /* Set the total length field in the IP header */
13385 iph->tot_len = htons((u16)(mss + hdr_len));
13386
13387 base_flags = (TXD_FLAG_CPU_PRE_DMA |
13388 TXD_FLAG_CPU_POST_DMA);
13389
63c3a66f
JP		 13390 if (tg3_flag(tp, HW_TSO_1) ||
13391 tg3_flag(tp, HW_TSO_2) ||
13392 tg3_flag(tp, HW_TSO_3)) {
bb158d69
MC		 13393 struct tcphdr *th;
13394 val = ETH_HLEN + TG3_TSO_IP_HDR_LEN;
13395 th = (struct tcphdr *)&tx_data[val];
13396 th->check = 0;
13397 } else
13398 base_flags |= TXD_FLAG_TCPUDP_CSUM;
13399
63c3a66f 13400 if (tg3_flag(tp, HW_TSO_3)) {
bb158d69
MC		 13401 mss |= (hdr_len & 0xc) << 12;
13402 if (hdr_len & 0x10)
13403 base_flags |= 0x00000010;
13404 base_flags |= (hdr_len & 0x3e0) << 5;
63c3a66f 13405 } else if (tg3_flag(tp, HW_TSO_2))
bb158d69 13406 mss |= hdr_len << 9;
63c3a66f 13407 else if (tg3_flag(tp, HW_TSO_1) ||
4153577a 13408 tg3_asic_rev(tp) == ASIC_REV_5705) {
bb158d69
MC		 13409 mss |= (TG3_TSO_TCP_OPT_LEN << 9);
13410 } else {
13411 base_flags |= (TG3_TSO_TCP_OPT_LEN << 10);
13412 }
13413
13414 data_off = ETH_ALEN * 2 + sizeof(tg3_tso_header);
13415 } else {
13416 num_pkts = 1;
13417 data_off = ETH_HLEN;
c441b456
MC		 13418
13419 if (tg3_flag(tp, USE_JUMBO_BDFLAG) &&
13420 tx_len > VLAN_ETH_FRAME_LEN)
13421 base_flags |= TXD_FLAG_JMB_PKT;
bb158d69
MC		 13422 }
13423
13424 for (i = data_off; i < tx_len; i++)
c76949a6
MC		 13425 tx_data[i] = (u8) (i & 0xff);
13426
f4188d8a
AD		 13427 map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE);
13428 if (pci_dma_mapping_error(tp->pdev, map)) {
a21771dd
MC		 13429 dev_kfree_skb(skb);
13430 return -EIO;
13431 }
c76949a6 13432
0d681b27
MC		 13433 val = tnapi->tx_prod;
13434 tnapi->tx_buffers[val].skb = skb;
13435 dma_unmap_addr_set(&tnapi->tx_buffers[val], mapping, map);
13436
c76949a6 13437 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
fd2ce37f 13438 rnapi->coal_now);
c76949a6
MC		 13439
13440 udelay(10);
13441
898a56f8 13442 rx_start_idx = rnapi->hw_status->idx[0].rx_producer;
c76949a6 13443
84b67b27
MC		 13444 budget = tg3_tx_avail(tnapi);
13445 if (tg3_tx_frag_set(tnapi, &val, &budget, map, tx_len,
d1a3b737
MC		 13446 base_flags | TXD_FLAG_END, mss, 0)) {
13447 tnapi->tx_buffers[val].skb = NULL;
13448 dev_kfree_skb(skb);
13449 return -EIO;
13450 }
c76949a6 13451
f3f3f27e 13452 tnapi->tx_prod++;
c76949a6 13453
6541b806
MC		 13454 /* Sync BD data before updating mailbox */
13455 wmb();
13456
f3f3f27e
MC		 13457 tw32_tx_mbox(tnapi->prodmbox, tnapi->tx_prod);
13458 tr32_mailbox(tnapi->prodmbox);
c76949a6
MC		 13459
13460 udelay(10);
13461
303fc921
MC		 13462 /* 350 usec to allow enough time on some 10/100 Mbps devices. */
13463 for (i = 0; i < 35; i++) {
c76949a6 13464 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
fd2ce37f 13465 coal_now);
c76949a6
MC		 13466
13467 udelay(10);
13468
898a56f8
MC		 13469 tx_idx = tnapi->hw_status->idx[0].tx_consumer;
13470 rx_idx = rnapi->hw_status->idx[0].rx_producer;
f3f3f27e 13471 if ((tx_idx == tnapi->tx_prod) &&
c76949a6
MC		 13472 (rx_idx == (rx_start_idx + num_pkts)))
13473 break;
13474 }
13475
ba1142e4 13476 tg3_tx_skb_unmap(tnapi, tnapi->tx_prod - 1, -1);
c76949a6
MC		 13477 dev_kfree_skb(skb);
13478
f3f3f27e 13479 if (tx_idx != tnapi->tx_prod)
c76949a6
MC		 13480 goto out;
13481
13482 if (rx_idx != rx_start_idx + num_pkts)
13483 goto out;
13484
bb158d69
MC		 13485 val = data_off;
13486 while (rx_idx != rx_start_idx) {
13487 desc = &rnapi->rx_rcb[rx_start_idx++];
13488 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
13489 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
c76949a6 13490
bb158d69
MC		 13491 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
13492 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
13493 goto out;
c76949a6 13494
bb158d69
MC		 13495 rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT)
13496 - ETH_FCS_LEN;
c76949a6 13497
28a45957 13498 if (!tso_loopback) {
bb158d69
MC		 13499 if (rx_len != tx_len)
13500 goto out;
4852a861 13501
bb158d69
MC		 13502 if (pktsz <= TG3_RX_STD_DMA_SZ - ETH_FCS_LEN) {
13503 if (opaque_key != RXD_OPAQUE_RING_STD)
13504 goto out;
13505 } else {
13506 if (opaque_key != RXD_OPAQUE_RING_JUMBO)
13507 goto out;
13508 }
13509 } else if ((desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
13510 (desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
54e0a67f 13511 >> RXD_TCPCSUM_SHIFT != 0xffff) {
4852a861 13512 goto out;
bb158d69 13513 }
4852a861 13514
bb158d69 13515 if (opaque_key == RXD_OPAQUE_RING_STD) {
9205fd9c 13516 rx_data = tpr->rx_std_buffers[desc_idx].data;
bb158d69
MC		 13517 map = dma_unmap_addr(&tpr->rx_std_buffers[desc_idx],
13518 mapping);
13519 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
9205fd9c 13520 rx_data = tpr->rx_jmb_buffers[desc_idx].data;
bb158d69
MC		 13521 map = dma_unmap_addr(&tpr->rx_jmb_buffers[desc_idx],
13522 mapping);
13523 } else
13524 goto out;
c76949a6 13525
bb158d69
MC		 13526 pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len,
13527 PCI_DMA_FROMDEVICE);
c76949a6 13528
9205fd9c 13529 rx_data += TG3_RX_OFFSET(tp);
bb158d69 13530 for (i = data_off; i < rx_len; i++, val++) {
9205fd9c 13531 if (*(rx_data + i) != (u8) (val & 0xff))
bb158d69
MC		 13532 goto out;
13533 }
c76949a6 13534 }
bb158d69 13535
c76949a6 13536 err = 0;
6aa20a22 13537
9205fd9c 13538 /* tg3_free_rings will unmap and free the rx_data */
c76949a6
MC		 13539out:
13540 return err;
13541}
13542
00c266b7
MC		 13543#define TG3_STD_LOOPBACK_FAILED 1
13544#define TG3_JMB_LOOPBACK_FAILED 2
bb158d69 13545#define TG3_TSO_LOOPBACK_FAILED 4
28a45957
MC		 13546#define TG3_LOOPBACK_FAILED \
13547 (TG3_STD_LOOPBACK_FAILED | \
13548 TG3_JMB_LOOPBACK_FAILED | \
13549 TG3_TSO_LOOPBACK_FAILED)
00c266b7 13550
941ec90f 13551static int tg3_test_loopback(struct tg3 *tp, u64 *data, bool do_extlpbk)
9f40dead 13552{
28a45957 13553 int err = -EIO;
2215e24c 13554 u32 eee_cap;
c441b456
MC		 13555 u32 jmb_pkt_sz = 9000;
13556
13557 if (tp->dma_limit)
13558 jmb_pkt_sz = tp->dma_limit - ETH_HLEN;
9f40dead 13559
ab789046
MC		 13560 eee_cap = tp->phy_flags & TG3_PHYFLG_EEE_CAP;
13561 tp->phy_flags &= ~TG3_PHYFLG_EEE_CAP;
13562
28a45957 13563 if (!netif_running(tp->dev)) {
93df8b8f
NNS		 13564 data[TG3_MAC_LOOPB_TEST] = TG3_LOOPBACK_FAILED;
13565 data[TG3_PHY_LOOPB_TEST] = TG3_LOOPBACK_FAILED;
941ec90f 13566 if (do_extlpbk)
93df8b8f 13567 data[TG3_EXT_LOOPB_TEST] = TG3_LOOPBACK_FAILED;
28a45957
MC		 13568 goto done;
13569 }
13570
953c96e0 13571 err = tg3_reset_hw(tp, true);
ab789046 13572 if (err) {
93df8b8f
NNS		 13573 data[TG3_MAC_LOOPB_TEST] = TG3_LOOPBACK_FAILED;
13574 data[TG3_PHY_LOOPB_TEST] = TG3_LOOPBACK_FAILED;
941ec90f 13575 if (do_extlpbk)
93df8b8f 13576 data[TG3_EXT_LOOPB_TEST] = TG3_LOOPBACK_FAILED;
ab789046
MC		 13577 goto done;
13578 }
9f40dead 13579
63c3a66f 13580 if (tg3_flag(tp, ENABLE_RSS)) {
4a85f098
MC		 13581 int i;
13582
13583 /* Reroute all rx packets to the 1st queue */
13584 for (i = MAC_RSS_INDIR_TBL_0;
13585 i < MAC_RSS_INDIR_TBL_0 + TG3_RSS_INDIR_TBL_SIZE; i += 4)
13586 tw32(i, 0x0);
13587 }
13588
6e01b20b
MC		 13589 /* HW errata - mac loopback fails in some cases on 5780.
13590 * Normal traffic and PHY loopback are not affected by
13591 * errata. Also, the MAC loopback test is deprecated for
13592 * all newer ASIC revisions.
13593 */
4153577a 13594 if (tg3_asic_rev(tp) != ASIC_REV_5780 &&
6e01b20b
MC		 13595 !tg3_flag(tp, CPMU_PRESENT)) {
13596 tg3_mac_loopback(tp, true);
9936bcf6 13597
28a45957 13598 if (tg3_run_loopback(tp, ETH_FRAME_LEN, false))
93df8b8f 13599 data[TG3_MAC_LOOPB_TEST] |= TG3_STD_LOOPBACK_FAILED;
6e01b20b
MC		 13600
13601 if (tg3_flag(tp, JUMBO_RING_ENABLE) &&
c441b456 13602 tg3_run_loopback(tp, jmb_pkt_sz + ETH_HLEN, false))
93df8b8f 13603 data[TG3_MAC_LOOPB_TEST] |= TG3_JMB_LOOPBACK_FAILED;
6e01b20b
MC		 13604
13605 tg3_mac_loopback(tp, false);
13606 }
4852a861 13607
f07e9af3 13608 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
63c3a66f 13609 !tg3_flag(tp, USE_PHYLIB)) {
5e5a7f37
MC		 13610 int i;
13611
941ec90f 13612 tg3_phy_lpbk_set(tp, 0, false);
5e5a7f37
MC		 13613
13614 /* Wait for link */
13615 for (i = 0; i < 100; i++) {
13616 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
13617 break;
13618 mdelay(1);
13619 }
13620
28a45957 13621 if (tg3_run_loopback(tp, ETH_FRAME_LEN, false))
93df8b8f 13622 data[TG3_PHY_LOOPB_TEST] |= TG3_STD_LOOPBACK_FAILED;
63c3a66f 13623 if (tg3_flag(tp, TSO_CAPABLE) &&
28a45957 13624 tg3_run_loopback(tp, ETH_FRAME_LEN, true))
93df8b8f 13625 data[TG3_PHY_LOOPB_TEST] |= TG3_TSO_LOOPBACK_FAILED;
63c3a66f 13626 if (tg3_flag(tp, JUMBO_RING_ENABLE) &&
c441b456 13627 tg3_run_loopback(tp, jmb_pkt_sz + ETH_HLEN, false))
93df8b8f 13628 data[TG3_PHY_LOOPB_TEST] |= TG3_JMB_LOOPBACK_FAILED;
9f40dead 13629
941ec90f
MC		 13630 if (do_extlpbk) {
13631 tg3_phy_lpbk_set(tp, 0, true);
13632
13633 /* All link indications report up, but the hardware
13634 * isn't really ready for about 20 msec. Double it
13635 * to be sure.
13636 */
13637 mdelay(40);
13638
13639 if (tg3_run_loopback(tp, ETH_FRAME_LEN, false))
93df8b8f
NNS		 13640 data[TG3_EXT_LOOPB_TEST] |=
13641 TG3_STD_LOOPBACK_FAILED;
941ec90f
MC		 13642 if (tg3_flag(tp, TSO_CAPABLE) &&
13643 tg3_run_loopback(tp, ETH_FRAME_LEN, true))
93df8b8f
NNS		 13644 data[TG3_EXT_LOOPB_TEST] |=
13645 TG3_TSO_LOOPBACK_FAILED;
941ec90f 13646 if (tg3_flag(tp, JUMBO_RING_ENABLE) &&
c441b456 13647 tg3_run_loopback(tp, jmb_pkt_sz + ETH_HLEN, false))
93df8b8f
NNS		 13648 data[TG3_EXT_LOOPB_TEST] |=
13649 TG3_JMB_LOOPBACK_FAILED;
941ec90f
MC		 13650 }
13651
5e5a7f37
MC		 13652 /* Re-enable gphy autopowerdown. */
13653 if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD)
13654 tg3_phy_toggle_apd(tp, true);
13655 }
6833c043 13656
93df8b8f
NNS		 13657 err = (data[TG3_MAC_LOOPB_TEST] | data[TG3_PHY_LOOPB_TEST] |
13658 data[TG3_EXT_LOOPB_TEST]) ? -EIO : 0;
28a45957 13659
ab789046
MC		 13660done:
13661 tp->phy_flags |= eee_cap;
13662
9f40dead
MC		 13663 return err;
13664}
13665
4cafd3f5
MC		 13666static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
13667 u64 *data)
13668{
566f86ad 13669 struct tg3 *tp = netdev_priv(dev);
941ec90f 13670 bool doextlpbk = etest->flags & ETH_TEST_FL_EXTERNAL_LB;
566f86ad 13671
2e460fc0
NS		 13672 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
13673 if (tg3_power_up(tp)) {
13674 etest->flags |= ETH_TEST_FL_FAILED;
13675 memset(data, 1, sizeof(u64) * TG3_NUM_TEST);
13676 return;
13677 }
13678 tg3_ape_driver_state_change(tp, RESET_KIND_INIT);
bed9829f 13679 }
bc1c7567 13680
566f86ad
MC		 13681 memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
13682
13683 if (tg3_test_nvram(tp) != 0) {
13684 etest->flags |= ETH_TEST_FL_FAILED;
93df8b8f 13685 data[TG3_NVRAM_TEST] = 1;
566f86ad 13686 }
941ec90f 13687 if (!doextlpbk && tg3_test_link(tp)) {
ca43007a 13688 etest->flags |= ETH_TEST_FL_FAILED;
93df8b8f 13689 data[TG3_LINK_TEST] = 1;
ca43007a 13690 }
a71116d1 13691 if (etest->flags & ETH_TEST_FL_OFFLINE) {
b02fd9e3 13692 int err, err2 = 0, irq_sync = 0;
bbe832c0
MC		 13693
13694 if (netif_running(dev)) {
b02fd9e3 13695 tg3_phy_stop(tp);
a71116d1 13696 tg3_netif_stop(tp);
bbe832c0
MC		 13697 irq_sync = 1;
13698 }
a71116d1 13699
bbe832c0 13700 tg3_full_lock(tp, irq_sync);
a71116d1 13701 tg3_halt(tp, RESET_KIND_SUSPEND, 1);
ec41c7df 13702 err = tg3_nvram_lock(tp);
a71116d1 13703 tg3_halt_cpu(tp, RX_CPU_BASE);
63c3a66f 13704 if (!tg3_flag(tp, 5705_PLUS))
a71116d1 13705 tg3_halt_cpu(tp, TX_CPU_BASE);
ec41c7df
MC		 13706 if (!err)
13707 tg3_nvram_unlock(tp);
a71116d1 13708
f07e9af3 13709 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
d9ab5ad1
MC		 13710 tg3_phy_reset(tp);
13711
a71116d1
MC		 13712 if (tg3_test_registers(tp) != 0) {
13713 etest->flags |= ETH_TEST_FL_FAILED;
93df8b8f 13714 data[TG3_REGISTER_TEST] = 1;
a71116d1 13715 }
28a45957 13716
7942e1db
MC		 13717 if (tg3_test_memory(tp) != 0) {
13718 etest->flags |= ETH_TEST_FL_FAILED;
93df8b8f 13719 data[TG3_MEMORY_TEST] = 1;
7942e1db 13720 }
28a45957 13721
941ec90f
MC		 13722 if (doextlpbk)
13723 etest->flags |= ETH_TEST_FL_EXTERNAL_LB_DONE;
13724
93df8b8f 13725 if (tg3_test_loopback(tp, data, doextlpbk))
c76949a6 13726 etest->flags |= ETH_TEST_FL_FAILED;
a71116d1 13727
f47c11ee
DM		 13728 tg3_full_unlock(tp);
13729
d4bc3927
MC		 13730 if (tg3_test_interrupt(tp) != 0) {
13731 etest->flags |= ETH_TEST_FL_FAILED;
93df8b8f 13732 data[TG3_INTERRUPT_TEST] = 1;
d4bc3927 13733 }
f47c11ee
DM		 13734
13735 tg3_full_lock(tp, 0);
d4bc3927 13736
a71116d1
MC		 13737 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
13738 if (netif_running(dev)) {
63c3a66f 13739 tg3_flag_set(tp, INIT_COMPLETE);
953c96e0 13740 err2 = tg3_restart_hw(tp, true);
b02fd9e3 13741 if (!err2)
b9ec6c1b 13742 tg3_netif_start(tp);
a71116d1 13743 }
f47c11ee
DM		 13744
13745 tg3_full_unlock(tp);
b02fd9e3
MC		 13746
13747 if (irq_sync && !err2)
13748 tg3_phy_start(tp);
a71116d1 13749 }
80096068 13750 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
5137a2ee 13751 tg3_power_down_prepare(tp);
bc1c7567 13752
4cafd3f5
MC		 13753}
13754
7260899b 13755static int tg3_hwtstamp_set(struct net_device *dev, struct ifreq *ifr)
0a633ac2
MC		 13756{
13757 struct tg3 *tp = netdev_priv(dev);
13758 struct hwtstamp_config stmpconf;
13759
13760 if (!tg3_flag(tp, PTP_CAPABLE))
7260899b 13761 return -EOPNOTSUPP;
0a633ac2
MC		 13762
13763 if (copy_from_user(&stmpconf, ifr->ifr_data, sizeof(stmpconf)))
13764 return -EFAULT;
13765
13766 if (stmpconf.flags)
13767 return -EINVAL;
13768
58b187c6
BH		 13769 if (stmpconf.tx_type != HWTSTAMP_TX_ON &&
13770 stmpconf.tx_type != HWTSTAMP_TX_OFF)
0a633ac2 13771 return -ERANGE;
0a633ac2
MC		 13772
13773 switch (stmpconf.rx_filter) {
13774 case HWTSTAMP_FILTER_NONE:
13775 tp->rxptpctl = 0;
13776 break;
13777 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
13778 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V1_EN |
13779 TG3_RX_PTP_CTL_ALL_V1_EVENTS;
13780 break;
13781 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
13782 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V1_EN |
13783 TG3_RX_PTP_CTL_SYNC_EVNT;
13784 break;
13785 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
13786 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V1_EN |
13787 TG3_RX_PTP_CTL_DELAY_REQ;
13788 break;
13789 case HWTSTAMP_FILTER_PTP_V2_EVENT:
13790 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_EN |
13791 TG3_RX_PTP_CTL_ALL_V2_EVENTS;
13792 break;
13793 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
13794 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L2_EN |
13795 TG3_RX_PTP_CTL_ALL_V2_EVENTS;
13796 break;
13797 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
13798 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L4_EN |
13799 TG3_RX_PTP_CTL_ALL_V2_EVENTS;
13800 break;
13801 case HWTSTAMP_FILTER_PTP_V2_SYNC:
13802 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_EN |
13803 TG3_RX_PTP_CTL_SYNC_EVNT;
13804 break;
13805 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
13806 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L2_EN |
13807 TG3_RX_PTP_CTL_SYNC_EVNT;
13808 break;
13809 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
13810 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L4_EN |
13811 TG3_RX_PTP_CTL_SYNC_EVNT;
13812 break;
13813 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
13814 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_EN |
13815 TG3_RX_PTP_CTL_DELAY_REQ;
13816 break;
13817 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
13818 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L2_EN |
13819 TG3_RX_PTP_CTL_DELAY_REQ;
13820 break;
13821 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
13822 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L4_EN |
13823 TG3_RX_PTP_CTL_DELAY_REQ;
13824 break;
13825 default:
13826 return -ERANGE;
13827 }
13828
13829 if (netif_running(dev) && tp->rxptpctl)
13830 tw32(TG3_RX_PTP_CTL,
13831 tp->rxptpctl | TG3_RX_PTP_CTL_HWTS_INTERLOCK);
13832
58b187c6
BH		 13833 if (stmpconf.tx_type == HWTSTAMP_TX_ON)
13834 tg3_flag_set(tp, TX_TSTAMP_EN);
13835 else
13836 tg3_flag_clear(tp, TX_TSTAMP_EN);
13837
0a633ac2
MC		 13838 return copy_to_user(ifr->ifr_data, &stmpconf, sizeof(stmpconf)) ?
13839 -EFAULT : 0;
13840}
13841
7260899b
BH		 13842static int tg3_hwtstamp_get(struct net_device *dev, struct ifreq *ifr)
13843{
13844 struct tg3 *tp = netdev_priv(dev);
13845 struct hwtstamp_config stmpconf;
13846
13847 if (!tg3_flag(tp, PTP_CAPABLE))
13848 return -EOPNOTSUPP;
13849
13850 stmpconf.flags = 0;
13851 stmpconf.tx_type = (tg3_flag(tp, TX_TSTAMP_EN) ?
13852 HWTSTAMP_TX_ON : HWTSTAMP_TX_OFF);
13853
13854 switch (tp->rxptpctl) {
13855 case 0:
13856 stmpconf.rx_filter = HWTSTAMP_FILTER_NONE;
13857 break;
13858 case TG3_RX_PTP_CTL_RX_PTP_V1_EN | TG3_RX_PTP_CTL_ALL_V1_EVENTS:
13859 stmpconf.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
13860 break;
13861 case TG3_RX_PTP_CTL_RX_PTP_V1_EN | TG3_RX_PTP_CTL_SYNC_EVNT:
13862 stmpconf.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_SYNC;
13863 break;
13864 case TG3_RX_PTP_CTL_RX_PTP_V1_EN | TG3_RX_PTP_CTL_DELAY_REQ:
13865 stmpconf.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ;
13866 break;
13867 case TG3_RX_PTP_CTL_RX_PTP_V2_EN | TG3_RX_PTP_CTL_ALL_V2_EVENTS:
13868 stmpconf.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
13869 break;
13870 case TG3_RX_PTP_CTL_RX_PTP_V2_L2_EN | TG3_RX_PTP_CTL_ALL_V2_EVENTS:
13871 stmpconf.rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_EVENT;
13872 break;
13873 case TG3_RX_PTP_CTL_RX_PTP_V2_L4_EN | TG3_RX_PTP_CTL_ALL_V2_EVENTS:
13874 stmpconf.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT;
13875 break;
13876 case TG3_RX_PTP_CTL_RX_PTP_V2_EN | TG3_RX_PTP_CTL_SYNC_EVNT:
13877 stmpconf.rx_filter = HWTSTAMP_FILTER_PTP_V2_SYNC;
13878 break;
13879 case TG3_RX_PTP_CTL_RX_PTP_V2_L2_EN | TG3_RX_PTP_CTL_SYNC_EVNT:
13880 stmpconf.rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_SYNC;
13881 break;
13882 case TG3_RX_PTP_CTL_RX_PTP_V2_L4_EN | TG3_RX_PTP_CTL_SYNC_EVNT:
13883 stmpconf.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_SYNC;
13884 break;
13885 case TG3_RX_PTP_CTL_RX_PTP_V2_EN | TG3_RX_PTP_CTL_DELAY_REQ:
13886 stmpconf.rx_filter = HWTSTAMP_FILTER_PTP_V2_DELAY_REQ;
13887 break;
13888 case TG3_RX_PTP_CTL_RX_PTP_V2_L2_EN | TG3_RX_PTP_CTL_DELAY_REQ:
13889 stmpconf.rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ;
13890 break;
13891 case TG3_RX_PTP_CTL_RX_PTP_V2_L4_EN | TG3_RX_PTP_CTL_DELAY_REQ:
13892 stmpconf.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ;
13893 break;
13894 default:
13895 WARN_ON_ONCE(1);
13896 return -ERANGE;
13897 }
13898
13899 return copy_to_user(ifr->ifr_data, &stmpconf, sizeof(stmpconf)) ?
13900 -EFAULT : 0;
13901}
13902
1da177e4
LT		 13903static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
13904{
13905 struct mii_ioctl_data *data = if_mii(ifr);
13906 struct tg3 *tp = netdev_priv(dev);
13907 int err;
13908
63c3a66f 13909 if (tg3_flag(tp, USE_PHYLIB)) {
3f0e3ad7 13910 struct phy_device *phydev;
f07e9af3 13911 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
b02fd9e3 13912 return -EAGAIN;
ead2402c 13913 phydev = tp->mdio_bus->phy_map[tp->phy_addr];
28b04113 13914 return phy_mii_ioctl(phydev, ifr, cmd);
b02fd9e3
MC		 13915 }
13916
33f401ae 13917 switch (cmd) {
1da177e4 13918 case SIOCGMIIPHY:
882e9793 13919 data->phy_id = tp->phy_addr;
1da177e4
LT		 13920
13921 /* fallthru */
13922 case SIOCGMIIREG: {
13923 u32 mii_regval;
13924
f07e9af3 13925 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
1da177e4
LT		 13926 break; /* We have no PHY */
13927
34eea5ac 13928 if (!netif_running(dev))
bc1c7567
MC		 13929 return -EAGAIN;
13930
f47c11ee 13931 spin_lock_bh(&tp->lock);
5c358045
HM		 13932 err = __tg3_readphy(tp, data->phy_id & 0x1f,
13933 data->reg_num & 0x1f, &mii_regval);
f47c11ee 13934 spin_unlock_bh(&tp->lock);
1da177e4
LT		 13935
13936 data->val_out = mii_regval;
13937
13938 return err;
13939 }
13940
13941 case SIOCSMIIREG:
f07e9af3 13942 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
1da177e4
LT		 13943 break; /* We have no PHY */
13944
34eea5ac 13945 if (!netif_running(dev))
bc1c7567
MC		 13946 return -EAGAIN;
13947
f47c11ee 13948 spin_lock_bh(&tp->lock);
5c358045
HM		 13949 err = __tg3_writephy(tp, data->phy_id & 0x1f,
13950 data->reg_num & 0x1f, data->val_in);
f47c11ee 13951 spin_unlock_bh(&tp->lock);
1da177e4
LT		 13952
13953 return err;
13954
0a633ac2 13955 case SIOCSHWTSTAMP:
7260899b
BH		 13956 return tg3_hwtstamp_set(dev, ifr);
13957
13958 case SIOCGHWTSTAMP:
13959 return tg3_hwtstamp_get(dev, ifr);
0a633ac2 13960
1da177e4
LT		 13961 default:
13962 /* do nothing */
13963 break;
13964 }
13965 return -EOPNOTSUPP;
13966}
13967
15f9850d
DM		 13968static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
13969{
13970 struct tg3 *tp = netdev_priv(dev);
13971
13972 memcpy(ec, &tp->coal, sizeof(*ec));
13973 return 0;
13974}
13975
d244c892
MC		 13976static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
13977{
13978 struct tg3 *tp = netdev_priv(dev);
13979 u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0;
13980 u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0;
13981
63c3a66f 13982 if (!tg3_flag(tp, 5705_PLUS)) {
d244c892
MC		 13983 max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT;
13984 max_txcoal_tick_int = MAX_TXCOAL_TICK_INT;
13985 max_stat_coal_ticks = MAX_STAT_COAL_TICKS;
13986 min_stat_coal_ticks = MIN_STAT_COAL_TICKS;
13987 }
13988
13989 if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) ||
13990 (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) ||
13991 (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) ||
13992 (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) ||
13993 (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) ||
13994 (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) ||
13995 (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) ||
13996 (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) ||
13997 (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) ||
13998 (ec->stats_block_coalesce_usecs < min_stat_coal_ticks))
13999 return -EINVAL;
14000
14001 /* No rx interrupts will be generated if both are zero */
14002 if ((ec->rx_coalesce_usecs == 0) &&
14003 (ec->rx_max_coalesced_frames == 0))
14004 return -EINVAL;
14005
14006 /* No tx interrupts will be generated if both are zero */
14007 if ((ec->tx_coalesce_usecs == 0) &&
14008 (ec->tx_max_coalesced_frames == 0))
14009 return -EINVAL;
14010
14011 /* Only copy relevant parameters, ignore all others. */
14012 tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs;
14013 tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs;
14014 tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
14015 tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames;
14016 tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;
14017 tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;
14018 tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;
14019 tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;
14020 tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs;
14021
14022 if (netif_running(dev)) {
14023 tg3_full_lock(tp, 0);
14024 __tg3_set_coalesce(tp, &tp->coal);
14025 tg3_full_unlock(tp);
14026 }
14027 return 0;
14028}
14029
1cbf9eb8
NS		 14030static int tg3_set_eee(struct net_device *dev, struct ethtool_eee *edata)
14031{
14032 struct tg3 *tp = netdev_priv(dev);
14033
14034 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP)) {
14035 netdev_warn(tp->dev, "Board does not support EEE!\n");
14036 return -EOPNOTSUPP;
14037 }
14038
14039 if (edata->advertised != tp->eee.advertised) {
14040 netdev_warn(tp->dev,
14041 "Direct manipulation of EEE advertisement is not supported\n");
14042 return -EINVAL;
14043 }
14044
14045 if (edata->tx_lpi_timer > TG3_CPMU_DBTMR1_LNKIDLE_MAX) {
14046 netdev_warn(tp->dev,
14047 "Maximal Tx Lpi timer supported is %#x(u)\n",
14048 TG3_CPMU_DBTMR1_LNKIDLE_MAX);
14049 return -EINVAL;
14050 }
14051
14052 tp->eee = *edata;
14053
14054 tp->phy_flags |= TG3_PHYFLG_USER_CONFIGURED;
14055 tg3_warn_mgmt_link_flap(tp);
14056
14057 if (netif_running(tp->dev)) {
14058 tg3_full_lock(tp, 0);
14059 tg3_setup_eee(tp);
14060 tg3_phy_reset(tp);
14061 tg3_full_unlock(tp);
14062 }
14063
14064 return 0;
14065}
14066
14067static int tg3_get_eee(struct net_device *dev, struct ethtool_eee *edata)
14068{
14069 struct tg3 *tp = netdev_priv(dev);
14070
14071 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP)) {
14072 netdev_warn(tp->dev,
14073 "Board does not support EEE!\n");
14074 return -EOPNOTSUPP;
14075 }
14076
14077 *edata = tp->eee;
14078 return 0;
14079}
14080
7282d491 14081static const struct ethtool_ops tg3_ethtool_ops = {
1da177e4
LT		 14082 .get_settings = tg3_get_settings,
14083 .set_settings = tg3_set_settings,
14084 .get_drvinfo = tg3_get_drvinfo,
14085 .get_regs_len = tg3_get_regs_len,
14086 .get_regs = tg3_get_regs,
14087 .get_wol = tg3_get_wol,
14088 .set_wol = tg3_set_wol,
14089 .get_msglevel = tg3_get_msglevel,
14090 .set_msglevel = tg3_set_msglevel,
14091 .nway_reset = tg3_nway_reset,
14092 .get_link = ethtool_op_get_link,
14093 .get_eeprom_len = tg3_get_eeprom_len,
14094 .get_eeprom = tg3_get_eeprom,
14095 .set_eeprom = tg3_set_eeprom,
14096 .get_ringparam = tg3_get_ringparam,
14097 .set_ringparam = tg3_set_ringparam,
14098 .get_pauseparam = tg3_get_pauseparam,
14099 .set_pauseparam = tg3_set_pauseparam,
4cafd3f5 14100 .self_test = tg3_self_test,
1da177e4 14101 .get_strings = tg3_get_strings,
81b8709c 14102 .set_phys_id = tg3_set_phys_id,
1da177e4 14103 .get_ethtool_stats = tg3_get_ethtool_stats,
15f9850d 14104 .get_coalesce = tg3_get_coalesce,
d244c892 14105 .set_coalesce = tg3_set_coalesce,
b9f2c044 14106 .get_sset_count = tg3_get_sset_count,
90415477
MC		 14107 .get_rxnfc = tg3_get_rxnfc,
14108 .get_rxfh_indir_size = tg3_get_rxfh_indir_size,
fe62d001
BH		 14109 .get_rxfh = tg3_get_rxfh,
14110 .set_rxfh = tg3_set_rxfh,
0968169c
MC		 14111 .get_channels = tg3_get_channels,
14112 .set_channels = tg3_set_channels,
7d41e49a 14113 .get_ts_info = tg3_get_ts_info,
1cbf9eb8
NS		 14114 .get_eee = tg3_get_eee,
14115 .set_eee = tg3_set_eee,
1da177e4
LT		 14116};
14117
b4017c53
DM		 14118static struct rtnl_link_stats64 *tg3_get_stats64(struct net_device *dev,
14119 struct rtnl_link_stats64 *stats)
14120{
14121 struct tg3 *tp = netdev_priv(dev);
14122
0f566b20
MC		 14123 spin_lock_bh(&tp->lock);
14124 if (!tp->hw_stats) {
7b31b4de 14125 *stats = tp->net_stats_prev;
0f566b20 14126 spin_unlock_bh(&tp->lock);
7b31b4de 14127 return stats;
0f566b20 14128 }
b4017c53 14129
b4017c53
DM		 14130 tg3_get_nstats(tp, stats);
14131 spin_unlock_bh(&tp->lock);
14132
14133 return stats;
14134}
14135
ccd5ba9d
MC		 14136static void tg3_set_rx_mode(struct net_device *dev)
14137{
14138 struct tg3 *tp = netdev_priv(dev);
14139
14140 if (!netif_running(dev))
14141 return;
14142
14143 tg3_full_lock(tp, 0);
14144 __tg3_set_rx_mode(dev);
14145 tg3_full_unlock(tp);
14146}
14147
faf1627a
MC		 14148static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
14149 int new_mtu)
14150{
14151 dev->mtu = new_mtu;
14152
14153 if (new_mtu > ETH_DATA_LEN) {
14154 if (tg3_flag(tp, 5780_CLASS)) {
14155 netdev_update_features(dev);
14156 tg3_flag_clear(tp, TSO_CAPABLE);
14157 } else {
14158 tg3_flag_set(tp, JUMBO_RING_ENABLE);
14159 }
14160 } else {
14161 if (tg3_flag(tp, 5780_CLASS)) {
14162 tg3_flag_set(tp, TSO_CAPABLE);
14163 netdev_update_features(dev);
14164 }
14165 tg3_flag_clear(tp, JUMBO_RING_ENABLE);
14166 }
14167}
14168
14169static int tg3_change_mtu(struct net_device *dev, int new_mtu)
14170{
14171 struct tg3 *tp = netdev_priv(dev);
953c96e0
JP		 14172 int err;
14173 bool reset_phy = false;
faf1627a
MC		 14174
14175 if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
14176 return -EINVAL;
14177
14178 if (!netif_running(dev)) {
14179 /* We'll just catch it later when the
14180 * device is up'd.
14181 */
14182 tg3_set_mtu(dev, tp, new_mtu);
14183 return 0;
14184 }
14185
14186 tg3_phy_stop(tp);
14187
14188 tg3_netif_stop(tp);
14189
c6993dfd
NS		 14190 tg3_set_mtu(dev, tp, new_mtu);
14191
faf1627a
MC		 14192 tg3_full_lock(tp, 1);
14193
14194 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
14195
2fae5e36
MC		 14196 /* Reset PHY, otherwise the read DMA engine will be in a mode that
14197 * breaks all requests to 256 bytes.
14198 */
4153577a 14199 if (tg3_asic_rev(tp) == ASIC_REV_57766)
953c96e0 14200 reset_phy = true;
2fae5e36
MC		 14201
14202 err = tg3_restart_hw(tp, reset_phy);
faf1627a
MC		 14203
14204 if (!err)
14205 tg3_netif_start(tp);
14206
14207 tg3_full_unlock(tp);
14208
14209 if (!err)
14210 tg3_phy_start(tp);
14211
14212 return err;
14213}
14214
14215static const struct net_device_ops tg3_netdev_ops = {
14216 .ndo_open = tg3_open,
14217 .ndo_stop = tg3_close,
14218 .ndo_start_xmit = tg3_start_xmit,
14219 .ndo_get_stats64 = tg3_get_stats64,
14220 .ndo_validate_addr = eth_validate_addr,
14221 .ndo_set_rx_mode = tg3_set_rx_mode,
14222 .ndo_set_mac_address = tg3_set_mac_addr,
14223 .ndo_do_ioctl = tg3_ioctl,
14224 .ndo_tx_timeout = tg3_tx_timeout,
14225 .ndo_change_mtu = tg3_change_mtu,
14226 .ndo_fix_features = tg3_fix_features,
14227 .ndo_set_features = tg3_set_features,
14228#ifdef CONFIG_NET_POLL_CONTROLLER
14229 .ndo_poll_controller = tg3_poll_controller,
14230#endif
14231};
14232
229b1ad1 14233static void tg3_get_eeprom_size(struct tg3 *tp)
1da177e4 14234{
1b27777a 14235 u32 cursize, val, magic;
1da177e4
LT		 14236
14237 tp->nvram_size = EEPROM_CHIP_SIZE;
14238
e4f34110 14239 if (tg3_nvram_read(tp, 0, &magic) != 0)
1da177e4
LT		 14240 return;
14241
b16250e3
MC		 14242 if ((magic != TG3_EEPROM_MAGIC) &&
14243 ((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) &&
14244 ((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW))
1da177e4
LT		 14245 return;
14246
14247 /*
14248 * Size the chip by reading offsets at increasing powers of two.
14249 * When we encounter our validation signature, we know the addressing
14250 * has wrapped around, and thus have our chip size.
14251 */
1b27777a 14252 cursize = 0x10;
1da177e4
LT		 14253
14254 while (cursize < tp->nvram_size) {
e4f34110 14255 if (tg3_nvram_read(tp, cursize, &val) != 0)
1da177e4
LT		 14256 return;
14257
1820180b 14258 if (val == magic)
1da177e4
LT		 14259 break;
14260
14261 cursize <<= 1;
14262 }
14263
14264 tp->nvram_size = cursize;
14265}
6aa20a22 14266
229b1ad1 14267static void tg3_get_nvram_size(struct tg3 *tp)
1da177e4
LT		 14268{
14269 u32 val;
14270
63c3a66f 14271 if (tg3_flag(tp, NO_NVRAM) || tg3_nvram_read(tp, 0, &val) != 0)
1b27777a
MC		 14272 return;
14273
14274 /* Selfboot format */
1820180b 14275 if (val != TG3_EEPROM_MAGIC) {
1b27777a
MC		 14276 tg3_get_eeprom_size(tp);
14277 return;
14278 }
14279
6d348f2c 14280 if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
1da177e4 14281 if (val != 0) {
6d348f2c
MC		 14282 /* This is confusing. We want to operate on the
14283 * 16-bit value at offset 0xf2. The tg3_nvram_read()
14284 * call will read from NVRAM and byteswap the data
14285 * according to the byteswapping settings for all
14286 * other register accesses. This ensures the data we
14287 * want will always reside in the lower 16-bits.
14288 * However, the data in NVRAM is in LE format, which
14289 * means the data from the NVRAM read will always be
14290 * opposite the endianness of the CPU. The 16-bit
14291 * byteswap then brings the data to CPU endianness.
14292 */
14293 tp->nvram_size = swab16((u16)(val & 0x0000ffff)) * 1024;
1da177e4
LT		 14294 return;
14295 }
14296 }
fd1122a2 14297 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
1da177e4
LT		 14298}
14299
229b1ad1 14300static void tg3_get_nvram_info(struct tg3 *tp)
1da177e4
LT		 14301{
14302 u32 nvcfg1;
14303
14304 nvcfg1 = tr32(NVRAM_CFG1);
14305 if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
63c3a66f 14306 tg3_flag_set(tp, FLASH);
8590a603 14307 } else {
1da177e4
LT		 14308 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
14309 tw32(NVRAM_CFG1, nvcfg1);
14310 }
14311
4153577a 14312 if (tg3_asic_rev(tp) == ASIC_REV_5750 ||
63c3a66f 14313 tg3_flag(tp, 5780_CLASS)) {
1da177e4 14314 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
8590a603
MC		 14315 case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
14316 tp->nvram_jedecnum = JEDEC_ATMEL;
14317 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
63c3a66f 14318 tg3_flag_set(tp, NVRAM_BUFFERED);
8590a603
MC		 14319 break;
14320 case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
14321 tp->nvram_jedecnum = JEDEC_ATMEL;
14322 tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
14323 break;
14324 case FLASH_VENDOR_ATMEL_EEPROM:
14325 tp->nvram_jedecnum = JEDEC_ATMEL;
14326 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
63c3a66f 14327 tg3_flag_set(tp, NVRAM_BUFFERED);
8590a603
MC		 14328 break;
14329 case FLASH_VENDOR_ST:
14330 tp->nvram_jedecnum = JEDEC_ST;
14331 tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
63c3a66f 14332 tg3_flag_set(tp, NVRAM_BUFFERED);
8590a603
MC		 14333 break;
14334 case FLASH_VENDOR_SAIFUN:
14335 tp->nvram_jedecnum = JEDEC_SAIFUN;
14336 tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
14337 break;
14338 case FLASH_VENDOR_SST_SMALL:
14339 case FLASH_VENDOR_SST_LARGE:
14340 tp->nvram_jedecnum = JEDEC_SST;
14341 tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
14342 break;
1da177e4 14343 }
8590a603 14344 } else {
1da177e4
LT		 14345 tp->nvram_jedecnum = JEDEC_ATMEL;
14346 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
63c3a66f 14347 tg3_flag_set(tp, NVRAM_BUFFERED);
1da177e4
LT		 14348 }
14349}
14350
229b1ad1 14351static void tg3_nvram_get_pagesize(struct tg3 *tp, u32 nvmcfg1)
a1b950d5
MC		 14352{
14353 switch (nvmcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
14354 case FLASH_5752PAGE_SIZE_256:
14355 tp->nvram_pagesize = 256;
14356 break;
14357 case FLASH_5752PAGE_SIZE_512:
14358 tp->nvram_pagesize = 512;
14359 break;
14360 case FLASH_5752PAGE_SIZE_1K:
14361 tp->nvram_pagesize = 1024;
14362 break;
14363 case FLASH_5752PAGE_SIZE_2K:
14364 tp->nvram_pagesize = 2048;
14365 break;
14366 case FLASH_5752PAGE_SIZE_4K:
14367 tp->nvram_pagesize = 4096;
14368 break;
14369 case FLASH_5752PAGE_SIZE_264:
14370 tp->nvram_pagesize = 264;
14371 break;
14372 case FLASH_5752PAGE_SIZE_528:
14373 tp->nvram_pagesize = 528;
14374 break;
14375 }
14376}
14377
229b1ad1 14378static void tg3_get_5752_nvram_info(struct tg3 *tp)
361b4ac2
MC		 14379{
14380 u32 nvcfg1;
14381
14382 nvcfg1 = tr32(NVRAM_CFG1);
14383
e6af301b
MC		 14384 /* NVRAM protection for TPM */
14385 if (nvcfg1 & (1 << 27))
63c3a66f 14386 tg3_flag_set(tp, PROTECTED_NVRAM);
e6af301b 14387
361b4ac2 14388 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
8590a603
MC		 14389 case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
14390 case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
14391 tp->nvram_jedecnum = JEDEC_ATMEL;
63c3a66f 14392 tg3_flag_set(tp, NVRAM_BUFFERED);
8590a603
MC		 14393 break;
14394 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
14395 tp->nvram_jedecnum = JEDEC_ATMEL;
63c3a66f
JP		 14396 tg3_flag_set(tp, NVRAM_BUFFERED);
14397 tg3_flag_set(tp, FLASH);
8590a603
MC		 14398 break;
14399 case FLASH_5752VENDOR_ST_M45PE10:
14400 case FLASH_5752VENDOR_ST_M45PE20:
14401 case FLASH_5752VENDOR_ST_M45PE40:
14402 tp->nvram_jedecnum = JEDEC_ST;
63c3a66f
JP		 14403 tg3_flag_set(tp, NVRAM_BUFFERED);
14404 tg3_flag_set(tp, FLASH);
8590a603 14405 break;
361b4ac2
MC		 14406 }
14407
63c3a66f 14408 if (tg3_flag(tp, FLASH)) {
a1b950d5 14409 tg3_nvram_get_pagesize(tp, nvcfg1);
8590a603 14410 } else {
361b4ac2
MC		 14411 /* For eeprom, set pagesize to maximum eeprom size */
14412 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
14413
14414 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
14415 tw32(NVRAM_CFG1, nvcfg1);
14416 }
14417}
14418
229b1ad1 14419static void tg3_get_5755_nvram_info(struct tg3 *tp)
d3c7b886 14420{
989a9d23 14421 u32 nvcfg1, protect = 0;
d3c7b886
MC		 14422
14423 nvcfg1 = tr32(NVRAM_CFG1);
14424
14425 /* NVRAM protection for TPM */
989a9d23 14426 if (nvcfg1 & (1 << 27)) {
63c3a66f 14427 tg3_flag_set(tp, PROTECTED_NVRAM);
989a9d23
MC		 14428 protect = 1;
14429 }
d3c7b886 14430
989a9d23
MC		 14431 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
14432 switch (nvcfg1) {
8590a603
MC		 14433 case FLASH_5755VENDOR_ATMEL_FLASH_1:
14434 case FLASH_5755VENDOR_ATMEL_FLASH_2:
14435 case FLASH_5755VENDOR_ATMEL_FLASH_3:
14436 case FLASH_5755VENDOR_ATMEL_FLASH_5:
14437 tp->nvram_jedecnum = JEDEC_ATMEL;
63c3a66f
JP		 14438 tg3_flag_set(tp, NVRAM_BUFFERED);
14439 tg3_flag_set(tp, FLASH);
8590a603
MC		 14440 tp->nvram_pagesize = 264;
14441 if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1 ||
14442 nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_5)
14443 tp->nvram_size = (protect ? 0x3e200 :
14444 TG3_NVRAM_SIZE_512KB);
14445 else if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_2)
14446 tp->nvram_size = (protect ? 0x1f200 :
14447 TG3_NVRAM_SIZE_256KB);
14448 else
14449 tp->nvram_size = (protect ? 0x1f200 :
14450 TG3_NVRAM_SIZE_128KB);
14451 break;
14452 case FLASH_5752VENDOR_ST_M45PE10:
14453 case FLASH_5752VENDOR_ST_M45PE20:
14454 case FLASH_5752VENDOR_ST_M45PE40:
14455 tp->nvram_jedecnum = JEDEC_ST;
63c3a66f
JP		 14456 tg3_flag_set(tp, NVRAM_BUFFERED);
14457 tg3_flag_set(tp, FLASH);
8590a603
MC		 14458 tp->nvram_pagesize = 256;
14459 if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE10)
14460 tp->nvram_size = (protect ?
14461 TG3_NVRAM_SIZE_64KB :
14462 TG3_NVRAM_SIZE_128KB);
14463 else if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE20)
14464 tp->nvram_size = (protect ?
14465 TG3_NVRAM_SIZE_64KB :
14466 TG3_NVRAM_SIZE_256KB);
14467 else
14468 tp->nvram_size = (protect ?
14469 TG3_NVRAM_SIZE_128KB :
14470 TG3_NVRAM_SIZE_512KB);
14471 break;
d3c7b886
MC		 14472 }
14473}
14474
229b1ad1 14475static void tg3_get_5787_nvram_info(struct tg3 *tp)
1b27777a
MC		 14476{
14477 u32 nvcfg1;
14478
14479 nvcfg1 = tr32(NVRAM_CFG1);
14480
14481 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
8590a603
MC		 14482 case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ:
14483 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
14484 case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ:
14485 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
14486 tp->nvram_jedecnum = JEDEC_ATMEL;
63c3a66f 14487 tg3_flag_set(tp, NVRAM_BUFFERED);
8590a603 14488 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
1b27777a 14489
8590a603
MC		 14490 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
14491 tw32(NVRAM_CFG1, nvcfg1);
14492 break;
14493 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
14494 case FLASH_5755VENDOR_ATMEL_FLASH_1:
14495 case FLASH_5755VENDOR_ATMEL_FLASH_2:
14496 case FLASH_5755VENDOR_ATMEL_FLASH_3:
14497 tp->nvram_jedecnum = JEDEC_ATMEL;
63c3a66f
JP		 14498 tg3_flag_set(tp, NVRAM_BUFFERED);
14499 tg3_flag_set(tp, FLASH);
8590a603
MC		 14500 tp->nvram_pagesize = 264;
14501 break;
14502 case FLASH_5752VENDOR_ST_M45PE10:
14503 case FLASH_5752VENDOR_ST_M45PE20:
14504 case FLASH_5752VENDOR_ST_M45PE40:
14505 tp->nvram_jedecnum = JEDEC_ST;
63c3a66f
JP		 14506 tg3_flag_set(tp, NVRAM_BUFFERED);
14507 tg3_flag_set(tp, FLASH);
8590a603
MC		 14508 tp->nvram_pagesize = 256;
14509 break;
1b27777a
MC		 14510 }
14511}
14512
229b1ad1 14513static void tg3_get_5761_nvram_info(struct tg3 *tp)
6b91fa02
MC		 14514{
14515 u32 nvcfg1, protect = 0;
14516
14517 nvcfg1 = tr32(NVRAM_CFG1);
14518
14519 /* NVRAM protection for TPM */
14520 if (nvcfg1 & (1 << 27)) {
63c3a66f 14521 tg3_flag_set(tp, PROTECTED_NVRAM);
6b91fa02
MC		 14522 protect = 1;
14523 }
14524
14525 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
14526 switch (nvcfg1) {
8590a603
MC		 14527 case FLASH_5761VENDOR_ATMEL_ADB021D:
14528 case FLASH_5761VENDOR_ATMEL_ADB041D:
14529 case FLASH_5761VENDOR_ATMEL_ADB081D:
14530 case FLASH_5761VENDOR_ATMEL_ADB161D:
14531 case FLASH_5761VENDOR_ATMEL_MDB021D:
14532 case FLASH_5761VENDOR_ATMEL_MDB041D:
14533 case FLASH_5761VENDOR_ATMEL_MDB081D:
14534 case FLASH_5761VENDOR_ATMEL_MDB161D:
14535 tp->nvram_jedecnum = JEDEC_ATMEL;
63c3a66f
JP		 14536 tg3_flag_set(tp, NVRAM_BUFFERED);
14537 tg3_flag_set(tp, FLASH);
14538 tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS);
8590a603
MC		 14539 tp->nvram_pagesize = 256;
14540 break;
14541 case FLASH_5761VENDOR_ST_A_M45PE20:
14542 case FLASH_5761VENDOR_ST_A_M45PE40:
14543 case FLASH_5761VENDOR_ST_A_M45PE80:
14544 case FLASH_5761VENDOR_ST_A_M45PE16:
14545 case FLASH_5761VENDOR_ST_M_M45PE20:
14546 case FLASH_5761VENDOR_ST_M_M45PE40:
14547 case FLASH_5761VENDOR_ST_M_M45PE80:
14548 case FLASH_5761VENDOR_ST_M_M45PE16:
14549 tp->nvram_jedecnum = JEDEC_ST;
63c3a66f
JP		 14550 tg3_flag_set(tp, NVRAM_BUFFERED);
14551 tg3_flag_set(tp, FLASH);
8590a603
MC		 14552 tp->nvram_pagesize = 256;
14553 break;
6b91fa02
MC		 14554 }
14555
14556 if (protect) {
14557 tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT);
14558 } else {
14559 switch (nvcfg1) {
8590a603
MC		 14560 case FLASH_5761VENDOR_ATMEL_ADB161D:
14561 case FLASH_5761VENDOR_ATMEL_MDB161D:
14562 case FLASH_5761VENDOR_ST_A_M45PE16:
14563 case FLASH_5761VENDOR_ST_M_M45PE16:
14564 tp->nvram_size = TG3_NVRAM_SIZE_2MB;
14565 break;
14566 case FLASH_5761VENDOR_ATMEL_ADB081D:
14567 case FLASH_5761VENDOR_ATMEL_MDB081D:
14568 case FLASH_5761VENDOR_ST_A_M45PE80:
14569 case FLASH_5761VENDOR_ST_M_M45PE80:
14570 tp->nvram_size = TG3_NVRAM_SIZE_1MB;
14571 break;
14572 case FLASH_5761VENDOR_ATMEL_ADB041D:
14573 case FLASH_5761VENDOR_ATMEL_MDB041D:
14574 case FLASH_5761VENDOR_ST_A_M45PE40:
14575 case FLASH_5761VENDOR_ST_M_M45PE40:
14576 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
14577 break;
14578 case FLASH_5761VENDOR_ATMEL_ADB021D:
14579 case FLASH_5761VENDOR_ATMEL_MDB021D:
14580 case FLASH_5761VENDOR_ST_A_M45PE20:
14581 case FLASH_5761VENDOR_ST_M_M45PE20:
14582 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
14583 break;
6b91fa02
MC		 14584 }
14585 }
14586}
14587
229b1ad1 14588static void tg3_get_5906_nvram_info(struct tg3 *tp)
b5d3772c
MC		 14589{
14590 tp->nvram_jedecnum = JEDEC_ATMEL;
63c3a66f 14591 tg3_flag_set(tp, NVRAM_BUFFERED);
b5d3772c
MC		 14592 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
14593}
14594
229b1ad1 14595static void tg3_get_57780_nvram_info(struct tg3 *tp)
321d32a0
MC		 14596{
14597 u32 nvcfg1;
14598
14599 nvcfg1 = tr32(NVRAM_CFG1);
14600
14601 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
14602 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
14603 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
14604 tp->nvram_jedecnum = JEDEC_ATMEL;
63c3a66f 14605 tg3_flag_set(tp, NVRAM_BUFFERED);
321d32a0
MC		 14606 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
14607
14608 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
14609 tw32(NVRAM_CFG1, nvcfg1);
14610 return;
14611 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
14612 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
14613 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
14614 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
14615 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
14616 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
14617 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
14618 tp->nvram_jedecnum = JEDEC_ATMEL;
63c3a66f
JP		 14619 tg3_flag_set(tp, NVRAM_BUFFERED);
14620 tg3_flag_set(tp, FLASH);
321d32a0
MC		 14621
14622 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
14623 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
14624 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
14625 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
14626 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
14627 break;
14628 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
14629 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
14630 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
14631 break;
14632 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
14633 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
14634 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
14635 break;
14636 }
14637 break;
14638 case FLASH_5752VENDOR_ST_M45PE10:
14639 case FLASH_5752VENDOR_ST_M45PE20:
14640 case FLASH_5752VENDOR_ST_M45PE40:
14641 tp->nvram_jedecnum = JEDEC_ST;
63c3a66f
JP		 14642 tg3_flag_set(tp, NVRAM_BUFFERED);
14643 tg3_flag_set(tp, FLASH);
321d32a0
MC		 14644
14645 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
14646 case FLASH_5752VENDOR_ST_M45PE10:
14647 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
14648 break;
14649 case FLASH_5752VENDOR_ST_M45PE20:
14650 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
14651 break;
14652 case FLASH_5752VENDOR_ST_M45PE40:
14653 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
14654 break;
14655 }
14656 break;
14657 default:
63c3a66f 14658 tg3_flag_set(tp, NO_NVRAM);
321d32a0
MC		 14659 return;
14660 }
14661
a1b950d5
MC		 14662 tg3_nvram_get_pagesize(tp, nvcfg1);
14663 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
63c3a66f 14664 tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS);
a1b950d5
MC		 14665}
14666
14667
229b1ad1 14668static void tg3_get_5717_nvram_info(struct tg3 *tp)
a1b950d5
MC		 14669{
14670 u32 nvcfg1;
14671
14672 nvcfg1 = tr32(NVRAM_CFG1);
14673
14674 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
14675 case FLASH_5717VENDOR_ATMEL_EEPROM:
14676 case FLASH_5717VENDOR_MICRO_EEPROM:
14677 tp->nvram_jedecnum = JEDEC_ATMEL;
63c3a66f 14678 tg3_flag_set(tp, NVRAM_BUFFERED);
a1b950d5
MC		 14679 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
14680
14681 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
14682 tw32(NVRAM_CFG1, nvcfg1);
14683 return;
14684 case FLASH_5717VENDOR_ATMEL_MDB011D:
14685 case FLASH_5717VENDOR_ATMEL_ADB011B:
14686 case FLASH_5717VENDOR_ATMEL_ADB011D:
14687 case FLASH_5717VENDOR_ATMEL_MDB021D:
14688 case FLASH_5717VENDOR_ATMEL_ADB021B:
14689 case FLASH_5717VENDOR_ATMEL_ADB021D:
14690 case FLASH_5717VENDOR_ATMEL_45USPT:
14691 tp->nvram_jedecnum = JEDEC_ATMEL;
63c3a66f
JP		 14692 tg3_flag_set(tp, NVRAM_BUFFERED);
14693 tg3_flag_set(tp, FLASH);
a1b950d5
MC		 14694
14695 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
14696 case FLASH_5717VENDOR_ATMEL_MDB021D:
66ee33bf
MC		 14697 /* Detect size with tg3_nvram_get_size() */
14698 break;
a1b950d5
MC		 14699 case FLASH_5717VENDOR_ATMEL_ADB021B:
14700 case FLASH_5717VENDOR_ATMEL_ADB021D:
14701 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
14702 break;
14703 default:
14704 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
14705 break;
14706 }
321d32a0 14707 break;
a1b950d5
MC		 14708 case FLASH_5717VENDOR_ST_M_M25PE10:
14709 case FLASH_5717VENDOR_ST_A_M25PE10:
14710 case FLASH_5717VENDOR_ST_M_M45PE10:
14711 case FLASH_5717VENDOR_ST_A_M45PE10:
14712 case FLASH_5717VENDOR_ST_M_M25PE20:
14713 case FLASH_5717VENDOR_ST_A_M25PE20:
14714 case FLASH_5717VENDOR_ST_M_M45PE20:
14715 case FLASH_5717VENDOR_ST_A_M45PE20:
14716 case FLASH_5717VENDOR_ST_25USPT:
14717 case FLASH_5717VENDOR_ST_45USPT:
14718 tp->nvram_jedecnum = JEDEC_ST;
63c3a66f
JP		 14719 tg3_flag_set(tp, NVRAM_BUFFERED);
14720 tg3_flag_set(tp, FLASH);
a1b950d5
MC		 14721
14722 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
14723 case FLASH_5717VENDOR_ST_M_M25PE20:
a1b950d5 14724 case FLASH_5717VENDOR_ST_M_M45PE20:
66ee33bf
MC		 14725 /* Detect size with tg3_nvram_get_size() */
14726 break;
14727 case FLASH_5717VENDOR_ST_A_M25PE20:
a1b950d5
MC		 14728 case FLASH_5717VENDOR_ST_A_M45PE20:
14729 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
14730 break;
14731 default:
14732 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
14733 break;
14734 }
321d32a0 14735 break;
a1b950d5 14736 default:
63c3a66f 14737 tg3_flag_set(tp, NO_NVRAM);
a1b950d5 14738 return;
321d32a0 14739 }
a1b950d5
MC		 14740
14741 tg3_nvram_get_pagesize(tp, nvcfg1);
14742 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
63c3a66f 14743 tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS);
321d32a0
MC		 14744}
14745
229b1ad1 14746static void tg3_get_5720_nvram_info(struct tg3 *tp)
9b91b5f1
MC		 14747{
14748 u32 nvcfg1, nvmpinstrp;
14749
14750 nvcfg1 = tr32(NVRAM_CFG1);
14751 nvmpinstrp = nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK;
14752
4153577a 14753 if (tg3_asic_rev(tp) == ASIC_REV_5762) {
c86a8560
MC		 14754 if (!(nvcfg1 & NVRAM_CFG1_5762VENDOR_MASK)) {
14755 tg3_flag_set(tp, NO_NVRAM);
14756 return;
14757 }
14758
14759 switch (nvmpinstrp) {
14760 case FLASH_5762_EEPROM_HD:
14761 nvmpinstrp = FLASH_5720_EEPROM_HD;
17e1a42f 14762 break;
c86a8560
MC		 14763 case FLASH_5762_EEPROM_LD:
14764 nvmpinstrp = FLASH_5720_EEPROM_LD;
17e1a42f 14765 break;
f6334bb8
MC		 14766 case FLASH_5720VENDOR_M_ST_M45PE20:
14767 /* This pinstrap supports multiple sizes, so force it
14768 * to read the actual size from location 0xf0.
14769 */
14770 nvmpinstrp = FLASH_5720VENDOR_ST_45USPT;
14771 break;
c86a8560
MC		 14772 }
14773 }
14774
9b91b5f1
MC		 14775 switch (nvmpinstrp) {
14776 case FLASH_5720_EEPROM_HD:
14777 case FLASH_5720_EEPROM_LD:
14778 tp->nvram_jedecnum = JEDEC_ATMEL;
63c3a66f 14779 tg3_flag_set(tp, NVRAM_BUFFERED);
9b91b5f1
MC		 14780
14781 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
14782 tw32(NVRAM_CFG1, nvcfg1);
14783 if (nvmpinstrp == FLASH_5720_EEPROM_HD)
14784 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
14785 else
14786 tp->nvram_pagesize = ATMEL_AT24C02_CHIP_SIZE;
14787 return;
14788 case FLASH_5720VENDOR_M_ATMEL_DB011D:
14789 case FLASH_5720VENDOR_A_ATMEL_DB011B:
14790 case FLASH_5720VENDOR_A_ATMEL_DB011D:
14791 case FLASH_5720VENDOR_M_ATMEL_DB021D:
14792 case FLASH_5720VENDOR_A_ATMEL_DB021B:
14793 case FLASH_5720VENDOR_A_ATMEL_DB021D:
14794 case FLASH_5720VENDOR_M_ATMEL_DB041D:
14795 case FLASH_5720VENDOR_A_ATMEL_DB041B:
14796 case FLASH_5720VENDOR_A_ATMEL_DB041D:
14797 case FLASH_5720VENDOR_M_ATMEL_DB081D:
14798 case FLASH_5720VENDOR_A_ATMEL_DB081D:
14799 case FLASH_5720VENDOR_ATMEL_45USPT:
14800 tp->nvram_jedecnum = JEDEC_ATMEL;
63c3a66f
JP		 14801 tg3_flag_set(tp, NVRAM_BUFFERED);
14802 tg3_flag_set(tp, FLASH);
9b91b5f1
MC		 14803
14804 switch (nvmpinstrp) {
14805 case FLASH_5720VENDOR_M_ATMEL_DB021D:
14806 case FLASH_5720VENDOR_A_ATMEL_DB021B:
14807 case FLASH_5720VENDOR_A_ATMEL_DB021D:
14808 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
14809 break;
14810 case FLASH_5720VENDOR_M_ATMEL_DB041D:
14811 case FLASH_5720VENDOR_A_ATMEL_DB041B:
14812 case FLASH_5720VENDOR_A_ATMEL_DB041D:
14813 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
14814 break;
14815 case FLASH_5720VENDOR_M_ATMEL_DB081D:
14816 case FLASH_5720VENDOR_A_ATMEL_DB081D:
14817 tp->nvram_size = TG3_NVRAM_SIZE_1MB;
14818 break;
14819 default:
4153577a 14820 if (tg3_asic_rev(tp) != ASIC_REV_5762)
c5d0b72e 14821 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
9b91b5f1
MC		 14822 break;
14823 }
14824 break;
14825 case FLASH_5720VENDOR_M_ST_M25PE10:
14826 case FLASH_5720VENDOR_M_ST_M45PE10:
14827 case FLASH_5720VENDOR_A_ST_M25PE10:
14828 case FLASH_5720VENDOR_A_ST_M45PE10:
14829 case FLASH_5720VENDOR_M_ST_M25PE20:
14830 case FLASH_5720VENDOR_M_ST_M45PE20:
14831 case FLASH_5720VENDOR_A_ST_M25PE20:
14832 case FLASH_5720VENDOR_A_ST_M45PE20:
14833 case FLASH_5720VENDOR_M_ST_M25PE40:
14834 case FLASH_5720VENDOR_M_ST_M45PE40:
14835 case FLASH_5720VENDOR_A_ST_M25PE40:
14836 case FLASH_5720VENDOR_A_ST_M45PE40:
14837 case FLASH_5720VENDOR_M_ST_M25PE80:
14838 case FLASH_5720VENDOR_M_ST_M45PE80:
14839 case FLASH_5720VENDOR_A_ST_M25PE80:
14840 case FLASH_5720VENDOR_A_ST_M45PE80:
14841 case FLASH_5720VENDOR_ST_25USPT:
14842 case FLASH_5720VENDOR_ST_45USPT:
14843 tp->nvram_jedecnum = JEDEC_ST;
63c3a66f
JP		 14844 tg3_flag_set(tp, NVRAM_BUFFERED);
14845 tg3_flag_set(tp, FLASH);
9b91b5f1
MC		 14846
14847 switch (nvmpinstrp) {
14848 case FLASH_5720VENDOR_M_ST_M25PE20:
14849 case FLASH_5720VENDOR_M_ST_M45PE20:
14850 case FLASH_5720VENDOR_A_ST_M25PE20:
14851 case FLASH_5720VENDOR_A_ST_M45PE20:
14852 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
14853 break;
14854 case FLASH_5720VENDOR_M_ST_M25PE40:
14855 case FLASH_5720VENDOR_M_ST_M45PE40:
14856 case FLASH_5720VENDOR_A_ST_M25PE40:
14857 case FLASH_5720VENDOR_A_ST_M45PE40:
14858 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
14859 break;
14860 case FLASH_5720VENDOR_M_ST_M25PE80:
14861 case FLASH_5720VENDOR_M_ST_M45PE80:
14862 case FLASH_5720VENDOR_A_ST_M25PE80:
14863 case FLASH_5720VENDOR_A_ST_M45PE80:
14864 tp->nvram_size = TG3_NVRAM_SIZE_1MB;
14865 break;
14866 default:
4153577a 14867 if (tg3_asic_rev(tp) != ASIC_REV_5762)
c5d0b72e 14868 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
9b91b5f1
MC		 14869 break;
14870 }
14871 break;
14872 default:
63c3a66f 14873 tg3_flag_set(tp, NO_NVRAM);
9b91b5f1
MC		 14874 return;
14875 }
14876
14877 tg3_nvram_get_pagesize(tp, nvcfg1);
14878 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
63c3a66f 14879 tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS);
c86a8560 14880
4153577a 14881 if (tg3_asic_rev(tp) == ASIC_REV_5762) {
c86a8560
MC		 14882 u32 val;
14883
14884 if (tg3_nvram_read(tp, 0, &val))
14885 return;
14886
14887 if (val != TG3_EEPROM_MAGIC &&
14888 (val & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW)
14889 tg3_flag_set(tp, NO_NVRAM);
14890 }
9b91b5f1
MC		 14891}
14892
1da177e4 14893/* Chips other than 5700/5701 use the NVRAM for fetching info. */
229b1ad1 14894static void tg3_nvram_init(struct tg3 *tp)
1da177e4 14895{
7e6c63f0
HM		 14896 if (tg3_flag(tp, IS_SSB_CORE)) {
14897 /* No NVRAM and EEPROM on the SSB Broadcom GigE core. */
14898 tg3_flag_clear(tp, NVRAM);
14899 tg3_flag_clear(tp, NVRAM_BUFFERED);
14900 tg3_flag_set(tp, NO_NVRAM);
14901 return;
14902 }
14903
1da177e4
LT		 14904 tw32_f(GRC_EEPROM_ADDR,
14905 (EEPROM_ADDR_FSM_RESET |
14906 (EEPROM_DEFAULT_CLOCK_PERIOD <<
14907 EEPROM_ADDR_CLKPERD_SHIFT)));
14908
9d57f01c 14909 msleep(1);
1da177e4
LT		 14910
14911 /* Enable seeprom accesses. */
14912 tw32_f(GRC_LOCAL_CTRL,
14913 tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
14914 udelay(100);
14915
4153577a
JP		 14916 if (tg3_asic_rev(tp) != ASIC_REV_5700 &&
14917 tg3_asic_rev(tp) != ASIC_REV_5701) {
63c3a66f 14918 tg3_flag_set(tp, NVRAM);
1da177e4 14919
ec41c7df 14920 if (tg3_nvram_lock(tp)) {
5129c3a3
MC		 14921 netdev_warn(tp->dev,
14922 "Cannot get nvram lock, %s failed\n",
05dbe005 14923 __func__);
ec41c7df
MC		 14924 return;
14925 }
e6af301b 14926 tg3_enable_nvram_access(tp);
1da177e4 14927
989a9d23
MC		 14928 tp->nvram_size = 0;
14929
4153577a 14930 if (tg3_asic_rev(tp) == ASIC_REV_5752)
361b4ac2 14931 tg3_get_5752_nvram_info(tp);
4153577a 14932 else if (tg3_asic_rev(tp) == ASIC_REV_5755)
d3c7b886 14933 tg3_get_5755_nvram_info(tp);
4153577a
JP		 14934 else if (tg3_asic_rev(tp) == ASIC_REV_5787 ||
14935 tg3_asic_rev(tp) == ASIC_REV_5784 ||
14936 tg3_asic_rev(tp) == ASIC_REV_5785)
1b27777a 14937 tg3_get_5787_nvram_info(tp);
4153577a 14938 else if (tg3_asic_rev(tp) == ASIC_REV_5761)
6b91fa02 14939 tg3_get_5761_nvram_info(tp);
4153577a 14940 else if (tg3_asic_rev(tp) == ASIC_REV_5906)
b5d3772c 14941 tg3_get_5906_nvram_info(tp);
4153577a 14942 else if (tg3_asic_rev(tp) == ASIC_REV_57780 ||
55086ad9 14943 tg3_flag(tp, 57765_CLASS))
321d32a0 14944 tg3_get_57780_nvram_info(tp);
4153577a
JP		 14945 else if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
14946 tg3_asic_rev(tp) == ASIC_REV_5719)
a1b950d5 14947 tg3_get_5717_nvram_info(tp);
4153577a
JP		 14948 else if (tg3_asic_rev(tp) == ASIC_REV_5720 ||
14949 tg3_asic_rev(tp) == ASIC_REV_5762)
9b91b5f1 14950 tg3_get_5720_nvram_info(tp);
361b4ac2
MC		 14951 else
14952 tg3_get_nvram_info(tp);
14953
989a9d23
MC		 14954 if (tp->nvram_size == 0)
14955 tg3_get_nvram_size(tp);
1da177e4 14956
e6af301b 14957 tg3_disable_nvram_access(tp);
381291b7 14958 tg3_nvram_unlock(tp);
1da177e4
LT		 14959
14960 } else {
63c3a66f
JP		 14961 tg3_flag_clear(tp, NVRAM);
14962 tg3_flag_clear(tp, NVRAM_BUFFERED);
1da177e4
LT		 14963
14964 tg3_get_eeprom_size(tp);
14965 }
14966}
14967
1da177e4
LT		 14968struct subsys_tbl_ent {
14969 u16 subsys_vendor, subsys_devid;
14970 u32 phy_id;
14971};
14972
229b1ad1 14973static struct subsys_tbl_ent subsys_id_to_phy_id[] = {
1da177e4 14974 /* Broadcom boards. */
24daf2b0 14975 { TG3PCI_SUBVENDOR_ID_BROADCOM,
79eb6904 14976 TG3PCI_SUBDEVICE_ID_BROADCOM_95700A6, TG3_PHY_ID_BCM5401 },
24daf2b0 14977 { TG3PCI_SUBVENDOR_ID_BROADCOM,
79eb6904 14978 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A5, TG3_PHY_ID_BCM5701 },
24daf2b0 14979 { TG3PCI_SUBVENDOR_ID_BROADCOM,
79eb6904 14980 TG3PCI_SUBDEVICE_ID_BROADCOM_95700T6, TG3_PHY_ID_BCM8002 },
24daf2b0
MC		 14981 { TG3PCI_SUBVENDOR_ID_BROADCOM,
14982 TG3PCI_SUBDEVICE_ID_BROADCOM_95700A9, 0 },
14983 { TG3PCI_SUBVENDOR_ID_BROADCOM,
79eb6904 14984 TG3PCI_SUBDEVICE_ID_BROADCOM_95701T1, TG3_PHY_ID_BCM5701 },
24daf2b0 14985 { TG3PCI_SUBVENDOR_ID_BROADCOM,
79eb6904 14986 TG3PCI_SUBDEVICE_ID_BROADCOM_95701T8, TG3_PHY_ID_BCM5701 },
24daf2b0
MC		 14987 { TG3PCI_SUBVENDOR_ID_BROADCOM,
14988 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A7, 0 },
14989 { TG3PCI_SUBVENDOR_ID_BROADCOM,
79eb6904 14990 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A10, TG3_PHY_ID_BCM5701 },
24daf2b0 14991 { TG3PCI_SUBVENDOR_ID_BROADCOM,
79eb6904 14992 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A12, TG3_PHY_ID_BCM5701 },
24daf2b0 14993 { TG3PCI_SUBVENDOR_ID_BROADCOM,
79eb6904 14994 TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX1, TG3_PHY_ID_BCM5703 },
24daf2b0 14995 { TG3PCI_SUBVENDOR_ID_BROADCOM,
79eb6904 14996 TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX2, TG3_PHY_ID_BCM5703 },
1da177e4
LT		 14997
14998 /* 3com boards. */
24daf2b0 14999 { TG3PCI_SUBVENDOR_ID_3COM,
79eb6904 15000 TG3PCI_SUBDEVICE_ID_3COM_3C996T, TG3_PHY_ID_BCM5401 },
24daf2b0 15001 { TG3PCI_SUBVENDOR_ID_3COM,
79eb6904 15002 TG3PCI_SUBDEVICE_ID_3COM_3C996BT, TG3_PHY_ID_BCM5701 },
24daf2b0
MC		 15003 { TG3PCI_SUBVENDOR_ID_3COM,
15004 TG3PCI_SUBDEVICE_ID_3COM_3C996SX, 0 },
15005 { TG3PCI_SUBVENDOR_ID_3COM,
79eb6904 15006 TG3PCI_SUBDEVICE_ID_3COM_3C1000T, TG3_PHY_ID_BCM5701 },
24daf2b0 15007 { TG3PCI_SUBVENDOR_ID_3COM,
79eb6904 15008 TG3PCI_SUBDEVICE_ID_3COM_3C940BR01, TG3_PHY_ID_BCM5701 },
1da177e4
LT		 15009
15010 /* DELL boards. */
24daf2b0 15011 { TG3PCI_SUBVENDOR_ID_DELL,
79eb6904 15012 TG3PCI_SUBDEVICE_ID_DELL_VIPER, TG3_PHY_ID_BCM5401 },
24daf2b0 15013 { TG3PCI_SUBVENDOR_ID_DELL,
79eb6904 15014 TG3PCI_SUBDEVICE_ID_DELL_JAGUAR, TG3_PHY_ID_BCM5401 },
24daf2b0 15015 { TG3PCI_SUBVENDOR_ID_DELL,
79eb6904 15016 TG3PCI_SUBDEVICE_ID_DELL_MERLOT, TG3_PHY_ID_BCM5411 },
24daf2b0 15017 { TG3PCI_SUBVENDOR_ID_DELL,
79eb6904 15018 TG3PCI_SUBDEVICE_ID_DELL_SLIM_MERLOT, TG3_PHY_ID_BCM5411 },
1da177e4
LT		 15019
15020 /* Compaq boards. */
24daf2b0 15021 { TG3PCI_SUBVENDOR_ID_COMPAQ,
79eb6904 15022 TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE, TG3_PHY_ID_BCM5701 },
24daf2b0 15023 { TG3PCI_SUBVENDOR_ID_COMPAQ,
79eb6904 15024 TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE_2, TG3_PHY_ID_BCM5701 },
24daf2b0
MC		 15025 { TG3PCI_SUBVENDOR_ID_COMPAQ,
15026 TG3PCI_SUBDEVICE_ID_COMPAQ_CHANGELING, 0 },
15027 { TG3PCI_SUBVENDOR_ID_COMPAQ,
79eb6904 15028 TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780, TG3_PHY_ID_BCM5701 },
24daf2b0 15029 { TG3PCI_SUBVENDOR_ID_COMPAQ,
79eb6904 15030 TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780_2, TG3_PHY_ID_BCM5701 },
1da177e4
LT		 15031
15032 /* IBM boards. */
24daf2b0
MC		 15033 { TG3PCI_SUBVENDOR_ID_IBM,
15034 TG3PCI_SUBDEVICE_ID_IBM_5703SAX2, 0 }
1da177e4
LT		 15035};
15036
229b1ad1 15037static struct subsys_tbl_ent *tg3_lookup_by_subsys(struct tg3 *tp)
1da177e4
LT		 15038{
15039 int i;
15040
15041 for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
15042 if ((subsys_id_to_phy_id[i].subsys_vendor ==
15043 tp->pdev->subsystem_vendor) &&
15044 (subsys_id_to_phy_id[i].subsys_devid ==
15045 tp->pdev->subsystem_device))
15046 return &subsys_id_to_phy_id[i];
15047 }
15048 return NULL;
15049}
15050
229b1ad1 15051static void tg3_get_eeprom_hw_cfg(struct tg3 *tp)
1da177e4 15052{
1da177e4 15053 u32 val;
f49639e6 15054
79eb6904 15055 tp->phy_id = TG3_PHY_ID_INVALID;
7d0c41ef
MC		 15056 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
15057
a85feb8c 15058 /* Assume an onboard device and WOL capable by default. */
63c3a66f
JP		 15059 tg3_flag_set(tp, EEPROM_WRITE_PROT);
15060 tg3_flag_set(tp, WOL_CAP);
72b845e0 15061
4153577a 15062 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
9d26e213 15063 if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) {
63c3a66f
JP		 15064 tg3_flag_clear(tp, EEPROM_WRITE_PROT);
15065 tg3_flag_set(tp, IS_NIC);
9d26e213 15066 }
0527ba35
MC		 15067 val = tr32(VCPU_CFGSHDW);
15068 if (val & VCPU_CFGSHDW_ASPM_DBNC)
63c3a66f 15069 tg3_flag_set(tp, ASPM_WORKAROUND);
0527ba35 15070 if ((val & VCPU_CFGSHDW_WOL_ENABLE) &&
6fdbab9d 15071 (val & VCPU_CFGSHDW_WOL_MAGPKT)) {
63c3a66f 15072 tg3_flag_set(tp, WOL_ENABLE);
6fdbab9d
RW		 15073 device_set_wakeup_enable(&tp->pdev->dev, true);
15074 }
05ac4cb7 15075 goto done;
b5d3772c
MC		 15076 }
15077
1da177e4
LT		 15078 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
15079 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
15080 u32 nic_cfg, led_cfg;
7c786065
NS		 15081 u32 cfg2 = 0, cfg4 = 0, cfg5 = 0;
15082 u32 nic_phy_id, ver, eeprom_phy_id;
7d0c41ef 15083 int eeprom_phy_serdes = 0;
1da177e4
LT		 15084
15085 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
15086 tp->nic_sram_data_cfg = nic_cfg;
15087
15088 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
15089 ver >>= NIC_SRAM_DATA_VER_SHIFT;
4153577a
JP		 15090 if (tg3_asic_rev(tp) != ASIC_REV_5700 &&
15091 tg3_asic_rev(tp) != ASIC_REV_5701 &&
15092 tg3_asic_rev(tp) != ASIC_REV_5703 &&
1da177e4
LT		 15093 (ver > 0) && (ver < 0x100))
15094 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
15095
4153577a 15096 if (tg3_asic_rev(tp) == ASIC_REV_5785)
a9daf367
MC		 15097 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_4, &cfg4);
15098
7c786065
NS		 15099 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
15100 tg3_asic_rev(tp) == ASIC_REV_5719 ||
15101 tg3_asic_rev(tp) == ASIC_REV_5720)
15102 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_5, &cfg5);
15103
1da177e4
LT		 15104 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
15105 NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
15106 eeprom_phy_serdes = 1;
15107
15108 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
15109 if (nic_phy_id != 0) {
15110 u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
15111 u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
15112
15113 eeprom_phy_id = (id1 >> 16) << 10;
15114 eeprom_phy_id |= (id2 & 0xfc00) << 16;
15115 eeprom_phy_id |= (id2 & 0x03ff) << 0;
15116 } else
15117 eeprom_phy_id = 0;
15118
7d0c41ef 15119 tp->phy_id = eeprom_phy_id;
747e8f8b 15120 if (eeprom_phy_serdes) {
63c3a66f 15121 if (!tg3_flag(tp, 5705_PLUS))
f07e9af3 15122 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
a50d0796 15123 else
f07e9af3 15124 tp->phy_flags |= TG3_PHYFLG_MII_SERDES;
747e8f8b 15125 }
7d0c41ef 15126
63c3a66f 15127 if (tg3_flag(tp, 5750_PLUS))
1da177e4
LT		 15128 led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
15129 SHASTA_EXT_LED_MODE_MASK);
cbf46853 15130 else
1da177e4
LT		 15131 led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
15132
15133 switch (led_cfg) {
15134 default:
15135 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
15136 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
15137 break;
15138
15139 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
15140 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
15141 break;
15142
15143 case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
15144 tp->led_ctrl = LED_CTRL_MODE_MAC;
9ba27794
MC		 15145
15146 /* Default to PHY_1_MODE if 0 (MAC_MODE) is
15147 * read on some older 5700/5701 bootcode.
15148 */
4153577a
JP		 15149 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
15150 tg3_asic_rev(tp) == ASIC_REV_5701)
9ba27794
MC		 15151 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
15152
1da177e4
LT		 15153 break;
15154
15155 case SHASTA_EXT_LED_SHARED:
15156 tp->led_ctrl = LED_CTRL_MODE_SHARED;
4153577a
JP		 15157 if (tg3_chip_rev_id(tp) != CHIPREV_ID_5750_A0 &&
15158 tg3_chip_rev_id(tp) != CHIPREV_ID_5750_A1)
1da177e4
LT		 15159 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
15160 LED_CTRL_MODE_PHY_2);
89f67978
NS		 15161
15162 if (tg3_flag(tp, 5717_PLUS) ||
15163 tg3_asic_rev(tp) == ASIC_REV_5762)
15164 tp->led_ctrl |= LED_CTRL_BLINK_RATE_OVERRIDE |
15165 LED_CTRL_BLINK_RATE_MASK;
15166
1da177e4
LT		 15167 break;
15168
15169 case SHASTA_EXT_LED_MAC:
15170 tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
15171 break;
15172
15173 case SHASTA_EXT_LED_COMBO:
15174 tp->led_ctrl = LED_CTRL_MODE_COMBO;
4153577a 15175 if (tg3_chip_rev_id(tp) != CHIPREV_ID_5750_A0)
1da177e4
LT		 15176 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
15177 LED_CTRL_MODE_PHY_2);
15178 break;
15179
855e1111 15180 }
1da177e4 15181
4153577a
JP		 15182 if ((tg3_asic_rev(tp) == ASIC_REV_5700 ||
15183 tg3_asic_rev(tp) == ASIC_REV_5701) &&
1da177e4
LT		 15184 tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
15185 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
15186
4153577a 15187 if (tg3_chip_rev(tp) == CHIPREV_5784_AX)
b2a5c19c 15188 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
5f60891b 15189
9d26e213 15190 if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) {
63c3a66f 15191 tg3_flag_set(tp, EEPROM_WRITE_PROT);
9d26e213
MC		 15192 if ((tp->pdev->subsystem_vendor ==
15193 PCI_VENDOR_ID_ARIMA) &&
15194 (tp->pdev->subsystem_device == 0x205a ||
15195 tp->pdev->subsystem_device == 0x2063))
63c3a66f 15196 tg3_flag_clear(tp, EEPROM_WRITE_PROT);
9d26e213 15197 } else {
63c3a66f
JP		 15198 tg3_flag_clear(tp, EEPROM_WRITE_PROT);
15199 tg3_flag_set(tp, IS_NIC);
9d26e213 15200 }
1da177e4
LT		 15201
15202 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
63c3a66f
JP		 15203 tg3_flag_set(tp, ENABLE_ASF);
15204 if (tg3_flag(tp, 5750_PLUS))
15205 tg3_flag_set(tp, ASF_NEW_HANDSHAKE);
1da177e4 15206 }
b2b98d4a
MC		 15207
15208 if ((nic_cfg & NIC_SRAM_DATA_CFG_APE_ENABLE) &&
63c3a66f
JP		 15209 tg3_flag(tp, 5750_PLUS))
15210 tg3_flag_set(tp, ENABLE_APE);
b2b98d4a 15211
f07e9af3 15212 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES &&
a85feb8c 15213 !(nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL))
63c3a66f 15214 tg3_flag_clear(tp, WOL_CAP);
1da177e4 15215
63c3a66f 15216 if (tg3_flag(tp, WOL_CAP) &&
6fdbab9d 15217 (nic_cfg & NIC_SRAM_DATA_CFG_WOL_ENABLE)) {
63c3a66f 15218 tg3_flag_set(tp, WOL_ENABLE);
6fdbab9d
RW		 15219 device_set_wakeup_enable(&tp->pdev->dev, true);
15220 }
0527ba35 15221
1da177e4 15222 if (cfg2 & (1 << 17))
f07e9af3 15223 tp->phy_flags |= TG3_PHYFLG_CAPACITIVE_COUPLING;
1da177e4
LT		 15224
15225 /* serdes signal pre-emphasis in register 0x590 set by */
15226 /* bootcode if bit 18 is set */
15227 if (cfg2 & (1 << 18))
f07e9af3 15228 tp->phy_flags |= TG3_PHYFLG_SERDES_PREEMPHASIS;
8ed5d97e 15229
63c3a66f 15230 if ((tg3_flag(tp, 57765_PLUS) ||
4153577a
JP		 15231 (tg3_asic_rev(tp) == ASIC_REV_5784 &&
15232 tg3_chip_rev(tp) != CHIPREV_5784_AX)) &&
6833c043 15233 (cfg2 & NIC_SRAM_DATA_CFG_2_APD_EN))
f07e9af3 15234 tp->phy_flags |= TG3_PHYFLG_ENABLE_APD;
6833c043 15235
942d1af0 15236 if (tg3_flag(tp, PCI_EXPRESS)) {
8ed5d97e
MC		 15237 u32 cfg3;
15238
15239 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3);
942d1af0
NS		 15240 if (tg3_asic_rev(tp) != ASIC_REV_5785 &&
15241 !tg3_flag(tp, 57765_PLUS) &&
15242 (cfg3 & NIC_SRAM_ASPM_DEBOUNCE))
63c3a66f 15243 tg3_flag_set(tp, ASPM_WORKAROUND);
942d1af0
NS		 15244 if (cfg3 & NIC_SRAM_LNK_FLAP_AVOID)
15245 tp->phy_flags |= TG3_PHYFLG_KEEP_LINK_ON_PWRDN;
15246 if (cfg3 & NIC_SRAM_1G_ON_VAUX_OK)
15247 tp->phy_flags |= TG3_PHYFLG_1G_ON_VAUX_OK;
8ed5d97e 15248 }
a9daf367 15249
14417063 15250 if (cfg4 & NIC_SRAM_RGMII_INBAND_DISABLE)
63c3a66f 15251 tg3_flag_set(tp, RGMII_INBAND_DISABLE);
a9daf367 15252 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_RX_EN)
63c3a66f 15253 tg3_flag_set(tp, RGMII_EXT_IBND_RX_EN);
a9daf367 15254 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_TX_EN)
63c3a66f 15255 tg3_flag_set(tp, RGMII_EXT_IBND_TX_EN);
7c786065
NS		 15256
15257 if (cfg5 & NIC_SRAM_DISABLE_1G_HALF_ADV)
15258 tp->phy_flags |= TG3_PHYFLG_DISABLE_1G_HD_ADV;
1da177e4 15259 }
05ac4cb7 15260done:
63c3a66f 15261 if (tg3_flag(tp, WOL_CAP))
43067ed8 15262 device_set_wakeup_enable(&tp->pdev->dev,
63c3a66f 15263 tg3_flag(tp, WOL_ENABLE));
43067ed8
RW		 15264 else
15265 device_set_wakeup_capable(&tp->pdev->dev, false);
7d0c41ef
MC		 15266}
15267
c86a8560
MC		 15268static int tg3_ape_otp_read(struct tg3 *tp, u32 offset, u32 *val)
15269{
15270 int i, err;
15271 u32 val2, off = offset * 8;
15272
15273 err = tg3_nvram_lock(tp);
15274 if (err)
15275 return err;
15276
15277 tg3_ape_write32(tp, TG3_APE_OTP_ADDR, off | APE_OTP_ADDR_CPU_ENABLE);
15278 tg3_ape_write32(tp, TG3_APE_OTP_CTRL, APE_OTP_CTRL_PROG_EN |
15279 APE_OTP_CTRL_CMD_RD | APE_OTP_CTRL_START);
15280 tg3_ape_read32(tp, TG3_APE_OTP_CTRL);
15281 udelay(10);
15282
15283 for (i = 0; i < 100; i++) {
15284 val2 = tg3_ape_read32(tp, TG3_APE_OTP_STATUS);
15285 if (val2 & APE_OTP_STATUS_CMD_DONE) {
15286 *val = tg3_ape_read32(tp, TG3_APE_OTP_RD_DATA);
15287 break;
15288 }
15289 udelay(10);
15290 }
15291
15292 tg3_ape_write32(tp, TG3_APE_OTP_CTRL, 0);
15293
15294 tg3_nvram_unlock(tp);
15295 if (val2 & APE_OTP_STATUS_CMD_DONE)
15296 return 0;
15297
15298 return -EBUSY;
15299}
15300
229b1ad1 15301static int tg3_issue_otp_command(struct tg3 *tp, u32 cmd)
b2a5c19c
MC		 15302{
15303 int i;
15304 u32 val;
15305
15306 tw32(OTP_CTRL, cmd | OTP_CTRL_OTP_CMD_START);
15307 tw32(OTP_CTRL, cmd);
15308
15309 /* Wait for up to 1 ms for command to execute. */
15310 for (i = 0; i < 100; i++) {
15311 val = tr32(OTP_STATUS);
15312 if (val & OTP_STATUS_CMD_DONE)
15313 break;
15314 udelay(10);
15315 }
15316
15317 return (val & OTP_STATUS_CMD_DONE) ? 0 : -EBUSY;
15318}
15319
15320/* Read the gphy configuration from the OTP region of the chip. The gphy
15321 * configuration is a 32-bit value that straddles the alignment boundary.
15322 * We do two 32-bit reads and then shift and merge the results.
15323 */
229b1ad1 15324static u32 tg3_read_otp_phycfg(struct tg3 *tp)
b2a5c19c
MC		 15325{
15326 u32 bhalf_otp, thalf_otp;
15327
15328 tw32(OTP_MODE, OTP_MODE_OTP_THRU_GRC);
15329
15330 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_INIT))
15331 return 0;
15332
15333 tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC1);
15334
15335 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
15336 return 0;
15337
15338 thalf_otp = tr32(OTP_READ_DATA);
15339
15340 tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC2);
15341
15342 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
15343 return 0;
15344
15345 bhalf_otp = tr32(OTP_READ_DATA);
15346
15347 return ((thalf_otp & 0x0000ffff) << 16) | (bhalf_otp >> 16);
15348}
15349
229b1ad1 15350static void tg3_phy_init_link_config(struct tg3 *tp)
e256f8a3 15351{
202ff1c2 15352 u32 adv = ADVERTISED_Autoneg;
e256f8a3 15353
7c786065
NS		 15354 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
15355 if (!(tp->phy_flags & TG3_PHYFLG_DISABLE_1G_HD_ADV))
15356 adv |= ADVERTISED_1000baseT_Half;
15357 adv |= ADVERTISED_1000baseT_Full;
15358 }
e256f8a3
MC		 15359
15360 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
15361 adv |= ADVERTISED_100baseT_Half |
15362 ADVERTISED_100baseT_Full |
15363 ADVERTISED_10baseT_Half |
15364 ADVERTISED_10baseT_Full |
15365 ADVERTISED_TP;
15366 else
15367 adv |= ADVERTISED_FIBRE;
15368
15369 tp->link_config.advertising = adv;
e740522e
MC		 15370 tp->link_config.speed = SPEED_UNKNOWN;
15371 tp->link_config.duplex = DUPLEX_UNKNOWN;
e256f8a3 15372 tp->link_config.autoneg = AUTONEG_ENABLE;
e740522e
MC		 15373 tp->link_config.active_speed = SPEED_UNKNOWN;
15374 tp->link_config.active_duplex = DUPLEX_UNKNOWN;
34655ad6
MC		 15375
15376 tp->old_link = -1;
e256f8a3
MC		 15377}
15378
229b1ad1 15379static int tg3_phy_probe(struct tg3 *tp)
7d0c41ef
MC		 15380{
15381 u32 hw_phy_id_1, hw_phy_id_2;
15382 u32 hw_phy_id, hw_phy_id_masked;
15383 int err;
1da177e4 15384
e256f8a3 15385 /* flow control autonegotiation is default behavior */
63c3a66f 15386 tg3_flag_set(tp, PAUSE_AUTONEG);
e256f8a3
MC		 15387 tp->link_config.flowctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
15388
8151ad57
MC		 15389 if (tg3_flag(tp, ENABLE_APE)) {
15390 switch (tp->pci_fn) {
15391 case 0:
15392 tp->phy_ape_lock = TG3_APE_LOCK_PHY0;
15393 break;
15394 case 1:
15395 tp->phy_ape_lock = TG3_APE_LOCK_PHY1;
15396 break;
15397 case 2:
15398 tp->phy_ape_lock = TG3_APE_LOCK_PHY2;
15399 break;
15400 case 3:
15401 tp->phy_ape_lock = TG3_APE_LOCK_PHY3;
15402 break;
15403 }
15404 }
15405
942d1af0
NS		 15406 if (!tg3_flag(tp, ENABLE_ASF) &&
15407 !(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) &&
15408 !(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
15409 tp->phy_flags &= ~(TG3_PHYFLG_1G_ON_VAUX_OK |
15410 TG3_PHYFLG_KEEP_LINK_ON_PWRDN);
15411
63c3a66f 15412 if (tg3_flag(tp, USE_PHYLIB))
b02fd9e3
MC		 15413 return tg3_phy_init(tp);
15414
1da177e4 15415 /* Reading the PHY ID register can conflict with ASF
877d0310 15416 * firmware access to the PHY hardware.
1da177e4
LT		 15417 */
15418 err = 0;
63c3a66f 15419 if (tg3_flag(tp, ENABLE_ASF) || tg3_flag(tp, ENABLE_APE)) {
79eb6904 15420 hw_phy_id = hw_phy_id_masked = TG3_PHY_ID_INVALID;
1da177e4
LT		 15421 } else {
15422 /* Now read the physical PHY_ID from the chip and verify
15423 * that it is sane. If it doesn't look good, we fall back
15424 * to either the hard-coded table based PHY_ID and failing
15425 * that the value found in the eeprom area.
15426 */
15427 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
15428 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
15429
15430 hw_phy_id = (hw_phy_id_1 & 0xffff) << 10;
15431 hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
15432 hw_phy_id |= (hw_phy_id_2 & 0x03ff) << 0;
15433
79eb6904 15434 hw_phy_id_masked = hw_phy_id & TG3_PHY_ID_MASK;
1da177e4
LT		 15435 }
15436
79eb6904 15437 if (!err && TG3_KNOWN_PHY_ID(hw_phy_id_masked)) {
1da177e4 15438 tp->phy_id = hw_phy_id;
79eb6904 15439 if (hw_phy_id_masked == TG3_PHY_ID_BCM8002)
f07e9af3 15440 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
da6b2d01 15441 else
f07e9af3 15442 tp->phy_flags &= ~TG3_PHYFLG_PHY_SERDES;
1da177e4 15443 } else {
79eb6904 15444 if (tp->phy_id != TG3_PHY_ID_INVALID) {
7d0c41ef
MC		 15445 /* Do nothing, phy ID already set up in
15446 * tg3_get_eeprom_hw_cfg().
15447 */
1da177e4
LT		 15448 } else {
15449 struct subsys_tbl_ent *p;
15450
15451 /* No eeprom signature? Try the hardcoded
15452 * subsys device table.
15453 */
24daf2b0 15454 p = tg3_lookup_by_subsys(tp);
7e6c63f0
HM		 15455 if (p) {
15456 tp->phy_id = p->phy_id;
15457 } else if (!tg3_flag(tp, IS_SSB_CORE)) {
15458 /* For now we saw the IDs 0xbc050cd0,
15459 * 0xbc050f80 and 0xbc050c30 on devices
15460 * connected to an BCM4785 and there are
15461 * probably more. Just assume that the phy is
15462 * supported when it is connected to a SSB core
15463 * for now.
15464 */
1da177e4 15465 return -ENODEV;
7e6c63f0 15466 }
1da177e4 15467
1da177e4 15468 if (!tp->phy_id ||
79eb6904 15469 tp->phy_id == TG3_PHY_ID_BCM8002)
f07e9af3 15470 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
1da177e4
LT		 15471 }
15472 }
15473
a6b68dab 15474 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) &&
4153577a
JP		 15475 (tg3_asic_rev(tp) == ASIC_REV_5719 ||
15476 tg3_asic_rev(tp) == ASIC_REV_5720 ||
c4dab506 15477 tg3_asic_rev(tp) == ASIC_REV_57766 ||
4153577a
JP		 15478 tg3_asic_rev(tp) == ASIC_REV_5762 ||
15479 (tg3_asic_rev(tp) == ASIC_REV_5717 &&
15480 tg3_chip_rev_id(tp) != CHIPREV_ID_5717_A0) ||
15481 (tg3_asic_rev(tp) == ASIC_REV_57765 &&
9e2ecbeb 15482 tg3_chip_rev_id(tp) != CHIPREV_ID_57765_A0))) {
52b02d04
MC		 15483 tp->phy_flags |= TG3_PHYFLG_EEE_CAP;
15484
9e2ecbeb
NS		 15485 tp->eee.supported = SUPPORTED_100baseT_Full |
15486 SUPPORTED_1000baseT_Full;
15487 tp->eee.advertised = ADVERTISED_100baseT_Full |
15488 ADVERTISED_1000baseT_Full;
15489 tp->eee.eee_enabled = 1;
15490 tp->eee.tx_lpi_enabled = 1;
15491 tp->eee.tx_lpi_timer = TG3_CPMU_DBTMR1_LNKIDLE_2047US;
15492 }
15493
e256f8a3
MC		 15494 tg3_phy_init_link_config(tp);
15495
942d1af0
NS		 15496 if (!(tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN) &&
15497 !(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) &&
63c3a66f
JP		 15498 !tg3_flag(tp, ENABLE_APE) &&
15499 !tg3_flag(tp, ENABLE_ASF)) {
e2bf73e7 15500 u32 bmsr, dummy;
1da177e4
LT		 15501
15502 tg3_readphy(tp, MII_BMSR, &bmsr);
15503 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
15504 (bmsr & BMSR_LSTATUS))
15505 goto skip_phy_reset;
6aa20a22 15506
1da177e4
LT		 15507 err = tg3_phy_reset(tp);
15508 if (err)
15509 return err;
15510
42b64a45 15511 tg3_phy_set_wirespeed(tp);
1da177e4 15512
e2bf73e7 15513 if (!tg3_phy_copper_an_config_ok(tp, &dummy)) {
42b64a45
MC		 15514 tg3_phy_autoneg_cfg(tp, tp->link_config.advertising,
15515 tp->link_config.flowctrl);
1da177e4
LT		 15516
15517 tg3_writephy(tp, MII_BMCR,
15518 BMCR_ANENABLE | BMCR_ANRESTART);
15519 }
1da177e4
LT		 15520 }
15521
15522skip_phy_reset:
79eb6904 15523 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
1da177e4
LT		 15524 err = tg3_init_5401phy_dsp(tp);
15525 if (err)
15526 return err;
1da177e4 15527
1da177e4
LT		 15528 err = tg3_init_5401phy_dsp(tp);
15529 }
15530
1da177e4
LT		 15531 return err;
15532}
15533
229b1ad1 15534static void tg3_read_vpd(struct tg3 *tp)
1da177e4 15535{
a4a8bb15 15536 u8 *vpd_data;
4181b2c8 15537 unsigned int block_end, rosize, len;
535a490e 15538 u32 vpdlen;
184b8904 15539 int j, i = 0;
a4a8bb15 15540
535a490e 15541 vpd_data = (u8 *)tg3_vpd_readblock(tp, &vpdlen);
a4a8bb15
MC		 15542 if (!vpd_data)
15543 goto out_no_vpd;
1da177e4 15544
535a490e 15545 i = pci_vpd_find_tag(vpd_data, 0, vpdlen, PCI_VPD_LRDT_RO_DATA);
4181b2c8
MC		 15546 if (i < 0)
15547 goto out_not_found;
1da177e4 15548
4181b2c8
MC		 15549 rosize = pci_vpd_lrdt_size(&vpd_data[i]);
15550 block_end = i + PCI_VPD_LRDT_TAG_SIZE + rosize;
15551 i += PCI_VPD_LRDT_TAG_SIZE;
1da177e4 15552
535a490e 15553 if (block_end > vpdlen)
4181b2c8 15554 goto out_not_found;
af2c6a4a 15555
184b8904
MC		 15556 j = pci_vpd_find_info_keyword(vpd_data, i, rosize,
15557 PCI_VPD_RO_KEYWORD_MFR_ID);
15558 if (j > 0) {
15559 len = pci_vpd_info_field_size(&vpd_data[j]);
15560
15561 j += PCI_VPD_INFO_FLD_HDR_SIZE;
15562 if (j + len > block_end || len != 4 ||
15563 memcmp(&vpd_data[j], "1028", 4))
15564 goto partno;
15565
15566 j = pci_vpd_find_info_keyword(vpd_data, i, rosize,
15567 PCI_VPD_RO_KEYWORD_VENDOR0);
15568 if (j < 0)
15569 goto partno;
15570
15571 len = pci_vpd_info_field_size(&vpd_data[j]);
15572
15573 j += PCI_VPD_INFO_FLD_HDR_SIZE;
15574 if (j + len > block_end)
15575 goto partno;
15576
715230a4
KC		 15577 if (len >= sizeof(tp->fw_ver))
15578 len = sizeof(tp->fw_ver) - 1;
15579 memset(tp->fw_ver, 0, sizeof(tp->fw_ver));
15580 snprintf(tp->fw_ver, sizeof(tp->fw_ver), "%.*s bc ", len,
15581 &vpd_data[j]);
184b8904
MC		 15582 }
15583
15584partno:
4181b2c8
MC		 15585 i = pci_vpd_find_info_keyword(vpd_data, i, rosize,
15586 PCI_VPD_RO_KEYWORD_PARTNO);
15587 if (i < 0)
15588 goto out_not_found;
af2c6a4a 15589
4181b2c8 15590 len = pci_vpd_info_field_size(&vpd_data[i]);
1da177e4 15591
4181b2c8
MC		 15592 i += PCI_VPD_INFO_FLD_HDR_SIZE;
15593 if (len > TG3_BPN_SIZE ||
535a490e 15594 (len + i) > vpdlen)
4181b2c8 15595 goto out_not_found;
1da177e4 15596
4181b2c8 15597 memcpy(tp->board_part_number, &vpd_data[i], len);
1da177e4 15598
1da177e4 15599out_not_found:
a4a8bb15 15600 kfree(vpd_data);
37a949c5 15601 if (tp->board_part_number[0])
a4a8bb15
MC		 15602 return;
15603
15604out_no_vpd:
4153577a 15605 if (tg3_asic_rev(tp) == ASIC_REV_5717) {
79d49695
MC		 15606 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 ||
15607 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717_C)
37a949c5
MC		 15608 strcpy(tp->board_part_number, "BCM5717");
15609 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718)
15610 strcpy(tp->board_part_number, "BCM5718");
15611 else
15612 goto nomatch;
4153577a 15613 } else if (tg3_asic_rev(tp) == ASIC_REV_57780) {
37a949c5
MC		 15614 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57780)
15615 strcpy(tp->board_part_number, "BCM57780");
15616 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57760)
15617 strcpy(tp->board_part_number, "BCM57760");
15618 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790)
15619 strcpy(tp->board_part_number, "BCM57790");
15620 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57788)
15621 strcpy(tp->board_part_number, "BCM57788");
15622 else
15623 goto nomatch;
4153577a 15624 } else if (tg3_asic_rev(tp) == ASIC_REV_57765) {
37a949c5
MC		 15625 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761)
15626 strcpy(tp->board_part_number, "BCM57761");
15627 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765)
15628 strcpy(tp->board_part_number, "BCM57765");
15629 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781)
15630 strcpy(tp->board_part_number, "BCM57781");
15631 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785)
15632 strcpy(tp->board_part_number, "BCM57785");
15633 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791)
15634 strcpy(tp->board_part_number, "BCM57791");
15635 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795)
15636 strcpy(tp->board_part_number, "BCM57795");
15637 else
15638 goto nomatch;
4153577a 15639 } else if (tg3_asic_rev(tp) == ASIC_REV_57766) {
55086ad9
MC		 15640 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57762)
15641 strcpy(tp->board_part_number, "BCM57762");
15642 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57766)
15643 strcpy(tp->board_part_number, "BCM57766");
15644 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57782)
15645 strcpy(tp->board_part_number, "BCM57782");
15646 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57786)
15647 strcpy(tp->board_part_number, "BCM57786");
15648 else
15649 goto nomatch;
4153577a 15650 } else if (tg3_asic_rev(tp) == ASIC_REV_5906) {
b5d3772c 15651 strcpy(tp->board_part_number, "BCM95906");
37a949c5
MC		 15652 } else {
15653nomatch:
b5d3772c 15654 strcpy(tp->board_part_number, "none");
37a949c5 15655 }
1da177e4
LT		 15656}
15657
229b1ad1 15658static int tg3_fw_img_is_valid(struct tg3 *tp, u32 offset)
9c8a620e
MC		 15659{
15660 u32 val;
15661
e4f34110 15662 if (tg3_nvram_read(tp, offset, &val) ||
9c8a620e 15663 (val & 0xfc000000) != 0x0c000000 ||
e4f34110 15664 tg3_nvram_read(tp, offset + 4, &val) ||
9c8a620e
MC		 15665 val != 0)
15666 return 0;
15667
15668 return 1;
15669}
15670
229b1ad1 15671static void tg3_read_bc_ver(struct tg3 *tp)
acd9c119 15672{
ff3a7cb2 15673 u32 val, offset, start, ver_offset;
75f9936e 15674 int i, dst_off;
ff3a7cb2 15675 bool newver = false;
acd9c119
MC		 15676
15677 if (tg3_nvram_read(tp, 0xc, &offset) ||
15678 tg3_nvram_read(tp, 0x4, &start))
15679 return;
15680
15681 offset = tg3_nvram_logical_addr(tp, offset);
15682
ff3a7cb2 15683 if (tg3_nvram_read(tp, offset, &val))
acd9c119
MC		 15684 return;
15685
ff3a7cb2
MC		 15686 if ((val & 0xfc000000) == 0x0c000000) {
15687 if (tg3_nvram_read(tp, offset + 4, &val))
acd9c119
MC		 15688 return;
15689
ff3a7cb2
MC		 15690 if (val == 0)
15691 newver = true;
15692 }
15693
75f9936e
MC		 15694 dst_off = strlen(tp->fw_ver);
15695
ff3a7cb2 15696 if (newver) {
75f9936e
MC		 15697 if (TG3_VER_SIZE - dst_off < 16 ||
15698 tg3_nvram_read(tp, offset + 8, &ver_offset))
ff3a7cb2
MC		 15699 return;
15700
15701 offset = offset + ver_offset - start;
15702 for (i = 0; i < 16; i += 4) {
15703 __be32 v;
15704 if (tg3_nvram_read_be32(tp, offset + i, &v))
15705 return;
15706
75f9936e 15707 memcpy(tp->fw_ver + dst_off + i, &v, sizeof(v));
ff3a7cb2
MC		 15708 }
15709 } else {
15710 u32 major, minor;
15711
15712 if (tg3_nvram_read(tp, TG3_NVM_PTREV_BCVER, &ver_offset))
15713 return;
15714
15715 major = (ver_offset & TG3_NVM_BCVER_MAJMSK) >>
15716 TG3_NVM_BCVER_MAJSFT;
15717 minor = ver_offset & TG3_NVM_BCVER_MINMSK;
75f9936e
MC		 15718 snprintf(&tp->fw_ver[dst_off], TG3_VER_SIZE - dst_off,
15719 "v%d.%02d", major, minor);
acd9c119
MC		 15720 }
15721}
15722
229b1ad1 15723static void tg3_read_hwsb_ver(struct tg3 *tp)
a6f6cb1c
MC		 15724{
15725 u32 val, major, minor;
15726
15727 /* Use native endian representation */
15728 if (tg3_nvram_read(tp, TG3_NVM_HWSB_CFG1, &val))
15729 return;
15730
15731 major = (val & TG3_NVM_HWSB_CFG1_MAJMSK) >>
15732 TG3_NVM_HWSB_CFG1_MAJSFT;
15733 minor = (val & TG3_NVM_HWSB_CFG1_MINMSK) >>
15734 TG3_NVM_HWSB_CFG1_MINSFT;
15735
15736 snprintf(&tp->fw_ver[0], 32, "sb v%d.%02d", major, minor);
15737}
15738
229b1ad1 15739static void tg3_read_sb_ver(struct tg3 *tp, u32 val)
dfe00d7d
MC		 15740{
15741 u32 offset, major, minor, build;
15742
75f9936e 15743 strncat(tp->fw_ver, "sb", TG3_VER_SIZE - strlen(tp->fw_ver) - 1);
dfe00d7d
MC		 15744
15745 if ((val & TG3_EEPROM_SB_FORMAT_MASK) != TG3_EEPROM_SB_FORMAT_1)
15746 return;
15747
15748 switch (val & TG3_EEPROM_SB_REVISION_MASK) {
15749 case TG3_EEPROM_SB_REVISION_0:
15750 offset = TG3_EEPROM_SB_F1R0_EDH_OFF;
15751 break;
15752 case TG3_EEPROM_SB_REVISION_2:
15753 offset = TG3_EEPROM_SB_F1R2_EDH_OFF;
15754 break;
15755 case TG3_EEPROM_SB_REVISION_3:
15756 offset = TG3_EEPROM_SB_F1R3_EDH_OFF;
15757 break;
a4153d40
MC		 15758 case TG3_EEPROM_SB_REVISION_4:
15759 offset = TG3_EEPROM_SB_F1R4_EDH_OFF;
15760 break;
15761 case TG3_EEPROM_SB_REVISION_5:
15762 offset = TG3_EEPROM_SB_F1R5_EDH_OFF;
15763 break;
bba226ac
MC		 15764 case TG3_EEPROM_SB_REVISION_6:
15765 offset = TG3_EEPROM_SB_F1R6_EDH_OFF;
15766 break;
dfe00d7d
MC		 15767 default:
15768 return;
15769 }
15770
e4f34110 15771 if (tg3_nvram_read(tp, offset, &val))
dfe00d7d
MC		 15772 return;
15773
15774 build = (val & TG3_EEPROM_SB_EDH_BLD_MASK) >>
15775 TG3_EEPROM_SB_EDH_BLD_SHFT;
15776 major = (val & TG3_EEPROM_SB_EDH_MAJ_MASK) >>
15777 TG3_EEPROM_SB_EDH_MAJ_SHFT;
15778 minor = val & TG3_EEPROM_SB_EDH_MIN_MASK;
15779
15780 if (minor > 99 || build > 26)
15781 return;
15782
75f9936e
MC		 15783 offset = strlen(tp->fw_ver);
15784 snprintf(&tp->fw_ver[offset], TG3_VER_SIZE - offset,
15785 " v%d.%02d", major, minor);
dfe00d7d
MC		 15786
15787 if (build > 0) {
75f9936e
MC		 15788 offset = strlen(tp->fw_ver);
15789 if (offset < TG3_VER_SIZE - 1)
15790 tp->fw_ver[offset] = 'a' + build - 1;
dfe00d7d
MC		 15791 }
15792}
15793
229b1ad1 15794static void tg3_read_mgmtfw_ver(struct tg3 *tp)
c4e6575c
MC		 15795{
15796 u32 val, offset, start;
acd9c119 15797 int i, vlen;
9c8a620e
MC		 15798
15799 for (offset = TG3_NVM_DIR_START;
15800 offset < TG3_NVM_DIR_END;
15801 offset += TG3_NVM_DIRENT_SIZE) {
e4f34110 15802 if (tg3_nvram_read(tp, offset, &val))
c4e6575c
MC		 15803 return;
15804
9c8a620e
MC		 15805 if ((val >> TG3_NVM_DIRTYPE_SHIFT) == TG3_NVM_DIRTYPE_ASFINI)
15806 break;
15807 }
15808
15809 if (offset == TG3_NVM_DIR_END)
15810 return;
15811
63c3a66f 15812 if (!tg3_flag(tp, 5705_PLUS))
9c8a620e 15813 start = 0x08000000;
e4f34110 15814 else if (tg3_nvram_read(tp, offset - 4, &start))
9c8a620e
MC		 15815 return;
15816
e4f34110 15817 if (tg3_nvram_read(tp, offset + 4, &offset) ||
9c8a620e 15818 !tg3_fw_img_is_valid(tp, offset) ||
e4f34110 15819 tg3_nvram_read(tp, offset + 8, &val))
9c8a620e
MC		 15820 return;
15821
15822 offset += val - start;
15823
acd9c119 15824 vlen = strlen(tp->fw_ver);
9c8a620e 15825
acd9c119
MC		 15826 tp->fw_ver[vlen++] = ',';
15827 tp->fw_ver[vlen++] = ' ';
9c8a620e
MC		 15828
15829 for (i = 0; i < 4; i++) {
a9dc529d
MC		 15830 __be32 v;
15831 if (tg3_nvram_read_be32(tp, offset, &v))
c4e6575c
MC		 15832 return;
15833
b9fc7dc5 15834 offset += sizeof(v);
c4e6575c 15835
acd9c119
MC		 15836 if (vlen > TG3_VER_SIZE - sizeof(v)) {
15837 memcpy(&tp->fw_ver[vlen], &v, TG3_VER_SIZE - vlen);
9c8a620e 15838 break;
c4e6575c 15839 }
9c8a620e 15840
acd9c119
MC		 15841 memcpy(&tp->fw_ver[vlen], &v, sizeof(v));
15842 vlen += sizeof(v);
c4e6575c 15843 }
acd9c119
MC		 15844}
15845
229b1ad1 15846static void tg3_probe_ncsi(struct tg3 *tp)
7fd76445 15847{
7fd76445 15848 u32 apedata;
7fd76445
MC		 15849
15850 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
15851 if (apedata != APE_SEG_SIG_MAGIC)
15852 return;
15853
15854 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
15855 if (!(apedata & APE_FW_STATUS_READY))
15856 return;
15857
165f4d1c
MC		 15858 if (tg3_ape_read32(tp, TG3_APE_FW_FEATURES) & TG3_APE_FW_FEATURE_NCSI)
15859 tg3_flag_set(tp, APE_HAS_NCSI);
15860}
15861
229b1ad1 15862static void tg3_read_dash_ver(struct tg3 *tp)
165f4d1c
MC		 15863{
15864 int vlen;
15865 u32 apedata;
15866 char *fwtype;
15867
7fd76445
MC		 15868 apedata = tg3_ape_read32(tp, TG3_APE_FW_VERSION);
15869
165f4d1c 15870 if (tg3_flag(tp, APE_HAS_NCSI))
ecc79648 15871 fwtype = "NCSI";
c86a8560
MC		 15872 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5725)
15873 fwtype = "SMASH";
165f4d1c 15874 else
ecc79648
MC		 15875 fwtype = "DASH";
15876
7fd76445
MC		 15877 vlen = strlen(tp->fw_ver);
15878
ecc79648
MC		 15879 snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " %s v%d.%d.%d.%d",
15880 fwtype,
7fd76445
MC		 15881 (apedata & APE_FW_VERSION_MAJMSK) >> APE_FW_VERSION_MAJSFT,
15882 (apedata & APE_FW_VERSION_MINMSK) >> APE_FW_VERSION_MINSFT,
15883 (apedata & APE_FW_VERSION_REVMSK) >> APE_FW_VERSION_REVSFT,
15884 (apedata & APE_FW_VERSION_BLDMSK));
15885}
15886
c86a8560
MC		 15887static void tg3_read_otp_ver(struct tg3 *tp)
15888{
15889 u32 val, val2;
15890
4153577a 15891 if (tg3_asic_rev(tp) != ASIC_REV_5762)
c86a8560
MC		 15892 return;
15893
15894 if (!tg3_ape_otp_read(tp, OTP_ADDRESS_MAGIC0, &val) &&
15895 !tg3_ape_otp_read(tp, OTP_ADDRESS_MAGIC0 + 4, &val2) &&
15896 TG3_OTP_MAGIC0_VALID(val)) {
15897 u64 val64 = (u64) val << 32 | val2;
15898 u32 ver = 0;
15899 int i, vlen;
15900
15901 for (i = 0; i < 7; i++) {
15902 if ((val64 & 0xff) == 0)
15903 break;
15904 ver = val64 & 0xff;
15905 val64 >>= 8;
15906 }
15907 vlen = strlen(tp->fw_ver);
15908 snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " .%02d", ver);
15909 }
15910}
15911
229b1ad1 15912static void tg3_read_fw_ver(struct tg3 *tp)
acd9c119
MC		 15913{
15914 u32 val;
75f9936e 15915 bool vpd_vers = false;
acd9c119 15916
75f9936e
MC		 15917 if (tp->fw_ver[0] != 0)
15918 vpd_vers = true;
df259d8c 15919
63c3a66f 15920 if (tg3_flag(tp, NO_NVRAM)) {
75f9936e 15921 strcat(tp->fw_ver, "sb");
c86a8560 15922 tg3_read_otp_ver(tp);
df259d8c
MC		 15923 return;
15924 }
15925
acd9c119
MC		 15926 if (tg3_nvram_read(tp, 0, &val))
15927 return;
15928
15929 if (val == TG3_EEPROM_MAGIC)
15930 tg3_read_bc_ver(tp);
15931 else if ((val & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW)
15932 tg3_read_sb_ver(tp, val);
a6f6cb1c
MC		 15933 else if ((val & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
15934 tg3_read_hwsb_ver(tp);
acd9c119 15935
165f4d1c
MC		 15936 if (tg3_flag(tp, ENABLE_ASF)) {
15937 if (tg3_flag(tp, ENABLE_APE)) {
15938 tg3_probe_ncsi(tp);
15939 if (!vpd_vers)
15940 tg3_read_dash_ver(tp);
15941 } else if (!vpd_vers) {
15942 tg3_read_mgmtfw_ver(tp);
15943 }
c9cab24e 15944 }
9c8a620e
MC		 15945
15946 tp->fw_ver[TG3_VER_SIZE - 1] = 0;
c4e6575c
MC		 15947}
15948
7cb32cf2
MC		 15949static inline u32 tg3_rx_ret_ring_size(struct tg3 *tp)
15950{
63c3a66f 15951 if (tg3_flag(tp, LRG_PROD_RING_CAP))
de9f5230 15952 return TG3_RX_RET_MAX_SIZE_5717;
63c3a66f 15953 else if (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS))
de9f5230 15954 return TG3_RX_RET_MAX_SIZE_5700;
7cb32cf2 15955 else
de9f5230 15956 return TG3_RX_RET_MAX_SIZE_5705;
7cb32cf2
MC		 15957}
15958
9baa3c34 15959static const struct pci_device_id tg3_write_reorder_chipsets[] = {
895950c2
JP		 15960 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C) },
15961 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE) },
15962 { PCI_DEVICE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8385_0) },
15963 { },
15964};
15965
229b1ad1 15966static struct pci_dev *tg3_find_peer(struct tg3 *tp)
16c7fa7d
MC		 15967{
15968 struct pci_dev *peer;
15969 unsigned int func, devnr = tp->pdev->devfn & ~7;
15970
15971 for (func = 0; func < 8; func++) {
15972 peer = pci_get_slot(tp->pdev->bus, devnr | func);
15973 if (peer && peer != tp->pdev)
15974 break;
15975 pci_dev_put(peer);
15976 }
15977 /* 5704 can be configured in single-port mode, set peer to
15978 * tp->pdev in that case.
15979 */
15980 if (!peer) {
15981 peer = tp->pdev;
15982 return peer;
15983 }
15984
15985 /*
15986 * We don't need to keep the refcount elevated; there's no way
15987 * to remove one half of this device without removing the other
15988 */
15989 pci_dev_put(peer);
15990
15991 return peer;
15992}
15993
229b1ad1 15994static void tg3_detect_asic_rev(struct tg3 *tp, u32 misc_ctrl_reg)
42b123b1
MC		 15995{
15996 tp->pci_chip_rev_id = misc_ctrl_reg >> MISC_HOST_CTRL_CHIPREV_SHIFT;
4153577a 15997 if (tg3_asic_rev(tp) == ASIC_REV_USE_PROD_ID_REG) {
42b123b1
MC		 15998 u32 reg;
15999
16000 /* All devices that use the alternate
16001 * ASIC REV location have a CPMU.
16002 */
16003 tg3_flag_set(tp, CPMU_PRESENT);
16004
16005 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 ||
79d49695 16006 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717_C ||
42b123b1
MC		 16007 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 ||
16008 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5719 ||
c65a17f4 16009 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5720 ||
68273712
NS		 16010 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57767 ||
16011 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57764 ||
c65a17f4
MC		 16012 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5762 ||
16013 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5725 ||
68273712
NS		 16014 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5727 ||
16015 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57787)
42b123b1
MC		 16016 reg = TG3PCI_GEN2_PRODID_ASICREV;
16017 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781 ||
16018 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785 ||
16019 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761 ||
16020 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765 ||
16021 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791 ||
16022 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795 ||
16023 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57762 ||
16024 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57766 ||
16025 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57782 ||
16026 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57786)
16027 reg = TG3PCI_GEN15_PRODID_ASICREV;
16028 else
16029 reg = TG3PCI_PRODID_ASICREV;
16030
16031 pci_read_config_dword(tp->pdev, reg, &tp->pci_chip_rev_id);
16032 }
16033
16034 /* Wrong chip ID in 5752 A0. This code can be removed later
16035 * as A0 is not in production.
16036 */
4153577a 16037 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5752_A0_HW)
42b123b1
MC		 16038 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
16039
4153577a 16040 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5717_C0)
79d49695
MC		 16041 tp->pci_chip_rev_id = CHIPREV_ID_5720_A0;
16042
4153577a
JP		 16043 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
16044 tg3_asic_rev(tp) == ASIC_REV_5719 ||
16045 tg3_asic_rev(tp) == ASIC_REV_5720)
42b123b1
MC		 16046 tg3_flag_set(tp, 5717_PLUS);
16047
4153577a
JP		 16048 if (tg3_asic_rev(tp) == ASIC_REV_57765 ||
16049 tg3_asic_rev(tp) == ASIC_REV_57766)
42b123b1
MC		 16050 tg3_flag_set(tp, 57765_CLASS);
16051
c65a17f4 16052 if (tg3_flag(tp, 57765_CLASS) || tg3_flag(tp, 5717_PLUS) ||
4153577a 16053 tg3_asic_rev(tp) == ASIC_REV_5762)
42b123b1
MC		 16054 tg3_flag_set(tp, 57765_PLUS);
16055
16056 /* Intentionally exclude ASIC_REV_5906 */
4153577a
JP		 16057 if (tg3_asic_rev(tp) == ASIC_REV_5755 ||
16058 tg3_asic_rev(tp) == ASIC_REV_5787 ||
16059 tg3_asic_rev(tp) == ASIC_REV_5784 ||
16060 tg3_asic_rev(tp) == ASIC_REV_5761 ||
16061 tg3_asic_rev(tp) == ASIC_REV_5785 ||
16062 tg3_asic_rev(tp) == ASIC_REV_57780 ||
42b123b1
MC		 16063 tg3_flag(tp, 57765_PLUS))
16064 tg3_flag_set(tp, 5755_PLUS);
16065
4153577a
JP		 16066 if (tg3_asic_rev(tp) == ASIC_REV_5780 ||
16067 tg3_asic_rev(tp) == ASIC_REV_5714)
42b123b1
MC		 16068 tg3_flag_set(tp, 5780_CLASS);
16069
4153577a
JP		 16070 if (tg3_asic_rev(tp) == ASIC_REV_5750 ||
16071 tg3_asic_rev(tp) == ASIC_REV_5752 ||
16072 tg3_asic_rev(tp) == ASIC_REV_5906 ||
42b123b1
MC		 16073 tg3_flag(tp, 5755_PLUS) ||
16074 tg3_flag(tp, 5780_CLASS))
16075 tg3_flag_set(tp, 5750_PLUS);
16076
4153577a 16077 if (tg3_asic_rev(tp) == ASIC_REV_5705 ||
42b123b1
MC		 16078 tg3_flag(tp, 5750_PLUS))
16079 tg3_flag_set(tp, 5705_PLUS);
16080}
16081
3d567e0e
NNS		 16082static bool tg3_10_100_only_device(struct tg3 *tp,
16083 const struct pci_device_id *ent)
16084{
16085 u32 grc_misc_cfg = tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK;
16086
4153577a
JP		 16087 if ((tg3_asic_rev(tp) == ASIC_REV_5703 &&
16088 (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
3d567e0e
NNS		 16089 (tp->phy_flags & TG3_PHYFLG_IS_FET))
16090 return true;
16091
16092 if (ent->driver_data & TG3_DRV_DATA_FLAG_10_100_ONLY) {
4153577a 16093 if (tg3_asic_rev(tp) == ASIC_REV_5705) {
3d567e0e
NNS		 16094 if (ent->driver_data & TG3_DRV_DATA_FLAG_5705_10_100)
16095 return true;
16096 } else {
16097 return true;
16098 }
16099 }
16100
16101 return false;
16102}
16103
1dd06ae8 16104static int tg3_get_invariants(struct tg3 *tp, const struct pci_device_id *ent)
1da177e4 16105{
1da177e4 16106 u32 misc_ctrl_reg;
1da177e4
LT		 16107 u32 pci_state_reg, grc_misc_cfg;
16108 u32 val;
16109 u16 pci_cmd;
5e7dfd0f 16110 int err;
1da177e4 16111
1da177e4
LT		 16112 /* Force memory write invalidate off. If we leave it on,
16113 * then on 5700_BX chips we have to enable a workaround.
16114 * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
16115 * to match the cacheline size. The Broadcom driver have this
16116 * workaround but turns MWI off all the times so never uses
16117 * it. This seems to suggest that the workaround is insufficient.
16118 */
16119 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
16120 pci_cmd &= ~PCI_COMMAND_INVALIDATE;
16121 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
16122
16821285
MC		 16123 /* Important! -- Make sure register accesses are byteswapped
16124 * correctly. Also, for those chips that require it, make
16125 * sure that indirect register accesses are enabled before
16126 * the first operation.
1da177e4
LT		 16127 */
16128 pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
16129 &misc_ctrl_reg);
16821285
MC		 16130 tp->misc_host_ctrl |= (misc_ctrl_reg &
16131 MISC_HOST_CTRL_CHIPREV);
16132 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
16133 tp->misc_host_ctrl);
1da177e4 16134
42b123b1 16135 tg3_detect_asic_rev(tp, misc_ctrl_reg);
ff645bec 16136
6892914f
MC		 16137 /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
16138 * we need to disable memory and use config. cycles
16139 * only to access all registers. The 5702/03 chips
16140 * can mistakenly decode the special cycles from the
16141 * ICH chipsets as memory write cycles, causing corruption
16142 * of register and memory space. Only certain ICH bridges
16143 * will drive special cycles with non-zero data during the
16144 * address phase which can fall within the 5703's address
16145 * range. This is not an ICH bug as the PCI spec allows
16146 * non-zero address during special cycles. However, only
16147 * these ICH bridges are known to drive non-zero addresses
16148 * during special cycles.
16149 *
16150 * Since special cycles do not cross PCI bridges, we only
16151 * enable this workaround if the 5703 is on the secondary
16152 * bus of these ICH bridges.
16153 */
4153577a
JP		 16154 if ((tg3_chip_rev_id(tp) == CHIPREV_ID_5703_A1) ||
16155 (tg3_chip_rev_id(tp) == CHIPREV_ID_5703_A2)) {
6892914f
MC		 16156 static struct tg3_dev_id {
16157 u32 vendor;
16158 u32 device;
16159 u32 rev;
16160 } ich_chipsets[] = {
16161 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8,
16162 PCI_ANY_ID },
16163 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8,
16164 PCI_ANY_ID },
16165 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11,
16166 0xa },
16167 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6,
16168 PCI_ANY_ID },
16169 { },
16170 };
16171 struct tg3_dev_id *pci_id = &ich_chipsets[0];
16172 struct pci_dev *bridge = NULL;
16173
16174 while (pci_id->vendor != 0) {
16175 bridge = pci_get_device(pci_id->vendor, pci_id->device,
16176 bridge);
16177 if (!bridge) {
16178 pci_id++;
16179 continue;
16180 }
16181 if (pci_id->rev != PCI_ANY_ID) {
44c10138 16182 if (bridge->revision > pci_id->rev)
6892914f
MC		 16183 continue;
16184 }
16185 if (bridge->subordinate &&
16186 (bridge->subordinate->number ==
16187 tp->pdev->bus->number)) {
63c3a66f 16188 tg3_flag_set(tp, ICH_WORKAROUND);
6892914f
MC		 16189 pci_dev_put(bridge);
16190 break;
16191 }
16192 }
16193 }
16194
4153577a 16195 if (tg3_asic_rev(tp) == ASIC_REV_5701) {
41588ba1
MC		 16196 static struct tg3_dev_id {
16197 u32 vendor;
16198 u32 device;
16199 } bridge_chipsets[] = {
16200 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0 },
16201 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1 },
16202 { },
16203 };
16204 struct tg3_dev_id *pci_id = &bridge_chipsets[0];
16205 struct pci_dev *bridge = NULL;
16206
16207 while (pci_id->vendor != 0) {
16208 bridge = pci_get_device(pci_id->vendor,
16209 pci_id->device,
16210 bridge);
16211 if (!bridge) {
16212 pci_id++;
16213 continue;
16214 }
16215 if (bridge->subordinate &&
16216 (bridge->subordinate->number <=
16217 tp->pdev->bus->number) &&
b918c62e 16218 (bridge->subordinate->busn_res.end >=
41588ba1 16219 tp->pdev->bus->number)) {
63c3a66f 16220 tg3_flag_set(tp, 5701_DMA_BUG);
41588ba1
MC		 16221 pci_dev_put(bridge);
16222 break;
16223 }
16224 }
16225 }
16226
4a29cc2e
MC		 16227 /* The EPB bridge inside 5714, 5715, and 5780 cannot support
16228 * DMA addresses > 40-bit. This bridge may have other additional
16229 * 57xx devices behind it in some 4-port NIC designs for example.
16230 * Any tg3 device found behind the bridge will also need the 40-bit
16231 * DMA workaround.
16232 */
42b123b1 16233 if (tg3_flag(tp, 5780_CLASS)) {
63c3a66f 16234 tg3_flag_set(tp, 40BIT_DMA_BUG);
0f847584 16235 tp->msi_cap = tp->pdev->msi_cap;
859a5887 16236 } else {
4a29cc2e
MC		 16237 struct pci_dev *bridge = NULL;
16238
16239 do {
16240 bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
16241 PCI_DEVICE_ID_SERVERWORKS_EPB,
16242 bridge);
16243 if (bridge && bridge->subordinate &&
16244 (bridge->subordinate->number <=
16245 tp->pdev->bus->number) &&
b918c62e 16246 (bridge->subordinate->busn_res.end >=
4a29cc2e 16247 tp->pdev->bus->number)) {
63c3a66f 16248 tg3_flag_set(tp, 40BIT_DMA_BUG);
4a29cc2e
MC		 16249 pci_dev_put(bridge);
16250 break;
16251 }
16252 } while (bridge);
16253 }
4cf78e4f 16254
4153577a
JP		 16255 if (tg3_asic_rev(tp) == ASIC_REV_5704 ||
16256 tg3_asic_rev(tp) == ASIC_REV_5714)
7544b097
MC		 16257 tp->pdev_peer = tg3_find_peer(tp);
16258
507399f1 16259 /* Determine TSO capabilities */
4153577a 16260 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5719_A0)
4d163b75 16261 ; /* Do nothing. HW bug. */
63c3a66f
JP		 16262 else if (tg3_flag(tp, 57765_PLUS))
16263 tg3_flag_set(tp, HW_TSO_3);
16264 else if (tg3_flag(tp, 5755_PLUS) ||
4153577a 16265 tg3_asic_rev(tp) == ASIC_REV_5906)
63c3a66f
JP		 16266 tg3_flag_set(tp, HW_TSO_2);
16267 else if (tg3_flag(tp, 5750_PLUS)) {
16268 tg3_flag_set(tp, HW_TSO_1);
16269 tg3_flag_set(tp, TSO_BUG);
4153577a
JP		 16270 if (tg3_asic_rev(tp) == ASIC_REV_5750 &&
16271 tg3_chip_rev_id(tp) >= CHIPREV_ID_5750_C2)
63c3a66f 16272 tg3_flag_clear(tp, TSO_BUG);
4153577a
JP		 16273 } else if (tg3_asic_rev(tp) != ASIC_REV_5700 &&
16274 tg3_asic_rev(tp) != ASIC_REV_5701 &&
16275 tg3_chip_rev_id(tp) != CHIPREV_ID_5705_A0) {
1caf13eb
MC		 16276 tg3_flag_set(tp, FW_TSO);
16277 tg3_flag_set(tp, TSO_BUG);
4153577a 16278 if (tg3_asic_rev(tp) == ASIC_REV_5705)
507399f1
MC		 16279 tp->fw_needed = FIRMWARE_TG3TSO5;
16280 else
16281 tp->fw_needed = FIRMWARE_TG3TSO;
16282 }
16283
dabc5c67 16284 /* Selectively allow TSO based on operating conditions */
6ff6f81d
MC		 16285 if (tg3_flag(tp, HW_TSO_1) ||
16286 tg3_flag(tp, HW_TSO_2) ||
16287 tg3_flag(tp, HW_TSO_3) ||
1caf13eb 16288 tg3_flag(tp, FW_TSO)) {
cf9ecf4b
MC		 16289 /* For firmware TSO, assume ASF is disabled.
16290 * We'll disable TSO later if we discover ASF
16291 * is enabled in tg3_get_eeprom_hw_cfg().
16292 */
dabc5c67 16293 tg3_flag_set(tp, TSO_CAPABLE);
cf9ecf4b 16294 } else {
dabc5c67
MC		 16295 tg3_flag_clear(tp, TSO_CAPABLE);
16296 tg3_flag_clear(tp, TSO_BUG);
16297 tp->fw_needed = NULL;
16298 }
16299
4153577a 16300 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0)
dabc5c67
MC		 16301 tp->fw_needed = FIRMWARE_TG3;
16302
c4dab506
NS		 16303 if (tg3_asic_rev(tp) == ASIC_REV_57766)
16304 tp->fw_needed = FIRMWARE_TG357766;
16305
507399f1
MC		 16306 tp->irq_max = 1;
16307
63c3a66f
JP		 16308 if (tg3_flag(tp, 5750_PLUS)) {
16309 tg3_flag_set(tp, SUPPORT_MSI);
4153577a
JP		 16310 if (tg3_chip_rev(tp) == CHIPREV_5750_AX ||
16311 tg3_chip_rev(tp) == CHIPREV_5750_BX ||
16312 (tg3_asic_rev(tp) == ASIC_REV_5714 &&
16313 tg3_chip_rev_id(tp) <= CHIPREV_ID_5714_A2 &&
7544b097 16314 tp->pdev_peer == tp->pdev))
63c3a66f 16315 tg3_flag_clear(tp, SUPPORT_MSI);
7544b097 16316
63c3a66f 16317 if (tg3_flag(tp, 5755_PLUS) ||
4153577a 16318 tg3_asic_rev(tp) == ASIC_REV_5906) {
63c3a66f 16319 tg3_flag_set(tp, 1SHOT_MSI);
52c0fd83 16320 }
4f125f42 16321
63c3a66f
JP		 16322 if (tg3_flag(tp, 57765_PLUS)) {
16323 tg3_flag_set(tp, SUPPORT_MSIX);
507399f1
MC		 16324 tp->irq_max = TG3_IRQ_MAX_VECS;
16325 }
f6eb9b1f 16326 }
0e1406dd 16327
9102426a
MC		 16328 tp->txq_max = 1;
16329 tp->rxq_max = 1;
16330 if (tp->irq_max > 1) {
16331 tp->rxq_max = TG3_RSS_MAX_NUM_QS;
16332 tg3_rss_init_dflt_indir_tbl(tp, TG3_RSS_MAX_NUM_QS);
16333
4153577a
JP		 16334 if (tg3_asic_rev(tp) == ASIC_REV_5719 ||
16335 tg3_asic_rev(tp) == ASIC_REV_5720)
9102426a
MC		 16336 tp->txq_max = tp->irq_max - 1;
16337 }
16338
b7abee6e 16339 if (tg3_flag(tp, 5755_PLUS) ||
4153577a 16340 tg3_asic_rev(tp) == ASIC_REV_5906)
63c3a66f 16341 tg3_flag_set(tp, SHORT_DMA_BUG);
f6eb9b1f 16342
4153577a 16343 if (tg3_asic_rev(tp) == ASIC_REV_5719)
a4cb428d 16344 tp->dma_limit = TG3_TX_BD_DMA_MAX_4K;
e31aa987 16345
4153577a
JP		 16346 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
16347 tg3_asic_rev(tp) == ASIC_REV_5719 ||
16348 tg3_asic_rev(tp) == ASIC_REV_5720 ||
16349 tg3_asic_rev(tp) == ASIC_REV_5762)
63c3a66f 16350 tg3_flag_set(tp, LRG_PROD_RING_CAP);
de9f5230 16351
63c3a66f 16352 if (tg3_flag(tp, 57765_PLUS) &&
4153577a 16353 tg3_chip_rev_id(tp) != CHIPREV_ID_5719_A0)
63c3a66f 16354 tg3_flag_set(tp, USE_JUMBO_BDFLAG);
b703df6f 16355
63c3a66f
JP		 16356 if (!tg3_flag(tp, 5705_PLUS) ||
16357 tg3_flag(tp, 5780_CLASS) ||
16358 tg3_flag(tp, USE_JUMBO_BDFLAG))
16359 tg3_flag_set(tp, JUMBO_CAPABLE);
0f893dc6 16360
52f4490c
MC		 16361 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
16362 &pci_state_reg);
16363
708ebb3a 16364 if (pci_is_pcie(tp->pdev)) {
5e7dfd0f
MC		 16365 u16 lnkctl;
16366
63c3a66f 16367 tg3_flag_set(tp, PCI_EXPRESS);
5f5c51e3 16368
0f49bfbd 16369 pcie_capability_read_word(tp->pdev, PCI_EXP_LNKCTL, &lnkctl);
5e7dfd0f 16370 if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN) {
4153577a 16371 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
63c3a66f 16372 tg3_flag_clear(tp, HW_TSO_2);
dabc5c67 16373 tg3_flag_clear(tp, TSO_CAPABLE);
7196cd6c 16374 }
4153577a
JP		 16375 if (tg3_asic_rev(tp) == ASIC_REV_5784 ||
16376 tg3_asic_rev(tp) == ASIC_REV_5761 ||
16377 tg3_chip_rev_id(tp) == CHIPREV_ID_57780_A0 ||
16378 tg3_chip_rev_id(tp) == CHIPREV_ID_57780_A1)
63c3a66f 16379 tg3_flag_set(tp, CLKREQ_BUG);
4153577a 16380 } else if (tg3_chip_rev_id(tp) == CHIPREV_ID_5717_A0) {
63c3a66f 16381 tg3_flag_set(tp, L1PLLPD_EN);
c7835a77 16382 }
4153577a 16383 } else if (tg3_asic_rev(tp) == ASIC_REV_5785) {
708ebb3a
JM		 16384 /* BCM5785 devices are effectively PCIe devices, and should
16385 * follow PCIe codepaths, but do not have a PCIe capabilities
16386 * section.
93a700a9 16387 */
63c3a66f
JP		 16388 tg3_flag_set(tp, PCI_EXPRESS);
16389 } else if (!tg3_flag(tp, 5705_PLUS) ||
16390 tg3_flag(tp, 5780_CLASS)) {
52f4490c
MC		 16391 tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX);
16392 if (!tp->pcix_cap) {
2445e461
MC		 16393 dev_err(&tp->pdev->dev,
16394 "Cannot find PCI-X capability, aborting\n");
52f4490c
MC		 16395 return -EIO;
16396 }
16397
16398 if (!(pci_state_reg & PCISTATE_CONV_PCI_MODE))
63c3a66f 16399 tg3_flag_set(tp, PCIX_MODE);
52f4490c 16400 }
1da177e4 16401
399de50b
MC		 16402 /* If we have an AMD 762 or VIA K8T800 chipset, write
16403 * reordering to the mailbox registers done by the host
16404 * controller can cause major troubles. We read back from
16405 * every mailbox register write to force the writes to be
16406 * posted to the chip in order.
16407 */
4143470c 16408 if (pci_dev_present(tg3_write_reorder_chipsets) &&
63c3a66f
JP		 16409 !tg3_flag(tp, PCI_EXPRESS))
16410 tg3_flag_set(tp, MBOX_WRITE_REORDER);
399de50b 16411
69fc4053
MC		 16412 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
16413 &tp->pci_cacheline_sz);
16414 pci_read_config_byte(tp->pdev, PCI_LATENCY_TIMER,
16415 &tp->pci_lat_timer);
4153577a 16416 if (tg3_asic_rev(tp) == ASIC_REV_5703 &&
1da177e4
LT		 16417 tp->pci_lat_timer < 64) {
16418 tp->pci_lat_timer = 64;
69fc4053
MC		 16419 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
16420 tp->pci_lat_timer);
1da177e4
LT		 16421 }
16422
16821285
MC		 16423 /* Important! -- It is critical that the PCI-X hw workaround
16424 * situation is decided before the first MMIO register access.
16425 */
4153577a 16426 if (tg3_chip_rev(tp) == CHIPREV_5700_BX) {
52f4490c
MC		 16427 /* 5700 BX chips need to have their TX producer index
16428 * mailboxes written twice to workaround a bug.
16429 */
63c3a66f 16430 tg3_flag_set(tp, TXD_MBOX_HWBUG);
1da177e4 16431
52f4490c 16432 /* If we are in PCI-X mode, enable register write workaround.
1da177e4
LT		 16433 *
16434 * The workaround is to use indirect register accesses
16435 * for all chip writes not to mailbox registers.
16436 */
63c3a66f 16437 if (tg3_flag(tp, PCIX_MODE)) {
1da177e4 16438 u32 pm_reg;
1da177e4 16439
63c3a66f 16440 tg3_flag_set(tp, PCIX_TARGET_HWBUG);
1da177e4
LT		 16441
16442 /* The chip can have it's power management PCI config
16443 * space registers clobbered due to this bug.
16444 * So explicitly force the chip into D0 here.
16445 */
9974a356 16446 pci_read_config_dword(tp->pdev,
0319f30e 16447 tp->pdev->pm_cap + PCI_PM_CTRL,
1da177e4
LT		 16448 &pm_reg);
16449 pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
16450 pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
9974a356 16451 pci_write_config_dword(tp->pdev,
0319f30e 16452 tp->pdev->pm_cap + PCI_PM_CTRL,
1da177e4
LT		 16453 pm_reg);
16454
16455 /* Also, force SERR#/PERR# in PCI command. */
16456 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
16457 pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
16458 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
16459 }
16460 }
16461
1da177e4 16462 if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
63c3a66f 16463 tg3_flag_set(tp, PCI_HIGH_SPEED);
1da177e4 16464 if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
63c3a66f 16465 tg3_flag_set(tp, PCI_32BIT);
1da177e4
LT		 16466
16467 /* Chip-specific fixup from Broadcom driver */
4153577a 16468 if ((tg3_chip_rev_id(tp) == CHIPREV_ID_5704_A0) &&
1da177e4
LT		 16469 (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
16470 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
16471 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
16472 }
16473
1ee582d8 16474 /* Default fast path register access methods */
20094930 16475 tp->read32 = tg3_read32;
1ee582d8 16476 tp->write32 = tg3_write32;
09ee929c 16477 tp->read32_mbox = tg3_read32;
20094930 16478 tp->write32_mbox = tg3_write32;
1ee582d8
MC		 16479 tp->write32_tx_mbox = tg3_write32;
16480 tp->write32_rx_mbox = tg3_write32;
16481
16482 /* Various workaround register access methods */
63c3a66f 16483 if (tg3_flag(tp, PCIX_TARGET_HWBUG))
1ee582d8 16484 tp->write32 = tg3_write_indirect_reg32;
4153577a 16485 else if (tg3_asic_rev(tp) == ASIC_REV_5701 ||
63c3a66f 16486 (tg3_flag(tp, PCI_EXPRESS) &&
4153577a 16487 tg3_chip_rev_id(tp) == CHIPREV_ID_5750_A0)) {
98efd8a6
MC		 16488 /*
16489 * Back to back register writes can cause problems on these
16490 * chips, the workaround is to read back all reg writes
16491 * except those to mailbox regs.
16492 *
16493 * See tg3_write_indirect_reg32().
16494 */
1ee582d8 16495 tp->write32 = tg3_write_flush_reg32;
98efd8a6
MC		 16496 }
16497
63c3a66f 16498 if (tg3_flag(tp, TXD_MBOX_HWBUG) || tg3_flag(tp, MBOX_WRITE_REORDER)) {
1ee582d8 16499 tp->write32_tx_mbox = tg3_write32_tx_mbox;
63c3a66f 16500 if (tg3_flag(tp, MBOX_WRITE_REORDER))
1ee582d8
MC		 16501 tp->write32_rx_mbox = tg3_write_flush_reg32;
16502 }
20094930 16503
63c3a66f 16504 if (tg3_flag(tp, ICH_WORKAROUND)) {
6892914f
MC		 16505 tp->read32 = tg3_read_indirect_reg32;
16506 tp->write32 = tg3_write_indirect_reg32;
16507 tp->read32_mbox = tg3_read_indirect_mbox;
16508 tp->write32_mbox = tg3_write_indirect_mbox;
16509 tp->write32_tx_mbox = tg3_write_indirect_mbox;
16510 tp->write32_rx_mbox = tg3_write_indirect_mbox;
16511
16512 iounmap(tp->regs);
22abe310 16513 tp->regs = NULL;
6892914f
MC		 16514
16515 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
16516 pci_cmd &= ~PCI_COMMAND_MEMORY;
16517 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
16518 }
4153577a 16519 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
b5d3772c
MC		 16520 tp->read32_mbox = tg3_read32_mbox_5906;
16521 tp->write32_mbox = tg3_write32_mbox_5906;
16522 tp->write32_tx_mbox = tg3_write32_mbox_5906;
16523 tp->write32_rx_mbox = tg3_write32_mbox_5906;
16524 }
6892914f 16525
bbadf503 16526 if (tp->write32 == tg3_write_indirect_reg32 ||
63c3a66f 16527 (tg3_flag(tp, PCIX_MODE) &&
4153577a
JP		 16528 (tg3_asic_rev(tp) == ASIC_REV_5700 ||
16529 tg3_asic_rev(tp) == ASIC_REV_5701)))
63c3a66f 16530 tg3_flag_set(tp, SRAM_USE_CONFIG);
bbadf503 16531
16821285
MC		 16532 /* The memory arbiter has to be enabled in order for SRAM accesses
16533 * to succeed. Normally on powerup the tg3 chip firmware will make
16534 * sure it is enabled, but other entities such as system netboot
16535 * code might disable it.
16536 */
16537 val = tr32(MEMARB_MODE);
16538 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
16539
9dc5e342 16540 tp->pci_fn = PCI_FUNC(tp->pdev->devfn) & 3;
4153577a 16541 if (tg3_asic_rev(tp) == ASIC_REV_5704 ||
9dc5e342
MC		 16542 tg3_flag(tp, 5780_CLASS)) {
16543 if (tg3_flag(tp, PCIX_MODE)) {
16544 pci_read_config_dword(tp->pdev,
16545 tp->pcix_cap + PCI_X_STATUS,
16546 &val);
16547 tp->pci_fn = val & 0x7;
16548 }
4153577a
JP		 16549 } else if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
16550 tg3_asic_rev(tp) == ASIC_REV_5719 ||
16551 tg3_asic_rev(tp) == ASIC_REV_5720) {
9dc5e342 16552 tg3_read_mem(tp, NIC_SRAM_CPMU_STATUS, &val);
857001f0
MC		 16553 if ((val & NIC_SRAM_CPMUSTAT_SIG_MSK) != NIC_SRAM_CPMUSTAT_SIG)
16554 val = tr32(TG3_CPMU_STATUS);
16555
4153577a 16556 if (tg3_asic_rev(tp) == ASIC_REV_5717)
857001f0
MC		 16557 tp->pci_fn = (val & TG3_CPMU_STATUS_FMSK_5717) ? 1 : 0;
16558 else
9dc5e342
MC		 16559 tp->pci_fn = (val & TG3_CPMU_STATUS_FMSK_5719) >>
16560 TG3_CPMU_STATUS_FSHFT_5719;
69f11c99
MC		 16561 }
16562
7e6c63f0
HM		 16563 if (tg3_flag(tp, FLUSH_POSTED_WRITES)) {
16564 tp->write32_tx_mbox = tg3_write_flush_reg32;
16565 tp->write32_rx_mbox = tg3_write_flush_reg32;
16566 }
16567
7d0c41ef 16568 /* Get eeprom hw config before calling tg3_set_power_state().
63c3a66f 16569 * In particular, the TG3_FLAG_IS_NIC flag must be
7d0c41ef
MC		 16570 * determined before calling tg3_set_power_state() so that
16571 * we know whether or not to switch out of Vaux power.
16572 * When the flag is set, it means that GPIO1 is used for eeprom
16573 * write protect and also implies that it is a LOM where GPIOs
16574 * are not used to switch power.
6aa20a22 16575 */
7d0c41ef
MC		 16576 tg3_get_eeprom_hw_cfg(tp);
16577
1caf13eb 16578 if (tg3_flag(tp, FW_TSO) && tg3_flag(tp, ENABLE_ASF)) {
cf9ecf4b
MC		 16579 tg3_flag_clear(tp, TSO_CAPABLE);
16580 tg3_flag_clear(tp, TSO_BUG);
16581 tp->fw_needed = NULL;
16582 }
16583
63c3a66f 16584 if (tg3_flag(tp, ENABLE_APE)) {
0d3031d9
MC		 16585 /* Allow reads and writes to the
16586 * APE register and memory space.
16587 */
16588 pci_state_reg |= PCISTATE_ALLOW_APE_CTLSPC_WR |
f92d9dc1
MC		 16589 PCISTATE_ALLOW_APE_SHMEM_WR |
16590 PCISTATE_ALLOW_APE_PSPACE_WR;
0d3031d9
MC		 16591 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE,
16592 pci_state_reg);
c9cab24e
MC		 16593
16594 tg3_ape_lock_init(tp);
0d3031d9
MC		 16595 }
16596
16821285
MC		 16597 /* Set up tp->grc_local_ctrl before calling
16598 * tg3_pwrsrc_switch_to_vmain(). GPIO1 driven high
16599 * will bring 5700's external PHY out of reset.
314fba34
MC		 16600 * It is also used as eeprom write protect on LOMs.
16601 */
16602 tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
4153577a 16603 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
63c3a66f 16604 tg3_flag(tp, EEPROM_WRITE_PROT))
314fba34
MC		 16605 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
16606 GRC_LCLCTRL_GPIO_OUTPUT1);
3e7d83bc
MC		 16607 /* Unused GPIO3 must be driven as output on 5752 because there
16608 * are no pull-up resistors on unused GPIO pins.
16609 */
4153577a 16610 else if (tg3_asic_rev(tp) == ASIC_REV_5752)
3e7d83bc 16611 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
314fba34 16612
4153577a
JP		 16613 if (tg3_asic_rev(tp) == ASIC_REV_5755 ||
16614 tg3_asic_rev(tp) == ASIC_REV_57780 ||
55086ad9 16615 tg3_flag(tp, 57765_CLASS))
af36e6b6
MC		 16616 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
16617
8d519ab2
MC		 16618 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
16619 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
5f0c4a3c
MC		 16620 /* Turn off the debug UART. */
16621 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
63c3a66f 16622 if (tg3_flag(tp, IS_NIC))
5f0c4a3c
MC		 16623 /* Keep VMain power. */
16624 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
16625 GRC_LCLCTRL_GPIO_OUTPUT0;
16626 }
16627
4153577a 16628 if (tg3_asic_rev(tp) == ASIC_REV_5762)
c86a8560
MC		 16629 tp->grc_local_ctrl |=
16630 tr32(GRC_LOCAL_CTRL) & GRC_LCLCTRL_GPIO_UART_SEL;
16631
16821285
MC		 16632 /* Switch out of Vaux if it is a NIC */
16633 tg3_pwrsrc_switch_to_vmain(tp);
1da177e4 16634
1da177e4
LT		 16635 /* Derive initial jumbo mode from MTU assigned in
16636 * ether_setup() via the alloc_etherdev() call
16637 */
63c3a66f
JP		 16638 if (tp->dev->mtu > ETH_DATA_LEN && !tg3_flag(tp, 5780_CLASS))
16639 tg3_flag_set(tp, JUMBO_RING_ENABLE);
1da177e4
LT		 16640
16641 /* Determine WakeOnLan speed to use. */
4153577a
JP		 16642 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
16643 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0 ||
16644 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B0 ||
16645 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B2) {
63c3a66f 16646 tg3_flag_clear(tp, WOL_SPEED_100MB);
1da177e4 16647 } else {
63c3a66f 16648 tg3_flag_set(tp, WOL_SPEED_100MB);
1da177e4
LT		 16649 }
16650
4153577a 16651 if (tg3_asic_rev(tp) == ASIC_REV_5906)
f07e9af3 16652 tp->phy_flags |= TG3_PHYFLG_IS_FET;
7f97a4bd 16653
1da177e4 16654 /* A few boards don't want Ethernet@WireSpeed phy feature */
4153577a
JP		 16655 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
16656 (tg3_asic_rev(tp) == ASIC_REV_5705 &&
16657 (tg3_chip_rev_id(tp) != CHIPREV_ID_5705_A0) &&
16658 (tg3_chip_rev_id(tp) != CHIPREV_ID_5705_A1)) ||
f07e9af3
MC		 16659 (tp->phy_flags & TG3_PHYFLG_IS_FET) ||
16660 (tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
16661 tp->phy_flags |= TG3_PHYFLG_NO_ETH_WIRE_SPEED;
1da177e4 16662
4153577a
JP		 16663 if (tg3_chip_rev(tp) == CHIPREV_5703_AX ||
16664 tg3_chip_rev(tp) == CHIPREV_5704_AX)
f07e9af3 16665 tp->phy_flags |= TG3_PHYFLG_ADC_BUG;
4153577a 16666 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5704_A0)
f07e9af3 16667 tp->phy_flags |= TG3_PHYFLG_5704_A0_BUG;
1da177e4 16668
63c3a66f 16669 if (tg3_flag(tp, 5705_PLUS) &&
f07e9af3 16670 !(tp->phy_flags & TG3_PHYFLG_IS_FET) &&
4153577a
JP		 16671 tg3_asic_rev(tp) != ASIC_REV_5785 &&
16672 tg3_asic_rev(tp) != ASIC_REV_57780 &&
63c3a66f 16673 !tg3_flag(tp, 57765_PLUS)) {
4153577a
JP		 16674 if (tg3_asic_rev(tp) == ASIC_REV_5755 ||
16675 tg3_asic_rev(tp) == ASIC_REV_5787 ||
16676 tg3_asic_rev(tp) == ASIC_REV_5784 ||
16677 tg3_asic_rev(tp) == ASIC_REV_5761) {
d4011ada
MC		 16678 if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 &&
16679 tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722)
f07e9af3 16680 tp->phy_flags |= TG3_PHYFLG_JITTER_BUG;
c1d2a196 16681 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M)
f07e9af3 16682 tp->phy_flags |= TG3_PHYFLG_ADJUST_TRIM;
321d32a0 16683 } else
f07e9af3 16684 tp->phy_flags |= TG3_PHYFLG_BER_BUG;
c424cb24 16685 }
1da177e4 16686
4153577a
JP		 16687 if (tg3_asic_rev(tp) == ASIC_REV_5784 &&
16688 tg3_chip_rev(tp) != CHIPREV_5784_AX) {
b2a5c19c
MC		 16689 tp->phy_otp = tg3_read_otp_phycfg(tp);
16690 if (tp->phy_otp == 0)
16691 tp->phy_otp = TG3_OTP_DEFAULT;
16692 }
16693
63c3a66f 16694 if (tg3_flag(tp, CPMU_PRESENT))
8ef21428
MC		 16695 tp->mi_mode = MAC_MI_MODE_500KHZ_CONST;
16696 else
16697 tp->mi_mode = MAC_MI_MODE_BASE;
16698
1da177e4 16699 tp->coalesce_mode = 0;
4153577a
JP		 16700 if (tg3_chip_rev(tp) != CHIPREV_5700_AX &&
16701 tg3_chip_rev(tp) != CHIPREV_5700_BX)
1da177e4
LT		 16702 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
16703
4d958473 16704 /* Set these bits to enable statistics workaround. */
4153577a 16705 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
94962f7f 16706 tg3_asic_rev(tp) == ASIC_REV_5762 ||
4153577a
JP		 16707 tg3_chip_rev_id(tp) == CHIPREV_ID_5719_A0 ||
16708 tg3_chip_rev_id(tp) == CHIPREV_ID_5720_A0) {
4d958473
MC		 16709 tp->coalesce_mode |= HOSTCC_MODE_ATTN;
16710 tp->grc_mode |= GRC_MODE_IRQ_ON_FLOW_ATTN;
16711 }
16712
4153577a
JP		 16713 if (tg3_asic_rev(tp) == ASIC_REV_5785 ||
16714 tg3_asic_rev(tp) == ASIC_REV_57780)
63c3a66f 16715 tg3_flag_set(tp, USE_PHYLIB);
57e6983c 16716
158d7abd
MC		 16717 err = tg3_mdio_init(tp);
16718 if (err)
16719 return err;
1da177e4
LT		 16720
16721 /* Initialize data/descriptor byte/word swapping. */
16722 val = tr32(GRC_MODE);
4153577a
JP		 16723 if (tg3_asic_rev(tp) == ASIC_REV_5720 ||
16724 tg3_asic_rev(tp) == ASIC_REV_5762)
f2096f94
MC		 16725 val &= (GRC_MODE_BYTE_SWAP_B2HRX_DATA |
16726 GRC_MODE_WORD_SWAP_B2HRX_DATA |
16727 GRC_MODE_B2HRX_ENABLE |
16728 GRC_MODE_HTX2B_ENABLE |
16729 GRC_MODE_HOST_STACKUP);
16730 else
16731 val &= GRC_MODE_HOST_STACKUP;
16732
1da177e4
LT		 16733 tw32(GRC_MODE, val | tp->grc_mode);
16734
16735 tg3_switch_clocks(tp);
16736
16737 /* Clear this out for sanity. */
16738 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
16739
388d3335
NG		 16740 /* Clear TG3PCI_REG_BASE_ADDR to prevent hangs. */
16741 tw32(TG3PCI_REG_BASE_ADDR, 0);
16742
1da177e4
LT		 16743 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
16744 &pci_state_reg);
16745 if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
63c3a66f 16746 !tg3_flag(tp, PCIX_TARGET_HWBUG)) {
4153577a
JP		 16747 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0 ||
16748 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B0 ||
16749 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B2 ||
16750 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B5) {
1da177e4
LT		 16751 void __iomem *sram_base;
16752
16753 /* Write some dummy words into the SRAM status block
16754 * area, see if it reads back correctly. If the return
16755 * value is bad, force enable the PCIX workaround.
16756 */
16757 sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
16758
16759 writel(0x00000000, sram_base);
16760 writel(0x00000000, sram_base + 4);
16761 writel(0xffffffff, sram_base + 4);
16762 if (readl(sram_base) != 0x00000000)
63c3a66f 16763 tg3_flag_set(tp, PCIX_TARGET_HWBUG);
1da177e4
LT		 16764 }
16765 }
16766
16767 udelay(50);
16768 tg3_nvram_init(tp);
16769
c4dab506
NS		 16770 /* If the device has an NVRAM, no need to load patch firmware */
16771 if (tg3_asic_rev(tp) == ASIC_REV_57766 &&
16772 !tg3_flag(tp, NO_NVRAM))
16773 tp->fw_needed = NULL;
16774
1da177e4
LT		 16775 grc_misc_cfg = tr32(GRC_MISC_CFG);
16776 grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
16777
4153577a 16778 if (tg3_asic_rev(tp) == ASIC_REV_5705 &&
1da177e4
LT		 16779 (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
16780 grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
63c3a66f 16781 tg3_flag_set(tp, IS_5788);
1da177e4 16782
63c3a66f 16783 if (!tg3_flag(tp, IS_5788) &&
4153577a 16784 tg3_asic_rev(tp) != ASIC_REV_5700)
63c3a66f
JP		 16785 tg3_flag_set(tp, TAGGED_STATUS);
16786 if (tg3_flag(tp, TAGGED_STATUS)) {
fac9b83e
DM		 16787 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
16788 HOSTCC_MODE_CLRTICK_TXBD);
16789
16790 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
16791 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
16792 tp->misc_host_ctrl);
16793 }
16794
3bda1258 16795 /* Preserve the APE MAC_MODE bits */
63c3a66f 16796 if (tg3_flag(tp, ENABLE_APE))
d2394e6b 16797 tp->mac_mode = MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
3bda1258 16798 else
6e01b20b 16799 tp->mac_mode = 0;
3bda1258 16800
3d567e0e 16801 if (tg3_10_100_only_device(tp, ent))
f07e9af3 16802 tp->phy_flags |= TG3_PHYFLG_10_100_ONLY;
1da177e4
LT		 16803
16804 err = tg3_phy_probe(tp);
16805 if (err) {
2445e461 16806 dev_err(&tp->pdev->dev, "phy probe failed, err %d\n", err);
1da177e4 16807 /* ... but do not return immediately ... */
b02fd9e3 16808 tg3_mdio_fini(tp);
1da177e4
LT		 16809 }
16810
184b8904 16811 tg3_read_vpd(tp);
c4e6575c 16812 tg3_read_fw_ver(tp);
1da177e4 16813
f07e9af3
MC		 16814 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
16815 tp->phy_flags &= ~TG3_PHYFLG_USE_MI_INTERRUPT;
1da177e4 16816 } else {
4153577a 16817 if (tg3_asic_rev(tp) == ASIC_REV_5700)
f07e9af3 16818 tp->phy_flags |= TG3_PHYFLG_USE_MI_INTERRUPT;
1da177e4 16819 else
f07e9af3 16820 tp->phy_flags &= ~TG3_PHYFLG_USE_MI_INTERRUPT;
1da177e4
LT		 16821 }
16822
16823 /* 5700 {AX,BX} chips have a broken status block link
16824 * change bit implementation, so we must use the
16825 * status register in those cases.
16826 */
4153577a 16827 if (tg3_asic_rev(tp) == ASIC_REV_5700)
63c3a66f 16828 tg3_flag_set(tp, USE_LINKCHG_REG);
1da177e4 16829 else
63c3a66f 16830 tg3_flag_clear(tp, USE_LINKCHG_REG);
1da177e4
LT		 16831
16832 /* The led_ctrl is set during tg3_phy_probe, here we might
16833 * have to force the link status polling mechanism based
16834 * upon subsystem IDs.
16835 */
16836 if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
4153577a 16837 tg3_asic_rev(tp) == ASIC_REV_5701 &&
f07e9af3
MC		 16838 !(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
16839 tp->phy_flags |= TG3_PHYFLG_USE_MI_INTERRUPT;
63c3a66f 16840 tg3_flag_set(tp, USE_LINKCHG_REG);
1da177e4
LT		 16841 }
16842
16843 /* For all SERDES we poll the MAC status register. */
f07e9af3 16844 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
63c3a66f 16845 tg3_flag_set(tp, POLL_SERDES);
1da177e4 16846 else
63c3a66f 16847 tg3_flag_clear(tp, POLL_SERDES);
1da177e4 16848
1743b83c
NS		 16849 if (tg3_flag(tp, ENABLE_APE) && tg3_flag(tp, ENABLE_ASF))
16850 tg3_flag_set(tp, POLL_CPMU_LINK);
16851
9205fd9c 16852 tp->rx_offset = NET_SKB_PAD + NET_IP_ALIGN;
d2757fc4 16853 tp->rx_copy_thresh = TG3_RX_COPY_THRESHOLD;
4153577a 16854 if (tg3_asic_rev(tp) == ASIC_REV_5701 &&
63c3a66f 16855 tg3_flag(tp, PCIX_MODE)) {
9205fd9c 16856 tp->rx_offset = NET_SKB_PAD;
d2757fc4 16857#ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
9dc7a113 16858 tp->rx_copy_thresh = ~(u16)0;
d2757fc4
MC		 16859#endif
16860 }
1da177e4 16861
2c49a44d
MC		 16862 tp->rx_std_ring_mask = TG3_RX_STD_RING_SIZE(tp) - 1;
16863 tp->rx_jmb_ring_mask = TG3_RX_JMB_RING_SIZE(tp) - 1;
7cb32cf2
MC		 16864 tp->rx_ret_ring_mask = tg3_rx_ret_ring_size(tp) - 1;
16865
2c49a44d 16866 tp->rx_std_max_post = tp->rx_std_ring_mask + 1;
f92905de
MC		 16867
16868 /* Increment the rx prod index on the rx std ring by at most
16869 * 8 for these chips to workaround hw errata.
16870 */
4153577a
JP		 16871 if (tg3_asic_rev(tp) == ASIC_REV_5750 ||
16872 tg3_asic_rev(tp) == ASIC_REV_5752 ||
16873 tg3_asic_rev(tp) == ASIC_REV_5755)
f92905de
MC		 16874 tp->rx_std_max_post = 8;
16875
63c3a66f 16876 if (tg3_flag(tp, ASPM_WORKAROUND))
8ed5d97e
MC		 16877 tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) &
16878 PCIE_PWR_MGMT_L1_THRESH_MSK;
16879
1da177e4
LT		 16880 return err;
16881}
16882
49b6e95f 16883#ifdef CONFIG_SPARC
229b1ad1 16884static int tg3_get_macaddr_sparc(struct tg3 *tp)
1da177e4
LT		 16885{
16886 struct net_device *dev = tp->dev;
16887 struct pci_dev *pdev = tp->pdev;
49b6e95f 16888 struct device_node *dp = pci_device_to_OF_node(pdev);
374d4cac 16889 const unsigned char *addr;
49b6e95f
DM		 16890 int len;
16891
16892 addr = of_get_property(dp, "local-mac-address", &len);
d458cdf7
JP		 16893 if (addr && len == ETH_ALEN) {
16894 memcpy(dev->dev_addr, addr, ETH_ALEN);
49b6e95f 16895 return 0;
1da177e4
LT		 16896 }
16897 return -ENODEV;
16898}
16899
229b1ad1 16900static int tg3_get_default_macaddr_sparc(struct tg3 *tp)
1da177e4
LT		 16901{
16902 struct net_device *dev = tp->dev;
16903
d458cdf7 16904 memcpy(dev->dev_addr, idprom->id_ethaddr, ETH_ALEN);
1da177e4
LT		 16905 return 0;
16906}
16907#endif
16908
229b1ad1 16909static int tg3_get_device_address(struct tg3 *tp)
1da177e4
LT		 16910{
16911 struct net_device *dev = tp->dev;
16912 u32 hi, lo, mac_offset;
008652b3 16913 int addr_ok = 0;
7e6c63f0 16914 int err;
1da177e4 16915
49b6e95f 16916#ifdef CONFIG_SPARC
1da177e4
LT		 16917 if (!tg3_get_macaddr_sparc(tp))
16918 return 0;
16919#endif
16920
7e6c63f0
HM		 16921 if (tg3_flag(tp, IS_SSB_CORE)) {
16922 err = ssb_gige_get_macaddr(tp->pdev, &dev->dev_addr[0]);
16923 if (!err && is_valid_ether_addr(&dev->dev_addr[0]))
16924 return 0;
16925 }
16926
1da177e4 16927 mac_offset = 0x7c;
4153577a 16928 if (tg3_asic_rev(tp) == ASIC_REV_5704 ||
63c3a66f 16929 tg3_flag(tp, 5780_CLASS)) {
1da177e4
LT		 16930 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
16931 mac_offset = 0xcc;
16932 if (tg3_nvram_lock(tp))
16933 tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
16934 else
16935 tg3_nvram_unlock(tp);
63c3a66f 16936 } else if (tg3_flag(tp, 5717_PLUS)) {
69f11c99 16937 if (tp->pci_fn & 1)
a1b950d5 16938 mac_offset = 0xcc;
69f11c99 16939 if (tp->pci_fn > 1)
a50d0796 16940 mac_offset += 0x18c;
4153577a 16941 } else if (tg3_asic_rev(tp) == ASIC_REV_5906)
b5d3772c 16942 mac_offset = 0x10;
1da177e4
LT		 16943
16944 /* First try to get it from MAC address mailbox. */
16945 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
16946 if ((hi >> 16) == 0x484b) {
16947 dev->dev_addr[0] = (hi >> 8) & 0xff;
16948 dev->dev_addr[1] = (hi >> 0) & 0xff;
16949
16950 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
16951 dev->dev_addr[2] = (lo >> 24) & 0xff;
16952 dev->dev_addr[3] = (lo >> 16) & 0xff;
16953 dev->dev_addr[4] = (lo >> 8) & 0xff;
16954 dev->dev_addr[5] = (lo >> 0) & 0xff;
1da177e4 16955
008652b3
MC		 16956 /* Some old bootcode may report a 0 MAC address in SRAM */
16957 addr_ok = is_valid_ether_addr(&dev->dev_addr[0]);
16958 }
16959 if (!addr_ok) {
16960 /* Next, try NVRAM. */
63c3a66f 16961 if (!tg3_flag(tp, NO_NVRAM) &&
df259d8c 16962 !tg3_nvram_read_be32(tp, mac_offset + 0, &hi) &&
6d348f2c 16963 !tg3_nvram_read_be32(tp, mac_offset + 4, &lo)) {
62cedd11
MC		 16964 memcpy(&dev->dev_addr[0], ((char *)&hi) + 2, 2);
16965 memcpy(&dev->dev_addr[2], (char *)&lo, sizeof(lo));
008652b3
MC		 16966 }
16967 /* Finally just fetch it out of the MAC control regs. */
16968 else {
16969 hi = tr32(MAC_ADDR_0_HIGH);
16970 lo = tr32(MAC_ADDR_0_LOW);
16971
16972 dev->dev_addr[5] = lo & 0xff;
16973 dev->dev_addr[4] = (lo >> 8) & 0xff;
16974 dev->dev_addr[3] = (lo >> 16) & 0xff;
16975 dev->dev_addr[2] = (lo >> 24) & 0xff;
16976 dev->dev_addr[1] = hi & 0xff;
16977 dev->dev_addr[0] = (hi >> 8) & 0xff;
16978 }
1da177e4
LT		 16979 }
16980
16981 if (!is_valid_ether_addr(&dev->dev_addr[0])) {
7582a335 16982#ifdef CONFIG_SPARC
1da177e4
LT		 16983 if (!tg3_get_default_macaddr_sparc(tp))
16984 return 0;
16985#endif
16986 return -EINVAL;
16987 }
16988 return 0;
16989}
16990
59e6b434
DM		 16991#define BOUNDARY_SINGLE_CACHELINE 1
16992#define BOUNDARY_MULTI_CACHELINE 2
16993
229b1ad1 16994static u32 tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
59e6b434
DM		 16995{
16996 int cacheline_size;
16997 u8 byte;
16998 int goal;
16999
17000 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
17001 if (byte == 0)
17002 cacheline_size = 1024;
17003 else
17004 cacheline_size = (int) byte * 4;
17005
17006 /* On 5703 and later chips, the boundary bits have no
17007 * effect.
17008 */
4153577a
JP		 17009 if (tg3_asic_rev(tp) != ASIC_REV_5700 &&
17010 tg3_asic_rev(tp) != ASIC_REV_5701 &&
63c3a66f 17011 !tg3_flag(tp, PCI_EXPRESS))
59e6b434
DM		 17012 goto out;
17013
17014#if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
17015 goal = BOUNDARY_MULTI_CACHELINE;
17016#else
17017#if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
17018 goal = BOUNDARY_SINGLE_CACHELINE;
17019#else
17020 goal = 0;
17021#endif
17022#endif
17023
63c3a66f 17024 if (tg3_flag(tp, 57765_PLUS)) {
cbf9ca6c
MC		 17025 val = goal ? 0 : DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
17026 goto out;
17027 }
17028
59e6b434
DM		 17029 if (!goal)
17030 goto out;
17031
17032 /* PCI controllers on most RISC systems tend to disconnect
17033 * when a device tries to burst across a cache-line boundary.
17034 * Therefore, letting tg3 do so just wastes PCI bandwidth.
17035 *
17036 * Unfortunately, for PCI-E there are only limited
17037 * write-side controls for this, and thus for reads
17038 * we will still get the disconnects. We'll also waste
17039 * these PCI cycles for both read and write for chips
17040 * other than 5700 and 5701 which do not implement the
17041 * boundary bits.
17042 */
63c3a66f 17043 if (tg3_flag(tp, PCIX_MODE) && !tg3_flag(tp, PCI_EXPRESS)) {
59e6b434
DM		 17044 switch (cacheline_size) {
17045 case 16:
17046 case 32:
17047 case 64:
17048 case 128:
17049 if (goal == BOUNDARY_SINGLE_CACHELINE) {
17050 val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
17051 DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
17052 } else {
17053 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
17054 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
17055 }
17056 break;
17057
17058 case 256:
17059 val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
17060 DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
17061 break;
17062
17063 default:
17064 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
17065 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
17066 break;
855e1111 17067 }
63c3a66f 17068 } else if (tg3_flag(tp, PCI_EXPRESS)) {
59e6b434
DM		 17069 switch (cacheline_size) {
17070 case 16:
17071 case 32:
17072 case 64:
17073 if (goal == BOUNDARY_SINGLE_CACHELINE) {
17074 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
17075 val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
17076 break;
17077 }
17078 /* fallthrough */
17079 case 128:
17080 default:
17081 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
17082 val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
17083 break;
855e1111 17084 }
59e6b434
DM		 17085 } else {
17086 switch (cacheline_size) {
17087 case 16:
17088 if (goal == BOUNDARY_SINGLE_CACHELINE) {
17089 val |= (DMA_RWCTRL_READ_BNDRY_16 |
17090 DMA_RWCTRL_WRITE_BNDRY_16);
17091 break;
17092 }
17093 /* fallthrough */
17094 case 32:
17095 if (goal == BOUNDARY_SINGLE_CACHELINE) {
17096 val |= (DMA_RWCTRL_READ_BNDRY_32 |
17097 DMA_RWCTRL_WRITE_BNDRY_32);
17098 break;
17099 }
17100 /* fallthrough */
17101 case 64:
17102 if (goal == BOUNDARY_SINGLE_CACHELINE) {
17103 val |= (DMA_RWCTRL_READ_BNDRY_64 |
17104 DMA_RWCTRL_WRITE_BNDRY_64);
17105 break;
17106 }
17107 /* fallthrough */
17108 case 128:
17109 if (goal == BOUNDARY_SINGLE_CACHELINE) {
17110 val |= (DMA_RWCTRL_READ_BNDRY_128 |
17111 DMA_RWCTRL_WRITE_BNDRY_128);
17112 break;
17113 }
17114 /* fallthrough */
17115 case 256:
17116 val |= (DMA_RWCTRL_READ_BNDRY_256 |
17117 DMA_RWCTRL_WRITE_BNDRY_256);
17118 break;
17119 case 512:
17120 val |= (DMA_RWCTRL_READ_BNDRY_512 |
17121 DMA_RWCTRL_WRITE_BNDRY_512);
17122 break;
17123 case 1024:
17124 default:
17125 val |= (DMA_RWCTRL_READ_BNDRY_1024 |
17126 DMA_RWCTRL_WRITE_BNDRY_1024);
17127 break;
855e1111 17128 }
59e6b434
DM		 17129 }
17130
17131out:
17132 return val;
17133}
17134
229b1ad1 17135static int tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma,
953c96e0 17136 int size, bool to_device)
1da177e4
LT		 17137{
17138 struct tg3_internal_buffer_desc test_desc;
17139 u32 sram_dma_descs;
17140 int i, ret;
17141
17142 sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
17143
17144 tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
17145 tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
17146 tw32(RDMAC_STATUS, 0);
17147 tw32(WDMAC_STATUS, 0);
17148
17149 tw32(BUFMGR_MODE, 0);
17150 tw32(FTQ_RESET, 0);
17151
17152 test_desc.addr_hi = ((u64) buf_dma) >> 32;
17153 test_desc.addr_lo = buf_dma & 0xffffffff;
17154 test_desc.nic_mbuf = 0x00002100;
17155 test_desc.len = size;
17156
17157 /*
17158 * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
17159 * the *second* time the tg3 driver was getting loaded after an
17160 * initial scan.
17161 *
17162 * Broadcom tells me:
17163 * ...the DMA engine is connected to the GRC block and a DMA
17164 * reset may affect the GRC block in some unpredictable way...
17165 * The behavior of resets to individual blocks has not been tested.
17166 *
17167 * Broadcom noted the GRC reset will also reset all sub-components.
17168 */
17169 if (to_device) {
17170 test_desc.cqid_sqid = (13 << 8) | 2;
17171
17172 tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
17173 udelay(40);
17174 } else {
17175 test_desc.cqid_sqid = (16 << 8) | 7;
17176
17177 tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
17178 udelay(40);
17179 }
17180 test_desc.flags = 0x00000005;
17181
17182 for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
17183 u32 val;
17184
17185 val = *(((u32 *)&test_desc) + i);
17186 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
17187 sram_dma_descs + (i * sizeof(u32)));
17188 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
17189 }
17190 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
17191
859a5887 17192 if (to_device)
1da177e4 17193 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
859a5887 17194 else
1da177e4 17195 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
1da177e4
LT		 17196
17197 ret = -ENODEV;
17198 for (i = 0; i < 40; i++) {
17199 u32 val;
17200
17201 if (to_device)
17202 val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
17203 else
17204 val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
17205 if ((val & 0xffff) == sram_dma_descs) {
17206 ret = 0;
17207 break;
17208 }
17209
17210 udelay(100);
17211 }
17212
17213 return ret;
17214}
17215
ded7340d 17216#define TEST_BUFFER_SIZE 0x2000
1da177e4 17217
9baa3c34 17218static const struct pci_device_id tg3_dma_wait_state_chipsets[] = {
895950c2
JP		 17219 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
17220 { },
17221};
17222
229b1ad1 17223static int tg3_test_dma(struct tg3 *tp)
1da177e4
LT		 17224{
17225 dma_addr_t buf_dma;
59e6b434 17226 u32 *buf, saved_dma_rwctrl;
cbf9ca6c 17227 int ret = 0;
1da177e4 17228
4bae65c8
MC		 17229 buf = dma_alloc_coherent(&tp->pdev->dev, TEST_BUFFER_SIZE,
17230 &buf_dma, GFP_KERNEL);
1da177e4
LT		 17231 if (!buf) {
17232 ret = -ENOMEM;
17233 goto out_nofree;
17234 }
17235
17236 tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
17237 (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
17238
59e6b434 17239 tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
1da177e4 17240
63c3a66f 17241 if (tg3_flag(tp, 57765_PLUS))
cbf9ca6c
MC		 17242 goto out;
17243
63c3a66f 17244 if (tg3_flag(tp, PCI_EXPRESS)) {
1da177e4
LT		 17245 /* DMA read watermark not used on PCIE */
17246 tp->dma_rwctrl |= 0x00180000;
63c3a66f 17247 } else if (!tg3_flag(tp, PCIX_MODE)) {
4153577a
JP		 17248 if (tg3_asic_rev(tp) == ASIC_REV_5705 ||
17249 tg3_asic_rev(tp) == ASIC_REV_5750)
1da177e4
LT		 17250 tp->dma_rwctrl |= 0x003f0000;
17251 else
17252 tp->dma_rwctrl |= 0x003f000f;
17253 } else {
4153577a
JP		 17254 if (tg3_asic_rev(tp) == ASIC_REV_5703 ||
17255 tg3_asic_rev(tp) == ASIC_REV_5704) {
1da177e4 17256 u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
49afdeb6 17257 u32 read_water = 0x7;
1da177e4 17258
4a29cc2e
MC		 17259 /* If the 5704 is behind the EPB bridge, we can
17260 * do the less restrictive ONE_DMA workaround for
17261 * better performance.
17262 */
63c3a66f 17263 if (tg3_flag(tp, 40BIT_DMA_BUG) &&
4153577a 17264 tg3_asic_rev(tp) == ASIC_REV_5704)
4a29cc2e
MC		 17265 tp->dma_rwctrl |= 0x8000;
17266 else if (ccval == 0x6 || ccval == 0x7)
1da177e4
LT		 17267 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
17268
4153577a 17269 if (tg3_asic_rev(tp) == ASIC_REV_5703)
49afdeb6 17270 read_water = 4;
59e6b434 17271 /* Set bit 23 to enable PCIX hw bug fix */
49afdeb6
MC		 17272 tp->dma_rwctrl |=
17273 (read_water << DMA_RWCTRL_READ_WATER_SHIFT) |
17274 (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
17275 (1 << 23);
4153577a 17276 } else if (tg3_asic_rev(tp) == ASIC_REV_5780) {
4cf78e4f
MC		 17277 /* 5780 always in PCIX mode */
17278 tp->dma_rwctrl |= 0x00144000;
4153577a 17279 } else if (tg3_asic_rev(tp) == ASIC_REV_5714) {
a4e2b347
MC		 17280 /* 5714 always in PCIX mode */
17281 tp->dma_rwctrl |= 0x00148000;
1da177e4
LT		 17282 } else {
17283 tp->dma_rwctrl |= 0x001b000f;
17284 }
17285 }
7e6c63f0
HM		 17286 if (tg3_flag(tp, ONE_DMA_AT_ONCE))
17287 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
1da177e4 17288
4153577a
JP		 17289 if (tg3_asic_rev(tp) == ASIC_REV_5703 ||
17290 tg3_asic_rev(tp) == ASIC_REV_5704)
1da177e4
LT		 17291 tp->dma_rwctrl &= 0xfffffff0;
17292
4153577a
JP		 17293 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
17294 tg3_asic_rev(tp) == ASIC_REV_5701) {
1da177e4
LT		 17295 /* Remove this if it causes problems for some boards. */
17296 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
17297
17298 /* On 5700/5701 chips, we need to set this bit.
17299 * Otherwise the chip will issue cacheline transactions
17300 * to streamable DMA memory with not all the byte
17301 * enables turned on. This is an error on several
17302 * RISC PCI controllers, in particular sparc64.
17303 *
17304 * On 5703/5704 chips, this bit has been reassigned
17305 * a different meaning. In particular, it is used
17306 * on those chips to enable a PCI-X workaround.
17307 */
17308 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
17309 }
17310
17311 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
17312
1da177e4 17313
4153577a
JP		 17314 if (tg3_asic_rev(tp) != ASIC_REV_5700 &&
17315 tg3_asic_rev(tp) != ASIC_REV_5701)
1da177e4
LT		 17316 goto out;
17317
59e6b434
DM		 17318 /* It is best to perform DMA test with maximum write burst size
17319 * to expose the 5700/5701 write DMA bug.
17320 */
17321 saved_dma_rwctrl = tp->dma_rwctrl;
17322 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
17323 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
17324
1da177e4
LT		 17325 while (1) {
17326 u32 *p = buf, i;
17327
17328 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
17329 p[i] = i;
17330
17331 /* Send the buffer to the chip. */
953c96e0 17332 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, true);
1da177e4 17333 if (ret) {
2445e461
MC		 17334 dev_err(&tp->pdev->dev,
17335 "%s: Buffer write failed. err = %d\n",
17336 __func__, ret);
1da177e4
LT		 17337 break;
17338 }
17339
1da177e4 17340 /* Now read it back. */
953c96e0 17341 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, false);
1da177e4 17342 if (ret) {
5129c3a3
MC		 17343 dev_err(&tp->pdev->dev, "%s: Buffer read failed. "
17344 "err = %d\n", __func__, ret);
1da177e4
LT		 17345 break;
17346 }
17347
17348 /* Verify it. */
17349 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
17350 if (p[i] == i)
17351 continue;
17352
59e6b434
DM		 17353 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
17354 DMA_RWCTRL_WRITE_BNDRY_16) {
17355 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
1da177e4
LT		 17356 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
17357 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
17358 break;
17359 } else {
2445e461
MC		 17360 dev_err(&tp->pdev->dev,
17361 "%s: Buffer corrupted on read back! "
17362 "(%d != %d)\n", __func__, p[i], i);
1da177e4
LT		 17363 ret = -ENODEV;
17364 goto out;
17365 }
17366 }
17367
17368 if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
17369 /* Success. */
17370 ret = 0;
17371 break;
17372 }
17373 }
59e6b434
DM		 17374 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
17375 DMA_RWCTRL_WRITE_BNDRY_16) {
17376 /* DMA test passed without adjusting DMA boundary,
6d1cfbab
MC		 17377 * now look for chipsets that are known to expose the
17378 * DMA bug without failing the test.
59e6b434 17379 */
4143470c 17380 if (pci_dev_present(tg3_dma_wait_state_chipsets)) {
6d1cfbab
MC		 17381 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
17382 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
859a5887 17383 } else {
6d1cfbab
MC		 17384 /* Safe to use the calculated DMA boundary. */
17385 tp->dma_rwctrl = saved_dma_rwctrl;
859a5887 17386 }
6d1cfbab 17387
59e6b434
DM		 17388 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
17389 }
1da177e4
LT		 17390
17391out:
4bae65c8 17392 dma_free_coherent(&tp->pdev->dev, TEST_BUFFER_SIZE, buf, buf_dma);
1da177e4
LT		 17393out_nofree:
17394 return ret;
17395}
17396
229b1ad1 17397static void tg3_init_bufmgr_config(struct tg3 *tp)
1da177e4 17398{
63c3a66f 17399 if (tg3_flag(tp, 57765_PLUS)) {
666bc831
MC		 17400 tp->bufmgr_config.mbuf_read_dma_low_water =
17401 DEFAULT_MB_RDMA_LOW_WATER_5705;
17402 tp->bufmgr_config.mbuf_mac_rx_low_water =
17403 DEFAULT_MB_MACRX_LOW_WATER_57765;
17404 tp->bufmgr_config.mbuf_high_water =
17405 DEFAULT_MB_HIGH_WATER_57765;
17406
17407 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
17408 DEFAULT_MB_RDMA_LOW_WATER_5705;
17409 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
17410 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_57765;
17411 tp->bufmgr_config.mbuf_high_water_jumbo =
17412 DEFAULT_MB_HIGH_WATER_JUMBO_57765;
63c3a66f 17413 } else if (tg3_flag(tp, 5705_PLUS)) {
fdfec172
MC		 17414 tp->bufmgr_config.mbuf_read_dma_low_water =
17415 DEFAULT_MB_RDMA_LOW_WATER_5705;
17416 tp->bufmgr_config.mbuf_mac_rx_low_water =
17417 DEFAULT_MB_MACRX_LOW_WATER_5705;
17418 tp->bufmgr_config.mbuf_high_water =
17419 DEFAULT_MB_HIGH_WATER_5705;
4153577a 17420 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
b5d3772c
MC		 17421 tp->bufmgr_config.mbuf_mac_rx_low_water =
17422 DEFAULT_MB_MACRX_LOW_WATER_5906;
17423 tp->bufmgr_config.mbuf_high_water =
17424 DEFAULT_MB_HIGH_WATER_5906;
17425 }
fdfec172
MC		 17426
17427 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
17428 DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
17429 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
17430 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780;
17431 tp->bufmgr_config.mbuf_high_water_jumbo =
17432 DEFAULT_MB_HIGH_WATER_JUMBO_5780;
17433 } else {
17434 tp->bufmgr_config.mbuf_read_dma_low_water =
17435 DEFAULT_MB_RDMA_LOW_WATER;
17436 tp->bufmgr_config.mbuf_mac_rx_low_water =
17437 DEFAULT_MB_MACRX_LOW_WATER;
17438 tp->bufmgr_config.mbuf_high_water =
17439 DEFAULT_MB_HIGH_WATER;
17440
17441 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
17442 DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
17443 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
17444 DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
17445 tp->bufmgr_config.mbuf_high_water_jumbo =
17446 DEFAULT_MB_HIGH_WATER_JUMBO;
17447 }
1da177e4
LT		 17448
17449 tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
17450 tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
17451}
17452
229b1ad1 17453static char *tg3_phy_string(struct tg3 *tp)
1da177e4 17454{
79eb6904
MC		 17455 switch (tp->phy_id & TG3_PHY_ID_MASK) {
17456 case TG3_PHY_ID_BCM5400: return "5400";
17457 case TG3_PHY_ID_BCM5401: return "5401";
17458 case TG3_PHY_ID_BCM5411: return "5411";
17459 case TG3_PHY_ID_BCM5701: return "5701";
17460 case TG3_PHY_ID_BCM5703: return "5703";
17461 case TG3_PHY_ID_BCM5704: return "5704";
17462 case TG3_PHY_ID_BCM5705: return "5705";
17463 case TG3_PHY_ID_BCM5750: return "5750";
17464 case TG3_PHY_ID_BCM5752: return "5752";
17465 case TG3_PHY_ID_BCM5714: return "5714";
17466 case TG3_PHY_ID_BCM5780: return "5780";
17467 case TG3_PHY_ID_BCM5755: return "5755";
17468 case TG3_PHY_ID_BCM5787: return "5787";
17469 case TG3_PHY_ID_BCM5784: return "5784";
17470 case TG3_PHY_ID_BCM5756: return "5722/5756";
17471 case TG3_PHY_ID_BCM5906: return "5906";
17472 case TG3_PHY_ID_BCM5761: return "5761";
17473 case TG3_PHY_ID_BCM5718C: return "5718C";
17474 case TG3_PHY_ID_BCM5718S: return "5718S";
17475 case TG3_PHY_ID_BCM57765: return "57765";
302b500b 17476 case TG3_PHY_ID_BCM5719C: return "5719C";
6418f2c1 17477 case TG3_PHY_ID_BCM5720C: return "5720C";
c65a17f4 17478 case TG3_PHY_ID_BCM5762: return "5762C";
79eb6904 17479 case TG3_PHY_ID_BCM8002: return "8002/serdes";
1da177e4
LT		 17480 case 0: return "serdes";
17481 default: return "unknown";
855e1111 17482 }
1da177e4
LT		 17483}
17484
229b1ad1 17485static char *tg3_bus_string(struct tg3 *tp, char *str)
f9804ddb 17486{
63c3a66f 17487 if (tg3_flag(tp, PCI_EXPRESS)) {
f9804ddb
MC		 17488 strcpy(str, "PCI Express");
17489 return str;
63c3a66f 17490 } else if (tg3_flag(tp, PCIX_MODE)) {
f9804ddb
MC		 17491 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
17492
17493 strcpy(str, "PCIX:");
17494
17495 if ((clock_ctrl == 7) ||
17496 ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) ==
17497 GRC_MISC_CFG_BOARD_ID_5704CIOBE))
17498 strcat(str, "133MHz");
17499 else if (clock_ctrl == 0)
17500 strcat(str, "33MHz");
17501 else if (clock_ctrl == 2)
17502 strcat(str, "50MHz");
17503 else if (clock_ctrl == 4)
17504 strcat(str, "66MHz");
17505 else if (clock_ctrl == 6)
17506 strcat(str, "100MHz");
f9804ddb
MC		 17507 } else {
17508 strcpy(str, "PCI:");
63c3a66f 17509 if (tg3_flag(tp, PCI_HIGH_SPEED))
f9804ddb
MC		 17510 strcat(str, "66MHz");
17511 else
17512 strcat(str, "33MHz");
17513 }
63c3a66f 17514 if (tg3_flag(tp, PCI_32BIT))
f9804ddb
MC		 17515 strcat(str, ":32-bit");
17516 else
17517 strcat(str, ":64-bit");
17518 return str;
17519}
17520
229b1ad1 17521static void tg3_init_coal(struct tg3 *tp)
15f9850d
DM		 17522{
17523 struct ethtool_coalesce *ec = &tp->coal;
17524
17525 memset(ec, 0, sizeof(*ec));
17526 ec->cmd = ETHTOOL_GCOALESCE;
17527 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
17528 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
17529 ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
17530 ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
17531 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
17532 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
17533 ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
17534 ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
17535 ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
17536
17537 if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
17538 HOSTCC_MODE_CLRTICK_TXBD)) {
17539 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
17540 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
17541 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
17542 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
17543 }
d244c892 17544
63c3a66f 17545 if (tg3_flag(tp, 5705_PLUS)) {
d244c892
MC		 17546 ec->rx_coalesce_usecs_irq = 0;
17547 ec->tx_coalesce_usecs_irq = 0;
17548 ec->stats_block_coalesce_usecs = 0;
17549 }
15f9850d
DM		 17550}
17551
229b1ad1 17552static int tg3_init_one(struct pci_dev *pdev,
1da177e4
LT		 17553 const struct pci_device_id *ent)
17554{
1da177e4
LT		 17555 struct net_device *dev;
17556 struct tg3 *tp;
5865fc1b 17557 int i, err;
646c9edd 17558 u32 sndmbx, rcvmbx, intmbx;
f9804ddb 17559 char str[40];
72f2afb8 17560 u64 dma_mask, persist_dma_mask;
c8f44aff 17561 netdev_features_t features = 0;
1da177e4 17562
05dbe005 17563 printk_once(KERN_INFO "%s\n", version);
1da177e4
LT		 17564
17565 err = pci_enable_device(pdev);
17566 if (err) {
2445e461 17567 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
1da177e4
LT		 17568 return err;
17569 }
17570
1da177e4
LT		 17571 err = pci_request_regions(pdev, DRV_MODULE_NAME);
17572 if (err) {
2445e461 17573 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n");
1da177e4
LT		 17574 goto err_out_disable_pdev;
17575 }
17576
17577 pci_set_master(pdev);
17578
fe5f5787 17579 dev = alloc_etherdev_mq(sizeof(*tp), TG3_IRQ_MAX_VECS);
1da177e4 17580 if (!dev) {
1da177e4 17581 err = -ENOMEM;
5865fc1b 17582 goto err_out_free_res;
1da177e4
LT		 17583 }
17584
1da177e4
LT		 17585 SET_NETDEV_DEV(dev, &pdev->dev);
17586
1da177e4
LT		 17587 tp = netdev_priv(dev);
17588 tp->pdev = pdev;
17589 tp->dev = dev;
1da177e4
LT		 17590 tp->rx_mode = TG3_DEF_RX_MODE;
17591 tp->tx_mode = TG3_DEF_TX_MODE;
9c13cb8b 17592 tp->irq_sync = 1;
0486a063 17593 tp->pcierr_recovery = false;
8ef21428 17594
1da177e4
LT		 17595 if (tg3_debug > 0)
17596 tp->msg_enable = tg3_debug;
17597 else
17598 tp->msg_enable = TG3_DEF_MSG_ENABLE;
17599
7e6c63f0
HM		 17600 if (pdev_is_ssb_gige_core(pdev)) {
17601 tg3_flag_set(tp, IS_SSB_CORE);
17602 if (ssb_gige_must_flush_posted_writes(pdev))
17603 tg3_flag_set(tp, FLUSH_POSTED_WRITES);
17604 if (ssb_gige_one_dma_at_once(pdev))
17605 tg3_flag_set(tp, ONE_DMA_AT_ONCE);
ee002b64
HM		 17606 if (ssb_gige_have_roboswitch(pdev)) {
17607 tg3_flag_set(tp, USE_PHYLIB);
7e6c63f0 17608 tg3_flag_set(tp, ROBOSWITCH);
ee002b64 17609 }
7e6c63f0
HM		 17610 if (ssb_gige_is_rgmii(pdev))
17611 tg3_flag_set(tp, RGMII_MODE);
17612 }
17613
1da177e4
LT		 17614 /* The word/byte swap controls here control register access byte
17615 * swapping. DMA data byte swapping is controlled in the GRC_MODE
17616 * setting below.
17617 */
17618 tp->misc_host_ctrl =
17619 MISC_HOST_CTRL_MASK_PCI_INT |
17620 MISC_HOST_CTRL_WORD_SWAP |
17621 MISC_HOST_CTRL_INDIR_ACCESS |
17622 MISC_HOST_CTRL_PCISTATE_RW;
17623
17624 /* The NONFRM (non-frame) byte/word swap controls take effect
17625 * on descriptor entries, anything which isn't packet data.
17626 *
17627 * The StrongARM chips on the board (one for tx, one for rx)
17628 * are running in big-endian mode.
17629 */
17630 tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
17631 GRC_MODE_WSWAP_NONFRM_DATA);
17632#ifdef __BIG_ENDIAN
17633 tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
17634#endif
17635 spin_lock_init(&tp->lock);
1da177e4 17636 spin_lock_init(&tp->indirect_lock);
c4028958 17637 INIT_WORK(&tp->reset_task, tg3_reset_task);
1da177e4 17638
d5fe488a 17639 tp->regs = pci_ioremap_bar(pdev, BAR_0);
ab0049b4 17640 if (!tp->regs) {
ab96b241 17641 dev_err(&pdev->dev, "Cannot map device registers, aborting\n");
1da177e4
LT		 17642 err = -ENOMEM;
17643 goto err_out_free_dev;
17644 }
17645
c9cab24e
MC		 17646 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
17647 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761E ||
17648 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S ||
17649 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761SE ||
17650 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 ||
79d49695 17651 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717_C ||
c9cab24e
MC		 17652 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 ||
17653 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5719 ||
c65a17f4 17654 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5720 ||
68273712
NS		 17655 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57767 ||
17656 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57764 ||
c65a17f4
MC		 17657 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5762 ||
17658 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5725 ||
68273712
NS		 17659 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5727 ||
17660 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57787) {
c9cab24e
MC		 17661 tg3_flag_set(tp, ENABLE_APE);
17662 tp->aperegs = pci_ioremap_bar(pdev, BAR_2);
17663 if (!tp->aperegs) {
17664 dev_err(&pdev->dev,
17665 "Cannot map APE registers, aborting\n");
17666 err = -ENOMEM;
17667 goto err_out_iounmap;
17668 }
17669 }
17670
1da177e4
LT		 17671 tp->rx_pending = TG3_DEF_RX_RING_PENDING;
17672 tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
1da177e4 17673
1da177e4 17674 dev->ethtool_ops = &tg3_ethtool_ops;
1da177e4 17675 dev->watchdog_timeo = TG3_TX_TIMEOUT;
2ffcc981 17676 dev->netdev_ops = &tg3_netdev_ops;
1da177e4 17677 dev->irq = pdev->irq;
1da177e4 17678
3d567e0e 17679 err = tg3_get_invariants(tp, ent);
1da177e4 17680 if (err) {
ab96b241
MC		 17681 dev_err(&pdev->dev,
17682 "Problem fetching invariants of chip, aborting\n");
c9cab24e 17683 goto err_out_apeunmap;
1da177e4
LT		 17684 }
17685
4a29cc2e
MC		 17686 /* The EPB bridge inside 5714, 5715, and 5780 and any
17687 * device behind the EPB cannot support DMA addresses > 40-bit.
72f2afb8
MC		 17688 * On 64-bit systems with IOMMU, use 40-bit dma_mask.
17689 * On 64-bit systems without IOMMU, use 64-bit dma_mask and
17690 * do DMA address check in tg3_start_xmit().
17691 */
63c3a66f 17692 if (tg3_flag(tp, IS_5788))
284901a9 17693 persist_dma_mask = dma_mask = DMA_BIT_MASK(32);
63c3a66f 17694 else if (tg3_flag(tp, 40BIT_DMA_BUG)) {
50cf156a 17695 persist_dma_mask = dma_mask = DMA_BIT_MASK(40);
72f2afb8 17696#ifdef CONFIG_HIGHMEM
6a35528a 17697 dma_mask = DMA_BIT_MASK(64);
72f2afb8 17698#endif
4a29cc2e 17699 } else
6a35528a 17700 persist_dma_mask = dma_mask = DMA_BIT_MASK(64);
72f2afb8
MC		 17701
17702 /* Configure DMA attributes. */
284901a9 17703 if (dma_mask > DMA_BIT_MASK(32)) {
72f2afb8
MC		 17704 err = pci_set_dma_mask(pdev, dma_mask);
17705 if (!err) {
0da0606f 17706 features |= NETIF_F_HIGHDMA;
72f2afb8
MC		 17707 err = pci_set_consistent_dma_mask(pdev,
17708 persist_dma_mask);
17709 if (err < 0) {
ab96b241
MC		 17710 dev_err(&pdev->dev, "Unable to obtain 64 bit "
17711 "DMA for consistent allocations\n");
c9cab24e 17712 goto err_out_apeunmap;
72f2afb8
MC		 17713 }
17714 }
17715 }
284901a9
YH		 17716 if (err || dma_mask == DMA_BIT_MASK(32)) {
17717 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
72f2afb8 17718 if (err) {
ab96b241
MC		 17719 dev_err(&pdev->dev,
17720 "No usable DMA configuration, aborting\n");
c9cab24e 17721 goto err_out_apeunmap;
72f2afb8
MC		 17722 }
17723 }
17724
fdfec172 17725 tg3_init_bufmgr_config(tp);
1da177e4 17726
0da0606f
MC		 17727 /* 5700 B0 chips do not support checksumming correctly due
17728 * to hardware bugs.
17729 */
4153577a 17730 if (tg3_chip_rev_id(tp) != CHIPREV_ID_5700_B0) {
0da0606f
MC		 17731 features |= NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_RXCSUM;
17732
17733 if (tg3_flag(tp, 5755_PLUS))
17734 features |= NETIF_F_IPV6_CSUM;
17735 }
17736
4e3a7aaa
MC		 17737 /* TSO is on by default on chips that support hardware TSO.
17738 * Firmware TSO on older chips gives lower performance, so it
17739 * is off by default, but can be enabled using ethtool.
17740 */
63c3a66f
JP		 17741 if ((tg3_flag(tp, HW_TSO_1) ||
17742 tg3_flag(tp, HW_TSO_2) ||
17743 tg3_flag(tp, HW_TSO_3)) &&
0da0606f
MC		 17744 (features & NETIF_F_IP_CSUM))
17745 features |= NETIF_F_TSO;
63c3a66f 17746 if (tg3_flag(tp, HW_TSO_2) || tg3_flag(tp, HW_TSO_3)) {
0da0606f
MC		 17747 if (features & NETIF_F_IPV6_CSUM)
17748 features |= NETIF_F_TSO6;
63c3a66f 17749 if (tg3_flag(tp, HW_TSO_3) ||
4153577a
JP		 17750 tg3_asic_rev(tp) == ASIC_REV_5761 ||
17751 (tg3_asic_rev(tp) == ASIC_REV_5784 &&
17752 tg3_chip_rev(tp) != CHIPREV_5784_AX) ||
17753 tg3_asic_rev(tp) == ASIC_REV_5785 ||
17754 tg3_asic_rev(tp) == ASIC_REV_57780)
0da0606f 17755 features |= NETIF_F_TSO_ECN;
b0026624 17756 }
1da177e4 17757
51dfe7b9
VY		 17758 dev->features |= features | NETIF_F_HW_VLAN_CTAG_TX |
17759 NETIF_F_HW_VLAN_CTAG_RX;
d542fe27
MC		 17760 dev->vlan_features |= features;
17761
06c03c02
MB		 17762 /*
17763 * Add loopback capability only for a subset of devices that support
17764 * MAC-LOOPBACK. Eventually this need to be enhanced to allow INT-PHY
17765 * loopback for the remaining devices.
17766 */
4153577a 17767 if (tg3_asic_rev(tp) != ASIC_REV_5780 &&
06c03c02
MB		 17768 !tg3_flag(tp, CPMU_PRESENT))
17769 /* Add the loopback capability */
0da0606f
MC		 17770 features |= NETIF_F_LOOPBACK;
17771
0da0606f 17772 dev->hw_features |= features;
e565eec3 17773 dev->priv_flags |= IFF_UNICAST_FLT;
06c03c02 17774
4153577a 17775 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5705_A1 &&
63c3a66f 17776 !tg3_flag(tp, TSO_CAPABLE) &&
1da177e4 17777 !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
63c3a66f 17778 tg3_flag_set(tp, MAX_RXPEND_64);
1da177e4
LT		 17779 tp->rx_pending = 63;
17780 }
17781
1da177e4
LT		 17782 err = tg3_get_device_address(tp);
17783 if (err) {
ab96b241
MC		 17784 dev_err(&pdev->dev,
17785 "Could not obtain valid ethernet address, aborting\n");
c9cab24e 17786 goto err_out_apeunmap;
c88864df
MC		 17787 }
17788
1da177e4
LT		 17789 /*
17790 * Reset chip in case UNDI or EFI driver did not shutdown
17791 * DMA self test will enable WDMAC and we'll see (spurious)
17792 * pending DMA on the PCI bus at that point.
17793 */
17794 if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
17795 (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
1da177e4 17796 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
944d980e 17797 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4
LT		 17798 }
17799
17800 err = tg3_test_dma(tp);
17801 if (err) {
ab96b241 17802 dev_err(&pdev->dev, "DMA engine test failed, aborting\n");
c88864df 17803 goto err_out_apeunmap;
1da177e4
LT		 17804 }
17805
78f90dcf
MC		 17806 intmbx = MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW;
17807 rcvmbx = MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW;
17808 sndmbx = MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW;
6fd45cb8 17809 for (i = 0; i < tp->irq_max; i++) {
78f90dcf
MC		 17810 struct tg3_napi *tnapi = &tp->napi[i];
17811
17812 tnapi->tp = tp;
17813 tnapi->tx_pending = TG3_DEF_TX_RING_PENDING;
17814
17815 tnapi->int_mbox = intmbx;
93a700a9 17816 if (i <= 4)
78f90dcf
MC		 17817 intmbx += 0x8;
17818 else
17819 intmbx += 0x4;
17820
17821 tnapi->consmbox = rcvmbx;
17822 tnapi->prodmbox = sndmbx;
17823
66cfd1bd 17824 if (i)
78f90dcf 17825 tnapi->coal_now = HOSTCC_MODE_COAL_VEC1_NOW << (i - 1);
66cfd1bd 17826 else
78f90dcf 17827 tnapi->coal_now = HOSTCC_MODE_NOW;
78f90dcf 17828
63c3a66f 17829 if (!tg3_flag(tp, SUPPORT_MSIX))
78f90dcf
MC		 17830 break;
17831
17832 /*
17833 * If we support MSIX, we'll be using RSS. If we're using
17834 * RSS, the first vector only handles link interrupts and the
17835 * remaining vectors handle rx and tx interrupts. Reuse the
17836 * mailbox values for the next iteration. The values we setup
17837 * above are still useful for the single vectored mode.
17838 */
17839 if (!i)
17840 continue;
17841
17842 rcvmbx += 0x8;
17843
17844 if (sndmbx & 0x4)
17845 sndmbx -= 0x4;
17846 else
17847 sndmbx += 0xc;
17848 }
17849
15f9850d
DM		 17850 tg3_init_coal(tp);
17851
c49a1561
MC		 17852 pci_set_drvdata(pdev, dev);
17853
4153577a
JP		 17854 if (tg3_asic_rev(tp) == ASIC_REV_5719 ||
17855 tg3_asic_rev(tp) == ASIC_REV_5720 ||
17856 tg3_asic_rev(tp) == ASIC_REV_5762)
fb4ce8ad
MC		 17857 tg3_flag_set(tp, PTP_CAPABLE);
17858
21f7638e
MC		 17859 tg3_timer_init(tp);
17860
402e1398
MC		 17861 tg3_carrier_off(tp);
17862
1da177e4
LT		 17863 err = register_netdev(dev);
17864 if (err) {
ab96b241 17865 dev_err(&pdev->dev, "Cannot register net device, aborting\n");
0d3031d9 17866 goto err_out_apeunmap;
1da177e4
LT		 17867 }
17868
05dbe005
JP		 17869 netdev_info(dev, "Tigon3 [partno(%s) rev %04x] (%s) MAC address %pM\n",
17870 tp->board_part_number,
4153577a 17871 tg3_chip_rev_id(tp),
05dbe005
JP		 17872 tg3_bus_string(tp, str),
17873 dev->dev_addr);
1da177e4 17874
f07e9af3 17875 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
3f0e3ad7 17876 struct phy_device *phydev;
ead2402c 17877 phydev = tp->mdio_bus->phy_map[tp->phy_addr];
5129c3a3
MC		 17878 netdev_info(dev,
17879 "attached PHY driver [%s] (mii_bus:phy_addr=%s)\n",
05dbe005 17880 phydev->drv->name, dev_name(&phydev->dev));
f07e9af3
MC		 17881 } else {
17882 char *ethtype;
17883
17884 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
17885 ethtype = "10/100Base-TX";
17886 else if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
17887 ethtype = "1000Base-SX";
17888 else
17889 ethtype = "10/100/1000Base-T";
17890
5129c3a3 17891 netdev_info(dev, "attached PHY is %s (%s Ethernet) "
47007831
MC		 17892 "(WireSpeed[%d], EEE[%d])\n",
17893 tg3_phy_string(tp), ethtype,
17894 (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED) == 0,
17895 (tp->phy_flags & TG3_PHYFLG_EEE_CAP) != 0);
f07e9af3 17896 }
05dbe005
JP		 17897
17898 netdev_info(dev, "RXcsums[%d] LinkChgREG[%d] MIirq[%d] ASF[%d] TSOcap[%d]\n",
dc668910 17899 (dev->features & NETIF_F_RXCSUM) != 0,
63c3a66f 17900 tg3_flag(tp, USE_LINKCHG_REG) != 0,
f07e9af3 17901 (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) != 0,
63c3a66f
JP		 17902 tg3_flag(tp, ENABLE_ASF) != 0,
17903 tg3_flag(tp, TSO_CAPABLE) != 0);
05dbe005
JP		 17904 netdev_info(dev, "dma_rwctrl[%08x] dma_mask[%d-bit]\n",
17905 tp->dma_rwctrl,
17906 pdev->dma_mask == DMA_BIT_MASK(32) ? 32 :
17907 ((u64)pdev->dma_mask) == DMA_BIT_MASK(40) ? 40 : 64);
1da177e4 17908
b45aa2f6
MC		 17909 pci_save_state(pdev);
17910
1da177e4
LT		 17911 return 0;
17912
0d3031d9
MC		 17913err_out_apeunmap:
17914 if (tp->aperegs) {
17915 iounmap(tp->aperegs);
17916 tp->aperegs = NULL;
17917 }
17918
1da177e4 17919err_out_iounmap:
6892914f
MC		 17920 if (tp->regs) {
17921 iounmap(tp->regs);
22abe310 17922 tp->regs = NULL;
6892914f 17923 }
1da177e4
LT		 17924
17925err_out_free_dev:
17926 free_netdev(dev);
17927
17928err_out_free_res:
17929 pci_release_regions(pdev);
17930
17931err_out_disable_pdev:
c80dc13d
GS		 17932 if (pci_is_enabled(pdev))
17933 pci_disable_device(pdev);
1da177e4
LT		 17934 return err;
17935}
17936
229b1ad1 17937static void tg3_remove_one(struct pci_dev *pdev)
1da177e4
LT		 17938{
17939 struct net_device *dev = pci_get_drvdata(pdev);
17940
17941 if (dev) {
17942 struct tg3 *tp = netdev_priv(dev);
17943
e3c5530b 17944 release_firmware(tp->fw);
077f849d 17945
db219973 17946 tg3_reset_task_cancel(tp);
158d7abd 17947
e730c823 17948 if (tg3_flag(tp, USE_PHYLIB)) {
b02fd9e3 17949 tg3_phy_fini(tp);
158d7abd 17950 tg3_mdio_fini(tp);
b02fd9e3 17951 }
158d7abd 17952
1da177e4 17953 unregister_netdev(dev);
0d3031d9
MC		 17954 if (tp->aperegs) {
17955 iounmap(tp->aperegs);
17956 tp->aperegs = NULL;
17957 }
6892914f
MC		 17958 if (tp->regs) {
17959 iounmap(tp->regs);
22abe310 17960 tp->regs = NULL;
6892914f 17961 }
1da177e4
LT		 17962 free_netdev(dev);
17963 pci_release_regions(pdev);
17964 pci_disable_device(pdev);
1da177e4
LT		 17965 }
17966}
17967
aa6027ca 17968#ifdef CONFIG_PM_SLEEP
c866b7ea 17969static int tg3_suspend(struct device *device)
1da177e4 17970{
c866b7ea 17971 struct pci_dev *pdev = to_pci_dev(device);
1da177e4
LT		 17972 struct net_device *dev = pci_get_drvdata(pdev);
17973 struct tg3 *tp = netdev_priv(dev);
8496e85c
RW		 17974 int err = 0;
17975
17976 rtnl_lock();
1da177e4
LT		 17977
17978 if (!netif_running(dev))
8496e85c 17979 goto unlock;
1da177e4 17980
db219973 17981 tg3_reset_task_cancel(tp);
b02fd9e3 17982 tg3_phy_stop(tp);
1da177e4
LT		 17983 tg3_netif_stop(tp);
17984
21f7638e 17985 tg3_timer_stop(tp);
1da177e4 17986
f47c11ee 17987 tg3_full_lock(tp, 1);
1da177e4 17988 tg3_disable_ints(tp);
f47c11ee 17989 tg3_full_unlock(tp);
1da177e4
LT		 17990
17991 netif_device_detach(dev);
17992
f47c11ee 17993 tg3_full_lock(tp, 0);
944d980e 17994 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
63c3a66f 17995 tg3_flag_clear(tp, INIT_COMPLETE);
f47c11ee 17996 tg3_full_unlock(tp);
1da177e4 17997
c866b7ea 17998 err = tg3_power_down_prepare(tp);
1da177e4 17999 if (err) {
b02fd9e3
MC		 18000 int err2;
18001
f47c11ee 18002 tg3_full_lock(tp, 0);
1da177e4 18003
63c3a66f 18004 tg3_flag_set(tp, INIT_COMPLETE);
953c96e0 18005 err2 = tg3_restart_hw(tp, true);
b02fd9e3 18006 if (err2)
b9ec6c1b 18007 goto out;
1da177e4 18008
21f7638e 18009 tg3_timer_start(tp);
1da177e4
LT		 18010
18011 netif_device_attach(dev);
18012 tg3_netif_start(tp);
18013
b9ec6c1b 18014out:
f47c11ee 18015 tg3_full_unlock(tp);
b02fd9e3
MC		 18016
18017 if (!err2)
18018 tg3_phy_start(tp);
1da177e4
LT		 18019 }
18020
8496e85c
RW		 18021unlock:
18022 rtnl_unlock();
1da177e4
LT		 18023 return err;
18024}
18025
c866b7ea 18026static int tg3_resume(struct device *device)
1da177e4 18027{
c866b7ea 18028 struct pci_dev *pdev = to_pci_dev(device);
1da177e4
LT		 18029 struct net_device *dev = pci_get_drvdata(pdev);
18030 struct tg3 *tp = netdev_priv(dev);
8496e85c
RW		 18031 int err = 0;
18032
18033 rtnl_lock();
1da177e4
LT		 18034
18035 if (!netif_running(dev))
8496e85c 18036 goto unlock;
1da177e4 18037
1da177e4
LT		 18038 netif_device_attach(dev);
18039
f47c11ee 18040 tg3_full_lock(tp, 0);
1da177e4 18041
2e460fc0
NS		 18042 tg3_ape_driver_state_change(tp, RESET_KIND_INIT);
18043
63c3a66f 18044 tg3_flag_set(tp, INIT_COMPLETE);
942d1af0
NS		 18045 err = tg3_restart_hw(tp,
18046 !(tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN));
b9ec6c1b
MC		 18047 if (err)
18048 goto out;
1da177e4 18049
21f7638e 18050 tg3_timer_start(tp);
1da177e4 18051
1da177e4
LT		 18052 tg3_netif_start(tp);
18053
b9ec6c1b 18054out:
f47c11ee 18055 tg3_full_unlock(tp);
1da177e4 18056
b02fd9e3
MC		 18057 if (!err)
18058 tg3_phy_start(tp);
18059
8496e85c
RW		 18060unlock:
18061 rtnl_unlock();
b9ec6c1b 18062 return err;
1da177e4 18063}
42df36a6 18064#endif /* CONFIG_PM_SLEEP */
1da177e4 18065
c866b7ea
RW		 18066static SIMPLE_DEV_PM_OPS(tg3_pm_ops, tg3_suspend, tg3_resume);
18067
4c305fa2
NS		 18068static void tg3_shutdown(struct pci_dev *pdev)
18069{
18070 struct net_device *dev = pci_get_drvdata(pdev);
18071 struct tg3 *tp = netdev_priv(dev);
18072
18073 rtnl_lock();
18074 netif_device_detach(dev);
18075
18076 if (netif_running(dev))
18077 dev_close(dev);
18078
18079 if (system_state == SYSTEM_POWER_OFF)
18080 tg3_power_down(tp);
18081
18082 rtnl_unlock();
18083}
18084
b45aa2f6
MC		 18085/**
18086 * tg3_io_error_detected - called when PCI error is detected
18087 * @pdev: Pointer to PCI device
18088 * @state: The current pci connection state
18089 *
18090 * This function is called after a PCI bus error affecting
18091 * this device has been detected.
18092 */
18093static pci_ers_result_t tg3_io_error_detected(struct pci_dev *pdev,
18094 pci_channel_state_t state)
18095{
18096 struct net_device *netdev = pci_get_drvdata(pdev);
18097 struct tg3 *tp = netdev_priv(netdev);
18098 pci_ers_result_t err = PCI_ERS_RESULT_NEED_RESET;
18099
18100 netdev_info(netdev, "PCI I/O error detected\n");
18101
18102 rtnl_lock();
18103
0486a063
IV		 18104 tp->pcierr_recovery = true;
18105
d8af4dfd
GS		 18106 /* We probably don't have netdev yet */
18107 if (!netdev || !netif_running(netdev))
b45aa2f6
MC		 18108 goto done;
18109
18110 tg3_phy_stop(tp);
18111
18112 tg3_netif_stop(tp);
18113
21f7638e 18114 tg3_timer_stop(tp);
b45aa2f6
MC		 18115
18116 /* Want to make sure that the reset task doesn't run */
db219973 18117 tg3_reset_task_cancel(tp);
b45aa2f6
MC		 18118
18119 netif_device_detach(netdev);
18120
18121 /* Clean up software state, even if MMIO is blocked */
18122 tg3_full_lock(tp, 0);
18123 tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
18124 tg3_full_unlock(tp);
18125
18126done:
72bb72b0 18127 if (state == pci_channel_io_perm_failure) {
68293099
DB		 18128 if (netdev) {
18129 tg3_napi_enable(tp);
18130 dev_close(netdev);
18131 }
b45aa2f6 18132 err = PCI_ERS_RESULT_DISCONNECT;
72bb72b0 18133 } else {
b45aa2f6 18134 pci_disable_device(pdev);
72bb72b0 18135 }
b45aa2f6
MC		 18136
18137 rtnl_unlock();
18138
18139 return err;
18140}
18141
18142/**
18143 * tg3_io_slot_reset - called after the pci bus has been reset.
18144 * @pdev: Pointer to PCI device
18145 *
18146 * Restart the card from scratch, as if from a cold-boot.
18147 * At this point, the card has exprienced a hard reset,
18148 * followed by fixups by BIOS, and has its config space
18149 * set up identically to what it was at cold boot.
18150 */
18151static pci_ers_result_t tg3_io_slot_reset(struct pci_dev *pdev)
18152{
18153 struct net_device *netdev = pci_get_drvdata(pdev);
18154 struct tg3 *tp = netdev_priv(netdev);
18155 pci_ers_result_t rc = PCI_ERS_RESULT_DISCONNECT;
18156 int err;
18157
18158 rtnl_lock();
18159
18160 if (pci_enable_device(pdev)) {
68293099
DB		 18161 dev_err(&pdev->dev,
18162 "Cannot re-enable PCI device after reset.\n");
b45aa2f6
MC		 18163 goto done;
18164 }
18165
18166 pci_set_master(pdev);
18167 pci_restore_state(pdev);
18168 pci_save_state(pdev);
18169
68293099 18170 if (!netdev || !netif_running(netdev)) {
b45aa2f6
MC		 18171 rc = PCI_ERS_RESULT_RECOVERED;
18172 goto done;
18173 }
18174
18175 err = tg3_power_up(tp);
bed9829f 18176 if (err)
b45aa2f6 18177 goto done;
b45aa2f6
MC		 18178
18179 rc = PCI_ERS_RESULT_RECOVERED;
18180
18181done:
68293099 18182 if (rc != PCI_ERS_RESULT_RECOVERED && netdev && netif_running(netdev)) {
72bb72b0
MC		 18183 tg3_napi_enable(tp);
18184 dev_close(netdev);
18185 }
b45aa2f6
MC		 18186 rtnl_unlock();
18187
18188 return rc;
18189}
18190
18191/**
18192 * tg3_io_resume - called when traffic can start flowing again.
18193 * @pdev: Pointer to PCI device
18194 *
18195 * This callback is called when the error recovery driver tells
18196 * us that its OK to resume normal operation.
18197 */
18198static void tg3_io_resume(struct pci_dev *pdev)
18199{
18200 struct net_device *netdev = pci_get_drvdata(pdev);
18201 struct tg3 *tp = netdev_priv(netdev);
18202 int err;
18203
18204 rtnl_lock();
18205
18206 if (!netif_running(netdev))
18207 goto done;
18208
18209 tg3_full_lock(tp, 0);
2e460fc0 18210 tg3_ape_driver_state_change(tp, RESET_KIND_INIT);
63c3a66f 18211 tg3_flag_set(tp, INIT_COMPLETE);
953c96e0 18212 err = tg3_restart_hw(tp, true);
b45aa2f6 18213 if (err) {
35763066 18214 tg3_full_unlock(tp);
b45aa2f6
MC		 18215 netdev_err(netdev, "Cannot restart hardware after reset.\n");
18216 goto done;
18217 }
18218
18219 netif_device_attach(netdev);
18220
21f7638e 18221 tg3_timer_start(tp);
b45aa2f6
MC		 18222
18223 tg3_netif_start(tp);
18224
35763066
NNS		 18225 tg3_full_unlock(tp);
18226
b45aa2f6
MC		 18227 tg3_phy_start(tp);
18228
18229done:
0486a063 18230 tp->pcierr_recovery = false;
b45aa2f6
MC		 18231 rtnl_unlock();
18232}
18233
3646f0e5 18234static const struct pci_error_handlers tg3_err_handler = {
b45aa2f6
MC		 18235 .error_detected = tg3_io_error_detected,
18236 .slot_reset = tg3_io_slot_reset,
18237 .resume = tg3_io_resume
18238};
18239
1da177e4
LT		 18240static struct pci_driver tg3_driver = {
18241 .name = DRV_MODULE_NAME,
18242 .id_table = tg3_pci_tbl,
18243 .probe = tg3_init_one,
229b1ad1 18244 .remove = tg3_remove_one,
b45aa2f6 18245 .err_handler = &tg3_err_handler,
42df36a6 18246 .driver.pm = &tg3_pm_ops,
4c305fa2 18247 .shutdown = tg3_shutdown,
1da177e4
LT		 18248};
18249
8dbb0dc2 18250module_pci_driver(tg3_driver);
Linux kernel - Deliverables
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