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Merge back intel_pstate fixes for v4.6.
[deliverable/linux.git] / drivers / net / ethernet / brocade / bna / bfa_ioc.c
CommitLineData
8b230ed8 1/*
2732ba56 2 * Linux network driver for QLogic BR-series Converged Network Adapter.
8b230ed8
RM		 3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License (GPL) Version 2 as
6 * published by the Free Software Foundation
7 *
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
11 * General Public License for more details.
12 */
13/*
2732ba56
RM		 14 * Copyright (c) 2005-2014 Brocade Communications Systems, Inc.
15 * Copyright (c) 2014-2015 QLogic Corporation
8b230ed8 16 * All rights reserved
2732ba56 17 * www.qlogic.com
8b230ed8
RM		 18 */
19
20#include "bfa_ioc.h"
a9602490 21#include "bfi_reg.h"
8b230ed8
RM		 22#include "bfa_defs.h"
23
1aa8b471 24/* IOC local definitions */
8b230ed8 25
1aa8b471 26/* Asic specific macros : see bfa_hw_cb.c and bfa_hw_ct.c for details. */
8b230ed8
RM		 27
28#define bfa_ioc_firmware_lock(__ioc) \
29 ((__ioc)->ioc_hwif->ioc_firmware_lock(__ioc))
30#define bfa_ioc_firmware_unlock(__ioc) \
31 ((__ioc)->ioc_hwif->ioc_firmware_unlock(__ioc))
32#define bfa_ioc_reg_init(__ioc) ((__ioc)->ioc_hwif->ioc_reg_init(__ioc))
33#define bfa_ioc_map_port(__ioc) ((__ioc)->ioc_hwif->ioc_map_port(__ioc))
1d32f769
RM		 34#define bfa_ioc_notify_fail(__ioc) \
35 ((__ioc)->ioc_hwif->ioc_notify_fail(__ioc))
79ea6c89
RM		 36#define bfa_ioc_sync_start(__ioc) \
37 ((__ioc)->ioc_hwif->ioc_sync_start(__ioc))
1d32f769
RM		 38#define bfa_ioc_sync_join(__ioc) \
39 ((__ioc)->ioc_hwif->ioc_sync_join(__ioc))
40#define bfa_ioc_sync_leave(__ioc) \
41 ((__ioc)->ioc_hwif->ioc_sync_leave(__ioc))
42#define bfa_ioc_sync_ack(__ioc) \
43 ((__ioc)->ioc_hwif->ioc_sync_ack(__ioc))
44#define bfa_ioc_sync_complete(__ioc) \
45 ((__ioc)->ioc_hwif->ioc_sync_complete(__ioc))
41ed903a
RM		 46#define bfa_ioc_set_cur_ioc_fwstate(__ioc, __fwstate) \
47 ((__ioc)->ioc_hwif->ioc_set_fwstate(__ioc, __fwstate))
48#define bfa_ioc_get_cur_ioc_fwstate(__ioc) \
49 ((__ioc)->ioc_hwif->ioc_get_fwstate(__ioc))
50#define bfa_ioc_set_alt_ioc_fwstate(__ioc, __fwstate) \
51 ((__ioc)->ioc_hwif->ioc_set_alt_fwstate(__ioc, __fwstate))
8b230ed8 52
b7ee31c5 53static bool bfa_nw_auto_recover = true;
8b230ed8
RM		 54
55/*
56 * forward declarations
57 */
d4e16d42 58static void bfa_ioc_hw_sem_init(struct bfa_ioc *ioc);
8b230ed8
RM		 59static void bfa_ioc_hw_sem_get(struct bfa_ioc *ioc);
60static void bfa_ioc_hw_sem_get_cancel(struct bfa_ioc *ioc);
61static void bfa_ioc_hwinit(struct bfa_ioc *ioc, bool force);
078086f3 62static void bfa_ioc_poll_fwinit(struct bfa_ioc *ioc);
8b230ed8
RM		 63static void bfa_ioc_send_enable(struct bfa_ioc *ioc);
64static void bfa_ioc_send_disable(struct bfa_ioc *ioc);
65static void bfa_ioc_send_getattr(struct bfa_ioc *ioc);
66static void bfa_ioc_hb_monitor(struct bfa_ioc *ioc);
67static void bfa_ioc_hb_stop(struct bfa_ioc *ioc);
68static void bfa_ioc_reset(struct bfa_ioc *ioc, bool force);
69static void bfa_ioc_mbox_poll(struct bfa_ioc *ioc);
fdad400f 70static void bfa_ioc_mbox_flush(struct bfa_ioc *ioc);
8b230ed8 71static void bfa_ioc_recover(struct bfa_ioc *ioc);
bd5a92e9 72static void bfa_ioc_event_notify(struct bfa_ioc *, enum bfa_ioc_event);
8b230ed8
RM		 73static void bfa_ioc_disable_comp(struct bfa_ioc *ioc);
74static void bfa_ioc_lpu_stop(struct bfa_ioc *ioc);
7afc5dbd 75static void bfa_nw_ioc_debug_save_ftrc(struct bfa_ioc *ioc);
1d32f769
RM		 76static void bfa_ioc_fail_notify(struct bfa_ioc *ioc);
77static void bfa_ioc_pf_enabled(struct bfa_ioc *ioc);
78static void bfa_ioc_pf_disabled(struct bfa_ioc *ioc);
1d32f769 79static void bfa_ioc_pf_failed(struct bfa_ioc *ioc);
078086f3 80static void bfa_ioc_pf_hwfailed(struct bfa_ioc *ioc);
1d32f769 81static void bfa_ioc_pf_fwmismatch(struct bfa_ioc *ioc);
c107ba17
RM		 82static enum bfa_status bfa_ioc_boot(struct bfa_ioc *ioc,
83 enum bfi_fwboot_type boot_type, u32 boot_param);
8a891429 84static u32 bfa_ioc_smem_pgnum(struct bfa_ioc *ioc, u32 fmaddr);
8a891429
RM		 85static void bfa_ioc_get_adapter_serial_num(struct bfa_ioc *ioc,
86 char *serial_num);
87static void bfa_ioc_get_adapter_fw_ver(struct bfa_ioc *ioc,
88 char *fw_ver);
89static void bfa_ioc_get_pci_chip_rev(struct bfa_ioc *ioc,
90 char *chip_rev);
91static void bfa_ioc_get_adapter_optrom_ver(struct bfa_ioc *ioc,
92 char *optrom_ver);
93static void bfa_ioc_get_adapter_manufacturer(struct bfa_ioc *ioc,
94 char *manufacturer);
95static void bfa_ioc_get_adapter_model(struct bfa_ioc *ioc, char *model);
96static u64 bfa_ioc_get_pwwn(struct bfa_ioc *ioc);
8b230ed8 97
1aa8b471 98/* IOC state machine definitions/declarations */
8b230ed8 99enum ioc_event {
1d32f769
RM		 100 IOC_E_RESET = 1, /*!< IOC reset request */
101 IOC_E_ENABLE = 2, /*!< IOC enable request */
102 IOC_E_DISABLE = 3, /*!< IOC disable request */
103 IOC_E_DETACH = 4, /*!< driver detach cleanup */
104 IOC_E_ENABLED = 5, /*!< f/w enabled */
105 IOC_E_FWRSP_GETATTR = 6, /*!< IOC get attribute response */
106 IOC_E_DISABLED = 7, /*!< f/w disabled */
078086f3
RM		 107 IOC_E_PFFAILED = 8, /*!< failure notice by iocpf sm */
108 IOC_E_HBFAIL = 9, /*!< heartbeat failure */
109 IOC_E_HWERROR = 10, /*!< hardware error interrupt */
110 IOC_E_TIMEOUT = 11, /*!< timeout */
111 IOC_E_HWFAILED = 12, /*!< PCI mapping failure notice */
8b230ed8
RM		 112};
113
1d32f769 114bfa_fsm_state_decl(bfa_ioc, uninit, struct bfa_ioc, enum ioc_event);
8b230ed8 115bfa_fsm_state_decl(bfa_ioc, reset, struct bfa_ioc, enum ioc_event);
8b230ed8
RM		 116bfa_fsm_state_decl(bfa_ioc, enabling, struct bfa_ioc, enum ioc_event);
117bfa_fsm_state_decl(bfa_ioc, getattr, struct bfa_ioc, enum ioc_event);
118bfa_fsm_state_decl(bfa_ioc, op, struct bfa_ioc, enum ioc_event);
1d32f769
RM		 119bfa_fsm_state_decl(bfa_ioc, fail_retry, struct bfa_ioc, enum ioc_event);
120bfa_fsm_state_decl(bfa_ioc, fail, struct bfa_ioc, enum ioc_event);
8b230ed8
RM		 121bfa_fsm_state_decl(bfa_ioc, disabling, struct bfa_ioc, enum ioc_event);
122bfa_fsm_state_decl(bfa_ioc, disabled, struct bfa_ioc, enum ioc_event);
078086f3 123bfa_fsm_state_decl(bfa_ioc, hwfail, struct bfa_ioc, enum ioc_event);
8b230ed8
RM		 124
125static struct bfa_sm_table ioc_sm_table[] = {
1d32f769 126 {BFA_SM(bfa_ioc_sm_uninit), BFA_IOC_UNINIT},
8b230ed8 127 {BFA_SM(bfa_ioc_sm_reset), BFA_IOC_RESET},
1d32f769 128 {BFA_SM(bfa_ioc_sm_enabling), BFA_IOC_ENABLING},
8b230ed8
RM		 129 {BFA_SM(bfa_ioc_sm_getattr), BFA_IOC_GETATTR},
130 {BFA_SM(bfa_ioc_sm_op), BFA_IOC_OPERATIONAL},
1d32f769
RM		 131 {BFA_SM(bfa_ioc_sm_fail_retry), BFA_IOC_INITFAIL},
132 {BFA_SM(bfa_ioc_sm_fail), BFA_IOC_FAIL},
8b230ed8
RM		 133 {BFA_SM(bfa_ioc_sm_disabling), BFA_IOC_DISABLING},
134 {BFA_SM(bfa_ioc_sm_disabled), BFA_IOC_DISABLED},
078086f3 135 {BFA_SM(bfa_ioc_sm_hwfail), BFA_IOC_HWFAIL},
8b230ed8
RM		 136};
137
1d32f769
RM		 138/*
139 * Forward declareations for iocpf state machine
140 */
141static void bfa_iocpf_enable(struct bfa_ioc *ioc);
142static void bfa_iocpf_disable(struct bfa_ioc *ioc);
143static void bfa_iocpf_fail(struct bfa_ioc *ioc);
144static void bfa_iocpf_initfail(struct bfa_ioc *ioc);
145static void bfa_iocpf_getattrfail(struct bfa_ioc *ioc);
146static void bfa_iocpf_stop(struct bfa_ioc *ioc);
147
1aa8b471 148/* IOCPF state machine events */
1d32f769
RM		 149enum iocpf_event {
150 IOCPF_E_ENABLE = 1, /*!< IOCPF enable request */
151 IOCPF_E_DISABLE = 2, /*!< IOCPF disable request */
152 IOCPF_E_STOP = 3, /*!< stop on driver detach */
0120b99c 153 IOCPF_E_FWREADY = 4, /*!< f/w initialization done */
1d32f769
RM		 154 IOCPF_E_FWRSP_ENABLE = 5, /*!< enable f/w response */
155 IOCPF_E_FWRSP_DISABLE = 6, /*!< disable f/w response */
156 IOCPF_E_FAIL = 7, /*!< failure notice by ioc sm */
157 IOCPF_E_INITFAIL = 8, /*!< init fail notice by ioc sm */
158 IOCPF_E_GETATTRFAIL = 9, /*!< init fail notice by ioc sm */
159 IOCPF_E_SEMLOCKED = 10, /*!< h/w semaphore is locked */
160 IOCPF_E_TIMEOUT = 11, /*!< f/w response timeout */
078086f3 161 IOCPF_E_SEM_ERROR = 12, /*!< h/w sem mapping error */
1d32f769
RM		 162};
163
1aa8b471 164/* IOCPF states */
1d32f769
RM		 165enum bfa_iocpf_state {
166 BFA_IOCPF_RESET = 1, /*!< IOC is in reset state */
167 BFA_IOCPF_SEMWAIT = 2, /*!< Waiting for IOC h/w semaphore */
168 BFA_IOCPF_HWINIT = 3, /*!< IOC h/w is being initialized */
169 BFA_IOCPF_READY = 4, /*!< IOCPF is initialized */
170 BFA_IOCPF_INITFAIL = 5, /*!< IOCPF failed */
171 BFA_IOCPF_FAIL = 6, /*!< IOCPF failed */
172 BFA_IOCPF_DISABLING = 7, /*!< IOCPF is being disabled */
173 BFA_IOCPF_DISABLED = 8, /*!< IOCPF is disabled */
174 BFA_IOCPF_FWMISMATCH = 9, /*!< IOC f/w different from drivers */
175};
176
177bfa_fsm_state_decl(bfa_iocpf, reset, struct bfa_iocpf, enum iocpf_event);
178bfa_fsm_state_decl(bfa_iocpf, fwcheck, struct bfa_iocpf, enum iocpf_event);
179bfa_fsm_state_decl(bfa_iocpf, mismatch, struct bfa_iocpf, enum iocpf_event);
180bfa_fsm_state_decl(bfa_iocpf, semwait, struct bfa_iocpf, enum iocpf_event);
181bfa_fsm_state_decl(bfa_iocpf, hwinit, struct bfa_iocpf, enum iocpf_event);
182bfa_fsm_state_decl(bfa_iocpf, enabling, struct bfa_iocpf, enum iocpf_event);
183bfa_fsm_state_decl(bfa_iocpf, ready, struct bfa_iocpf, enum iocpf_event);
184bfa_fsm_state_decl(bfa_iocpf, initfail_sync, struct bfa_iocpf,
185 enum iocpf_event);
186bfa_fsm_state_decl(bfa_iocpf, initfail, struct bfa_iocpf, enum iocpf_event);
187bfa_fsm_state_decl(bfa_iocpf, fail_sync, struct bfa_iocpf, enum iocpf_event);
188bfa_fsm_state_decl(bfa_iocpf, fail, struct bfa_iocpf, enum iocpf_event);
189bfa_fsm_state_decl(bfa_iocpf, disabling, struct bfa_iocpf, enum iocpf_event);
190bfa_fsm_state_decl(bfa_iocpf, disabling_sync, struct bfa_iocpf,
191 enum iocpf_event);
192bfa_fsm_state_decl(bfa_iocpf, disabled, struct bfa_iocpf, enum iocpf_event);
193
194static struct bfa_sm_table iocpf_sm_table[] = {
195 {BFA_SM(bfa_iocpf_sm_reset), BFA_IOCPF_RESET},
196 {BFA_SM(bfa_iocpf_sm_fwcheck), BFA_IOCPF_FWMISMATCH},
197 {BFA_SM(bfa_iocpf_sm_mismatch), BFA_IOCPF_FWMISMATCH},
198 {BFA_SM(bfa_iocpf_sm_semwait), BFA_IOCPF_SEMWAIT},
199 {BFA_SM(bfa_iocpf_sm_hwinit), BFA_IOCPF_HWINIT},
200 {BFA_SM(bfa_iocpf_sm_enabling), BFA_IOCPF_HWINIT},
201 {BFA_SM(bfa_iocpf_sm_ready), BFA_IOCPF_READY},
202 {BFA_SM(bfa_iocpf_sm_initfail_sync), BFA_IOCPF_INITFAIL},
203 {BFA_SM(bfa_iocpf_sm_initfail), BFA_IOCPF_INITFAIL},
204 {BFA_SM(bfa_iocpf_sm_fail_sync), BFA_IOCPF_FAIL},
205 {BFA_SM(bfa_iocpf_sm_fail), BFA_IOCPF_FAIL},
206 {BFA_SM(bfa_iocpf_sm_disabling), BFA_IOCPF_DISABLING},
207 {BFA_SM(bfa_iocpf_sm_disabling_sync), BFA_IOCPF_DISABLING},
208 {BFA_SM(bfa_iocpf_sm_disabled), BFA_IOCPF_DISABLED},
209};
210
1aa8b471 211/* IOC State Machine */
1d32f769 212
1aa8b471 213/* Beginning state. IOC uninit state. */
1d32f769
RM		 214static void
215bfa_ioc_sm_uninit_entry(struct bfa_ioc *ioc)
216{
217}
218
1aa8b471 219/* IOC is in uninit state. */
1d32f769
RM		 220static void
221bfa_ioc_sm_uninit(struct bfa_ioc *ioc, enum ioc_event event)
222{
223 switch (event) {
224 case IOC_E_RESET:
225 bfa_fsm_set_state(ioc, bfa_ioc_sm_reset);
226 break;
227
228 default:
ac51f60f 229 bfa_sm_fault(event);
1d32f769
RM		 230 }
231}
232
1aa8b471 233/* Reset entry actions -- initialize state machine */
8b230ed8
RM		 234static void
235bfa_ioc_sm_reset_entry(struct bfa_ioc *ioc)
236{
1d32f769 237 bfa_fsm_set_state(&ioc->iocpf, bfa_iocpf_sm_reset);
8b230ed8
RM		 238}
239
1aa8b471 240/* IOC is in reset state. */
8b230ed8
RM		 241static void
242bfa_ioc_sm_reset(struct bfa_ioc *ioc, enum ioc_event event)
243{
244 switch (event) {
245 case IOC_E_ENABLE:
1d32f769 246 bfa_fsm_set_state(ioc, bfa_ioc_sm_enabling);
8b230ed8
RM		 247 break;
248
249 case IOC_E_DISABLE:
250 bfa_ioc_disable_comp(ioc);
251 break;
252
253 case IOC_E_DETACH:
1d32f769
RM		 254 bfa_fsm_set_state(ioc, bfa_ioc_sm_uninit);
255 break;
256
257 default:
ac51f60f 258 bfa_sm_fault(event);
1d32f769
RM		 259 }
260}
261
262static void
263bfa_ioc_sm_enabling_entry(struct bfa_ioc *ioc)
264{
265 bfa_iocpf_enable(ioc);
266}
267
1aa8b471 268/* Host IOC function is being enabled, awaiting response from firmware.
1d32f769
RM		 269 * Semaphore is acquired.
270 */
271static void
272bfa_ioc_sm_enabling(struct bfa_ioc *ioc, enum ioc_event event)
273{
274 switch (event) {
275 case IOC_E_ENABLED:
276 bfa_fsm_set_state(ioc, bfa_ioc_sm_getattr);
277 break;
278
f374b361 279 case IOC_E_PFFAILED:
1d32f769
RM		 280 /* !!! fall through !!! */
281 case IOC_E_HWERROR:
282 ioc->cbfn->enable_cbfn(ioc->bfa, BFA_STATUS_IOC_FAILURE);
078086f3 283 bfa_fsm_set_state(ioc, bfa_ioc_sm_fail);
f374b361 284 if (event != IOC_E_PFFAILED)
1d32f769
RM		 285 bfa_iocpf_initfail(ioc);
286 break;
287
078086f3
RM		 288 case IOC_E_HWFAILED:
289 ioc->cbfn->enable_cbfn(ioc->bfa, BFA_STATUS_IOC_FAILURE);
290 bfa_fsm_set_state(ioc, bfa_ioc_sm_hwfail);
291 break;
292
1d32f769
RM		 293 case IOC_E_DISABLE:
294 bfa_fsm_set_state(ioc, bfa_ioc_sm_disabling);
295 break;
296
297 case IOC_E_DETACH:
298 bfa_fsm_set_state(ioc, bfa_ioc_sm_uninit);
299 bfa_iocpf_stop(ioc);
300 break;
301
302 case IOC_E_ENABLE:
8b230ed8
RM		 303 break;
304
305 default:
ac51f60f 306 bfa_sm_fault(event);
8b230ed8
RM		 307 }
308}
309
1aa8b471 310/* Semaphore should be acquired for version check. */
8b230ed8 311static void
1d32f769
RM		 312bfa_ioc_sm_getattr_entry(struct bfa_ioc *ioc)
313{
314 mod_timer(&ioc->ioc_timer, jiffies +
315 msecs_to_jiffies(BFA_IOC_TOV));
316 bfa_ioc_send_getattr(ioc);
317}
318
1aa8b471 319/* IOC configuration in progress. Timer is active. */
1d32f769
RM		 320static void
321bfa_ioc_sm_getattr(struct bfa_ioc *ioc, enum ioc_event event)
322{
323 switch (event) {
324 case IOC_E_FWRSP_GETATTR:
325 del_timer(&ioc->ioc_timer);
1d32f769
RM		 326 bfa_fsm_set_state(ioc, bfa_ioc_sm_op);
327 break;
328
f374b361 329 case IOC_E_PFFAILED:
1d32f769
RM		 330 case IOC_E_HWERROR:
331 del_timer(&ioc->ioc_timer);
332 /* fall through */
333 case IOC_E_TIMEOUT:
334 ioc->cbfn->enable_cbfn(ioc->bfa, BFA_STATUS_IOC_FAILURE);
078086f3 335 bfa_fsm_set_state(ioc, bfa_ioc_sm_fail);
f374b361 336 if (event != IOC_E_PFFAILED)
1d32f769
RM		 337 bfa_iocpf_getattrfail(ioc);
338 break;
339
340 case IOC_E_DISABLE:
341 del_timer(&ioc->ioc_timer);
342 bfa_fsm_set_state(ioc, bfa_ioc_sm_disabling);
343 break;
344
345 case IOC_E_ENABLE:
346 break;
347
348 default:
ac51f60f 349 bfa_sm_fault(event);
1d32f769
RM		 350 }
351}
352
353static void
354bfa_ioc_sm_op_entry(struct bfa_ioc *ioc)
355{
356 ioc->cbfn->enable_cbfn(ioc->bfa, BFA_STATUS_OK);
078086f3 357 bfa_ioc_event_notify(ioc, BFA_IOC_E_ENABLED);
f96c1d24 358 bfa_ioc_hb_monitor(ioc);
1d32f769
RM		 359}
360
361static void
362bfa_ioc_sm_op(struct bfa_ioc *ioc, enum ioc_event event)
363{
364 switch (event) {
365 case IOC_E_ENABLE:
366 break;
367
368 case IOC_E_DISABLE:
369 bfa_ioc_hb_stop(ioc);
370 bfa_fsm_set_state(ioc, bfa_ioc_sm_disabling);
371 break;
372
f374b361 373 case IOC_E_PFFAILED:
1d32f769
RM		 374 case IOC_E_HWERROR:
375 bfa_ioc_hb_stop(ioc);
376 /* !!! fall through !!! */
377 case IOC_E_HBFAIL:
1d32f769
RM		 378 if (ioc->iocpf.auto_recover)
379 bfa_fsm_set_state(ioc, bfa_ioc_sm_fail_retry);
380 else
381 bfa_fsm_set_state(ioc, bfa_ioc_sm_fail);
382
078086f3
RM		 383 bfa_ioc_fail_notify(ioc);
384
f374b361 385 if (event != IOC_E_PFFAILED)
1d32f769
RM		 386 bfa_iocpf_fail(ioc);
387 break;
388
389 default:
ac51f60f 390 bfa_sm_fault(event);
1d32f769
RM		 391 }
392}
393
394static void
395bfa_ioc_sm_disabling_entry(struct bfa_ioc *ioc)
396{
397 bfa_iocpf_disable(ioc);
398}
399
1aa8b471 400/* IOC is being disabled */
1d32f769
RM		 401static void
402bfa_ioc_sm_disabling(struct bfa_ioc *ioc, enum ioc_event event)
403{
404 switch (event) {
405 case IOC_E_DISABLED:
406 bfa_fsm_set_state(ioc, bfa_ioc_sm_disabled);
407 break;
408
409 case IOC_E_HWERROR:
410 /*
411 * No state change. Will move to disabled state
412 * after iocpf sm completes failure processing and
413 * moves to disabled state.
414 */
415 bfa_iocpf_fail(ioc);
416 break;
417
078086f3
RM		 418 case IOC_E_HWFAILED:
419 bfa_fsm_set_state(ioc, bfa_ioc_sm_hwfail);
420 bfa_ioc_disable_comp(ioc);
421 break;
422
1d32f769 423 default:
ac51f60f 424 bfa_sm_fault(event);
1d32f769
RM		 425 }
426}
427
1aa8b471 428/* IOC disable completion entry. */
1d32f769
RM		 429static void
430bfa_ioc_sm_disabled_entry(struct bfa_ioc *ioc)
431{
432 bfa_ioc_disable_comp(ioc);
433}
434
435static void
436bfa_ioc_sm_disabled(struct bfa_ioc *ioc, enum ioc_event event)
437{
438 switch (event) {
439 case IOC_E_ENABLE:
440 bfa_fsm_set_state(ioc, bfa_ioc_sm_enabling);
441 break;
442
443 case IOC_E_DISABLE:
444 ioc->cbfn->disable_cbfn(ioc->bfa);
445 break;
446
447 case IOC_E_DETACH:
448 bfa_fsm_set_state(ioc, bfa_ioc_sm_uninit);
449 bfa_iocpf_stop(ioc);
450 break;
451
452 default:
ac51f60f 453 bfa_sm_fault(event);
1d32f769
RM		 454 }
455}
456
457static void
458bfa_ioc_sm_fail_retry_entry(struct bfa_ioc *ioc)
459{
460}
461
1aa8b471 462/* Hardware initialization retry. */
1d32f769
RM		 463static void
464bfa_ioc_sm_fail_retry(struct bfa_ioc *ioc, enum ioc_event event)
465{
466 switch (event) {
467 case IOC_E_ENABLED:
468 bfa_fsm_set_state(ioc, bfa_ioc_sm_getattr);
469 break;
470
f374b361 471 case IOC_E_PFFAILED:
1d32f769
RM		 472 case IOC_E_HWERROR:
473 /**
474 * Initialization retry failed.
475 */
476 ioc->cbfn->enable_cbfn(ioc->bfa, BFA_STATUS_IOC_FAILURE);
078086f3 477 bfa_fsm_set_state(ioc, bfa_ioc_sm_fail);
f374b361 478 if (event != IOC_E_PFFAILED)
1d32f769
RM		 479 bfa_iocpf_initfail(ioc);
480 break;
481
078086f3
RM		 482 case IOC_E_HWFAILED:
483 ioc->cbfn->enable_cbfn(ioc->bfa, BFA_STATUS_IOC_FAILURE);
484 bfa_fsm_set_state(ioc, bfa_ioc_sm_hwfail);
1d32f769
RM		 485 break;
486
487 case IOC_E_ENABLE:
488 break;
489
490 case IOC_E_DISABLE:
491 bfa_fsm_set_state(ioc, bfa_ioc_sm_disabling);
492 break;
493
494 case IOC_E_DETACH:
495 bfa_fsm_set_state(ioc, bfa_ioc_sm_uninit);
496 bfa_iocpf_stop(ioc);
497 break;
498
499 default:
ac51f60f 500 bfa_sm_fault(event);
1d32f769
RM		 501 }
502}
503
504static void
505bfa_ioc_sm_fail_entry(struct bfa_ioc *ioc)
8b230ed8 506{
1d32f769
RM		 507}
508
1aa8b471 509/* IOC failure. */
1d32f769
RM		 510static void
511bfa_ioc_sm_fail(struct bfa_ioc *ioc, enum ioc_event event)
512{
513 switch (event) {
514 case IOC_E_ENABLE:
515 ioc->cbfn->enable_cbfn(ioc->bfa, BFA_STATUS_IOC_FAILURE);
516 break;
517
518 case IOC_E_DISABLE:
519 bfa_fsm_set_state(ioc, bfa_ioc_sm_disabling);
520 break;
521
522 case IOC_E_DETACH:
523 bfa_fsm_set_state(ioc, bfa_ioc_sm_uninit);
524 bfa_iocpf_stop(ioc);
525 break;
526
527 case IOC_E_HWERROR:
528 /* HB failure notification, ignore. */
529 break;
530
531 default:
ac51f60f 532 bfa_sm_fault(event);
1d32f769
RM		 533 }
534}
535
078086f3
RM		 536static void
537bfa_ioc_sm_hwfail_entry(struct bfa_ioc *ioc)
538{
539}
540
1aa8b471 541/* IOC failure. */
078086f3
RM		 542static void
543bfa_ioc_sm_hwfail(struct bfa_ioc *ioc, enum ioc_event event)
544{
545 switch (event) {
546
547 case IOC_E_ENABLE:
548 ioc->cbfn->enable_cbfn(ioc->bfa, BFA_STATUS_IOC_FAILURE);
549 break;
550
551 case IOC_E_DISABLE:
552 ioc->cbfn->disable_cbfn(ioc->bfa);
553 break;
554
555 case IOC_E_DETACH:
556 bfa_fsm_set_state(ioc, bfa_ioc_sm_uninit);
557 break;
558
559 default:
560 bfa_sm_fault(event);
561 }
562}
563
1aa8b471 564/* IOCPF State Machine */
1d32f769 565
1aa8b471 566/* Reset entry actions -- initialize state machine */
1d32f769
RM		 567static void
568bfa_iocpf_sm_reset_entry(struct bfa_iocpf *iocpf)
569{
078086f3 570 iocpf->fw_mismatch_notified = false;
1d32f769
RM		 571 iocpf->auto_recover = bfa_nw_auto_recover;
572}
573
1aa8b471 574/* Beginning state. IOC is in reset state. */
1d32f769
RM		 575static void
576bfa_iocpf_sm_reset(struct bfa_iocpf *iocpf, enum iocpf_event event)
577{
578 switch (event) {
579 case IOCPF_E_ENABLE:
580 bfa_fsm_set_state(iocpf, bfa_iocpf_sm_fwcheck);
581 break;
582
583 case IOCPF_E_STOP:
584 break;
585
586 default:
ac51f60f 587 bfa_sm_fault(event);
1d32f769
RM		 588 }
589}
590
1aa8b471 591/* Semaphore should be acquired for version check. */
1d32f769
RM		 592static void
593bfa_iocpf_sm_fwcheck_entry(struct bfa_iocpf *iocpf)
594{
d4e16d42 595 bfa_ioc_hw_sem_init(iocpf->ioc);
1d32f769 596 bfa_ioc_hw_sem_get(iocpf->ioc);
8b230ed8
RM		 597}
598
1aa8b471 599/* Awaiting h/w semaphore to continue with version check. */
8b230ed8 600static void
1d32f769 601bfa_iocpf_sm_fwcheck(struct bfa_iocpf *iocpf, enum iocpf_event event)
8b230ed8 602{
1d32f769
RM		 603 struct bfa_ioc *ioc = iocpf->ioc;
604
8b230ed8 605 switch (event) {
1d32f769 606 case IOCPF_E_SEMLOCKED:
8b230ed8 607 if (bfa_ioc_firmware_lock(ioc)) {
79ea6c89 608 if (bfa_ioc_sync_start(ioc)) {
1d32f769
RM		 609 bfa_ioc_sync_join(ioc);
610 bfa_fsm_set_state(iocpf, bfa_iocpf_sm_hwinit);
611 } else {
612 bfa_ioc_firmware_unlock(ioc);
613 bfa_nw_ioc_hw_sem_release(ioc);
614 mod_timer(&ioc->sem_timer, jiffies +
615 msecs_to_jiffies(BFA_IOC_HWSEM_TOV));
616 }
8b230ed8 617 } else {
8a891429 618 bfa_nw_ioc_hw_sem_release(ioc);
1d32f769 619 bfa_fsm_set_state(iocpf, bfa_iocpf_sm_mismatch);
8b230ed8
RM		 620 }
621 break;
622
078086f3
RM		 623 case IOCPF_E_SEM_ERROR:
624 bfa_fsm_set_state(iocpf, bfa_iocpf_sm_fail);
625 bfa_ioc_pf_hwfailed(ioc);
626 break;
627
1d32f769 628 case IOCPF_E_DISABLE:
8b230ed8 629 bfa_ioc_hw_sem_get_cancel(ioc);
1d32f769
RM		 630 bfa_fsm_set_state(iocpf, bfa_iocpf_sm_reset);
631 bfa_ioc_pf_disabled(ioc);
8b230ed8
RM		 632 break;
633
1d32f769
RM		 634 case IOCPF_E_STOP:
635 bfa_ioc_hw_sem_get_cancel(ioc);
636 bfa_fsm_set_state(iocpf, bfa_iocpf_sm_reset);
8b230ed8
RM		 637 break;
638
639 default:
ac51f60f 640 bfa_sm_fault(event);
8b230ed8
RM		 641 }
642}
643
1aa8b471 644/* Notify enable completion callback */
8b230ed8 645static void
1d32f769 646bfa_iocpf_sm_mismatch_entry(struct bfa_iocpf *iocpf)
8b230ed8 647{
1d32f769 648 /* Call only the first time sm enters fwmismatch state. */
23677ce3 649 if (!iocpf->fw_mismatch_notified)
1d32f769
RM		 650 bfa_ioc_pf_fwmismatch(iocpf->ioc);
651
078086f3 652 iocpf->fw_mismatch_notified = true;
1d32f769
RM		 653 mod_timer(&(iocpf->ioc)->iocpf_timer, jiffies +
654 msecs_to_jiffies(BFA_IOC_TOV));
8b230ed8
RM		 655}
656
1aa8b471 657/* Awaiting firmware version match. */
8b230ed8 658static void
1d32f769 659bfa_iocpf_sm_mismatch(struct bfa_iocpf *iocpf, enum iocpf_event event)
8b230ed8 660{
1d32f769
RM		 661 struct bfa_ioc *ioc = iocpf->ioc;
662
8b230ed8 663 switch (event) {
1d32f769
RM		 664 case IOCPF_E_TIMEOUT:
665 bfa_fsm_set_state(iocpf, bfa_iocpf_sm_fwcheck);
8b230ed8
RM		 666 break;
667
1d32f769
RM		 668 case IOCPF_E_DISABLE:
669 del_timer(&ioc->iocpf_timer);
670 bfa_fsm_set_state(iocpf, bfa_iocpf_sm_reset);
671 bfa_ioc_pf_disabled(ioc);
8b230ed8
RM		 672 break;
673
1d32f769
RM		 674 case IOCPF_E_STOP:
675 del_timer(&ioc->iocpf_timer);
676 bfa_fsm_set_state(iocpf, bfa_iocpf_sm_reset);
8b230ed8
RM		 677 break;
678
679 default:
ac51f60f 680 bfa_sm_fault(event);
8b230ed8
RM		 681 }
682}
683
1aa8b471 684/* Request for semaphore. */
8b230ed8 685static void
1d32f769 686bfa_iocpf_sm_semwait_entry(struct bfa_iocpf *iocpf)
8b230ed8 687{
1d32f769 688 bfa_ioc_hw_sem_get(iocpf->ioc);
8b230ed8
RM		 689}
690
1aa8b471 691/* Awaiting semaphore for h/w initialzation. */
8b230ed8 692static void
1d32f769 693bfa_iocpf_sm_semwait(struct bfa_iocpf *iocpf, enum iocpf_event event)
8b230ed8 694{
1d32f769
RM		 695 struct bfa_ioc *ioc = iocpf->ioc;
696
8b230ed8 697 switch (event) {
1d32f769
RM		 698 case IOCPF_E_SEMLOCKED:
699 if (bfa_ioc_sync_complete(ioc)) {
700 bfa_ioc_sync_join(ioc);
701 bfa_fsm_set_state(iocpf, bfa_iocpf_sm_hwinit);
702 } else {
703 bfa_nw_ioc_hw_sem_release(ioc);
704 mod_timer(&ioc->sem_timer, jiffies +
705 msecs_to_jiffies(BFA_IOC_HWSEM_TOV));
706 }
8b230ed8
RM		 707 break;
708
078086f3
RM		 709 case IOCPF_E_SEM_ERROR:
710 bfa_fsm_set_state(iocpf, bfa_iocpf_sm_fail);
711 bfa_ioc_pf_hwfailed(ioc);
712 break;
713
1d32f769 714 case IOCPF_E_DISABLE:
8b230ed8 715 bfa_ioc_hw_sem_get_cancel(ioc);
1d32f769 716 bfa_fsm_set_state(iocpf, bfa_iocpf_sm_disabling_sync);
8b230ed8
RM		 717 break;
718
719 default:
ac51f60f 720 bfa_sm_fault(event);
8b230ed8
RM		 721 }
722}
723
724static void
1d32f769 725bfa_iocpf_sm_hwinit_entry(struct bfa_iocpf *iocpf)
8b230ed8 726{
078086f3 727 iocpf->poll_time = 0;
aafd5c2c 728 bfa_ioc_reset(iocpf->ioc, false);
8b230ed8
RM		 729}
730
1aa8b471 731/* Hardware is being initialized. Interrupts are enabled.
8b230ed8
RM		 732 * Holding hardware semaphore lock.
733 */
734static void
1d32f769 735bfa_iocpf_sm_hwinit(struct bfa_iocpf *iocpf, enum iocpf_event event)
8b230ed8 736{
1d32f769
RM		 737 struct bfa_ioc *ioc = iocpf->ioc;
738
8b230ed8 739 switch (event) {
1d32f769 740 case IOCPF_E_FWREADY:
1d32f769 741 bfa_fsm_set_state(iocpf, bfa_iocpf_sm_enabling);
8b230ed8
RM		 742 break;
743
1d32f769 744 case IOCPF_E_TIMEOUT:
8a891429 745 bfa_nw_ioc_hw_sem_release(ioc);
1d32f769
RM		 746 bfa_ioc_pf_failed(ioc);
747 bfa_fsm_set_state(iocpf, bfa_iocpf_sm_initfail_sync);
8b230ed8
RM		 748 break;
749
1d32f769
RM		 750 case IOCPF_E_DISABLE:
751 del_timer(&ioc->iocpf_timer);
752 bfa_ioc_sync_leave(ioc);
8a891429 753 bfa_nw_ioc_hw_sem_release(ioc);
1d32f769 754 bfa_fsm_set_state(iocpf, bfa_iocpf_sm_disabled);
8b230ed8
RM		 755 break;
756
757 default:
ac51f60f 758 bfa_sm_fault(event);
8b230ed8
RM		 759 }
760}
761
762static void
1d32f769 763bfa_iocpf_sm_enabling_entry(struct bfa_iocpf *iocpf)
8b230ed8 764{
1d32f769
RM		 765 mod_timer(&(iocpf->ioc)->iocpf_timer, jiffies +
766 msecs_to_jiffies(BFA_IOC_TOV));
078086f3
RM		 767 /**
768 * Enable Interrupts before sending fw IOC ENABLE cmd.
769 */
770 iocpf->ioc->cbfn->reset_cbfn(iocpf->ioc->bfa);
1d32f769 771 bfa_ioc_send_enable(iocpf->ioc);
8b230ed8
RM		 772}
773
1aa8b471 774/* Host IOC function is being enabled, awaiting response from firmware.
8b230ed8
RM		 775 * Semaphore is acquired.
776 */
777static void
1d32f769 778bfa_iocpf_sm_enabling(struct bfa_iocpf *iocpf, enum iocpf_event event)
8b230ed8 779{
1d32f769
RM		 780 struct bfa_ioc *ioc = iocpf->ioc;
781
8b230ed8 782 switch (event) {
1d32f769
RM		 783 case IOCPF_E_FWRSP_ENABLE:
784 del_timer(&ioc->iocpf_timer);
8a891429 785 bfa_nw_ioc_hw_sem_release(ioc);
1d32f769 786 bfa_fsm_set_state(iocpf, bfa_iocpf_sm_ready);
8b230ed8
RM		 787 break;
788
1d32f769
RM		 789 case IOCPF_E_INITFAIL:
790 del_timer(&ioc->iocpf_timer);
791 /*
792 * !!! fall through !!!
793 */
794 case IOCPF_E_TIMEOUT:
8a891429 795 bfa_nw_ioc_hw_sem_release(ioc);
1d32f769
RM		 796 if (event == IOCPF_E_TIMEOUT)
797 bfa_ioc_pf_failed(ioc);
798 bfa_fsm_set_state(iocpf, bfa_iocpf_sm_initfail_sync);
8b230ed8
RM		 799 break;
800
1d32f769
RM		 801 case IOCPF_E_DISABLE:
802 del_timer(&ioc->iocpf_timer);
8a891429 803 bfa_nw_ioc_hw_sem_release(ioc);
1d32f769 804 bfa_fsm_set_state(iocpf, bfa_iocpf_sm_disabling);
8b230ed8
RM		 805 break;
806
8b230ed8 807 default:
ac51f60f 808 bfa_sm_fault(event);
8b230ed8
RM		 809 }
810}
811
812static void
1d32f769 813bfa_iocpf_sm_ready_entry(struct bfa_iocpf *iocpf)
8b230ed8 814{
1d32f769 815 bfa_ioc_pf_enabled(iocpf->ioc);
8b230ed8
RM		 816}
817
8b230ed8 818static void
1d32f769 819bfa_iocpf_sm_ready(struct bfa_iocpf *iocpf, enum iocpf_event event)
8b230ed8
RM		 820{
821 switch (event) {
1d32f769
RM		 822 case IOCPF_E_DISABLE:
823 bfa_fsm_set_state(iocpf, bfa_iocpf_sm_disabling);
8b230ed8
RM		 824 break;
825
1d32f769
RM		 826 case IOCPF_E_GETATTRFAIL:
827 bfa_fsm_set_state(iocpf, bfa_iocpf_sm_initfail_sync);
828 break;
8b230ed8 829
1d32f769
RM		 830 case IOCPF_E_FAIL:
831 bfa_fsm_set_state(iocpf, bfa_iocpf_sm_fail_sync);
8b230ed8
RM		 832 break;
833
8b230ed8 834 default:
ac51f60f 835 bfa_sm_fault(event);
8b230ed8
RM		 836 }
837}
838
839static void
1d32f769 840bfa_iocpf_sm_disabling_entry(struct bfa_iocpf *iocpf)
8b230ed8 841{
1d32f769
RM		 842 mod_timer(&(iocpf->ioc)->iocpf_timer, jiffies +
843 msecs_to_jiffies(BFA_IOC_TOV));
844 bfa_ioc_send_disable(iocpf->ioc);
8b230ed8
RM		 845}
846
1aa8b471 847/* IOC is being disabled */
8b230ed8 848static void
1d32f769 849bfa_iocpf_sm_disabling(struct bfa_iocpf *iocpf, enum iocpf_event event)
8b230ed8 850{
1d32f769 851 struct bfa_ioc *ioc = iocpf->ioc;
8b230ed8 852
1d32f769
RM		 853 switch (event) {
854 case IOCPF_E_FWRSP_DISABLE:
1d32f769
RM		 855 del_timer(&ioc->iocpf_timer);
856 bfa_fsm_set_state(iocpf, bfa_iocpf_sm_disabling_sync);
8b230ed8
RM		 857 break;
858
1d32f769
RM		 859 case IOCPF_E_FAIL:
860 del_timer(&ioc->iocpf_timer);
861 /*
862 * !!! fall through !!!
8b230ed8 863 */
8b230ed8 864
1d32f769 865 case IOCPF_E_TIMEOUT:
41ed903a 866 bfa_ioc_set_cur_ioc_fwstate(ioc, BFI_IOC_FAIL);
1d32f769
RM		 867 bfa_fsm_set_state(iocpf, bfa_iocpf_sm_disabling_sync);
868 break;
869
870 case IOCPF_E_FWRSP_ENABLE:
8b230ed8
RM		 871 break;
872
873 default:
ac51f60f 874 bfa_sm_fault(event);
8b230ed8
RM		 875 }
876}
877
878static void
1d32f769 879bfa_iocpf_sm_disabling_sync_entry(struct bfa_iocpf *iocpf)
8b230ed8 880{
1d32f769 881 bfa_ioc_hw_sem_get(iocpf->ioc);
8b230ed8
RM		 882}
883
1aa8b471 884/* IOC hb ack request is being removed. */
8b230ed8 885static void
1d32f769 886bfa_iocpf_sm_disabling_sync(struct bfa_iocpf *iocpf, enum iocpf_event event)
8b230ed8 887{
1d32f769
RM		 888 struct bfa_ioc *ioc = iocpf->ioc;
889
8b230ed8 890 switch (event) {
1d32f769
RM		 891 case IOCPF_E_SEMLOCKED:
892 bfa_ioc_sync_leave(ioc);
893 bfa_nw_ioc_hw_sem_release(ioc);
894 bfa_fsm_set_state(iocpf, bfa_iocpf_sm_disabled);
8b230ed8
RM		 895 break;
896
078086f3
RM		 897 case IOCPF_E_SEM_ERROR:
898 bfa_fsm_set_state(iocpf, bfa_iocpf_sm_fail);
899 bfa_ioc_pf_hwfailed(ioc);
900 break;
901
1d32f769 902 case IOCPF_E_FAIL:
8b230ed8
RM		 903 break;
904
905 default:
ac51f60f 906 bfa_sm_fault(event);
8b230ed8
RM		 907 }
908}
909
1aa8b471 910/* IOC disable completion entry. */
8b230ed8 911static void
1d32f769 912bfa_iocpf_sm_disabled_entry(struct bfa_iocpf *iocpf)
8b230ed8 913{
fdad400f 914 bfa_ioc_mbox_flush(iocpf->ioc);
1d32f769 915 bfa_ioc_pf_disabled(iocpf->ioc);
8b230ed8
RM		 916}
917
918static void
1d32f769 919bfa_iocpf_sm_disabled(struct bfa_iocpf *iocpf, enum iocpf_event event)
8b230ed8 920{
1d32f769 921 struct bfa_ioc *ioc = iocpf->ioc;
8b230ed8 922
1d32f769
RM		 923 switch (event) {
924 case IOCPF_E_ENABLE:
1d32f769 925 bfa_fsm_set_state(iocpf, bfa_iocpf_sm_semwait);
8b230ed8
RM		 926 break;
927
1d32f769 928 case IOCPF_E_STOP:
8b230ed8 929 bfa_ioc_firmware_unlock(ioc);
1d32f769 930 bfa_fsm_set_state(iocpf, bfa_iocpf_sm_reset);
8b230ed8
RM		 931 break;
932
933 default:
ac51f60f 934 bfa_sm_fault(event);
8b230ed8
RM		 935 }
936}
937
938static void
1d32f769 939bfa_iocpf_sm_initfail_sync_entry(struct bfa_iocpf *iocpf)
8b230ed8 940{
7afc5dbd 941 bfa_nw_ioc_debug_save_ftrc(iocpf->ioc);
1d32f769 942 bfa_ioc_hw_sem_get(iocpf->ioc);
8b230ed8
RM		 943}
944
1aa8b471 945/* Hardware initialization failed. */
8b230ed8 946static void
1d32f769 947bfa_iocpf_sm_initfail_sync(struct bfa_iocpf *iocpf, enum iocpf_event event)
8b230ed8 948{
1d32f769
RM		 949 struct bfa_ioc *ioc = iocpf->ioc;
950
8b230ed8 951 switch (event) {
1d32f769
RM		 952 case IOCPF_E_SEMLOCKED:
953 bfa_ioc_notify_fail(ioc);
078086f3 954 bfa_ioc_sync_leave(ioc);
41ed903a 955 bfa_ioc_set_cur_ioc_fwstate(ioc, BFI_IOC_FAIL);
078086f3
RM		 956 bfa_nw_ioc_hw_sem_release(ioc);
957 bfa_fsm_set_state(iocpf, bfa_iocpf_sm_initfail);
958 break;
959
960 case IOCPF_E_SEM_ERROR:
961 bfa_fsm_set_state(iocpf, bfa_iocpf_sm_fail);
962 bfa_ioc_pf_hwfailed(ioc);
8b230ed8
RM		 963 break;
964
1d32f769
RM		 965 case IOCPF_E_DISABLE:
966 bfa_ioc_hw_sem_get_cancel(ioc);
967 bfa_fsm_set_state(iocpf, bfa_iocpf_sm_disabling_sync);
968 break;
969
970 case IOCPF_E_STOP:
971 bfa_ioc_hw_sem_get_cancel(ioc);
8b230ed8 972 bfa_ioc_firmware_unlock(ioc);
1d32f769 973 bfa_fsm_set_state(iocpf, bfa_iocpf_sm_reset);
8b230ed8
RM		 974 break;
975
1d32f769 976 case IOCPF_E_FAIL:
8b230ed8
RM		 977 break;
978
979 default:
ac51f60f 980 bfa_sm_fault(event);
8b230ed8
RM		 981 }
982}
983
984static void
1d32f769 985bfa_iocpf_sm_initfail_entry(struct bfa_iocpf *iocpf)
8b230ed8 986{
1d32f769 987}
8b230ed8 988
1aa8b471 989/* Hardware initialization failed. */
1d32f769
RM		 990static void
991bfa_iocpf_sm_initfail(struct bfa_iocpf *iocpf, enum iocpf_event event)
992{
993 struct bfa_ioc *ioc = iocpf->ioc;
8b230ed8 994
1d32f769
RM		 995 switch (event) {
996 case IOCPF_E_DISABLE:
997 bfa_fsm_set_state(iocpf, bfa_iocpf_sm_disabled);
998 break;
8b230ed8 999
1d32f769
RM		 1000 case IOCPF_E_STOP:
1001 bfa_ioc_firmware_unlock(ioc);
1002 bfa_fsm_set_state(iocpf, bfa_iocpf_sm_reset);
1003 break;
1004
1005 default:
ac51f60f 1006 bfa_sm_fault(event);
8b230ed8 1007 }
1d32f769 1008}
8b230ed8 1009
1d32f769
RM		 1010static void
1011bfa_iocpf_sm_fail_sync_entry(struct bfa_iocpf *iocpf)
1012{
8b230ed8 1013 /**
1d32f769 1014 * Mark IOC as failed in hardware and stop firmware.
8b230ed8 1015 */
1d32f769 1016 bfa_ioc_lpu_stop(iocpf->ioc);
8b230ed8
RM		 1017
1018 /**
1d32f769 1019 * Flush any queued up mailbox requests.
8b230ed8 1020 */
fdad400f 1021 bfa_ioc_mbox_flush(iocpf->ioc);
1d32f769 1022 bfa_ioc_hw_sem_get(iocpf->ioc);
8b230ed8
RM		 1023}
1024
1aa8b471 1025/* IOC is in failed state. */
8b230ed8 1026static void
1d32f769 1027bfa_iocpf_sm_fail_sync(struct bfa_iocpf *iocpf, enum iocpf_event event)
8b230ed8 1028{
1d32f769 1029 struct bfa_ioc *ioc = iocpf->ioc;
8b230ed8 1030
1d32f769
RM		 1031 switch (event) {
1032 case IOCPF_E_SEMLOCKED:
1d32f769
RM		 1033 bfa_ioc_sync_ack(ioc);
1034 bfa_ioc_notify_fail(ioc);
1035 if (!iocpf->auto_recover) {
1036 bfa_ioc_sync_leave(ioc);
41ed903a 1037 bfa_ioc_set_cur_ioc_fwstate(ioc, BFI_IOC_FAIL);
1d32f769
RM		 1038 bfa_nw_ioc_hw_sem_release(ioc);
1039 bfa_fsm_set_state(iocpf, bfa_iocpf_sm_fail);
1040 } else {
1041 if (bfa_ioc_sync_complete(ioc))
1042 bfa_fsm_set_state(iocpf, bfa_iocpf_sm_hwinit);
1043 else {
1044 bfa_nw_ioc_hw_sem_release(ioc);
1045 bfa_fsm_set_state(iocpf, bfa_iocpf_sm_semwait);
1046 }
1047 }
8b230ed8
RM		 1048 break;
1049
078086f3
RM		 1050 case IOCPF_E_SEM_ERROR:
1051 bfa_fsm_set_state(iocpf, bfa_iocpf_sm_fail);
1052 bfa_ioc_pf_hwfailed(ioc);
1053 break;
1054
1d32f769
RM		 1055 case IOCPF_E_DISABLE:
1056 bfa_ioc_hw_sem_get_cancel(ioc);
1057 bfa_fsm_set_state(iocpf, bfa_iocpf_sm_disabling_sync);
8b230ed8
RM		 1058 break;
1059
1d32f769 1060 case IOCPF_E_FAIL:
8b230ed8
RM		 1061 break;
1062
1d32f769 1063 default:
ac51f60f 1064 bfa_sm_fault(event);
1d32f769
RM		 1065 }
1066}
8b230ed8 1067
1d32f769
RM		 1068static void
1069bfa_iocpf_sm_fail_entry(struct bfa_iocpf *iocpf)
1070{
1071}
1072
1aa8b471 1073/* IOC is in failed state. */
1d32f769
RM		 1074static void
1075bfa_iocpf_sm_fail(struct bfa_iocpf *iocpf, enum iocpf_event event)
1076{
1077 switch (event) {
1078 case IOCPF_E_DISABLE:
1079 bfa_fsm_set_state(iocpf, bfa_iocpf_sm_disabled);
8b230ed8 1080 break;
1d32f769 1081
8b230ed8 1082 default:
ac51f60f 1083 bfa_sm_fault(event);
8b230ed8
RM		 1084 }
1085}
1086
1aa8b471 1087/* BFA IOC private functions */
8b230ed8 1088
1aa8b471 1089/* Notify common modules registered for notification. */
8b230ed8 1090static void
bd5a92e9 1091bfa_ioc_event_notify(struct bfa_ioc *ioc, enum bfa_ioc_event event)
8b230ed8 1092{
bd5a92e9 1093 struct bfa_ioc_notify *notify;
8b230ed8 1094
16712c53 1095 list_for_each_entry(notify, &ioc->notify_q, qe)
bd5a92e9 1096 notify->cbfn(notify->cbarg, event);
8b230ed8
RM		 1097}
1098
bd5a92e9
RM		 1099static void
1100bfa_ioc_disable_comp(struct bfa_ioc *ioc)
1101{
1102 ioc->cbfn->disable_cbfn(ioc->bfa);
1103 bfa_ioc_event_notify(ioc, BFA_IOC_E_DISABLED);
1104}
1105
8b230ed8 1106bool
8a891429 1107bfa_nw_ioc_sem_get(void __iomem *sem_reg)
8b230ed8
RM		 1108{
1109 u32 r32;
1110 int cnt = 0;
1111#define BFA_SEM_SPINCNT 3000
1112
1113 r32 = readl(sem_reg);
1114
078086f3 1115 while ((r32 & 1) && (cnt < BFA_SEM_SPINCNT)) {
8b230ed8
RM		 1116 cnt++;
1117 udelay(2);
1118 r32 = readl(sem_reg);
1119 }
1120
078086f3 1121 if (!(r32 & 1))
8b230ed8
RM		 1122 return true;
1123
8b230ed8
RM		 1124 return false;
1125}
1126
1127void
8a891429 1128bfa_nw_ioc_sem_release(void __iomem *sem_reg)
8b230ed8 1129{
1d51a132 1130 readl(sem_reg);
8b230ed8
RM		 1131 writel(1, sem_reg);
1132}
1133
e491c77e
JH		 1134/* Clear fwver hdr */
1135static void
1136bfa_ioc_fwver_clear(struct bfa_ioc *ioc)
1137{
1138 u32 pgnum, pgoff, loff = 0;
1139 int i;
1140
1141 pgnum = PSS_SMEM_PGNUM(ioc->ioc_regs.smem_pg0, loff);
1142 pgoff = PSS_SMEM_PGOFF(loff);
1143 writel(pgnum, ioc->ioc_regs.host_page_num_fn);
1144
1145 for (i = 0; i < (sizeof(struct bfi_ioc_image_hdr) / sizeof(u32)); i++) {
1146 writel(0, ioc->ioc_regs.smem_page_start + loff);
1147 loff += sizeof(u32);
1148 }
1149}
1150
1151
d4e16d42
RM		 1152static void
1153bfa_ioc_hw_sem_init(struct bfa_ioc *ioc)
1154{
1155 struct bfi_ioc_image_hdr fwhdr;
e491c77e
JH		 1156 u32 fwstate, r32;
1157
1158 /* Spin on init semaphore to serialize. */
1159 r32 = readl(ioc->ioc_regs.ioc_init_sem_reg);
1160 while (r32 & 0x1) {
1161 udelay(20);
1162 r32 = readl(ioc->ioc_regs.ioc_init_sem_reg);
1163 }
d4e16d42 1164
41ed903a 1165 fwstate = bfa_ioc_get_cur_ioc_fwstate(ioc);
e491c77e
JH		 1166 if (fwstate == BFI_IOC_UNINIT) {
1167 writel(1, ioc->ioc_regs.ioc_init_sem_reg);
d4e16d42 1168 return;
e491c77e 1169 }
d4e16d42
RM		 1170
1171 bfa_nw_ioc_fwver_get(ioc, &fwhdr);
1172
e491c77e
JH		 1173 if (swab32(fwhdr.exec) == BFI_FWBOOT_TYPE_NORMAL) {
1174 writel(1, ioc->ioc_regs.ioc_init_sem_reg);
d4e16d42 1175 return;
e491c77e 1176 }
d4e16d42 1177
e491c77e 1178 bfa_ioc_fwver_clear(ioc);
41ed903a
RM		 1179 bfa_ioc_set_cur_ioc_fwstate(ioc, BFI_IOC_UNINIT);
1180 bfa_ioc_set_alt_ioc_fwstate(ioc, BFI_IOC_UNINIT);
d4e16d42
RM		 1181
1182 /*
1183 * Try to lock and then unlock the semaphore.
1184 */
1185 readl(ioc->ioc_regs.ioc_sem_reg);
1186 writel(1, ioc->ioc_regs.ioc_sem_reg);
e491c77e
JH		 1187
1188 /* Unlock init semaphore */
1189 writel(1, ioc->ioc_regs.ioc_init_sem_reg);
d4e16d42
RM		 1190}
1191
8b230ed8
RM		 1192static void
1193bfa_ioc_hw_sem_get(struct bfa_ioc *ioc)
1194{
1195 u32 r32;
1196
1197 /**
1198 * First read to the semaphore register will return 0, subsequent reads
1199 * will return 1. Semaphore is released by writing 1 to the register
1200 */
1201 r32 = readl(ioc->ioc_regs.ioc_sem_reg);
078086f3
RM		 1202 if (r32 == ~0) {
1203 bfa_fsm_send_event(&ioc->iocpf, IOCPF_E_SEM_ERROR);
1204 return;
1205 }
1206 if (!(r32 & 1)) {
1d32f769 1207 bfa_fsm_send_event(&ioc->iocpf, IOCPF_E_SEMLOCKED);
8b230ed8
RM		 1208 return;
1209 }
1210
1211 mod_timer(&ioc->sem_timer, jiffies +
1212 msecs_to_jiffies(BFA_IOC_HWSEM_TOV));
1213}
1214
1215void
8a891429 1216bfa_nw_ioc_hw_sem_release(struct bfa_ioc *ioc)
8b230ed8
RM		 1217{
1218 writel(1, ioc->ioc_regs.ioc_sem_reg);
1219}
1220
1221static void
1222bfa_ioc_hw_sem_get_cancel(struct bfa_ioc *ioc)
1223{
1224 del_timer(&ioc->sem_timer);
1225}
1226
1aa8b471 1227/* Initialize LPU local memory (aka secondary memory / SRAM) */
8b230ed8
RM		 1228static void
1229bfa_ioc_lmem_init(struct bfa_ioc *ioc)
1230{
1231 u32 pss_ctl;
1232 int i;
1233#define PSS_LMEM_INIT_TIME 10000
1234
1235 pss_ctl = readl(ioc->ioc_regs.pss_ctl_reg);
1236 pss_ctl &= ~__PSS_LMEM_RESET;
1237 pss_ctl |= __PSS_LMEM_INIT_EN;
1238
1239 /*
1240 * i2c workaround 12.5khz clock
1241 */
1242 pss_ctl |= __PSS_I2C_CLK_DIV(3UL);
1243 writel(pss_ctl, ioc->ioc_regs.pss_ctl_reg);
1244
1245 /**
1246 * wait for memory initialization to be complete
1247 */
1248 i = 0;
1249 do {
1250 pss_ctl = readl(ioc->ioc_regs.pss_ctl_reg);
1251 i++;
1252 } while (!(pss_ctl & __PSS_LMEM_INIT_DONE) && (i < PSS_LMEM_INIT_TIME));
1253
1254 /**
1255 * If memory initialization is not successful, IOC timeout will catch
1256 * such failures.
1257 */
1258 BUG_ON(!(pss_ctl & __PSS_LMEM_INIT_DONE));
1259
1260 pss_ctl &= ~(__PSS_LMEM_INIT_DONE | __PSS_LMEM_INIT_EN);
1261 writel(pss_ctl, ioc->ioc_regs.pss_ctl_reg);
1262}
1263
1264static void
1265bfa_ioc_lpu_start(struct bfa_ioc *ioc)
1266{
1267 u32 pss_ctl;
1268
1269 /**
1270 * Take processor out of reset.
1271 */
1272 pss_ctl = readl(ioc->ioc_regs.pss_ctl_reg);
1273 pss_ctl &= ~__PSS_LPU0_RESET;
1274
1275 writel(pss_ctl, ioc->ioc_regs.pss_ctl_reg);
1276}
1277
1278static void
1279bfa_ioc_lpu_stop(struct bfa_ioc *ioc)
1280{
1281 u32 pss_ctl;
1282
1283 /**
1284 * Put processors in reset.
1285 */
1286 pss_ctl = readl(ioc->ioc_regs.pss_ctl_reg);
1287 pss_ctl |= (__PSS_LPU0_RESET | __PSS_LPU1_RESET);
1288
1289 writel(pss_ctl, ioc->ioc_regs.pss_ctl_reg);
1290}
1291
1aa8b471 1292/* Get driver and firmware versions. */
8b230ed8 1293void
8a891429 1294bfa_nw_ioc_fwver_get(struct bfa_ioc *ioc, struct bfi_ioc_image_hdr *fwhdr)
8b230ed8 1295{
58598542 1296 u32 pgnum;
8b230ed8
RM		 1297 u32 loff = 0;
1298 int i;
1299 u32 *fwsig = (u32 *) fwhdr;
1300
1301 pgnum = bfa_ioc_smem_pgnum(ioc, loff);
8b230ed8
RM		 1302 writel(pgnum, ioc->ioc_regs.host_page_num_fn);
1303
1304 for (i = 0; i < (sizeof(struct bfi_ioc_image_hdr) / sizeof(u32));
1305 i++) {
1306 fwsig[i] =
ebb56d37 1307 swab32(readl(loff + ioc->ioc_regs.smem_page_start));
8b230ed8
RM		 1308 loff += sizeof(u32);
1309 }
1310}
1311
c107ba17
RM		 1312static bool
1313bfa_ioc_fwver_md5_check(struct bfi_ioc_image_hdr *fwhdr_1,
1314 struct bfi_ioc_image_hdr *fwhdr_2)
1315{
1316 int i;
1317
1318 for (i = 0; i < BFI_IOC_MD5SUM_SZ; i++) {
1319 if (fwhdr_1->md5sum[i] != fwhdr_2->md5sum[i])
1320 return false;
1321 }
1322
1323 return true;
1324}
1325
dbedd44e 1326/* Returns TRUE if major minor and maintenance are same.
c107ba17
RM		 1327 * If patch version are same, check for MD5 Checksum to be same.
1328 */
1329static bool
1330bfa_ioc_fw_ver_compatible(struct bfi_ioc_image_hdr *drv_fwhdr,
1331 struct bfi_ioc_image_hdr *fwhdr_to_cmp)
1332{
1333 if (drv_fwhdr->signature != fwhdr_to_cmp->signature)
1334 return false;
1335 if (drv_fwhdr->fwver.major != fwhdr_to_cmp->fwver.major)
1336 return false;
1337 if (drv_fwhdr->fwver.minor != fwhdr_to_cmp->fwver.minor)
1338 return false;
1339 if (drv_fwhdr->fwver.maint != fwhdr_to_cmp->fwver.maint)
1340 return false;
1341 if (drv_fwhdr->fwver.patch == fwhdr_to_cmp->fwver.patch &&
1342 drv_fwhdr->fwver.phase == fwhdr_to_cmp->fwver.phase &&
1343 drv_fwhdr->fwver.build == fwhdr_to_cmp->fwver.build)
1344 return bfa_ioc_fwver_md5_check(drv_fwhdr, fwhdr_to_cmp);
1345
1346 return true;
1347}
1348
1349static bool
1350bfa_ioc_flash_fwver_valid(struct bfi_ioc_image_hdr *flash_fwhdr)
1351{
1352 if (flash_fwhdr->fwver.major == 0 || flash_fwhdr->fwver.major == 0xFF)
1353 return false;
1354
1355 return true;
1356}
1357
1358static bool
1359fwhdr_is_ga(struct bfi_ioc_image_hdr *fwhdr)
1360{
1361 if (fwhdr->fwver.phase == 0 &&
1362 fwhdr->fwver.build == 0)
1363 return false;
1364
1365 return true;
1366}
1367
1368/* Returns TRUE if both are compatible and patch of fwhdr_to_cmp is better. */
1369static enum bfi_ioc_img_ver_cmp
1370bfa_ioc_fw_ver_patch_cmp(struct bfi_ioc_image_hdr *base_fwhdr,
1371 struct bfi_ioc_image_hdr *fwhdr_to_cmp)
1372{
93719d26 1373 if (!bfa_ioc_fw_ver_compatible(base_fwhdr, fwhdr_to_cmp))
c107ba17
RM		 1374 return BFI_IOC_IMG_VER_INCOMP;
1375
1376 if (fwhdr_to_cmp->fwver.patch > base_fwhdr->fwver.patch)
1377 return BFI_IOC_IMG_VER_BETTER;
1378 else if (fwhdr_to_cmp->fwver.patch < base_fwhdr->fwver.patch)
1379 return BFI_IOC_IMG_VER_OLD;
1380
1381 /* GA takes priority over internal builds of the same patch stream.
1382 * At this point major minor maint and patch numbers are same.
1383 */
93719d26 1384 if (fwhdr_is_ga(base_fwhdr))
c107ba17
RM		 1385 if (fwhdr_is_ga(fwhdr_to_cmp))
1386 return BFI_IOC_IMG_VER_SAME;
1387 else
1388 return BFI_IOC_IMG_VER_OLD;
1389 else
1390 if (fwhdr_is_ga(fwhdr_to_cmp))
1391 return BFI_IOC_IMG_VER_BETTER;
1392
1393 if (fwhdr_to_cmp->fwver.phase > base_fwhdr->fwver.phase)
1394 return BFI_IOC_IMG_VER_BETTER;
1395 else if (fwhdr_to_cmp->fwver.phase < base_fwhdr->fwver.phase)
1396 return BFI_IOC_IMG_VER_OLD;
1397
1398 if (fwhdr_to_cmp->fwver.build > base_fwhdr->fwver.build)
1399 return BFI_IOC_IMG_VER_BETTER;
1400 else if (fwhdr_to_cmp->fwver.build < base_fwhdr->fwver.build)
1401 return BFI_IOC_IMG_VER_OLD;
1402
1403 /* All Version Numbers are equal.
1404 * Md5 check to be done as a part of compatibility check.
1405 */
1406 return BFI_IOC_IMG_VER_SAME;
1407}
1408
1409/* register definitions */
1410#define FLI_CMD_REG 0x0001d000
1411#define FLI_WRDATA_REG 0x0001d00c
1412#define FLI_RDDATA_REG 0x0001d010
1413#define FLI_ADDR_REG 0x0001d004
1414#define FLI_DEV_STATUS_REG 0x0001d014
1415
1416#define BFA_FLASH_FIFO_SIZE 128 /* fifo size */
1417#define BFA_FLASH_CHECK_MAX 10000 /* max # of status check */
1418#define BFA_FLASH_BLOCKING_OP_MAX 1000000 /* max # of blocking op check */
1419#define BFA_FLASH_WIP_MASK 0x01 /* write in progress bit mask */
1420
1421#define NFC_STATE_RUNNING 0x20000001
1422#define NFC_STATE_PAUSED 0x00004560
1423#define NFC_VER_VALID 0x147
1424
1425enum bfa_flash_cmd {
1426 BFA_FLASH_FAST_READ = 0x0b, /* fast read */
1427 BFA_FLASH_WRITE_ENABLE = 0x06, /* write enable */
1428 BFA_FLASH_SECTOR_ERASE = 0xd8, /* sector erase */
1429 BFA_FLASH_WRITE = 0x02, /* write */
1430 BFA_FLASH_READ_STATUS = 0x05, /* read status */
1431};
1432
1433/* hardware error definition */
1434enum bfa_flash_err {
1435 BFA_FLASH_NOT_PRESENT = -1, /*!< flash not present */
1436 BFA_FLASH_UNINIT = -2, /*!< flash not initialized */
1437 BFA_FLASH_BAD = -3, /*!< flash bad */
1438 BFA_FLASH_BUSY = -4, /*!< flash busy */
1439 BFA_FLASH_ERR_CMD_ACT = -5, /*!< command active never cleared */
1440 BFA_FLASH_ERR_FIFO_CNT = -6, /*!< fifo count never cleared */
1441 BFA_FLASH_ERR_WIP = -7, /*!< write-in-progress never cleared */
1442 BFA_FLASH_ERR_TIMEOUT = -8, /*!< fli timeout */
1443 BFA_FLASH_ERR_LEN = -9, /*!< invalid length */
1444};
1445
1446/* flash command register data structure */
1447union bfa_flash_cmd_reg {
1448 struct {
1449#ifdef __BIG_ENDIAN
1450 u32 act:1;
1451 u32 rsv:1;
1452 u32 write_cnt:9;
1453 u32 read_cnt:9;
1454 u32 addr_cnt:4;
1455 u32 cmd:8;
1456#else
1457 u32 cmd:8;
1458 u32 addr_cnt:4;
1459 u32 read_cnt:9;
1460 u32 write_cnt:9;
1461 u32 rsv:1;
1462 u32 act:1;
1463#endif
1464 } r;
1465 u32 i;
1466};
1467
1468/* flash device status register data structure */
1469union bfa_flash_dev_status_reg {
1470 struct {
1471#ifdef __BIG_ENDIAN
1472 u32 rsv:21;
1473 u32 fifo_cnt:6;
1474 u32 busy:1;
1475 u32 init_status:1;
1476 u32 present:1;
1477 u32 bad:1;
1478 u32 good:1;
1479#else
1480 u32 good:1;
1481 u32 bad:1;
1482 u32 present:1;
1483 u32 init_status:1;
1484 u32 busy:1;
1485 u32 fifo_cnt:6;
1486 u32 rsv:21;
1487#endif
1488 } r;
1489 u32 i;
1490};
1491
1492/* flash address register data structure */
1493union bfa_flash_addr_reg {
1494 struct {
1495#ifdef __BIG_ENDIAN
1496 u32 addr:24;
1497 u32 dummy:8;
1498#else
1499 u32 dummy:8;
1500 u32 addr:24;
1501#endif
1502 } r;
1503 u32 i;
1504};
1505
1506/* Flash raw private functions */
1507static void
1508bfa_flash_set_cmd(void __iomem *pci_bar, u8 wr_cnt,
1509 u8 rd_cnt, u8 ad_cnt, u8 op)
1510{
1511 union bfa_flash_cmd_reg cmd;
1512
1513 cmd.i = 0;
1514 cmd.r.act = 1;
1515 cmd.r.write_cnt = wr_cnt;
1516 cmd.r.read_cnt = rd_cnt;
1517 cmd.r.addr_cnt = ad_cnt;
1518 cmd.r.cmd = op;
1519 writel(cmd.i, (pci_bar + FLI_CMD_REG));
1520}
1521
1522static void
1523bfa_flash_set_addr(void __iomem *pci_bar, u32 address)
1524{
1525 union bfa_flash_addr_reg addr;
1526
1527 addr.r.addr = address & 0x00ffffff;
1528 addr.r.dummy = 0;
1529 writel(addr.i, (pci_bar + FLI_ADDR_REG));
1530}
1531
1532static int
1533bfa_flash_cmd_act_check(void __iomem *pci_bar)
1534{
1535 union bfa_flash_cmd_reg cmd;
1536
1537 cmd.i = readl(pci_bar + FLI_CMD_REG);
1538
1539 if (cmd.r.act)
1540 return BFA_FLASH_ERR_CMD_ACT;
1541
1542 return 0;
1543}
1544
1545/* Flush FLI data fifo. */
4c52b1da 1546static int
c107ba17
RM		 1547bfa_flash_fifo_flush(void __iomem *pci_bar)
1548{
1549 u32 i;
1550 u32 t;
1551 union bfa_flash_dev_status_reg dev_status;
1552
1553 dev_status.i = readl(pci_bar + FLI_DEV_STATUS_REG);
1554
1555 if (!dev_status.r.fifo_cnt)
1556 return 0;
1557
1558 /* fifo counter in terms of words */
1559 for (i = 0; i < dev_status.r.fifo_cnt; i++)
1560 t = readl(pci_bar + FLI_RDDATA_REG);
1561
1562 /* Check the device status. It may take some time. */
1563 for (i = 0; i < BFA_FLASH_CHECK_MAX; i++) {
1564 dev_status.i = readl(pci_bar + FLI_DEV_STATUS_REG);
1565 if (!dev_status.r.fifo_cnt)
1566 break;
1567 }
1568
1569 if (dev_status.r.fifo_cnt)
1570 return BFA_FLASH_ERR_FIFO_CNT;
1571
1572 return 0;
1573}
1574
1575/* Read flash status. */
4c52b1da 1576static int
c107ba17
RM		 1577bfa_flash_status_read(void __iomem *pci_bar)
1578{
1579 union bfa_flash_dev_status_reg dev_status;
4c52b1da 1580 int status;
c107ba17
RM		 1581 u32 ret_status;
1582 int i;
1583
1584 status = bfa_flash_fifo_flush(pci_bar);
1585 if (status < 0)
1586 return status;
1587
1588 bfa_flash_set_cmd(pci_bar, 0, 4, 0, BFA_FLASH_READ_STATUS);
1589
1590 for (i = 0; i < BFA_FLASH_CHECK_MAX; i++) {
1591 status = bfa_flash_cmd_act_check(pci_bar);
1592 if (!status)
1593 break;
1594 }
1595
1596 if (status)
1597 return status;
1598
1599 dev_status.i = readl(pci_bar + FLI_DEV_STATUS_REG);
1600 if (!dev_status.r.fifo_cnt)
1601 return BFA_FLASH_BUSY;
1602
1603 ret_status = readl(pci_bar + FLI_RDDATA_REG);
1604 ret_status >>= 24;
1605
1606 status = bfa_flash_fifo_flush(pci_bar);
1607 if (status < 0)
1608 return status;
1609
1610 return ret_status;
1611}
1612
1613/* Start flash read operation. */
4c52b1da 1614static int
c107ba17
RM		 1615bfa_flash_read_start(void __iomem *pci_bar, u32 offset, u32 len,
1616 char *buf)
1617{
4c52b1da 1618 int status;
c107ba17
RM		 1619
1620 /* len must be mutiple of 4 and not exceeding fifo size */
1621 if (len == 0 || len > BFA_FLASH_FIFO_SIZE || (len & 0x03) != 0)
1622 return BFA_FLASH_ERR_LEN;
1623
1624 /* check status */
1625 status = bfa_flash_status_read(pci_bar);
1626 if (status == BFA_FLASH_BUSY)
1627 status = bfa_flash_status_read(pci_bar);
1628
1629 if (status < 0)
1630 return status;
1631
1632 /* check if write-in-progress bit is cleared */
1633 if (status & BFA_FLASH_WIP_MASK)
1634 return BFA_FLASH_ERR_WIP;
1635
1636 bfa_flash_set_addr(pci_bar, offset);
1637
1638 bfa_flash_set_cmd(pci_bar, 0, (u8)len, 4, BFA_FLASH_FAST_READ);
1639
1640 return 0;
1641}
1642
1643/* Check flash read operation. */
1644static u32
1645bfa_flash_read_check(void __iomem *pci_bar)
1646{
1647 if (bfa_flash_cmd_act_check(pci_bar))
1648 return 1;
1649
1650 return 0;
1651}
1652
1653/* End flash read operation. */
1654static void
1655bfa_flash_read_end(void __iomem *pci_bar, u32 len, char *buf)
1656{
1657 u32 i;
1658
1659 /* read data fifo up to 32 words */
1660 for (i = 0; i < len; i += 4) {
1661 u32 w = readl(pci_bar + FLI_RDDATA_REG);
1662 *((u32 *)(buf + i)) = swab32(w);
1663 }
1664
1665 bfa_flash_fifo_flush(pci_bar);
1666}
1667
1668/* Perform flash raw read. */
1669
1670#define FLASH_BLOCKING_OP_MAX 500
1671#define FLASH_SEM_LOCK_REG 0x18820
1672
1673static int
1674bfa_raw_sem_get(void __iomem *bar)
1675{
1676 int locked;
1677
ebb56d37 1678 locked = readl(bar + FLASH_SEM_LOCK_REG);
c107ba17
RM		 1679
1680 return !locked;
1681}
1682
1683static enum bfa_status
1684bfa_flash_sem_get(void __iomem *bar)
1685{
1686 u32 n = FLASH_BLOCKING_OP_MAX;
1687
1688 while (!bfa_raw_sem_get(bar)) {
1689 if (--n <= 0)
1690 return BFA_STATUS_BADFLASH;
bc48bc80 1691 mdelay(10);
c107ba17
RM		 1692 }
1693 return BFA_STATUS_OK;
1694}
1695
1696static void
1697bfa_flash_sem_put(void __iomem *bar)
1698{
1699 writel(0, (bar + FLASH_SEM_LOCK_REG));
1700}
1701
1702static enum bfa_status
1703bfa_flash_raw_read(void __iomem *pci_bar, u32 offset, char *buf,
1704 u32 len)
1705{
4c52b1da
AH		 1706 u32 n;
1707 int status;
c107ba17
RM		 1708 u32 off, l, s, residue, fifo_sz;
1709
1710 residue = len;
1711 off = 0;
1712 fifo_sz = BFA_FLASH_FIFO_SIZE;
1713 status = bfa_flash_sem_get(pci_bar);
1714 if (status != BFA_STATUS_OK)
1715 return status;
1716
1717 while (residue) {
1718 s = offset + off;
1719 n = s / fifo_sz;
1720 l = (n + 1) * fifo_sz - s;
1721 if (l > residue)
1722 l = residue;
1723
1724 status = bfa_flash_read_start(pci_bar, offset + off, l,
1725 &buf[off]);
1726 if (status < 0) {
1727 bfa_flash_sem_put(pci_bar);
1728 return BFA_STATUS_FAILED;
1729 }
1730
1731 n = BFA_FLASH_BLOCKING_OP_MAX;
1732 while (bfa_flash_read_check(pci_bar)) {
1733 if (--n <= 0) {
1734 bfa_flash_sem_put(pci_bar);
1735 return BFA_STATUS_FAILED;
1736 }
1737 }
1738
1739 bfa_flash_read_end(pci_bar, l, &buf[off]);
1740
1741 residue -= l;
1742 off += l;
1743 }
1744 bfa_flash_sem_put(pci_bar);
1745
1746 return BFA_STATUS_OK;
1747}
1748
c107ba17
RM		 1749#define BFA_FLASH_PART_FWIMG_ADDR 0x100000 /* fw image address */
1750
2fd888a5 1751static enum bfa_status
c107ba17
RM		 1752bfa_nw_ioc_flash_img_get_chnk(struct bfa_ioc *ioc, u32 off,
1753 u32 *fwimg)
1754{
1755 return bfa_flash_raw_read(ioc->pcidev.pci_bar_kva,
1756 BFA_FLASH_PART_FWIMG_ADDR + (off * sizeof(u32)),
1757 (char *)fwimg, BFI_FLASH_CHUNK_SZ);
1758}
1759
1760static enum bfi_ioc_img_ver_cmp
1761bfa_ioc_flash_fwver_cmp(struct bfa_ioc *ioc,
1762 struct bfi_ioc_image_hdr *base_fwhdr)
1763{
1764 struct bfi_ioc_image_hdr *flash_fwhdr;
1765 enum bfa_status status;
1766 u32 fwimg[BFI_FLASH_CHUNK_SZ_WORDS];
1767
1768 status = bfa_nw_ioc_flash_img_get_chnk(ioc, 0, fwimg);
1769 if (status != BFA_STATUS_OK)
1770 return BFI_IOC_IMG_VER_INCOMP;
1771
1772 flash_fwhdr = (struct bfi_ioc_image_hdr *)fwimg;
1773 if (bfa_ioc_flash_fwver_valid(flash_fwhdr))
1774 return bfa_ioc_fw_ver_patch_cmp(base_fwhdr, flash_fwhdr);
1775 else
1776 return BFI_IOC_IMG_VER_INCOMP;
1777}
1778
1779/**
1780 * Returns TRUE if driver is willing to work with current smem f/w version.
1781 */
8b230ed8 1782bool
8a891429 1783bfa_nw_ioc_fwver_cmp(struct bfa_ioc *ioc, struct bfi_ioc_image_hdr *fwhdr)
8b230ed8
RM		 1784{
1785 struct bfi_ioc_image_hdr *drv_fwhdr;
c107ba17 1786 enum bfi_ioc_img_ver_cmp smem_flash_cmp, drv_smem_cmp;
8b230ed8
RM		 1787
1788 drv_fwhdr = (struct bfi_ioc_image_hdr *)
078086f3 1789 bfa_cb_image_get_chunk(bfa_ioc_asic_gen(ioc), 0);
8b230ed8 1790
c107ba17
RM		 1791 /* If smem is incompatible or old, driver should not work with it. */
1792 drv_smem_cmp = bfa_ioc_fw_ver_patch_cmp(drv_fwhdr, fwhdr);
1793 if (drv_smem_cmp == BFI_IOC_IMG_VER_INCOMP ||
1794 drv_smem_cmp == BFI_IOC_IMG_VER_OLD) {
1795 return false;
8b230ed8
RM		 1796 }
1797
c107ba17
RM		 1798 /* IF Flash has a better F/W than smem do not work with smem.
1799 * If smem f/w == flash f/w, as smem f/w not old | incmp, work with it.
1800 * If Flash is old or incomp work with smem iff smem f/w == drv f/w.
1801 */
1802 smem_flash_cmp = bfa_ioc_flash_fwver_cmp(ioc, fwhdr);
1803
1804 if (smem_flash_cmp == BFI_IOC_IMG_VER_BETTER)
1805 return false;
1806 else if (smem_flash_cmp == BFI_IOC_IMG_VER_SAME)
1807 return true;
1808 else
1809 return (drv_smem_cmp == BFI_IOC_IMG_VER_SAME) ?
1810 true : false;
8b230ed8
RM		 1811}
1812
1aa8b471 1813/* Return true if current running version is valid. Firmware signature and
8b230ed8
RM		 1814 * execution context (driver/bios) must match.
1815 */
1816static bool
79ea6c89 1817bfa_ioc_fwver_valid(struct bfa_ioc *ioc, u32 boot_env)
8b230ed8 1818{
c107ba17 1819 struct bfi_ioc_image_hdr fwhdr;
8b230ed8 1820
8a891429 1821 bfa_nw_ioc_fwver_get(ioc, &fwhdr);
078086f3 1822 if (swab32(fwhdr.bootenv) != boot_env)
8b230ed8
RM		 1823 return false;
1824
8a891429 1825 return bfa_nw_ioc_fwver_cmp(ioc, &fwhdr);
8b230ed8
RM		 1826}
1827
1aa8b471 1828/* Conditionally flush any pending message from firmware at start. */
8b230ed8
RM		 1829static void
1830bfa_ioc_msgflush(struct bfa_ioc *ioc)
1831{
1832 u32 r32;
1833
1834 r32 = readl(ioc->ioc_regs.lpu_mbox_cmd);
1835 if (r32)
1836 writel(1, ioc->ioc_regs.lpu_mbox_cmd);
1837}
1838
8b230ed8
RM		 1839static void
1840bfa_ioc_hwinit(struct bfa_ioc *ioc, bool force)
1841{
1842 enum bfi_ioc_state ioc_fwstate;
1843 bool fwvalid;
79ea6c89 1844 u32 boot_env;
8b230ed8 1845
41ed903a 1846 ioc_fwstate = bfa_ioc_get_cur_ioc_fwstate(ioc);
8b230ed8
RM		 1847
1848 if (force)
1849 ioc_fwstate = BFI_IOC_UNINIT;
1850
078086f3
RM		 1851 boot_env = BFI_FWBOOT_ENV_OS;
1852
8b230ed8
RM		 1853 /**
1854 * check if firmware is valid
1855 */
1856 fwvalid = (ioc_fwstate == BFI_IOC_UNINIT) ?
79ea6c89 1857 false : bfa_ioc_fwver_valid(ioc, boot_env);
8b230ed8
RM		 1858
1859 if (!fwvalid) {
c107ba17
RM		 1860 if (bfa_ioc_boot(ioc, BFI_FWBOOT_TYPE_NORMAL, boot_env) ==
1861 BFA_STATUS_OK)
1862 bfa_ioc_poll_fwinit(ioc);
1863
8b230ed8
RM		 1864 return;
1865 }
1866
1867 /**
1868 * If hardware initialization is in progress (initialized by other IOC),
1869 * just wait for an initialization completion interrupt.
1870 */
1871 if (ioc_fwstate == BFI_IOC_INITING) {
078086f3 1872 bfa_ioc_poll_fwinit(ioc);
8b230ed8
RM		 1873 return;
1874 }
1875
1876 /**
1877 * If IOC function is disabled and firmware version is same,
1878 * just re-enable IOC.
8b230ed8 1879 */
2c7d3821 1880 if (ioc_fwstate == BFI_IOC_DISABLED || ioc_fwstate == BFI_IOC_OP) {
8b230ed8
RM		 1881 /**
1882 * When using MSI-X any pending firmware ready event should
1883 * be flushed. Otherwise MSI-X interrupts are not delivered.
1884 */
1885 bfa_ioc_msgflush(ioc);
1d32f769 1886 bfa_fsm_send_event(&ioc->iocpf, IOCPF_E_FWREADY);
8b230ed8
RM		 1887 return;
1888 }
1889
1890 /**
1891 * Initialize the h/w for any other states.
1892 */
c107ba17
RM		 1893 if (bfa_ioc_boot(ioc, BFI_FWBOOT_TYPE_NORMAL, boot_env) ==
1894 BFA_STATUS_OK)
1895 bfa_ioc_poll_fwinit(ioc);
8b230ed8
RM		 1896}
1897
1898void
ad24d6f0 1899bfa_nw_ioc_timeout(struct bfa_ioc *ioc)
8b230ed8 1900{
8b230ed8
RM		 1901 bfa_fsm_send_event(ioc, IOC_E_TIMEOUT);
1902}
1903
8a891429 1904static void
8b230ed8
RM		 1905bfa_ioc_mbox_send(struct bfa_ioc *ioc, void *ioc_msg, int len)
1906{
1907 u32 *msgp = (u32 *) ioc_msg;
1908 u32 i;
1909
1910 BUG_ON(!(len <= BFI_IOC_MSGLEN_MAX));
1911
1912 /*
1913 * first write msg to mailbox registers
1914 */
1915 for (i = 0; i < len / sizeof(u32); i++)
1916 writel(cpu_to_le32(msgp[i]),
1917 ioc->ioc_regs.hfn_mbox + i * sizeof(u32));
1918
1919 for (; i < BFI_IOC_MSGLEN_MAX / sizeof(u32); i++)
1920 writel(0, ioc->ioc_regs.hfn_mbox + i * sizeof(u32));
1921
1922 /*
1923 * write 1 to mailbox CMD to trigger LPU event
1924 */
1925 writel(1, ioc->ioc_regs.hfn_mbox_cmd);
1926 (void) readl(ioc->ioc_regs.hfn_mbox_cmd);
1927}
1928
1929static void
1930bfa_ioc_send_enable(struct bfa_ioc *ioc)
1931{
1932 struct bfi_ioc_ctrl_req enable_req;
1933 struct timeval tv;
1934
1935 bfi_h2i_set(enable_req.mh, BFI_MC_IOC, BFI_IOC_H2I_ENABLE_REQ,
1936 bfa_ioc_portid(ioc));
078086f3 1937 enable_req.clscode = htons(ioc->clscode);
8b230ed8
RM		 1938 do_gettimeofday(&tv);
1939 enable_req.tv_sec = ntohl(tv.tv_sec);
1940 bfa_ioc_mbox_send(ioc, &enable_req, sizeof(struct bfi_ioc_ctrl_req));
1941}
1942
1943static void
1944bfa_ioc_send_disable(struct bfa_ioc *ioc)
1945{
1946 struct bfi_ioc_ctrl_req disable_req;
1947
1948 bfi_h2i_set(disable_req.mh, BFI_MC_IOC, BFI_IOC_H2I_DISABLE_REQ,
1949 bfa_ioc_portid(ioc));
1950 bfa_ioc_mbox_send(ioc, &disable_req, sizeof(struct bfi_ioc_ctrl_req));
1951}
1952
1953static void
1954bfa_ioc_send_getattr(struct bfa_ioc *ioc)
1955{
1956 struct bfi_ioc_getattr_req attr_req;
1957
1958 bfi_h2i_set(attr_req.mh, BFI_MC_IOC, BFI_IOC_H2I_GETATTR_REQ,
1959 bfa_ioc_portid(ioc));
1960 bfa_dma_be_addr_set(attr_req.attr_addr, ioc->attr_dma.pa);
1961 bfa_ioc_mbox_send(ioc, &attr_req, sizeof(attr_req));
1962}
1963
1964void
ad24d6f0 1965bfa_nw_ioc_hb_check(struct bfa_ioc *ioc)
8b230ed8 1966{
ad24d6f0 1967 u32 hb_count;
8b230ed8
RM		 1968
1969 hb_count = readl(ioc->ioc_regs.heartbeat);
1970 if (ioc->hb_count == hb_count) {
8b230ed8
RM		 1971 bfa_ioc_recover(ioc);
1972 return;
1973 } else {
1974 ioc->hb_count = hb_count;
1975 }
1976
1977 bfa_ioc_mbox_poll(ioc);
1978 mod_timer(&ioc->hb_timer, jiffies +
1979 msecs_to_jiffies(BFA_IOC_HB_TOV));
1980}
1981
1982static void
1983bfa_ioc_hb_monitor(struct bfa_ioc *ioc)
1984{
1985 ioc->hb_count = readl(ioc->ioc_regs.heartbeat);
1986 mod_timer(&ioc->hb_timer, jiffies +
1987 msecs_to_jiffies(BFA_IOC_HB_TOV));
1988}
1989
1990static void
1991bfa_ioc_hb_stop(struct bfa_ioc *ioc)
1992{
1993 del_timer(&ioc->hb_timer);
1994}
1995
1aa8b471 1996/* Initiate a full firmware download. */
c107ba17 1997static enum bfa_status
8b230ed8 1998bfa_ioc_download_fw(struct bfa_ioc *ioc, u32 boot_type,
79ea6c89 1999 u32 boot_env)
8b230ed8
RM		 2000{
2001 u32 *fwimg;
58598542 2002 u32 pgnum;
8b230ed8
RM		 2003 u32 loff = 0;
2004 u32 chunkno = 0;
2005 u32 i;
078086f3 2006 u32 asicmode;
c107ba17
RM		 2007 u32 fwimg_size;
2008 u32 fwimg_buf[BFI_FLASH_CHUNK_SZ_WORDS];
2009 enum bfa_status status;
2010
2011 if (boot_env == BFI_FWBOOT_ENV_OS &&
2012 boot_type == BFI_FWBOOT_TYPE_FLASH) {
2013 fwimg_size = BFI_FLASH_IMAGE_SZ/sizeof(u32);
8b230ed8 2014
c107ba17
RM		 2015 status = bfa_nw_ioc_flash_img_get_chnk(ioc,
2016 BFA_IOC_FLASH_CHUNK_ADDR(chunkno), fwimg_buf);
2017 if (status != BFA_STATUS_OK)
2018 return status;
2019
2020 fwimg = fwimg_buf;
2021 } else {
2022 fwimg_size = bfa_cb_image_get_size(bfa_ioc_asic_gen(ioc));
2023 fwimg = bfa_cb_image_get_chunk(bfa_ioc_asic_gen(ioc),
2024 BFA_IOC_FLASH_CHUNK_ADDR(chunkno));
2025 }
8b230ed8
RM		 2026
2027 pgnum = bfa_ioc_smem_pgnum(ioc, loff);
8b230ed8
RM		 2028
2029 writel(pgnum, ioc->ioc_regs.host_page_num_fn);
2030
c107ba17 2031 for (i = 0; i < fwimg_size; i++) {
8b230ed8
RM		 2032 if (BFA_IOC_FLASH_CHUNK_NO(i) != chunkno) {
2033 chunkno = BFA_IOC_FLASH_CHUNK_NO(i);
c107ba17
RM		 2034 if (boot_env == BFI_FWBOOT_ENV_OS &&
2035 boot_type == BFI_FWBOOT_TYPE_FLASH) {
2036 status = bfa_nw_ioc_flash_img_get_chnk(ioc,
2037 BFA_IOC_FLASH_CHUNK_ADDR(chunkno),
2038 fwimg_buf);
2039 if (status != BFA_STATUS_OK)
2040 return status;
2041
2042 fwimg = fwimg_buf;
2043 } else {
2044 fwimg = bfa_cb_image_get_chunk(
2045 bfa_ioc_asic_gen(ioc),
8b230ed8 2046 BFA_IOC_FLASH_CHUNK_ADDR(chunkno));
c107ba17 2047 }
8b230ed8
RM		 2048 }
2049
2050 /**
2051 * write smem
2052 */
ebb56d37
IV		 2053 writel(swab32(fwimg[BFA_IOC_FLASH_OFFSET_IN_CHUNK(i)]),
2054 ioc->ioc_regs.smem_page_start + loff);
8b230ed8
RM		 2055
2056 loff += sizeof(u32);
2057
2058 /**
2059 * handle page offset wrap around
2060 */
2061 loff = PSS_SMEM_PGOFF(loff);
2062 if (loff == 0) {
2063 pgnum++;
2064 writel(pgnum,
2065 ioc->ioc_regs.host_page_num_fn);
2066 }
2067 }
2068
2069 writel(bfa_ioc_smem_pgnum(ioc, 0),
2070 ioc->ioc_regs.host_page_num_fn);
2071
2072 /*
078086f3 2073 * Set boot type, env and device mode at the end.
8b230ed8 2074 */
c107ba17
RM		 2075 if (boot_env == BFI_FWBOOT_ENV_OS &&
2076 boot_type == BFI_FWBOOT_TYPE_FLASH) {
2077 boot_type = BFI_FWBOOT_TYPE_NORMAL;
2078 }
078086f3
RM		 2079 asicmode = BFI_FWBOOT_DEVMODE(ioc->asic_gen, ioc->asic_mode,
2080 ioc->port0_mode, ioc->port1_mode);
2081 writel(asicmode, ((ioc->ioc_regs.smem_page_start)
2082 + BFI_FWBOOT_DEVMODE_OFF));
79ea6c89 2083 writel(boot_type, ((ioc->ioc_regs.smem_page_start)
078086f3 2084 + (BFI_FWBOOT_TYPE_OFF)));
79ea6c89 2085 writel(boot_env, ((ioc->ioc_regs.smem_page_start)
078086f3 2086 + (BFI_FWBOOT_ENV_OFF)));
c107ba17 2087 return BFA_STATUS_OK;
8b230ed8
RM		 2088}
2089
2090static void
2091bfa_ioc_reset(struct bfa_ioc *ioc, bool force)
2092{
2093 bfa_ioc_hwinit(ioc, force);
2094}
2095
1aa8b471 2096/* BFA ioc enable reply by firmware */
078086f3
RM		 2097static void
2098bfa_ioc_enable_reply(struct bfa_ioc *ioc, enum bfa_mode port_mode,
2099 u8 cap_bm)
2100{
2101 struct bfa_iocpf *iocpf = &ioc->iocpf;
2102
2103 ioc->port_mode = ioc->port_mode_cfg = port_mode;
2104 ioc->ad_cap_bm = cap_bm;
2105 bfa_fsm_send_event(iocpf, IOCPF_E_FWRSP_ENABLE);
2106}
2107
1aa8b471 2108/* Update BFA configuration from firmware configuration. */
8b230ed8
RM		 2109static void
2110bfa_ioc_getattr_reply(struct bfa_ioc *ioc)
2111{
2112 struct bfi_ioc_attr *attr = ioc->attr;
2113
2114 attr->adapter_prop = ntohl(attr->adapter_prop);
2115 attr->card_type = ntohl(attr->card_type);
2116 attr->maxfrsize = ntohs(attr->maxfrsize);
2117
2118 bfa_fsm_send_event(ioc, IOC_E_FWRSP_GETATTR);
2119}
2120
1aa8b471 2121/* Attach time initialization of mbox logic. */
8b230ed8
RM		 2122static void
2123bfa_ioc_mbox_attach(struct bfa_ioc *ioc)
2124{
2125 struct bfa_ioc_mbox_mod *mod = &ioc->mbox_mod;
2126 int mc;
2127
2128 INIT_LIST_HEAD(&mod->cmd_q);
2129 for (mc = 0; mc < BFI_MC_MAX; mc++) {
2130 mod->mbhdlr[mc].cbfn = NULL;
2131 mod->mbhdlr[mc].cbarg = ioc->bfa;
2132 }
2133}
2134
1aa8b471 2135/* Mbox poll timer -- restarts any pending mailbox requests. */
8b230ed8
RM		 2136static void
2137bfa_ioc_mbox_poll(struct bfa_ioc *ioc)
2138{
2139 struct bfa_ioc_mbox_mod *mod = &ioc->mbox_mod;
2140 struct bfa_mbox_cmd *cmd;
078086f3
RM		 2141 bfa_mbox_cmd_cbfn_t cbfn;
2142 void *cbarg;
2143 u32 stat;
8b230ed8
RM		 2144
2145 /**
2146 * If no command pending, do nothing
2147 */
2148 if (list_empty(&mod->cmd_q))
2149 return;
2150
2151 /**
2152 * If previous command is not yet fetched by firmware, do nothing
2153 */
2154 stat = readl(ioc->ioc_regs.hfn_mbox_cmd);
2155 if (stat)
2156 return;
2157
2158 /**
2159 * Enqueue command to firmware.
2160 */
2b26fb95
IV		 2161 cmd = list_first_entry(&mod->cmd_q, struct bfa_mbox_cmd, qe);
2162 list_del(&cmd->qe);
8b230ed8 2163 bfa_ioc_mbox_send(ioc, cmd->msg, sizeof(cmd->msg));
078086f3
RM		 2164
2165 /**
2166 * Give a callback to the client, indicating that the command is sent
2167 */
2168 if (cmd->cbfn) {
2169 cbfn = cmd->cbfn;
2170 cbarg = cmd->cbarg;
2171 cmd->cbfn = NULL;
2172 cbfn(cbarg);
2173 }
8b230ed8
RM		 2174}
2175
1aa8b471 2176/* Cleanup any pending requests. */
8b230ed8 2177static void
fdad400f 2178bfa_ioc_mbox_flush(struct bfa_ioc *ioc)
8b230ed8
RM		 2179{
2180 struct bfa_ioc_mbox_mod *mod = &ioc->mbox_mod;
2181 struct bfa_mbox_cmd *cmd;
2182
2b26fb95
IV		 2183 while (!list_empty(&mod->cmd_q)) {
2184 cmd = list_first_entry(&mod->cmd_q, struct bfa_mbox_cmd, qe);
2185 list_del(&cmd->qe);
2186 }
8b230ed8
RM		 2187}
2188
7afc5dbd 2189/**
1aa8b471 2190 * bfa_nw_ioc_smem_read - Read data from SMEM to host through PCI memmap
7afc5dbd 2191 *
1aa8b471
BH		 2192 * @ioc: memory for IOC
2193 * @tbuf: app memory to store data from smem
2194 * @soff: smem offset
2195 * @sz: size of smem in bytes
7afc5dbd
KG		 2196 */
2197static int
2198bfa_nw_ioc_smem_read(struct bfa_ioc *ioc, void *tbuf, u32 soff, u32 sz)
2199{
2200 u32 pgnum, loff, r32;
2201 int i, len;
2202 u32 *buf = tbuf;
2203
2204 pgnum = PSS_SMEM_PGNUM(ioc->ioc_regs.smem_pg0, soff);
2205 loff = PSS_SMEM_PGOFF(soff);
2206
2207 /*
2208 * Hold semaphore to serialize pll init and fwtrc.
2209 */
93719d26 2210 if (!bfa_nw_ioc_sem_get(ioc->ioc_regs.ioc_init_sem_reg))
7afc5dbd
KG		 2211 return 1;
2212
2213 writel(pgnum, ioc->ioc_regs.host_page_num_fn);
2214
2215 len = sz/sizeof(u32);
2216 for (i = 0; i < len; i++) {
ebb56d37 2217 r32 = swab32(readl(loff + ioc->ioc_regs.smem_page_start));
7afc5dbd
KG		 2218 buf[i] = be32_to_cpu(r32);
2219 loff += sizeof(u32);
2220
2221 /**
2222 * handle page offset wrap around
2223 */
2224 loff = PSS_SMEM_PGOFF(loff);
2225 if (loff == 0) {
2226 pgnum++;
2227 writel(pgnum, ioc->ioc_regs.host_page_num_fn);
2228 }
2229 }
2230
2231 writel(PSS_SMEM_PGNUM(ioc->ioc_regs.smem_pg0, 0),
2232 ioc->ioc_regs.host_page_num_fn);
2233
2234 /*
2235 * release semaphore
2236 */
2237 readl(ioc->ioc_regs.ioc_init_sem_reg);
2238 writel(1, ioc->ioc_regs.ioc_init_sem_reg);
2239 return 0;
2240}
2241
1aa8b471 2242/* Retrieve saved firmware trace from a prior IOC failure. */
7afc5dbd
KG		 2243int
2244bfa_nw_ioc_debug_fwtrc(struct bfa_ioc *ioc, void *trcdata, int *trclen)
2245{
2246 u32 loff = BFI_IOC_TRC_OFF + BNA_DBG_FWTRC_LEN * ioc->port_id;
2247 int tlen, status = 0;
2248
2249 tlen = *trclen;
2250 if (tlen > BNA_DBG_FWTRC_LEN)
2251 tlen = BNA_DBG_FWTRC_LEN;
2252
2253 status = bfa_nw_ioc_smem_read(ioc, trcdata, loff, tlen);
2254 *trclen = tlen;
2255 return status;
2256}
2257
1aa8b471 2258/* Save firmware trace if configured. */
7afc5dbd
KG		 2259static void
2260bfa_nw_ioc_debug_save_ftrc(struct bfa_ioc *ioc)
2261{
2262 int tlen;
2263
2264 if (ioc->dbg_fwsave_once) {
93719d26 2265 ioc->dbg_fwsave_once = false;
7afc5dbd
KG		 2266 if (ioc->dbg_fwsave_len) {
2267 tlen = ioc->dbg_fwsave_len;
2268 bfa_nw_ioc_debug_fwtrc(ioc, ioc->dbg_fwsave, &tlen);
2269 }
2270 }
2271}
2272
1aa8b471 2273/* Retrieve saved firmware trace from a prior IOC failure. */
7afc5dbd
KG		 2274int
2275bfa_nw_ioc_debug_fwsave(struct bfa_ioc *ioc, void *trcdata, int *trclen)
2276{
2277 int tlen;
2278
2279 if (ioc->dbg_fwsave_len == 0)
2280 return BFA_STATUS_ENOFSAVE;
2281
2282 tlen = *trclen;
2283 if (tlen > ioc->dbg_fwsave_len)
2284 tlen = ioc->dbg_fwsave_len;
2285
2286 memcpy(trcdata, ioc->dbg_fwsave, tlen);
2287 *trclen = tlen;
2288 return BFA_STATUS_OK;
2289}
2290
1d32f769
RM		 2291static void
2292bfa_ioc_fail_notify(struct bfa_ioc *ioc)
2293{
1d32f769
RM		 2294 /**
2295 * Notify driver and common modules registered for notification.
2296 */
2297 ioc->cbfn->hbfail_cbfn(ioc->bfa);
bd5a92e9 2298 bfa_ioc_event_notify(ioc, BFA_IOC_E_FAILED);
7afc5dbd 2299 bfa_nw_ioc_debug_save_ftrc(ioc);
1d32f769
RM		 2300}
2301
1aa8b471 2302/* IOCPF to IOC interface */
1d32f769
RM		 2303static void
2304bfa_ioc_pf_enabled(struct bfa_ioc *ioc)
2305{
2306 bfa_fsm_send_event(ioc, IOC_E_ENABLED);
2307}
2308
2309static void
2310bfa_ioc_pf_disabled(struct bfa_ioc *ioc)
2311{
2312 bfa_fsm_send_event(ioc, IOC_E_DISABLED);
2313}
2314
2315static void
078086f3 2316bfa_ioc_pf_failed(struct bfa_ioc *ioc)
1d32f769 2317{
078086f3 2318 bfa_fsm_send_event(ioc, IOC_E_PFFAILED);
1d32f769
RM		 2319}
2320
2321static void
078086f3 2322bfa_ioc_pf_hwfailed(struct bfa_ioc *ioc)
1d32f769 2323{
078086f3 2324 bfa_fsm_send_event(ioc, IOC_E_HWFAILED);
1d32f769
RM		 2325}
2326
2327static void
2328bfa_ioc_pf_fwmismatch(struct bfa_ioc *ioc)
2329{
2330 /**
2331 * Provide enable completion callback and AEN notification.
2332 */
2333 ioc->cbfn->enable_cbfn(ioc->bfa, BFA_STATUS_IOC_FAILURE);
2334}
2335
1aa8b471 2336/* IOC public */
8a891429 2337static enum bfa_status
8b230ed8
RM		 2338bfa_ioc_pll_init(struct bfa_ioc *ioc)
2339{
2340 /*
2341 * Hold semaphore so that nobody can access the chip during init.
2342 */
8a891429 2343 bfa_nw_ioc_sem_get(ioc->ioc_regs.ioc_init_sem_reg);
8b230ed8
RM		 2344
2345 bfa_ioc_pll_init_asic(ioc);
2346
2347 ioc->pllinit = true;
e491c77e
JH		 2348
2349 /* Initialize LMEM */
2350 bfa_ioc_lmem_init(ioc);
2351
8b230ed8
RM		 2352 /*
2353 * release semaphore.
2354 */
8a891429 2355 bfa_nw_ioc_sem_release(ioc->ioc_regs.ioc_init_sem_reg);
8b230ed8
RM		 2356
2357 return BFA_STATUS_OK;
2358}
2359
1aa8b471 2360/* Interface used by diag module to do firmware boot with memory test
8b230ed8
RM		 2361 * as the entry vector.
2362 */
c107ba17 2363static enum bfa_status
078086f3
RM		 2364bfa_ioc_boot(struct bfa_ioc *ioc, enum bfi_fwboot_type boot_type,
2365 u32 boot_env)
8b230ed8 2366{
c107ba17
RM		 2367 struct bfi_ioc_image_hdr *drv_fwhdr;
2368 enum bfa_status status;
8b230ed8
RM		 2369 bfa_ioc_stats(ioc, ioc_boots);
2370
2371 if (bfa_ioc_pll_init(ioc) != BFA_STATUS_OK)
c107ba17
RM		 2372 return BFA_STATUS_FAILED;
2373 if (boot_env == BFI_FWBOOT_ENV_OS &&
2374 boot_type == BFI_FWBOOT_TYPE_NORMAL) {
2375 drv_fwhdr = (struct bfi_ioc_image_hdr *)
2376 bfa_cb_image_get_chunk(bfa_ioc_asic_gen(ioc), 0);
2377 /* Work with Flash iff flash f/w is better than driver f/w.
2378 * Otherwise push drivers firmware.
2379 */
2380 if (bfa_ioc_flash_fwver_cmp(ioc, drv_fwhdr) ==
2381 BFI_IOC_IMG_VER_BETTER)
2382 boot_type = BFI_FWBOOT_TYPE_FLASH;
2383 }
8b230ed8
RM		 2384
2385 /**
2386 * Initialize IOC state of all functions on a chip reset.
2387 */
078086f3 2388 if (boot_type == BFI_FWBOOT_TYPE_MEMTEST) {
41ed903a
RM		 2389 bfa_ioc_set_cur_ioc_fwstate(ioc, BFI_IOC_MEMTEST);
2390 bfa_ioc_set_alt_ioc_fwstate(ioc, BFI_IOC_MEMTEST);
8b230ed8 2391 } else {
41ed903a
RM		 2392 bfa_ioc_set_cur_ioc_fwstate(ioc, BFI_IOC_INITING);
2393 bfa_ioc_set_alt_ioc_fwstate(ioc, BFI_IOC_INITING);
8b230ed8
RM		 2394 }
2395
2396 bfa_ioc_msgflush(ioc);
c107ba17
RM		 2397 status = bfa_ioc_download_fw(ioc, boot_type, boot_env);
2398 if (status == BFA_STATUS_OK)
2399 bfa_ioc_lpu_start(ioc);
2400 else
4818e856 2401 bfa_fsm_send_event(&ioc->iocpf, IOCPF_E_TIMEOUT);
c107ba17
RM		 2402
2403 return status;
8b230ed8
RM		 2404}
2405
1aa8b471 2406/* Enable/disable IOC failure auto recovery. */
8b230ed8 2407void
8a891429 2408bfa_nw_ioc_auto_recover(bool auto_recover)
8b230ed8 2409{
8a891429 2410 bfa_nw_auto_recover = auto_recover;
8b230ed8
RM		 2411}
2412
078086f3 2413static bool
8b230ed8
RM		 2414bfa_ioc_msgget(struct bfa_ioc *ioc, void *mbmsg)
2415{
2416 u32 *msgp = mbmsg;
2417 u32 r32;
2418 int i;
2419
078086f3
RM		 2420 r32 = readl(ioc->ioc_regs.lpu_mbox_cmd);
2421 if ((r32 & 1) == 0)
2422 return false;
2423
8b230ed8
RM		 2424 /**
2425 * read the MBOX msg
2426 */
2427 for (i = 0; i < (sizeof(union bfi_ioc_i2h_msg_u) / sizeof(u32));
2428 i++) {
2429 r32 = readl(ioc->ioc_regs.lpu_mbox +
2430 i * sizeof(u32));
2431 msgp[i] = htonl(r32);
2432 }
2433
2434 /**
2435 * turn off mailbox interrupt by clearing mailbox status
2436 */
2437 writel(1, ioc->ioc_regs.lpu_mbox_cmd);
2438 readl(ioc->ioc_regs.lpu_mbox_cmd);
078086f3
RM		 2439
2440 return true;
8b230ed8
RM		 2441}
2442
8a891429 2443static void
8b230ed8
RM		 2444bfa_ioc_isr(struct bfa_ioc *ioc, struct bfi_mbmsg *m)
2445{
2446 union bfi_ioc_i2h_msg_u *msg;
1d32f769 2447 struct bfa_iocpf *iocpf = &ioc->iocpf;
8b230ed8
RM		 2448
2449 msg = (union bfi_ioc_i2h_msg_u *) m;
2450
2451 bfa_ioc_stats(ioc, ioc_isrs);
2452
2453 switch (msg->mh.msg_id) {
2454 case BFI_IOC_I2H_HBEAT:
2455 break;
2456
8b230ed8 2457 case BFI_IOC_I2H_ENABLE_REPLY:
078086f3
RM		 2458 bfa_ioc_enable_reply(ioc,
2459 (enum bfa_mode)msg->fw_event.port_mode,
2460 msg->fw_event.cap_bm);
8b230ed8
RM		 2461 break;
2462
2463 case BFI_IOC_I2H_DISABLE_REPLY:
1d32f769 2464 bfa_fsm_send_event(iocpf, IOCPF_E_FWRSP_DISABLE);
8b230ed8
RM		 2465 break;
2466
2467 case BFI_IOC_I2H_GETATTR_REPLY:
2468 bfa_ioc_getattr_reply(ioc);
2469 break;
2470
2471 default:
2472 BUG_ON(1);
2473 }
2474}
2475
2476/**
1aa8b471 2477 * bfa_nw_ioc_attach - IOC attach time initialization and setup.
8b230ed8 2478 *
1aa8b471
BH		 2479 * @ioc: memory for IOC
2480 * @bfa: driver instance structure
8b230ed8
RM		 2481 */
2482void
8a891429 2483bfa_nw_ioc_attach(struct bfa_ioc *ioc, void *bfa, struct bfa_ioc_cbfn *cbfn)
8b230ed8
RM		 2484{
2485 ioc->bfa = bfa;
2486 ioc->cbfn = cbfn;
2487 ioc->fcmode = false;
2488 ioc->pllinit = false;
2489 ioc->dbg_fwsave_once = true;
1d32f769 2490 ioc->iocpf.ioc = ioc;
8b230ed8
RM		 2491
2492 bfa_ioc_mbox_attach(ioc);
bd5a92e9 2493 INIT_LIST_HEAD(&ioc->notify_q);
8b230ed8 2494
1d32f769
RM		 2495 bfa_fsm_set_state(ioc, bfa_ioc_sm_uninit);
2496 bfa_fsm_send_event(ioc, IOC_E_RESET);
8b230ed8
RM		 2497}
2498
1aa8b471 2499/* Driver detach time IOC cleanup. */
8b230ed8 2500void
8a891429 2501bfa_nw_ioc_detach(struct bfa_ioc *ioc)
8b230ed8
RM		 2502{
2503 bfa_fsm_send_event(ioc, IOC_E_DETACH);
078086f3
RM		 2504
2505 /* Done with detach, empty the notify_q. */
2506 INIT_LIST_HEAD(&ioc->notify_q);
8b230ed8
RM		 2507}
2508
2509/**
1aa8b471 2510 * bfa_nw_ioc_pci_init - Setup IOC PCI properties.
8b230ed8 2511 *
1aa8b471 2512 * @pcidev: PCI device information for this IOC
8b230ed8
RM		 2513 */
2514void
8a891429 2515bfa_nw_ioc_pci_init(struct bfa_ioc *ioc, struct bfa_pcidev *pcidev,
078086f3 2516 enum bfi_pcifn_class clscode)
8b230ed8 2517{
078086f3 2518 ioc->clscode = clscode;
8b230ed8 2519 ioc->pcidev = *pcidev;
078086f3
RM		 2520
2521 /**
2522 * Initialize IOC and device personality
2523 */
2524 ioc->port0_mode = ioc->port1_mode = BFI_PORT_MODE_FC;
2525 ioc->asic_mode = BFI_ASIC_MODE_FC;
2526
2527 switch (pcidev->device_id) {
2528 case PCI_DEVICE_ID_BROCADE_CT:
2529 ioc->asic_gen = BFI_ASIC_GEN_CT;
2530 ioc->port0_mode = ioc->port1_mode = BFI_PORT_MODE_ETH;
2531 ioc->asic_mode = BFI_ASIC_MODE_ETH;
2532 ioc->port_mode = ioc->port_mode_cfg = BFA_MODE_CNA;
2533 ioc->ad_cap_bm = BFA_CM_CNA;
2534 break;
2535
586b2816
RM		 2536 case BFA_PCI_DEVICE_ID_CT2:
2537 ioc->asic_gen = BFI_ASIC_GEN_CT2;
2538 if (clscode == BFI_PCIFN_CLASS_FC &&
2539 pcidev->ssid == BFA_PCI_CT2_SSID_FC) {
2540 ioc->asic_mode = BFI_ASIC_MODE_FC16;
2541 ioc->fcmode = true;
2542 ioc->port_mode = ioc->port_mode_cfg = BFA_MODE_HBA;
2543 ioc->ad_cap_bm = BFA_CM_HBA;
2544 } else {
2545 ioc->port0_mode = ioc->port1_mode = BFI_PORT_MODE_ETH;
2546 ioc->asic_mode = BFI_ASIC_MODE_ETH;
2547 if (pcidev->ssid == BFA_PCI_CT2_SSID_FCoE) {
2548 ioc->port_mode =
2549 ioc->port_mode_cfg = BFA_MODE_CNA;
2550 ioc->ad_cap_bm = BFA_CM_CNA;
2551 } else {
2552 ioc->port_mode =
2553 ioc->port_mode_cfg = BFA_MODE_NIC;
2554 ioc->ad_cap_bm = BFA_CM_NIC;
2555 }
2556 }
2557 break;
2558
078086f3
RM		 2559 default:
2560 BUG_ON(1);
2561 }
8b230ed8 2562
be3a84d1
RM		 2563 /**
2564 * Set asic specific interfaces.
2565 */
2566 if (ioc->asic_gen == BFI_ASIC_GEN_CT)
2567 bfa_nw_ioc_set_ct_hwif(ioc);
70f14381
RM		 2568 else {
2569 WARN_ON(ioc->asic_gen != BFI_ASIC_GEN_CT2);
be3a84d1 2570 bfa_nw_ioc_set_ct2_hwif(ioc);
70f14381
RM		 2571 bfa_nw_ioc_ct2_poweron(ioc);
2572 }
8b230ed8
RM		 2573
2574 bfa_ioc_map_port(ioc);
2575 bfa_ioc_reg_init(ioc);
2576}
2577
2578/**
1aa8b471 2579 * bfa_nw_ioc_mem_claim - Initialize IOC dma memory
8b230ed8 2580 *
1aa8b471
BH		 2581 * @dm_kva: kernel virtual address of IOC dma memory
2582 * @dm_pa: physical address of IOC dma memory
8b230ed8
RM		 2583 */
2584void
8a891429 2585bfa_nw_ioc_mem_claim(struct bfa_ioc *ioc, u8 *dm_kva, u64 dm_pa)
8b230ed8
RM		 2586{
2587 /**
2588 * dma memory for firmware attribute
2589 */
2590 ioc->attr_dma.kva = dm_kva;
2591 ioc->attr_dma.pa = dm_pa;
2592 ioc->attr = (struct bfi_ioc_attr *) dm_kva;
2593}
2594
1aa8b471 2595/* Return size of dma memory required. */
8b230ed8 2596u32
8a891429 2597bfa_nw_ioc_meminfo(void)
8b230ed8
RM		 2598{
2599 return roundup(sizeof(struct bfi_ioc_attr), BFA_DMA_ALIGN_SZ);
2600}
2601
2602void
8a891429 2603bfa_nw_ioc_enable(struct bfa_ioc *ioc)
8b230ed8
RM		 2604{
2605 bfa_ioc_stats(ioc, ioc_enables);
2606 ioc->dbg_fwsave_once = true;
2607
2608 bfa_fsm_send_event(ioc, IOC_E_ENABLE);
2609}
2610
2611void
8a891429 2612bfa_nw_ioc_disable(struct bfa_ioc *ioc)
8b230ed8
RM		 2613{
2614 bfa_ioc_stats(ioc, ioc_disables);
2615 bfa_fsm_send_event(ioc, IOC_E_DISABLE);
2616}
2617
1aa8b471 2618/* Initialize memory for saving firmware trace. */
7afc5dbd
KG		 2619void
2620bfa_nw_ioc_debug_memclaim(struct bfa_ioc *ioc, void *dbg_fwsave)
2621{
2622 ioc->dbg_fwsave = dbg_fwsave;
2623 ioc->dbg_fwsave_len = ioc->iocpf.auto_recover ? BNA_DBG_FWTRC_LEN : 0;
2624}
2625
8a891429 2626static u32
8b230ed8
RM		 2627bfa_ioc_smem_pgnum(struct bfa_ioc *ioc, u32 fmaddr)
2628{
2629 return PSS_SMEM_PGNUM(ioc->ioc_regs.smem_pg0, fmaddr);
2630}
2631
1aa8b471 2632/* Register mailbox message handler function, to be called by common modules */
8b230ed8 2633void
8a891429 2634bfa_nw_ioc_mbox_regisr(struct bfa_ioc *ioc, enum bfi_mclass mc,
8b230ed8
RM		 2635 bfa_ioc_mbox_mcfunc_t cbfn, void *cbarg)
2636{
2637 struct bfa_ioc_mbox_mod *mod = &ioc->mbox_mod;
2638
2639 mod->mbhdlr[mc].cbfn = cbfn;
2640 mod->mbhdlr[mc].cbarg = cbarg;
2641}
2642
2643/**
1aa8b471 2644 * bfa_nw_ioc_mbox_queue - Queue a mailbox command request to firmware.
8b230ed8 2645 *
1aa8b471
BH		 2646 * @ioc: IOC instance
2647 * @cmd: Mailbox command
2648 *
2649 * Waits if mailbox is busy. Responsibility of caller to serialize
8b230ed8 2650 */
af027a34
RM		 2651bool
2652bfa_nw_ioc_mbox_queue(struct bfa_ioc *ioc, struct bfa_mbox_cmd *cmd,
2653 bfa_mbox_cmd_cbfn_t cbfn, void *cbarg)
8b230ed8
RM		 2654{
2655 struct bfa_ioc_mbox_mod *mod = &ioc->mbox_mod;
2656 u32 stat;
2657
af027a34
RM		 2658 cmd->cbfn = cbfn;
2659 cmd->cbarg = cbarg;
2660
8b230ed8
RM		 2661 /**
2662 * If a previous command is pending, queue new command
2663 */
2664 if (!list_empty(&mod->cmd_q)) {
2665 list_add_tail(&cmd->qe, &mod->cmd_q);
af027a34 2666 return true;
8b230ed8
RM		 2667 }
2668
2669 /**
2670 * If mailbox is busy, queue command for poll timer
2671 */
2672 stat = readl(ioc->ioc_regs.hfn_mbox_cmd);
2673 if (stat) {
2674 list_add_tail(&cmd->qe, &mod->cmd_q);
af027a34 2675 return true;
8b230ed8
RM		 2676 }
2677
2678 /**
2679 * mailbox is free -- queue command to firmware
2680 */
2681 bfa_ioc_mbox_send(ioc, cmd->msg, sizeof(cmd->msg));
bd5a92e9 2682
af027a34 2683 return false;
8b230ed8
RM		 2684}
2685
1aa8b471 2686/* Handle mailbox interrupts */
8b230ed8 2687void
8a891429 2688bfa_nw_ioc_mbox_isr(struct bfa_ioc *ioc)
8b230ed8
RM		 2689{
2690 struct bfa_ioc_mbox_mod *mod = &ioc->mbox_mod;
2691 struct bfi_mbmsg m;
2692 int mc;
2693
078086f3
RM		 2694 if (bfa_ioc_msgget(ioc, &m)) {
2695 /**
2696 * Treat IOC message class as special.
2697 */
2698 mc = m.mh.msg_class;
2699 if (mc == BFI_MC_IOC) {
2700 bfa_ioc_isr(ioc, &m);
2701 return;
2702 }
8b230ed8 2703
078086f3
RM		 2704 if ((mc >= BFI_MC_MAX) || (mod->mbhdlr[mc].cbfn == NULL))
2705 return;
2706
2707 mod->mbhdlr[mc].cbfn(mod->mbhdlr[mc].cbarg, &m);
8b230ed8
RM		 2708 }
2709
078086f3 2710 bfa_ioc_lpu_read_stat(ioc);
8b230ed8 2711
078086f3
RM		 2712 /**
2713 * Try to send pending mailbox commands
2714 */
2715 bfa_ioc_mbox_poll(ioc);
8b230ed8
RM		 2716}
2717
2718void
8a891429 2719bfa_nw_ioc_error_isr(struct bfa_ioc *ioc)
8b230ed8 2720{
9b08a4fc
RM		 2721 bfa_ioc_stats(ioc, ioc_hbfails);
2722 bfa_ioc_stats_hb_count(ioc, ioc->hb_count);
8b230ed8
RM		 2723 bfa_fsm_send_event(ioc, IOC_E_HWERROR);
2724}
2725
1aa8b471 2726/* return true if IOC is disabled */
bd5a92e9
RM		 2727bool
2728bfa_nw_ioc_is_disabled(struct bfa_ioc *ioc)
2729{
2730 return bfa_fsm_cmp_state(ioc, bfa_ioc_sm_disabling) ||
2731 bfa_fsm_cmp_state(ioc, bfa_ioc_sm_disabled);
2732}
2733
1aa8b471 2734/* return true if IOC is operational */
72a9730b
KG		 2735bool
2736bfa_nw_ioc_is_operational(struct bfa_ioc *ioc)
2737{
2738 return bfa_fsm_cmp_state(ioc, bfa_ioc_sm_op);
2739}
2740
1aa8b471 2741/* Add to IOC heartbeat failure notification queue. To be used by common
8b230ed8
RM		 2742 * modules such as cee, port, diag.
2743 */
2744void
bd5a92e9
RM		 2745bfa_nw_ioc_notify_register(struct bfa_ioc *ioc,
2746 struct bfa_ioc_notify *notify)
8b230ed8 2747{
bd5a92e9 2748 list_add_tail(&notify->qe, &ioc->notify_q);
8b230ed8
RM		 2749}
2750
2732ba56 2751#define BFA_MFG_NAME "QLogic"
8a891429 2752static void
8b230ed8
RM		 2753bfa_ioc_get_adapter_attr(struct bfa_ioc *ioc,
2754 struct bfa_adapter_attr *ad_attr)
2755{
2756 struct bfi_ioc_attr *ioc_attr;
2757
2758 ioc_attr = ioc->attr;
2759
2760 bfa_ioc_get_adapter_serial_num(ioc, ad_attr->serial_num);
2761 bfa_ioc_get_adapter_fw_ver(ioc, ad_attr->fw_ver);
2762 bfa_ioc_get_adapter_optrom_ver(ioc, ad_attr->optrom_ver);
2763 bfa_ioc_get_adapter_manufacturer(ioc, ad_attr->manufacturer);
2764 memcpy(&ad_attr->vpd, &ioc_attr->vpd,
2765 sizeof(struct bfa_mfg_vpd));
2766
2767 ad_attr->nports = bfa_ioc_get_nports(ioc);
2768 ad_attr->max_speed = bfa_ioc_speed_sup(ioc);
2769
2770 bfa_ioc_get_adapter_model(ioc, ad_attr->model);
2771 /* For now, model descr uses same model string */
2772 bfa_ioc_get_adapter_model(ioc, ad_attr->model_descr);
2773
2774 ad_attr->card_type = ioc_attr->card_type;
2775 ad_attr->is_mezz = bfa_mfg_is_mezz(ioc_attr->card_type);
2776
2777 if (BFI_ADAPTER_IS_SPECIAL(ioc_attr->adapter_prop))
2778 ad_attr->prototype = 1;
2779 else
2780 ad_attr->prototype = 0;
2781
2782 ad_attr->pwwn = bfa_ioc_get_pwwn(ioc);
d6b30598 2783 bfa_nw_ioc_get_mac(ioc, ad_attr->mac);
8b230ed8
RM		 2784
2785 ad_attr->pcie_gen = ioc_attr->pcie_gen;
2786 ad_attr->pcie_lanes = ioc_attr->pcie_lanes;
2787 ad_attr->pcie_lanes_orig = ioc_attr->pcie_lanes_orig;
2788 ad_attr->asic_rev = ioc_attr->asic_rev;
2789
2790 bfa_ioc_get_pci_chip_rev(ioc, ad_attr->hw_ver);
8b230ed8
RM		 2791}
2792
8a891429 2793static enum bfa_ioc_type
8b230ed8
RM		 2794bfa_ioc_get_type(struct bfa_ioc *ioc)
2795{
078086f3 2796 if (ioc->clscode == BFI_PCIFN_CLASS_ETH)
8b230ed8 2797 return BFA_IOC_TYPE_LL;
078086f3
RM		 2798
2799 BUG_ON(!(ioc->clscode == BFI_PCIFN_CLASS_FC));
2800
2801 return (ioc->attr->port_mode == BFI_PORT_MODE_FC)
2802 ? BFA_IOC_TYPE_FC : BFA_IOC_TYPE_FCoE;
8b230ed8
RM		 2803}
2804
8a891429 2805static void
8b230ed8
RM		 2806bfa_ioc_get_adapter_serial_num(struct bfa_ioc *ioc, char *serial_num)
2807{
8b230ed8
RM		 2808 memcpy(serial_num,
2809 (void *)ioc->attr->brcd_serialnum,
2810 BFA_ADAPTER_SERIAL_NUM_LEN);
2811}
2812
8a891429 2813static void
8b230ed8
RM		 2814bfa_ioc_get_adapter_fw_ver(struct bfa_ioc *ioc, char *fw_ver)
2815{
8b230ed8
RM		 2816 memcpy(fw_ver, ioc->attr->fw_version, BFA_VERSION_LEN);
2817}
2818
8a891429 2819static void
8b230ed8
RM		 2820bfa_ioc_get_pci_chip_rev(struct bfa_ioc *ioc, char *chip_rev)
2821{
2822 BUG_ON(!(chip_rev));
2823
2824 memset(chip_rev, 0, BFA_IOC_CHIP_REV_LEN);
2825
2826 chip_rev[0] = 'R';
2827 chip_rev[1] = 'e';
2828 chip_rev[2] = 'v';
2829 chip_rev[3] = '-';
2830 chip_rev[4] = ioc->attr->asic_rev;
2831 chip_rev[5] = '\0';
2832}
2833
8a891429 2834static void
8b230ed8
RM		 2835bfa_ioc_get_adapter_optrom_ver(struct bfa_ioc *ioc, char *optrom_ver)
2836{
8b230ed8
RM		 2837 memcpy(optrom_ver, ioc->attr->optrom_version,
2838 BFA_VERSION_LEN);
2839}
2840
8a891429 2841static void
8b230ed8
RM		 2842bfa_ioc_get_adapter_manufacturer(struct bfa_ioc *ioc, char *manufacturer)
2843{
8b230ed8
RM		 2844 memcpy(manufacturer, BFA_MFG_NAME, BFA_ADAPTER_MFG_NAME_LEN);
2845}
2846
8a891429 2847static void
8b230ed8
RM		 2848bfa_ioc_get_adapter_model(struct bfa_ioc *ioc, char *model)
2849{
2850 struct bfi_ioc_attr *ioc_attr;
2851
2852 BUG_ON(!(model));
2853 memset(model, 0, BFA_ADAPTER_MODEL_NAME_LEN);
2854
2855 ioc_attr = ioc->attr;
2856
8b230ed8
RM		 2857 snprintf(model, BFA_ADAPTER_MODEL_NAME_LEN, "%s-%u",
2858 BFA_MFG_NAME, ioc_attr->card_type);
2859}
2860
8a891429 2861static enum bfa_ioc_state
8b230ed8
RM		 2862bfa_ioc_get_state(struct bfa_ioc *ioc)
2863{
1d32f769
RM		 2864 enum bfa_iocpf_state iocpf_st;
2865 enum bfa_ioc_state ioc_st = bfa_sm_to_state(ioc_sm_table, ioc->fsm);
2866
2867 if (ioc_st == BFA_IOC_ENABLING ||
2868 ioc_st == BFA_IOC_FAIL || ioc_st == BFA_IOC_INITFAIL) {
2869
2870 iocpf_st = bfa_sm_to_state(iocpf_sm_table, ioc->iocpf.fsm);
2871
2872 switch (iocpf_st) {
2873 case BFA_IOCPF_SEMWAIT:
2874 ioc_st = BFA_IOC_SEMWAIT;
2875 break;
2876
2877 case BFA_IOCPF_HWINIT:
2878 ioc_st = BFA_IOC_HWINIT;
2879 break;
2880
2881 case BFA_IOCPF_FWMISMATCH:
2882 ioc_st = BFA_IOC_FWMISMATCH;
2883 break;
2884
2885 case BFA_IOCPF_FAIL:
2886 ioc_st = BFA_IOC_FAIL;
2887 break;
2888
2889 case BFA_IOCPF_INITFAIL:
2890 ioc_st = BFA_IOC_INITFAIL;
2891 break;
2892
2893 default:
2894 break;
2895 }
2896 }
2897 return ioc_st;
8b230ed8
RM		 2898}
2899
2900void
8a891429 2901bfa_nw_ioc_get_attr(struct bfa_ioc *ioc, struct bfa_ioc_attr *ioc_attr)
8b230ed8
RM		 2902{
2903 memset((void *)ioc_attr, 0, sizeof(struct bfa_ioc_attr));
2904
2905 ioc_attr->state = bfa_ioc_get_state(ioc);
43c07ada 2906 ioc_attr->port_id = bfa_ioc_portid(ioc);
078086f3
RM		 2907 ioc_attr->port_mode = ioc->port_mode;
2908
2909 ioc_attr->port_mode_cfg = ioc->port_mode_cfg;
2910 ioc_attr->cap_bm = ioc->ad_cap_bm;
8b230ed8
RM		 2911
2912 ioc_attr->ioc_type = bfa_ioc_get_type(ioc);
2913
2914 bfa_ioc_get_adapter_attr(ioc, &ioc_attr->adapter_attr);
2915
43c07ada
RM		 2916 ioc_attr->pci_attr.device_id = bfa_ioc_devid(ioc);
2917 ioc_attr->pci_attr.pcifn = bfa_ioc_pcifn(ioc);
2918 ioc_attr->def_fn = bfa_ioc_is_default(ioc);
8b230ed8
RM		 2919 bfa_ioc_get_pci_chip_rev(ioc, ioc_attr->pci_attr.chip_rev);
2920}
2921
1aa8b471 2922/* WWN public */
8a891429 2923static u64
8b230ed8
RM		 2924bfa_ioc_get_pwwn(struct bfa_ioc *ioc)
2925{
2926 return ioc->attr->pwwn;
2927}
2928
d6b30598
IV		 2929void
2930bfa_nw_ioc_get_mac(struct bfa_ioc *ioc, u8 *mac)
8b230ed8 2931{
d6b30598 2932 ether_addr_copy(mac, ioc->attr->mac);
8b230ed8
RM		 2933}
2934
1aa8b471 2935/* Firmware failure detected. Start recovery actions. */
8b230ed8
RM		 2936static void
2937bfa_ioc_recover(struct bfa_ioc *ioc)
2938{
1e581486
RM		 2939 pr_crit("Heart Beat of IOC has failed\n");
2940 bfa_ioc_stats(ioc, ioc_hbfails);
9b08a4fc 2941 bfa_ioc_stats_hb_count(ioc, ioc->hb_count);
1e581486 2942 bfa_fsm_send_event(ioc, IOC_E_HBFAIL);
8b230ed8
RM		 2943}
2944
1aa8b471 2945/* BFA IOC PF private functions */
1d32f769
RM		 2946
2947static void
2948bfa_iocpf_enable(struct bfa_ioc *ioc)
2949{
2950 bfa_fsm_send_event(&ioc->iocpf, IOCPF_E_ENABLE);
2951}
2952
2953static void
2954bfa_iocpf_disable(struct bfa_ioc *ioc)
2955{
2956 bfa_fsm_send_event(&ioc->iocpf, IOCPF_E_DISABLE);
2957}
2958
2959static void
2960bfa_iocpf_fail(struct bfa_ioc *ioc)
2961{
2962 bfa_fsm_send_event(&ioc->iocpf, IOCPF_E_FAIL);
2963}
2964
2965static void
2966bfa_iocpf_initfail(struct bfa_ioc *ioc)
2967{
2968 bfa_fsm_send_event(&ioc->iocpf, IOCPF_E_INITFAIL);
2969}
2970
2971static void
2972bfa_iocpf_getattrfail(struct bfa_ioc *ioc)
2973{
2974 bfa_fsm_send_event(&ioc->iocpf, IOCPF_E_GETATTRFAIL);
2975}
2976
2977static void
2978bfa_iocpf_stop(struct bfa_ioc *ioc)
2979{
2980 bfa_fsm_send_event(&ioc->iocpf, IOCPF_E_STOP);
2981}
2982
2983void
ad24d6f0 2984bfa_nw_iocpf_timeout(struct bfa_ioc *ioc)
1d32f769 2985{
078086f3
RM		 2986 enum bfa_iocpf_state iocpf_st;
2987
2988 iocpf_st = bfa_sm_to_state(iocpf_sm_table, ioc->iocpf.fsm);
1d32f769 2989
078086f3
RM		 2990 if (iocpf_st == BFA_IOCPF_HWINIT)
2991 bfa_ioc_poll_fwinit(ioc);
2992 else
2993 bfa_fsm_send_event(&ioc->iocpf, IOCPF_E_TIMEOUT);
1d32f769 2994}
8b230ed8 2995
1d32f769 2996void
ad24d6f0 2997bfa_nw_iocpf_sem_timeout(struct bfa_ioc *ioc)
1d32f769 2998{
1d32f769 2999 bfa_ioc_hw_sem_get(ioc);
8b230ed8 3000}
078086f3
RM		 3001
3002static void
3003bfa_ioc_poll_fwinit(struct bfa_ioc *ioc)
3004{
41ed903a 3005 u32 fwstate = bfa_ioc_get_cur_ioc_fwstate(ioc);
078086f3
RM		 3006
3007 if (fwstate == BFI_IOC_DISABLED) {
3008 bfa_fsm_send_event(&ioc->iocpf, IOCPF_E_FWREADY);
3009 return;
3010 }
3011
3012 if (ioc->iocpf.poll_time >= BFA_IOC_TOV) {
4818e856 3013 bfa_fsm_send_event(&ioc->iocpf, IOCPF_E_TIMEOUT);
078086f3
RM		 3014 } else {
3015 ioc->iocpf.poll_time += BFA_IOC_POLL_TOV;
3016 mod_timer(&ioc->iocpf_timer, jiffies +
3017 msecs_to_jiffies(BFA_IOC_POLL_TOV));
3018 }
3019}
72a9730b
KG		 3020
3021/*
3022 * Flash module specific
3023 */
3024
3025/*
3026 * FLASH DMA buffer should be big enough to hold both MFG block and
3027 * asic block(64k) at the same time and also should be 2k aligned to
3028 * avoid write segement to cross sector boundary.
3029 */
3030#define BFA_FLASH_SEG_SZ 2048
3031#define BFA_FLASH_DMA_BUF_SZ \
3032 roundup(0x010000 + sizeof(struct bfa_mfg_block), BFA_FLASH_SEG_SZ)
3033
3034static void
3035bfa_flash_cb(struct bfa_flash *flash)
3036{
3037 flash->op_busy = 0;
3038 if (flash->cbfn)
3039 flash->cbfn(flash->cbarg, flash->status);
3040}
3041
3042static void
3043bfa_flash_notify(void *cbarg, enum bfa_ioc_event event)
3044{
3045 struct bfa_flash *flash = cbarg;
3046
3047 switch (event) {
3048 case BFA_IOC_E_DISABLED:
3049 case BFA_IOC_E_FAILED:
3050 if (flash->op_busy) {
3051 flash->status = BFA_STATUS_IOC_FAILURE;
3052 flash->cbfn(flash->cbarg, flash->status);
3053 flash->op_busy = 0;
3054 }
3055 break;
3056 default:
3057 break;
3058 }
3059}
3060
3061/*
3062 * Send flash write request.
72a9730b
KG		 3063 */
3064static void
3065bfa_flash_write_send(struct bfa_flash *flash)
3066{
3067 struct bfi_flash_write_req *msg =
3068 (struct bfi_flash_write_req *) flash->mb.msg;
3069 u32 len;
3070
3071 msg->type = be32_to_cpu(flash->type);
3072 msg->instance = flash->instance;
3073 msg->offset = be32_to_cpu(flash->addr_off + flash->offset);
3074 len = (flash->residue < BFA_FLASH_DMA_BUF_SZ) ?
3075 flash->residue : BFA_FLASH_DMA_BUF_SZ;
3076 msg->length = be32_to_cpu(len);
3077
3078 /* indicate if it's the last msg of the whole write operation */
3079 msg->last = (len == flash->residue) ? 1 : 0;
3080
3081 bfi_h2i_set(msg->mh, BFI_MC_FLASH, BFI_FLASH_H2I_WRITE_REQ,
3082 bfa_ioc_portid(flash->ioc));
3083 bfa_alen_set(&msg->alen, len, flash->dbuf_pa);
3084 memcpy(flash->dbuf_kva, flash->ubuf + flash->offset, len);
3085 bfa_nw_ioc_mbox_queue(flash->ioc, &flash->mb, NULL, NULL);
3086
3087 flash->residue -= len;
3088 flash->offset += len;
3089}
3090
1aa8b471
BH		 3091/**
3092 * bfa_flash_read_send - Send flash read request.
72a9730b 3093 *
1aa8b471 3094 * @cbarg: callback argument
72a9730b
KG		 3095 */
3096static void
3097bfa_flash_read_send(void *cbarg)
3098{
3099 struct bfa_flash *flash = cbarg;
3100 struct bfi_flash_read_req *msg =
3101 (struct bfi_flash_read_req *) flash->mb.msg;
3102 u32 len;
3103
3104 msg->type = be32_to_cpu(flash->type);
3105 msg->instance = flash->instance;
3106 msg->offset = be32_to_cpu(flash->addr_off + flash->offset);
3107 len = (flash->residue < BFA_FLASH_DMA_BUF_SZ) ?
3108 flash->residue : BFA_FLASH_DMA_BUF_SZ;
3109 msg->length = be32_to_cpu(len);
3110 bfi_h2i_set(msg->mh, BFI_MC_FLASH, BFI_FLASH_H2I_READ_REQ,
3111 bfa_ioc_portid(flash->ioc));
3112 bfa_alen_set(&msg->alen, len, flash->dbuf_pa);
3113 bfa_nw_ioc_mbox_queue(flash->ioc, &flash->mb, NULL, NULL);
3114}
3115
1aa8b471
BH		 3116/**
3117 * bfa_flash_intr - Process flash response messages upon receiving interrupts.
72a9730b 3118 *
1aa8b471
BH		 3119 * @flasharg: flash structure
3120 * @msg: message structure
72a9730b
KG		 3121 */
3122static void
3123bfa_flash_intr(void *flasharg, struct bfi_mbmsg *msg)
3124{
3125 struct bfa_flash *flash = flasharg;
3126 u32 status;
3127
3128 union {
3129 struct bfi_flash_query_rsp *query;
3130 struct bfi_flash_write_rsp *write;
3131 struct bfi_flash_read_rsp *read;
3132 struct bfi_mbmsg *msg;
3133 } m;
3134
3135 m.msg = msg;
3136
3137 /* receiving response after ioc failure */
3138 if (!flash->op_busy && msg->mh.msg_id != BFI_FLASH_I2H_EVENT)
3139 return;
3140
3141 switch (msg->mh.msg_id) {
3142 case BFI_FLASH_I2H_QUERY_RSP:
3143 status = be32_to_cpu(m.query->status);
3144 if (status == BFA_STATUS_OK) {
3145 u32 i;
3146 struct bfa_flash_attr *attr, *f;
3147
3148 attr = (struct bfa_flash_attr *) flash->ubuf;
3149 f = (struct bfa_flash_attr *) flash->dbuf_kva;
3150 attr->status = be32_to_cpu(f->status);
3151 attr->npart = be32_to_cpu(f->npart);
3152 for (i = 0; i < attr->npart; i++) {
3153 attr->part[i].part_type =
3154 be32_to_cpu(f->part[i].part_type);
3155 attr->part[i].part_instance =
3156 be32_to_cpu(f->part[i].part_instance);
3157 attr->part[i].part_off =
3158 be32_to_cpu(f->part[i].part_off);
3159 attr->part[i].part_size =
3160 be32_to_cpu(f->part[i].part_size);
3161 attr->part[i].part_len =
3162 be32_to_cpu(f->part[i].part_len);
3163 attr->part[i].part_status =
3164 be32_to_cpu(f->part[i].part_status);
3165 }
3166 }
3167 flash->status = status;
3168 bfa_flash_cb(flash);
3169 break;
3170 case BFI_FLASH_I2H_WRITE_RSP:
3171 status = be32_to_cpu(m.write->status);
3172 if (status != BFA_STATUS_OK || flash->residue == 0) {
3173 flash->status = status;
3174 bfa_flash_cb(flash);
3175 } else
3176 bfa_flash_write_send(flash);
3177 break;
3178 case BFI_FLASH_I2H_READ_RSP:
3179 status = be32_to_cpu(m.read->status);
3180 if (status != BFA_STATUS_OK) {
3181 flash->status = status;
3182 bfa_flash_cb(flash);
3183 } else {
3184 u32 len = be32_to_cpu(m.read->length);
3185 memcpy(flash->ubuf + flash->offset,
3186 flash->dbuf_kva, len);
3187 flash->residue -= len;
3188 flash->offset += len;
3189 if (flash->residue == 0) {
3190 flash->status = status;
3191 bfa_flash_cb(flash);
3192 } else
3193 bfa_flash_read_send(flash);
3194 }
3195 break;
3196 case BFI_FLASH_I2H_BOOT_VER_RSP:
3197 case BFI_FLASH_I2H_EVENT:
3198 break;
3199 default:
3200 WARN_ON(1);
3201 }
3202}
3203
3204/*
3205 * Flash memory info API.
3206 */
3207u32
3208bfa_nw_flash_meminfo(void)
3209{
3210 return roundup(BFA_FLASH_DMA_BUF_SZ, BFA_DMA_ALIGN_SZ);
3211}
3212
1aa8b471
BH		 3213/**
3214 * bfa_nw_flash_attach - Flash attach API.
72a9730b 3215 *
1aa8b471
BH		 3216 * @flash: flash structure
3217 * @ioc: ioc structure
3218 * @dev: device structure
72a9730b
KG		 3219 */
3220void
3221bfa_nw_flash_attach(struct bfa_flash *flash, struct bfa_ioc *ioc, void *dev)
3222{
3223 flash->ioc = ioc;
3224 flash->cbfn = NULL;
3225 flash->cbarg = NULL;
3226 flash->op_busy = 0;
3227
3228 bfa_nw_ioc_mbox_regisr(flash->ioc, BFI_MC_FLASH, bfa_flash_intr, flash);
72a9730b
KG		 3229 bfa_ioc_notify_init(&flash->ioc_notify, bfa_flash_notify, flash);
3230 list_add_tail(&flash->ioc_notify.qe, &flash->ioc->notify_q);
3231}
3232
1aa8b471
BH		 3233/**
3234 * bfa_nw_flash_memclaim - Claim memory for flash
72a9730b 3235 *
1aa8b471
BH		 3236 * @flash: flash structure
3237 * @dm_kva: pointer to virtual memory address
3238 * @dm_pa: physical memory address
72a9730b
KG		 3239 */
3240void
3241bfa_nw_flash_memclaim(struct bfa_flash *flash, u8 *dm_kva, u64 dm_pa)
3242{
3243 flash->dbuf_kva = dm_kva;
3244 flash->dbuf_pa = dm_pa;
3245 memset(flash->dbuf_kva, 0, BFA_FLASH_DMA_BUF_SZ);
3246 dm_kva += roundup(BFA_FLASH_DMA_BUF_SZ, BFA_DMA_ALIGN_SZ);
3247 dm_pa += roundup(BFA_FLASH_DMA_BUF_SZ, BFA_DMA_ALIGN_SZ);
3248}
3249
1aa8b471
BH		 3250/**
3251 * bfa_nw_flash_get_attr - Get flash attribute.
72a9730b 3252 *
1aa8b471
BH		 3253 * @flash: flash structure
3254 * @attr: flash attribute structure
3255 * @cbfn: callback function
3256 * @cbarg: callback argument
72a9730b
KG		 3257 *
3258 * Return status.
3259 */
3260enum bfa_status
3261bfa_nw_flash_get_attr(struct bfa_flash *flash, struct bfa_flash_attr *attr,
3262 bfa_cb_flash cbfn, void *cbarg)
3263{
3264 struct bfi_flash_query_req *msg =
3265 (struct bfi_flash_query_req *) flash->mb.msg;
3266
3267 if (!bfa_nw_ioc_is_operational(flash->ioc))
3268 return BFA_STATUS_IOC_NON_OP;
3269
3270 if (flash->op_busy)
3271 return BFA_STATUS_DEVBUSY;
3272
3273 flash->op_busy = 1;
3274 flash->cbfn = cbfn;
3275 flash->cbarg = cbarg;
3276 flash->ubuf = (u8 *) attr;
3277
3278 bfi_h2i_set(msg->mh, BFI_MC_FLASH, BFI_FLASH_H2I_QUERY_REQ,
3279 bfa_ioc_portid(flash->ioc));
3280 bfa_alen_set(&msg->alen, sizeof(struct bfa_flash_attr), flash->dbuf_pa);
3281 bfa_nw_ioc_mbox_queue(flash->ioc, &flash->mb, NULL, NULL);
3282
3283 return BFA_STATUS_OK;
3284}
3285
1aa8b471
BH		 3286/**
3287 * bfa_nw_flash_update_part - Update flash partition.
72a9730b 3288 *
1aa8b471
BH		 3289 * @flash: flash structure
3290 * @type: flash partition type
3291 * @instance: flash partition instance
3292 * @buf: update data buffer
3293 * @len: data buffer length
3294 * @offset: offset relative to the partition starting address
3295 * @cbfn: callback function
3296 * @cbarg: callback argument
72a9730b
KG		 3297 *
3298 * Return status.
3299 */
3300enum bfa_status
3301bfa_nw_flash_update_part(struct bfa_flash *flash, u32 type, u8 instance,
3302 void *buf, u32 len, u32 offset,
3303 bfa_cb_flash cbfn, void *cbarg)
3304{
3305 if (!bfa_nw_ioc_is_operational(flash->ioc))
3306 return BFA_STATUS_IOC_NON_OP;
3307
3308 /*
3309 * 'len' must be in word (4-byte) boundary
3310 */
3311 if (!len || (len & 0x03))
3312 return BFA_STATUS_FLASH_BAD_LEN;
3313
3314 if (type == BFA_FLASH_PART_MFG)
3315 return BFA_STATUS_EINVAL;
3316
3317 if (flash->op_busy)
3318 return BFA_STATUS_DEVBUSY;
3319
3320 flash->op_busy = 1;
3321 flash->cbfn = cbfn;
3322 flash->cbarg = cbarg;
3323 flash->type = type;
3324 flash->instance = instance;
3325 flash->residue = len;
3326 flash->offset = 0;
3327 flash->addr_off = offset;
3328 flash->ubuf = buf;
3329
3330 bfa_flash_write_send(flash);
3331
3332 return BFA_STATUS_OK;
3333}
3334
1aa8b471
BH		 3335/**
3336 * bfa_nw_flash_read_part - Read flash partition.
72a9730b 3337 *
1aa8b471
BH		 3338 * @flash: flash structure
3339 * @type: flash partition type
3340 * @instance: flash partition instance
3341 * @buf: read data buffer
3342 * @len: data buffer length
3343 * @offset: offset relative to the partition starting address
3344 * @cbfn: callback function
3345 * @cbarg: callback argument
72a9730b
KG		 3346 *
3347 * Return status.
3348 */
3349enum bfa_status
3350bfa_nw_flash_read_part(struct bfa_flash *flash, u32 type, u8 instance,
3351 void *buf, u32 len, u32 offset,
3352 bfa_cb_flash cbfn, void *cbarg)
3353{
3354 if (!bfa_nw_ioc_is_operational(flash->ioc))
3355 return BFA_STATUS_IOC_NON_OP;
3356
3357 /*
3358 * 'len' must be in word (4-byte) boundary
3359 */
3360 if (!len || (len & 0x03))
3361 return BFA_STATUS_FLASH_BAD_LEN;
3362
3363 if (flash->op_busy)
3364 return BFA_STATUS_DEVBUSY;
3365
3366 flash->op_busy = 1;
3367 flash->cbfn = cbfn;
3368 flash->cbarg = cbarg;
3369 flash->type = type;
3370 flash->instance = instance;
3371 flash->residue = len;
3372 flash->offset = 0;
3373 flash->addr_off = offset;
3374 flash->ubuf = buf;
3375
3376 bfa_flash_read_send(flash);
3377
3378 return BFA_STATUS_OK;
3379}
Linux kernel - Deliverables
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