[deliverable/linux.git] / drivers / net / ethernet / brocade / bna / bfa_ioc.h

/*
 * Linux network driver for QLogic BR-series Converged Network Adapter.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License (GPL) Version 2 as
 * published by the Free Software Foundation
 *
 * This program is distributed in the hope that it will be useful, but
 * WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * General Public License for more details.
 */
/*
 * Copyright (c) 2005-2014 Brocade Communications Systems, Inc.
 * Copyright (c) 2014-2015 QLogic Corporation
 * All rights reserved
 * www.qlogic.com
 */

#ifndef __BFA_IOC_H__
#define __BFA_IOC_H__

#include "bfa_cs.h"
#include "bfi.h"
#include "cna.h"

#define BFA_IOC_TOV		3000	/* msecs */
#define BFA_IOC_HWSEM_TOV	500	/* msecs */
#define BFA_IOC_HB_TOV		500	/* msecs */
#define BFA_IOC_POLL_TOV	200	/* msecs */
#define BNA_DBG_FWTRC_LEN      (BFI_IOC_TRC_ENTS * BFI_IOC_TRC_ENT_SZ + \
				BFI_IOC_TRC_HDR_SZ)

/* PCI device information required by IOC */
struct bfa_pcidev {
	int	pci_slot;
	u8	pci_func;
	u16	device_id;
	u16	ssid;
	void	__iomem *pci_bar_kva;
};

/* Structure used to remember the DMA-able memory block's KVA and Physical
 * Address
 */
struct bfa_dma {
	void	*kva;	/* ! Kernel virtual address	*/
	u64	pa;	/* ! Physical address		*/
};

#define BFA_DMA_ALIGN_SZ	256

/* smem size for Crossbow and Catapult */
#define BFI_SMEM_CB_SIZE	0x200000U	/* ! 2MB for crossbow	*/
#define BFI_SMEM_CT_SIZE	0x280000U	/* ! 2.5MB for catapult	*/

/* BFA dma address assignment macro. (big endian format) */
#define bfa_dma_be_addr_set(dma_addr, pa)	\
		__bfa_dma_be_addr_set(&dma_addr, (u64)pa)
static inline void
__bfa_dma_be_addr_set(union bfi_addr_u *dma_addr, u64 pa)
{
	dma_addr->a32.addr_lo = (u32) htonl(pa);
	dma_addr->a32.addr_hi = (u32) htonl(upper_32_bits(pa));
}

#define bfa_alen_set(__alen, __len, __pa)	\
	__bfa_alen_set(__alen, __len, (u64)__pa)

static inline void
__bfa_alen_set(struct bfi_alen *alen, u32 len, u64 pa)
{
	alen->al_len = cpu_to_be32(len);
	bfa_dma_be_addr_set(alen->al_addr, pa);
}

struct bfa_ioc_regs {
	void __iomem *hfn_mbox_cmd;
	void __iomem *hfn_mbox;
	void __iomem *lpu_mbox_cmd;
	void __iomem *lpu_mbox;
	void __iomem *lpu_read_stat;
	void __iomem *pss_ctl_reg;
	void __iomem *pss_err_status_reg;
	void __iomem *app_pll_fast_ctl_reg;
	void __iomem *app_pll_slow_ctl_reg;
	void __iomem *ioc_sem_reg;
	void __iomem *ioc_usage_sem_reg;
	void __iomem *ioc_init_sem_reg;
	void __iomem *ioc_usage_reg;
	void __iomem *host_page_num_fn;
	void __iomem *heartbeat;
	void __iomem *ioc_fwstate;
	void __iomem *alt_ioc_fwstate;
	void __iomem *ll_halt;
	void __iomem *alt_ll_halt;
	void __iomem *err_set;
	void __iomem *ioc_fail_sync;
	void __iomem *shirq_isr_next;
	void __iomem *shirq_msk_next;
	void __iomem *smem_page_start;
	u32	smem_pg0;
};

/* IOC Mailbox structures */
typedef void (*bfa_mbox_cmd_cbfn_t)(void *cbarg);
struct bfa_mbox_cmd {
	struct list_head	qe;
	bfa_mbox_cmd_cbfn_t     cbfn;
	void		    *cbarg;
	u32     msg[BFI_IOC_MSGSZ];
};

/* IOC mailbox module */
typedef void (*bfa_ioc_mbox_mcfunc_t)(void *cbarg, struct bfi_mbmsg *m);
struct bfa_ioc_mbox_mod {
	struct list_head	cmd_q;		/*!< pending mbox queue	*/
	int			nmclass;	/*!< number of handlers */
	struct {
		bfa_ioc_mbox_mcfunc_t	cbfn;	/*!< message handlers	*/
		void			*cbarg;
	} mbhdlr[BFI_MC_MAX];
};

/* IOC callback function interfaces */
typedef void (*bfa_ioc_enable_cbfn_t)(void *bfa, enum bfa_status status);
typedef void (*bfa_ioc_disable_cbfn_t)(void *bfa);
typedef void (*bfa_ioc_hbfail_cbfn_t)(void *bfa);
typedef void (*bfa_ioc_reset_cbfn_t)(void *bfa);
struct bfa_ioc_cbfn {
	bfa_ioc_enable_cbfn_t	enable_cbfn;
	bfa_ioc_disable_cbfn_t	disable_cbfn;
	bfa_ioc_hbfail_cbfn_t	hbfail_cbfn;
	bfa_ioc_reset_cbfn_t	reset_cbfn;
};

/* IOC event notification mechanism. */
enum bfa_ioc_event {
	BFA_IOC_E_ENABLED	= 1,
	BFA_IOC_E_DISABLED	= 2,
	BFA_IOC_E_FAILED	= 3,
};

typedef void (*bfa_ioc_notify_cbfn_t)(void *, enum bfa_ioc_event);

struct bfa_ioc_notify {
	struct list_head	qe;
	bfa_ioc_notify_cbfn_t	cbfn;
	void			*cbarg;
};

/* Initialize a IOC event notification structure */
#define bfa_ioc_notify_init(__notify, __cbfn, __cbarg) do {	\
	(__notify)->cbfn = (__cbfn);				\
	(__notify)->cbarg = (__cbarg);				\
} while (0)

struct bfa_iocpf {
	bfa_fsm_t		fsm;
	struct bfa_ioc		*ioc;
	bool			fw_mismatch_notified;
	bool			auto_recover;
	u32			poll_time;
};

struct bfa_ioc {
	bfa_fsm_t		fsm;
	struct bfa		*bfa;
	struct bfa_pcidev	pcidev;
	struct timer_list	ioc_timer;
	struct timer_list	iocpf_timer;
	struct timer_list	sem_timer;
	struct timer_list	hb_timer;
	u32			hb_count;
	struct list_head	notify_q;
	void			*dbg_fwsave;
	int			dbg_fwsave_len;
	bool			dbg_fwsave_once;
	enum bfi_pcifn_class	clscode;
	struct bfa_ioc_regs	ioc_regs;
	struct bfa_ioc_drv_stats stats;
	bool			fcmode;
	bool			pllinit;
	bool			stats_busy;	/*!< outstanding stats */
	u8			port_id;

	struct bfa_dma		attr_dma;
	struct bfi_ioc_attr	*attr;
	struct bfa_ioc_cbfn	*cbfn;
	struct bfa_ioc_mbox_mod	mbox_mod;
	const struct bfa_ioc_hwif *ioc_hwif;
	struct bfa_iocpf	iocpf;
	enum bfi_asic_gen	asic_gen;
	enum bfi_asic_mode	asic_mode;
	enum bfi_port_mode	port0_mode;
	enum bfi_port_mode	port1_mode;
	enum bfa_mode		port_mode;
	u8			ad_cap_bm;	/*!< adapter cap bit mask */
	u8			port_mode_cfg;	/*!< config port mode */
};

struct bfa_ioc_hwif {
	enum bfa_status (*ioc_pll_init) (void __iomem *rb,
						enum bfi_asic_mode m);
	bool		(*ioc_firmware_lock)	(struct bfa_ioc *ioc);
	void		(*ioc_firmware_unlock)	(struct bfa_ioc *ioc);
	void		(*ioc_reg_init)	(struct bfa_ioc *ioc);
	void		(*ioc_map_port)	(struct bfa_ioc *ioc);
	void		(*ioc_isr_mode_set)	(struct bfa_ioc *ioc,
					bool msix);
	void		(*ioc_notify_fail)	(struct bfa_ioc *ioc);
	void		(*ioc_ownership_reset)	(struct bfa_ioc *ioc);
	bool		(*ioc_sync_start)       (struct bfa_ioc *ioc);
	void		(*ioc_sync_join)	(struct bfa_ioc *ioc);
	void		(*ioc_sync_leave)	(struct bfa_ioc *ioc);
	void		(*ioc_sync_ack)		(struct bfa_ioc *ioc);
	bool		(*ioc_sync_complete)	(struct bfa_ioc *ioc);
	bool		(*ioc_lpu_read_stat)	(struct bfa_ioc *ioc);
	void		(*ioc_set_fwstate)	(struct bfa_ioc *ioc,
					enum bfi_ioc_state fwstate);
	enum bfi_ioc_state (*ioc_get_fwstate) (struct bfa_ioc *ioc);
	void		(*ioc_set_alt_fwstate)	(struct bfa_ioc *ioc,
					enum bfi_ioc_state fwstate);
	enum bfi_ioc_state (*ioc_get_alt_fwstate) (struct bfa_ioc *ioc);

};

#define bfa_ioc_pcifn(__ioc)		((__ioc)->pcidev.pci_func)
#define bfa_ioc_devid(__ioc)		((__ioc)->pcidev.device_id)
#define bfa_ioc_bar0(__ioc)		((__ioc)->pcidev.pci_bar_kva)
#define bfa_ioc_portid(__ioc)		((__ioc)->port_id)
#define bfa_ioc_asic_gen(__ioc)		((__ioc)->asic_gen)
#define bfa_ioc_is_default(__ioc)	\
	(bfa_ioc_pcifn(__ioc) == bfa_ioc_portid(__ioc))
#define bfa_ioc_speed_sup(__ioc)	\
	BFI_ADAPTER_GETP(SPEED, (__ioc)->attr->adapter_prop)
#define bfa_ioc_get_nports(__ioc)	\
	BFI_ADAPTER_GETP(NPORTS, (__ioc)->attr->adapter_prop)

#define bfa_ioc_stats(_ioc, _stats)	((_ioc)->stats._stats++)
#define bfa_ioc_stats_hb_count(_ioc, _hb_count)	\
	((_ioc)->stats.hb_count = (_hb_count))
#define BFA_IOC_FWIMG_MINSZ	(16 * 1024)
#define BFA_IOC_FW_SMEM_SIZE(__ioc)					\
	((bfa_ioc_asic_gen(__ioc) == BFI_ASIC_GEN_CB)			\
	? BFI_SMEM_CB_SIZE : BFI_SMEM_CT_SIZE)
#define BFA_IOC_FLASH_CHUNK_NO(off)		(off / BFI_FLASH_CHUNK_SZ_WORDS)
#define BFA_IOC_FLASH_OFFSET_IN_CHUNK(off)	(off % BFI_FLASH_CHUNK_SZ_WORDS)
#define BFA_IOC_FLASH_CHUNK_ADDR(chunkno)  (chunkno * BFI_FLASH_CHUNK_SZ_WORDS)

/* IOC mailbox interface */
bool bfa_nw_ioc_mbox_queue(struct bfa_ioc *ioc,
			struct bfa_mbox_cmd *cmd,
			bfa_mbox_cmd_cbfn_t cbfn, void *cbarg);
void bfa_nw_ioc_mbox_isr(struct bfa_ioc *ioc);
void bfa_nw_ioc_mbox_regisr(struct bfa_ioc *ioc, enum bfi_mclass mc,
		bfa_ioc_mbox_mcfunc_t cbfn, void *cbarg);

/* IOC interfaces */

#define bfa_ioc_pll_init_asic(__ioc) \
	((__ioc)->ioc_hwif->ioc_pll_init((__ioc)->pcidev.pci_bar_kva, \
			   (__ioc)->asic_mode))

#define bfa_ioc_lpu_read_stat(__ioc) do {				\
		if ((__ioc)->ioc_hwif->ioc_lpu_read_stat)		\
			((__ioc)->ioc_hwif->ioc_lpu_read_stat(__ioc));	\
} while (0)

void bfa_nw_ioc_set_ct_hwif(struct bfa_ioc *ioc);
void bfa_nw_ioc_set_ct2_hwif(struct bfa_ioc *ioc);
void bfa_nw_ioc_ct2_poweron(struct bfa_ioc *ioc);

void bfa_nw_ioc_attach(struct bfa_ioc *ioc, void *bfa,
		struct bfa_ioc_cbfn *cbfn);
void bfa_nw_ioc_auto_recover(bool auto_recover);
void bfa_nw_ioc_detach(struct bfa_ioc *ioc);
void bfa_nw_ioc_pci_init(struct bfa_ioc *ioc, struct bfa_pcidev *pcidev,
		enum bfi_pcifn_class clscode);
u32 bfa_nw_ioc_meminfo(void);
void bfa_nw_ioc_mem_claim(struct bfa_ioc *ioc,  u8 *dm_kva, u64 dm_pa);
void bfa_nw_ioc_enable(struct bfa_ioc *ioc);
void bfa_nw_ioc_disable(struct bfa_ioc *ioc);

void bfa_nw_ioc_error_isr(struct bfa_ioc *ioc);
bool bfa_nw_ioc_is_disabled(struct bfa_ioc *ioc);
bool bfa_nw_ioc_is_operational(struct bfa_ioc *ioc);
void bfa_nw_ioc_get_attr(struct bfa_ioc *ioc, struct bfa_ioc_attr *ioc_attr);
enum bfa_status bfa_nw_ioc_fwsig_invalidate(struct bfa_ioc *ioc);
void bfa_nw_ioc_notify_register(struct bfa_ioc *ioc,
	struct bfa_ioc_notify *notify);
bool bfa_nw_ioc_sem_get(void __iomem *sem_reg);
void bfa_nw_ioc_sem_release(void __iomem *sem_reg);
void bfa_nw_ioc_hw_sem_release(struct bfa_ioc *ioc);
void bfa_nw_ioc_fwver_get(struct bfa_ioc *ioc,
			struct bfi_ioc_image_hdr *fwhdr);
bool bfa_nw_ioc_fwver_cmp(struct bfa_ioc *ioc,
			struct bfi_ioc_image_hdr *fwhdr);
void bfa_nw_ioc_get_mac(struct bfa_ioc *ioc, u8 *mac);
void bfa_nw_ioc_debug_memclaim(struct bfa_ioc *ioc, void *dbg_fwsave);
int bfa_nw_ioc_debug_fwtrc(struct bfa_ioc *ioc, void *trcdata, int *trclen);
int bfa_nw_ioc_debug_fwsave(struct bfa_ioc *ioc, void *trcdata, int *trclen);

/*
 * Timeout APIs
 */
void bfa_nw_ioc_timeout(struct bfa_ioc *ioc);
void bfa_nw_ioc_hb_check(struct bfa_ioc *ioc);
void bfa_nw_iocpf_timeout(struct bfa_ioc *ioc);
void bfa_nw_iocpf_sem_timeout(struct bfa_ioc *ioc);

/*
 * F/W Image Size & Chunk
 */
u32 *bfa_cb_image_get_chunk(enum bfi_asic_gen asic_gen, u32 off);
u32 bfa_cb_image_get_size(enum bfi_asic_gen asic_gen);

/*
 *	Flash module specific
 */
typedef void	(*bfa_cb_flash) (void *cbarg, enum bfa_status status);

struct bfa_flash {
	struct bfa_ioc *ioc;		/* back pointer to ioc */
	u32		type;		/* partition type */
	u8		instance;	/* partition instance */
	u8		rsv[3];
	u32		op_busy;	/*  operation busy flag */
	u32		residue;	/*  residual length */
	u32		offset;		/*  offset */
	enum bfa_status	status;		/*  status */
	u8		*dbuf_kva;	/*  dma buf virtual address */
	u64		dbuf_pa;	/*  dma buf physical address */
	bfa_cb_flash	cbfn;		/*  user callback function */
	void		*cbarg;		/*  user callback arg */
	u8		*ubuf;		/*  user supplied buffer */
	u32		addr_off;	/*  partition address offset */
	struct bfa_mbox_cmd mb;		/*  mailbox */
	struct bfa_ioc_notify ioc_notify; /*  ioc event notify */
};

enum bfa_status bfa_nw_flash_get_attr(struct bfa_flash *flash,
			struct bfa_flash_attr *attr,
			bfa_cb_flash cbfn, void *cbarg);
enum bfa_status bfa_nw_flash_update_part(struct bfa_flash *flash,
			u32 type, u8 instance, void *buf, u32 len, u32 offset,
			bfa_cb_flash cbfn, void *cbarg);
enum bfa_status bfa_nw_flash_read_part(struct bfa_flash *flash,
			u32 type, u8 instance, void *buf, u32 len, u32 offset,
			bfa_cb_flash cbfn, void *cbarg);
u32	bfa_nw_flash_meminfo(void);
void	bfa_nw_flash_attach(struct bfa_flash *flash,
			    struct bfa_ioc *ioc, void *dev);
void	bfa_nw_flash_memclaim(struct bfa_flash *flash, u8 *dm_kva, u64 dm_pa);

#endif /* __BFA_IOC_H__ */
Commit	Line	Data
8b230ed8	1	/*
2732ba56	2	* Linux network driver for QLogic BR-series Converged Network Adapter.
8b230ed8 RM	3	*
	4	* This program is free software; you can redistribute it and/or modify it
	5	* under the terms of the GNU General Public License (GPL) Version 2 as
	6	* published by the Free Software Foundation
	7	*
	8	* This program is distributed in the hope that it will be useful, but
	9	* WITHOUT ANY WARRANTY; without even the implied warranty of
	10	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	11	* General Public License for more details.
	12	*/
	13	/*
2732ba56 RM	14	* Copyright (c) 2005-2014 Brocade Communications Systems, Inc.
2732ba56 RM	15	* Copyright (c) 2014-2015 QLogic Corporation
8b230ed8	16	* All rights reserved
2732ba56	17	* www.qlogic.com
8b230ed8 RM	18	*/
	19
	20	#ifndef __BFA_IOC_H__
	21	#define __BFA_IOC_H__
	22
758ccc34	23	#include "bfa_cs.h"
8b230ed8 RM	24	#include "bfi.h"
	25	#include "cna.h"
	26
	27	#define BFA_IOC_TOV 3000 /* msecs */
	28	#define BFA_IOC_HWSEM_TOV 500 /* msecs */
	29	#define BFA_IOC_HB_TOV 500 /* msecs */
078086f3	30	#define BFA_IOC_POLL_TOV 200 /* msecs */
7afc5dbd KG	31	#define BNA_DBG_FWTRC_LEN (BFI_IOC_TRC_ENTS * BFI_IOC_TRC_ENT_SZ + \
7afc5dbd KG	32	BFI_IOC_TRC_HDR_SZ)
8b230ed8	33
1aa8b471	34	/* PCI device information required by IOC */
8b230ed8 RM	35	struct bfa_pcidev {
	36	int pci_slot;
	37	u8 pci_func;
	38	u16 device_id;
586b2816	39	u16 ssid;
8b230ed8 RM	40	void __iomem *pci_bar_kva;
	41	};
	42
1aa8b471	43	/* Structure used to remember the DMA-able memory block's KVA and Physical
8b230ed8 RM	44	* Address
	45	*/
	46	struct bfa_dma {
	47	void kva; / ! Kernel virtual address */
	48	u64 pa; /* ! Physical address */
	49	};
	50
	51	#define BFA_DMA_ALIGN_SZ 256
	52
1aa8b471	53	/* smem size for Crossbow and Catapult */
8b230ed8 RM	54	#define BFI_SMEM_CB_SIZE 0x200000U /* ! 2MB for crossbow */
	55	#define BFI_SMEM_CT_SIZE 0x280000U /* ! 2.5MB for catapult */
	56
1aa8b471	57	/* BFA dma address assignment macro. (big endian format) */
8b230ed8 RM	58	#define bfa_dma_be_addr_set(dma_addr, pa) \
	59	__bfa_dma_be_addr_set(&dma_addr, (u64)pa)
	60	static inline void
	61	__bfa_dma_be_addr_set(union bfi_addr_u *dma_addr, u64 pa)
	62	{
	63	dma_addr->a32.addr_lo = (u32) htonl(pa);
	64	dma_addr->a32.addr_hi = (u32) htonl(upper_32_bits(pa));
	65	}
	66
72a9730b KG	67	#define bfa_alen_set(__alen, __len, __pa) \
	68	__bfa_alen_set(__alen, __len, (u64)__pa)
	69
	70	static inline void
	71	__bfa_alen_set(struct bfi_alen *alen, u32 len, u64 pa)
	72	{
	73	alen->al_len = cpu_to_be32(len);
	74	bfa_dma_be_addr_set(alen->al_addr, pa);
	75	}
	76
8b230ed8 RM	77	struct bfa_ioc_regs {
	78	void __iomem *hfn_mbox_cmd;
	79	void __iomem *hfn_mbox;
	80	void __iomem *lpu_mbox_cmd;
	81	void __iomem *lpu_mbox;
be3a84d1	82	void __iomem *lpu_read_stat;
8b230ed8 RM	83	void __iomem *pss_ctl_reg;
	84	void __iomem *pss_err_status_reg;
	85	void __iomem *app_pll_fast_ctl_reg;
	86	void __iomem *app_pll_slow_ctl_reg;
	87	void __iomem *ioc_sem_reg;
	88	void __iomem *ioc_usage_sem_reg;
	89	void __iomem *ioc_init_sem_reg;
	90	void __iomem *ioc_usage_reg;
	91	void __iomem *host_page_num_fn;
	92	void __iomem *heartbeat;
	93	void __iomem *ioc_fwstate;
1d32f769	94	void __iomem *alt_ioc_fwstate;
8b230ed8	95	void __iomem *ll_halt;
1d32f769	96	void __iomem *alt_ll_halt;
8b230ed8	97	void __iomem *err_set;
1d32f769	98	void __iomem *ioc_fail_sync;
8b230ed8 RM	99	void __iomem *shirq_isr_next;
	100	void __iomem *shirq_msk_next;
	101	void __iomem *smem_page_start;
	102	u32 smem_pg0;
	103	};
	104
1aa8b471	105	/* IOC Mailbox structures */
bd5a92e9	106	typedef void (bfa_mbox_cmd_cbfn_t)(void cbarg);
8b230ed8 RM	107	struct bfa_mbox_cmd {
8b230ed8 RM	108	struct list_head qe;
bd5a92e9 RM	109	bfa_mbox_cmd_cbfn_t cbfn;
	110	void *cbarg;
	111	u32 msg[BFI_IOC_MSGSZ];
8b230ed8 RM	112	};
8b230ed8 RM	113
1aa8b471	114	/* IOC mailbox module */
8b230ed8 RM	115	typedef void (bfa_ioc_mbox_mcfunc_t)(void cbarg, struct bfi_mbmsg *m);
	116	struct bfa_ioc_mbox_mod {
	117	struct list_head cmd_q; /!< pending mbox queue /
	118	int nmclass; /!< number of handlers /
	119	struct {
	120	bfa_ioc_mbox_mcfunc_t cbfn; /!< message handlers /
	121	void *cbarg;
	122	} mbhdlr[BFI_MC_MAX];
	123	};
	124
1aa8b471	125	/* IOC callback function interfaces */
8b230ed8 RM	126	typedef void (bfa_ioc_enable_cbfn_t)(void bfa, enum bfa_status status);
	127	typedef void (bfa_ioc_disable_cbfn_t)(void bfa);
	128	typedef void (bfa_ioc_hbfail_cbfn_t)(void bfa);
	129	typedef void (bfa_ioc_reset_cbfn_t)(void bfa);
	130	struct bfa_ioc_cbfn {
	131	bfa_ioc_enable_cbfn_t enable_cbfn;
	132	bfa_ioc_disable_cbfn_t disable_cbfn;
	133	bfa_ioc_hbfail_cbfn_t hbfail_cbfn;
	134	bfa_ioc_reset_cbfn_t reset_cbfn;
	135	};
	136
1aa8b471	137	/* IOC event notification mechanism. */
bd5a92e9 RM	138	enum bfa_ioc_event {
	139	BFA_IOC_E_ENABLED = 1,
	140	BFA_IOC_E_DISABLED = 2,
	141	BFA_IOC_E_FAILED = 3,
	142	};
	143
	144	typedef void (bfa_ioc_notify_cbfn_t)(void , enum bfa_ioc_event);
	145
	146	struct bfa_ioc_notify {
	147	struct list_head qe;
	148	bfa_ioc_notify_cbfn_t cbfn;
	149	void *cbarg;
	150	};
	151
1aa8b471	152	/* Initialize a IOC event notification structure */
bd5a92e9	153	#define bfa_ioc_notify_init(__notify, __cbfn, __cbarg) do { \
8b230ed8 RM	154	(__notify)->cbfn = (__cbfn); \
	155	(__notify)->cbarg = (__cbarg); \
	156	} while (0)
	157
1d32f769 RM	158	struct bfa_iocpf {
	159	bfa_fsm_t fsm;
	160	struct bfa_ioc *ioc;
078086f3	161	bool fw_mismatch_notified;
1d32f769	162	bool auto_recover;
078086f3	163	u32 poll_time;
1d32f769 RM	164	};
1d32f769 RM	165
8b230ed8 RM	166	struct bfa_ioc {
8b230ed8 RM	167	bfa_fsm_t fsm;
0120b99c RM	168	struct bfa *bfa;
	169	struct bfa_pcidev pcidev;
	170	struct timer_list ioc_timer;
	171	struct timer_list iocpf_timer;
	172	struct timer_list sem_timer;
8b230ed8 RM	173	struct timer_list hb_timer;
8b230ed8 RM	174	u32 hb_count;
bd5a92e9	175	struct list_head notify_q;
8b230ed8 RM	176	void *dbg_fwsave;
	177	int dbg_fwsave_len;
	178	bool dbg_fwsave_once;
078086f3	179	enum bfi_pcifn_class clscode;
0120b99c	180	struct bfa_ioc_regs ioc_regs;
8b230ed8	181	struct bfa_ioc_drv_stats stats;
8b230ed8	182	bool fcmode;
8b230ed8	183	bool pllinit;
0120b99c	184	bool stats_busy; /!< outstanding stats /
8b230ed8 RM	185	u8 port_id;
	186
	187	struct bfa_dma attr_dma;
	188	struct bfi_ioc_attr *attr;
	189	struct bfa_ioc_cbfn *cbfn;
	190	struct bfa_ioc_mbox_mod mbox_mod;
d91d25d5	191	const struct bfa_ioc_hwif *ioc_hwif;
1d32f769	192	struct bfa_iocpf iocpf;
078086f3 RM	193	enum bfi_asic_gen asic_gen;
	194	enum bfi_asic_mode asic_mode;
	195	enum bfi_port_mode port0_mode;
	196	enum bfi_port_mode port1_mode;
	197	enum bfa_mode port_mode;
	198	u8 ad_cap_bm; /!< adapter cap bit mask /
	199	u8 port_mode_cfg; /!< config port mode /
8b230ed8 RM	200	};
	201
	202	struct bfa_ioc_hwif {
078086f3 RM	203	enum bfa_status (ioc_pll_init) (void __iomem rb,
078086f3 RM	204	enum bfi_asic_mode m);
8b230ed8 RM	205	bool (ioc_firmware_lock) (struct bfa_ioc ioc);
	206	void (ioc_firmware_unlock) (struct bfa_ioc ioc);
	207	void (ioc_reg_init) (struct bfa_ioc ioc);
	208	void (ioc_map_port) (struct bfa_ioc ioc);
	209	void (ioc_isr_mode_set) (struct bfa_ioc ioc,
	210	bool msix);
1d32f769	211	void (ioc_notify_fail) (struct bfa_ioc ioc);
8b230ed8	212	void (ioc_ownership_reset) (struct bfa_ioc ioc);
79ea6c89	213	bool (ioc_sync_start) (struct bfa_ioc ioc);
1d32f769 RM	214	void (ioc_sync_join) (struct bfa_ioc ioc);
	215	void (ioc_sync_leave) (struct bfa_ioc ioc);
	216	void (ioc_sync_ack) (struct bfa_ioc ioc);
	217	bool (ioc_sync_complete) (struct bfa_ioc ioc);
078086f3	218	bool (ioc_lpu_read_stat) (struct bfa_ioc ioc);
41ed903a RM	219	void (ioc_set_fwstate) (struct bfa_ioc ioc,
	220	enum bfi_ioc_state fwstate);
	221	enum bfi_ioc_state (ioc_get_fwstate) (struct bfa_ioc ioc);
	222	void (ioc_set_alt_fwstate) (struct bfa_ioc ioc,
	223	enum bfi_ioc_state fwstate);
	224	enum bfi_ioc_state (ioc_get_alt_fwstate) (struct bfa_ioc ioc);
	225
8b230ed8 RM	226	};
	227
	228	#define bfa_ioc_pcifn(__ioc) ((__ioc)->pcidev.pci_func)
	229	#define bfa_ioc_devid(__ioc) ((__ioc)->pcidev.device_id)
	230	#define bfa_ioc_bar0(__ioc) ((__ioc)->pcidev.pci_bar_kva)
	231	#define bfa_ioc_portid(__ioc) ((__ioc)->port_id)
078086f3	232	#define bfa_ioc_asic_gen(__ioc) ((__ioc)->asic_gen)
43c07ada RM	233	#define bfa_ioc_is_default(__ioc) \
43c07ada RM	234	(bfa_ioc_pcifn(__ioc) == bfa_ioc_portid(__ioc))
8b230ed8 RM	235	#define bfa_ioc_speed_sup(__ioc) \
	236	BFI_ADAPTER_GETP(SPEED, (__ioc)->attr->adapter_prop)
	237	#define bfa_ioc_get_nports(__ioc) \
	238	BFI_ADAPTER_GETP(NPORTS, (__ioc)->attr->adapter_prop)
	239
	240	#define bfa_ioc_stats(_ioc, _stats) ((_ioc)->stats._stats++)
9b08a4fc RM	241	#define bfa_ioc_stats_hb_count(_ioc, _hb_count) \
9b08a4fc RM	242	((_ioc)->stats.hb_count = (_hb_count))
8b230ed8	243	#define BFA_IOC_FWIMG_MINSZ (16 * 1024)
8b230ed8	244	#define BFA_IOC_FW_SMEM_SIZE(__ioc) \
078086f3 RM	245	((bfa_ioc_asic_gen(__ioc) == BFI_ASIC_GEN_CB) \
078086f3 RM	246	? BFI_SMEM_CB_SIZE : BFI_SMEM_CT_SIZE)
8b230ed8 RM	247	#define BFA_IOC_FLASH_CHUNK_NO(off) (off / BFI_FLASH_CHUNK_SZ_WORDS)
	248	#define BFA_IOC_FLASH_OFFSET_IN_CHUNK(off) (off % BFI_FLASH_CHUNK_SZ_WORDS)
	249	#define BFA_IOC_FLASH_CHUNK_ADDR(chunkno) (chunkno * BFI_FLASH_CHUNK_SZ_WORDS)
	250
1aa8b471	251	/* IOC mailbox interface */
af027a34 RM	252	bool bfa_nw_ioc_mbox_queue(struct bfa_ioc *ioc,
	253	struct bfa_mbox_cmd *cmd,
	254	bfa_mbox_cmd_cbfn_t cbfn, void *cbarg);
8a891429 RM	255	void bfa_nw_ioc_mbox_isr(struct bfa_ioc *ioc);
8a891429 RM	256	void bfa_nw_ioc_mbox_regisr(struct bfa_ioc *ioc, enum bfi_mclass mc,
8b230ed8 RM	257	bfa_ioc_mbox_mcfunc_t cbfn, void *cbarg);
8b230ed8 RM	258
1aa8b471	259	/* IOC interfaces */
8b230ed8 RM	260
	261	#define bfa_ioc_pll_init_asic(__ioc) \
	262	((__ioc)->ioc_hwif->ioc_pll_init((__ioc)->pcidev.pci_bar_kva, \
078086f3	263	(__ioc)->asic_mode))
8b230ed8	264
078086f3 RM	265	#define bfa_ioc_lpu_read_stat(__ioc) do { \
	266	if ((__ioc)->ioc_hwif->ioc_lpu_read_stat) \
	267	((__ioc)->ioc_hwif->ioc_lpu_read_stat(__ioc)); \
	268	} while (0)
	269
8a891429	270	void bfa_nw_ioc_set_ct_hwif(struct bfa_ioc *ioc);
be3a84d1	271	void bfa_nw_ioc_set_ct2_hwif(struct bfa_ioc *ioc);
70f14381	272	void bfa_nw_ioc_ct2_poweron(struct bfa_ioc *ioc);
8b230ed8	273
8a891429	274	void bfa_nw_ioc_attach(struct bfa_ioc ioc, void bfa,
8b230ed8	275	struct bfa_ioc_cbfn *cbfn);
8a891429 RM	276	void bfa_nw_ioc_auto_recover(bool auto_recover);
	277	void bfa_nw_ioc_detach(struct bfa_ioc *ioc);
	278	void bfa_nw_ioc_pci_init(struct bfa_ioc ioc, struct bfa_pcidev pcidev,
078086f3	279	enum bfi_pcifn_class clscode);
8a891429 RM	280	u32 bfa_nw_ioc_meminfo(void);
	281	void bfa_nw_ioc_mem_claim(struct bfa_ioc ioc, u8 dm_kva, u64 dm_pa);
	282	void bfa_nw_ioc_enable(struct bfa_ioc *ioc);
	283	void bfa_nw_ioc_disable(struct bfa_ioc *ioc);
	284
	285	void bfa_nw_ioc_error_isr(struct bfa_ioc *ioc);
bd5a92e9	286	bool bfa_nw_ioc_is_disabled(struct bfa_ioc *ioc);
7afc5dbd	287	bool bfa_nw_ioc_is_operational(struct bfa_ioc *ioc);
8a891429	288	void bfa_nw_ioc_get_attr(struct bfa_ioc ioc, struct bfa_ioc_attr ioc_attr);
c107ba17	289	enum bfa_status bfa_nw_ioc_fwsig_invalidate(struct bfa_ioc *ioc);
bd5a92e9 RM	290	void bfa_nw_ioc_notify_register(struct bfa_ioc *ioc,
bd5a92e9 RM	291	struct bfa_ioc_notify *notify);
8a891429 RM	292	bool bfa_nw_ioc_sem_get(void __iomem *sem_reg);
	293	void bfa_nw_ioc_sem_release(void __iomem *sem_reg);
	294	void bfa_nw_ioc_hw_sem_release(struct bfa_ioc *ioc);
	295	void bfa_nw_ioc_fwver_get(struct bfa_ioc *ioc,
8b230ed8	296	struct bfi_ioc_image_hdr *fwhdr);
8a891429	297	bool bfa_nw_ioc_fwver_cmp(struct bfa_ioc *ioc,
8b230ed8	298	struct bfi_ioc_image_hdr *fwhdr);
d6b30598	299	void bfa_nw_ioc_get_mac(struct bfa_ioc ioc, u8 mac);
7afc5dbd KG	300	void bfa_nw_ioc_debug_memclaim(struct bfa_ioc ioc, void dbg_fwsave);
	301	int bfa_nw_ioc_debug_fwtrc(struct bfa_ioc ioc, void trcdata, int *trclen);
	302	int bfa_nw_ioc_debug_fwsave(struct bfa_ioc ioc, void trcdata, int *trclen);
8b230ed8 RM	303
	304	/*
	305	* Timeout APIs
	306	*/
ad24d6f0 IV	307	void bfa_nw_ioc_timeout(struct bfa_ioc *ioc);
	308	void bfa_nw_ioc_hb_check(struct bfa_ioc *ioc);
	309	void bfa_nw_iocpf_timeout(struct bfa_ioc *ioc);
	310	void bfa_nw_iocpf_sem_timeout(struct bfa_ioc *ioc);
8b230ed8 RM	311
	312	/*
	313	* F/W Image Size & Chunk
	314	*/
078086f3 RM	315	u32 *bfa_cb_image_get_chunk(enum bfi_asic_gen asic_gen, u32 off);
078086f3 RM	316	u32 bfa_cb_image_get_size(enum bfi_asic_gen asic_gen);
8b230ed8	317
72a9730b KG	318	/*
	319	* Flash module specific
	320	*/
	321	typedef void (bfa_cb_flash) (void cbarg, enum bfa_status status);
	322
	323	struct bfa_flash {
	324	struct bfa_ioc ioc; / back pointer to ioc */
	325	u32 type; /* partition type */
	326	u8 instance; /* partition instance */
	327	u8 rsv[3];
	328	u32 op_busy; /* operation busy flag */
	329	u32 residue; /* residual length */
	330	u32 offset; /* offset */
	331	enum bfa_status status; /* status */
	332	u8 dbuf_kva; / dma buf virtual address */
	333	u64 dbuf_pa; /* dma buf physical address */
	334	bfa_cb_flash cbfn; /* user callback function */
	335	void cbarg; / user callback arg */
	336	u8 ubuf; / user supplied buffer */
	337	u32 addr_off; /* partition address offset */
	338	struct bfa_mbox_cmd mb; /* mailbox */
	339	struct bfa_ioc_notify ioc_notify; /* ioc event notify */
	340	};
	341
	342	enum bfa_status bfa_nw_flash_get_attr(struct bfa_flash *flash,
	343	struct bfa_flash_attr *attr,
	344	bfa_cb_flash cbfn, void *cbarg);
	345	enum bfa_status bfa_nw_flash_update_part(struct bfa_flash *flash,
	346	u32 type, u8 instance, void *buf, u32 len, u32 offset,
	347	bfa_cb_flash cbfn, void *cbarg);
	348	enum bfa_status bfa_nw_flash_read_part(struct bfa_flash *flash,
	349	u32 type, u8 instance, void *buf, u32 len, u32 offset,
	350	bfa_cb_flash cbfn, void *cbarg);
	351	u32 bfa_nw_flash_meminfo(void);
	352	void bfa_nw_flash_attach(struct bfa_flash *flash,
	353	struct bfa_ioc ioc, void dev);
	354	void bfa_nw_flash_memclaim(struct bfa_flash flash, u8 dm_kva, u64 dm_pa);
	355
8b230ed8	356	#endif /* __BFA_IOC_H__ */