[deliverable/linux.git] / drivers / net / ethernet / brocade / bna / bfi.h

/*
 * Linux network driver for QLogic BR-series Converged Network Adapter.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License (GPL) Version 2 as
 * published by the Free Software Foundation
 *
 * This program is distributed in the hope that it will be useful, but
 * WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * General Public License for more details.
 */
/*
 * Copyright (c) 2005-2014 Brocade Communications Systems, Inc.
 * Copyright (c) 2014-2015 QLogic Corporation
 * All rights reserved
 * www.qlogic.com
 */
#ifndef __BFI_H__
#define __BFI_H__

#include "bfa_defs.h"

#pragma pack(1)

/* BFI FW image type */
#define	BFI_FLASH_CHUNK_SZ			256	/*!< Flash chunk size */
#define	BFI_FLASH_CHUNK_SZ_WORDS	(BFI_FLASH_CHUNK_SZ/sizeof(u32))
#define BFI_FLASH_IMAGE_SZ		0x100000

/* Msg header common to all msgs */
struct bfi_mhdr {
	u8		msg_class;	/*!< @ref enum bfi_mclass	    */
	u8		msg_id;		/*!< msg opcode with in the class   */
	union {
		struct {
			u8	qid;
			u8	fn_lpu;	/*!< msg destination		    */
		} h2i;
		u16	i2htok;	/*!< token in msgs to host	    */
	} mtag;
};

#define bfi_fn_lpu(__fn, __lpu)	((__fn) << 1 | (__lpu))
#define bfi_mhdr_2_fn(_mh)	((_mh)->mtag.h2i.fn_lpu >> 1)
#define bfi_mhdr_2_qid(_mh)	((_mh)->mtag.h2i.qid)

#define bfi_h2i_set(_mh, _mc, _op, _fn_lpu) do {		\
	(_mh).msg_class			= (_mc);		\
	(_mh).msg_id			= (_op);		\
	(_mh).mtag.h2i.fn_lpu	= (_fn_lpu);			\
} while (0)

#define bfi_i2h_set(_mh, _mc, _op, _i2htok) do {		\
	(_mh).msg_class			= (_mc);		\
	(_mh).msg_id			= (_op);		\
	(_mh).mtag.i2htok		= (_i2htok);		\
} while (0)

/*
 * Message opcodes: 0-127 to firmware, 128-255 to host
 */
#define BFI_I2H_OPCODE_BASE	128
#define BFA_I2HM(_x)			((_x) + BFI_I2H_OPCODE_BASE)

/****************************************************************************
 *
 * Scatter Gather Element and Page definition
 *
 ****************************************************************************
 */

/* DMA addresses */
union bfi_addr_u {
	struct {
		u32	addr_lo;
		u32	addr_hi;
	} a32;
};

/* Generic DMA addr-len pair. */
struct bfi_alen {
	union bfi_addr_u	al_addr;	/* DMA addr of buffer	*/
	u32			al_len;		/* length of buffer */
};

/*
 * Large Message structure - 128 Bytes size Msgs
 */
#define BFI_LMSG_SZ		128
#define BFI_LMSG_PL_WSZ	\
			((BFI_LMSG_SZ - sizeof(struct bfi_mhdr)) / 4)

/* Mailbox message structure */
#define BFI_MBMSG_SZ		7
struct bfi_mbmsg {
	struct bfi_mhdr mh;
	u32		pl[BFI_MBMSG_SZ];
};

/* Supported PCI function class codes (personality) */
enum bfi_pcifn_class {
	BFI_PCIFN_CLASS_FC	= 0x0c04,
	BFI_PCIFN_CLASS_ETH	= 0x0200,
};

/* Message Classes */
enum bfi_mclass {
	BFI_MC_IOC		= 1,	/*!< IO Controller (IOC)	    */
	BFI_MC_DIAG		= 2,	/*!< Diagnostic Msgs		    */
	BFI_MC_FLASH		= 3,	/*!< Flash message class	    */
	BFI_MC_CEE		= 4,	/*!< CEE			    */
	BFI_MC_FCPORT		= 5,	/*!< FC port			    */
	BFI_MC_IOCFC		= 6,	/*!< FC - IO Controller (IOC)	    */
	BFI_MC_LL		= 7,	/*!< Link Layer			    */
	BFI_MC_UF		= 8,	/*!< Unsolicited frame receive	    */
	BFI_MC_FCXP		= 9,	/*!< FC Transport		    */
	BFI_MC_LPS		= 10,	/*!< lport fc login services	    */
	BFI_MC_RPORT		= 11,	/*!< Remote port		    */
	BFI_MC_ITNIM		= 12,	/*!< I-T nexus (Initiator mode)	    */
	BFI_MC_IOIM_READ	= 13,	/*!< read IO (Initiator mode)	    */
	BFI_MC_IOIM_WRITE	= 14,	/*!< write IO (Initiator mode)	    */
	BFI_MC_IOIM_IO		= 15,	/*!< IO (Initiator mode)	    */
	BFI_MC_IOIM		= 16,	/*!< IO (Initiator mode)	    */
	BFI_MC_IOIM_IOCOM	= 17,	/*!< good IO completion		    */
	BFI_MC_TSKIM		= 18,	/*!< Initiator Task management	    */
	BFI_MC_SBOOT		= 19,	/*!< SAN boot services		    */
	BFI_MC_IPFC		= 20,	/*!< IP over FC Msgs		    */
	BFI_MC_PORT		= 21,	/*!< Physical port		    */
	BFI_MC_SFP		= 22,	/*!< SFP module			    */
	BFI_MC_MSGQ		= 23,	/*!< MSGQ			    */
	BFI_MC_ENET		= 24,	/*!< ENET commands/responses	    */
	BFI_MC_PHY		= 25,	/*!< External PHY message class	    */
	BFI_MC_NBOOT		= 26,	/*!< Network Boot		    */
	BFI_MC_TIO_READ		= 27,	/*!< read IO (Target mode)	    */
	BFI_MC_TIO_WRITE	= 28,	/*!< write IO (Target mode)	    */
	BFI_MC_TIO_DATA_XFERED	= 29,	/*!< ds transferred (target mode)   */
	BFI_MC_TIO_IO		= 30,	/*!< IO (Target mode)		    */
	BFI_MC_TIO		= 31,	/*!< IO (target mode)		    */
	BFI_MC_MFG		= 32,	/*!< MFG/ASIC block commands	    */
	BFI_MC_EDMA		= 33,	/*!< EDMA copy commands		    */
	BFI_MC_MAX		= 34
};

#define BFI_IOC_MSGLEN_MAX	32	/* 32 bytes */

#define BFI_FWBOOT_ENV_OS		0

/*----------------------------------------------------------------------
 *				IOC
 *----------------------------------------------------------------------
 */

/* Different asic generations */
enum bfi_asic_gen {
	BFI_ASIC_GEN_CB		= 1,
	BFI_ASIC_GEN_CT		= 2,
	BFI_ASIC_GEN_CT2	= 3,
};

enum bfi_asic_mode {
	BFI_ASIC_MODE_FC	= 1,	/* FC up to 8G speed		*/
	BFI_ASIC_MODE_FC16	= 2,	/* FC up to 16G speed		*/
	BFI_ASIC_MODE_ETH	= 3,	/* Ethernet ports		*/
	BFI_ASIC_MODE_COMBO	= 4,	/* FC 16G and Ethernet 10G port	*/
};

enum bfi_ioc_h2i_msgs {
	BFI_IOC_H2I_ENABLE_REQ		= 1,
	BFI_IOC_H2I_DISABLE_REQ		= 2,
	BFI_IOC_H2I_GETATTR_REQ		= 3,
	BFI_IOC_H2I_DBG_SYNC		= 4,
	BFI_IOC_H2I_DBG_DUMP		= 5,
};

enum bfi_ioc_i2h_msgs {
	BFI_IOC_I2H_ENABLE_REPLY	= BFA_I2HM(1),
	BFI_IOC_I2H_DISABLE_REPLY	= BFA_I2HM(2),
	BFI_IOC_I2H_GETATTR_REPLY	= BFA_I2HM(3),
	BFI_IOC_I2H_HBEAT		= BFA_I2HM(4),
};

/* BFI_IOC_H2I_GETATTR_REQ message */
struct bfi_ioc_getattr_req {
	struct bfi_mhdr mh;
	union bfi_addr_u	attr_addr;
};

struct bfi_ioc_attr {
	u64		mfg_pwwn;	/*!< Mfg port wwn	   */
	u64		mfg_nwwn;	/*!< Mfg node wwn	   */
	mac_t		mfg_mac;	/*!< Mfg mac		   */
	u8		port_mode;	/* enum bfi_port_mode	   */
	u8		rsvd_a;
	u64		pwwn;
	u64		nwwn;
	mac_t		mac;		/*!< PBC or Mfg mac	   */
	u16	rsvd_b;
	mac_t		fcoe_mac;
	u16	rsvd_c;
	char		brcd_serialnum[STRSZ(BFA_MFG_SERIALNUM_SIZE)];
	u8		pcie_gen;
	u8		pcie_lanes_orig;
	u8		pcie_lanes;
	u8		rx_bbcredit;	/*!< receive buffer credits */
	u32	adapter_prop;	/*!< adapter properties     */
	u16	maxfrsize;	/*!< max receive frame size */
	char		asic_rev;
	u8		rsvd_d;
	char		fw_version[BFA_VERSION_LEN];
	char		optrom_version[BFA_VERSION_LEN];
	struct bfa_mfg_vpd vpd;
	u32	card_type;	/*!< card type			*/
};

/* BFI_IOC_I2H_GETATTR_REPLY message */
struct bfi_ioc_getattr_reply {
	struct bfi_mhdr mh;	/*!< Common msg header		*/
	u8			status;	/*!< cfg reply status		*/
	u8			rsvd[3];
};

/* Firmware memory page offsets */
#define BFI_IOC_SMEM_PG0_CB	(0x40)
#define BFI_IOC_SMEM_PG0_CT	(0x180)

/* Firmware statistic offset */
#define BFI_IOC_FWSTATS_OFF	(0x6B40)
#define BFI_IOC_FWSTATS_SZ	(4096)

/* Firmware trace offset */
#define BFI_IOC_TRC_OFF		(0x4b00)
#define BFI_IOC_TRC_ENTS	256
#define BFI_IOC_TRC_ENT_SZ	16
#define BFI_IOC_TRC_HDR_SZ	32

#define BFI_IOC_FW_SIGNATURE	(0xbfadbfad)
#define BFI_IOC_FW_INV_SIGN	(0xdeaddead)
#define BFI_IOC_MD5SUM_SZ	4

struct bfi_ioc_fwver {
#ifdef __BIG_ENDIAN
	u8 patch;
	u8 maint;
	u8 minor;
	u8 major;
	u8 rsvd[2];
	u8 build;
	u8 phase;
#else
	u8 major;
	u8 minor;
	u8 maint;
	u8 patch;
	u8 phase;
	u8 build;
	u8 rsvd[2];
#endif
};

struct bfi_ioc_image_hdr {
	u32	signature;	/*!< constant signature */
	u8	asic_gen;	/*!< asic generation */
	u8	asic_mode;
	u8	port0_mode;	/*!< device mode for port 0 */
	u8	port1_mode;	/*!< device mode for port 1 */
	u32	exec;		/*!< exec vector	*/
	u32	bootenv;	/*!< firmware boot env */
	u32	rsvd_b[2];
	struct bfi_ioc_fwver fwver;
	u32	md5sum[BFI_IOC_MD5SUM_SZ];
};

enum bfi_ioc_img_ver_cmp {
	BFI_IOC_IMG_VER_INCOMP,
	BFI_IOC_IMG_VER_OLD,
	BFI_IOC_IMG_VER_SAME,
	BFI_IOC_IMG_VER_BETTER
};

#define BFI_FWBOOT_DEVMODE_OFF		4
#define BFI_FWBOOT_TYPE_OFF		8
#define BFI_FWBOOT_ENV_OFF		12
#define BFI_FWBOOT_DEVMODE(__asic_gen, __asic_mode, __p0_mode, __p1_mode) \
	(((u32)(__asic_gen)) << 24 |	\
	 ((u32)(__asic_mode)) << 16 |	\
	 ((u32)(__p0_mode)) << 8 |	\
	 ((u32)(__p1_mode)))

enum bfi_fwboot_type {
	BFI_FWBOOT_TYPE_NORMAL	= 0,
	BFI_FWBOOT_TYPE_FLASH	= 1,
	BFI_FWBOOT_TYPE_MEMTEST	= 2,
};

enum bfi_port_mode {
	BFI_PORT_MODE_FC	= 1,
	BFI_PORT_MODE_ETH	= 2,
};

struct bfi_ioc_hbeat {
	struct bfi_mhdr mh;		/*!< common msg header		*/
	u32	   hb_count;	/*!< current heart beat count	*/
};

/* IOC hardware/firmware state */
enum bfi_ioc_state {
	BFI_IOC_UNINIT		= 0,	/*!< not initialized		     */
	BFI_IOC_INITING		= 1,	/*!< h/w is being initialized	     */
	BFI_IOC_HWINIT		= 2,	/*!< h/w is initialized		     */
	BFI_IOC_CFG		= 3,	/*!< IOC configuration in progress   */
	BFI_IOC_OP		= 4,	/*!< IOC is operational		     */
	BFI_IOC_DISABLING	= 5,	/*!< IOC is being disabled	     */
	BFI_IOC_DISABLED	= 6,	/*!< IOC is disabled		     */
	BFI_IOC_CFG_DISABLED	= 7,	/*!< IOC is being disabled;transient */
	BFI_IOC_FAIL		= 8,	/*!< IOC heart-beat failure	     */
	BFI_IOC_MEMTEST		= 9,	/*!< IOC is doing memtest	     */
};

#define BFI_IOC_ENDIAN_SIG  0x12345678

enum {
	BFI_ADAPTER_TYPE_FC	= 0x01,		/*!< FC adapters	   */
	BFI_ADAPTER_TYPE_MK	= 0x0f0000,	/*!< adapter type mask     */
	BFI_ADAPTER_TYPE_SH	= 16,	        /*!< adapter type shift    */
	BFI_ADAPTER_NPORTS_MK	= 0xff00,	/*!< number of ports mask  */
	BFI_ADAPTER_NPORTS_SH	= 8,	        /*!< number of ports shift */
	BFI_ADAPTER_SPEED_MK	= 0xff,		/*!< adapter speed mask    */
	BFI_ADAPTER_SPEED_SH	= 0,	        /*!< adapter speed shift   */
	BFI_ADAPTER_PROTO	= 0x100000,	/*!< prototype adapaters   */
	BFI_ADAPTER_TTV		= 0x200000,	/*!< TTV debug capable     */
	BFI_ADAPTER_UNSUPP	= 0x400000,	/*!< unknown adapter type  */
};

#define BFI_ADAPTER_GETP(__prop, __adap_prop)			\
	(((__adap_prop) & BFI_ADAPTER_ ## __prop ## _MK) >>	\
		BFI_ADAPTER_ ## __prop ## _SH)
#define BFI_ADAPTER_SETP(__prop, __val)				\
	((__val) << BFI_ADAPTER_ ## __prop ## _SH)
#define BFI_ADAPTER_IS_PROTO(__adap_type)			\
	((__adap_type) & BFI_ADAPTER_PROTO)
#define BFI_ADAPTER_IS_TTV(__adap_type)				\
	((__adap_type) & BFI_ADAPTER_TTV)
#define BFI_ADAPTER_IS_UNSUPP(__adap_type)			\
	((__adap_type) & BFI_ADAPTER_UNSUPP)
#define BFI_ADAPTER_IS_SPECIAL(__adap_type)			\
	((__adap_type) & (BFI_ADAPTER_TTV | BFI_ADAPTER_PROTO |	\
			BFI_ADAPTER_UNSUPP))

/* BFI_IOC_H2I_ENABLE_REQ & BFI_IOC_H2I_DISABLE_REQ messages */
struct bfi_ioc_ctrl_req {
	struct bfi_mhdr mh;
	u16			clscode;
	u16			rsvd;
	u32		tv_sec;
};

/* BFI_IOC_I2H_ENABLE_REPLY & BFI_IOC_I2H_DISABLE_REPLY messages */
struct bfi_ioc_ctrl_reply {
	struct bfi_mhdr mh;			/*!< Common msg header     */
	u8			status;		/*!< enable/disable status */
	u8			port_mode;	/*!< enum bfa_mode */
	u8			cap_bm;		/*!< capability bit mask */
	u8			rsvd;
};

#define BFI_IOC_MSGSZ   8
/* H2I Messages */
union bfi_ioc_h2i_msg_u {
	struct bfi_mhdr mh;
	struct bfi_ioc_ctrl_req enable_req;
	struct bfi_ioc_ctrl_req disable_req;
	struct bfi_ioc_getattr_req getattr_req;
	u32			mboxmsg[BFI_IOC_MSGSZ];
};

/* I2H Messages */
union bfi_ioc_i2h_msg_u {
	struct bfi_mhdr mh;
	struct bfi_ioc_ctrl_reply fw_event;
	u32			mboxmsg[BFI_IOC_MSGSZ];
};

/*----------------------------------------------------------------------
 *				MSGQ
 *----------------------------------------------------------------------
 */

enum bfi_msgq_h2i_msgs {
	BFI_MSGQ_H2I_INIT_REQ	   = 1,
	BFI_MSGQ_H2I_DOORBELL_PI	= 2,
	BFI_MSGQ_H2I_DOORBELL_CI	= 3,
	BFI_MSGQ_H2I_CMDQ_COPY_RSP      = 4,
};

enum bfi_msgq_i2h_msgs {
	BFI_MSGQ_I2H_INIT_RSP	   = BFA_I2HM(BFI_MSGQ_H2I_INIT_REQ),
	BFI_MSGQ_I2H_DOORBELL_PI	= BFA_I2HM(BFI_MSGQ_H2I_DOORBELL_PI),
	BFI_MSGQ_I2H_DOORBELL_CI	= BFA_I2HM(BFI_MSGQ_H2I_DOORBELL_CI),
	BFI_MSGQ_I2H_CMDQ_COPY_REQ      = BFA_I2HM(BFI_MSGQ_H2I_CMDQ_COPY_RSP),
};

/* Messages(commands/responsed/AENS will have the following header */
struct bfi_msgq_mhdr {
	u8	msg_class;
	u8	msg_id;
	u16	msg_token;
	u16	num_entries;
	u8	enet_id;
	u8	rsvd[1];
};

#define bfi_msgq_mhdr_set(_mh, _mc, _mid, _tok, _enet_id) do {	\
	(_mh).msg_class	 = (_mc);	\
	(_mh).msg_id	    = (_mid);       \
	(_mh).msg_token	 = (_tok);       \
	(_mh).enet_id	   = (_enet_id);   \
} while (0)

/*
 * Mailbox  for messaging interface
 */
#define BFI_MSGQ_CMD_ENTRY_SIZE	 (64)    /* TBD */
#define BFI_MSGQ_RSP_ENTRY_SIZE	 (64)    /* TBD */

#define bfi_msgq_num_cmd_entries(_size)				 \
	(((_size) + BFI_MSGQ_CMD_ENTRY_SIZE - 1) / BFI_MSGQ_CMD_ENTRY_SIZE)

struct bfi_msgq {
	union bfi_addr_u addr;
	u16 q_depth;     /* Total num of entries in the queue */
	u8 rsvd[2];
};

/* BFI_ENET_MSGQ_CFG_REQ TBD init or cfg? */
struct bfi_msgq_cfg_req {
	struct bfi_mhdr mh;
	struct bfi_msgq cmdq;
	struct bfi_msgq rspq;
};

/* BFI_ENET_MSGQ_CFG_RSP */
struct bfi_msgq_cfg_rsp {
	struct bfi_mhdr mh;
	u8 cmd_status;
	u8 rsvd[3];
};

/* BFI_MSGQ_H2I_DOORBELL */
struct bfi_msgq_h2i_db {
	struct bfi_mhdr mh;
	union {
		u16 cmdq_pi;
		u16 rspq_ci;
	} idx;
};

/* BFI_MSGQ_I2H_DOORBELL */
struct bfi_msgq_i2h_db {
	struct bfi_mhdr mh;
	union {
		u16 rspq_pi;
		u16 cmdq_ci;
	} idx;
};

#define BFI_CMD_COPY_SZ 28

/* BFI_MSGQ_H2I_CMD_COPY_RSP */
struct bfi_msgq_h2i_cmdq_copy_rsp {
	struct bfi_mhdr mh;
	u8	      data[BFI_CMD_COPY_SZ];
};

/* BFI_MSGQ_I2H_CMD_COPY_REQ */
struct bfi_msgq_i2h_cmdq_copy_req {
	struct bfi_mhdr mh;
	u16     offset;
	u16     len;
};

/*
 *      FLASH module specific
 */
enum bfi_flash_h2i_msgs {
	BFI_FLASH_H2I_QUERY_REQ = 1,
	BFI_FLASH_H2I_ERASE_REQ = 2,
	BFI_FLASH_H2I_WRITE_REQ = 3,
	BFI_FLASH_H2I_READ_REQ = 4,
	BFI_FLASH_H2I_BOOT_VER_REQ = 5,
};

enum bfi_flash_i2h_msgs {
	BFI_FLASH_I2H_QUERY_RSP = BFA_I2HM(1),
	BFI_FLASH_I2H_ERASE_RSP = BFA_I2HM(2),
	BFI_FLASH_I2H_WRITE_RSP = BFA_I2HM(3),
	BFI_FLASH_I2H_READ_RSP = BFA_I2HM(4),
	BFI_FLASH_I2H_BOOT_VER_RSP = BFA_I2HM(5),
	BFI_FLASH_I2H_EVENT = BFA_I2HM(127),
};

/*
 * Flash query request
 */
struct bfi_flash_query_req {
	struct bfi_mhdr mh;   /* Common msg header */
	struct bfi_alen alen;
};

/*
 * Flash write request
 */
struct bfi_flash_write_req {
	struct bfi_mhdr mh;	/* Common msg header */
	struct bfi_alen alen;
	u32	type;   /* partition type */
	u8	instance; /* partition instance */
	u8	last;
	u8	rsv[2];
	u32	offset;
	u32	length;
};

/*
 * Flash read request
 */
struct bfi_flash_read_req {
	struct bfi_mhdr mh;	/* Common msg header */
	u32	type;		/* partition type */
	u8	instance;	/* partition instance */
	u8	rsv[3];
	u32	offset;
	u32	length;
	struct bfi_alen alen;
};

/*
 * Flash query response
 */
struct bfi_flash_query_rsp {
	struct bfi_mhdr mh;	/* Common msg header */
	u32	status;
};

/*
 * Flash read response
 */
struct bfi_flash_read_rsp {
	struct bfi_mhdr mh;	/* Common msg header */
	u32	type;		/* partition type */
	u8	instance;	/* partition instance */
	u8	rsv[3];
	u32	status;
	u32	length;
};

/*
 * Flash write response
 */
struct bfi_flash_write_rsp {
	struct bfi_mhdr mh;	/* Common msg header */
	u32	type;		/* partition type */
	u8	instance;	/* partition instance */
	u8	rsv[3];
	u32	status;
	u32	length;
};

#pragma pack()

#endif /* __BFI_H__ */
Commit	Line	Data
8b230ed8	1	/*
2732ba56	2	* Linux network driver for QLogic BR-series Converged Network Adapter.
8b230ed8 RM	3	*
	4	* This program is free software; you can redistribute it and/or modify it
	5	* under the terms of the GNU General Public License (GPL) Version 2 as
	6	* published by the Free Software Foundation
	7	*
	8	* This program is distributed in the hope that it will be useful, but
	9	* WITHOUT ANY WARRANTY; without even the implied warranty of
	10	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	11	* General Public License for more details.
	12	*/
	13	/*
2732ba56 RM	14	* Copyright (c) 2005-2014 Brocade Communications Systems, Inc.
2732ba56 RM	15	* Copyright (c) 2014-2015 QLogic Corporation
8b230ed8	16	* All rights reserved
2732ba56	17	* www.qlogic.com
8b230ed8	18	*/
8b230ed8 RM	19	#ifndef __BFI_H__
	20	#define __BFI_H__
	21
	22	#include "bfa_defs.h"
	23
	24	#pragma pack(1)
	25
1aa8b471	26	/* BFI FW image type */
8b230ed8 RM	27	#define BFI_FLASH_CHUNK_SZ 256 /!< Flash chunk size /
8b230ed8 RM	28	#define BFI_FLASH_CHUNK_SZ_WORDS (BFI_FLASH_CHUNK_SZ/sizeof(u32))
c107ba17	29	#define BFI_FLASH_IMAGE_SZ 0x100000
8b230ed8	30
1aa8b471	31	/* Msg header common to all msgs */
8b230ed8 RM	32	struct bfi_mhdr {
	33	u8 msg_class; /!< @ref enum bfi_mclass /
	34	u8 msg_id; /!< msg opcode with in the class /
	35	union {
	36	struct {
078086f3 RM	37	u8 qid;
078086f3 RM	38	u8 fn_lpu; /!< msg destination /
8b230ed8 RM	39	} h2i;
	40	u16 i2htok; /!< token in msgs to host /
	41	} mtag;
	42	};
	43
078086f3 RM	44	#define bfi_fn_lpu(__fn, __lpu) ((__fn) << 1 \| (__lpu))
	45	#define bfi_mhdr_2_fn(_mh) ((_mh)->mtag.h2i.fn_lpu >> 1)
	46	#define bfi_mhdr_2_qid(_mh) ((_mh)->mtag.h2i.qid)
	47
	48	#define bfi_h2i_set(_mh, _mc, _op, _fn_lpu) do { \
0120b99c	49	(_mh).msg_class = (_mc); \
8b230ed8	50	(_mh).msg_id = (_op); \
078086f3	51	(_mh).mtag.h2i.fn_lpu = (_fn_lpu); \
8b230ed8 RM	52	} while (0)
	53
	54	#define bfi_i2h_set(_mh, _mc, _op, _i2htok) do { \
0120b99c	55	(_mh).msg_class = (_mc); \
8b230ed8 RM	56	(_mh).msg_id = (_op); \
	57	(_mh).mtag.i2htok = (_i2htok); \
	58	} while (0)
	59
	60	/*
	61	* Message opcodes: 0-127 to firmware, 128-255 to host
	62	*/
	63	#define BFI_I2H_OPCODE_BASE 128
0120b99c	64	#define BFA_I2HM(_x) ((_x) + BFI_I2H_OPCODE_BASE)
8b230ed8	65
1aa8b471	66	/****************************************************************************
8b230ed8 RM	67	*
	68	* Scatter Gather Element and Page definition
	69	*
	70	****************************************************************************
	71	*/
	72
1aa8b471	73	/* DMA addresses */
8b230ed8 RM	74	union bfi_addr_u {
	75	struct {
	76	u32 addr_lo;
	77	u32 addr_hi;
	78	} a32;
	79	};
	80
1aa8b471	81	/* Generic DMA addr-len pair. */
72a9730b KG	82	struct bfi_alen {
	83	union bfi_addr_u al_addr; /* DMA addr of buffer */
	84	u32 al_len; /* length of buffer */
	85	};
	86
8b230ed8 RM	87	/*
	88	* Large Message structure - 128 Bytes size Msgs
	89	*/
	90	#define BFI_LMSG_SZ 128
	91	#define BFI_LMSG_PL_WSZ \
	92	((BFI_LMSG_SZ - sizeof(struct bfi_mhdr)) / 4)
	93
1aa8b471	94	/* Mailbox message structure */
8b230ed8 RM	95	#define BFI_MBMSG_SZ 7
	96	struct bfi_mbmsg {
	97	struct bfi_mhdr mh;
	98	u32 pl[BFI_MBMSG_SZ];
	99	};
	100
1aa8b471	101	/* Supported PCI function class codes (personality) */
078086f3 RM	102	enum bfi_pcifn_class {
	103	BFI_PCIFN_CLASS_FC = 0x0c04,
	104	BFI_PCIFN_CLASS_ETH = 0x0200,
	105	};
	106
1aa8b471	107	/* Message Classes */
8b230ed8 RM	108	enum bfi_mclass {
	109	BFI_MC_IOC = 1, /!< IO Controller (IOC) /
	110	BFI_MC_DIAG = 2, /!< Diagnostic Msgs /
	111	BFI_MC_FLASH = 3, /!< Flash message class /
	112	BFI_MC_CEE = 4, /!< CEE /
	113	BFI_MC_FCPORT = 5, /!< FC port /
	114	BFI_MC_IOCFC = 6, /!< FC - IO Controller (IOC) /
	115	BFI_MC_LL = 7, /!< Link Layer /
	116	BFI_MC_UF = 8, /!< Unsolicited frame receive /
	117	BFI_MC_FCXP = 9, /!< FC Transport /
	118	BFI_MC_LPS = 10, /!< lport fc login services /
	119	BFI_MC_RPORT = 11, /!< Remote port /
	120	BFI_MC_ITNIM = 12, /!< I-T nexus (Initiator mode) /
	121	BFI_MC_IOIM_READ = 13, /!< read IO (Initiator mode) /
	122	BFI_MC_IOIM_WRITE = 14, /!< write IO (Initiator mode) /
	123	BFI_MC_IOIM_IO = 15, /!< IO (Initiator mode) /
	124	BFI_MC_IOIM = 16, /!< IO (Initiator mode) /
	125	BFI_MC_IOIM_IOCOM = 17, /!< good IO completion /
	126	BFI_MC_TSKIM = 18, /!< Initiator Task management /
	127	BFI_MC_SBOOT = 19, /!< SAN boot services /
	128	BFI_MC_IPFC = 20, /!< IP over FC Msgs /
	129	BFI_MC_PORT = 21, /!< Physical port /
	130	BFI_MC_SFP = 22, /!< SFP module /
	131	BFI_MC_MSGQ = 23, /!< MSGQ /
	132	BFI_MC_ENET = 24, /!< ENET commands/responses /
aafd5c2c RM	133	BFI_MC_PHY = 25, /!< External PHY message class /
	134	BFI_MC_NBOOT = 26, /!< Network Boot /
	135	BFI_MC_TIO_READ = 27, /!< read IO (Target mode) /
	136	BFI_MC_TIO_WRITE = 28, /!< write IO (Target mode) /
	137	BFI_MC_TIO_DATA_XFERED = 29, /!< ds transferred (target mode) /
	138	BFI_MC_TIO_IO = 30, /!< IO (Target mode) /
	139	BFI_MC_TIO = 31, /!< IO (target mode) /
	140	BFI_MC_MFG = 32, /!< MFG/ASIC block commands /
	141	BFI_MC_EDMA = 33, /!< EDMA copy commands /
	142	BFI_MC_MAX = 34
8b230ed8 RM	143	};
8b230ed8 RM	144
8b230ed8 RM	145	#define BFI_IOC_MSGLEN_MAX 32 /* 32 bytes */
8b230ed8 RM	146
af027a34 RM	147	#define BFI_FWBOOT_ENV_OS 0
af027a34 RM	148
1aa8b471	149	/*----------------------------------------------------------------------
8b230ed8 RM	150	* IOC
	151	*----------------------------------------------------------------------
	152	*/
	153
1aa8b471	154	/* Different asic generations */
078086f3 RM	155	enum bfi_asic_gen {
	156	BFI_ASIC_GEN_CB = 1,
	157	BFI_ASIC_GEN_CT = 2,
1bf9fd70	158	BFI_ASIC_GEN_CT2 = 3,
078086f3 RM	159	};
	160
	161	enum bfi_asic_mode {
dbedd44e JP	162	BFI_ASIC_MODE_FC = 1, /* FC up to 8G speed */
dbedd44e JP	163	BFI_ASIC_MODE_FC16 = 2, /* FC up to 16G speed */
078086f3 RM	164	BFI_ASIC_MODE_ETH = 3, /* Ethernet ports */
	165	BFI_ASIC_MODE_COMBO = 4, /* FC 16G and Ethernet 10G port */
	166	};
	167
8b230ed8 RM	168	enum bfi_ioc_h2i_msgs {
	169	BFI_IOC_H2I_ENABLE_REQ = 1,
	170	BFI_IOC_H2I_DISABLE_REQ = 2,
	171	BFI_IOC_H2I_GETATTR_REQ = 3,
	172	BFI_IOC_H2I_DBG_SYNC = 4,
	173	BFI_IOC_H2I_DBG_DUMP = 5,
	174	};
	175
	176	enum bfi_ioc_i2h_msgs {
	177	BFI_IOC_I2H_ENABLE_REPLY = BFA_I2HM(1),
0120b99c RM	178	BFI_IOC_I2H_DISABLE_REPLY = BFA_I2HM(2),
0120b99c RM	179	BFI_IOC_I2H_GETATTR_REPLY = BFA_I2HM(3),
078086f3	180	BFI_IOC_I2H_HBEAT = BFA_I2HM(4),
8b230ed8 RM	181	};
8b230ed8 RM	182
1aa8b471	183	/* BFI_IOC_H2I_GETATTR_REQ message */
8b230ed8 RM	184	struct bfi_ioc_getattr_req {
	185	struct bfi_mhdr mh;
	186	union bfi_addr_u attr_addr;
	187	};
	188
	189	struct bfi_ioc_attr {
	190	u64 mfg_pwwn; /!< Mfg port wwn /
	191	u64 mfg_nwwn; /!< Mfg node wwn /
	192	mac_t mfg_mac; /!< Mfg mac /
078086f3 RM	193	u8 port_mode; /* enum bfi_port_mode */
078086f3 RM	194	u8 rsvd_a;
8b230ed8 RM	195	u64 pwwn;
	196	u64 nwwn;
	197	mac_t mac; /!< PBC or Mfg mac /
	198	u16 rsvd_b;
	199	mac_t fcoe_mac;
	200	u16 rsvd_c;
	201	char brcd_serialnum[STRSZ(BFA_MFG_SERIALNUM_SIZE)];
	202	u8 pcie_gen;
	203	u8 pcie_lanes_orig;
	204	u8 pcie_lanes;
	205	u8 rx_bbcredit; /!< receive buffer credits /
	206	u32 adapter_prop; /!< adapter properties /
	207	u16 maxfrsize; /!< max receive frame size /
	208	char asic_rev;
	209	u8 rsvd_d;
	210	char fw_version[BFA_VERSION_LEN];
	211	char optrom_version[BFA_VERSION_LEN];
	212	struct bfa_mfg_vpd vpd;
	213	u32 card_type; /!< card type /
	214	};
	215
1aa8b471	216	/* BFI_IOC_I2H_GETATTR_REPLY message */
8b230ed8 RM	217	struct bfi_ioc_getattr_reply {
	218	struct bfi_mhdr mh; /!< Common msg header /
	219	u8 status; /!< cfg reply status /
	220	u8 rsvd[3];
	221	};
	222
1aa8b471	223	/* Firmware memory page offsets */
8b230ed8 RM	224	#define BFI_IOC_SMEM_PG0_CB (0x40)
	225	#define BFI_IOC_SMEM_PG0_CT (0x180)
	226
1aa8b471	227	/* Firmware statistic offset */
8b230ed8 RM	228	#define BFI_IOC_FWSTATS_OFF (0x6B40)
	229	#define BFI_IOC_FWSTATS_SZ (4096)
	230
1aa8b471	231	/* Firmware trace offset */
8b230ed8 RM	232	#define BFI_IOC_TRC_OFF (0x4b00)
8b230ed8 RM	233	#define BFI_IOC_TRC_ENTS 256
7afc5dbd KG	234	#define BFI_IOC_TRC_ENT_SZ 16
7afc5dbd KG	235	#define BFI_IOC_TRC_HDR_SZ 32
8b230ed8 RM	236
8b230ed8 RM	237	#define BFI_IOC_FW_SIGNATURE (0xbfadbfad)
c107ba17	238	#define BFI_IOC_FW_INV_SIGN (0xdeaddead)
8b230ed8	239	#define BFI_IOC_MD5SUM_SZ 4
c107ba17 RM	240
	241	struct bfi_ioc_fwver {
	242	#ifdef __BIG_ENDIAN
	243	u8 patch;
	244	u8 maint;
	245	u8 minor;
	246	u8 major;
	247	u8 rsvd[2];
	248	u8 build;
	249	u8 phase;
	250	#else
	251	u8 major;
	252	u8 minor;
	253	u8 maint;
	254	u8 patch;
	255	u8 phase;
	256	u8 build;
	257	u8 rsvd[2];
	258	#endif
	259	};
	260
8b230ed8 RM	261	struct bfi_ioc_image_hdr {
8b230ed8 RM	262	u32 signature; /!< constant signature /
078086f3 RM	263	u8 asic_gen; /!< asic generation /
	264	u8 asic_mode;
	265	u8 port0_mode; /!< device mode for port 0 /
	266	u8 port1_mode; /!< device mode for port 1 /
8b230ed8	267	u32 exec; /!< exec vector /
078086f3	268	u32 bootenv; /!< firmware boot env /
c107ba17 RM	269	u32 rsvd_b[2];
c107ba17 RM	270	struct bfi_ioc_fwver fwver;
8b230ed8 RM	271	u32 md5sum[BFI_IOC_MD5SUM_SZ];
	272	};
	273
c107ba17 RM	274	enum bfi_ioc_img_ver_cmp {
	275	BFI_IOC_IMG_VER_INCOMP,
	276	BFI_IOC_IMG_VER_OLD,
	277	BFI_IOC_IMG_VER_SAME,
	278	BFI_IOC_IMG_VER_BETTER
	279	};
	280
078086f3 RM	281	#define BFI_FWBOOT_DEVMODE_OFF 4
	282	#define BFI_FWBOOT_TYPE_OFF 8
	283	#define BFI_FWBOOT_ENV_OFF 12
	284	#define BFI_FWBOOT_DEVMODE(__asic_gen, __asic_mode, __p0_mode, __p1_mode) \
	285	(((u32)(__asic_gen)) << 24 \| \
	286	((u32)(__asic_mode)) << 16 \| \
	287	((u32)(__p0_mode)) << 8 \| \
	288	((u32)(__p1_mode)))
	289
d4e16d42 RM	290	enum bfi_fwboot_type {
	291	BFI_FWBOOT_TYPE_NORMAL = 0,
	292	BFI_FWBOOT_TYPE_FLASH = 1,
	293	BFI_FWBOOT_TYPE_MEMTEST = 2,
	294	};
	295
078086f3 RM	296	enum bfi_port_mode {
	297	BFI_PORT_MODE_FC = 1,
	298	BFI_PORT_MODE_ETH = 2,
	299	};
	300
8b230ed8 RM	301	struct bfi_ioc_hbeat {
	302	struct bfi_mhdr mh; /!< common msg header /
	303	u32 hb_count; /!< current heart beat count /
	304	};
	305
1aa8b471	306	/* IOC hardware/firmware state */
8b230ed8 RM	307	enum bfi_ioc_state {
	308	BFI_IOC_UNINIT = 0, /!< not initialized /
	309	BFI_IOC_INITING = 1, /!< h/w is being initialized /
	310	BFI_IOC_HWINIT = 2, /!< h/w is initialized /
	311	BFI_IOC_CFG = 3, /!< IOC configuration in progress /
	312	BFI_IOC_OP = 4, /!< IOC is operational /
	313	BFI_IOC_DISABLING = 5, /!< IOC is being disabled /
	314	BFI_IOC_DISABLED = 6, /!< IOC is disabled /
	315	BFI_IOC_CFG_DISABLED = 7, /!< IOC is being disabled;transient /
	316	BFI_IOC_FAIL = 8, /!< IOC heart-beat failure /
	317	BFI_IOC_MEMTEST = 9, /!< IOC is doing memtest /
	318	};
	319
	320	#define BFI_IOC_ENDIAN_SIG 0x12345678
	321
	322	enum {
	323	BFI_ADAPTER_TYPE_FC = 0x01, /!< FC adapters /
	324	BFI_ADAPTER_TYPE_MK = 0x0f0000, /!< adapter type mask /
	325	BFI_ADAPTER_TYPE_SH = 16, /!< adapter type shift /
	326	BFI_ADAPTER_NPORTS_MK = 0xff00, /!< number of ports mask /
	327	BFI_ADAPTER_NPORTS_SH = 8, /!< number of ports shift /
	328	BFI_ADAPTER_SPEED_MK = 0xff, /!< adapter speed mask /
	329	BFI_ADAPTER_SPEED_SH = 0, /!< adapter speed shift /
	330	BFI_ADAPTER_PROTO = 0x100000, /!< prototype adapaters /
	331	BFI_ADAPTER_TTV = 0x200000, /!< TTV debug capable /
	332	BFI_ADAPTER_UNSUPP = 0x400000, /!< unknown adapter type /
	333	};
	334
	335	#define BFI_ADAPTER_GETP(__prop, __adap_prop) \
	336	(((__adap_prop) & BFI_ADAPTER_ ## __prop ## _MK) >> \
	337	BFI_ADAPTER_ ## __prop ## _SH)
	338	#define BFI_ADAPTER_SETP(__prop, __val) \
	339	((__val) << BFI_ADAPTER_ ## __prop ## _SH)
	340	#define BFI_ADAPTER_IS_PROTO(__adap_type) \
	341	((__adap_type) & BFI_ADAPTER_PROTO)
	342	#define BFI_ADAPTER_IS_TTV(__adap_type) \
	343	((__adap_type) & BFI_ADAPTER_TTV)
	344	#define BFI_ADAPTER_IS_UNSUPP(__adap_type) \
	345	((__adap_type) & BFI_ADAPTER_UNSUPP)
	346	#define BFI_ADAPTER_IS_SPECIAL(__adap_type) \
	347	((__adap_type) & (BFI_ADAPTER_TTV \| BFI_ADAPTER_PROTO \| \
	348	BFI_ADAPTER_UNSUPP))
	349
1aa8b471	350	/* BFI_IOC_H2I_ENABLE_REQ & BFI_IOC_H2I_DISABLE_REQ messages */
8b230ed8 RM	351	struct bfi_ioc_ctrl_req {
8b230ed8 RM	352	struct bfi_mhdr mh;
078086f3 RM	353	u16 clscode;
078086f3 RM	354	u16 rsvd;
8b230ed8 RM	355	u32 tv_sec;
	356	};
	357
1aa8b471	358	/* BFI_IOC_I2H_ENABLE_REPLY & BFI_IOC_I2H_DISABLE_REPLY messages */
8b230ed8	359	struct bfi_ioc_ctrl_reply {
078086f3	360	struct bfi_mhdr mh; /!< Common msg header /
8b230ed8	361	u8 status; /!< enable/disable status /
078086f3 RM	362	u8 port_mode; /!< enum bfa_mode /
	363	u8 cap_bm; /!< capability bit mask /
	364	u8 rsvd;
8b230ed8 RM	365	};
	366
	367	#define BFI_IOC_MSGSZ 8
1aa8b471	368	/* H2I Messages */
8b230ed8 RM	369	union bfi_ioc_h2i_msg_u {
	370	struct bfi_mhdr mh;
	371	struct bfi_ioc_ctrl_req enable_req;
	372	struct bfi_ioc_ctrl_req disable_req;
	373	struct bfi_ioc_getattr_req getattr_req;
	374	u32 mboxmsg[BFI_IOC_MSGSZ];
	375	};
	376
1aa8b471	377	/* I2H Messages */
8b230ed8 RM	378	union bfi_ioc_i2h_msg_u {
8b230ed8 RM	379	struct bfi_mhdr mh;
078086f3	380	struct bfi_ioc_ctrl_reply fw_event;
8b230ed8 RM	381	u32 mboxmsg[BFI_IOC_MSGSZ];
	382	};
	383
1aa8b471	384	/*----------------------------------------------------------------------
af027a34 RM	385	* MSGQ
	386	*----------------------------------------------------------------------
	387	*/
	388
	389	enum bfi_msgq_h2i_msgs {
	390	BFI_MSGQ_H2I_INIT_REQ = 1,
	391	BFI_MSGQ_H2I_DOORBELL_PI = 2,
	392	BFI_MSGQ_H2I_DOORBELL_CI = 3,
	393	BFI_MSGQ_H2I_CMDQ_COPY_RSP = 4,
	394	};
	395
	396	enum bfi_msgq_i2h_msgs {
	397	BFI_MSGQ_I2H_INIT_RSP = BFA_I2HM(BFI_MSGQ_H2I_INIT_REQ),
	398	BFI_MSGQ_I2H_DOORBELL_PI = BFA_I2HM(BFI_MSGQ_H2I_DOORBELL_PI),
	399	BFI_MSGQ_I2H_DOORBELL_CI = BFA_I2HM(BFI_MSGQ_H2I_DOORBELL_CI),
	400	BFI_MSGQ_I2H_CMDQ_COPY_REQ = BFA_I2HM(BFI_MSGQ_H2I_CMDQ_COPY_RSP),
	401	};
	402
	403	/* Messages(commands/responsed/AENS will have the following header */
	404	struct bfi_msgq_mhdr {
	405	u8 msg_class;
	406	u8 msg_id;
	407	u16 msg_token;
	408	u16 num_entries;
	409	u8 enet_id;
	410	u8 rsvd[1];
	411	};
	412
	413	#define bfi_msgq_mhdr_set(_mh, _mc, _mid, _tok, _enet_id) do { \
	414	(_mh).msg_class = (_mc); \
	415	(_mh).msg_id = (_mid); \
	416	(_mh).msg_token = (_tok); \
	417	(_mh).enet_id = (_enet_id); \
	418	} while (0)
	419
	420	/*
	421	* Mailbox for messaging interface
	422	*/
	423	#define BFI_MSGQ_CMD_ENTRY_SIZE (64) /* TBD */
	424	#define BFI_MSGQ_RSP_ENTRY_SIZE (64) /* TBD */
	425
	426	#define bfi_msgq_num_cmd_entries(_size) \
	427	(((_size) + BFI_MSGQ_CMD_ENTRY_SIZE - 1) / BFI_MSGQ_CMD_ENTRY_SIZE)
	428
	429	struct bfi_msgq {
	430	union bfi_addr_u addr;
	431	u16 q_depth; /* Total num of entries in the queue */
	432	u8 rsvd[2];
	433	};
	434
	435	/* BFI_ENET_MSGQ_CFG_REQ TBD init or cfg? */
	436	struct bfi_msgq_cfg_req {
	437	struct bfi_mhdr mh;
	438	struct bfi_msgq cmdq;
	439	struct bfi_msgq rspq;
	440	};
	441
	442	/* BFI_ENET_MSGQ_CFG_RSP */
	443	struct bfi_msgq_cfg_rsp {
	444	struct bfi_mhdr mh;
	445	u8 cmd_status;
	446	u8 rsvd[3];
	447	};
	448
449	/* BFI_MSGQ_H2I_DOORBELL */
450	struct bfi_msgq_h2i_db {
451	struct bfi_mhdr mh;
452	union {
453	u16 cmdq_pi;
454	u16 rspq_ci;
455	} idx;
456	};
457
458	/* BFI_MSGQ_I2H_DOORBELL */
459	struct bfi_msgq_i2h_db {
460	struct bfi_mhdr mh;
461	union {
462	u16 rspq_pi;
463	u16 cmdq_ci;
464	} idx;
465	};
466
467	#define BFI_CMD_COPY_SZ 28
468
469	/* BFI_MSGQ_H2I_CMD_COPY_RSP */
470	struct bfi_msgq_h2i_cmdq_copy_rsp {
471	struct bfi_mhdr mh;
472	u8 data[BFI_CMD_COPY_SZ];
473	};
474
475	/* BFI_MSGQ_I2H_CMD_COPY_REQ */
476	struct bfi_msgq_i2h_cmdq_copy_req {
477	struct bfi_mhdr mh;
478	u16 offset;
479	u16 len;
480	};
481
72a9730b KG	482	/*
	483	* FLASH module specific
	484	*/
	485	enum bfi_flash_h2i_msgs {
	486	BFI_FLASH_H2I_QUERY_REQ = 1,
	487	BFI_FLASH_H2I_ERASE_REQ = 2,
	488	BFI_FLASH_H2I_WRITE_REQ = 3,
	489	BFI_FLASH_H2I_READ_REQ = 4,
	490	BFI_FLASH_H2I_BOOT_VER_REQ = 5,
	491	};
	492
	493	enum bfi_flash_i2h_msgs {
	494	BFI_FLASH_I2H_QUERY_RSP = BFA_I2HM(1),
	495	BFI_FLASH_I2H_ERASE_RSP = BFA_I2HM(2),
	496	BFI_FLASH_I2H_WRITE_RSP = BFA_I2HM(3),
	497	BFI_FLASH_I2H_READ_RSP = BFA_I2HM(4),
	498	BFI_FLASH_I2H_BOOT_VER_RSP = BFA_I2HM(5),
	499	BFI_FLASH_I2H_EVENT = BFA_I2HM(127),
	500	};
	501
	502	/*
	503	* Flash query request
	504	*/
	505	struct bfi_flash_query_req {
	506	struct bfi_mhdr mh; /* Common msg header */
	507	struct bfi_alen alen;
	508	};
	509
	510	/*
	511	* Flash write request
	512	*/
	513	struct bfi_flash_write_req {
	514	struct bfi_mhdr mh; /* Common msg header */
	515	struct bfi_alen alen;
	516	u32 type; /* partition type */
	517	u8 instance; /* partition instance */
	518	u8 last;
	519	u8 rsv[2];
	520	u32 offset;
	521	u32 length;
	522	};
	523
	524	/*
	525	* Flash read request
	526	*/
	527	struct bfi_flash_read_req {
	528	struct bfi_mhdr mh; /* Common msg header */
	529	u32 type; /* partition type */
	530	u8 instance; /* partition instance */
	531	u8 rsv[3];
	532	u32 offset;
	533	u32 length;
	534	struct bfi_alen alen;
	535	};
	536
	537	/*
	538	* Flash query response
	539	*/
	540	struct bfi_flash_query_rsp {
	541	struct bfi_mhdr mh; /* Common msg header */
	542	u32 status;
	543	};
	544
	545	/*
546	* Flash read response
547	*/
548	struct bfi_flash_read_rsp {
549	struct bfi_mhdr mh; /* Common msg header */
550	u32 type; /* partition type */
551	u8 instance; /* partition instance */
552	u8 rsv[3];
553	u32 status;
554	u32 length;
555	};
556
557	/*
558	* Flash write response
559	*/
560	struct bfi_flash_write_rsp {
561	struct bfi_mhdr mh; /* Common msg header */
562	u32 type; /* partition type */
563	u8 instance; /* partition instance */
564	u8 rsv[3];
565	u32 status;
566	u32 length;
567	};
568
8b230ed8 RM	569	#pragma pack()
	570
	571	#endif /* __BFI_H__ */