[deliverable/linux.git] / drivers / net / ethernet / brocade / bna / bnad.h

/*
 * Linux network driver for Brocade Converged Network Adapter.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License (GPL) Version 2 as
 * published by the Free Software Foundation
 *
 * This program is distributed in the hope that it will be useful, but
 * WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * General Public License for more details.
 */
/*
 * Copyright (c) 2005-2010 Brocade Communications Systems, Inc.
 * All rights reserved
 * www.brocade.com
 */
#ifndef __BNAD_H__
#define __BNAD_H__

#include <linux/rtnetlink.h>
#include <linux/workqueue.h>
#include <linux/ipv6.h>
#include <linux/etherdevice.h>
#include <linux/mutex.h>
#include <linux/firmware.h>
#include <linux/if_vlan.h>

/* Fix for IA64 */
#include <asm/checksum.h>
#include <net/ip6_checksum.h>

#include <net/ip.h>
#include <net/tcp.h>

#include "bna.h"

#define BNAD_TXQ_DEPTH		2048
#define BNAD_RXQ_DEPTH		2048

#define BNAD_MAX_TX		1
#define BNAD_MAX_TXQ_PER_TX	8	/* 8 priority queues */
#define BNAD_TXQ_NUM		1

#define BNAD_MAX_RX		1
#define BNAD_MAX_RXP_PER_RX	16
#define BNAD_MAX_RXQ_PER_RXP	2

/*
 * Control structure pointed to ccb->ctrl, which
 * determines the NAPI / LRO behavior CCB
 * There is 1:1 corres. between ccb & ctrl
 */
struct bnad_rx_ctrl {
	struct bna_ccb *ccb;
	unsigned long  flags;
	struct napi_struct	napi;
};

#define BNAD_RXMODE_PROMISC_DEFAULT	BNA_RXMODE_PROMISC

#define BNAD_GET_TX_ID(_skb)	(0)

/*
 * GLOBAL #defines (CONSTANTS)
 */
#define BNAD_NAME			"bna"
#define BNAD_NAME_LEN			64

#define BNAD_VERSION			"3.0.2.0"

#define BNAD_MAILBOX_MSIX_INDEX		0
#define BNAD_MAILBOX_MSIX_VECTORS	1
#define BNAD_INTX_TX_IB_BITMASK		0x1
#define BNAD_INTX_RX_IB_BITMASK		0x2

#define BNAD_STATS_TIMER_FREQ		1000	/* in msecs */
#define BNAD_DIM_TIMER_FREQ		1000	/* in msecs */

#define BNAD_IOCETH_TIMEOUT	     10000

#define BNAD_MAX_Q_DEPTH		0x10000
#define BNAD_MIN_Q_DEPTH		0x200

#define BNAD_JUMBO_MTU			9000

#define BNAD_NETIF_WAKE_THRESHOLD	8

#define BNAD_RXQ_REFILL_THRESHOLD_SHIFT	3

/* Bit positions for tcb->flags */
#define BNAD_TXQ_FREE_SENT		0
#define BNAD_TXQ_TX_STARTED		1

/* Bit positions for rcb->flags */
#define BNAD_RXQ_REFILL			0
#define BNAD_RXQ_STARTED		1

/* Resource limits */
#define BNAD_NUM_TXQ			(bnad->num_tx * bnad->num_txq_per_tx)
#define BNAD_NUM_RXP			(bnad->num_rx * bnad->num_rxp_per_rx)

/*
 * DATA STRUCTURES
 */

/* enums */
enum bnad_intr_source {
	BNAD_INTR_TX		= 1,
	BNAD_INTR_RX		= 2
};

enum bnad_link_state {
	BNAD_LS_DOWN		= 0,
	BNAD_LS_UP		= 1
};

struct bnad_completion {
	struct completion	ioc_comp;
	struct completion	ucast_comp;
	struct completion	mcast_comp;
	struct completion	tx_comp;
	struct completion	rx_comp;
	struct completion	stats_comp;
	struct completion	enet_comp;
	struct completion	mtu_comp;

	u8			ioc_comp_status;
	u8			ucast_comp_status;
	u8			mcast_comp_status;
	u8			tx_comp_status;
	u8			rx_comp_status;
	u8			stats_comp_status;
	u8			port_comp_status;
	u8			mtu_comp_status;
};

/* Tx Rx Control Stats */
struct bnad_drv_stats {
	u64		netif_queue_stop;
	u64		netif_queue_wakeup;
	u64		netif_queue_stopped;
	u64		tso4;
	u64		tso6;
	u64		tso_err;
	u64		tcpcsum_offload;
	u64		udpcsum_offload;
	u64		csum_help;
	u64		csum_help_err;

	u64		hw_stats_updates;
	u64		netif_rx_schedule;
	u64		netif_rx_complete;
	u64		netif_rx_dropped;

	u64		link_toggle;
	u64		cee_toggle;
	u64		cee_up;

	u64		rxp_info_alloc_failed;
	u64		mbox_intr_disabled;
	u64		mbox_intr_enabled;
	u64		tx_unmap_q_alloc_failed;
	u64		rx_unmap_q_alloc_failed;

	u64		rxbuf_alloc_failed;
};

/* Complete driver stats */
struct bnad_stats {
	struct bnad_drv_stats drv_stats;
	struct bna_stats *bna_stats;
};

/* Tx / Rx Resources */
struct bnad_tx_res_info {
	struct bna_res_info res_info[BNA_TX_RES_T_MAX];
};

struct bnad_rx_res_info {
	struct bna_res_info res_info[BNA_RX_RES_T_MAX];
};

struct bnad_tx_info {
	struct bna_tx *tx; /* 1:1 between tx_info & tx */
	struct bna_tcb *tcb[BNAD_MAX_TXQ_PER_TX];
	u32 tx_id;
} ____cacheline_aligned;

struct bnad_rx_info {
	struct bna_rx *rx; /* 1:1 between rx_info & rx */

	struct bnad_rx_ctrl rx_ctrl[BNAD_MAX_RXP_PER_RX];
	u32 rx_id;
} ____cacheline_aligned;

/* Unmap queues for Tx / Rx cleanup */
struct bnad_skb_unmap {
	struct sk_buff		*skb;
	DEFINE_DMA_UNMAP_ADDR(dma_addr);
};

struct bnad_unmap_q {
	u32		producer_index;
	u32		consumer_index;
	u32		q_depth;
	/* This should be the last one */
	struct bnad_skb_unmap unmap_array[1];
};

/* Bit mask values for bnad->cfg_flags */
#define	BNAD_CF_DIM_ENABLED		0x01	/* DIM */
#define	BNAD_CF_PROMISC			0x02
#define BNAD_CF_ALLMULTI		0x04
#define	BNAD_CF_MSIX			0x08	/* If in MSIx mode */

/* Defines for run_flags bit-mask */
/* Set, tested & cleared using xxx_bit() functions */
/* Values indicated bit positions */
#define BNAD_RF_CEE_RUNNING		0
#define BNAD_RF_MTU_SET		1
#define BNAD_RF_MBOX_IRQ_DISABLED	2
#define BNAD_RF_NETDEV_REGISTERED	3
#define BNAD_RF_DIM_TIMER_RUNNING	4
#define BNAD_RF_STATS_TIMER_RUNNING	5
#define BNAD_RF_TX_PRIO_SET		6


/* Define for Fast Path flags */
/* Defined as bit positions */
#define BNAD_FP_IN_RX_PATH	      0

struct bnad {
	struct net_device	*netdev;

	/* Data path */
	struct bnad_tx_info tx_info[BNAD_MAX_TX];
	struct bnad_rx_info rx_info[BNAD_MAX_RX];

	unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
	/*
	 * These q numbers are global only because
	 * they are used to calculate MSIx vectors.
	 * Actually the exact # of queues are per Tx/Rx
	 * object.
	 */
	u32		num_tx;
	u32		num_rx;
	u32		num_txq_per_tx;
	u32		num_rxp_per_rx;

	u32		txq_depth;
	u32		rxq_depth;

	u8			tx_coalescing_timeo;
	u8			rx_coalescing_timeo;

	struct bna_rx_config rx_config[BNAD_MAX_RX];
	struct bna_tx_config tx_config[BNAD_MAX_TX];

	void __iomem		*bar0;	/* BAR0 address */

	struct bna bna;

	u32		cfg_flags;
	unsigned long		run_flags;

	struct pci_dev		*pcidev;
	u64		mmio_start;
	u64		mmio_len;

	u32		msix_num;
	struct msix_entry	*msix_table;

	struct mutex		conf_mutex;
	spinlock_t		bna_lock ____cacheline_aligned;

	/* Timers */
	struct timer_list	ioc_timer;
	struct timer_list	dim_timer;
	struct timer_list	stats_timer;

	/* Control path resources, memory & irq */
	struct bna_res_info res_info[BNA_RES_T_MAX];
	struct bna_res_info mod_res_info[BNA_MOD_RES_T_MAX];
	struct bnad_tx_res_info tx_res_info[BNAD_MAX_TX];
	struct bnad_rx_res_info rx_res_info[BNAD_MAX_RX];

	struct bnad_completion bnad_completions;

	/* Burnt in MAC address */
	mac_t			perm_addr;

	struct tasklet_struct	tx_free_tasklet;

	/* Statistics */
	struct bnad_stats stats;

	struct bnad_diag *diag;

	char			adapter_name[BNAD_NAME_LEN];
	char			port_name[BNAD_NAME_LEN];
	char			mbox_irq_name[BNAD_NAME_LEN];
};

/*
 * EXTERN VARIABLES
 */
extern struct firmware *bfi_fw;
extern u32		bnad_rxqs_per_cq;

/*
 * EXTERN PROTOTYPES
 */
extern u32 *cna_get_firmware_buf(struct pci_dev *pdev);
/* Netdev entry point prototypes */
extern void bnad_set_ethtool_ops(struct net_device *netdev);

/* Configuration & setup */
extern void bnad_tx_coalescing_timeo_set(struct bnad *bnad);
extern void bnad_rx_coalescing_timeo_set(struct bnad *bnad);

extern int bnad_setup_rx(struct bnad *bnad, u32 rx_id);
extern int bnad_setup_tx(struct bnad *bnad, u32 tx_id);
extern void bnad_cleanup_tx(struct bnad *bnad, u32 tx_id);
extern void bnad_cleanup_rx(struct bnad *bnad, u32 rx_id);

/* Timer start/stop protos */
extern void bnad_dim_timer_start(struct bnad *bnad);

/* Statistics */
extern void bnad_netdev_qstats_fill(struct bnad *bnad,
		struct rtnl_link_stats64 *stats);
extern void bnad_netdev_hwstats_fill(struct bnad *bnad,
		struct rtnl_link_stats64 *stats);

/**
 * MACROS
 */
/* To set & get the stats counters */
#define BNAD_UPDATE_CTR(_bnad, _ctr)				\
				(((_bnad)->stats.drv_stats._ctr)++)

#define BNAD_GET_CTR(_bnad, _ctr) ((_bnad)->stats.drv_stats._ctr)

#define bnad_enable_rx_irq_unsafe(_ccb)			\
{							\
	if (likely(test_bit(BNAD_RXQ_STARTED, &ccb->rcb[0]->flags))) {\
		bna_ib_coalescing_timer_set((_ccb)->i_dbell,	\
			(_ccb)->rx_coalescing_timeo);		\
		bna_ib_ack((_ccb)->i_dbell, 0);			\
	}							\
}

#define bnad_dim_timer_running(_bnad)				\
	(((_bnad)->cfg_flags & BNAD_CF_DIM_ENABLED) &&		\
	(test_bit(BNAD_RF_DIM_TIMER_RUNNING, &((_bnad)->run_flags))))

#endif /* __BNAD_H__ */
Commit	Line	Data
8b230ed8 RM	1	/*
	2	* Linux network driver for Brocade Converged Network Adapter.
	3	*
	4	* This program is free software; you can redistribute it and/or modify it
	5	* under the terms of the GNU General Public License (GPL) Version 2 as
	6	* published by the Free Software Foundation
	7	*
	8	* This program is distributed in the hope that it will be useful, but
	9	* WITHOUT ANY WARRANTY; without even the implied warranty of
	10	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	11	* General Public License for more details.
	12	*/
	13	/*
	14	* Copyright (c) 2005-2010 Brocade Communications Systems, Inc.
	15	* All rights reserved
	16	* www.brocade.com
	17	*/
	18	#ifndef __BNAD_H__
	19	#define __BNAD_H__
	20
	21	#include <linux/rtnetlink.h>
	22	#include <linux/workqueue.h>
	23	#include <linux/ipv6.h>
	24	#include <linux/etherdevice.h>
	25	#include <linux/mutex.h>
	26	#include <linux/firmware.h>
f859d7cb	27	#include <linux/if_vlan.h>
8b230ed8 RM	28
	29	/* Fix for IA64 */
	30	#include <asm/checksum.h>
	31	#include <net/ip6_checksum.h>
	32
	33	#include <net/ip.h>
	34	#include <net/tcp.h>
	35
	36	#include "bna.h"
	37
	38	#define BNAD_TXQ_DEPTH 2048
	39	#define BNAD_RXQ_DEPTH 2048
	40
772b5235	41	#define BNAD_MAX_TX 1
8b230ed8 RM	42	#define BNAD_MAX_TXQ_PER_TX 8 /* 8 priority queues */
	43	#define BNAD_TXQ_NUM 1
	44
772b5235 RM	45	#define BNAD_MAX_RX 1
772b5235 RM	46	#define BNAD_MAX_RXP_PER_RX 16
078086f3	47	#define BNAD_MAX_RXQ_PER_RXP 2
8b230ed8 RM	48
	49	/*
	50	* Control structure pointed to ccb->ctrl, which
	51	* determines the NAPI / LRO behavior CCB
	52	* There is 1:1 corres. between ccb & ctrl
	53	*/
	54	struct bnad_rx_ctrl {
	55	struct bna_ccb *ccb;
be7fa326	56	unsigned long flags;
8b230ed8 RM	57	struct napi_struct napi;
	58	};
	59
	60	#define BNAD_RXMODE_PROMISC_DEFAULT BNA_RXMODE_PROMISC
	61
	62	#define BNAD_GET_TX_ID(_skb) (0)
	63
	64	/*
	65	* GLOBAL #defines (CONSTANTS)
	66	*/
	67	#define BNAD_NAME "bna"
	68	#define BNAD_NAME_LEN 64
	69
5098af0a	70	#define BNAD_VERSION "3.0.2.0"
8b230ed8	71
8811e267	72	#define BNAD_MAILBOX_MSIX_INDEX 0
8b230ed8	73	#define BNAD_MAILBOX_MSIX_VECTORS 1
8811e267 RM	74	#define BNAD_INTX_TX_IB_BITMASK 0x1
8811e267 RM	75	#define BNAD_INTX_RX_IB_BITMASK 0x2
8b230ed8	76
0120b99c RM	77	#define BNAD_STATS_TIMER_FREQ 1000 /* in msecs */
0120b99c RM	78	#define BNAD_DIM_TIMER_FREQ 1000 /* in msecs */
8b230ed8	79
078086f3 RM	80	#define BNAD_IOCETH_TIMEOUT 10000
078086f3 RM	81
8b230ed8 RM	82	#define BNAD_MAX_Q_DEPTH 0x10000
	83	#define BNAD_MIN_Q_DEPTH 0x200
	84
	85	#define BNAD_JUMBO_MTU 9000
	86
	87	#define BNAD_NETIF_WAKE_THRESHOLD 8
	88
	89	#define BNAD_RXQ_REFILL_THRESHOLD_SHIFT 3
	90
	91	/* Bit positions for tcb->flags */
	92	#define BNAD_TXQ_FREE_SENT 0
be7fa326	93	#define BNAD_TXQ_TX_STARTED 1
8b230ed8 RM	94
	95	/* Bit positions for rcb->flags */
	96	#define BNAD_RXQ_REFILL 0
	97	#define BNAD_RXQ_STARTED 1
	98
078086f3 RM	99	/* Resource limits */
	100	#define BNAD_NUM_TXQ (bnad->num_tx * bnad->num_txq_per_tx)
	101	#define BNAD_NUM_RXP (bnad->num_rx * bnad->num_rxp_per_rx)
	102
8b230ed8 RM	103	/*
	104	* DATA STRUCTURES
	105	*/
	106
	107	/* enums */
	108	enum bnad_intr_source {
	109	BNAD_INTR_TX = 1,
	110	BNAD_INTR_RX = 2
	111	};
	112
	113	enum bnad_link_state {
	114	BNAD_LS_DOWN = 0,
0120b99c	115	BNAD_LS_UP = 1
8b230ed8 RM	116	};
	117
	118	struct bnad_completion {
0120b99c RM	119	struct completion ioc_comp;
0120b99c RM	120	struct completion ucast_comp;
8b230ed8 RM	121	struct completion mcast_comp;
	122	struct completion tx_comp;
	123	struct completion rx_comp;
	124	struct completion stats_comp;
078086f3 RM	125	struct completion enet_comp;
078086f3 RM	126	struct completion mtu_comp;
8b230ed8 RM	127
	128	u8 ioc_comp_status;
	129	u8 ucast_comp_status;
	130	u8 mcast_comp_status;
	131	u8 tx_comp_status;
	132	u8 rx_comp_status;
	133	u8 stats_comp_status;
	134	u8 port_comp_status;
078086f3	135	u8 mtu_comp_status;
8b230ed8 RM	136	};
	137
	138	/* Tx Rx Control Stats */
	139	struct bnad_drv_stats {
0120b99c	140	u64 netif_queue_stop;
8b230ed8	141	u64 netif_queue_wakeup;
f7c0fa4c	142	u64 netif_queue_stopped;
8b230ed8 RM	143	u64 tso4;
	144	u64 tso6;
	145	u64 tso_err;
	146	u64 tcpcsum_offload;
	147	u64 udpcsum_offload;
	148	u64 csum_help;
	149	u64 csum_help_err;
	150
	151	u64 hw_stats_updates;
	152	u64 netif_rx_schedule;
	153	u64 netif_rx_complete;
	154	u64 netif_rx_dropped;
	155
	156	u64 link_toggle;
078086f3	157	u64 cee_toggle;
8b230ed8 RM	158	u64 cee_up;
	159
	160	u64 rxp_info_alloc_failed;
	161	u64 mbox_intr_disabled;
	162	u64 mbox_intr_enabled;
	163	u64 tx_unmap_q_alloc_failed;
	164	u64 rx_unmap_q_alloc_failed;
	165
	166	u64 rxbuf_alloc_failed;
	167	};
	168
	169	/* Complete driver stats */
	170	struct bnad_stats {
	171	struct bnad_drv_stats drv_stats;
	172	struct bna_stats *bna_stats;
	173	};
	174
	175	/* Tx / Rx Resources */
	176	struct bnad_tx_res_info {
	177	struct bna_res_info res_info[BNA_TX_RES_T_MAX];
	178	};
	179
	180	struct bnad_rx_res_info {
	181	struct bna_res_info res_info[BNA_RX_RES_T_MAX];
	182	};
	183
	184	struct bnad_tx_info {
	185	struct bna_tx tx; / 1:1 between tx_info & tx */
	186	struct bna_tcb *tcb[BNAD_MAX_TXQ_PER_TX];
078086f3	187	u32 tx_id;
8b230ed8 RM	188	} ____cacheline_aligned;
	189
	190	struct bnad_rx_info {
	191	struct bna_rx rx; / 1:1 between rx_info & rx */
	192
772b5235	193	struct bnad_rx_ctrl rx_ctrl[BNAD_MAX_RXP_PER_RX];
078086f3	194	u32 rx_id;
8b230ed8 RM	195	} ____cacheline_aligned;
	196
	197	/* Unmap queues for Tx / Rx cleanup */
	198	struct bnad_skb_unmap {
	199	struct sk_buff *skb;
5ea74318	200	DEFINE_DMA_UNMAP_ADDR(dma_addr);
8b230ed8 RM	201	};
	202
	203	struct bnad_unmap_q {
	204	u32 producer_index;
	205	u32 consumer_index;
0120b99c	206	u32 q_depth;
8b230ed8 RM	207	/* This should be the last one */
	208	struct bnad_skb_unmap unmap_array[1];
	209	};
	210
	211	/* Bit mask values for bnad->cfg_flags */
	212	#define BNAD_CF_DIM_ENABLED 0x01 /* DIM */
	213	#define BNAD_CF_PROMISC 0x02
	214	#define BNAD_CF_ALLMULTI 0x04
	215	#define BNAD_CF_MSIX 0x08 /* If in MSIx mode */
	216
	217	/* Defines for run_flags bit-mask */
	218	/* Set, tested & cleared using xxx_bit() functions */
	219	/* Values indicated bit positions */
078086f3 RM	220	#define BNAD_RF_CEE_RUNNING 0
078086f3 RM	221	#define BNAD_RF_MTU_SET 1
be7fa326	222	#define BNAD_RF_MBOX_IRQ_DISABLED 2
078086f3	223	#define BNAD_RF_NETDEV_REGISTERED 3
be7fa326 RM	224	#define BNAD_RF_DIM_TIMER_RUNNING 4
be7fa326 RM	225	#define BNAD_RF_STATS_TIMER_RUNNING 5
078086f3 RM	226	#define BNAD_RF_TX_PRIO_SET 6
	227
	228
	229	/* Define for Fast Path flags */
	230	/* Defined as bit positions */
	231	#define BNAD_FP_IN_RX_PATH 0
8b230ed8 RM	232
8b230ed8 RM	233	struct bnad {
0120b99c	234	struct net_device *netdev;
8b230ed8 RM	235
8b230ed8 RM	236	/* Data path */
772b5235 RM	237	struct bnad_tx_info tx_info[BNAD_MAX_TX];
772b5235 RM	238	struct bnad_rx_info rx_info[BNAD_MAX_RX];
8b230ed8	239
f859d7cb	240	unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
8b230ed8 RM	241	/*
	242	* These q numbers are global only because
	243	* they are used to calculate MSIx vectors.
	244	* Actually the exact # of queues are per Tx/Rx
	245	* object.
	246	*/
	247	u32 num_tx;
	248	u32 num_rx;
	249	u32 num_txq_per_tx;
	250	u32 num_rxp_per_rx;
	251
	252	u32 txq_depth;
	253	u32 rxq_depth;
	254
	255	u8 tx_coalescing_timeo;
	256	u8 rx_coalescing_timeo;
	257
772b5235 RM	258	struct bna_rx_config rx_config[BNAD_MAX_RX];
772b5235 RM	259	struct bna_tx_config tx_config[BNAD_MAX_TX];
8b230ed8	260
8b230ed8 RM	261	void __iomem bar0; / BAR0 address */
	262
	263	struct bna bna;
	264
	265	u32 cfg_flags;
	266	unsigned long run_flags;
	267
0120b99c	268	struct pci_dev *pcidev;
8b230ed8 RM	269	u64 mmio_start;
	270	u64 mmio_len;
	271
	272	u32 msix_num;
8b230ed8 RM	273	struct msix_entry *msix_table;
	274
	275	struct mutex conf_mutex;
	276	spinlock_t bna_lock ____cacheline_aligned;
	277
	278	/* Timers */
	279	struct timer_list ioc_timer;
	280	struct timer_list dim_timer;
	281	struct timer_list stats_timer;
	282
	283	/* Control path resources, memory & irq */
	284	struct bna_res_info res_info[BNA_RES_T_MAX];
078086f3	285	struct bna_res_info mod_res_info[BNA_MOD_RES_T_MAX];
772b5235 RM	286	struct bnad_tx_res_info tx_res_info[BNAD_MAX_TX];
772b5235 RM	287	struct bnad_rx_res_info rx_res_info[BNAD_MAX_RX];
8b230ed8 RM	288
	289	struct bnad_completion bnad_completions;
	290
	291	/* Burnt in MAC address */
	292	mac_t perm_addr;
	293
	294	struct tasklet_struct tx_free_tasklet;
	295
	296	/* Statistics */
	297	struct bnad_stats stats;
8b230ed8 RM	298
	299	struct bnad_diag *diag;
	300
	301	char adapter_name[BNAD_NAME_LEN];
0120b99c	302	char port_name[BNAD_NAME_LEN];
8b230ed8 RM	303	char mbox_irq_name[BNAD_NAME_LEN];
	304	};
	305
	306	/*
	307	* EXTERN VARIABLES
	308	*/
	309	extern struct firmware *bfi_fw;
0120b99c	310	extern u32 bnad_rxqs_per_cq;
8b230ed8 RM	311
	312	/*
	313	* EXTERN PROTOTYPES
	314	*/
	315	extern u32 cna_get_firmware_buf(struct pci_dev pdev);
	316	/* Netdev entry point prototypes */
	317	extern void bnad_set_ethtool_ops(struct net_device *netdev);
	318
	319	/* Configuration & setup */
	320	extern void bnad_tx_coalescing_timeo_set(struct bnad *bnad);
	321	extern void bnad_rx_coalescing_timeo_set(struct bnad *bnad);
	322
078086f3 RM	323	extern int bnad_setup_rx(struct bnad *bnad, u32 rx_id);
	324	extern int bnad_setup_tx(struct bnad *bnad, u32 tx_id);
	325	extern void bnad_cleanup_tx(struct bnad *bnad, u32 tx_id);
	326	extern void bnad_cleanup_rx(struct bnad *bnad, u32 rx_id);
8b230ed8 RM	327
	328	/* Timer start/stop protos */
	329	extern void bnad_dim_timer_start(struct bnad *bnad);
	330
	331	/* Statistics */
f7c0fa4c RM	332	extern void bnad_netdev_qstats_fill(struct bnad *bnad,
	333	struct rtnl_link_stats64 *stats);
	334	extern void bnad_netdev_hwstats_fill(struct bnad *bnad,
	335	struct rtnl_link_stats64 *stats);
8b230ed8 RM	336
	337	/**
	338	* MACROS
	339	*/
	340	/* To set & get the stats counters */
	341	#define BNAD_UPDATE_CTR(_bnad, _ctr) \
	342	(((_bnad)->stats.drv_stats._ctr)++)
	343
	344	#define BNAD_GET_CTR(_bnad, _ctr) ((_bnad)->stats.drv_stats._ctr)
	345
	346	#define bnad_enable_rx_irq_unsafe(_ccb) \
	347	{ \
be7fa326 RM	348	if (likely(test_bit(BNAD_RXQ_STARTED, &ccb->rcb[0]->flags))) {\
	349	bna_ib_coalescing_timer_set((_ccb)->i_dbell, \
	350	(_ccb)->rx_coalescing_timeo); \
	351	bna_ib_ack((_ccb)->i_dbell, 0); \
	352	} \
8b230ed8 RM	353	}
	354
	355	#define bnad_dim_timer_running(_bnad) \
0120b99c	356	(((_bnad)->cfg_flags & BNAD_CF_DIM_ENABLED) && \
8b230ed8 RM	357	(test_bit(BNAD_RF_DIM_TIMER_RUNNING, &((_bnad)->run_flags))))
	358
	359	#endif /* __BNAD_H__ */