[deliverable/linux.git] / drivers / net / ethernet / brocade / bna / bnad.h

/*
 * Linux network driver for QLogic BR-series Converged Network Adapter.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License (GPL) Version 2 as
 * published by the Free Software Foundation
 *
 * This program is distributed in the hope that it will be useful, but
 * WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * General Public License for more details.
 */
/*
 * Copyright (c) 2005-2014 Brocade Communications Systems, Inc.
 * Copyright (c) 2014-2015 QLogic Corporation
 * All rights reserved
 * www.qlogic.com
 */
#ifndef __BNAD_H__
#define __BNAD_H__

#include <linux/rtnetlink.h>
#include <linux/workqueue.h>
#include <linux/ipv6.h>
#include <linux/etherdevice.h>
#include <linux/mutex.h>
#include <linux/firmware.h>
#include <linux/if_vlan.h>

/* Fix for IA64 */
#include <asm/checksum.h>
#include <net/ip6_checksum.h>

#include <net/ip.h>
#include <net/tcp.h>

#include "bna.h"

#define BNAD_TXQ_DEPTH		2048
#define BNAD_RXQ_DEPTH		2048

#define BNAD_MAX_TX		1
#define BNAD_MAX_TXQ_PER_TX	8	/* 8 priority queues */
#define BNAD_TXQ_NUM		1

#define BNAD_MAX_RX		1
#define BNAD_MAX_RXP_PER_RX	16
#define BNAD_MAX_RXQ_PER_RXP	2

/*
 * Control structure pointed to ccb->ctrl, which
 * determines the NAPI / LRO behavior CCB
 * There is 1:1 corres. between ccb & ctrl
 */
struct bnad_rx_ctrl {
	struct bna_ccb *ccb;
	struct bnad *bnad;
	unsigned long  flags;
	struct napi_struct	napi;
	u64		rx_intr_ctr;
	u64		rx_poll_ctr;
	u64		rx_schedule;
	u64		rx_keep_poll;
	u64		rx_complete;
};

#define BNAD_RXMODE_PROMISC_DEFAULT	BNA_RXMODE_PROMISC

/*
 * GLOBAL #defines (CONSTANTS)
 */
#define BNAD_NAME			"bna"
#define BNAD_NAME_LEN			64

#define BNAD_VERSION			"3.2.25.1"

#define BNAD_MAILBOX_MSIX_INDEX		0
#define BNAD_MAILBOX_MSIX_VECTORS	1
#define BNAD_INTX_TX_IB_BITMASK		0x1
#define BNAD_INTX_RX_IB_BITMASK		0x2

#define BNAD_STATS_TIMER_FREQ		1000	/* in msecs */
#define BNAD_DIM_TIMER_FREQ		1000	/* in msecs */

#define BNAD_IOCETH_TIMEOUT	     10000

#define BNAD_MIN_Q_DEPTH		512
#define BNAD_MAX_RXQ_DEPTH		16384
#define BNAD_MAX_TXQ_DEPTH		2048

#define BNAD_JUMBO_MTU			9000

#define BNAD_NETIF_WAKE_THRESHOLD	8

#define BNAD_RXQ_REFILL_THRESHOLD_SHIFT	3

/* Bit positions for tcb->flags */
#define BNAD_TXQ_FREE_SENT		0
#define BNAD_TXQ_TX_STARTED		1

/* Bit positions for rcb->flags */
#define BNAD_RXQ_STARTED		0
#define BNAD_RXQ_POST_OK		1

/* Resource limits */
#define BNAD_NUM_TXQ			(bnad->num_tx * bnad->num_txq_per_tx)
#define BNAD_NUM_RXP			(bnad->num_rx * bnad->num_rxp_per_rx)

#define BNAD_FRAME_SIZE(_mtu) \
	(ETH_HLEN + VLAN_HLEN + (_mtu) + ETH_FCS_LEN)

/*
 * DATA STRUCTURES
 */

/* enums */
enum bnad_intr_source {
	BNAD_INTR_TX		= 1,
	BNAD_INTR_RX		= 2
};

enum bnad_link_state {
	BNAD_LS_DOWN		= 0,
	BNAD_LS_UP		= 1
};

struct bnad_iocmd_comp {
	struct bnad		*bnad;
	struct completion	comp;
	int			comp_status;
};

struct bnad_completion {
	struct completion	ioc_comp;
	struct completion	ucast_comp;
	struct completion	mcast_comp;
	struct completion	tx_comp;
	struct completion	rx_comp;
	struct completion	stats_comp;
	struct completion	enet_comp;
	struct completion	mtu_comp;

	u8			ioc_comp_status;
	u8			ucast_comp_status;
	u8			mcast_comp_status;
	u8			tx_comp_status;
	u8			rx_comp_status;
	u8			stats_comp_status;
	u8			port_comp_status;
	u8			mtu_comp_status;
};

/* Tx Rx Control Stats */
struct bnad_drv_stats {
	u64		netif_queue_stop;
	u64		netif_queue_wakeup;
	u64		netif_queue_stopped;
	u64		tso4;
	u64		tso6;
	u64		tso_err;
	u64		tcpcsum_offload;
	u64		udpcsum_offload;
	u64		csum_help;
	u64		tx_skb_too_short;
	u64		tx_skb_stopping;
	u64		tx_skb_max_vectors;
	u64		tx_skb_mss_too_long;
	u64		tx_skb_tso_too_short;
	u64		tx_skb_tso_prepare;
	u64		tx_skb_non_tso_too_long;
	u64		tx_skb_tcp_hdr;
	u64		tx_skb_udp_hdr;
	u64		tx_skb_csum_err;
	u64		tx_skb_headlen_too_long;
	u64		tx_skb_headlen_zero;
	u64		tx_skb_frag_zero;
	u64		tx_skb_len_mismatch;

	u64		hw_stats_updates;
	u64		netif_rx_dropped;

	u64		link_toggle;
	u64		cee_toggle;

	u64		rxp_info_alloc_failed;
	u64		mbox_intr_disabled;
	u64		mbox_intr_enabled;
	u64		tx_unmap_q_alloc_failed;
	u64		rx_unmap_q_alloc_failed;

	u64		rxbuf_alloc_failed;
};

/* Complete driver stats */
struct bnad_stats {
	struct bnad_drv_stats drv_stats;
	struct bna_stats *bna_stats;
};

/* Tx / Rx Resources */
struct bnad_tx_res_info {
	struct bna_res_info res_info[BNA_TX_RES_T_MAX];
};

struct bnad_rx_res_info {
	struct bna_res_info res_info[BNA_RX_RES_T_MAX];
};

struct bnad_tx_info {
	struct bna_tx *tx; /* 1:1 between tx_info & tx */
	struct bna_tcb *tcb[BNAD_MAX_TXQ_PER_TX];
	u32 tx_id;
	struct delayed_work tx_cleanup_work;
} ____cacheline_aligned;

struct bnad_rx_info {
	struct bna_rx *rx; /* 1:1 between rx_info & rx */

	struct bnad_rx_ctrl rx_ctrl[BNAD_MAX_RXP_PER_RX];
	u32 rx_id;
	struct work_struct rx_cleanup_work;
} ____cacheline_aligned;

struct bnad_tx_vector {
	DEFINE_DMA_UNMAP_ADDR(dma_addr);
	DEFINE_DMA_UNMAP_LEN(dma_len);
};

struct bnad_tx_unmap {
	struct sk_buff		*skb;
	u32			nvecs;
	struct bnad_tx_vector	vectors[BFI_TX_MAX_VECTORS_PER_WI];
};

struct bnad_rx_vector {
	DEFINE_DMA_UNMAP_ADDR(dma_addr);
	u32			len;
};

struct bnad_rx_unmap {
	struct page		*page;
	struct sk_buff		*skb;
	struct bnad_rx_vector	vector;
	u32			page_offset;
};

enum bnad_rxbuf_type {
	BNAD_RXBUF_NONE		= 0,
	BNAD_RXBUF_SK_BUFF	= 1,
	BNAD_RXBUF_PAGE		= 2,
	BNAD_RXBUF_MULTI_BUFF	= 3
};

#define BNAD_RXBUF_IS_SK_BUFF(_type)	((_type) == BNAD_RXBUF_SK_BUFF)
#define BNAD_RXBUF_IS_MULTI_BUFF(_type)	((_type) == BNAD_RXBUF_MULTI_BUFF)

struct bnad_rx_unmap_q {
	int			reuse_pi;
	int			alloc_order;
	u32			map_size;
	enum bnad_rxbuf_type	type;
	struct bnad_rx_unmap	unmap[0] ____cacheline_aligned;
};

#define BNAD_PCI_DEV_IS_CAT2(_bnad) \
	((_bnad)->pcidev->device == BFA_PCI_DEVICE_ID_CT2)

/* Bit mask values for bnad->cfg_flags */
#define	BNAD_CF_DIM_ENABLED		0x01	/* DIM */
#define	BNAD_CF_PROMISC			0x02
#define BNAD_CF_ALLMULTI		0x04
#define	BNAD_CF_DEFAULT			0x08
#define	BNAD_CF_MSIX			0x10	/* If in MSIx mode */

/* Defines for run_flags bit-mask */
/* Set, tested & cleared using xxx_bit() functions */
/* Values indicated bit positions */
#define BNAD_RF_CEE_RUNNING		0
#define BNAD_RF_MTU_SET		1
#define BNAD_RF_MBOX_IRQ_DISABLED	2
#define BNAD_RF_NETDEV_REGISTERED	3
#define BNAD_RF_DIM_TIMER_RUNNING	4
#define BNAD_RF_STATS_TIMER_RUNNING	5
#define BNAD_RF_TX_PRIO_SET		6

struct bnad {
	struct net_device	*netdev;
	u32			id;
	struct list_head	list_entry;

	/* Data path */
	struct bnad_tx_info tx_info[BNAD_MAX_TX];
	struct bnad_rx_info rx_info[BNAD_MAX_RX];

	unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
	/*
	 * These q numbers are global only because
	 * they are used to calculate MSIx vectors.
	 * Actually the exact # of queues are per Tx/Rx
	 * object.
	 */
	u32		num_tx;
	u32		num_rx;
	u32		num_txq_per_tx;
	u32		num_rxp_per_rx;

	u32		txq_depth;
	u32		rxq_depth;

	u8			tx_coalescing_timeo;
	u8			rx_coalescing_timeo;

	struct bna_rx_config rx_config[BNAD_MAX_RX] ____cacheline_aligned;
	struct bna_tx_config tx_config[BNAD_MAX_TX] ____cacheline_aligned;

	void __iomem		*bar0;	/* BAR0 address */

	struct bna bna;

	u32		cfg_flags;
	unsigned long		run_flags;

	struct pci_dev		*pcidev;
	u64		mmio_start;
	u64		mmio_len;

	u32		msix_num;
	struct msix_entry	*msix_table;

	struct mutex		conf_mutex;
	spinlock_t		bna_lock ____cacheline_aligned;

	/* Timers */
	struct timer_list	ioc_timer;
	struct timer_list	dim_timer;
	struct timer_list	stats_timer;

	/* Control path resources, memory & irq */
	struct bna_res_info res_info[BNA_RES_T_MAX];
	struct bna_res_info mod_res_info[BNA_MOD_RES_T_MAX];
	struct bnad_tx_res_info tx_res_info[BNAD_MAX_TX];
	struct bnad_rx_res_info rx_res_info[BNAD_MAX_RX];

	struct bnad_completion bnad_completions;

	/* Burnt in MAC address */
	u8			perm_addr[ETH_ALEN];

	struct workqueue_struct *work_q;

	/* Statistics */
	struct bnad_stats stats;

	struct bnad_diag *diag;

	char			adapter_name[BNAD_NAME_LEN];
	char			port_name[BNAD_NAME_LEN];
	char			mbox_irq_name[BNAD_NAME_LEN];
	char			wq_name[BNAD_NAME_LEN];

	/* debugfs specific data */
	char	*regdata;
	u32	reglen;
	struct dentry *bnad_dentry_files[5];
	struct dentry *port_debugfs_root;
};

struct bnad_drvinfo {
	struct bfa_ioc_attr  ioc_attr;
	struct bfa_cee_attr  cee_attr;
	struct bfa_flash_attr flash_attr;
	u32	cee_status;
	u32	flash_status;
};

/*
 * EXTERN VARIABLES
 */
extern const struct firmware *bfi_fw;

/*
 * EXTERN PROTOTYPES
 */
u32 *cna_get_firmware_buf(struct pci_dev *pdev);
/* Netdev entry point prototypes */
void bnad_set_rx_mode(struct net_device *netdev);
struct net_device_stats *bnad_get_netdev_stats(struct net_device *netdev);
int bnad_mac_addr_set_locked(struct bnad *bnad, const u8 *mac_addr);
int bnad_enable_default_bcast(struct bnad *bnad);
void bnad_restore_vlans(struct bnad *bnad, u32 rx_id);
void bnad_set_ethtool_ops(struct net_device *netdev);
void bnad_cb_completion(void *arg, enum bfa_status status);

/* Configuration & setup */
void bnad_tx_coalescing_timeo_set(struct bnad *bnad);
void bnad_rx_coalescing_timeo_set(struct bnad *bnad);

int bnad_setup_rx(struct bnad *bnad, u32 rx_id);
int bnad_setup_tx(struct bnad *bnad, u32 tx_id);
void bnad_destroy_tx(struct bnad *bnad, u32 tx_id);
void bnad_destroy_rx(struct bnad *bnad, u32 rx_id);

/* Timer start/stop protos */
void bnad_dim_timer_start(struct bnad *bnad);

/* Statistics */
void bnad_netdev_qstats_fill(struct bnad *bnad,
			     struct rtnl_link_stats64 *stats);
void bnad_netdev_hwstats_fill(struct bnad *bnad,
			      struct rtnl_link_stats64 *stats);

/* Debugfs */
void bnad_debugfs_init(struct bnad *bnad);
void bnad_debugfs_uninit(struct bnad *bnad);

/* MACROS */
/* To set & get the stats counters */
#define BNAD_UPDATE_CTR(_bnad, _ctr)				\
				(((_bnad)->stats.drv_stats._ctr)++)

#define BNAD_GET_CTR(_bnad, _ctr) ((_bnad)->stats.drv_stats._ctr)

#define bnad_enable_rx_irq_unsafe(_ccb)			\
{							\
	if (likely(test_bit(BNAD_RXQ_STARTED, &(_ccb)->rcb[0]->flags))) {\
		bna_ib_coalescing_timer_set((_ccb)->i_dbell,	\
			(_ccb)->rx_coalescing_timeo);		\
		bna_ib_ack((_ccb)->i_dbell, 0);			\
	}							\
}

#endif /* __BNAD_H__ */
Commit	Line	Data
8b230ed8	1	/*
2732ba56	2	* Linux network driver for QLogic BR-series Converged Network Adapter.
8b230ed8 RM	3	*
	4	* This program is free software; you can redistribute it and/or modify it
	5	* under the terms of the GNU General Public License (GPL) Version 2 as
	6	* published by the Free Software Foundation
	7	*
	8	* This program is distributed in the hope that it will be useful, but
	9	* WITHOUT ANY WARRANTY; without even the implied warranty of
	10	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	11	* General Public License for more details.
	12	*/
	13	/*
2732ba56 RM	14	* Copyright (c) 2005-2014 Brocade Communications Systems, Inc.
2732ba56 RM	15	* Copyright (c) 2014-2015 QLogic Corporation
8b230ed8	16	* All rights reserved
2732ba56	17	* www.qlogic.com
8b230ed8 RM	18	*/
	19	#ifndef __BNAD_H__
	20	#define __BNAD_H__
	21
	22	#include <linux/rtnetlink.h>
	23	#include <linux/workqueue.h>
	24	#include <linux/ipv6.h>
	25	#include <linux/etherdevice.h>
	26	#include <linux/mutex.h>
	27	#include <linux/firmware.h>
f859d7cb	28	#include <linux/if_vlan.h>
8b230ed8 RM	29
	30	/* Fix for IA64 */
	31	#include <asm/checksum.h>
	32	#include <net/ip6_checksum.h>
	33
	34	#include <net/ip.h>
	35	#include <net/tcp.h>
	36
	37	#include "bna.h"
	38
	39	#define BNAD_TXQ_DEPTH 2048
	40	#define BNAD_RXQ_DEPTH 2048
	41
772b5235	42	#define BNAD_MAX_TX 1
8b230ed8 RM	43	#define BNAD_MAX_TXQ_PER_TX 8 /* 8 priority queues */
	44	#define BNAD_TXQ_NUM 1
	45
772b5235 RM	46	#define BNAD_MAX_RX 1
772b5235 RM	47	#define BNAD_MAX_RXP_PER_RX 16
078086f3	48	#define BNAD_MAX_RXQ_PER_RXP 2
8b230ed8 RM	49
	50	/*
	51	* Control structure pointed to ccb->ctrl, which
	52	* determines the NAPI / LRO behavior CCB
	53	* There is 1:1 corres. between ccb & ctrl
	54	*/
	55	struct bnad_rx_ctrl {
	56	struct bna_ccb *ccb;
2be67144	57	struct bnad *bnad;
be7fa326	58	unsigned long flags;
8b230ed8	59	struct napi_struct napi;
271e8b79 RM	60	u64 rx_intr_ctr;
	61	u64 rx_poll_ctr;
	62	u64 rx_schedule;
	63	u64 rx_keep_poll;
	64	u64 rx_complete;
8b230ed8 RM	65	};
	66
	67	#define BNAD_RXMODE_PROMISC_DEFAULT BNA_RXMODE_PROMISC
	68
8b230ed8 RM	69	/*
	70	* GLOBAL #defines (CONSTANTS)
	71	*/
	72	#define BNAD_NAME "bna"
	73	#define BNAD_NAME_LEN 64
	74
3f307c3d	75	#define BNAD_VERSION "3.2.25.1"
8b230ed8	76
8811e267	77	#define BNAD_MAILBOX_MSIX_INDEX 0
8b230ed8	78	#define BNAD_MAILBOX_MSIX_VECTORS 1
8811e267 RM	79	#define BNAD_INTX_TX_IB_BITMASK 0x1
8811e267 RM	80	#define BNAD_INTX_RX_IB_BITMASK 0x2
8b230ed8	81
0120b99c RM	82	#define BNAD_STATS_TIMER_FREQ 1000 /* in msecs */
0120b99c RM	83	#define BNAD_DIM_TIMER_FREQ 1000 /* in msecs */
8b230ed8	84
078086f3 RM	85	#define BNAD_IOCETH_TIMEOUT 10000
078086f3 RM	86
5216562a	87	#define BNAD_MIN_Q_DEPTH 512
66f9513a	88	#define BNAD_MAX_RXQ_DEPTH 16384
5216562a	89	#define BNAD_MAX_TXQ_DEPTH 2048
41eb5ba4	90
8b230ed8 RM	91	#define BNAD_JUMBO_MTU 9000
	92
	93	#define BNAD_NETIF_WAKE_THRESHOLD 8
	94
	95	#define BNAD_RXQ_REFILL_THRESHOLD_SHIFT 3
	96
	97	/* Bit positions for tcb->flags */
	98	#define BNAD_TXQ_FREE_SENT 0
be7fa326	99	#define BNAD_TXQ_TX_STARTED 1
8b230ed8 RM	100
8b230ed8 RM	101	/* Bit positions for rcb->flags */
5216562a RM	102	#define BNAD_RXQ_STARTED 0
5216562a RM	103	#define BNAD_RXQ_POST_OK 1
8b230ed8	104
078086f3 RM	105	/* Resource limits */
	106	#define BNAD_NUM_TXQ (bnad->num_tx * bnad->num_txq_per_tx)
	107	#define BNAD_NUM_RXP (bnad->num_rx * bnad->num_rxp_per_rx)
	108
e29aa339 RM	109	#define BNAD_FRAME_SIZE(_mtu) \
	110	(ETH_HLEN + VLAN_HLEN + (_mtu) + ETH_FCS_LEN)
	111
8b230ed8 RM	112	/*
	113	* DATA STRUCTURES
	114	*/
	115
	116	/* enums */
	117	enum bnad_intr_source {
	118	BNAD_INTR_TX = 1,
	119	BNAD_INTR_RX = 2
	120	};
	121
	122	enum bnad_link_state {
	123	BNAD_LS_DOWN = 0,
0120b99c	124	BNAD_LS_UP = 1
8b230ed8 RM	125	};
8b230ed8 RM	126
72a9730b KG	127	struct bnad_iocmd_comp {
	128	struct bnad *bnad;
	129	struct completion comp;
	130	int comp_status;
	131	};
	132
8b230ed8	133	struct bnad_completion {
0120b99c RM	134	struct completion ioc_comp;
0120b99c RM	135	struct completion ucast_comp;
8b230ed8 RM	136	struct completion mcast_comp;
	137	struct completion tx_comp;
	138	struct completion rx_comp;
	139	struct completion stats_comp;
078086f3 RM	140	struct completion enet_comp;
078086f3 RM	141	struct completion mtu_comp;
8b230ed8 RM	142
	143	u8 ioc_comp_status;
	144	u8 ucast_comp_status;
	145	u8 mcast_comp_status;
	146	u8 tx_comp_status;
	147	u8 rx_comp_status;
	148	u8 stats_comp_status;
	149	u8 port_comp_status;
078086f3	150	u8 mtu_comp_status;
8b230ed8 RM	151	};
	152
	153	/* Tx Rx Control Stats */
	154	struct bnad_drv_stats {
0120b99c	155	u64 netif_queue_stop;
8b230ed8	156	u64 netif_queue_wakeup;
f7c0fa4c	157	u64 netif_queue_stopped;
8b230ed8 RM	158	u64 tso4;
	159	u64 tso6;
	160	u64 tso_err;
	161	u64 tcpcsum_offload;
	162	u64 udpcsum_offload;
	163	u64 csum_help;
271e8b79 RM	164	u64 tx_skb_too_short;
	165	u64 tx_skb_stopping;
	166	u64 tx_skb_max_vectors;
	167	u64 tx_skb_mss_too_long;
	168	u64 tx_skb_tso_too_short;
	169	u64 tx_skb_tso_prepare;
	170	u64 tx_skb_non_tso_too_long;
	171	u64 tx_skb_tcp_hdr;
	172	u64 tx_skb_udp_hdr;
	173	u64 tx_skb_csum_err;
	174	u64 tx_skb_headlen_too_long;
	175	u64 tx_skb_headlen_zero;
	176	u64 tx_skb_frag_zero;
	177	u64 tx_skb_len_mismatch;
8b230ed8 RM	178
8b230ed8 RM	179	u64 hw_stats_updates;
8b230ed8 RM	180	u64 netif_rx_dropped;
	181
	182	u64 link_toggle;
078086f3	183	u64 cee_toggle;
8b230ed8 RM	184
	185	u64 rxp_info_alloc_failed;
	186	u64 mbox_intr_disabled;
	187	u64 mbox_intr_enabled;
	188	u64 tx_unmap_q_alloc_failed;
	189	u64 rx_unmap_q_alloc_failed;
	190
	191	u64 rxbuf_alloc_failed;
	192	};
	193
	194	/* Complete driver stats */
	195	struct bnad_stats {
	196	struct bnad_drv_stats drv_stats;
	197	struct bna_stats *bna_stats;
	198	};
	199
	200	/* Tx / Rx Resources */
	201	struct bnad_tx_res_info {
	202	struct bna_res_info res_info[BNA_TX_RES_T_MAX];
	203	};
	204
	205	struct bnad_rx_res_info {
	206	struct bna_res_info res_info[BNA_RX_RES_T_MAX];
	207	};
	208
	209	struct bnad_tx_info {
	210	struct bna_tx tx; / 1:1 between tx_info & tx */
	211	struct bna_tcb *tcb[BNAD_MAX_TXQ_PER_TX];
078086f3	212	u32 tx_id;
01b54b14	213	struct delayed_work tx_cleanup_work;
8b230ed8 RM	214	} ____cacheline_aligned;
	215
	216	struct bnad_rx_info {
	217	struct bna_rx rx; / 1:1 between rx_info & rx */
	218
772b5235	219	struct bnad_rx_ctrl rx_ctrl[BNAD_MAX_RXP_PER_RX];
078086f3	220	u32 rx_id;
01b54b14	221	struct work_struct rx_cleanup_work;
8b230ed8 RM	222	} ____cacheline_aligned;
8b230ed8 RM	223
5216562a RM	224	struct bnad_tx_vector {
5216562a RM	225	DEFINE_DMA_UNMAP_ADDR(dma_addr);
24f5d33d	226	DEFINE_DMA_UNMAP_LEN(dma_len);
5216562a RM	227	};
	228
	229	struct bnad_tx_unmap {
8b230ed8	230	struct sk_buff *skb;
5216562a RM	231	u32 nvecs;
	232	struct bnad_tx_vector vectors[BFI_TX_MAX_VECTORS_PER_WI];
	233	};
	234
	235	struct bnad_rx_vector {
5ea74318	236	DEFINE_DMA_UNMAP_ADDR(dma_addr);
5216562a	237	u32 len;
8b230ed8 RM	238	};
8b230ed8 RM	239
5216562a	240	struct bnad_rx_unmap {
30f9fc94	241	struct page *page;
5216562a RM	242	struct sk_buff *skb;
5216562a RM	243	struct bnad_rx_vector vector;
66f9513a	244	u32 page_offset;
8b230ed8 RM	245	};
8b230ed8 RM	246
30f9fc94 RM	247	enum bnad_rxbuf_type {
30f9fc94 RM	248	BNAD_RXBUF_NONE = 0,
e29aa339	249	BNAD_RXBUF_SK_BUFF = 1,
30f9fc94	250	BNAD_RXBUF_PAGE = 2,
e29aa339	251	BNAD_RXBUF_MULTI_BUFF = 3
30f9fc94 RM	252	};
30f9fc94 RM	253
e29aa339 RM	254	#define BNAD_RXBUF_IS_SK_BUFF(_type) ((_type) == BNAD_RXBUF_SK_BUFF)
e29aa339 RM	255	#define BNAD_RXBUF_IS_MULTI_BUFF(_type) ((_type) == BNAD_RXBUF_MULTI_BUFF)
30f9fc94 RM	256
	257	struct bnad_rx_unmap_q {
	258	int reuse_pi;
	259	int alloc_order;
	260	u32 map_size;
	261	enum bnad_rxbuf_type type;
66f9513a	262	struct bnad_rx_unmap unmap[0] ____cacheline_aligned;
30f9fc94 RM	263	};
30f9fc94 RM	264
e29aa339 RM	265	#define BNAD_PCI_DEV_IS_CAT2(_bnad) \
	266	((_bnad)->pcidev->device == BFA_PCI_DEVICE_ID_CT2)
	267
8b230ed8 RM	268	/* Bit mask values for bnad->cfg_flags */
	269	#define BNAD_CF_DIM_ENABLED 0x01 /* DIM */
	270	#define BNAD_CF_PROMISC 0x02
	271	#define BNAD_CF_ALLMULTI 0x04
fe1624cf RM	272	#define BNAD_CF_DEFAULT 0x08
fe1624cf RM	273	#define BNAD_CF_MSIX 0x10 /* If in MSIx mode */
8b230ed8 RM	274
	275	/* Defines for run_flags bit-mask */
	276	/* Set, tested & cleared using xxx_bit() functions */
	277	/* Values indicated bit positions */
078086f3 RM	278	#define BNAD_RF_CEE_RUNNING 0
078086f3 RM	279	#define BNAD_RF_MTU_SET 1
be7fa326	280	#define BNAD_RF_MBOX_IRQ_DISABLED 2
078086f3	281	#define BNAD_RF_NETDEV_REGISTERED 3
be7fa326 RM	282	#define BNAD_RF_DIM_TIMER_RUNNING 4
be7fa326 RM	283	#define BNAD_RF_STATS_TIMER_RUNNING 5
078086f3 RM	284	#define BNAD_RF_TX_PRIO_SET 6
078086f3 RM	285
8b230ed8	286	struct bnad {
0120b99c	287	struct net_device *netdev;
72a9730b KG	288	u32 id;
72a9730b KG	289	struct list_head list_entry;
8b230ed8 RM	290
8b230ed8 RM	291	/* Data path */
772b5235 RM	292	struct bnad_tx_info tx_info[BNAD_MAX_TX];
772b5235 RM	293	struct bnad_rx_info rx_info[BNAD_MAX_RX];
8b230ed8	294
f859d7cb	295	unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
8b230ed8 RM	296	/*
	297	* These q numbers are global only because
	298	* they are used to calculate MSIx vectors.
	299	* Actually the exact # of queues are per Tx/Rx
	300	* object.
	301	*/
	302	u32 num_tx;
	303	u32 num_rx;
	304	u32 num_txq_per_tx;
	305	u32 num_rxp_per_rx;
	306
	307	u32 txq_depth;
	308	u32 rxq_depth;
	309
	310	u8 tx_coalescing_timeo;
	311	u8 rx_coalescing_timeo;
	312
5e46631f RM	313	struct bna_rx_config rx_config[BNAD_MAX_RX] ____cacheline_aligned;
5e46631f RM	314	struct bna_tx_config tx_config[BNAD_MAX_TX] ____cacheline_aligned;
8b230ed8	315
8b230ed8 RM	316	void __iomem bar0; / BAR0 address */
	317
	318	struct bna bna;
	319
	320	u32 cfg_flags;
	321	unsigned long run_flags;
	322
0120b99c	323	struct pci_dev *pcidev;
8b230ed8 RM	324	u64 mmio_start;
	325	u64 mmio_len;
	326
	327	u32 msix_num;
8b230ed8 RM	328	struct msix_entry *msix_table;
	329
	330	struct mutex conf_mutex;
	331	spinlock_t bna_lock ____cacheline_aligned;
	332
	333	/* Timers */
	334	struct timer_list ioc_timer;
	335	struct timer_list dim_timer;
	336	struct timer_list stats_timer;
	337
	338	/* Control path resources, memory & irq */
	339	struct bna_res_info res_info[BNA_RES_T_MAX];
078086f3	340	struct bna_res_info mod_res_info[BNA_MOD_RES_T_MAX];
772b5235 RM	341	struct bnad_tx_res_info tx_res_info[BNAD_MAX_TX];
772b5235 RM	342	struct bnad_rx_res_info rx_res_info[BNAD_MAX_RX];
8b230ed8 RM	343
	344	struct bnad_completion bnad_completions;
	345
	346	/* Burnt in MAC address */
d6b30598	347	u8 perm_addr[ETH_ALEN];
8b230ed8	348
01b54b14	349	struct workqueue_struct *work_q;
8b230ed8 RM	350
	351	/* Statistics */
	352	struct bnad_stats stats;
8b230ed8 RM	353
	354	struct bnad_diag *diag;
	355
	356	char adapter_name[BNAD_NAME_LEN];
0120b99c	357	char port_name[BNAD_NAME_LEN];
8b230ed8	358	char mbox_irq_name[BNAD_NAME_LEN];
01b54b14	359	char wq_name[BNAD_NAME_LEN];
7afc5dbd KG	360
	361	/* debugfs specific data */
	362	char *regdata;
	363	u32 reglen;
	364	struct dentry *bnad_dentry_files[5];
	365	struct dentry *port_debugfs_root;
	366	};
	367
	368	struct bnad_drvinfo {
	369	struct bfa_ioc_attr ioc_attr;
	370	struct bfa_cee_attr cee_attr;
	371	struct bfa_flash_attr flash_attr;
	372	u32 cee_status;
	373	u32 flash_status;
8b230ed8 RM	374	};
	375
	376	/*
	377	* EXTERN VARIABLES
	378	*/
e1e0918f	379	extern const struct firmware *bfi_fw;
8b230ed8 RM	380
	381	/*
	382	* EXTERN PROTOTYPES
	383	*/
49ca19bd	384	u32 cna_get_firmware_buf(struct pci_dev pdev);
8b230ed8	385	/* Netdev entry point prototypes */
49ca19bd JP	386	void bnad_set_rx_mode(struct net_device *netdev);
49ca19bd JP	387	struct net_device_stats bnad_get_netdev_stats(struct net_device netdev);
558caad7	388	int bnad_mac_addr_set_locked(struct bnad bnad, const u8 mac_addr);
49ca19bd JP	389	int bnad_enable_default_bcast(struct bnad *bnad);
	390	void bnad_restore_vlans(struct bnad *bnad, u32 rx_id);
	391	void bnad_set_ethtool_ops(struct net_device *netdev);
	392	void bnad_cb_completion(void *arg, enum bfa_status status);
8b230ed8 RM	393
8b230ed8 RM	394	/* Configuration & setup */
49ca19bd JP	395	void bnad_tx_coalescing_timeo_set(struct bnad *bnad);
49ca19bd JP	396	void bnad_rx_coalescing_timeo_set(struct bnad *bnad);
8b230ed8	397
49ca19bd JP	398	int bnad_setup_rx(struct bnad *bnad, u32 rx_id);
	399	int bnad_setup_tx(struct bnad *bnad, u32 tx_id);
	400	void bnad_destroy_tx(struct bnad *bnad, u32 tx_id);
	401	void bnad_destroy_rx(struct bnad *bnad, u32 rx_id);
8b230ed8 RM	402
8b230ed8 RM	403	/* Timer start/stop protos */
49ca19bd	404	void bnad_dim_timer_start(struct bnad *bnad);
8b230ed8 RM	405
8b230ed8 RM	406	/* Statistics */
49ca19bd JP	407	void bnad_netdev_qstats_fill(struct bnad *bnad,
	408	struct rtnl_link_stats64 *stats);
	409	void bnad_netdev_hwstats_fill(struct bnad *bnad,
	410	struct rtnl_link_stats64 *stats);
8b230ed8	411
7afc5dbd	412	/* Debugfs */
49ca19bd JP	413	void bnad_debugfs_init(struct bnad *bnad);
49ca19bd JP	414	void bnad_debugfs_uninit(struct bnad *bnad);
7afc5dbd	415
1aa8b471	416	/* MACROS */
8b230ed8 RM	417	/* To set & get the stats counters */
	418	#define BNAD_UPDATE_CTR(_bnad, _ctr) \
	419	(((_bnad)->stats.drv_stats._ctr)++)
	420
	421	#define BNAD_GET_CTR(_bnad, _ctr) ((_bnad)->stats.drv_stats._ctr)
	422
	423	#define bnad_enable_rx_irq_unsafe(_ccb) \
	424	{ \
271e8b79	425	if (likely(test_bit(BNAD_RXQ_STARTED, &(_ccb)->rcb[0]->flags))) {\
be7fa326 RM	426	bna_ib_coalescing_timer_set((_ccb)->i_dbell, \
	427	(_ccb)->rx_coalescing_timeo); \
	428	bna_ib_ack((_ccb)->i_dbell, 0); \
	429	} \
8b230ed8 RM	430	}
8b230ed8 RM	431
8b230ed8	432	#endif /* __BNAD_H__ */