[deliverable/linux.git] / drivers / net / ethernet / brocade / bna / bnad.h

/*
 * Linux network driver for Brocade Converged Network Adapter.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License (GPL) Version 2 as
 * published by the Free Software Foundation
 *
 * This program is distributed in the hope that it will be useful, but
 * WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * General Public License for more details.
 */
/*
 * Copyright (c) 2005-2010 Brocade Communications Systems, Inc.
 * All rights reserved
 * www.brocade.com
 */
#ifndef __BNAD_H__
#define __BNAD_H__

#include <linux/rtnetlink.h>
#include <linux/workqueue.h>
#include <linux/ipv6.h>
#include <linux/etherdevice.h>
#include <linux/mutex.h>
#include <linux/firmware.h>
#include <linux/if_vlan.h>

/* Fix for IA64 */
#include <asm/checksum.h>
#include <net/ip6_checksum.h>

#include <net/ip.h>
#include <net/tcp.h>

#include "bna.h"

#define BNAD_TXQ_DEPTH		2048
#define BNAD_RXQ_DEPTH		2048

#define BNAD_MAX_TX		1
#define BNAD_MAX_TXQ_PER_TX	8	/* 8 priority queues */
#define BNAD_TXQ_NUM		1

#define BNAD_MAX_RX		1
#define BNAD_MAX_RXP_PER_RX	16
#define BNAD_MAX_RXQ_PER_RXP	2

/*
 * Control structure pointed to ccb->ctrl, which
 * determines the NAPI / LRO behavior CCB
 * There is 1:1 corres. between ccb & ctrl
 */
struct bnad_rx_ctrl {
	struct bna_ccb *ccb;
	struct bnad *bnad;
	unsigned long  flags;
	struct napi_struct	napi;
	u64		rx_intr_ctr;
	u64		rx_poll_ctr;
	u64		rx_schedule;
	u64		rx_keep_poll;
	u64		rx_complete;
};

#define BNAD_RXMODE_PROMISC_DEFAULT	BNA_RXMODE_PROMISC

/*
 * GLOBAL #defines (CONSTANTS)
 */
#define BNAD_NAME			"bna"
#define BNAD_NAME_LEN			64

#define BNAD_VERSION			"3.0.2.0"

#define BNAD_MAILBOX_MSIX_INDEX		0
#define BNAD_MAILBOX_MSIX_VECTORS	1
#define BNAD_INTX_TX_IB_BITMASK		0x1
#define BNAD_INTX_RX_IB_BITMASK		0x2

#define BNAD_STATS_TIMER_FREQ		1000	/* in msecs */
#define BNAD_DIM_TIMER_FREQ		1000	/* in msecs */

#define BNAD_IOCETH_TIMEOUT	     10000

#define BNAD_MAX_Q_DEPTH		0x10000
#define BNAD_MIN_Q_DEPTH		0x200

#define BNAD_JUMBO_MTU			9000

#define BNAD_NETIF_WAKE_THRESHOLD	8

#define BNAD_RXQ_REFILL_THRESHOLD_SHIFT	3

/* Bit positions for tcb->flags */
#define BNAD_TXQ_FREE_SENT		0
#define BNAD_TXQ_TX_STARTED		1

/* Bit positions for rcb->flags */
#define BNAD_RXQ_REFILL			0
#define BNAD_RXQ_STARTED		1

/* Resource limits */
#define BNAD_NUM_TXQ			(bnad->num_tx * bnad->num_txq_per_tx)
#define BNAD_NUM_RXP			(bnad->num_rx * bnad->num_rxp_per_rx)

/*
 * DATA STRUCTURES
 */

/* enums */
enum bnad_intr_source {
	BNAD_INTR_TX		= 1,
	BNAD_INTR_RX		= 2
};

enum bnad_link_state {
	BNAD_LS_DOWN		= 0,
	BNAD_LS_UP		= 1
};

struct bnad_completion {
	struct completion	ioc_comp;
	struct completion	ucast_comp;
	struct completion	mcast_comp;
	struct completion	tx_comp;
	struct completion	rx_comp;
	struct completion	stats_comp;
	struct completion	enet_comp;
	struct completion	mtu_comp;

	u8			ioc_comp_status;
	u8			ucast_comp_status;
	u8			mcast_comp_status;
	u8			tx_comp_status;
	u8			rx_comp_status;
	u8			stats_comp_status;
	u8			port_comp_status;
	u8			mtu_comp_status;
};

/* Tx Rx Control Stats */
struct bnad_drv_stats {
	u64		netif_queue_stop;
	u64		netif_queue_wakeup;
	u64		netif_queue_stopped;
	u64		tso4;
	u64		tso6;
	u64		tso_err;
	u64		tcpcsum_offload;
	u64		udpcsum_offload;
	u64		csum_help;
	u64		tx_skb_too_short;
	u64		tx_skb_stopping;
	u64		tx_skb_max_vectors;
	u64		tx_skb_mss_too_long;
	u64		tx_skb_tso_too_short;
	u64		tx_skb_tso_prepare;
	u64		tx_skb_non_tso_too_long;
	u64		tx_skb_tcp_hdr;
	u64		tx_skb_udp_hdr;
	u64		tx_skb_csum_err;
	u64		tx_skb_headlen_too_long;
	u64		tx_skb_headlen_zero;
	u64		tx_skb_frag_zero;
	u64		tx_skb_len_mismatch;

	u64		hw_stats_updates;
	u64		netif_rx_dropped;

	u64		link_toggle;
	u64		cee_toggle;

	u64		rxp_info_alloc_failed;
	u64		mbox_intr_disabled;
	u64		mbox_intr_enabled;
	u64		tx_unmap_q_alloc_failed;
	u64		rx_unmap_q_alloc_failed;

	u64		rxbuf_alloc_failed;
};

/* Complete driver stats */
struct bnad_stats {
	struct bnad_drv_stats drv_stats;
	struct bna_stats *bna_stats;
};

/* Tx / Rx Resources */
struct bnad_tx_res_info {
	struct bna_res_info res_info[BNA_TX_RES_T_MAX];
};

struct bnad_rx_res_info {
	struct bna_res_info res_info[BNA_RX_RES_T_MAX];
};

struct bnad_tx_info {
	struct bna_tx *tx; /* 1:1 between tx_info & tx */
	struct bna_tcb *tcb[BNAD_MAX_TXQ_PER_TX];
	u32 tx_id;
} ____cacheline_aligned;

struct bnad_rx_info {
	struct bna_rx *rx; /* 1:1 between rx_info & rx */

	struct bnad_rx_ctrl rx_ctrl[BNAD_MAX_RXP_PER_RX];
	u32 rx_id;
} ____cacheline_aligned;

/* Unmap queues for Tx / Rx cleanup */
struct bnad_skb_unmap {
	struct sk_buff		*skb;
	DEFINE_DMA_UNMAP_ADDR(dma_addr);
};

struct bnad_unmap_q {
	u32		producer_index;
	u32		consumer_index;
	u32		q_depth;
	/* This should be the last one */
	struct bnad_skb_unmap unmap_array[1];
};

/* Bit mask values for bnad->cfg_flags */
#define	BNAD_CF_DIM_ENABLED		0x01	/* DIM */
#define	BNAD_CF_PROMISC			0x02
#define BNAD_CF_ALLMULTI		0x04
#define	BNAD_CF_MSIX			0x08	/* If in MSIx mode */

/* Defines for run_flags bit-mask */
/* Set, tested & cleared using xxx_bit() functions */
/* Values indicated bit positions */
#define BNAD_RF_CEE_RUNNING		0
#define BNAD_RF_MTU_SET		1
#define BNAD_RF_MBOX_IRQ_DISABLED	2
#define BNAD_RF_NETDEV_REGISTERED	3
#define BNAD_RF_DIM_TIMER_RUNNING	4
#define BNAD_RF_STATS_TIMER_RUNNING	5
#define BNAD_RF_TX_PRIO_SET		6


/* Define for Fast Path flags */
/* Defined as bit positions */
#define BNAD_FP_IN_RX_PATH	      0

struct bnad {
	struct net_device	*netdev;

	/* Data path */
	struct bnad_tx_info tx_info[BNAD_MAX_TX];
	struct bnad_rx_info rx_info[BNAD_MAX_RX];

	unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
	/*
	 * These q numbers are global only because
	 * they are used to calculate MSIx vectors.
	 * Actually the exact # of queues are per Tx/Rx
	 * object.
	 */
	u32		num_tx;
	u32		num_rx;
	u32		num_txq_per_tx;
	u32		num_rxp_per_rx;

	u32		txq_depth;
	u32		rxq_depth;

	u8			tx_coalescing_timeo;
	u8			rx_coalescing_timeo;

	struct bna_rx_config rx_config[BNAD_MAX_RX];
	struct bna_tx_config tx_config[BNAD_MAX_TX];

	void __iomem		*bar0;	/* BAR0 address */

	struct bna bna;

	u32		cfg_flags;
	unsigned long		run_flags;

	struct pci_dev		*pcidev;
	u64		mmio_start;
	u64		mmio_len;

	u32		msix_num;
	struct msix_entry	*msix_table;

	struct mutex		conf_mutex;
	spinlock_t		bna_lock ____cacheline_aligned;

	/* Timers */
	struct timer_list	ioc_timer;
	struct timer_list	dim_timer;
	struct timer_list	stats_timer;

	/* Control path resources, memory & irq */
	struct bna_res_info res_info[BNA_RES_T_MAX];
	struct bna_res_info mod_res_info[BNA_MOD_RES_T_MAX];
	struct bnad_tx_res_info tx_res_info[BNAD_MAX_TX];
	struct bnad_rx_res_info rx_res_info[BNAD_MAX_RX];

	struct bnad_completion bnad_completions;

	/* Burnt in MAC address */
	mac_t			perm_addr;

	struct tasklet_struct	tx_free_tasklet;

	/* Statistics */
	struct bnad_stats stats;

	struct bnad_diag *diag;

	char			adapter_name[BNAD_NAME_LEN];
	char			port_name[BNAD_NAME_LEN];
	char			mbox_irq_name[BNAD_NAME_LEN];
};

/*
 * EXTERN VARIABLES
 */
extern struct firmware *bfi_fw;
extern u32		bnad_rxqs_per_cq;

/*
 * EXTERN PROTOTYPES
 */
extern u32 *cna_get_firmware_buf(struct pci_dev *pdev);
/* Netdev entry point prototypes */
extern void bnad_set_rx_mode(struct net_device *netdev);
extern struct net_device_stats *bnad_get_netdev_stats(
				struct net_device *netdev);
extern int bnad_mac_addr_set_locked(struct bnad *bnad, u8 *mac_addr);
extern int bnad_enable_default_bcast(struct bnad *bnad);
extern void bnad_restore_vlans(struct bnad *bnad, u32 rx_id);
extern void bnad_set_ethtool_ops(struct net_device *netdev);

/* Configuration & setup */
extern void bnad_tx_coalescing_timeo_set(struct bnad *bnad);
extern void bnad_rx_coalescing_timeo_set(struct bnad *bnad);

extern int bnad_setup_rx(struct bnad *bnad, u32 rx_id);
extern int bnad_setup_tx(struct bnad *bnad, u32 tx_id);
extern void bnad_cleanup_tx(struct bnad *bnad, u32 tx_id);
extern void bnad_cleanup_rx(struct bnad *bnad, u32 rx_id);

/* Timer start/stop protos */
extern void bnad_dim_timer_start(struct bnad *bnad);

/* Statistics */
extern void bnad_netdev_qstats_fill(struct bnad *bnad,
		struct rtnl_link_stats64 *stats);
extern void bnad_netdev_hwstats_fill(struct bnad *bnad,
		struct rtnl_link_stats64 *stats);

/**
 * MACROS
 */
/* To set & get the stats counters */
#define BNAD_UPDATE_CTR(_bnad, _ctr)				\
				(((_bnad)->stats.drv_stats._ctr)++)

#define BNAD_GET_CTR(_bnad, _ctr) ((_bnad)->stats.drv_stats._ctr)

#define bnad_enable_rx_irq_unsafe(_ccb)			\
{							\
	if (likely(test_bit(BNAD_RXQ_STARTED, &(_ccb)->rcb[0]->flags))) {\
		bna_ib_coalescing_timer_set((_ccb)->i_dbell,	\
			(_ccb)->rx_coalescing_timeo);		\
		bna_ib_ack((_ccb)->i_dbell, 0);			\
	}							\
}

#endif /* __BNAD_H__ */
Commit	Line	Data
8b230ed8 RM	1	/*
	2	* Linux network driver for Brocade Converged Network Adapter.
	3	*
	4	* This program is free software; you can redistribute it and/or modify it
	5	* under the terms of the GNU General Public License (GPL) Version 2 as
	6	* published by the Free Software Foundation
	7	*
	8	* This program is distributed in the hope that it will be useful, but
	9	* WITHOUT ANY WARRANTY; without even the implied warranty of
	10	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	11	* General Public License for more details.
	12	*/
	13	/*
	14	* Copyright (c) 2005-2010 Brocade Communications Systems, Inc.
	15	* All rights reserved
	16	* www.brocade.com
	17	*/
	18	#ifndef __BNAD_H__
	19	#define __BNAD_H__
	20
	21	#include <linux/rtnetlink.h>
	22	#include <linux/workqueue.h>
	23	#include <linux/ipv6.h>
	24	#include <linux/etherdevice.h>
	25	#include <linux/mutex.h>
	26	#include <linux/firmware.h>
f859d7cb	27	#include <linux/if_vlan.h>
8b230ed8 RM	28
	29	/* Fix for IA64 */
	30	#include <asm/checksum.h>
	31	#include <net/ip6_checksum.h>
	32
	33	#include <net/ip.h>
	34	#include <net/tcp.h>
	35
	36	#include "bna.h"
	37
	38	#define BNAD_TXQ_DEPTH 2048
	39	#define BNAD_RXQ_DEPTH 2048
	40
772b5235	41	#define BNAD_MAX_TX 1
8b230ed8 RM	42	#define BNAD_MAX_TXQ_PER_TX 8 /* 8 priority queues */
	43	#define BNAD_TXQ_NUM 1
	44
772b5235 RM	45	#define BNAD_MAX_RX 1
772b5235 RM	46	#define BNAD_MAX_RXP_PER_RX 16
078086f3	47	#define BNAD_MAX_RXQ_PER_RXP 2
8b230ed8 RM	48
	49	/*
	50	* Control structure pointed to ccb->ctrl, which
	51	* determines the NAPI / LRO behavior CCB
	52	* There is 1:1 corres. between ccb & ctrl
	53	*/
	54	struct bnad_rx_ctrl {
	55	struct bna_ccb *ccb;
2be67144	56	struct bnad *bnad;
be7fa326	57	unsigned long flags;
8b230ed8	58	struct napi_struct napi;
271e8b79 RM	59	u64 rx_intr_ctr;
	60	u64 rx_poll_ctr;
	61	u64 rx_schedule;
	62	u64 rx_keep_poll;
	63	u64 rx_complete;
8b230ed8 RM	64	};
	65
	66	#define BNAD_RXMODE_PROMISC_DEFAULT BNA_RXMODE_PROMISC
	67
8b230ed8 RM	68	/*
	69	* GLOBAL #defines (CONSTANTS)
	70	*/
	71	#define BNAD_NAME "bna"
	72	#define BNAD_NAME_LEN 64
	73
5098af0a	74	#define BNAD_VERSION "3.0.2.0"
8b230ed8	75
8811e267	76	#define BNAD_MAILBOX_MSIX_INDEX 0
8b230ed8	77	#define BNAD_MAILBOX_MSIX_VECTORS 1
8811e267 RM	78	#define BNAD_INTX_TX_IB_BITMASK 0x1
8811e267 RM	79	#define BNAD_INTX_RX_IB_BITMASK 0x2
8b230ed8	80
0120b99c RM	81	#define BNAD_STATS_TIMER_FREQ 1000 /* in msecs */
0120b99c RM	82	#define BNAD_DIM_TIMER_FREQ 1000 /* in msecs */
8b230ed8	83
078086f3 RM	84	#define BNAD_IOCETH_TIMEOUT 10000
078086f3 RM	85
8b230ed8 RM	86	#define BNAD_MAX_Q_DEPTH 0x10000
	87	#define BNAD_MIN_Q_DEPTH 0x200
	88
	89	#define BNAD_JUMBO_MTU 9000
	90
	91	#define BNAD_NETIF_WAKE_THRESHOLD 8
	92
	93	#define BNAD_RXQ_REFILL_THRESHOLD_SHIFT 3
	94
	95	/* Bit positions for tcb->flags */
	96	#define BNAD_TXQ_FREE_SENT 0
be7fa326	97	#define BNAD_TXQ_TX_STARTED 1
8b230ed8 RM	98
	99	/* Bit positions for rcb->flags */
	100	#define BNAD_RXQ_REFILL 0
	101	#define BNAD_RXQ_STARTED 1
	102
078086f3 RM	103	/* Resource limits */
	104	#define BNAD_NUM_TXQ (bnad->num_tx * bnad->num_txq_per_tx)
	105	#define BNAD_NUM_RXP (bnad->num_rx * bnad->num_rxp_per_rx)
	106
8b230ed8 RM	107	/*
	108	* DATA STRUCTURES
	109	*/
	110
	111	/* enums */
	112	enum bnad_intr_source {
	113	BNAD_INTR_TX = 1,
	114	BNAD_INTR_RX = 2
	115	};
	116
	117	enum bnad_link_state {
	118	BNAD_LS_DOWN = 0,
0120b99c	119	BNAD_LS_UP = 1
8b230ed8 RM	120	};
	121
	122	struct bnad_completion {
0120b99c RM	123	struct completion ioc_comp;
0120b99c RM	124	struct completion ucast_comp;
8b230ed8 RM	125	struct completion mcast_comp;
	126	struct completion tx_comp;
	127	struct completion rx_comp;
	128	struct completion stats_comp;
078086f3 RM	129	struct completion enet_comp;
078086f3 RM	130	struct completion mtu_comp;
8b230ed8 RM	131
	132	u8 ioc_comp_status;
	133	u8 ucast_comp_status;
	134	u8 mcast_comp_status;
	135	u8 tx_comp_status;
	136	u8 rx_comp_status;
	137	u8 stats_comp_status;
	138	u8 port_comp_status;
078086f3	139	u8 mtu_comp_status;
8b230ed8 RM	140	};
	141
	142	/* Tx Rx Control Stats */
	143	struct bnad_drv_stats {
0120b99c	144	u64 netif_queue_stop;
8b230ed8	145	u64 netif_queue_wakeup;
f7c0fa4c	146	u64 netif_queue_stopped;
8b230ed8 RM	147	u64 tso4;
	148	u64 tso6;
	149	u64 tso_err;
	150	u64 tcpcsum_offload;
	151	u64 udpcsum_offload;
	152	u64 csum_help;
271e8b79 RM	153	u64 tx_skb_too_short;
	154	u64 tx_skb_stopping;
	155	u64 tx_skb_max_vectors;
	156	u64 tx_skb_mss_too_long;
	157	u64 tx_skb_tso_too_short;
	158	u64 tx_skb_tso_prepare;
	159	u64 tx_skb_non_tso_too_long;
	160	u64 tx_skb_tcp_hdr;
	161	u64 tx_skb_udp_hdr;
	162	u64 tx_skb_csum_err;
	163	u64 tx_skb_headlen_too_long;
	164	u64 tx_skb_headlen_zero;
	165	u64 tx_skb_frag_zero;
	166	u64 tx_skb_len_mismatch;
8b230ed8 RM	167
8b230ed8 RM	168	u64 hw_stats_updates;
8b230ed8 RM	169	u64 netif_rx_dropped;
	170
	171	u64 link_toggle;
078086f3	172	u64 cee_toggle;
8b230ed8 RM	173
	174	u64 rxp_info_alloc_failed;
	175	u64 mbox_intr_disabled;
	176	u64 mbox_intr_enabled;
	177	u64 tx_unmap_q_alloc_failed;
	178	u64 rx_unmap_q_alloc_failed;
	179
	180	u64 rxbuf_alloc_failed;
	181	};
	182
	183	/* Complete driver stats */
	184	struct bnad_stats {
	185	struct bnad_drv_stats drv_stats;
	186	struct bna_stats *bna_stats;
	187	};
	188
	189	/* Tx / Rx Resources */
	190	struct bnad_tx_res_info {
	191	struct bna_res_info res_info[BNA_TX_RES_T_MAX];
	192	};
	193
	194	struct bnad_rx_res_info {
	195	struct bna_res_info res_info[BNA_RX_RES_T_MAX];
	196	};
	197
	198	struct bnad_tx_info {
	199	struct bna_tx tx; / 1:1 between tx_info & tx */
	200	struct bna_tcb *tcb[BNAD_MAX_TXQ_PER_TX];
078086f3	201	u32 tx_id;
8b230ed8 RM	202	} ____cacheline_aligned;
	203
	204	struct bnad_rx_info {
	205	struct bna_rx rx; / 1:1 between rx_info & rx */
	206
772b5235	207	struct bnad_rx_ctrl rx_ctrl[BNAD_MAX_RXP_PER_RX];
078086f3	208	u32 rx_id;
8b230ed8 RM	209	} ____cacheline_aligned;
	210
	211	/* Unmap queues for Tx / Rx cleanup */
	212	struct bnad_skb_unmap {
	213	struct sk_buff *skb;
5ea74318	214	DEFINE_DMA_UNMAP_ADDR(dma_addr);
8b230ed8 RM	215	};
	216
	217	struct bnad_unmap_q {
	218	u32 producer_index;
	219	u32 consumer_index;
0120b99c	220	u32 q_depth;
8b230ed8 RM	221	/* This should be the last one */
	222	struct bnad_skb_unmap unmap_array[1];
	223	};
	224
	225	/* Bit mask values for bnad->cfg_flags */
	226	#define BNAD_CF_DIM_ENABLED 0x01 /* DIM */
	227	#define BNAD_CF_PROMISC 0x02
	228	#define BNAD_CF_ALLMULTI 0x04
	229	#define BNAD_CF_MSIX 0x08 /* If in MSIx mode */
	230
	231	/* Defines for run_flags bit-mask */
	232	/* Set, tested & cleared using xxx_bit() functions */
	233	/* Values indicated bit positions */
078086f3 RM	234	#define BNAD_RF_CEE_RUNNING 0
078086f3 RM	235	#define BNAD_RF_MTU_SET 1
be7fa326	236	#define BNAD_RF_MBOX_IRQ_DISABLED 2
078086f3	237	#define BNAD_RF_NETDEV_REGISTERED 3
be7fa326 RM	238	#define BNAD_RF_DIM_TIMER_RUNNING 4
be7fa326 RM	239	#define BNAD_RF_STATS_TIMER_RUNNING 5
078086f3 RM	240	#define BNAD_RF_TX_PRIO_SET 6
	241
	242
	243	/* Define for Fast Path flags */
	244	/* Defined as bit positions */
	245	#define BNAD_FP_IN_RX_PATH 0
8b230ed8 RM	246
8b230ed8 RM	247	struct bnad {
0120b99c	248	struct net_device *netdev;
8b230ed8 RM	249
8b230ed8 RM	250	/* Data path */
772b5235 RM	251	struct bnad_tx_info tx_info[BNAD_MAX_TX];
772b5235 RM	252	struct bnad_rx_info rx_info[BNAD_MAX_RX];
8b230ed8	253
f859d7cb	254	unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
8b230ed8 RM	255	/*
	256	* These q numbers are global only because
	257	* they are used to calculate MSIx vectors.
	258	* Actually the exact # of queues are per Tx/Rx
	259	* object.
	260	*/
	261	u32 num_tx;
	262	u32 num_rx;
	263	u32 num_txq_per_tx;
	264	u32 num_rxp_per_rx;
	265
	266	u32 txq_depth;
	267	u32 rxq_depth;
	268
	269	u8 tx_coalescing_timeo;
	270	u8 rx_coalescing_timeo;
	271
772b5235 RM	272	struct bna_rx_config rx_config[BNAD_MAX_RX];
772b5235 RM	273	struct bna_tx_config tx_config[BNAD_MAX_TX];
8b230ed8	274
8b230ed8 RM	275	void __iomem bar0; / BAR0 address */
	276
	277	struct bna bna;
	278
	279	u32 cfg_flags;
	280	unsigned long run_flags;
	281
0120b99c	282	struct pci_dev *pcidev;
8b230ed8 RM	283	u64 mmio_start;
	284	u64 mmio_len;
	285
	286	u32 msix_num;
8b230ed8 RM	287	struct msix_entry *msix_table;
	288
	289	struct mutex conf_mutex;
	290	spinlock_t bna_lock ____cacheline_aligned;
	291
	292	/* Timers */
	293	struct timer_list ioc_timer;
	294	struct timer_list dim_timer;
	295	struct timer_list stats_timer;
	296
	297	/* Control path resources, memory & irq */
	298	struct bna_res_info res_info[BNA_RES_T_MAX];
078086f3	299	struct bna_res_info mod_res_info[BNA_MOD_RES_T_MAX];
772b5235 RM	300	struct bnad_tx_res_info tx_res_info[BNAD_MAX_TX];
772b5235 RM	301	struct bnad_rx_res_info rx_res_info[BNAD_MAX_RX];
8b230ed8 RM	302
	303	struct bnad_completion bnad_completions;
	304
	305	/* Burnt in MAC address */
	306	mac_t perm_addr;
	307
	308	struct tasklet_struct tx_free_tasklet;
	309
	310	/* Statistics */
	311	struct bnad_stats stats;
8b230ed8 RM	312
	313	struct bnad_diag *diag;
	314
	315	char adapter_name[BNAD_NAME_LEN];
0120b99c	316	char port_name[BNAD_NAME_LEN];
8b230ed8 RM	317	char mbox_irq_name[BNAD_NAME_LEN];
	318	};
	319
	320	/*
	321	* EXTERN VARIABLES
	322	*/
	323	extern struct firmware *bfi_fw;
0120b99c	324	extern u32 bnad_rxqs_per_cq;
8b230ed8 RM	325
	326	/*
	327	* EXTERN PROTOTYPES
	328	*/
	329	extern u32 cna_get_firmware_buf(struct pci_dev pdev);
	330	/* Netdev entry point prototypes */
a2122d95 RM	331	extern void bnad_set_rx_mode(struct net_device *netdev);
	332	extern struct net_device_stats *bnad_get_netdev_stats(
	333	struct net_device *netdev);
	334	extern int bnad_mac_addr_set_locked(struct bnad bnad, u8 mac_addr);
	335	extern int bnad_enable_default_bcast(struct bnad *bnad);
	336	extern void bnad_restore_vlans(struct bnad *bnad, u32 rx_id);
8b230ed8 RM	337	extern void bnad_set_ethtool_ops(struct net_device *netdev);
	338
	339	/* Configuration & setup */
	340	extern void bnad_tx_coalescing_timeo_set(struct bnad *bnad);
	341	extern void bnad_rx_coalescing_timeo_set(struct bnad *bnad);
	342
078086f3 RM	343	extern int bnad_setup_rx(struct bnad *bnad, u32 rx_id);
	344	extern int bnad_setup_tx(struct bnad *bnad, u32 tx_id);
	345	extern void bnad_cleanup_tx(struct bnad *bnad, u32 tx_id);
	346	extern void bnad_cleanup_rx(struct bnad *bnad, u32 rx_id);
8b230ed8 RM	347
	348	/* Timer start/stop protos */
	349	extern void bnad_dim_timer_start(struct bnad *bnad);
	350
	351	/* Statistics */
f7c0fa4c RM	352	extern void bnad_netdev_qstats_fill(struct bnad *bnad,
	353	struct rtnl_link_stats64 *stats);
	354	extern void bnad_netdev_hwstats_fill(struct bnad *bnad,
	355	struct rtnl_link_stats64 *stats);
8b230ed8 RM	356
	357	/**
	358	* MACROS
	359	*/
	360	/* To set & get the stats counters */
	361	#define BNAD_UPDATE_CTR(_bnad, _ctr) \
	362	(((_bnad)->stats.drv_stats._ctr)++)
	363
	364	#define BNAD_GET_CTR(_bnad, _ctr) ((_bnad)->stats.drv_stats._ctr)
	365
	366	#define bnad_enable_rx_irq_unsafe(_ccb) \
	367	{ \
271e8b79	368	if (likely(test_bit(BNAD_RXQ_STARTED, &(_ccb)->rcb[0]->flags))) {\
be7fa326 RM	369	bna_ib_coalescing_timer_set((_ccb)->i_dbell, \
	370	(_ccb)->rx_coalescing_timeo); \
	371	bna_ib_ack((_ccb)->i_dbell, 0); \
	372	} \
8b230ed8 RM	373	}
8b230ed8 RM	374
8b230ed8	375	#endif /* __BNAD_H__ */