Commit | Line | Data |
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8b230ed8 RM |
1 | /* |
2 | * Linux network driver for Brocade Converged Network Adapter. | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify it | |
5 | * under the terms of the GNU General Public License (GPL) Version 2 as | |
6 | * published by the Free Software Foundation | |
7 | * | |
8 | * This program is distributed in the hope that it will be useful, but | |
9 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
11 | * General Public License for more details. | |
12 | */ | |
13 | /* | |
14 | * Copyright (c) 2005-2010 Brocade Communications Systems, Inc. | |
15 | * All rights reserved | |
16 | * www.brocade.com | |
17 | */ | |
18 | #ifndef __BNAD_H__ | |
19 | #define __BNAD_H__ | |
20 | ||
21 | #include <linux/rtnetlink.h> | |
22 | #include <linux/workqueue.h> | |
23 | #include <linux/ipv6.h> | |
24 | #include <linux/etherdevice.h> | |
25 | #include <linux/mutex.h> | |
26 | #include <linux/firmware.h> | |
f859d7cb | 27 | #include <linux/if_vlan.h> |
8b230ed8 RM |
28 | |
29 | /* Fix for IA64 */ | |
30 | #include <asm/checksum.h> | |
31 | #include <net/ip6_checksum.h> | |
32 | ||
33 | #include <net/ip.h> | |
34 | #include <net/tcp.h> | |
35 | ||
36 | #include "bna.h" | |
37 | ||
38 | #define BNAD_TXQ_DEPTH 2048 | |
39 | #define BNAD_RXQ_DEPTH 2048 | |
40 | ||
772b5235 | 41 | #define BNAD_MAX_TX 1 |
8b230ed8 RM |
42 | #define BNAD_MAX_TXQ_PER_TX 8 /* 8 priority queues */ |
43 | #define BNAD_TXQ_NUM 1 | |
44 | ||
772b5235 RM |
45 | #define BNAD_MAX_RX 1 |
46 | #define BNAD_MAX_RXP_PER_RX 16 | |
078086f3 | 47 | #define BNAD_MAX_RXQ_PER_RXP 2 |
8b230ed8 RM |
48 | |
49 | /* | |
50 | * Control structure pointed to ccb->ctrl, which | |
51 | * determines the NAPI / LRO behavior CCB | |
52 | * There is 1:1 corres. between ccb & ctrl | |
53 | */ | |
54 | struct bnad_rx_ctrl { | |
55 | struct bna_ccb *ccb; | |
2be67144 | 56 | struct bnad *bnad; |
be7fa326 | 57 | unsigned long flags; |
8b230ed8 | 58 | struct napi_struct napi; |
271e8b79 RM |
59 | u64 rx_intr_ctr; |
60 | u64 rx_poll_ctr; | |
61 | u64 rx_schedule; | |
62 | u64 rx_keep_poll; | |
63 | u64 rx_complete; | |
8b230ed8 RM |
64 | }; |
65 | ||
66 | #define BNAD_RXMODE_PROMISC_DEFAULT BNA_RXMODE_PROMISC | |
67 | ||
8b230ed8 RM |
68 | /* |
69 | * GLOBAL #defines (CONSTANTS) | |
70 | */ | |
71 | #define BNAD_NAME "bna" | |
72 | #define BNAD_NAME_LEN 64 | |
73 | ||
9450f750 | 74 | #define BNAD_VERSION "3.0.23.0" |
8b230ed8 | 75 | |
8811e267 | 76 | #define BNAD_MAILBOX_MSIX_INDEX 0 |
8b230ed8 | 77 | #define BNAD_MAILBOX_MSIX_VECTORS 1 |
8811e267 RM |
78 | #define BNAD_INTX_TX_IB_BITMASK 0x1 |
79 | #define BNAD_INTX_RX_IB_BITMASK 0x2 | |
8b230ed8 | 80 | |
0120b99c RM |
81 | #define BNAD_STATS_TIMER_FREQ 1000 /* in msecs */ |
82 | #define BNAD_DIM_TIMER_FREQ 1000 /* in msecs */ | |
8b230ed8 | 83 | |
078086f3 RM |
84 | #define BNAD_IOCETH_TIMEOUT 10000 |
85 | ||
8b230ed8 RM |
86 | #define BNAD_MAX_Q_DEPTH 0x10000 |
87 | #define BNAD_MIN_Q_DEPTH 0x200 | |
88 | ||
41eb5ba4 RM |
89 | #define BNAD_MAX_RXQ_DEPTH (BNAD_MAX_Q_DEPTH / bnad_rxqs_per_cq) |
90 | /* keeping MAX TX and RX Q depth equal */ | |
91 | #define BNAD_MAX_TXQ_DEPTH BNAD_MAX_RXQ_DEPTH | |
92 | ||
8b230ed8 RM |
93 | #define BNAD_JUMBO_MTU 9000 |
94 | ||
95 | #define BNAD_NETIF_WAKE_THRESHOLD 8 | |
96 | ||
97 | #define BNAD_RXQ_REFILL_THRESHOLD_SHIFT 3 | |
98 | ||
99 | /* Bit positions for tcb->flags */ | |
100 | #define BNAD_TXQ_FREE_SENT 0 | |
be7fa326 | 101 | #define BNAD_TXQ_TX_STARTED 1 |
8b230ed8 RM |
102 | |
103 | /* Bit positions for rcb->flags */ | |
104 | #define BNAD_RXQ_REFILL 0 | |
105 | #define BNAD_RXQ_STARTED 1 | |
5bcf6ac0 | 106 | #define BNAD_RXQ_POST_OK 2 |
8b230ed8 | 107 | |
078086f3 RM |
108 | /* Resource limits */ |
109 | #define BNAD_NUM_TXQ (bnad->num_tx * bnad->num_txq_per_tx) | |
110 | #define BNAD_NUM_RXP (bnad->num_rx * bnad->num_rxp_per_rx) | |
111 | ||
8b230ed8 RM |
112 | /* |
113 | * DATA STRUCTURES | |
114 | */ | |
115 | ||
116 | /* enums */ | |
117 | enum bnad_intr_source { | |
118 | BNAD_INTR_TX = 1, | |
119 | BNAD_INTR_RX = 2 | |
120 | }; | |
121 | ||
122 | enum bnad_link_state { | |
123 | BNAD_LS_DOWN = 0, | |
0120b99c | 124 | BNAD_LS_UP = 1 |
8b230ed8 RM |
125 | }; |
126 | ||
72a9730b KG |
127 | struct bnad_iocmd_comp { |
128 | struct bnad *bnad; | |
129 | struct completion comp; | |
130 | int comp_status; | |
131 | }; | |
132 | ||
8b230ed8 | 133 | struct bnad_completion { |
0120b99c RM |
134 | struct completion ioc_comp; |
135 | struct completion ucast_comp; | |
8b230ed8 RM |
136 | struct completion mcast_comp; |
137 | struct completion tx_comp; | |
138 | struct completion rx_comp; | |
139 | struct completion stats_comp; | |
078086f3 RM |
140 | struct completion enet_comp; |
141 | struct completion mtu_comp; | |
8b230ed8 RM |
142 | |
143 | u8 ioc_comp_status; | |
144 | u8 ucast_comp_status; | |
145 | u8 mcast_comp_status; | |
146 | u8 tx_comp_status; | |
147 | u8 rx_comp_status; | |
148 | u8 stats_comp_status; | |
149 | u8 port_comp_status; | |
078086f3 | 150 | u8 mtu_comp_status; |
8b230ed8 RM |
151 | }; |
152 | ||
153 | /* Tx Rx Control Stats */ | |
154 | struct bnad_drv_stats { | |
0120b99c | 155 | u64 netif_queue_stop; |
8b230ed8 | 156 | u64 netif_queue_wakeup; |
f7c0fa4c | 157 | u64 netif_queue_stopped; |
8b230ed8 RM |
158 | u64 tso4; |
159 | u64 tso6; | |
160 | u64 tso_err; | |
161 | u64 tcpcsum_offload; | |
162 | u64 udpcsum_offload; | |
163 | u64 csum_help; | |
271e8b79 RM |
164 | u64 tx_skb_too_short; |
165 | u64 tx_skb_stopping; | |
166 | u64 tx_skb_max_vectors; | |
167 | u64 tx_skb_mss_too_long; | |
168 | u64 tx_skb_tso_too_short; | |
169 | u64 tx_skb_tso_prepare; | |
170 | u64 tx_skb_non_tso_too_long; | |
171 | u64 tx_skb_tcp_hdr; | |
172 | u64 tx_skb_udp_hdr; | |
173 | u64 tx_skb_csum_err; | |
174 | u64 tx_skb_headlen_too_long; | |
175 | u64 tx_skb_headlen_zero; | |
176 | u64 tx_skb_frag_zero; | |
177 | u64 tx_skb_len_mismatch; | |
8b230ed8 RM |
178 | |
179 | u64 hw_stats_updates; | |
8b230ed8 RM |
180 | u64 netif_rx_dropped; |
181 | ||
182 | u64 link_toggle; | |
078086f3 | 183 | u64 cee_toggle; |
8b230ed8 RM |
184 | |
185 | u64 rxp_info_alloc_failed; | |
186 | u64 mbox_intr_disabled; | |
187 | u64 mbox_intr_enabled; | |
188 | u64 tx_unmap_q_alloc_failed; | |
189 | u64 rx_unmap_q_alloc_failed; | |
190 | ||
191 | u64 rxbuf_alloc_failed; | |
192 | }; | |
193 | ||
194 | /* Complete driver stats */ | |
195 | struct bnad_stats { | |
196 | struct bnad_drv_stats drv_stats; | |
197 | struct bna_stats *bna_stats; | |
198 | }; | |
199 | ||
200 | /* Tx / Rx Resources */ | |
201 | struct bnad_tx_res_info { | |
202 | struct bna_res_info res_info[BNA_TX_RES_T_MAX]; | |
203 | }; | |
204 | ||
205 | struct bnad_rx_res_info { | |
206 | struct bna_res_info res_info[BNA_RX_RES_T_MAX]; | |
207 | }; | |
208 | ||
209 | struct bnad_tx_info { | |
210 | struct bna_tx *tx; /* 1:1 between tx_info & tx */ | |
211 | struct bna_tcb *tcb[BNAD_MAX_TXQ_PER_TX]; | |
078086f3 | 212 | u32 tx_id; |
01b54b14 | 213 | struct delayed_work tx_cleanup_work; |
8b230ed8 RM |
214 | } ____cacheline_aligned; |
215 | ||
216 | struct bnad_rx_info { | |
217 | struct bna_rx *rx; /* 1:1 between rx_info & rx */ | |
218 | ||
772b5235 | 219 | struct bnad_rx_ctrl rx_ctrl[BNAD_MAX_RXP_PER_RX]; |
078086f3 | 220 | u32 rx_id; |
01b54b14 | 221 | struct work_struct rx_cleanup_work; |
8b230ed8 RM |
222 | } ____cacheline_aligned; |
223 | ||
224 | /* Unmap queues for Tx / Rx cleanup */ | |
225 | struct bnad_skb_unmap { | |
226 | struct sk_buff *skb; | |
5ea74318 | 227 | DEFINE_DMA_UNMAP_ADDR(dma_addr); |
8b230ed8 RM |
228 | }; |
229 | ||
230 | struct bnad_unmap_q { | |
231 | u32 producer_index; | |
232 | u32 consumer_index; | |
0120b99c | 233 | u32 q_depth; |
8b230ed8 RM |
234 | /* This should be the last one */ |
235 | struct bnad_skb_unmap unmap_array[1]; | |
236 | }; | |
237 | ||
238 | /* Bit mask values for bnad->cfg_flags */ | |
239 | #define BNAD_CF_DIM_ENABLED 0x01 /* DIM */ | |
240 | #define BNAD_CF_PROMISC 0x02 | |
241 | #define BNAD_CF_ALLMULTI 0x04 | |
242 | #define BNAD_CF_MSIX 0x08 /* If in MSIx mode */ | |
243 | ||
244 | /* Defines for run_flags bit-mask */ | |
245 | /* Set, tested & cleared using xxx_bit() functions */ | |
246 | /* Values indicated bit positions */ | |
078086f3 RM |
247 | #define BNAD_RF_CEE_RUNNING 0 |
248 | #define BNAD_RF_MTU_SET 1 | |
be7fa326 | 249 | #define BNAD_RF_MBOX_IRQ_DISABLED 2 |
078086f3 | 250 | #define BNAD_RF_NETDEV_REGISTERED 3 |
be7fa326 RM |
251 | #define BNAD_RF_DIM_TIMER_RUNNING 4 |
252 | #define BNAD_RF_STATS_TIMER_RUNNING 5 | |
078086f3 RM |
253 | #define BNAD_RF_TX_PRIO_SET 6 |
254 | ||
255 | ||
256 | /* Define for Fast Path flags */ | |
257 | /* Defined as bit positions */ | |
258 | #define BNAD_FP_IN_RX_PATH 0 | |
8b230ed8 RM |
259 | |
260 | struct bnad { | |
0120b99c | 261 | struct net_device *netdev; |
72a9730b KG |
262 | u32 id; |
263 | struct list_head list_entry; | |
8b230ed8 RM |
264 | |
265 | /* Data path */ | |
772b5235 RM |
266 | struct bnad_tx_info tx_info[BNAD_MAX_TX]; |
267 | struct bnad_rx_info rx_info[BNAD_MAX_RX]; | |
8b230ed8 | 268 | |
f859d7cb | 269 | unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)]; |
8b230ed8 RM |
270 | /* |
271 | * These q numbers are global only because | |
272 | * they are used to calculate MSIx vectors. | |
273 | * Actually the exact # of queues are per Tx/Rx | |
274 | * object. | |
275 | */ | |
276 | u32 num_tx; | |
277 | u32 num_rx; | |
278 | u32 num_txq_per_tx; | |
279 | u32 num_rxp_per_rx; | |
280 | ||
281 | u32 txq_depth; | |
282 | u32 rxq_depth; | |
283 | ||
284 | u8 tx_coalescing_timeo; | |
285 | u8 rx_coalescing_timeo; | |
286 | ||
772b5235 RM |
287 | struct bna_rx_config rx_config[BNAD_MAX_RX]; |
288 | struct bna_tx_config tx_config[BNAD_MAX_TX]; | |
8b230ed8 | 289 | |
8b230ed8 RM |
290 | void __iomem *bar0; /* BAR0 address */ |
291 | ||
292 | struct bna bna; | |
293 | ||
294 | u32 cfg_flags; | |
295 | unsigned long run_flags; | |
296 | ||
0120b99c | 297 | struct pci_dev *pcidev; |
8b230ed8 RM |
298 | u64 mmio_start; |
299 | u64 mmio_len; | |
300 | ||
301 | u32 msix_num; | |
8b230ed8 RM |
302 | struct msix_entry *msix_table; |
303 | ||
304 | struct mutex conf_mutex; | |
305 | spinlock_t bna_lock ____cacheline_aligned; | |
306 | ||
307 | /* Timers */ | |
308 | struct timer_list ioc_timer; | |
309 | struct timer_list dim_timer; | |
310 | struct timer_list stats_timer; | |
311 | ||
312 | /* Control path resources, memory & irq */ | |
313 | struct bna_res_info res_info[BNA_RES_T_MAX]; | |
078086f3 | 314 | struct bna_res_info mod_res_info[BNA_MOD_RES_T_MAX]; |
772b5235 RM |
315 | struct bnad_tx_res_info tx_res_info[BNAD_MAX_TX]; |
316 | struct bnad_rx_res_info rx_res_info[BNAD_MAX_RX]; | |
8b230ed8 RM |
317 | |
318 | struct bnad_completion bnad_completions; | |
319 | ||
320 | /* Burnt in MAC address */ | |
321 | mac_t perm_addr; | |
322 | ||
01b54b14 | 323 | struct workqueue_struct *work_q; |
8b230ed8 RM |
324 | |
325 | /* Statistics */ | |
326 | struct bnad_stats stats; | |
8b230ed8 RM |
327 | |
328 | struct bnad_diag *diag; | |
329 | ||
330 | char adapter_name[BNAD_NAME_LEN]; | |
0120b99c | 331 | char port_name[BNAD_NAME_LEN]; |
8b230ed8 | 332 | char mbox_irq_name[BNAD_NAME_LEN]; |
01b54b14 | 333 | char wq_name[BNAD_NAME_LEN]; |
7afc5dbd KG |
334 | |
335 | /* debugfs specific data */ | |
336 | char *regdata; | |
337 | u32 reglen; | |
338 | struct dentry *bnad_dentry_files[5]; | |
339 | struct dentry *port_debugfs_root; | |
340 | }; | |
341 | ||
342 | struct bnad_drvinfo { | |
343 | struct bfa_ioc_attr ioc_attr; | |
344 | struct bfa_cee_attr cee_attr; | |
345 | struct bfa_flash_attr flash_attr; | |
346 | u32 cee_status; | |
347 | u32 flash_status; | |
8b230ed8 RM |
348 | }; |
349 | ||
350 | /* | |
351 | * EXTERN VARIABLES | |
352 | */ | |
e1e0918f | 353 | extern const struct firmware *bfi_fw; |
0120b99c | 354 | extern u32 bnad_rxqs_per_cq; |
8b230ed8 RM |
355 | |
356 | /* | |
357 | * EXTERN PROTOTYPES | |
358 | */ | |
359 | extern u32 *cna_get_firmware_buf(struct pci_dev *pdev); | |
360 | /* Netdev entry point prototypes */ | |
a2122d95 RM |
361 | extern void bnad_set_rx_mode(struct net_device *netdev); |
362 | extern struct net_device_stats *bnad_get_netdev_stats( | |
363 | struct net_device *netdev); | |
364 | extern int bnad_mac_addr_set_locked(struct bnad *bnad, u8 *mac_addr); | |
365 | extern int bnad_enable_default_bcast(struct bnad *bnad); | |
366 | extern void bnad_restore_vlans(struct bnad *bnad, u32 rx_id); | |
8b230ed8 | 367 | extern void bnad_set_ethtool_ops(struct net_device *netdev); |
72a9730b | 368 | extern void bnad_cb_completion(void *arg, enum bfa_status status); |
8b230ed8 RM |
369 | |
370 | /* Configuration & setup */ | |
371 | extern void bnad_tx_coalescing_timeo_set(struct bnad *bnad); | |
372 | extern void bnad_rx_coalescing_timeo_set(struct bnad *bnad); | |
373 | ||
078086f3 RM |
374 | extern int bnad_setup_rx(struct bnad *bnad, u32 rx_id); |
375 | extern int bnad_setup_tx(struct bnad *bnad, u32 tx_id); | |
b3cc6e88 JH |
376 | extern void bnad_destroy_tx(struct bnad *bnad, u32 tx_id); |
377 | extern void bnad_destroy_rx(struct bnad *bnad, u32 rx_id); | |
8b230ed8 RM |
378 | |
379 | /* Timer start/stop protos */ | |
380 | extern void bnad_dim_timer_start(struct bnad *bnad); | |
381 | ||
382 | /* Statistics */ | |
f7c0fa4c RM |
383 | extern void bnad_netdev_qstats_fill(struct bnad *bnad, |
384 | struct rtnl_link_stats64 *stats); | |
385 | extern void bnad_netdev_hwstats_fill(struct bnad *bnad, | |
386 | struct rtnl_link_stats64 *stats); | |
8b230ed8 | 387 | |
7afc5dbd KG |
388 | /* Debugfs */ |
389 | void bnad_debugfs_init(struct bnad *bnad); | |
390 | void bnad_debugfs_uninit(struct bnad *bnad); | |
391 | ||
1aa8b471 | 392 | /* MACROS */ |
8b230ed8 RM |
393 | /* To set & get the stats counters */ |
394 | #define BNAD_UPDATE_CTR(_bnad, _ctr) \ | |
395 | (((_bnad)->stats.drv_stats._ctr)++) | |
396 | ||
397 | #define BNAD_GET_CTR(_bnad, _ctr) ((_bnad)->stats.drv_stats._ctr) | |
398 | ||
399 | #define bnad_enable_rx_irq_unsafe(_ccb) \ | |
400 | { \ | |
271e8b79 | 401 | if (likely(test_bit(BNAD_RXQ_STARTED, &(_ccb)->rcb[0]->flags))) {\ |
be7fa326 RM |
402 | bna_ib_coalescing_timer_set((_ccb)->i_dbell, \ |
403 | (_ccb)->rx_coalescing_timeo); \ | |
404 | bna_ib_ack((_ccb)->i_dbell, 0); \ | |
405 | } \ | |
8b230ed8 RM |
406 | } |
407 | ||
8b230ed8 | 408 | #endif /* __BNAD_H__ */ |