[deliverable/linux.git] / drivers / net / ethernet / brocade / bna / bnad.h

/*
 * Linux network driver for Brocade Converged Network Adapter.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License (GPL) Version 2 as
 * published by the Free Software Foundation
 *
 * This program is distributed in the hope that it will be useful, but
 * WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * General Public License for more details.
 */
/*
 * Copyright (c) 2005-2010 Brocade Communications Systems, Inc.
 * All rights reserved
 * www.brocade.com
 */
#ifndef __BNAD_H__
#define __BNAD_H__

#include <linux/rtnetlink.h>
#include <linux/workqueue.h>
#include <linux/ipv6.h>
#include <linux/etherdevice.h>
#include <linux/mutex.h>
#include <linux/firmware.h>
#include <linux/if_vlan.h>

/* Fix for IA64 */
#include <asm/checksum.h>
#include <net/ip6_checksum.h>

#include <net/ip.h>
#include <net/tcp.h>

#include "bna.h"

#define BNAD_TXQ_DEPTH		2048
#define BNAD_RXQ_DEPTH		2048

#define BNAD_MAX_TX		1
#define BNAD_MAX_TXQ_PER_TX	8	/* 8 priority queues */
#define BNAD_TXQ_NUM		1

#define BNAD_MAX_RX		1
#define BNAD_MAX_RXP_PER_RX	16
#define BNAD_MAX_RXQ_PER_RXP	2

/*
 * Control structure pointed to ccb->ctrl, which
 * determines the NAPI / LRO behavior CCB
 * There is 1:1 corres. between ccb & ctrl
 */
struct bnad_rx_ctrl {
	struct bna_ccb *ccb;
	struct bnad *bnad;
	unsigned long  flags;
	struct napi_struct	napi;
	u64		rx_intr_ctr;
	u64		rx_poll_ctr;
	u64		rx_schedule;
	u64		rx_keep_poll;
	u64		rx_complete;
};

#define BNAD_RXMODE_PROMISC_DEFAULT	BNA_RXMODE_PROMISC

/*
 * GLOBAL #defines (CONSTANTS)
 */
#define BNAD_NAME			"bna"
#define BNAD_NAME_LEN			64

#define BNAD_VERSION			"3.2.21.1"

#define BNAD_MAILBOX_MSIX_INDEX		0
#define BNAD_MAILBOX_MSIX_VECTORS	1
#define BNAD_INTX_TX_IB_BITMASK		0x1
#define BNAD_INTX_RX_IB_BITMASK		0x2

#define BNAD_STATS_TIMER_FREQ		1000	/* in msecs */
#define BNAD_DIM_TIMER_FREQ		1000	/* in msecs */

#define BNAD_IOCETH_TIMEOUT	     10000

#define BNAD_MIN_Q_DEPTH		512
#define BNAD_MAX_RXQ_DEPTH		2048
#define BNAD_MAX_TXQ_DEPTH		2048

#define BNAD_JUMBO_MTU			9000

#define BNAD_NETIF_WAKE_THRESHOLD	8

#define BNAD_RXQ_REFILL_THRESHOLD_SHIFT	3

/* Bit positions for tcb->flags */
#define BNAD_TXQ_FREE_SENT		0
#define BNAD_TXQ_TX_STARTED		1

/* Bit positions for rcb->flags */
#define BNAD_RXQ_STARTED		0
#define BNAD_RXQ_POST_OK		1

/* Resource limits */
#define BNAD_NUM_TXQ			(bnad->num_tx * bnad->num_txq_per_tx)
#define BNAD_NUM_RXP			(bnad->num_rx * bnad->num_rxp_per_rx)

/*
 * DATA STRUCTURES
 */

/* enums */
enum bnad_intr_source {
	BNAD_INTR_TX		= 1,
	BNAD_INTR_RX		= 2
};

enum bnad_link_state {
	BNAD_LS_DOWN		= 0,
	BNAD_LS_UP		= 1
};

struct bnad_iocmd_comp {
	struct bnad		*bnad;
	struct completion	comp;
	int			comp_status;
};

struct bnad_completion {
	struct completion	ioc_comp;
	struct completion	ucast_comp;
	struct completion	mcast_comp;
	struct completion	tx_comp;
	struct completion	rx_comp;
	struct completion	stats_comp;
	struct completion	enet_comp;
	struct completion	mtu_comp;

	u8			ioc_comp_status;
	u8			ucast_comp_status;
	u8			mcast_comp_status;
	u8			tx_comp_status;
	u8			rx_comp_status;
	u8			stats_comp_status;
	u8			port_comp_status;
	u8			mtu_comp_status;
};

/* Tx Rx Control Stats */
struct bnad_drv_stats {
	u64		netif_queue_stop;
	u64		netif_queue_wakeup;
	u64		netif_queue_stopped;
	u64		tso4;
	u64		tso6;
	u64		tso_err;
	u64		tcpcsum_offload;
	u64		udpcsum_offload;
	u64		csum_help;
	u64		tx_skb_too_short;
	u64		tx_skb_stopping;
	u64		tx_skb_max_vectors;
	u64		tx_skb_mss_too_long;
	u64		tx_skb_tso_too_short;
	u64		tx_skb_tso_prepare;
	u64		tx_skb_non_tso_too_long;
	u64		tx_skb_tcp_hdr;
	u64		tx_skb_udp_hdr;
	u64		tx_skb_csum_err;
	u64		tx_skb_headlen_too_long;
	u64		tx_skb_headlen_zero;
	u64		tx_skb_frag_zero;
	u64		tx_skb_len_mismatch;

	u64		hw_stats_updates;
	u64		netif_rx_dropped;

	u64		link_toggle;
	u64		cee_toggle;

	u64		rxp_info_alloc_failed;
	u64		mbox_intr_disabled;
	u64		mbox_intr_enabled;
	u64		tx_unmap_q_alloc_failed;
	u64		rx_unmap_q_alloc_failed;

	u64		rxbuf_alloc_failed;
};

/* Complete driver stats */
struct bnad_stats {
	struct bnad_drv_stats drv_stats;
	struct bna_stats *bna_stats;
};

/* Tx / Rx Resources */
struct bnad_tx_res_info {
	struct bna_res_info res_info[BNA_TX_RES_T_MAX];
};

struct bnad_rx_res_info {
	struct bna_res_info res_info[BNA_RX_RES_T_MAX];
};

struct bnad_tx_info {
	struct bna_tx *tx; /* 1:1 between tx_info & tx */
	struct bna_tcb *tcb[BNAD_MAX_TXQ_PER_TX];
	u32 tx_id;
	struct delayed_work tx_cleanup_work;
} ____cacheline_aligned;

struct bnad_rx_info {
	struct bna_rx *rx; /* 1:1 between rx_info & rx */

	struct bnad_rx_ctrl rx_ctrl[BNAD_MAX_RXP_PER_RX];
	u32 rx_id;
	struct work_struct rx_cleanup_work;
} ____cacheline_aligned;

struct bnad_tx_vector {
	DEFINE_DMA_UNMAP_ADDR(dma_addr);
};

struct bnad_tx_unmap {
	struct sk_buff		*skb;
	u32			nvecs;
	struct bnad_tx_vector	vectors[BFI_TX_MAX_VECTORS_PER_WI];
};

struct bnad_rx_vector {
	DEFINE_DMA_UNMAP_ADDR(dma_addr);
	u32			len;
};

struct bnad_rx_unmap {
	struct page		*page;
	u32			page_offset;
	struct sk_buff		*skb;
	struct bnad_rx_vector	vector;
};

enum bnad_rxbuf_type {
	BNAD_RXBUF_NONE		= 0,
	BNAD_RXBUF_SKB		= 1,
	BNAD_RXBUF_PAGE		= 2,
	BNAD_RXBUF_MULTI	= 3
};

#define BNAD_RXBUF_IS_PAGE(_type)	((_type) == BNAD_RXBUF_PAGE)

struct bnad_rx_unmap_q {
	int			reuse_pi;
	int			alloc_order;
	u32			map_size;
	enum bnad_rxbuf_type	type;
	struct bnad_rx_unmap	unmap[0];
};

/* Bit mask values for bnad->cfg_flags */
#define	BNAD_CF_DIM_ENABLED		0x01	/* DIM */
#define	BNAD_CF_PROMISC			0x02
#define BNAD_CF_ALLMULTI		0x04
#define	BNAD_CF_DEFAULT			0x08
#define	BNAD_CF_MSIX			0x10	/* If in MSIx mode */

/* Defines for run_flags bit-mask */
/* Set, tested & cleared using xxx_bit() functions */
/* Values indicated bit positions */
#define BNAD_RF_CEE_RUNNING		0
#define BNAD_RF_MTU_SET		1
#define BNAD_RF_MBOX_IRQ_DISABLED	2
#define BNAD_RF_NETDEV_REGISTERED	3
#define BNAD_RF_DIM_TIMER_RUNNING	4
#define BNAD_RF_STATS_TIMER_RUNNING	5
#define BNAD_RF_TX_PRIO_SET		6

struct bnad {
	struct net_device	*netdev;
	u32			id;
	struct list_head	list_entry;

	/* Data path */
	struct bnad_tx_info tx_info[BNAD_MAX_TX];
	struct bnad_rx_info rx_info[BNAD_MAX_RX];

	unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
	/*
	 * These q numbers are global only because
	 * they are used to calculate MSIx vectors.
	 * Actually the exact # of queues are per Tx/Rx
	 * object.
	 */
	u32		num_tx;
	u32		num_rx;
	u32		num_txq_per_tx;
	u32		num_rxp_per_rx;

	u32		txq_depth;
	u32		rxq_depth;

	u8			tx_coalescing_timeo;
	u8			rx_coalescing_timeo;

	struct bna_rx_config rx_config[BNAD_MAX_RX] ____cacheline_aligned;
	struct bna_tx_config tx_config[BNAD_MAX_TX] ____cacheline_aligned;

	void __iomem		*bar0;	/* BAR0 address */

	struct bna bna;

	u32		cfg_flags;
	unsigned long		run_flags;

	struct pci_dev		*pcidev;
	u64		mmio_start;
	u64		mmio_len;

	u32		msix_num;
	struct msix_entry	*msix_table;

	struct mutex		conf_mutex;
	spinlock_t		bna_lock ____cacheline_aligned;

	/* Timers */
	struct timer_list	ioc_timer;
	struct timer_list	dim_timer;
	struct timer_list	stats_timer;

	/* Control path resources, memory & irq */
	struct bna_res_info res_info[BNA_RES_T_MAX];
	struct bna_res_info mod_res_info[BNA_MOD_RES_T_MAX];
	struct bnad_tx_res_info tx_res_info[BNAD_MAX_TX];
	struct bnad_rx_res_info rx_res_info[BNAD_MAX_RX];

	struct bnad_completion bnad_completions;

	/* Burnt in MAC address */
	mac_t			perm_addr;

	struct workqueue_struct *work_q;

	/* Statistics */
	struct bnad_stats stats;

	struct bnad_diag *diag;

	char			adapter_name[BNAD_NAME_LEN];
	char			port_name[BNAD_NAME_LEN];
	char			mbox_irq_name[BNAD_NAME_LEN];
	char			wq_name[BNAD_NAME_LEN];

	/* debugfs specific data */
	char	*regdata;
	u32	reglen;
	struct dentry *bnad_dentry_files[5];
	struct dentry *port_debugfs_root;
};

struct bnad_drvinfo {
	struct bfa_ioc_attr  ioc_attr;
	struct bfa_cee_attr  cee_attr;
	struct bfa_flash_attr flash_attr;
	u32	cee_status;
	u32	flash_status;
};

/*
 * EXTERN VARIABLES
 */
extern const struct firmware *bfi_fw;

/*
 * EXTERN PROTOTYPES
 */
u32 *cna_get_firmware_buf(struct pci_dev *pdev);
/* Netdev entry point prototypes */
void bnad_set_rx_mode(struct net_device *netdev);
struct net_device_stats *bnad_get_netdev_stats(struct net_device *netdev);
int bnad_mac_addr_set_locked(struct bnad *bnad, u8 *mac_addr);
int bnad_enable_default_bcast(struct bnad *bnad);
void bnad_restore_vlans(struct bnad *bnad, u32 rx_id);
void bnad_set_ethtool_ops(struct net_device *netdev);
void bnad_cb_completion(void *arg, enum bfa_status status);

/* Configuration & setup */
void bnad_tx_coalescing_timeo_set(struct bnad *bnad);
void bnad_rx_coalescing_timeo_set(struct bnad *bnad);

int bnad_setup_rx(struct bnad *bnad, u32 rx_id);
int bnad_setup_tx(struct bnad *bnad, u32 tx_id);
void bnad_destroy_tx(struct bnad *bnad, u32 tx_id);
void bnad_destroy_rx(struct bnad *bnad, u32 rx_id);

/* Timer start/stop protos */
void bnad_dim_timer_start(struct bnad *bnad);

/* Statistics */
void bnad_netdev_qstats_fill(struct bnad *bnad,
			     struct rtnl_link_stats64 *stats);
void bnad_netdev_hwstats_fill(struct bnad *bnad,
			      struct rtnl_link_stats64 *stats);

/* Debugfs */
void bnad_debugfs_init(struct bnad *bnad);
void bnad_debugfs_uninit(struct bnad *bnad);

/* MACROS */
/* To set & get the stats counters */
#define BNAD_UPDATE_CTR(_bnad, _ctr)				\
				(((_bnad)->stats.drv_stats._ctr)++)

#define BNAD_GET_CTR(_bnad, _ctr) ((_bnad)->stats.drv_stats._ctr)

#define bnad_enable_rx_irq_unsafe(_ccb)			\
{							\
	if (likely(test_bit(BNAD_RXQ_STARTED, &(_ccb)->rcb[0]->flags))) {\
		bna_ib_coalescing_timer_set((_ccb)->i_dbell,	\
			(_ccb)->rx_coalescing_timeo);		\
		bna_ib_ack((_ccb)->i_dbell, 0);			\
	}							\
}

#endif /* __BNAD_H__ */
Commit	Line	Data
8b230ed8 RM	1	/*
	2	* Linux network driver for Brocade Converged Network Adapter.
	3	*
	4	* This program is free software; you can redistribute it and/or modify it
	5	* under the terms of the GNU General Public License (GPL) Version 2 as
	6	* published by the Free Software Foundation
	7	*
	8	* This program is distributed in the hope that it will be useful, but
	9	* WITHOUT ANY WARRANTY; without even the implied warranty of
	10	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	11	* General Public License for more details.
	12	*/
	13	/*
	14	* Copyright (c) 2005-2010 Brocade Communications Systems, Inc.
	15	* All rights reserved
	16	* www.brocade.com
	17	*/
	18	#ifndef __BNAD_H__
	19	#define __BNAD_H__
	20
	21	#include <linux/rtnetlink.h>
	22	#include <linux/workqueue.h>
	23	#include <linux/ipv6.h>
	24	#include <linux/etherdevice.h>
	25	#include <linux/mutex.h>
	26	#include <linux/firmware.h>
f859d7cb	27	#include <linux/if_vlan.h>
8b230ed8 RM	28
	29	/* Fix for IA64 */
	30	#include <asm/checksum.h>
	31	#include <net/ip6_checksum.h>
	32
	33	#include <net/ip.h>
	34	#include <net/tcp.h>
	35
	36	#include "bna.h"
	37
	38	#define BNAD_TXQ_DEPTH 2048
	39	#define BNAD_RXQ_DEPTH 2048
	40
772b5235	41	#define BNAD_MAX_TX 1
8b230ed8 RM	42	#define BNAD_MAX_TXQ_PER_TX 8 /* 8 priority queues */
	43	#define BNAD_TXQ_NUM 1
	44
772b5235 RM	45	#define BNAD_MAX_RX 1
772b5235 RM	46	#define BNAD_MAX_RXP_PER_RX 16
078086f3	47	#define BNAD_MAX_RXQ_PER_RXP 2
8b230ed8 RM	48
	49	/*
	50	* Control structure pointed to ccb->ctrl, which
	51	* determines the NAPI / LRO behavior CCB
	52	* There is 1:1 corres. between ccb & ctrl
	53	*/
	54	struct bnad_rx_ctrl {
	55	struct bna_ccb *ccb;
2be67144	56	struct bnad *bnad;
be7fa326	57	unsigned long flags;
8b230ed8	58	struct napi_struct napi;
271e8b79 RM	59	u64 rx_intr_ctr;
	60	u64 rx_poll_ctr;
	61	u64 rx_schedule;
	62	u64 rx_keep_poll;
	63	u64 rx_complete;
8b230ed8 RM	64	};
	65
	66	#define BNAD_RXMODE_PROMISC_DEFAULT BNA_RXMODE_PROMISC
	67
8b230ed8 RM	68	/*
	69	* GLOBAL #defines (CONSTANTS)
	70	*/
	71	#define BNAD_NAME "bna"
	72	#define BNAD_NAME_LEN 64
	73
45e98341	74	#define BNAD_VERSION "3.2.21.1"
8b230ed8	75
8811e267	76	#define BNAD_MAILBOX_MSIX_INDEX 0
8b230ed8	77	#define BNAD_MAILBOX_MSIX_VECTORS 1
8811e267 RM	78	#define BNAD_INTX_TX_IB_BITMASK 0x1
8811e267 RM	79	#define BNAD_INTX_RX_IB_BITMASK 0x2
8b230ed8	80
0120b99c RM	81	#define BNAD_STATS_TIMER_FREQ 1000 /* in msecs */
0120b99c RM	82	#define BNAD_DIM_TIMER_FREQ 1000 /* in msecs */
8b230ed8	83
078086f3 RM	84	#define BNAD_IOCETH_TIMEOUT 10000
078086f3 RM	85
5216562a RM	86	#define BNAD_MIN_Q_DEPTH 512
	87	#define BNAD_MAX_RXQ_DEPTH 2048
	88	#define BNAD_MAX_TXQ_DEPTH 2048
41eb5ba4	89
8b230ed8 RM	90	#define BNAD_JUMBO_MTU 9000
	91
	92	#define BNAD_NETIF_WAKE_THRESHOLD 8
	93
	94	#define BNAD_RXQ_REFILL_THRESHOLD_SHIFT 3
	95
	96	/* Bit positions for tcb->flags */
	97	#define BNAD_TXQ_FREE_SENT 0
be7fa326	98	#define BNAD_TXQ_TX_STARTED 1
8b230ed8 RM	99
8b230ed8 RM	100	/* Bit positions for rcb->flags */
5216562a RM	101	#define BNAD_RXQ_STARTED 0
5216562a RM	102	#define BNAD_RXQ_POST_OK 1
8b230ed8	103
078086f3 RM	104	/* Resource limits */
	105	#define BNAD_NUM_TXQ (bnad->num_tx * bnad->num_txq_per_tx)
	106	#define BNAD_NUM_RXP (bnad->num_rx * bnad->num_rxp_per_rx)
	107
8b230ed8 RM	108	/*
	109	* DATA STRUCTURES
	110	*/
	111
	112	/* enums */
	113	enum bnad_intr_source {
	114	BNAD_INTR_TX = 1,
	115	BNAD_INTR_RX = 2
	116	};
	117
	118	enum bnad_link_state {
	119	BNAD_LS_DOWN = 0,
0120b99c	120	BNAD_LS_UP = 1
8b230ed8 RM	121	};
8b230ed8 RM	122
72a9730b KG	123	struct bnad_iocmd_comp {
	124	struct bnad *bnad;
	125	struct completion comp;
	126	int comp_status;
	127	};
	128
8b230ed8	129	struct bnad_completion {
0120b99c RM	130	struct completion ioc_comp;
0120b99c RM	131	struct completion ucast_comp;
8b230ed8 RM	132	struct completion mcast_comp;
	133	struct completion tx_comp;
	134	struct completion rx_comp;
	135	struct completion stats_comp;
078086f3 RM	136	struct completion enet_comp;
078086f3 RM	137	struct completion mtu_comp;
8b230ed8 RM	138
	139	u8 ioc_comp_status;
	140	u8 ucast_comp_status;
	141	u8 mcast_comp_status;
	142	u8 tx_comp_status;
	143	u8 rx_comp_status;
	144	u8 stats_comp_status;
	145	u8 port_comp_status;
078086f3	146	u8 mtu_comp_status;
8b230ed8 RM	147	};
	148
	149	/* Tx Rx Control Stats */
	150	struct bnad_drv_stats {
0120b99c	151	u64 netif_queue_stop;
8b230ed8	152	u64 netif_queue_wakeup;
f7c0fa4c	153	u64 netif_queue_stopped;
8b230ed8 RM	154	u64 tso4;
	155	u64 tso6;
	156	u64 tso_err;
	157	u64 tcpcsum_offload;
	158	u64 udpcsum_offload;
	159	u64 csum_help;
271e8b79 RM	160	u64 tx_skb_too_short;
	161	u64 tx_skb_stopping;
	162	u64 tx_skb_max_vectors;
	163	u64 tx_skb_mss_too_long;
	164	u64 tx_skb_tso_too_short;
	165	u64 tx_skb_tso_prepare;
	166	u64 tx_skb_non_tso_too_long;
	167	u64 tx_skb_tcp_hdr;
	168	u64 tx_skb_udp_hdr;
	169	u64 tx_skb_csum_err;
	170	u64 tx_skb_headlen_too_long;
	171	u64 tx_skb_headlen_zero;
	172	u64 tx_skb_frag_zero;
	173	u64 tx_skb_len_mismatch;
8b230ed8 RM	174
8b230ed8 RM	175	u64 hw_stats_updates;
8b230ed8 RM	176	u64 netif_rx_dropped;
	177
	178	u64 link_toggle;
078086f3	179	u64 cee_toggle;
8b230ed8 RM	180
	181	u64 rxp_info_alloc_failed;
	182	u64 mbox_intr_disabled;
	183	u64 mbox_intr_enabled;
	184	u64 tx_unmap_q_alloc_failed;
	185	u64 rx_unmap_q_alloc_failed;
	186
	187	u64 rxbuf_alloc_failed;
	188	};
	189
	190	/* Complete driver stats */
	191	struct bnad_stats {
	192	struct bnad_drv_stats drv_stats;
	193	struct bna_stats *bna_stats;
	194	};
	195
	196	/* Tx / Rx Resources */
	197	struct bnad_tx_res_info {
	198	struct bna_res_info res_info[BNA_TX_RES_T_MAX];
	199	};
	200
	201	struct bnad_rx_res_info {
	202	struct bna_res_info res_info[BNA_RX_RES_T_MAX];
	203	};
	204
	205	struct bnad_tx_info {
	206	struct bna_tx tx; / 1:1 between tx_info & tx */
	207	struct bna_tcb *tcb[BNAD_MAX_TXQ_PER_TX];
078086f3	208	u32 tx_id;
01b54b14	209	struct delayed_work tx_cleanup_work;
8b230ed8 RM	210	} ____cacheline_aligned;
	211
	212	struct bnad_rx_info {
	213	struct bna_rx rx; / 1:1 between rx_info & rx */
	214
772b5235	215	struct bnad_rx_ctrl rx_ctrl[BNAD_MAX_RXP_PER_RX];
078086f3	216	u32 rx_id;
01b54b14	217	struct work_struct rx_cleanup_work;
8b230ed8 RM	218	} ____cacheline_aligned;
8b230ed8 RM	219
5216562a RM	220	struct bnad_tx_vector {
	221	DEFINE_DMA_UNMAP_ADDR(dma_addr);
	222	};
	223
	224	struct bnad_tx_unmap {
8b230ed8	225	struct sk_buff *skb;
5216562a RM	226	u32 nvecs;
	227	struct bnad_tx_vector vectors[BFI_TX_MAX_VECTORS_PER_WI];
	228	};
	229
	230	struct bnad_rx_vector {
5ea74318	231	DEFINE_DMA_UNMAP_ADDR(dma_addr);
5216562a	232	u32 len;
8b230ed8 RM	233	};
8b230ed8 RM	234
5216562a	235	struct bnad_rx_unmap {
30f9fc94 RM	236	struct page *page;
30f9fc94 RM	237	u32 page_offset;
5216562a RM	238	struct sk_buff *skb;
5216562a RM	239	struct bnad_rx_vector vector;
8b230ed8 RM	240	};
8b230ed8 RM	241
30f9fc94 RM	242	enum bnad_rxbuf_type {
	243	BNAD_RXBUF_NONE = 0,
	244	BNAD_RXBUF_SKB = 1,
	245	BNAD_RXBUF_PAGE = 2,
	246	BNAD_RXBUF_MULTI = 3
	247	};
	248
	249	#define BNAD_RXBUF_IS_PAGE(_type) ((_type) == BNAD_RXBUF_PAGE)
	250
	251	struct bnad_rx_unmap_q {
	252	int reuse_pi;
	253	int alloc_order;
	254	u32 map_size;
	255	enum bnad_rxbuf_type type;
	256	struct bnad_rx_unmap unmap[0];
	257	};
	258
8b230ed8 RM	259	/* Bit mask values for bnad->cfg_flags */
	260	#define BNAD_CF_DIM_ENABLED 0x01 /* DIM */
	261	#define BNAD_CF_PROMISC 0x02
	262	#define BNAD_CF_ALLMULTI 0x04
fe1624cf RM	263	#define BNAD_CF_DEFAULT 0x08
fe1624cf RM	264	#define BNAD_CF_MSIX 0x10 /* If in MSIx mode */
8b230ed8 RM	265
	266	/* Defines for run_flags bit-mask */
	267	/* Set, tested & cleared using xxx_bit() functions */
	268	/* Values indicated bit positions */
078086f3 RM	269	#define BNAD_RF_CEE_RUNNING 0
078086f3 RM	270	#define BNAD_RF_MTU_SET 1
be7fa326	271	#define BNAD_RF_MBOX_IRQ_DISABLED 2
078086f3	272	#define BNAD_RF_NETDEV_REGISTERED 3
be7fa326 RM	273	#define BNAD_RF_DIM_TIMER_RUNNING 4
be7fa326 RM	274	#define BNAD_RF_STATS_TIMER_RUNNING 5
078086f3 RM	275	#define BNAD_RF_TX_PRIO_SET 6
078086f3 RM	276
8b230ed8	277	struct bnad {
0120b99c	278	struct net_device *netdev;
72a9730b KG	279	u32 id;
72a9730b KG	280	struct list_head list_entry;
8b230ed8 RM	281
8b230ed8 RM	282	/* Data path */
772b5235 RM	283	struct bnad_tx_info tx_info[BNAD_MAX_TX];
772b5235 RM	284	struct bnad_rx_info rx_info[BNAD_MAX_RX];
8b230ed8	285
f859d7cb	286	unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
8b230ed8 RM	287	/*
	288	* These q numbers are global only because
	289	* they are used to calculate MSIx vectors.
	290	* Actually the exact # of queues are per Tx/Rx
	291	* object.
	292	*/
	293	u32 num_tx;
	294	u32 num_rx;
	295	u32 num_txq_per_tx;
	296	u32 num_rxp_per_rx;
	297
	298	u32 txq_depth;
	299	u32 rxq_depth;
	300
	301	u8 tx_coalescing_timeo;
	302	u8 rx_coalescing_timeo;
	303
5e46631f RM	304	struct bna_rx_config rx_config[BNAD_MAX_RX] ____cacheline_aligned;
5e46631f RM	305	struct bna_tx_config tx_config[BNAD_MAX_TX] ____cacheline_aligned;
8b230ed8	306
8b230ed8 RM	307	void __iomem bar0; / BAR0 address */
	308
	309	struct bna bna;
	310
	311	u32 cfg_flags;
	312	unsigned long run_flags;
	313
0120b99c	314	struct pci_dev *pcidev;
8b230ed8 RM	315	u64 mmio_start;
	316	u64 mmio_len;
	317
	318	u32 msix_num;
8b230ed8 RM	319	struct msix_entry *msix_table;
	320
	321	struct mutex conf_mutex;
	322	spinlock_t bna_lock ____cacheline_aligned;
	323
	324	/* Timers */
	325	struct timer_list ioc_timer;
	326	struct timer_list dim_timer;
	327	struct timer_list stats_timer;
	328
	329	/* Control path resources, memory & irq */
	330	struct bna_res_info res_info[BNA_RES_T_MAX];
078086f3	331	struct bna_res_info mod_res_info[BNA_MOD_RES_T_MAX];
772b5235 RM	332	struct bnad_tx_res_info tx_res_info[BNAD_MAX_TX];
772b5235 RM	333	struct bnad_rx_res_info rx_res_info[BNAD_MAX_RX];
8b230ed8 RM	334
	335	struct bnad_completion bnad_completions;
	336
	337	/* Burnt in MAC address */
	338	mac_t perm_addr;
	339
01b54b14	340	struct workqueue_struct *work_q;
8b230ed8 RM	341
	342	/* Statistics */
	343	struct bnad_stats stats;
8b230ed8 RM	344
	345	struct bnad_diag *diag;
	346
	347	char adapter_name[BNAD_NAME_LEN];
0120b99c	348	char port_name[BNAD_NAME_LEN];
8b230ed8	349	char mbox_irq_name[BNAD_NAME_LEN];
01b54b14	350	char wq_name[BNAD_NAME_LEN];
7afc5dbd KG	351
	352	/* debugfs specific data */
	353	char *regdata;
	354	u32 reglen;
	355	struct dentry *bnad_dentry_files[5];
	356	struct dentry *port_debugfs_root;
	357	};
	358
	359	struct bnad_drvinfo {
	360	struct bfa_ioc_attr ioc_attr;
	361	struct bfa_cee_attr cee_attr;
	362	struct bfa_flash_attr flash_attr;
	363	u32 cee_status;
	364	u32 flash_status;
8b230ed8 RM	365	};
	366
	367	/*
	368	* EXTERN VARIABLES
	369	*/
e1e0918f	370	extern const struct firmware *bfi_fw;
8b230ed8 RM	371
	372	/*
	373	* EXTERN PROTOTYPES
	374	*/
49ca19bd	375	u32 cna_get_firmware_buf(struct pci_dev pdev);
8b230ed8	376	/* Netdev entry point prototypes */
49ca19bd JP	377	void bnad_set_rx_mode(struct net_device *netdev);
	378	struct net_device_stats bnad_get_netdev_stats(struct net_device netdev);
	379	int bnad_mac_addr_set_locked(struct bnad bnad, u8 mac_addr);
	380	int bnad_enable_default_bcast(struct bnad *bnad);
	381	void bnad_restore_vlans(struct bnad *bnad, u32 rx_id);
	382	void bnad_set_ethtool_ops(struct net_device *netdev);
	383	void bnad_cb_completion(void *arg, enum bfa_status status);
8b230ed8 RM	384
8b230ed8 RM	385	/* Configuration & setup */
49ca19bd JP	386	void bnad_tx_coalescing_timeo_set(struct bnad *bnad);
49ca19bd JP	387	void bnad_rx_coalescing_timeo_set(struct bnad *bnad);
8b230ed8	388
49ca19bd JP	389	int bnad_setup_rx(struct bnad *bnad, u32 rx_id);
	390	int bnad_setup_tx(struct bnad *bnad, u32 tx_id);
	391	void bnad_destroy_tx(struct bnad *bnad, u32 tx_id);
	392	void bnad_destroy_rx(struct bnad *bnad, u32 rx_id);
8b230ed8 RM	393
8b230ed8 RM	394	/* Timer start/stop protos */
49ca19bd	395	void bnad_dim_timer_start(struct bnad *bnad);
8b230ed8 RM	396
8b230ed8 RM	397	/* Statistics */
49ca19bd JP	398	void bnad_netdev_qstats_fill(struct bnad *bnad,
	399	struct rtnl_link_stats64 *stats);
	400	void bnad_netdev_hwstats_fill(struct bnad *bnad,
	401	struct rtnl_link_stats64 *stats);
8b230ed8	402
7afc5dbd	403	/* Debugfs */
49ca19bd JP	404	void bnad_debugfs_init(struct bnad *bnad);
49ca19bd JP	405	void bnad_debugfs_uninit(struct bnad *bnad);
7afc5dbd	406
1aa8b471	407	/* MACROS */
8b230ed8 RM	408	/* To set & get the stats counters */
	409	#define BNAD_UPDATE_CTR(_bnad, _ctr) \
	410	(((_bnad)->stats.drv_stats._ctr)++)
	411
	412	#define BNAD_GET_CTR(_bnad, _ctr) ((_bnad)->stats.drv_stats._ctr)
	413
	414	#define bnad_enable_rx_irq_unsafe(_ccb) \
	415	{ \
271e8b79	416	if (likely(test_bit(BNAD_RXQ_STARTED, &(_ccb)->rcb[0]->flags))) {\
be7fa326 RM	417	bna_ib_coalescing_timer_set((_ccb)->i_dbell, \
	418	(_ccb)->rx_coalescing_timeo); \
	419	bna_ib_ack((_ccb)->i_dbell, 0); \
	420	} \
8b230ed8 RM	421	}
8b230ed8 RM	422
8b230ed8	423	#endif /* __BNAD_H__ */