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Merge tag 'pci-v3.15-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaa...
[deliverable/linux.git] / drivers / net / ethernet / cadence / macb.c
CommitLineData
89e5785f 1/*
f75ba50b 2 * Cadence MACB/GEM Ethernet Controller driver
89e5785f
HS		 3 *
4 * Copyright (C) 2004-2006 Atmel Corporation
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
c220f8cd 11#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
89e5785f
HS		 12#include <linux/clk.h>
13#include <linux/module.h>
14#include <linux/moduleparam.h>
15#include <linux/kernel.h>
16#include <linux/types.h>
909a8583 17#include <linux/circ_buf.h>
89e5785f
HS		 18#include <linux/slab.h>
19#include <linux/init.h>
60fe716f 20#include <linux/io.h>
2dbfdbb9 21#include <linux/gpio.h>
a6b7a407 22#include <linux/interrupt.h>
89e5785f
HS		 23#include <linux/netdevice.h>
24#include <linux/etherdevice.h>
89e5785f 25#include <linux/dma-mapping.h>
84e0cdb0 26#include <linux/platform_data/macb.h>
89e5785f 27#include <linux/platform_device.h>
6c36a707 28#include <linux/phy.h>
b17471f5 29#include <linux/of.h>
fb97a846 30#include <linux/of_device.h>
148cbb53 31#include <linux/of_mdio.h>
fb97a846 32#include <linux/of_net.h>
8ef29f8a 33#include <linux/pinctrl/consumer.h>
89e5785f 34
89e5785f
HS		 35#include "macb.h"
36
1b44791a 37#define MACB_RX_BUFFER_SIZE 128
1b44791a 38#define RX_BUFFER_MULTIPLE 64 /* bytes */
55054a16
HS		 39#define RX_RING_SIZE 512 /* must be power of 2 */
40#define RX_RING_BYTES (sizeof(struct macb_dma_desc) * RX_RING_SIZE)
89e5785f 41
55054a16
HS		 42#define TX_RING_SIZE 128 /* must be power of 2 */
43#define TX_RING_BYTES (sizeof(struct macb_dma_desc) * TX_RING_SIZE)
89e5785f 44
909a8583
NF		 45/* level of occupied TX descriptors under which we wake up TX process */
46#define MACB_TX_WAKEUP_THRESH (3 * TX_RING_SIZE / 4)
89e5785f
HS		 47
48#define MACB_RX_INT_FLAGS (MACB_BIT(RCOMP) | MACB_BIT(RXUBR) \
49 | MACB_BIT(ISR_ROVR))
e86cd53a
NF		 50#define MACB_TX_ERR_FLAGS (MACB_BIT(ISR_TUND) \
51 | MACB_BIT(ISR_RLE) \
52 | MACB_BIT(TXERR))
53#define MACB_TX_INT_FLAGS (MACB_TX_ERR_FLAGS | MACB_BIT(TCOMP))
54
55/*
56 * Graceful stop timeouts in us. We should allow up to
57 * 1 frame time (10 Mbits/s, full-duplex, ignoring collisions)
58 */
59#define MACB_HALT_TIMEOUT 1230
89e5785f 60
55054a16
HS		 61/* Ring buffer accessors */
62static unsigned int macb_tx_ring_wrap(unsigned int index)
63{
64 return index & (TX_RING_SIZE - 1);
65}
66
55054a16
HS		 67static struct macb_dma_desc *macb_tx_desc(struct macb *bp, unsigned int index)
68{
69 return &bp->tx_ring[macb_tx_ring_wrap(index)];
70}
71
72static struct macb_tx_skb *macb_tx_skb(struct macb *bp, unsigned int index)
73{
74 return &bp->tx_skb[macb_tx_ring_wrap(index)];
75}
76
77static dma_addr_t macb_tx_dma(struct macb *bp, unsigned int index)
78{
79 dma_addr_t offset;
80
81 offset = macb_tx_ring_wrap(index) * sizeof(struct macb_dma_desc);
82
83 return bp->tx_ring_dma + offset;
84}
85
86static unsigned int macb_rx_ring_wrap(unsigned int index)
87{
88 return index & (RX_RING_SIZE - 1);
89}
90
91static struct macb_dma_desc *macb_rx_desc(struct macb *bp, unsigned int index)
92{
93 return &bp->rx_ring[macb_rx_ring_wrap(index)];
94}
95
96static void *macb_rx_buffer(struct macb *bp, unsigned int index)
97{
1b44791a 98 return bp->rx_buffers + bp->rx_buffer_size * macb_rx_ring_wrap(index);
55054a16
HS		 99}
100
314bccc4 101void macb_set_hwaddr(struct macb *bp)
89e5785f
HS		 102{
103 u32 bottom;
104 u16 top;
105
106 bottom = cpu_to_le32(*((u32 *)bp->dev->dev_addr));
f75ba50b 107 macb_or_gem_writel(bp, SA1B, bottom);
89e5785f 108 top = cpu_to_le16(*((u16 *)(bp->dev->dev_addr + 4)));
f75ba50b 109 macb_or_gem_writel(bp, SA1T, top);
3629a6ce
JE		 110
111 /* Clear unused address register sets */
112 macb_or_gem_writel(bp, SA2B, 0);
113 macb_or_gem_writel(bp, SA2T, 0);
114 macb_or_gem_writel(bp, SA3B, 0);
115 macb_or_gem_writel(bp, SA3T, 0);
116 macb_or_gem_writel(bp, SA4B, 0);
117 macb_or_gem_writel(bp, SA4T, 0);
89e5785f 118}
314bccc4 119EXPORT_SYMBOL_GPL(macb_set_hwaddr);
89e5785f 120
314bccc4 121void macb_get_hwaddr(struct macb *bp)
89e5785f 122{
d25e78aa 123 struct macb_platform_data *pdata;
89e5785f
HS		 124 u32 bottom;
125 u16 top;
126 u8 addr[6];
17b8bb3e
JE		 127 int i;
128
c607a0d9 129 pdata = dev_get_platdata(&bp->pdev->dev);
d25e78aa 130
17b8bb3e
JE		 131 /* Check all 4 address register for vaild address */
132 for (i = 0; i < 4; i++) {
133 bottom = macb_or_gem_readl(bp, SA1B + i * 8);
134 top = macb_or_gem_readl(bp, SA1T + i * 8);
135
d25e78aa
JE		 136 if (pdata && pdata->rev_eth_addr) {
137 addr[5] = bottom & 0xff;
138 addr[4] = (bottom >> 8) & 0xff;
139 addr[3] = (bottom >> 16) & 0xff;
140 addr[2] = (bottom >> 24) & 0xff;
141 addr[1] = top & 0xff;
142 addr[0] = (top & 0xff00) >> 8;
143 } else {
144 addr[0] = bottom & 0xff;
145 addr[1] = (bottom >> 8) & 0xff;
146 addr[2] = (bottom >> 16) & 0xff;
147 addr[3] = (bottom >> 24) & 0xff;
148 addr[4] = top & 0xff;
149 addr[5] = (top >> 8) & 0xff;
150 }
17b8bb3e
JE		 151
152 if (is_valid_ether_addr(addr)) {
153 memcpy(bp->dev->dev_addr, addr, sizeof(addr));
154 return;
155 }
d1d5741d 156 }
17b8bb3e
JE		 157
158 netdev_info(bp->dev, "invalid hw address, using random\n");
159 eth_hw_addr_random(bp->dev);
89e5785f 160}
314bccc4 161EXPORT_SYMBOL_GPL(macb_get_hwaddr);
89e5785f 162
6c36a707 163static int macb_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
89e5785f 164{
6c36a707 165 struct macb *bp = bus->priv;
89e5785f
HS		 166 int value;
167
89e5785f
HS		 168 macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_SOF)
169 | MACB_BF(RW, MACB_MAN_READ)
6c36a707
R		 170 | MACB_BF(PHYA, mii_id)
171 | MACB_BF(REGA, regnum)
89e5785f
HS		 172 | MACB_BF(CODE, MACB_MAN_CODE)));
173
6c36a707
R		 174 /* wait for end of transfer */
175 while (!MACB_BFEXT(IDLE, macb_readl(bp, NSR)))
176 cpu_relax();
89e5785f
HS		 177
178 value = MACB_BFEXT(DATA, macb_readl(bp, MAN));
89e5785f
HS		 179
180 return value;
181}
182
6c36a707
R		 183static int macb_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
184 u16 value)
89e5785f 185{
6c36a707 186 struct macb *bp = bus->priv;
89e5785f
HS		 187
188 macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_SOF)
189 | MACB_BF(RW, MACB_MAN_WRITE)
6c36a707
R		 190 | MACB_BF(PHYA, mii_id)
191 | MACB_BF(REGA, regnum)
89e5785f 192 | MACB_BF(CODE, MACB_MAN_CODE)
6c36a707 193 | MACB_BF(DATA, value)));
89e5785f 194
6c36a707
R		 195 /* wait for end of transfer */
196 while (!MACB_BFEXT(IDLE, macb_readl(bp, NSR)))
197 cpu_relax();
198
199 return 0;
200}
89e5785f 201
6c36a707
R		 202static int macb_mdio_reset(struct mii_bus *bus)
203{
204 return 0;
89e5785f
HS		 205}
206
e1824dfe
SB		 207/**
208 * macb_set_tx_clk() - Set a clock to a new frequency
209 * @clk Pointer to the clock to change
210 * @rate New frequency in Hz
211 * @dev Pointer to the struct net_device
212 */
213static void macb_set_tx_clk(struct clk *clk, int speed, struct net_device *dev)
214{
215 long ferr, rate, rate_rounded;
216
217 switch (speed) {
218 case SPEED_10:
219 rate = 2500000;
220 break;
221 case SPEED_100:
222 rate = 25000000;
223 break;
224 case SPEED_1000:
225 rate = 125000000;
226 break;
227 default:
9319e47c 228 return;
e1824dfe
SB		 229 }
230
231 rate_rounded = clk_round_rate(clk, rate);
232 if (rate_rounded < 0)
233 return;
234
235 /* RGMII allows 50 ppm frequency error. Test and warn if this limit
236 * is not satisfied.
237 */
238 ferr = abs(rate_rounded - rate);
239 ferr = DIV_ROUND_UP(ferr, rate / 100000);
240 if (ferr > 5)
241 netdev_warn(dev, "unable to generate target frequency: %ld Hz\n",
242 rate);
243
244 if (clk_set_rate(clk, rate_rounded))
245 netdev_err(dev, "adjusting tx_clk failed.\n");
246}
247
6c36a707 248static void macb_handle_link_change(struct net_device *dev)
89e5785f 249{
6c36a707
R		 250 struct macb *bp = netdev_priv(dev);
251 struct phy_device *phydev = bp->phy_dev;
252 unsigned long flags;
89e5785f 253
6c36a707 254 int status_change = 0;
89e5785f 255
6c36a707
R		 256 spin_lock_irqsave(&bp->lock, flags);
257
258 if (phydev->link) {
259 if ((bp->speed != phydev->speed) ||
260 (bp->duplex != phydev->duplex)) {
261 u32 reg;
262
263 reg = macb_readl(bp, NCFGR);
264 reg &= ~(MACB_BIT(SPD) | MACB_BIT(FD));
140b7552
PV		 265 if (macb_is_gem(bp))
266 reg &= ~GEM_BIT(GBE);
6c36a707
R		 267
268 if (phydev->duplex)
269 reg |= MACB_BIT(FD);
179956f4 270 if (phydev->speed == SPEED_100)
6c36a707 271 reg |= MACB_BIT(SPD);
140b7552
PV		 272 if (phydev->speed == SPEED_1000)
273 reg |= GEM_BIT(GBE);
6c36a707 274
140b7552 275 macb_or_gem_writel(bp, NCFGR, reg);
6c36a707
R		 276
277 bp->speed = phydev->speed;
278 bp->duplex = phydev->duplex;
279 status_change = 1;
280 }
89e5785f
HS		 281 }
282
6c36a707 283 if (phydev->link != bp->link) {
c8f15686 284 if (!phydev->link) {
6c36a707
R		 285 bp->speed = 0;
286 bp->duplex = -1;
287 }
288 bp->link = phydev->link;
89e5785f 289
6c36a707
R		 290 status_change = 1;
291 }
89e5785f 292
6c36a707
R		 293 spin_unlock_irqrestore(&bp->lock, flags);
294
e1824dfe
SB		 295 if (!IS_ERR(bp->tx_clk))
296 macb_set_tx_clk(bp->tx_clk, phydev->speed, dev);
297
6c36a707 298 if (status_change) {
03fc4721
NF		 299 if (phydev->link) {
300 netif_carrier_on(dev);
c220f8cd
JI		 301 netdev_info(dev, "link up (%d/%s)\n",
302 phydev->speed,
303 phydev->duplex == DUPLEX_FULL ?
304 "Full" : "Half");
03fc4721
NF		 305 } else {
306 netif_carrier_off(dev);
c220f8cd 307 netdev_info(dev, "link down\n");
03fc4721 308 }
6c36a707 309 }
89e5785f
HS		 310}
311
6c36a707
R		 312/* based on au1000_eth. c*/
313static int macb_mii_probe(struct net_device *dev)
89e5785f 314{
6c36a707 315 struct macb *bp = netdev_priv(dev);
2dbfdbb9 316 struct macb_platform_data *pdata;
7455a76f 317 struct phy_device *phydev;
2dbfdbb9 318 int phy_irq;
7455a76f 319 int ret;
6c36a707 320
7455a76f 321 phydev = phy_find_first(bp->mii_bus);
6c36a707 322 if (!phydev) {
c220f8cd 323 netdev_err(dev, "no PHY found\n");
7daa78e3 324 return -ENXIO;
6c36a707
R		 325 }
326
2dbfdbb9
JE		 327 pdata = dev_get_platdata(&bp->pdev->dev);
328 if (pdata && gpio_is_valid(pdata->phy_irq_pin)) {
329 ret = devm_gpio_request(&bp->pdev->dev, pdata->phy_irq_pin, "phy int");
330 if (!ret) {
331 phy_irq = gpio_to_irq(pdata->phy_irq_pin);
332 phydev->irq = (phy_irq < 0) ? PHY_POLL : phy_irq;
333 }
334 }
6c36a707
R		 335
336 /* attach the mac to the phy */
f9a8f83b 337 ret = phy_connect_direct(dev, phydev, &macb_handle_link_change,
fb97a846 338 bp->phy_interface);
7455a76f 339 if (ret) {
c220f8cd 340 netdev_err(dev, "Could not attach to PHY\n");
7455a76f 341 return ret;
6c36a707
R		 342 }
343
344 /* mask with MAC supported features */
140b7552
PV		 345 if (macb_is_gem(bp))
346 phydev->supported &= PHY_GBIT_FEATURES;
347 else
348 phydev->supported &= PHY_BASIC_FEATURES;
6c36a707
R		 349
350 phydev->advertising = phydev->supported;
351
352 bp->link = 0;
353 bp->speed = 0;
354 bp->duplex = -1;
355 bp->phy_dev = phydev;
356
357 return 0;
89e5785f
HS		 358}
359
0005f541 360int macb_mii_init(struct macb *bp)
89e5785f 361{
84e0cdb0 362 struct macb_platform_data *pdata;
148cbb53 363 struct device_node *np;
6c36a707 364 int err = -ENXIO, i;
89e5785f 365
3dbda77e 366 /* Enable management port */
6c36a707 367 macb_writel(bp, NCR, MACB_BIT(MPE));
89e5785f 368
298cf9be
LB		 369 bp->mii_bus = mdiobus_alloc();
370 if (bp->mii_bus == NULL) {
371 err = -ENOMEM;
372 goto err_out;
373 }
374
375 bp->mii_bus->name = "MACB_mii_bus";
376 bp->mii_bus->read = &macb_mdio_read;
377 bp->mii_bus->write = &macb_mdio_write;
378 bp->mii_bus->reset = &macb_mdio_reset;
98d5e57e
FF		 379 snprintf(bp->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
380 bp->pdev->name, bp->pdev->id);
298cf9be
LB		 381 bp->mii_bus->priv = bp;
382 bp->mii_bus->parent = &bp->dev->dev;
c607a0d9 383 pdata = dev_get_platdata(&bp->pdev->dev);
89e5785f 384
298cf9be
LB		 385 bp->mii_bus->irq = kmalloc(sizeof(int)*PHY_MAX_ADDR, GFP_KERNEL);
386 if (!bp->mii_bus->irq) {
6c36a707 387 err = -ENOMEM;
298cf9be 388 goto err_out_free_mdiobus;
89e5785f
HS		 389 }
390
91523947 391 dev_set_drvdata(&bp->dev->dev, bp->mii_bus);
89e5785f 392
148cbb53
BB		 393 np = bp->pdev->dev.of_node;
394 if (np) {
395 /* try dt phy registration */
396 err = of_mdiobus_register(bp->mii_bus, np);
397
398 /* fallback to standard phy registration if no phy were
399 found during dt phy registration */
400 if (!err && !phy_find_first(bp->mii_bus)) {
401 for (i = 0; i < PHY_MAX_ADDR; i++) {
402 struct phy_device *phydev;
403
404 phydev = mdiobus_scan(bp->mii_bus, i);
405 if (IS_ERR(phydev)) {
406 err = PTR_ERR(phydev);
407 break;
408 }
409 }
410
411 if (err)
412 goto err_out_unregister_bus;
413 }
414 } else {
415 for (i = 0; i < PHY_MAX_ADDR; i++)
416 bp->mii_bus->irq[i] = PHY_POLL;
417
418 if (pdata)
419 bp->mii_bus->phy_mask = pdata->phy_mask;
420
421 err = mdiobus_register(bp->mii_bus);
422 }
423
424 if (err)
6c36a707 425 goto err_out_free_mdio_irq;
89e5785f 426
7daa78e3
BB		 427 err = macb_mii_probe(bp->dev);
428 if (err)
6c36a707 429 goto err_out_unregister_bus;
89e5785f 430
6c36a707 431 return 0;
89e5785f 432
6c36a707 433err_out_unregister_bus:
298cf9be 434 mdiobus_unregister(bp->mii_bus);
6c36a707 435err_out_free_mdio_irq:
298cf9be
LB		 436 kfree(bp->mii_bus->irq);
437err_out_free_mdiobus:
438 mdiobus_free(bp->mii_bus);
6c36a707
R		 439err_out:
440 return err;
89e5785f 441}
0005f541 442EXPORT_SYMBOL_GPL(macb_mii_init);
89e5785f
HS		 443
444static void macb_update_stats(struct macb *bp)
445{
446 u32 __iomem *reg = bp->regs + MACB_PFR;
a494ed8e
JI		 447 u32 *p = &bp->hw_stats.macb.rx_pause_frames;
448 u32 *end = &bp->hw_stats.macb.tx_pause_frames + 1;
89e5785f
HS		 449
450 WARN_ON((unsigned long)(end - p - 1) != (MACB_TPF - MACB_PFR) / 4);
451
452 for(; p < end; p++, reg++)
0f0d84e5 453 *p += __raw_readl(reg);
89e5785f
HS		 454}
455
e86cd53a 456static int macb_halt_tx(struct macb *bp)
89e5785f 457{
e86cd53a
NF		 458 unsigned long halt_time, timeout;
459 u32 status;
89e5785f 460
e86cd53a 461 macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(THALT));
89e5785f 462
e86cd53a
NF		 463 timeout = jiffies + usecs_to_jiffies(MACB_HALT_TIMEOUT);
464 do {
465 halt_time = jiffies;
466 status = macb_readl(bp, TSR);
467 if (!(status & MACB_BIT(TGO)))
468 return 0;
89e5785f 469
e86cd53a
NF		 470 usleep_range(10, 250);
471 } while (time_before(halt_time, timeout));
bdcba151 472
e86cd53a
NF		 473 return -ETIMEDOUT;
474}
39eddb4c 475
e86cd53a
NF		 476static void macb_tx_error_task(struct work_struct *work)
477{
478 struct macb *bp = container_of(work, struct macb, tx_error_task);
479 struct macb_tx_skb *tx_skb;
480 struct sk_buff *skb;
481 unsigned int tail;
bdcba151 482
e86cd53a
NF		 483 netdev_vdbg(bp->dev, "macb_tx_error_task: t = %u, h = %u\n",
484 bp->tx_tail, bp->tx_head);
bdcba151 485
e86cd53a
NF		 486 /* Make sure nobody is trying to queue up new packets */
487 netif_stop_queue(bp->dev);
d3e61457 488
e86cd53a
NF		 489 /*
490 * Stop transmission now
491 * (in case we have just queued new packets)
492 */
493 if (macb_halt_tx(bp))
494 /* Just complain for now, reinitializing TX path can be good */
495 netdev_err(bp->dev, "BUG: halt tx timed out\n");
bdcba151 496
e86cd53a 497 /* No need for the lock here as nobody will interrupt us anymore */
bdcba151 498
e86cd53a
NF		 499 /*
500 * Treat frames in TX queue including the ones that caused the error.
501 * Free transmit buffers in upper layer.
502 */
503 for (tail = bp->tx_tail; tail != bp->tx_head; tail++) {
504 struct macb_dma_desc *desc;
505 u32 ctrl;
55054a16 506
e86cd53a
NF		 507 desc = macb_tx_desc(bp, tail);
508 ctrl = desc->ctrl;
509 tx_skb = macb_tx_skb(bp, tail);
510 skb = tx_skb->skb;
bdcba151 511
e86cd53a
NF		 512 if (ctrl & MACB_BIT(TX_USED)) {
513 netdev_vdbg(bp->dev, "txerr skb %u (data %p) TX complete\n",
514 macb_tx_ring_wrap(tail), skb->data);
515 bp->stats.tx_packets++;
516 bp->stats.tx_bytes += skb->len;
517 } else {
518 /*
519 * "Buffers exhausted mid-frame" errors may only happen
520 * if the driver is buggy, so complain loudly about those.
521 * Statistics are updated by hardware.
522 */
523 if (ctrl & MACB_BIT(TX_BUF_EXHAUSTED))
524 netdev_err(bp->dev,
525 "BUG: TX buffers exhausted mid-frame\n");
39eddb4c 526
e86cd53a
NF		 527 desc->ctrl = ctrl | MACB_BIT(TX_USED);
528 }
529
530 dma_unmap_single(&bp->pdev->dev, tx_skb->mapping, skb->len,
531 DMA_TO_DEVICE);
532 tx_skb->skb = NULL;
533 dev_kfree_skb(skb);
89e5785f
HS		 534 }
535
e86cd53a
NF		 536 /* Make descriptor updates visible to hardware */
537 wmb();
538
539 /* Reinitialize the TX desc queue */
540 macb_writel(bp, TBQP, bp->tx_ring_dma);
541 /* Make TX ring reflect state of hardware */
542 bp->tx_head = bp->tx_tail = 0;
543
544 /* Now we are ready to start transmission again */
545 netif_wake_queue(bp->dev);
546
547 /* Housework before enabling TX IRQ */
548 macb_writel(bp, TSR, macb_readl(bp, TSR));
549 macb_writel(bp, IER, MACB_TX_INT_FLAGS);
550}
551
552static void macb_tx_interrupt(struct macb *bp)
553{
554 unsigned int tail;
555 unsigned int head;
556 u32 status;
557
558 status = macb_readl(bp, TSR);
559 macb_writel(bp, TSR, status);
560
581df9e1
NF		 561 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
562 macb_writel(bp, ISR, MACB_BIT(TCOMP));
749a2b66 563
e86cd53a
NF		 564 netdev_vdbg(bp->dev, "macb_tx_interrupt status = 0x%03lx\n",
565 (unsigned long)status);
89e5785f
HS		 566
567 head = bp->tx_head;
55054a16
HS		 568 for (tail = bp->tx_tail; tail != head; tail++) {
569 struct macb_tx_skb *tx_skb;
570 struct sk_buff *skb;
571 struct macb_dma_desc *desc;
572 u32 ctrl;
89e5785f 573
55054a16 574 desc = macb_tx_desc(bp, tail);
89e5785f 575
03dbe05f 576 /* Make hw descriptor updates visible to CPU */
89e5785f 577 rmb();
03dbe05f 578
55054a16 579 ctrl = desc->ctrl;
89e5785f 580
55054a16 581 if (!(ctrl & MACB_BIT(TX_USED)))
89e5785f
HS		 582 break;
583
55054a16
HS		 584 tx_skb = macb_tx_skb(bp, tail);
585 skb = tx_skb->skb;
586
a268adb1 587 netdev_vdbg(bp->dev, "skb %u (data %p) TX complete\n",
55054a16
HS		 588 macb_tx_ring_wrap(tail), skb->data);
589 dma_unmap_single(&bp->pdev->dev, tx_skb->mapping, skb->len,
89e5785f
HS		 590 DMA_TO_DEVICE);
591 bp->stats.tx_packets++;
592 bp->stats.tx_bytes += skb->len;
55054a16 593 tx_skb->skb = NULL;
89e5785f
HS		 594 dev_kfree_skb_irq(skb);
595 }
596
597 bp->tx_tail = tail;
55054a16 598 if (netif_queue_stopped(bp->dev)
909a8583
NF		 599 && CIRC_CNT(bp->tx_head, bp->tx_tail,
600 TX_RING_SIZE) <= MACB_TX_WAKEUP_THRESH)
89e5785f
HS		 601 netif_wake_queue(bp->dev);
602}
603
4df95131
NF		 604static void gem_rx_refill(struct macb *bp)
605{
606 unsigned int entry;
607 struct sk_buff *skb;
608 struct macb_dma_desc *desc;
609 dma_addr_t paddr;
610
611 while (CIRC_SPACE(bp->rx_prepared_head, bp->rx_tail, RX_RING_SIZE) > 0) {
612 u32 addr, ctrl;
613
614 entry = macb_rx_ring_wrap(bp->rx_prepared_head);
615 desc = &bp->rx_ring[entry];
616
617 /* Make hw descriptor updates visible to CPU */
618 rmb();
619
620 addr = desc->addr;
621 ctrl = desc->ctrl;
622 bp->rx_prepared_head++;
623
624 if ((addr & MACB_BIT(RX_USED)))
625 continue;
626
627 if (bp->rx_skbuff[entry] == NULL) {
628 /* allocate sk_buff for this free entry in ring */
629 skb = netdev_alloc_skb(bp->dev, bp->rx_buffer_size);
630 if (unlikely(skb == NULL)) {
631 netdev_err(bp->dev,
632 "Unable to allocate sk_buff\n");
633 break;
634 }
4df95131
NF		 635
636 /* now fill corresponding descriptor entry */
637 paddr = dma_map_single(&bp->pdev->dev, skb->data,
638 bp->rx_buffer_size, DMA_FROM_DEVICE);
92030908
SB		 639 if (dma_mapping_error(&bp->pdev->dev, paddr)) {
640 dev_kfree_skb(skb);
641 break;
642 }
643
644 bp->rx_skbuff[entry] = skb;
4df95131
NF		 645
646 if (entry == RX_RING_SIZE - 1)
647 paddr |= MACB_BIT(RX_WRAP);
648 bp->rx_ring[entry].addr = paddr;
649 bp->rx_ring[entry].ctrl = 0;
650
651 /* properly align Ethernet header */
652 skb_reserve(skb, NET_IP_ALIGN);
653 }
654 }
655
656 /* Make descriptor updates visible to hardware */
657 wmb();
658
659 netdev_vdbg(bp->dev, "rx ring: prepared head %d, tail %d\n",
660 bp->rx_prepared_head, bp->rx_tail);
661}
662
663/* Mark DMA descriptors from begin up to and not including end as unused */
664static void discard_partial_frame(struct macb *bp, unsigned int begin,
665 unsigned int end)
666{
667 unsigned int frag;
668
669 for (frag = begin; frag != end; frag++) {
670 struct macb_dma_desc *desc = macb_rx_desc(bp, frag);
671 desc->addr &= ~MACB_BIT(RX_USED);
672 }
673
674 /* Make descriptor updates visible to hardware */
675 wmb();
676
677 /*
678 * When this happens, the hardware stats registers for
679 * whatever caused this is updated, so we don't have to record
680 * anything.
681 */
682}
683
684static int gem_rx(struct macb *bp, int budget)
685{
686 unsigned int len;
687 unsigned int entry;
688 struct sk_buff *skb;
689 struct macb_dma_desc *desc;
690 int count = 0;
691
692 while (count < budget) {
693 u32 addr, ctrl;
694
695 entry = macb_rx_ring_wrap(bp->rx_tail);
696 desc = &bp->rx_ring[entry];
697
698 /* Make hw descriptor updates visible to CPU */
699 rmb();
700
701 addr = desc->addr;
702 ctrl = desc->ctrl;
703
704 if (!(addr & MACB_BIT(RX_USED)))
705 break;
706
707 desc->addr &= ~MACB_BIT(RX_USED);
708 bp->rx_tail++;
709 count++;
710
711 if (!(ctrl & MACB_BIT(RX_SOF) && ctrl & MACB_BIT(RX_EOF))) {
712 netdev_err(bp->dev,
713 "not whole frame pointed by descriptor\n");
714 bp->stats.rx_dropped++;
715 break;
716 }
717 skb = bp->rx_skbuff[entry];
718 if (unlikely(!skb)) {
719 netdev_err(bp->dev,
720 "inconsistent Rx descriptor chain\n");
721 bp->stats.rx_dropped++;
722 break;
723 }
724 /* now everything is ready for receiving packet */
725 bp->rx_skbuff[entry] = NULL;
726 len = MACB_BFEXT(RX_FRMLEN, ctrl);
727
728 netdev_vdbg(bp->dev, "gem_rx %u (len %u)\n", entry, len);
729
730 skb_put(skb, len);
731 addr = MACB_BF(RX_WADDR, MACB_BFEXT(RX_WADDR, addr));
732 dma_unmap_single(&bp->pdev->dev, addr,
48330e08 733 bp->rx_buffer_size, DMA_FROM_DEVICE);
4df95131
NF		 734
735 skb->protocol = eth_type_trans(skb, bp->dev);
736 skb_checksum_none_assert(skb);
737
738 bp->stats.rx_packets++;
739 bp->stats.rx_bytes += skb->len;
740
741#if defined(DEBUG) && defined(VERBOSE_DEBUG)
742 netdev_vdbg(bp->dev, "received skb of length %u, csum: %08x\n",
743 skb->len, skb->csum);
744 print_hex_dump(KERN_DEBUG, " mac: ", DUMP_PREFIX_ADDRESS, 16, 1,
745 skb->mac_header, 16, true);
746 print_hex_dump(KERN_DEBUG, "data: ", DUMP_PREFIX_ADDRESS, 16, 1,
747 skb->data, 32, true);
748#endif
749
750 netif_receive_skb(skb);
751 }
752
753 gem_rx_refill(bp);
754
755 return count;
756}
757
89e5785f
HS		 758static int macb_rx_frame(struct macb *bp, unsigned int first_frag,
759 unsigned int last_frag)
760{
761 unsigned int len;
762 unsigned int frag;
29bc2e1e 763 unsigned int offset;
89e5785f 764 struct sk_buff *skb;
55054a16 765 struct macb_dma_desc *desc;
89e5785f 766
55054a16
HS		 767 desc = macb_rx_desc(bp, last_frag);
768 len = MACB_BFEXT(RX_FRMLEN, desc->ctrl);
89e5785f 769
a268adb1 770 netdev_vdbg(bp->dev, "macb_rx_frame frags %u - %u (len %u)\n",
55054a16
HS		 771 macb_rx_ring_wrap(first_frag),
772 macb_rx_ring_wrap(last_frag), len);
89e5785f 773
29bc2e1e
HS		 774 /*
775 * The ethernet header starts NET_IP_ALIGN bytes into the
776 * first buffer. Since the header is 14 bytes, this makes the
777 * payload word-aligned.
778 *
779 * Instead of calling skb_reserve(NET_IP_ALIGN), we just copy
780 * the two padding bytes into the skb so that we avoid hitting
781 * the slowpath in memcpy(), and pull them off afterwards.
782 */
783 skb = netdev_alloc_skb(bp->dev, len + NET_IP_ALIGN);
89e5785f
HS		 784 if (!skb) {
785 bp->stats.rx_dropped++;
55054a16
HS		 786 for (frag = first_frag; ; frag++) {
787 desc = macb_rx_desc(bp, frag);
788 desc->addr &= ~MACB_BIT(RX_USED);
89e5785f
HS		 789 if (frag == last_frag)
790 break;
791 }
03dbe05f
HS		 792
793 /* Make descriptor updates visible to hardware */
89e5785f 794 wmb();
03dbe05f 795
89e5785f
HS		 796 return 1;
797 }
798
29bc2e1e
HS		 799 offset = 0;
800 len += NET_IP_ALIGN;
bc8acf2c 801 skb_checksum_none_assert(skb);
89e5785f
HS		 802 skb_put(skb, len);
803
55054a16 804 for (frag = first_frag; ; frag++) {
1b44791a 805 unsigned int frag_len = bp->rx_buffer_size;
89e5785f
HS		 806
807 if (offset + frag_len > len) {
808 BUG_ON(frag != last_frag);
809 frag_len = len - offset;
810 }
27d7ff46 811 skb_copy_to_linear_data_offset(skb, offset,
55054a16 812 macb_rx_buffer(bp, frag), frag_len);
1b44791a 813 offset += bp->rx_buffer_size;
55054a16
HS		 814 desc = macb_rx_desc(bp, frag);
815 desc->addr &= ~MACB_BIT(RX_USED);
89e5785f
HS		 816
817 if (frag == last_frag)
818 break;
819 }
820
03dbe05f
HS		 821 /* Make descriptor updates visible to hardware */
822 wmb();
823
29bc2e1e 824 __skb_pull(skb, NET_IP_ALIGN);
89e5785f
HS		 825 skb->protocol = eth_type_trans(skb, bp->dev);
826
827 bp->stats.rx_packets++;
29bc2e1e 828 bp->stats.rx_bytes += skb->len;
a268adb1 829 netdev_vdbg(bp->dev, "received skb of length %u, csum: %08x\n",
c220f8cd 830 skb->len, skb->csum);
89e5785f
HS		 831 netif_receive_skb(skb);
832
833 return 0;
834}
835
89e5785f
HS		 836static int macb_rx(struct macb *bp, int budget)
837{
838 int received = 0;
55054a16 839 unsigned int tail;
89e5785f
HS		 840 int first_frag = -1;
841
55054a16
HS		 842 for (tail = bp->rx_tail; budget > 0; tail++) {
843 struct macb_dma_desc *desc = macb_rx_desc(bp, tail);
89e5785f
HS		 844 u32 addr, ctrl;
845
03dbe05f 846 /* Make hw descriptor updates visible to CPU */
89e5785f 847 rmb();
03dbe05f 848
55054a16
HS		 849 addr = desc->addr;
850 ctrl = desc->ctrl;
89e5785f
HS		 851
852 if (!(addr & MACB_BIT(RX_USED)))
853 break;
854
855 if (ctrl & MACB_BIT(RX_SOF)) {
856 if (first_frag != -1)
857 discard_partial_frame(bp, first_frag, tail);
858 first_frag = tail;
859 }
860
861 if (ctrl & MACB_BIT(RX_EOF)) {
862 int dropped;
863 BUG_ON(first_frag == -1);
864
865 dropped = macb_rx_frame(bp, first_frag, tail);
866 first_frag = -1;
867 if (!dropped) {
868 received++;
869 budget--;
870 }
871 }
872 }
873
874 if (first_frag != -1)
875 bp->rx_tail = first_frag;
876 else
877 bp->rx_tail = tail;
878
879 return received;
880}
881
bea3348e 882static int macb_poll(struct napi_struct *napi, int budget)
89e5785f 883{
bea3348e 884 struct macb *bp = container_of(napi, struct macb, napi);
bea3348e 885 int work_done;
89e5785f
HS		 886 u32 status;
887
888 status = macb_readl(bp, RSR);
889 macb_writel(bp, RSR, status);
890
bea3348e 891 work_done = 0;
89e5785f 892
a268adb1 893 netdev_vdbg(bp->dev, "poll: status = %08lx, budget = %d\n",
c220f8cd 894 (unsigned long)status, budget);
89e5785f 895
4df95131 896 work_done = bp->macbgem_ops.mog_rx(bp, budget);
b336369c 897 if (work_done < budget) {
288379f0 898 napi_complete(napi);
89e5785f 899
b336369c
JH		 900 /*
901 * We've done what we can to clean the buffers. Make sure we
902 * get notified when new packets arrive.
903 */
904 macb_writel(bp, IER, MACB_RX_INT_FLAGS);
8770e91a
NF		 905
906 /* Packets received while interrupts were disabled */
907 status = macb_readl(bp, RSR);
908 if (unlikely(status))
909 napi_reschedule(napi);
b336369c 910 }
89e5785f
HS		 911
912 /* TODO: Handle errors */
913
bea3348e 914 return work_done;
89e5785f
HS		 915}
916
917static irqreturn_t macb_interrupt(int irq, void *dev_id)
918{
919 struct net_device *dev = dev_id;
920 struct macb *bp = netdev_priv(dev);
921 u32 status;
922
923 status = macb_readl(bp, ISR);
924
925 if (unlikely(!status))
926 return IRQ_NONE;
927
928 spin_lock(&bp->lock);
929
930 while (status) {
89e5785f
HS		 931 /* close possible race with dev_close */
932 if (unlikely(!netif_running(dev))) {
95ebcea6 933 macb_writel(bp, IDR, -1);
89e5785f
HS		 934 break;
935 }
936
a268adb1
HS		 937 netdev_vdbg(bp->dev, "isr = 0x%08lx\n", (unsigned long)status);
938
89e5785f 939 if (status & MACB_RX_INT_FLAGS) {
b336369c
JH		 940 /*
941 * There's no point taking any more interrupts
942 * until we have processed the buffers. The
943 * scheduling call may fail if the poll routine
944 * is already scheduled, so disable interrupts
945 * now.
946 */
947 macb_writel(bp, IDR, MACB_RX_INT_FLAGS);
581df9e1
NF		 948 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
949 macb_writel(bp, ISR, MACB_BIT(RCOMP));
b336369c 950
288379f0 951 if (napi_schedule_prep(&bp->napi)) {
a268adb1 952 netdev_vdbg(bp->dev, "scheduling RX softirq\n");
288379f0 953 __napi_schedule(&bp->napi);
89e5785f
HS		 954 }
955 }
956
e86cd53a
NF		 957 if (unlikely(status & (MACB_TX_ERR_FLAGS))) {
958 macb_writel(bp, IDR, MACB_TX_INT_FLAGS);
959 schedule_work(&bp->tx_error_task);
960 break;
961 }
962
963 if (status & MACB_BIT(TCOMP))
964 macb_tx_interrupt(bp);
89e5785f
HS		 965
966 /*
967 * Link change detection isn't possible with RMII, so we'll
968 * add that if/when we get our hands on a full-blown MII PHY.
969 */
970
b19f7f71
AS		 971 if (status & MACB_BIT(ISR_ROVR)) {
972 /* We missed at least one packet */
f75ba50b
JI		 973 if (macb_is_gem(bp))
974 bp->hw_stats.gem.rx_overruns++;
975 else
976 bp->hw_stats.macb.rx_overruns++;
b19f7f71
AS		 977 }
978
89e5785f
HS		 979 if (status & MACB_BIT(HRESP)) {
980 /*
c220f8cd
JI		 981 * TODO: Reset the hardware, and maybe move the
982 * netdev_err to a lower-priority context as well
983 * (work queue?)
89e5785f 984 */
c220f8cd 985 netdev_err(dev, "DMA bus error: HRESP not OK\n");
89e5785f
HS		 986 }
987
988 status = macb_readl(bp, ISR);
989 }
990
991 spin_unlock(&bp->lock);
992
993 return IRQ_HANDLED;
994}
995
6e8cf5c0
TP		 996#ifdef CONFIG_NET_POLL_CONTROLLER
997/*
998 * Polling receive - used by netconsole and other diagnostic tools
999 * to allow network i/o with interrupts disabled.
1000 */
1001static void macb_poll_controller(struct net_device *dev)
1002{
1003 unsigned long flags;
1004
1005 local_irq_save(flags);
1006 macb_interrupt(dev->irq, dev);
1007 local_irq_restore(flags);
1008}
1009#endif
1010
89e5785f
HS		 1011static int macb_start_xmit(struct sk_buff *skb, struct net_device *dev)
1012{
1013 struct macb *bp = netdev_priv(dev);
1014 dma_addr_t mapping;
1015 unsigned int len, entry;
55054a16
HS		 1016 struct macb_dma_desc *desc;
1017 struct macb_tx_skb *tx_skb;
89e5785f 1018 u32 ctrl;
4871953c 1019 unsigned long flags;
89e5785f 1020
a268adb1
HS		 1021#if defined(DEBUG) && defined(VERBOSE_DEBUG)
1022 netdev_vdbg(bp->dev,
c220f8cd
JI		 1023 "start_xmit: len %u head %p data %p tail %p end %p\n",
1024 skb->len, skb->head, skb->data,
1025 skb_tail_pointer(skb), skb_end_pointer(skb));
1026 print_hex_dump(KERN_DEBUG, "data: ", DUMP_PREFIX_OFFSET, 16, 1,
1027 skb->data, 16, true);
89e5785f
HS		 1028#endif
1029
1030 len = skb->len;
4871953c 1031 spin_lock_irqsave(&bp->lock, flags);
89e5785f
HS		 1032
1033 /* This is a hard error, log it. */
909a8583 1034 if (CIRC_SPACE(bp->tx_head, bp->tx_tail, TX_RING_SIZE) < 1) {
89e5785f 1035 netif_stop_queue(dev);
4871953c 1036 spin_unlock_irqrestore(&bp->lock, flags);
c220f8cd
JI		 1037 netdev_err(bp->dev, "BUG! Tx Ring full when queue awake!\n");
1038 netdev_dbg(bp->dev, "tx_head = %u, tx_tail = %u\n",
1039 bp->tx_head, bp->tx_tail);
5b548140 1040 return NETDEV_TX_BUSY;
89e5785f
HS		 1041 }
1042
55054a16 1043 entry = macb_tx_ring_wrap(bp->tx_head);
a268adb1 1044 netdev_vdbg(bp->dev, "Allocated ring entry %u\n", entry);
89e5785f
HS		 1045 mapping = dma_map_single(&bp->pdev->dev, skb->data,
1046 len, DMA_TO_DEVICE);
92030908
SB		 1047 if (dma_mapping_error(&bp->pdev->dev, mapping)) {
1048 kfree_skb(skb);
1049 goto unlock;
1050 }
55054a16 1051
92030908 1052 bp->tx_head++;
55054a16
HS		 1053 tx_skb = &bp->tx_skb[entry];
1054 tx_skb->skb = skb;
1055 tx_skb->mapping = mapping;
a268adb1 1056 netdev_vdbg(bp->dev, "Mapped skb data %p to DMA addr %08lx\n",
c220f8cd 1057 skb->data, (unsigned long)mapping);
89e5785f
HS		 1058
1059 ctrl = MACB_BF(TX_FRMLEN, len);
1060 ctrl |= MACB_BIT(TX_LAST);
1061 if (entry == (TX_RING_SIZE - 1))
1062 ctrl |= MACB_BIT(TX_WRAP);
1063
55054a16
HS		 1064 desc = &bp->tx_ring[entry];
1065 desc->addr = mapping;
1066 desc->ctrl = ctrl;
03dbe05f
HS		 1067
1068 /* Make newly initialized descriptor visible to hardware */
89e5785f
HS		 1069 wmb();
1070
e072092f
RC		 1071 skb_tx_timestamp(skb);
1072
89e5785f
HS		 1073 macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(TSTART));
1074
909a8583 1075 if (CIRC_SPACE(bp->tx_head, bp->tx_tail, TX_RING_SIZE) < 1)
89e5785f
HS		 1076 netif_stop_queue(dev);
1077
92030908 1078unlock:
4871953c 1079 spin_unlock_irqrestore(&bp->lock, flags);
89e5785f 1080
6ed10654 1081 return NETDEV_TX_OK;
89e5785f
HS		 1082}
1083
4df95131 1084static void macb_init_rx_buffer_size(struct macb *bp, size_t size)
1b44791a
NF		 1085{
1086 if (!macb_is_gem(bp)) {
1087 bp->rx_buffer_size = MACB_RX_BUFFER_SIZE;
1088 } else {
4df95131 1089 bp->rx_buffer_size = size;
1b44791a 1090
1b44791a 1091 if (bp->rx_buffer_size % RX_BUFFER_MULTIPLE) {
4df95131
NF		 1092 netdev_dbg(bp->dev,
1093 "RX buffer must be multiple of %d bytes, expanding\n",
1b44791a
NF		 1094 RX_BUFFER_MULTIPLE);
1095 bp->rx_buffer_size =
4df95131 1096 roundup(bp->rx_buffer_size, RX_BUFFER_MULTIPLE);
1b44791a 1097 }
1b44791a 1098 }
4df95131
NF		 1099
1100 netdev_dbg(bp->dev, "mtu [%u] rx_buffer_size [%Zu]\n",
1101 bp->dev->mtu, bp->rx_buffer_size);
1b44791a
NF		 1102}
1103
4df95131
NF		 1104static void gem_free_rx_buffers(struct macb *bp)
1105{
1106 struct sk_buff *skb;
1107 struct macb_dma_desc *desc;
1108 dma_addr_t addr;
1109 int i;
1110
1111 if (!bp->rx_skbuff)
1112 return;
1113
1114 for (i = 0; i < RX_RING_SIZE; i++) {
1115 skb = bp->rx_skbuff[i];
1116
1117 if (skb == NULL)
1118 continue;
1119
1120 desc = &bp->rx_ring[i];
1121 addr = MACB_BF(RX_WADDR, MACB_BFEXT(RX_WADDR, desc->addr));
1122 dma_unmap_single(&bp->pdev->dev, addr, skb->len,
1123 DMA_FROM_DEVICE);
1124 dev_kfree_skb_any(skb);
1125 skb = NULL;
1126 }
1127
1128 kfree(bp->rx_skbuff);
1129 bp->rx_skbuff = NULL;
1130}
1131
1132static void macb_free_rx_buffers(struct macb *bp)
1133{
1134 if (bp->rx_buffers) {
1135 dma_free_coherent(&bp->pdev->dev,
1136 RX_RING_SIZE * bp->rx_buffer_size,
1137 bp->rx_buffers, bp->rx_buffers_dma);
1138 bp->rx_buffers = NULL;
1139 }
1140}
1b44791a 1141
89e5785f
HS		 1142static void macb_free_consistent(struct macb *bp)
1143{
1144 if (bp->tx_skb) {
1145 kfree(bp->tx_skb);
1146 bp->tx_skb = NULL;
1147 }
4df95131 1148 bp->macbgem_ops.mog_free_rx_buffers(bp);
89e5785f
HS		 1149 if (bp->rx_ring) {
1150 dma_free_coherent(&bp->pdev->dev, RX_RING_BYTES,
1151 bp->rx_ring, bp->rx_ring_dma);
1152 bp->rx_ring = NULL;
1153 }
1154 if (bp->tx_ring) {
1155 dma_free_coherent(&bp->pdev->dev, TX_RING_BYTES,
1156 bp->tx_ring, bp->tx_ring_dma);
1157 bp->tx_ring = NULL;
1158 }
4df95131
NF		 1159}
1160
1161static int gem_alloc_rx_buffers(struct macb *bp)
1162{
1163 int size;
1164
1165 size = RX_RING_SIZE * sizeof(struct sk_buff *);
1166 bp->rx_skbuff = kzalloc(size, GFP_KERNEL);
1167 if (!bp->rx_skbuff)
1168 return -ENOMEM;
1169 else
1170 netdev_dbg(bp->dev,
1171 "Allocated %d RX struct sk_buff entries at %p\n",
1172 RX_RING_SIZE, bp->rx_skbuff);
1173 return 0;
1174}
1175
1176static int macb_alloc_rx_buffers(struct macb *bp)
1177{
1178 int size;
1179
1180 size = RX_RING_SIZE * bp->rx_buffer_size;
1181 bp->rx_buffers = dma_alloc_coherent(&bp->pdev->dev, size,
1182 &bp->rx_buffers_dma, GFP_KERNEL);
1183 if (!bp->rx_buffers)
1184 return -ENOMEM;
1185 else
1186 netdev_dbg(bp->dev,
1187 "Allocated RX buffers of %d bytes at %08lx (mapped %p)\n",
1188 size, (unsigned long)bp->rx_buffers_dma, bp->rx_buffers);
1189 return 0;
89e5785f
HS		 1190}
1191
1192static int macb_alloc_consistent(struct macb *bp)
1193{
1194 int size;
1195
55054a16 1196 size = TX_RING_SIZE * sizeof(struct macb_tx_skb);
89e5785f
HS		 1197 bp->tx_skb = kmalloc(size, GFP_KERNEL);
1198 if (!bp->tx_skb)
1199 goto out_err;
1200
1201 size = RX_RING_BYTES;
1202 bp->rx_ring = dma_alloc_coherent(&bp->pdev->dev, size,
1203 &bp->rx_ring_dma, GFP_KERNEL);
1204 if (!bp->rx_ring)
1205 goto out_err;
c220f8cd
JI		 1206 netdev_dbg(bp->dev,
1207 "Allocated RX ring of %d bytes at %08lx (mapped %p)\n",
1208 size, (unsigned long)bp->rx_ring_dma, bp->rx_ring);
89e5785f
HS		 1209
1210 size = TX_RING_BYTES;
1211 bp->tx_ring = dma_alloc_coherent(&bp->pdev->dev, size,
1212 &bp->tx_ring_dma, GFP_KERNEL);
1213 if (!bp->tx_ring)
1214 goto out_err;
c220f8cd
JI		 1215 netdev_dbg(bp->dev,
1216 "Allocated TX ring of %d bytes at %08lx (mapped %p)\n",
1217 size, (unsigned long)bp->tx_ring_dma, bp->tx_ring);
89e5785f 1218
4df95131 1219 if (bp->macbgem_ops.mog_alloc_rx_buffers(bp))
89e5785f 1220 goto out_err;
89e5785f
HS		 1221
1222 return 0;
1223
1224out_err:
1225 macb_free_consistent(bp);
1226 return -ENOMEM;
1227}
1228
4df95131
NF		 1229static void gem_init_rings(struct macb *bp)
1230{
1231 int i;
1232
1233 for (i = 0; i < TX_RING_SIZE; i++) {
1234 bp->tx_ring[i].addr = 0;
1235 bp->tx_ring[i].ctrl = MACB_BIT(TX_USED);
1236 }
1237 bp->tx_ring[TX_RING_SIZE - 1].ctrl |= MACB_BIT(TX_WRAP);
1238
1239 bp->rx_tail = bp->rx_prepared_head = bp->tx_head = bp->tx_tail = 0;
1240
1241 gem_rx_refill(bp);
1242}
1243
89e5785f
HS		 1244static void macb_init_rings(struct macb *bp)
1245{
1246 int i;
1247 dma_addr_t addr;
1248
1249 addr = bp->rx_buffers_dma;
1250 for (i = 0; i < RX_RING_SIZE; i++) {
1251 bp->rx_ring[i].addr = addr;
1252 bp->rx_ring[i].ctrl = 0;
1b44791a 1253 addr += bp->rx_buffer_size;
89e5785f
HS		 1254 }
1255 bp->rx_ring[RX_RING_SIZE - 1].addr |= MACB_BIT(RX_WRAP);
1256
1257 for (i = 0; i < TX_RING_SIZE; i++) {
1258 bp->tx_ring[i].addr = 0;
1259 bp->tx_ring[i].ctrl = MACB_BIT(TX_USED);
1260 }
1261 bp->tx_ring[TX_RING_SIZE - 1].ctrl |= MACB_BIT(TX_WRAP);
1262
1263 bp->rx_tail = bp->tx_head = bp->tx_tail = 0;
1264}
1265
1266static void macb_reset_hw(struct macb *bp)
1267{
89e5785f
HS		 1268 /*
1269 * Disable RX and TX (XXX: Should we halt the transmission
1270 * more gracefully?)
1271 */
1272 macb_writel(bp, NCR, 0);
1273
1274 /* Clear the stats registers (XXX: Update stats first?) */
1275 macb_writel(bp, NCR, MACB_BIT(CLRSTAT));
1276
1277 /* Clear all status flags */
95ebcea6
JE		 1278 macb_writel(bp, TSR, -1);
1279 macb_writel(bp, RSR, -1);
89e5785f
HS		 1280
1281 /* Disable all interrupts */
95ebcea6 1282 macb_writel(bp, IDR, -1);
89e5785f
HS		 1283 macb_readl(bp, ISR);
1284}
1285
70c9f3d4
JI		 1286static u32 gem_mdc_clk_div(struct macb *bp)
1287{
1288 u32 config;
1289 unsigned long pclk_hz = clk_get_rate(bp->pclk);
1290
1291 if (pclk_hz <= 20000000)
1292 config = GEM_BF(CLK, GEM_CLK_DIV8);
1293 else if (pclk_hz <= 40000000)
1294 config = GEM_BF(CLK, GEM_CLK_DIV16);
1295 else if (pclk_hz <= 80000000)
1296 config = GEM_BF(CLK, GEM_CLK_DIV32);
1297 else if (pclk_hz <= 120000000)
1298 config = GEM_BF(CLK, GEM_CLK_DIV48);
1299 else if (pclk_hz <= 160000000)
1300 config = GEM_BF(CLK, GEM_CLK_DIV64);
1301 else
1302 config = GEM_BF(CLK, GEM_CLK_DIV96);
1303
1304 return config;
1305}
1306
1307static u32 macb_mdc_clk_div(struct macb *bp)
1308{
1309 u32 config;
1310 unsigned long pclk_hz;
1311
1312 if (macb_is_gem(bp))
1313 return gem_mdc_clk_div(bp);
1314
1315 pclk_hz = clk_get_rate(bp->pclk);
1316 if (pclk_hz <= 20000000)
1317 config = MACB_BF(CLK, MACB_CLK_DIV8);
1318 else if (pclk_hz <= 40000000)
1319 config = MACB_BF(CLK, MACB_CLK_DIV16);
1320 else if (pclk_hz <= 80000000)
1321 config = MACB_BF(CLK, MACB_CLK_DIV32);
1322 else
1323 config = MACB_BF(CLK, MACB_CLK_DIV64);
1324
1325 return config;
1326}
1327
757a03c6
JI		 1328/*
1329 * Get the DMA bus width field of the network configuration register that we
1330 * should program. We find the width from decoding the design configuration
1331 * register to find the maximum supported data bus width.
1332 */
1333static u32 macb_dbw(struct macb *bp)
1334{
1335 if (!macb_is_gem(bp))
1336 return 0;
1337
1338 switch (GEM_BFEXT(DBWDEF, gem_readl(bp, DCFG1))) {
1339 case 4:
1340 return GEM_BF(DBW, GEM_DBW128);
1341 case 2:
1342 return GEM_BF(DBW, GEM_DBW64);
1343 case 1:
1344 default:
1345 return GEM_BF(DBW, GEM_DBW32);
1346 }
1347}
1348
0116da4f 1349/*
b3e3bd71
NF		 1350 * Configure the receive DMA engine
1351 * - use the correct receive buffer size
1352 * - set the possibility to use INCR16 bursts
1353 * (if not supported by FIFO, it will fallback to default)
1354 * - set both rx/tx packet buffers to full memory size
1355 * These are configurable parameters for GEM.
0116da4f
JI		 1356 */
1357static void macb_configure_dma(struct macb *bp)
1358{
1359 u32 dmacfg;
1360
1361 if (macb_is_gem(bp)) {
1362 dmacfg = gem_readl(bp, DMACFG) & ~GEM_BF(RXBS, -1L);
1b44791a 1363 dmacfg |= GEM_BF(RXBS, bp->rx_buffer_size / RX_BUFFER_MULTIPLE);
b3e3bd71
NF		 1364 dmacfg |= GEM_BF(FBLDO, 16);
1365 dmacfg |= GEM_BIT(TXPBMS) | GEM_BF(RXBMS, -1L);
a1ae385d 1366 dmacfg &= ~GEM_BIT(ENDIA);
0116da4f
JI		 1367 gem_writel(bp, DMACFG, dmacfg);
1368 }
1369}
1370
581df9e1
NF		 1371/*
1372 * Configure peripheral capacities according to integration options used
1373 */
1374static void macb_configure_caps(struct macb *bp)
1375{
1376 if (macb_is_gem(bp)) {
01276ed2 1377 if (GEM_BFEXT(IRQCOR, gem_readl(bp, DCFG1)) == 0)
581df9e1
NF		 1378 bp->caps |= MACB_CAPS_ISR_CLEAR_ON_WRITE;
1379 }
1380}
1381
89e5785f
HS		 1382static void macb_init_hw(struct macb *bp)
1383{
1384 u32 config;
1385
1386 macb_reset_hw(bp);
314bccc4 1387 macb_set_hwaddr(bp);
89e5785f 1388
70c9f3d4 1389 config = macb_mdc_clk_div(bp);
29bc2e1e 1390 config |= MACB_BF(RBOF, NET_IP_ALIGN); /* Make eth data aligned */
89e5785f
HS		 1391 config |= MACB_BIT(PAE); /* PAuse Enable */
1392 config |= MACB_BIT(DRFCS); /* Discard Rx FCS */
8dd4bd00 1393 config |= MACB_BIT(BIG); /* Receive oversized frames */
89e5785f
HS		 1394 if (bp->dev->flags & IFF_PROMISC)
1395 config |= MACB_BIT(CAF); /* Copy All Frames */
1396 if (!(bp->dev->flags & IFF_BROADCAST))
1397 config |= MACB_BIT(NBC); /* No BroadCast */
757a03c6 1398 config |= macb_dbw(bp);
89e5785f 1399 macb_writel(bp, NCFGR, config);
26cdfb49
VD		 1400 bp->speed = SPEED_10;
1401 bp->duplex = DUPLEX_HALF;
89e5785f 1402
0116da4f 1403 macb_configure_dma(bp);
581df9e1 1404 macb_configure_caps(bp);
0116da4f 1405
89e5785f
HS		 1406 /* Initialize TX and RX buffers */
1407 macb_writel(bp, RBQP, bp->rx_ring_dma);
1408 macb_writel(bp, TBQP, bp->tx_ring_dma);
1409
1410 /* Enable TX and RX */
6c36a707 1411 macb_writel(bp, NCR, MACB_BIT(RE) | MACB_BIT(TE) | MACB_BIT(MPE));
89e5785f
HS		 1412
1413 /* Enable interrupts */
e86cd53a
NF		 1414 macb_writel(bp, IER, (MACB_RX_INT_FLAGS
1415 | MACB_TX_INT_FLAGS
89e5785f 1416 | MACB_BIT(HRESP)));
89e5785f 1417
89e5785f
HS		 1418}
1419
446ebd01
PV		 1420/*
1421 * The hash address register is 64 bits long and takes up two
1422 * locations in the memory map. The least significant bits are stored
1423 * in EMAC_HSL and the most significant bits in EMAC_HSH.
1424 *
1425 * The unicast hash enable and the multicast hash enable bits in the
1426 * network configuration register enable the reception of hash matched
1427 * frames. The destination address is reduced to a 6 bit index into
1428 * the 64 bit hash register using the following hash function. The
1429 * hash function is an exclusive or of every sixth bit of the
1430 * destination address.
1431 *
1432 * hi[5] = da[5] ^ da[11] ^ da[17] ^ da[23] ^ da[29] ^ da[35] ^ da[41] ^ da[47]
1433 * hi[4] = da[4] ^ da[10] ^ da[16] ^ da[22] ^ da[28] ^ da[34] ^ da[40] ^ da[46]
1434 * hi[3] = da[3] ^ da[09] ^ da[15] ^ da[21] ^ da[27] ^ da[33] ^ da[39] ^ da[45]
1435 * hi[2] = da[2] ^ da[08] ^ da[14] ^ da[20] ^ da[26] ^ da[32] ^ da[38] ^ da[44]
1436 * hi[1] = da[1] ^ da[07] ^ da[13] ^ da[19] ^ da[25] ^ da[31] ^ da[37] ^ da[43]
1437 * hi[0] = da[0] ^ da[06] ^ da[12] ^ da[18] ^ da[24] ^ da[30] ^ da[36] ^ da[42]
1438 *
1439 * da[0] represents the least significant bit of the first byte
1440 * received, that is, the multicast/unicast indicator, and da[47]
1441 * represents the most significant bit of the last byte received. If
1442 * the hash index, hi[n], points to a bit that is set in the hash
1443 * register then the frame will be matched according to whether the
1444 * frame is multicast or unicast. A multicast match will be signalled
1445 * if the multicast hash enable bit is set, da[0] is 1 and the hash
1446 * index points to a bit set in the hash register. A unicast match
1447 * will be signalled if the unicast hash enable bit is set, da[0] is 0
1448 * and the hash index points to a bit set in the hash register. To
1449 * receive all multicast frames, the hash register should be set with
1450 * all ones and the multicast hash enable bit should be set in the
1451 * network configuration register.
1452 */
1453
1454static inline int hash_bit_value(int bitnr, __u8 *addr)
1455{
1456 if (addr[bitnr / 8] & (1 << (bitnr % 8)))
1457 return 1;
1458 return 0;
1459}
1460
1461/*
1462 * Return the hash index value for the specified address.
1463 */
1464static int hash_get_index(__u8 *addr)
1465{
1466 int i, j, bitval;
1467 int hash_index = 0;
1468
1469 for (j = 0; j < 6; j++) {
1470 for (i = 0, bitval = 0; i < 8; i++)
1471 bitval ^= hash_bit_value(i*6 + j, addr);
1472
1473 hash_index |= (bitval << j);
1474 }
1475
1476 return hash_index;
1477}
1478
1479/*
1480 * Add multicast addresses to the internal multicast-hash table.
1481 */
1482static void macb_sethashtable(struct net_device *dev)
1483{
22bedad3 1484 struct netdev_hw_addr *ha;
446ebd01 1485 unsigned long mc_filter[2];
f9dcbcc9 1486 unsigned int bitnr;
446ebd01
PV		 1487 struct macb *bp = netdev_priv(dev);
1488
1489 mc_filter[0] = mc_filter[1] = 0;
1490
22bedad3
JP		 1491 netdev_for_each_mc_addr(ha, dev) {
1492 bitnr = hash_get_index(ha->addr);
446ebd01
PV		 1493 mc_filter[bitnr >> 5] |= 1 << (bitnr & 31);
1494 }
1495
f75ba50b
JI		 1496 macb_or_gem_writel(bp, HRB, mc_filter[0]);
1497 macb_or_gem_writel(bp, HRT, mc_filter[1]);
446ebd01
PV		 1498}
1499
1500/*
1501 * Enable/Disable promiscuous and multicast modes.
1502 */
e0da1f14 1503void macb_set_rx_mode(struct net_device *dev)
446ebd01
PV		 1504{
1505 unsigned long cfg;
1506 struct macb *bp = netdev_priv(dev);
1507
1508 cfg = macb_readl(bp, NCFGR);
1509
1510 if (dev->flags & IFF_PROMISC)
1511 /* Enable promiscuous mode */
1512 cfg |= MACB_BIT(CAF);
1513 else if (dev->flags & (~IFF_PROMISC))
1514 /* Disable promiscuous mode */
1515 cfg &= ~MACB_BIT(CAF);
1516
1517 if (dev->flags & IFF_ALLMULTI) {
1518 /* Enable all multicast mode */
f75ba50b
JI		 1519 macb_or_gem_writel(bp, HRB, -1);
1520 macb_or_gem_writel(bp, HRT, -1);
446ebd01 1521 cfg |= MACB_BIT(NCFGR_MTI);
4cd24eaf 1522 } else if (!netdev_mc_empty(dev)) {
446ebd01
PV		 1523 /* Enable specific multicasts */
1524 macb_sethashtable(dev);
1525 cfg |= MACB_BIT(NCFGR_MTI);
1526 } else if (dev->flags & (~IFF_ALLMULTI)) {
1527 /* Disable all multicast mode */
f75ba50b
JI		 1528 macb_or_gem_writel(bp, HRB, 0);
1529 macb_or_gem_writel(bp, HRT, 0);
446ebd01
PV		 1530 cfg &= ~MACB_BIT(NCFGR_MTI);
1531 }
1532
1533 macb_writel(bp, NCFGR, cfg);
1534}
e0da1f14 1535EXPORT_SYMBOL_GPL(macb_set_rx_mode);
446ebd01 1536
89e5785f
HS		 1537static int macb_open(struct net_device *dev)
1538{
1539 struct macb *bp = netdev_priv(dev);
4df95131 1540 size_t bufsz = dev->mtu + ETH_HLEN + ETH_FCS_LEN + NET_IP_ALIGN;
89e5785f
HS		 1541 int err;
1542
c220f8cd 1543 netdev_dbg(bp->dev, "open\n");
89e5785f 1544
03fc4721
NF		 1545 /* carrier starts down */
1546 netif_carrier_off(dev);
1547
6c36a707
R		 1548 /* if the phy is not yet register, retry later*/
1549 if (!bp->phy_dev)
1550 return -EAGAIN;
1b44791a
NF		 1551
1552 /* RX buffers initialization */
4df95131 1553 macb_init_rx_buffer_size(bp, bufsz);
6c36a707 1554
89e5785f
HS		 1555 err = macb_alloc_consistent(bp);
1556 if (err) {
c220f8cd
JI		 1557 netdev_err(dev, "Unable to allocate DMA memory (error %d)\n",
1558 err);
89e5785f
HS		 1559 return err;
1560 }
1561
bea3348e
SH		 1562 napi_enable(&bp->napi);
1563
4df95131 1564 bp->macbgem_ops.mog_init_rings(bp);
89e5785f 1565 macb_init_hw(bp);
89e5785f 1566
6c36a707
R		 1567 /* schedule a link state check */
1568 phy_start(bp->phy_dev);
89e5785f 1569
6c36a707 1570 netif_start_queue(dev);
89e5785f
HS		 1571
1572 return 0;
1573}
1574
1575static int macb_close(struct net_device *dev)
1576{
1577 struct macb *bp = netdev_priv(dev);
1578 unsigned long flags;
1579
89e5785f 1580 netif_stop_queue(dev);
bea3348e 1581 napi_disable(&bp->napi);
89e5785f 1582
6c36a707
R		 1583 if (bp->phy_dev)
1584 phy_stop(bp->phy_dev);
1585
89e5785f
HS		 1586 spin_lock_irqsave(&bp->lock, flags);
1587 macb_reset_hw(bp);
1588 netif_carrier_off(dev);
1589 spin_unlock_irqrestore(&bp->lock, flags);
1590
1591 macb_free_consistent(bp);
1592
1593 return 0;
1594}
1595
a494ed8e
JI		 1596static void gem_update_stats(struct macb *bp)
1597{
1598 u32 __iomem *reg = bp->regs + GEM_OTX;
1599 u32 *p = &bp->hw_stats.gem.tx_octets_31_0;
1600 u32 *end = &bp->hw_stats.gem.rx_udp_checksum_errors + 1;
1601
1602 for (; p < end; p++, reg++)
1603 *p += __raw_readl(reg);
1604}
1605
1606static struct net_device_stats *gem_get_stats(struct macb *bp)
1607{
1608 struct gem_stats *hwstat = &bp->hw_stats.gem;
1609 struct net_device_stats *nstat = &bp->stats;
1610
1611 gem_update_stats(bp);
1612
1613 nstat->rx_errors = (hwstat->rx_frame_check_sequence_errors +
1614 hwstat->rx_alignment_errors +
1615 hwstat->rx_resource_errors +
1616 hwstat->rx_overruns +
1617 hwstat->rx_oversize_frames +
1618 hwstat->rx_jabbers +
1619 hwstat->rx_undersized_frames +
1620 hwstat->rx_length_field_frame_errors);
1621 nstat->tx_errors = (hwstat->tx_late_collisions +
1622 hwstat->tx_excessive_collisions +
1623 hwstat->tx_underrun +
1624 hwstat->tx_carrier_sense_errors);
1625 nstat->multicast = hwstat->rx_multicast_frames;
1626 nstat->collisions = (hwstat->tx_single_collision_frames +
1627 hwstat->tx_multiple_collision_frames +
1628 hwstat->tx_excessive_collisions);
1629 nstat->rx_length_errors = (hwstat->rx_oversize_frames +
1630 hwstat->rx_jabbers +
1631 hwstat->rx_undersized_frames +
1632 hwstat->rx_length_field_frame_errors);
1633 nstat->rx_over_errors = hwstat->rx_resource_errors;
1634 nstat->rx_crc_errors = hwstat->rx_frame_check_sequence_errors;
1635 nstat->rx_frame_errors = hwstat->rx_alignment_errors;
1636 nstat->rx_fifo_errors = hwstat->rx_overruns;
1637 nstat->tx_aborted_errors = hwstat->tx_excessive_collisions;
1638 nstat->tx_carrier_errors = hwstat->tx_carrier_sense_errors;
1639 nstat->tx_fifo_errors = hwstat->tx_underrun;
1640
1641 return nstat;
1642}
1643
2ea32eed 1644struct net_device_stats *macb_get_stats(struct net_device *dev)
89e5785f
HS		 1645{
1646 struct macb *bp = netdev_priv(dev);
1647 struct net_device_stats *nstat = &bp->stats;
a494ed8e
JI		 1648 struct macb_stats *hwstat = &bp->hw_stats.macb;
1649
1650 if (macb_is_gem(bp))
1651 return gem_get_stats(bp);
89e5785f 1652
6c36a707
R		 1653 /* read stats from hardware */
1654 macb_update_stats(bp);
1655
89e5785f
HS		 1656 /* Convert HW stats into netdevice stats */
1657 nstat->rx_errors = (hwstat->rx_fcs_errors +
1658 hwstat->rx_align_errors +
1659 hwstat->rx_resource_errors +
1660 hwstat->rx_overruns +
1661 hwstat->rx_oversize_pkts +
1662 hwstat->rx_jabbers +
1663 hwstat->rx_undersize_pkts +
1664 hwstat->sqe_test_errors +
1665 hwstat->rx_length_mismatch);
1666 nstat->tx_errors = (hwstat->tx_late_cols +
1667 hwstat->tx_excessive_cols +
1668 hwstat->tx_underruns +
1669 hwstat->tx_carrier_errors);
1670 nstat->collisions = (hwstat->tx_single_cols +
1671 hwstat->tx_multiple_cols +
1672 hwstat->tx_excessive_cols);
1673 nstat->rx_length_errors = (hwstat->rx_oversize_pkts +
1674 hwstat->rx_jabbers +
1675 hwstat->rx_undersize_pkts +
1676 hwstat->rx_length_mismatch);
b19f7f71
AS		 1677 nstat->rx_over_errors = hwstat->rx_resource_errors +
1678 hwstat->rx_overruns;
89e5785f
HS		 1679 nstat->rx_crc_errors = hwstat->rx_fcs_errors;
1680 nstat->rx_frame_errors = hwstat->rx_align_errors;
1681 nstat->rx_fifo_errors = hwstat->rx_overruns;
1682 /* XXX: What does "missed" mean? */
1683 nstat->tx_aborted_errors = hwstat->tx_excessive_cols;
1684 nstat->tx_carrier_errors = hwstat->tx_carrier_errors;
1685 nstat->tx_fifo_errors = hwstat->tx_underruns;
1686 /* Don't know about heartbeat or window errors... */
1687
1688 return nstat;
1689}
2ea32eed 1690EXPORT_SYMBOL_GPL(macb_get_stats);
89e5785f
HS		 1691
1692static int macb_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1693{
1694 struct macb *bp = netdev_priv(dev);
6c36a707
R		 1695 struct phy_device *phydev = bp->phy_dev;
1696
1697 if (!phydev)
1698 return -ENODEV;
89e5785f 1699
6c36a707 1700 return phy_ethtool_gset(phydev, cmd);
89e5785f
HS		 1701}
1702
1703static int macb_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1704{
1705 struct macb *bp = netdev_priv(dev);
6c36a707 1706 struct phy_device *phydev = bp->phy_dev;
89e5785f 1707
6c36a707
R		 1708 if (!phydev)
1709 return -ENODEV;
1710
1711 return phy_ethtool_sset(phydev, cmd);
89e5785f
HS		 1712}
1713
d1d1b53d
NF		 1714static int macb_get_regs_len(struct net_device *netdev)
1715{
1716 return MACB_GREGS_NBR * sizeof(u32);
1717}
1718
1719static void macb_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1720 void *p)
1721{
1722 struct macb *bp = netdev_priv(dev);
1723 unsigned int tail, head;
1724 u32 *regs_buff = p;
1725
1726 regs->version = (macb_readl(bp, MID) & ((1 << MACB_REV_SIZE) - 1))
1727 | MACB_GREGS_VERSION;
1728
1729 tail = macb_tx_ring_wrap(bp->tx_tail);
1730 head = macb_tx_ring_wrap(bp->tx_head);
1731
1732 regs_buff[0] = macb_readl(bp, NCR);
1733 regs_buff[1] = macb_or_gem_readl(bp, NCFGR);
1734 regs_buff[2] = macb_readl(bp, NSR);
1735 regs_buff[3] = macb_readl(bp, TSR);
1736 regs_buff[4] = macb_readl(bp, RBQP);
1737 regs_buff[5] = macb_readl(bp, TBQP);
1738 regs_buff[6] = macb_readl(bp, RSR);
1739 regs_buff[7] = macb_readl(bp, IMR);
1740
1741 regs_buff[8] = tail;
1742 regs_buff[9] = head;
1743 regs_buff[10] = macb_tx_dma(bp, tail);
1744 regs_buff[11] = macb_tx_dma(bp, head);
1745
1746 if (macb_is_gem(bp)) {
1747 regs_buff[12] = gem_readl(bp, USRIO);
1748 regs_buff[13] = gem_readl(bp, DMACFG);
1749 }
1750}
1751
0005f541 1752const struct ethtool_ops macb_ethtool_ops = {
89e5785f
HS		 1753 .get_settings = macb_get_settings,
1754 .set_settings = macb_set_settings,
d1d1b53d
NF		 1755 .get_regs_len = macb_get_regs_len,
1756 .get_regs = macb_get_regs,
89e5785f 1757 .get_link = ethtool_op_get_link,
17f393e8 1758 .get_ts_info = ethtool_op_get_ts_info,
89e5785f 1759};
0005f541 1760EXPORT_SYMBOL_GPL(macb_ethtool_ops);
89e5785f 1761
0005f541 1762int macb_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
89e5785f
HS		 1763{
1764 struct macb *bp = netdev_priv(dev);
6c36a707 1765 struct phy_device *phydev = bp->phy_dev;
89e5785f
HS		 1766
1767 if (!netif_running(dev))
1768 return -EINVAL;
1769
6c36a707
R		 1770 if (!phydev)
1771 return -ENODEV;
89e5785f 1772
28b04113 1773 return phy_mii_ioctl(phydev, rq, cmd);
89e5785f 1774}
0005f541 1775EXPORT_SYMBOL_GPL(macb_ioctl);
89e5785f 1776
5f1fa992
AB		 1777static const struct net_device_ops macb_netdev_ops = {
1778 .ndo_open = macb_open,
1779 .ndo_stop = macb_close,
1780 .ndo_start_xmit = macb_start_xmit,
afc4b13d 1781 .ndo_set_rx_mode = macb_set_rx_mode,
5f1fa992
AB		 1782 .ndo_get_stats = macb_get_stats,
1783 .ndo_do_ioctl = macb_ioctl,
1784 .ndo_validate_addr = eth_validate_addr,
1785 .ndo_change_mtu = eth_change_mtu,
1786 .ndo_set_mac_address = eth_mac_addr,
6e8cf5c0
TP		 1787#ifdef CONFIG_NET_POLL_CONTROLLER
1788 .ndo_poll_controller = macb_poll_controller,
1789#endif
5f1fa992
AB		 1790};
1791
fb97a846
JCPV		 1792#if defined(CONFIG_OF)
1793static const struct of_device_id macb_dt_ids[] = {
1794 { .compatible = "cdns,at32ap7000-macb" },
1795 { .compatible = "cdns,at91sam9260-macb" },
1796 { .compatible = "cdns,macb" },
1797 { .compatible = "cdns,pc302-gem" },
1798 { .compatible = "cdns,gem" },
1799 { /* sentinel */ }
1800};
fb97a846 1801MODULE_DEVICE_TABLE(of, macb_dt_ids);
fb97a846
JCPV		 1802#endif
1803
06c3fd6a 1804static int __init macb_probe(struct platform_device *pdev)
89e5785f 1805{
84e0cdb0 1806 struct macb_platform_data *pdata;
89e5785f
HS		 1807 struct resource *regs;
1808 struct net_device *dev;
1809 struct macb *bp;
6c36a707 1810 struct phy_device *phydev;
89e5785f
HS		 1811 u32 config;
1812 int err = -ENXIO;
8ef29f8a 1813 struct pinctrl *pinctrl;
50907043 1814 const char *mac;
89e5785f
HS		 1815
1816 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1817 if (!regs) {
1818 dev_err(&pdev->dev, "no mmio resource defined\n");
1819 goto err_out;
1820 }
1821
8ef29f8a
JCPV		 1822 pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
1823 if (IS_ERR(pinctrl)) {
1824 err = PTR_ERR(pinctrl);
1825 if (err == -EPROBE_DEFER)
1826 goto err_out;
1827
1828 dev_warn(&pdev->dev, "No pinctrl provided\n");
1829 }
1830
89e5785f
HS		 1831 err = -ENOMEM;
1832 dev = alloc_etherdev(sizeof(*bp));
41de8d4c 1833 if (!dev)
89e5785f 1834 goto err_out;
89e5785f 1835
89e5785f
HS		 1836 SET_NETDEV_DEV(dev, &pdev->dev);
1837
1838 /* TODO: Actually, we have some interesting features... */
1839 dev->features |= 0;
1840
1841 bp = netdev_priv(dev);
1842 bp->pdev = pdev;
1843 bp->dev = dev;
1844
1845 spin_lock_init(&bp->lock);
e86cd53a 1846 INIT_WORK(&bp->tx_error_task, macb_tx_error_task);
89e5785f 1847
b48e0bab 1848 bp->pclk = devm_clk_get(&pdev->dev, "pclk");
0cc8674f 1849 if (IS_ERR(bp->pclk)) {
b48e0bab
SB		 1850 err = PTR_ERR(bp->pclk);
1851 dev_err(&pdev->dev, "failed to get macb_clk (%u)\n", err);
0cc8674f
AV		 1852 goto err_out_free_dev;
1853 }
461845db 1854
b48e0bab 1855 bp->hclk = devm_clk_get(&pdev->dev, "hclk");
89e5785f 1856 if (IS_ERR(bp->hclk)) {
b48e0bab
SB		 1857 err = PTR_ERR(bp->hclk);
1858 dev_err(&pdev->dev, "failed to get hclk (%u)\n", err);
1859 goto err_out_free_dev;
1860 }
1861
e1824dfe
SB		 1862 bp->tx_clk = devm_clk_get(&pdev->dev, "tx_clk");
1863
b48e0bab
SB		 1864 err = clk_prepare_enable(bp->pclk);
1865 if (err) {
1866 dev_err(&pdev->dev, "failed to enable pclk (%u)\n", err);
1867 goto err_out_free_dev;
1868 }
1869
1870 err = clk_prepare_enable(bp->hclk);
1871 if (err) {
1872 dev_err(&pdev->dev, "failed to enable hclk (%u)\n", err);
1873 goto err_out_disable_pclk;
89e5785f 1874 }
89e5785f 1875
e1824dfe
SB		 1876 if (!IS_ERR(bp->tx_clk)) {
1877 err = clk_prepare_enable(bp->tx_clk);
1878 if (err) {
1879 dev_err(&pdev->dev, "failed to enable tx_clk (%u)\n",
1880 err);
1881 goto err_out_disable_hclk;
1882 }
1883 }
1884
60fe716f 1885 bp->regs = devm_ioremap(&pdev->dev, regs->start, resource_size(regs));
89e5785f
HS		 1886 if (!bp->regs) {
1887 dev_err(&pdev->dev, "failed to map registers, aborting.\n");
1888 err = -ENOMEM;
1889 goto err_out_disable_clocks;
1890 }
1891
1892 dev->irq = platform_get_irq(pdev, 0);
0a4acf08
SB		 1893 err = devm_request_irq(&pdev->dev, dev->irq, macb_interrupt, 0,
1894 dev->name, dev);
89e5785f 1895 if (err) {
c220f8cd
JI		 1896 dev_err(&pdev->dev, "Unable to request IRQ %d (error %d)\n",
1897 dev->irq, err);
60fe716f 1898 goto err_out_disable_clocks;
89e5785f
HS		 1899 }
1900
5f1fa992 1901 dev->netdev_ops = &macb_netdev_ops;
bea3348e 1902 netif_napi_add(dev, &bp->napi, macb_poll, 64);
89e5785f
HS		 1903 dev->ethtool_ops = &macb_ethtool_ops;
1904
1905 dev->base_addr = regs->start;
1906
4df95131
NF		 1907 /* setup appropriated routines according to adapter type */
1908 if (macb_is_gem(bp)) {
1909 bp->macbgem_ops.mog_alloc_rx_buffers = gem_alloc_rx_buffers;
1910 bp->macbgem_ops.mog_free_rx_buffers = gem_free_rx_buffers;
1911 bp->macbgem_ops.mog_init_rings = gem_init_rings;
1912 bp->macbgem_ops.mog_rx = gem_rx;
1913 } else {
1914 bp->macbgem_ops.mog_alloc_rx_buffers = macb_alloc_rx_buffers;
1915 bp->macbgem_ops.mog_free_rx_buffers = macb_free_rx_buffers;
1916 bp->macbgem_ops.mog_init_rings = macb_init_rings;
1917 bp->macbgem_ops.mog_rx = macb_rx;
1918 }
1919
89e5785f 1920 /* Set MII management clock divider */
70c9f3d4 1921 config = macb_mdc_clk_div(bp);
757a03c6 1922 config |= macb_dbw(bp);
89e5785f
HS		 1923 macb_writel(bp, NCFGR, config);
1924
50907043
GR		 1925 mac = of_get_mac_address(pdev->dev.of_node);
1926 if (mac)
1927 memcpy(bp->dev->dev_addr, mac, ETH_ALEN);
1928 else
fb97a846
JCPV		 1929 macb_get_hwaddr(bp);
1930
50907043 1931 err = of_get_phy_mode(pdev->dev.of_node);
fb97a846 1932 if (err < 0) {
c607a0d9 1933 pdata = dev_get_platdata(&pdev->dev);
fb97a846
JCPV		 1934 if (pdata && pdata->is_rmii)
1935 bp->phy_interface = PHY_INTERFACE_MODE_RMII;
1936 else
1937 bp->phy_interface = PHY_INTERFACE_MODE_MII;
1938 } else {
1939 bp->phy_interface = err;
1940 }
6c36a707 1941
140b7552
PV		 1942 if (bp->phy_interface == PHY_INTERFACE_MODE_RGMII)
1943 macb_or_gem_writel(bp, USRIO, GEM_BIT(RGMII));
1944 else if (bp->phy_interface == PHY_INTERFACE_MODE_RMII)
0cc8674f 1945#if defined(CONFIG_ARCH_AT91)
f75ba50b
JI		 1946 macb_or_gem_writel(bp, USRIO, (MACB_BIT(RMII) |
1947 MACB_BIT(CLKEN)));
0cc8674f 1948#else
f75ba50b 1949 macb_or_gem_writel(bp, USRIO, 0);
0cc8674f 1950#endif
89e5785f 1951 else
0cc8674f 1952#if defined(CONFIG_ARCH_AT91)
f75ba50b 1953 macb_or_gem_writel(bp, USRIO, MACB_BIT(CLKEN));
0cc8674f 1954#else
f75ba50b 1955 macb_or_gem_writel(bp, USRIO, MACB_BIT(MII));
0cc8674f 1956#endif
89e5785f 1957
89e5785f
HS		 1958 err = register_netdev(dev);
1959 if (err) {
1960 dev_err(&pdev->dev, "Cannot register net device, aborting.\n");
0a4acf08 1961 goto err_out_disable_clocks;
89e5785f
HS		 1962 }
1963
72ca820b
NF		 1964 err = macb_mii_init(bp);
1965 if (err)
6c36a707 1966 goto err_out_unregister_netdev;
89e5785f 1967
6c36a707 1968 platform_set_drvdata(pdev, dev);
89e5785f 1969
03fc4721
NF		 1970 netif_carrier_off(dev);
1971
f75ba50b
JI		 1972 netdev_info(dev, "Cadence %s at 0x%08lx irq %d (%pM)\n",
1973 macb_is_gem(bp) ? "GEM" : "MACB", dev->base_addr,
1974 dev->irq, dev->dev_addr);
89e5785f 1975
6c36a707 1976 phydev = bp->phy_dev;
c220f8cd
JI		 1977 netdev_info(dev, "attached PHY driver [%s] (mii_bus:phy_addr=%s, irq=%d)\n",
1978 phydev->drv->name, dev_name(&phydev->dev), phydev->irq);
6c36a707 1979
89e5785f
HS		 1980 return 0;
1981
6c36a707
R		 1982err_out_unregister_netdev:
1983 unregister_netdev(dev);
89e5785f 1984err_out_disable_clocks:
e1824dfe
SB		 1985 if (!IS_ERR(bp->tx_clk))
1986 clk_disable_unprepare(bp->tx_clk);
1987err_out_disable_hclk:
ace58010 1988 clk_disable_unprepare(bp->hclk);
b48e0bab 1989err_out_disable_pclk:
ace58010 1990 clk_disable_unprepare(bp->pclk);
89e5785f
HS		 1991err_out_free_dev:
1992 free_netdev(dev);
1993err_out:
89e5785f
HS		 1994 return err;
1995}
1996
06c3fd6a 1997static int __exit macb_remove(struct platform_device *pdev)
89e5785f
HS		 1998{
1999 struct net_device *dev;
2000 struct macb *bp;
2001
2002 dev = platform_get_drvdata(pdev);
2003
2004 if (dev) {
2005 bp = netdev_priv(dev);
84b7901f
AN		 2006 if (bp->phy_dev)
2007 phy_disconnect(bp->phy_dev);
298cf9be
LB		 2008 mdiobus_unregister(bp->mii_bus);
2009 kfree(bp->mii_bus->irq);
2010 mdiobus_free(bp->mii_bus);
89e5785f 2011 unregister_netdev(dev);
e1824dfe
SB		 2012 if (!IS_ERR(bp->tx_clk))
2013 clk_disable_unprepare(bp->tx_clk);
ace58010 2014 clk_disable_unprepare(bp->hclk);
ace58010 2015 clk_disable_unprepare(bp->pclk);
89e5785f 2016 free_netdev(dev);
89e5785f
HS		 2017 }
2018
2019 return 0;
2020}
2021
c1f598fd 2022#ifdef CONFIG_PM
0dfc3e18 2023static int macb_suspend(struct device *dev)
c1f598fd 2024{
0dfc3e18 2025 struct platform_device *pdev = to_platform_device(dev);
c1f598fd
HS		 2026 struct net_device *netdev = platform_get_drvdata(pdev);
2027 struct macb *bp = netdev_priv(netdev);
2028
03fc4721 2029 netif_carrier_off(netdev);
c1f598fd
HS		 2030 netif_device_detach(netdev);
2031
e1824dfe
SB		 2032 if (!IS_ERR(bp->tx_clk))
2033 clk_disable_unprepare(bp->tx_clk);
ace58010
ST		 2034 clk_disable_unprepare(bp->hclk);
2035 clk_disable_unprepare(bp->pclk);
c1f598fd
HS		 2036
2037 return 0;
2038}
2039
0dfc3e18 2040static int macb_resume(struct device *dev)
c1f598fd 2041{
0dfc3e18 2042 struct platform_device *pdev = to_platform_device(dev);
c1f598fd
HS		 2043 struct net_device *netdev = platform_get_drvdata(pdev);
2044 struct macb *bp = netdev_priv(netdev);
2045
ace58010
ST		 2046 clk_prepare_enable(bp->pclk);
2047 clk_prepare_enable(bp->hclk);
e1824dfe
SB		 2048 if (!IS_ERR(bp->tx_clk))
2049 clk_prepare_enable(bp->tx_clk);
c1f598fd
HS		 2050
2051 netif_device_attach(netdev);
2052
2053 return 0;
2054}
c1f598fd
HS		 2055#endif
2056
0dfc3e18
SB		 2057static SIMPLE_DEV_PM_OPS(macb_pm_ops, macb_suspend, macb_resume);
2058
89e5785f 2059static struct platform_driver macb_driver = {
06c3fd6a 2060 .remove = __exit_p(macb_remove),
89e5785f
HS		 2061 .driver = {
2062 .name = "macb",
72abb461 2063 .owner = THIS_MODULE,
fb97a846 2064 .of_match_table = of_match_ptr(macb_dt_ids),
0dfc3e18 2065 .pm = &macb_pm_ops,
89e5785f
HS		 2066 },
2067};
2068
b543a8d8 2069module_platform_driver_probe(macb_driver, macb_probe);
89e5785f
HS		 2070
2071MODULE_LICENSE("GPL");
f75ba50b 2072MODULE_DESCRIPTION("Cadence MACB/GEM Ethernet driver");
e05503ef 2073MODULE_AUTHOR("Haavard Skinnemoen (Atmel)");
72abb461 2074MODULE_ALIAS("platform:macb");
Linux kernel - Deliverables
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