net: macb: Add compatible string for Zynq Ultrascale+ MPSoC
[deliverable/linux.git] / drivers / net / ethernet / cadence / macb.c
CommitLineData
89e5785f 1/*
f75ba50b 2 * Cadence MACB/GEM Ethernet Controller driver
89e5785f
HS
3 *
4 * Copyright (C) 2004-2006 Atmel Corporation
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
c220f8cd 11#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
89e5785f
HS
12#include <linux/clk.h>
13#include <linux/module.h>
14#include <linux/moduleparam.h>
15#include <linux/kernel.h>
16#include <linux/types.h>
909a8583 17#include <linux/circ_buf.h>
89e5785f
HS
18#include <linux/slab.h>
19#include <linux/init.h>
60fe716f 20#include <linux/io.h>
2dbfdbb9 21#include <linux/gpio.h>
a6b7a407 22#include <linux/interrupt.h>
89e5785f
HS
23#include <linux/netdevice.h>
24#include <linux/etherdevice.h>
89e5785f 25#include <linux/dma-mapping.h>
84e0cdb0 26#include <linux/platform_data/macb.h>
89e5785f 27#include <linux/platform_device.h>
6c36a707 28#include <linux/phy.h>
b17471f5 29#include <linux/of.h>
fb97a846 30#include <linux/of_device.h>
148cbb53 31#include <linux/of_mdio.h>
fb97a846 32#include <linux/of_net.h>
89e5785f 33
89e5785f
HS
34#include "macb.h"
35
1b44791a 36#define MACB_RX_BUFFER_SIZE 128
1b44791a 37#define RX_BUFFER_MULTIPLE 64 /* bytes */
55054a16
HS
38#define RX_RING_SIZE 512 /* must be power of 2 */
39#define RX_RING_BYTES (sizeof(struct macb_dma_desc) * RX_RING_SIZE)
89e5785f 40
55054a16
HS
41#define TX_RING_SIZE 128 /* must be power of 2 */
42#define TX_RING_BYTES (sizeof(struct macb_dma_desc) * TX_RING_SIZE)
89e5785f 43
909a8583
NF
44/* level of occupied TX descriptors under which we wake up TX process */
45#define MACB_TX_WAKEUP_THRESH (3 * TX_RING_SIZE / 4)
89e5785f
HS
46
47#define MACB_RX_INT_FLAGS (MACB_BIT(RCOMP) | MACB_BIT(RXUBR) \
48 | MACB_BIT(ISR_ROVR))
e86cd53a
NF
49#define MACB_TX_ERR_FLAGS (MACB_BIT(ISR_TUND) \
50 | MACB_BIT(ISR_RLE) \
51 | MACB_BIT(TXERR))
52#define MACB_TX_INT_FLAGS (MACB_TX_ERR_FLAGS | MACB_BIT(TCOMP))
53
a4c35ed3
CP
54#define MACB_MAX_TX_LEN ((unsigned int)((1 << MACB_TX_FRMLEN_SIZE) - 1))
55#define GEM_MAX_TX_LEN ((unsigned int)((1 << GEM_TX_FRMLEN_SIZE) - 1))
56
e86cd53a
NF
57/*
58 * Graceful stop timeouts in us. We should allow up to
59 * 1 frame time (10 Mbits/s, full-duplex, ignoring collisions)
60 */
61#define MACB_HALT_TIMEOUT 1230
89e5785f 62
55054a16
HS
63/* Ring buffer accessors */
64static unsigned int macb_tx_ring_wrap(unsigned int index)
65{
66 return index & (TX_RING_SIZE - 1);
67}
68
02c958dd
CP
69static struct macb_dma_desc *macb_tx_desc(struct macb_queue *queue,
70 unsigned int index)
55054a16 71{
02c958dd 72 return &queue->tx_ring[macb_tx_ring_wrap(index)];
55054a16
HS
73}
74
02c958dd
CP
75static struct macb_tx_skb *macb_tx_skb(struct macb_queue *queue,
76 unsigned int index)
55054a16 77{
02c958dd 78 return &queue->tx_skb[macb_tx_ring_wrap(index)];
55054a16
HS
79}
80
02c958dd 81static dma_addr_t macb_tx_dma(struct macb_queue *queue, unsigned int index)
55054a16
HS
82{
83 dma_addr_t offset;
84
85 offset = macb_tx_ring_wrap(index) * sizeof(struct macb_dma_desc);
86
02c958dd 87 return queue->tx_ring_dma + offset;
55054a16
HS
88}
89
90static unsigned int macb_rx_ring_wrap(unsigned int index)
91{
92 return index & (RX_RING_SIZE - 1);
93}
94
95static struct macb_dma_desc *macb_rx_desc(struct macb *bp, unsigned int index)
96{
97 return &bp->rx_ring[macb_rx_ring_wrap(index)];
98}
99
100static void *macb_rx_buffer(struct macb *bp, unsigned int index)
101{
1b44791a 102 return bp->rx_buffers + bp->rx_buffer_size * macb_rx_ring_wrap(index);
55054a16
HS
103}
104
421d9df0 105static void macb_set_hwaddr(struct macb *bp)
89e5785f
HS
106{
107 u32 bottom;
108 u16 top;
109
110 bottom = cpu_to_le32(*((u32 *)bp->dev->dev_addr));
f75ba50b 111 macb_or_gem_writel(bp, SA1B, bottom);
89e5785f 112 top = cpu_to_le16(*((u16 *)(bp->dev->dev_addr + 4)));
f75ba50b 113 macb_or_gem_writel(bp, SA1T, top);
3629a6ce
JE
114
115 /* Clear unused address register sets */
116 macb_or_gem_writel(bp, SA2B, 0);
117 macb_or_gem_writel(bp, SA2T, 0);
118 macb_or_gem_writel(bp, SA3B, 0);
119 macb_or_gem_writel(bp, SA3T, 0);
120 macb_or_gem_writel(bp, SA4B, 0);
121 macb_or_gem_writel(bp, SA4T, 0);
89e5785f
HS
122}
123
421d9df0 124static void macb_get_hwaddr(struct macb *bp)
89e5785f 125{
d25e78aa 126 struct macb_platform_data *pdata;
89e5785f
HS
127 u32 bottom;
128 u16 top;
129 u8 addr[6];
17b8bb3e
JE
130 int i;
131
c607a0d9 132 pdata = dev_get_platdata(&bp->pdev->dev);
d25e78aa 133
17b8bb3e
JE
134 /* Check all 4 address register for vaild address */
135 for (i = 0; i < 4; i++) {
136 bottom = macb_or_gem_readl(bp, SA1B + i * 8);
137 top = macb_or_gem_readl(bp, SA1T + i * 8);
138
d25e78aa
JE
139 if (pdata && pdata->rev_eth_addr) {
140 addr[5] = bottom & 0xff;
141 addr[4] = (bottom >> 8) & 0xff;
142 addr[3] = (bottom >> 16) & 0xff;
143 addr[2] = (bottom >> 24) & 0xff;
144 addr[1] = top & 0xff;
145 addr[0] = (top & 0xff00) >> 8;
146 } else {
147 addr[0] = bottom & 0xff;
148 addr[1] = (bottom >> 8) & 0xff;
149 addr[2] = (bottom >> 16) & 0xff;
150 addr[3] = (bottom >> 24) & 0xff;
151 addr[4] = top & 0xff;
152 addr[5] = (top >> 8) & 0xff;
153 }
17b8bb3e
JE
154
155 if (is_valid_ether_addr(addr)) {
156 memcpy(bp->dev->dev_addr, addr, sizeof(addr));
157 return;
158 }
d1d5741d 159 }
17b8bb3e
JE
160
161 netdev_info(bp->dev, "invalid hw address, using random\n");
162 eth_hw_addr_random(bp->dev);
89e5785f
HS
163}
164
6c36a707 165static int macb_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
89e5785f 166{
6c36a707 167 struct macb *bp = bus->priv;
89e5785f
HS
168 int value;
169
89e5785f
HS
170 macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_SOF)
171 | MACB_BF(RW, MACB_MAN_READ)
6c36a707
R
172 | MACB_BF(PHYA, mii_id)
173 | MACB_BF(REGA, regnum)
89e5785f
HS
174 | MACB_BF(CODE, MACB_MAN_CODE)));
175
6c36a707
R
176 /* wait for end of transfer */
177 while (!MACB_BFEXT(IDLE, macb_readl(bp, NSR)))
178 cpu_relax();
89e5785f
HS
179
180 value = MACB_BFEXT(DATA, macb_readl(bp, MAN));
89e5785f
HS
181
182 return value;
183}
184
6c36a707
R
185static int macb_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
186 u16 value)
89e5785f 187{
6c36a707 188 struct macb *bp = bus->priv;
89e5785f
HS
189
190 macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_SOF)
191 | MACB_BF(RW, MACB_MAN_WRITE)
6c36a707
R
192 | MACB_BF(PHYA, mii_id)
193 | MACB_BF(REGA, regnum)
89e5785f 194 | MACB_BF(CODE, MACB_MAN_CODE)
6c36a707 195 | MACB_BF(DATA, value)));
89e5785f 196
6c36a707
R
197 /* wait for end of transfer */
198 while (!MACB_BFEXT(IDLE, macb_readl(bp, NSR)))
199 cpu_relax();
200
201 return 0;
202}
89e5785f 203
e1824dfe
SB
204/**
205 * macb_set_tx_clk() - Set a clock to a new frequency
206 * @clk Pointer to the clock to change
207 * @rate New frequency in Hz
208 * @dev Pointer to the struct net_device
209 */
210static void macb_set_tx_clk(struct clk *clk, int speed, struct net_device *dev)
211{
212 long ferr, rate, rate_rounded;
213
93b31f48
CP
214 if (!clk)
215 return;
216
e1824dfe
SB
217 switch (speed) {
218 case SPEED_10:
219 rate = 2500000;
220 break;
221 case SPEED_100:
222 rate = 25000000;
223 break;
224 case SPEED_1000:
225 rate = 125000000;
226 break;
227 default:
9319e47c 228 return;
e1824dfe
SB
229 }
230
231 rate_rounded = clk_round_rate(clk, rate);
232 if (rate_rounded < 0)
233 return;
234
235 /* RGMII allows 50 ppm frequency error. Test and warn if this limit
236 * is not satisfied.
237 */
238 ferr = abs(rate_rounded - rate);
239 ferr = DIV_ROUND_UP(ferr, rate / 100000);
240 if (ferr > 5)
241 netdev_warn(dev, "unable to generate target frequency: %ld Hz\n",
242 rate);
243
244 if (clk_set_rate(clk, rate_rounded))
245 netdev_err(dev, "adjusting tx_clk failed.\n");
246}
247
6c36a707 248static void macb_handle_link_change(struct net_device *dev)
89e5785f 249{
6c36a707
R
250 struct macb *bp = netdev_priv(dev);
251 struct phy_device *phydev = bp->phy_dev;
252 unsigned long flags;
89e5785f 253
6c36a707 254 int status_change = 0;
89e5785f 255
6c36a707
R
256 spin_lock_irqsave(&bp->lock, flags);
257
258 if (phydev->link) {
259 if ((bp->speed != phydev->speed) ||
260 (bp->duplex != phydev->duplex)) {
261 u32 reg;
262
263 reg = macb_readl(bp, NCFGR);
264 reg &= ~(MACB_BIT(SPD) | MACB_BIT(FD));
140b7552
PV
265 if (macb_is_gem(bp))
266 reg &= ~GEM_BIT(GBE);
6c36a707
R
267
268 if (phydev->duplex)
269 reg |= MACB_BIT(FD);
179956f4 270 if (phydev->speed == SPEED_100)
6c36a707 271 reg |= MACB_BIT(SPD);
e175587f
NF
272 if (phydev->speed == SPEED_1000 &&
273 bp->caps & MACB_CAPS_GIGABIT_MODE_AVAILABLE)
140b7552 274 reg |= GEM_BIT(GBE);
6c36a707 275
140b7552 276 macb_or_gem_writel(bp, NCFGR, reg);
6c36a707
R
277
278 bp->speed = phydev->speed;
279 bp->duplex = phydev->duplex;
280 status_change = 1;
281 }
89e5785f
HS
282 }
283
6c36a707 284 if (phydev->link != bp->link) {
c8f15686 285 if (!phydev->link) {
6c36a707
R
286 bp->speed = 0;
287 bp->duplex = -1;
288 }
289 bp->link = phydev->link;
89e5785f 290
6c36a707
R
291 status_change = 1;
292 }
89e5785f 293
6c36a707
R
294 spin_unlock_irqrestore(&bp->lock, flags);
295
296 if (status_change) {
03fc4721 297 if (phydev->link) {
2c29b235
JA
298 /* Update the TX clock rate if and only if the link is
299 * up and there has been a link change.
300 */
301 macb_set_tx_clk(bp->tx_clk, phydev->speed, dev);
302
03fc4721 303 netif_carrier_on(dev);
c220f8cd
JI
304 netdev_info(dev, "link up (%d/%s)\n",
305 phydev->speed,
306 phydev->duplex == DUPLEX_FULL ?
307 "Full" : "Half");
03fc4721
NF
308 } else {
309 netif_carrier_off(dev);
c220f8cd 310 netdev_info(dev, "link down\n");
03fc4721 311 }
6c36a707 312 }
89e5785f
HS
313}
314
6c36a707
R
315/* based on au1000_eth. c*/
316static int macb_mii_probe(struct net_device *dev)
89e5785f 317{
6c36a707 318 struct macb *bp = netdev_priv(dev);
2dbfdbb9 319 struct macb_platform_data *pdata;
7455a76f 320 struct phy_device *phydev;
2dbfdbb9 321 int phy_irq;
7455a76f 322 int ret;
6c36a707 323
7455a76f 324 phydev = phy_find_first(bp->mii_bus);
6c36a707 325 if (!phydev) {
c220f8cd 326 netdev_err(dev, "no PHY found\n");
7daa78e3 327 return -ENXIO;
6c36a707
R
328 }
329
2dbfdbb9
JE
330 pdata = dev_get_platdata(&bp->pdev->dev);
331 if (pdata && gpio_is_valid(pdata->phy_irq_pin)) {
332 ret = devm_gpio_request(&bp->pdev->dev, pdata->phy_irq_pin, "phy int");
333 if (!ret) {
334 phy_irq = gpio_to_irq(pdata->phy_irq_pin);
335 phydev->irq = (phy_irq < 0) ? PHY_POLL : phy_irq;
336 }
337 }
6c36a707
R
338
339 /* attach the mac to the phy */
f9a8f83b 340 ret = phy_connect_direct(dev, phydev, &macb_handle_link_change,
fb97a846 341 bp->phy_interface);
7455a76f 342 if (ret) {
c220f8cd 343 netdev_err(dev, "Could not attach to PHY\n");
7455a76f 344 return ret;
6c36a707
R
345 }
346
347 /* mask with MAC supported features */
e175587f 348 if (macb_is_gem(bp) && bp->caps & MACB_CAPS_GIGABIT_MODE_AVAILABLE)
140b7552
PV
349 phydev->supported &= PHY_GBIT_FEATURES;
350 else
351 phydev->supported &= PHY_BASIC_FEATURES;
6c36a707
R
352
353 phydev->advertising = phydev->supported;
354
355 bp->link = 0;
356 bp->speed = 0;
357 bp->duplex = -1;
358 bp->phy_dev = phydev;
359
360 return 0;
89e5785f
HS
361}
362
421d9df0 363static int macb_mii_init(struct macb *bp)
89e5785f 364{
84e0cdb0 365 struct macb_platform_data *pdata;
148cbb53 366 struct device_node *np;
6c36a707 367 int err = -ENXIO, i;
89e5785f 368
3dbda77e 369 /* Enable management port */
6c36a707 370 macb_writel(bp, NCR, MACB_BIT(MPE));
89e5785f 371
298cf9be
LB
372 bp->mii_bus = mdiobus_alloc();
373 if (bp->mii_bus == NULL) {
374 err = -ENOMEM;
375 goto err_out;
376 }
377
378 bp->mii_bus->name = "MACB_mii_bus";
379 bp->mii_bus->read = &macb_mdio_read;
380 bp->mii_bus->write = &macb_mdio_write;
98d5e57e
FF
381 snprintf(bp->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
382 bp->pdev->name, bp->pdev->id);
298cf9be
LB
383 bp->mii_bus->priv = bp;
384 bp->mii_bus->parent = &bp->dev->dev;
c607a0d9 385 pdata = dev_get_platdata(&bp->pdev->dev);
89e5785f 386
298cf9be
LB
387 bp->mii_bus->irq = kmalloc(sizeof(int)*PHY_MAX_ADDR, GFP_KERNEL);
388 if (!bp->mii_bus->irq) {
6c36a707 389 err = -ENOMEM;
298cf9be 390 goto err_out_free_mdiobus;
89e5785f
HS
391 }
392
91523947 393 dev_set_drvdata(&bp->dev->dev, bp->mii_bus);
89e5785f 394
148cbb53
BB
395 np = bp->pdev->dev.of_node;
396 if (np) {
397 /* try dt phy registration */
398 err = of_mdiobus_register(bp->mii_bus, np);
399
400 /* fallback to standard phy registration if no phy were
401 found during dt phy registration */
402 if (!err && !phy_find_first(bp->mii_bus)) {
403 for (i = 0; i < PHY_MAX_ADDR; i++) {
404 struct phy_device *phydev;
405
406 phydev = mdiobus_scan(bp->mii_bus, i);
407 if (IS_ERR(phydev)) {
408 err = PTR_ERR(phydev);
409 break;
410 }
411 }
412
413 if (err)
414 goto err_out_unregister_bus;
415 }
416 } else {
417 for (i = 0; i < PHY_MAX_ADDR; i++)
418 bp->mii_bus->irq[i] = PHY_POLL;
419
420 if (pdata)
421 bp->mii_bus->phy_mask = pdata->phy_mask;
422
423 err = mdiobus_register(bp->mii_bus);
424 }
425
426 if (err)
6c36a707 427 goto err_out_free_mdio_irq;
89e5785f 428
7daa78e3
BB
429 err = macb_mii_probe(bp->dev);
430 if (err)
6c36a707 431 goto err_out_unregister_bus;
89e5785f 432
6c36a707 433 return 0;
89e5785f 434
6c36a707 435err_out_unregister_bus:
298cf9be 436 mdiobus_unregister(bp->mii_bus);
6c36a707 437err_out_free_mdio_irq:
298cf9be
LB
438 kfree(bp->mii_bus->irq);
439err_out_free_mdiobus:
440 mdiobus_free(bp->mii_bus);
6c36a707
R
441err_out:
442 return err;
89e5785f
HS
443}
444
445static void macb_update_stats(struct macb *bp)
446{
447 u32 __iomem *reg = bp->regs + MACB_PFR;
a494ed8e
JI
448 u32 *p = &bp->hw_stats.macb.rx_pause_frames;
449 u32 *end = &bp->hw_stats.macb.tx_pause_frames + 1;
89e5785f
HS
450
451 WARN_ON((unsigned long)(end - p - 1) != (MACB_TPF - MACB_PFR) / 4);
452
453 for(; p < end; p++, reg++)
a50dad35 454 *p += readl_relaxed(reg);
89e5785f
HS
455}
456
e86cd53a 457static int macb_halt_tx(struct macb *bp)
89e5785f 458{
e86cd53a
NF
459 unsigned long halt_time, timeout;
460 u32 status;
89e5785f 461
e86cd53a 462 macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(THALT));
89e5785f 463
e86cd53a
NF
464 timeout = jiffies + usecs_to_jiffies(MACB_HALT_TIMEOUT);
465 do {
466 halt_time = jiffies;
467 status = macb_readl(bp, TSR);
468 if (!(status & MACB_BIT(TGO)))
469 return 0;
89e5785f 470
e86cd53a
NF
471 usleep_range(10, 250);
472 } while (time_before(halt_time, timeout));
bdcba151 473
e86cd53a
NF
474 return -ETIMEDOUT;
475}
39eddb4c 476
a4c35ed3
CP
477static void macb_tx_unmap(struct macb *bp, struct macb_tx_skb *tx_skb)
478{
479 if (tx_skb->mapping) {
480 if (tx_skb->mapped_as_page)
481 dma_unmap_page(&bp->pdev->dev, tx_skb->mapping,
482 tx_skb->size, DMA_TO_DEVICE);
483 else
484 dma_unmap_single(&bp->pdev->dev, tx_skb->mapping,
485 tx_skb->size, DMA_TO_DEVICE);
486 tx_skb->mapping = 0;
487 }
488
489 if (tx_skb->skb) {
490 dev_kfree_skb_any(tx_skb->skb);
491 tx_skb->skb = NULL;
492 }
493}
494
e86cd53a
NF
495static void macb_tx_error_task(struct work_struct *work)
496{
02c958dd
CP
497 struct macb_queue *queue = container_of(work, struct macb_queue,
498 tx_error_task);
499 struct macb *bp = queue->bp;
e86cd53a 500 struct macb_tx_skb *tx_skb;
02c958dd 501 struct macb_dma_desc *desc;
e86cd53a
NF
502 struct sk_buff *skb;
503 unsigned int tail;
02c958dd
CP
504 unsigned long flags;
505
506 netdev_vdbg(bp->dev, "macb_tx_error_task: q = %u, t = %u, h = %u\n",
507 (unsigned int)(queue - bp->queues),
508 queue->tx_tail, queue->tx_head);
bdcba151 509
02c958dd
CP
510 /* Prevent the queue IRQ handlers from running: each of them may call
511 * macb_tx_interrupt(), which in turn may call netif_wake_subqueue().
512 * As explained below, we have to halt the transmission before updating
513 * TBQP registers so we call netif_tx_stop_all_queues() to notify the
514 * network engine about the macb/gem being halted.
515 */
516 spin_lock_irqsave(&bp->lock, flags);
bdcba151 517
e86cd53a 518 /* Make sure nobody is trying to queue up new packets */
02c958dd 519 netif_tx_stop_all_queues(bp->dev);
d3e61457 520
e86cd53a
NF
521 /*
522 * Stop transmission now
523 * (in case we have just queued new packets)
02c958dd 524 * macb/gem must be halted to write TBQP register
e86cd53a
NF
525 */
526 if (macb_halt_tx(bp))
527 /* Just complain for now, reinitializing TX path can be good */
528 netdev_err(bp->dev, "BUG: halt tx timed out\n");
bdcba151 529
e86cd53a
NF
530 /*
531 * Treat frames in TX queue including the ones that caused the error.
532 * Free transmit buffers in upper layer.
533 */
02c958dd
CP
534 for (tail = queue->tx_tail; tail != queue->tx_head; tail++) {
535 u32 ctrl;
55054a16 536
02c958dd 537 desc = macb_tx_desc(queue, tail);
e86cd53a 538 ctrl = desc->ctrl;
02c958dd 539 tx_skb = macb_tx_skb(queue, tail);
e86cd53a 540 skb = tx_skb->skb;
bdcba151 541
e86cd53a 542 if (ctrl & MACB_BIT(TX_USED)) {
a4c35ed3
CP
543 /* skb is set for the last buffer of the frame */
544 while (!skb) {
545 macb_tx_unmap(bp, tx_skb);
546 tail++;
02c958dd 547 tx_skb = macb_tx_skb(queue, tail);
a4c35ed3
CP
548 skb = tx_skb->skb;
549 }
550
551 /* ctrl still refers to the first buffer descriptor
552 * since it's the only one written back by the hardware
553 */
554 if (!(ctrl & MACB_BIT(TX_BUF_EXHAUSTED))) {
555 netdev_vdbg(bp->dev, "txerr skb %u (data %p) TX complete\n",
556 macb_tx_ring_wrap(tail), skb->data);
557 bp->stats.tx_packets++;
558 bp->stats.tx_bytes += skb->len;
559 }
e86cd53a
NF
560 } else {
561 /*
562 * "Buffers exhausted mid-frame" errors may only happen
563 * if the driver is buggy, so complain loudly about those.
564 * Statistics are updated by hardware.
565 */
566 if (ctrl & MACB_BIT(TX_BUF_EXHAUSTED))
567 netdev_err(bp->dev,
568 "BUG: TX buffers exhausted mid-frame\n");
39eddb4c 569
e86cd53a
NF
570 desc->ctrl = ctrl | MACB_BIT(TX_USED);
571 }
572
a4c35ed3 573 macb_tx_unmap(bp, tx_skb);
89e5785f
HS
574 }
575
02c958dd
CP
576 /* Set end of TX queue */
577 desc = macb_tx_desc(queue, 0);
578 desc->addr = 0;
579 desc->ctrl = MACB_BIT(TX_USED);
580
e86cd53a
NF
581 /* Make descriptor updates visible to hardware */
582 wmb();
583
584 /* Reinitialize the TX desc queue */
02c958dd 585 queue_writel(queue, TBQP, queue->tx_ring_dma);
e86cd53a 586 /* Make TX ring reflect state of hardware */
02c958dd
CP
587 queue->tx_head = 0;
588 queue->tx_tail = 0;
e86cd53a
NF
589
590 /* Housework before enabling TX IRQ */
591 macb_writel(bp, TSR, macb_readl(bp, TSR));
02c958dd
CP
592 queue_writel(queue, IER, MACB_TX_INT_FLAGS);
593
594 /* Now we are ready to start transmission again */
595 netif_tx_start_all_queues(bp->dev);
596 macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(TSTART));
597
598 spin_unlock_irqrestore(&bp->lock, flags);
e86cd53a
NF
599}
600
02c958dd 601static void macb_tx_interrupt(struct macb_queue *queue)
e86cd53a
NF
602{
603 unsigned int tail;
604 unsigned int head;
605 u32 status;
02c958dd
CP
606 struct macb *bp = queue->bp;
607 u16 queue_index = queue - bp->queues;
e86cd53a
NF
608
609 status = macb_readl(bp, TSR);
610 macb_writel(bp, TSR, status);
611
581df9e1 612 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
02c958dd 613 queue_writel(queue, ISR, MACB_BIT(TCOMP));
749a2b66 614
e86cd53a
NF
615 netdev_vdbg(bp->dev, "macb_tx_interrupt status = 0x%03lx\n",
616 (unsigned long)status);
89e5785f 617
02c958dd
CP
618 head = queue->tx_head;
619 for (tail = queue->tx_tail; tail != head; tail++) {
55054a16
HS
620 struct macb_tx_skb *tx_skb;
621 struct sk_buff *skb;
622 struct macb_dma_desc *desc;
623 u32 ctrl;
89e5785f 624
02c958dd 625 desc = macb_tx_desc(queue, tail);
89e5785f 626
03dbe05f 627 /* Make hw descriptor updates visible to CPU */
89e5785f 628 rmb();
03dbe05f 629
55054a16 630 ctrl = desc->ctrl;
89e5785f 631
a4c35ed3
CP
632 /* TX_USED bit is only set by hardware on the very first buffer
633 * descriptor of the transmitted frame.
634 */
55054a16 635 if (!(ctrl & MACB_BIT(TX_USED)))
89e5785f
HS
636 break;
637
a4c35ed3
CP
638 /* Process all buffers of the current transmitted frame */
639 for (;; tail++) {
02c958dd 640 tx_skb = macb_tx_skb(queue, tail);
a4c35ed3
CP
641 skb = tx_skb->skb;
642
643 /* First, update TX stats if needed */
644 if (skb) {
645 netdev_vdbg(bp->dev, "skb %u (data %p) TX complete\n",
646 macb_tx_ring_wrap(tail), skb->data);
647 bp->stats.tx_packets++;
648 bp->stats.tx_bytes += skb->len;
649 }
55054a16 650
a4c35ed3
CP
651 /* Now we can safely release resources */
652 macb_tx_unmap(bp, tx_skb);
653
654 /* skb is set only for the last buffer of the frame.
655 * WARNING: at this point skb has been freed by
656 * macb_tx_unmap().
657 */
658 if (skb)
659 break;
660 }
89e5785f
HS
661 }
662
02c958dd
CP
663 queue->tx_tail = tail;
664 if (__netif_subqueue_stopped(bp->dev, queue_index) &&
665 CIRC_CNT(queue->tx_head, queue->tx_tail,
666 TX_RING_SIZE) <= MACB_TX_WAKEUP_THRESH)
667 netif_wake_subqueue(bp->dev, queue_index);
89e5785f
HS
668}
669
4df95131
NF
670static void gem_rx_refill(struct macb *bp)
671{
672 unsigned int entry;
673 struct sk_buff *skb;
4df95131
NF
674 dma_addr_t paddr;
675
676 while (CIRC_SPACE(bp->rx_prepared_head, bp->rx_tail, RX_RING_SIZE) > 0) {
4df95131 677 entry = macb_rx_ring_wrap(bp->rx_prepared_head);
4df95131
NF
678
679 /* Make hw descriptor updates visible to CPU */
680 rmb();
681
4df95131
NF
682 bp->rx_prepared_head++;
683
4df95131
NF
684 if (bp->rx_skbuff[entry] == NULL) {
685 /* allocate sk_buff for this free entry in ring */
686 skb = netdev_alloc_skb(bp->dev, bp->rx_buffer_size);
687 if (unlikely(skb == NULL)) {
688 netdev_err(bp->dev,
689 "Unable to allocate sk_buff\n");
690 break;
691 }
4df95131
NF
692
693 /* now fill corresponding descriptor entry */
694 paddr = dma_map_single(&bp->pdev->dev, skb->data,
695 bp->rx_buffer_size, DMA_FROM_DEVICE);
92030908
SB
696 if (dma_mapping_error(&bp->pdev->dev, paddr)) {
697 dev_kfree_skb(skb);
698 break;
699 }
700
701 bp->rx_skbuff[entry] = skb;
4df95131
NF
702
703 if (entry == RX_RING_SIZE - 1)
704 paddr |= MACB_BIT(RX_WRAP);
705 bp->rx_ring[entry].addr = paddr;
706 bp->rx_ring[entry].ctrl = 0;
707
708 /* properly align Ethernet header */
709 skb_reserve(skb, NET_IP_ALIGN);
d4c216c5
PCK
710 } else {
711 bp->rx_ring[entry].addr &= ~MACB_BIT(RX_USED);
712 bp->rx_ring[entry].ctrl = 0;
4df95131
NF
713 }
714 }
715
716 /* Make descriptor updates visible to hardware */
717 wmb();
718
719 netdev_vdbg(bp->dev, "rx ring: prepared head %d, tail %d\n",
720 bp->rx_prepared_head, bp->rx_tail);
721}
722
723/* Mark DMA descriptors from begin up to and not including end as unused */
724static void discard_partial_frame(struct macb *bp, unsigned int begin,
725 unsigned int end)
726{
727 unsigned int frag;
728
729 for (frag = begin; frag != end; frag++) {
730 struct macb_dma_desc *desc = macb_rx_desc(bp, frag);
731 desc->addr &= ~MACB_BIT(RX_USED);
732 }
733
734 /* Make descriptor updates visible to hardware */
735 wmb();
736
737 /*
738 * When this happens, the hardware stats registers for
739 * whatever caused this is updated, so we don't have to record
740 * anything.
741 */
742}
743
744static int gem_rx(struct macb *bp, int budget)
745{
746 unsigned int len;
747 unsigned int entry;
748 struct sk_buff *skb;
749 struct macb_dma_desc *desc;
750 int count = 0;
751
752 while (count < budget) {
753 u32 addr, ctrl;
754
755 entry = macb_rx_ring_wrap(bp->rx_tail);
756 desc = &bp->rx_ring[entry];
757
758 /* Make hw descriptor updates visible to CPU */
759 rmb();
760
761 addr = desc->addr;
762 ctrl = desc->ctrl;
763
764 if (!(addr & MACB_BIT(RX_USED)))
765 break;
766
4df95131
NF
767 bp->rx_tail++;
768 count++;
769
770 if (!(ctrl & MACB_BIT(RX_SOF) && ctrl & MACB_BIT(RX_EOF))) {
771 netdev_err(bp->dev,
772 "not whole frame pointed by descriptor\n");
773 bp->stats.rx_dropped++;
774 break;
775 }
776 skb = bp->rx_skbuff[entry];
777 if (unlikely(!skb)) {
778 netdev_err(bp->dev,
779 "inconsistent Rx descriptor chain\n");
780 bp->stats.rx_dropped++;
781 break;
782 }
783 /* now everything is ready for receiving packet */
784 bp->rx_skbuff[entry] = NULL;
785 len = MACB_BFEXT(RX_FRMLEN, ctrl);
786
787 netdev_vdbg(bp->dev, "gem_rx %u (len %u)\n", entry, len);
788
789 skb_put(skb, len);
790 addr = MACB_BF(RX_WADDR, MACB_BFEXT(RX_WADDR, addr));
791 dma_unmap_single(&bp->pdev->dev, addr,
48330e08 792 bp->rx_buffer_size, DMA_FROM_DEVICE);
4df95131
NF
793
794 skb->protocol = eth_type_trans(skb, bp->dev);
795 skb_checksum_none_assert(skb);
924ec53c
CP
796 if (bp->dev->features & NETIF_F_RXCSUM &&
797 !(bp->dev->flags & IFF_PROMISC) &&
798 GEM_BFEXT(RX_CSUM, ctrl) & GEM_RX_CSUM_CHECKED_MASK)
799 skb->ip_summed = CHECKSUM_UNNECESSARY;
4df95131
NF
800
801 bp->stats.rx_packets++;
802 bp->stats.rx_bytes += skb->len;
803
804#if defined(DEBUG) && defined(VERBOSE_DEBUG)
805 netdev_vdbg(bp->dev, "received skb of length %u, csum: %08x\n",
806 skb->len, skb->csum);
807 print_hex_dump(KERN_DEBUG, " mac: ", DUMP_PREFIX_ADDRESS, 16, 1,
51f83014 808 skb_mac_header(skb), 16, true);
4df95131
NF
809 print_hex_dump(KERN_DEBUG, "data: ", DUMP_PREFIX_ADDRESS, 16, 1,
810 skb->data, 32, true);
811#endif
812
813 netif_receive_skb(skb);
814 }
815
816 gem_rx_refill(bp);
817
818 return count;
819}
820
89e5785f
HS
821static int macb_rx_frame(struct macb *bp, unsigned int first_frag,
822 unsigned int last_frag)
823{
824 unsigned int len;
825 unsigned int frag;
29bc2e1e 826 unsigned int offset;
89e5785f 827 struct sk_buff *skb;
55054a16 828 struct macb_dma_desc *desc;
89e5785f 829
55054a16
HS
830 desc = macb_rx_desc(bp, last_frag);
831 len = MACB_BFEXT(RX_FRMLEN, desc->ctrl);
89e5785f 832
a268adb1 833 netdev_vdbg(bp->dev, "macb_rx_frame frags %u - %u (len %u)\n",
55054a16
HS
834 macb_rx_ring_wrap(first_frag),
835 macb_rx_ring_wrap(last_frag), len);
89e5785f 836
29bc2e1e
HS
837 /*
838 * The ethernet header starts NET_IP_ALIGN bytes into the
839 * first buffer. Since the header is 14 bytes, this makes the
840 * payload word-aligned.
841 *
842 * Instead of calling skb_reserve(NET_IP_ALIGN), we just copy
843 * the two padding bytes into the skb so that we avoid hitting
844 * the slowpath in memcpy(), and pull them off afterwards.
845 */
846 skb = netdev_alloc_skb(bp->dev, len + NET_IP_ALIGN);
89e5785f
HS
847 if (!skb) {
848 bp->stats.rx_dropped++;
55054a16
HS
849 for (frag = first_frag; ; frag++) {
850 desc = macb_rx_desc(bp, frag);
851 desc->addr &= ~MACB_BIT(RX_USED);
89e5785f
HS
852 if (frag == last_frag)
853 break;
854 }
03dbe05f
HS
855
856 /* Make descriptor updates visible to hardware */
89e5785f 857 wmb();
03dbe05f 858
89e5785f
HS
859 return 1;
860 }
861
29bc2e1e
HS
862 offset = 0;
863 len += NET_IP_ALIGN;
bc8acf2c 864 skb_checksum_none_assert(skb);
89e5785f
HS
865 skb_put(skb, len);
866
55054a16 867 for (frag = first_frag; ; frag++) {
1b44791a 868 unsigned int frag_len = bp->rx_buffer_size;
89e5785f
HS
869
870 if (offset + frag_len > len) {
871 BUG_ON(frag != last_frag);
872 frag_len = len - offset;
873 }
27d7ff46 874 skb_copy_to_linear_data_offset(skb, offset,
55054a16 875 macb_rx_buffer(bp, frag), frag_len);
1b44791a 876 offset += bp->rx_buffer_size;
55054a16
HS
877 desc = macb_rx_desc(bp, frag);
878 desc->addr &= ~MACB_BIT(RX_USED);
89e5785f
HS
879
880 if (frag == last_frag)
881 break;
882 }
883
03dbe05f
HS
884 /* Make descriptor updates visible to hardware */
885 wmb();
886
29bc2e1e 887 __skb_pull(skb, NET_IP_ALIGN);
89e5785f
HS
888 skb->protocol = eth_type_trans(skb, bp->dev);
889
890 bp->stats.rx_packets++;
29bc2e1e 891 bp->stats.rx_bytes += skb->len;
a268adb1 892 netdev_vdbg(bp->dev, "received skb of length %u, csum: %08x\n",
c220f8cd 893 skb->len, skb->csum);
89e5785f
HS
894 netif_receive_skb(skb);
895
896 return 0;
897}
898
89e5785f
HS
899static int macb_rx(struct macb *bp, int budget)
900{
901 int received = 0;
55054a16 902 unsigned int tail;
89e5785f
HS
903 int first_frag = -1;
904
55054a16
HS
905 for (tail = bp->rx_tail; budget > 0; tail++) {
906 struct macb_dma_desc *desc = macb_rx_desc(bp, tail);
89e5785f
HS
907 u32 addr, ctrl;
908
03dbe05f 909 /* Make hw descriptor updates visible to CPU */
89e5785f 910 rmb();
03dbe05f 911
55054a16
HS
912 addr = desc->addr;
913 ctrl = desc->ctrl;
89e5785f
HS
914
915 if (!(addr & MACB_BIT(RX_USED)))
916 break;
917
918 if (ctrl & MACB_BIT(RX_SOF)) {
919 if (first_frag != -1)
920 discard_partial_frame(bp, first_frag, tail);
921 first_frag = tail;
922 }
923
924 if (ctrl & MACB_BIT(RX_EOF)) {
925 int dropped;
926 BUG_ON(first_frag == -1);
927
928 dropped = macb_rx_frame(bp, first_frag, tail);
929 first_frag = -1;
930 if (!dropped) {
931 received++;
932 budget--;
933 }
934 }
935 }
936
937 if (first_frag != -1)
938 bp->rx_tail = first_frag;
939 else
940 bp->rx_tail = tail;
941
942 return received;
943}
944
bea3348e 945static int macb_poll(struct napi_struct *napi, int budget)
89e5785f 946{
bea3348e 947 struct macb *bp = container_of(napi, struct macb, napi);
bea3348e 948 int work_done;
89e5785f
HS
949 u32 status;
950
951 status = macb_readl(bp, RSR);
952 macb_writel(bp, RSR, status);
953
bea3348e 954 work_done = 0;
89e5785f 955
a268adb1 956 netdev_vdbg(bp->dev, "poll: status = %08lx, budget = %d\n",
c220f8cd 957 (unsigned long)status, budget);
89e5785f 958
4df95131 959 work_done = bp->macbgem_ops.mog_rx(bp, budget);
b336369c 960 if (work_done < budget) {
288379f0 961 napi_complete(napi);
89e5785f 962
8770e91a
NF
963 /* Packets received while interrupts were disabled */
964 status = macb_readl(bp, RSR);
504ad98d 965 if (status) {
02f7a34f
SB
966 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
967 macb_writel(bp, ISR, MACB_BIT(RCOMP));
8770e91a 968 napi_reschedule(napi);
02f7a34f
SB
969 } else {
970 macb_writel(bp, IER, MACB_RX_INT_FLAGS);
971 }
b336369c 972 }
89e5785f
HS
973
974 /* TODO: Handle errors */
975
bea3348e 976 return work_done;
89e5785f
HS
977}
978
979static irqreturn_t macb_interrupt(int irq, void *dev_id)
980{
02c958dd
CP
981 struct macb_queue *queue = dev_id;
982 struct macb *bp = queue->bp;
983 struct net_device *dev = bp->dev;
89e5785f
HS
984 u32 status;
985
02c958dd 986 status = queue_readl(queue, ISR);
89e5785f
HS
987
988 if (unlikely(!status))
989 return IRQ_NONE;
990
991 spin_lock(&bp->lock);
992
993 while (status) {
89e5785f
HS
994 /* close possible race with dev_close */
995 if (unlikely(!netif_running(dev))) {
02c958dd 996 queue_writel(queue, IDR, -1);
89e5785f
HS
997 break;
998 }
999
02c958dd
CP
1000 netdev_vdbg(bp->dev, "queue = %u, isr = 0x%08lx\n",
1001 (unsigned int)(queue - bp->queues),
1002 (unsigned long)status);
a268adb1 1003
89e5785f 1004 if (status & MACB_RX_INT_FLAGS) {
b336369c
JH
1005 /*
1006 * There's no point taking any more interrupts
1007 * until we have processed the buffers. The
1008 * scheduling call may fail if the poll routine
1009 * is already scheduled, so disable interrupts
1010 * now.
1011 */
02c958dd 1012 queue_writel(queue, IDR, MACB_RX_INT_FLAGS);
581df9e1 1013 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
02c958dd 1014 queue_writel(queue, ISR, MACB_BIT(RCOMP));
b336369c 1015
288379f0 1016 if (napi_schedule_prep(&bp->napi)) {
a268adb1 1017 netdev_vdbg(bp->dev, "scheduling RX softirq\n");
288379f0 1018 __napi_schedule(&bp->napi);
89e5785f
HS
1019 }
1020 }
1021
e86cd53a 1022 if (unlikely(status & (MACB_TX_ERR_FLAGS))) {
02c958dd
CP
1023 queue_writel(queue, IDR, MACB_TX_INT_FLAGS);
1024 schedule_work(&queue->tx_error_task);
6a027b70
SB
1025
1026 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
02c958dd 1027 queue_writel(queue, ISR, MACB_TX_ERR_FLAGS);
6a027b70 1028
e86cd53a
NF
1029 break;
1030 }
1031
1032 if (status & MACB_BIT(TCOMP))
02c958dd 1033 macb_tx_interrupt(queue);
89e5785f
HS
1034
1035 /*
1036 * Link change detection isn't possible with RMII, so we'll
1037 * add that if/when we get our hands on a full-blown MII PHY.
1038 */
1039
b19f7f71
AS
1040 if (status & MACB_BIT(ISR_ROVR)) {
1041 /* We missed at least one packet */
f75ba50b
JI
1042 if (macb_is_gem(bp))
1043 bp->hw_stats.gem.rx_overruns++;
1044 else
1045 bp->hw_stats.macb.rx_overruns++;
6a027b70
SB
1046
1047 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
02c958dd 1048 queue_writel(queue, ISR, MACB_BIT(ISR_ROVR));
b19f7f71
AS
1049 }
1050
89e5785f
HS
1051 if (status & MACB_BIT(HRESP)) {
1052 /*
c220f8cd
JI
1053 * TODO: Reset the hardware, and maybe move the
1054 * netdev_err to a lower-priority context as well
1055 * (work queue?)
89e5785f 1056 */
c220f8cd 1057 netdev_err(dev, "DMA bus error: HRESP not OK\n");
6a027b70
SB
1058
1059 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
02c958dd 1060 queue_writel(queue, ISR, MACB_BIT(HRESP));
89e5785f
HS
1061 }
1062
02c958dd 1063 status = queue_readl(queue, ISR);
89e5785f
HS
1064 }
1065
1066 spin_unlock(&bp->lock);
1067
1068 return IRQ_HANDLED;
1069}
1070
6e8cf5c0
TP
1071#ifdef CONFIG_NET_POLL_CONTROLLER
1072/*
1073 * Polling receive - used by netconsole and other diagnostic tools
1074 * to allow network i/o with interrupts disabled.
1075 */
1076static void macb_poll_controller(struct net_device *dev)
1077{
02c958dd
CP
1078 struct macb *bp = netdev_priv(dev);
1079 struct macb_queue *queue;
6e8cf5c0 1080 unsigned long flags;
02c958dd 1081 unsigned int q;
6e8cf5c0
TP
1082
1083 local_irq_save(flags);
02c958dd
CP
1084 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue)
1085 macb_interrupt(dev->irq, queue);
6e8cf5c0
TP
1086 local_irq_restore(flags);
1087}
1088#endif
1089
a4c35ed3
CP
1090static inline unsigned int macb_count_tx_descriptors(struct macb *bp,
1091 unsigned int len)
1092{
1093 return (len + bp->max_tx_length - 1) / bp->max_tx_length;
1094}
1095
1096static unsigned int macb_tx_map(struct macb *bp,
02c958dd 1097 struct macb_queue *queue,
a4c35ed3 1098 struct sk_buff *skb)
89e5785f 1099{
89e5785f 1100 dma_addr_t mapping;
02c958dd 1101 unsigned int len, entry, i, tx_head = queue->tx_head;
a4c35ed3 1102 struct macb_tx_skb *tx_skb = NULL;
55054a16 1103 struct macb_dma_desc *desc;
a4c35ed3
CP
1104 unsigned int offset, size, count = 0;
1105 unsigned int f, nr_frags = skb_shinfo(skb)->nr_frags;
1106 unsigned int eof = 1;
89e5785f 1107 u32 ctrl;
a4c35ed3
CP
1108
1109 /* First, map non-paged data */
1110 len = skb_headlen(skb);
1111 offset = 0;
1112 while (len) {
1113 size = min(len, bp->max_tx_length);
1114 entry = macb_tx_ring_wrap(tx_head);
02c958dd 1115 tx_skb = &queue->tx_skb[entry];
a4c35ed3
CP
1116
1117 mapping = dma_map_single(&bp->pdev->dev,
1118 skb->data + offset,
1119 size, DMA_TO_DEVICE);
1120 if (dma_mapping_error(&bp->pdev->dev, mapping))
1121 goto dma_error;
1122
1123 /* Save info to properly release resources */
1124 tx_skb->skb = NULL;
1125 tx_skb->mapping = mapping;
1126 tx_skb->size = size;
1127 tx_skb->mapped_as_page = false;
1128
1129 len -= size;
1130 offset += size;
1131 count++;
1132 tx_head++;
1133 }
1134
1135 /* Then, map paged data from fragments */
1136 for (f = 0; f < nr_frags; f++) {
1137 const skb_frag_t *frag = &skb_shinfo(skb)->frags[f];
1138
1139 len = skb_frag_size(frag);
1140 offset = 0;
1141 while (len) {
1142 size = min(len, bp->max_tx_length);
1143 entry = macb_tx_ring_wrap(tx_head);
02c958dd 1144 tx_skb = &queue->tx_skb[entry];
a4c35ed3
CP
1145
1146 mapping = skb_frag_dma_map(&bp->pdev->dev, frag,
1147 offset, size, DMA_TO_DEVICE);
1148 if (dma_mapping_error(&bp->pdev->dev, mapping))
1149 goto dma_error;
1150
1151 /* Save info to properly release resources */
1152 tx_skb->skb = NULL;
1153 tx_skb->mapping = mapping;
1154 tx_skb->size = size;
1155 tx_skb->mapped_as_page = true;
1156
1157 len -= size;
1158 offset += size;
1159 count++;
1160 tx_head++;
1161 }
1162 }
1163
1164 /* Should never happen */
1165 if (unlikely(tx_skb == NULL)) {
1166 netdev_err(bp->dev, "BUG! empty skb!\n");
1167 return 0;
1168 }
1169
1170 /* This is the last buffer of the frame: save socket buffer */
1171 tx_skb->skb = skb;
1172
1173 /* Update TX ring: update buffer descriptors in reverse order
1174 * to avoid race condition
1175 */
1176
1177 /* Set 'TX_USED' bit in buffer descriptor at tx_head position
1178 * to set the end of TX queue
1179 */
1180 i = tx_head;
1181 entry = macb_tx_ring_wrap(i);
1182 ctrl = MACB_BIT(TX_USED);
02c958dd 1183 desc = &queue->tx_ring[entry];
a4c35ed3
CP
1184 desc->ctrl = ctrl;
1185
1186 do {
1187 i--;
1188 entry = macb_tx_ring_wrap(i);
02c958dd
CP
1189 tx_skb = &queue->tx_skb[entry];
1190 desc = &queue->tx_ring[entry];
a4c35ed3
CP
1191
1192 ctrl = (u32)tx_skb->size;
1193 if (eof) {
1194 ctrl |= MACB_BIT(TX_LAST);
1195 eof = 0;
1196 }
1197 if (unlikely(entry == (TX_RING_SIZE - 1)))
1198 ctrl |= MACB_BIT(TX_WRAP);
1199
1200 /* Set TX buffer descriptor */
1201 desc->addr = tx_skb->mapping;
1202 /* desc->addr must be visible to hardware before clearing
1203 * 'TX_USED' bit in desc->ctrl.
1204 */
1205 wmb();
1206 desc->ctrl = ctrl;
02c958dd 1207 } while (i != queue->tx_head);
a4c35ed3 1208
02c958dd 1209 queue->tx_head = tx_head;
a4c35ed3
CP
1210
1211 return count;
1212
1213dma_error:
1214 netdev_err(bp->dev, "TX DMA map failed\n");
1215
02c958dd
CP
1216 for (i = queue->tx_head; i != tx_head; i++) {
1217 tx_skb = macb_tx_skb(queue, i);
a4c35ed3
CP
1218
1219 macb_tx_unmap(bp, tx_skb);
1220 }
1221
1222 return 0;
1223}
1224
1225static int macb_start_xmit(struct sk_buff *skb, struct net_device *dev)
1226{
02c958dd 1227 u16 queue_index = skb_get_queue_mapping(skb);
a4c35ed3 1228 struct macb *bp = netdev_priv(dev);
02c958dd 1229 struct macb_queue *queue = &bp->queues[queue_index];
4871953c 1230 unsigned long flags;
a4c35ed3 1231 unsigned int count, nr_frags, frag_size, f;
89e5785f 1232
a268adb1
HS
1233#if defined(DEBUG) && defined(VERBOSE_DEBUG)
1234 netdev_vdbg(bp->dev,
02c958dd
CP
1235 "start_xmit: queue %hu len %u head %p data %p tail %p end %p\n",
1236 queue_index, skb->len, skb->head, skb->data,
c220f8cd
JI
1237 skb_tail_pointer(skb), skb_end_pointer(skb));
1238 print_hex_dump(KERN_DEBUG, "data: ", DUMP_PREFIX_OFFSET, 16, 1,
1239 skb->data, 16, true);
89e5785f
HS
1240#endif
1241
a4c35ed3
CP
1242 /* Count how many TX buffer descriptors are needed to send this
1243 * socket buffer: skb fragments of jumbo frames may need to be
1244 * splitted into many buffer descriptors.
1245 */
1246 count = macb_count_tx_descriptors(bp, skb_headlen(skb));
1247 nr_frags = skb_shinfo(skb)->nr_frags;
1248 for (f = 0; f < nr_frags; f++) {
1249 frag_size = skb_frag_size(&skb_shinfo(skb)->frags[f]);
1250 count += macb_count_tx_descriptors(bp, frag_size);
1251 }
1252
4871953c 1253 spin_lock_irqsave(&bp->lock, flags);
89e5785f
HS
1254
1255 /* This is a hard error, log it. */
02c958dd
CP
1256 if (CIRC_SPACE(queue->tx_head, queue->tx_tail, TX_RING_SIZE) < count) {
1257 netif_stop_subqueue(dev, queue_index);
4871953c 1258 spin_unlock_irqrestore(&bp->lock, flags);
c220f8cd 1259 netdev_dbg(bp->dev, "tx_head = %u, tx_tail = %u\n",
02c958dd 1260 queue->tx_head, queue->tx_tail);
5b548140 1261 return NETDEV_TX_BUSY;
89e5785f
HS
1262 }
1263
a4c35ed3 1264 /* Map socket buffer for DMA transfer */
02c958dd 1265 if (!macb_tx_map(bp, queue, skb)) {
c88b5b6a 1266 dev_kfree_skb_any(skb);
92030908
SB
1267 goto unlock;
1268 }
55054a16 1269
03dbe05f 1270 /* Make newly initialized descriptor visible to hardware */
89e5785f
HS
1271 wmb();
1272
e072092f
RC
1273 skb_tx_timestamp(skb);
1274
89e5785f
HS
1275 macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(TSTART));
1276
02c958dd
CP
1277 if (CIRC_SPACE(queue->tx_head, queue->tx_tail, TX_RING_SIZE) < 1)
1278 netif_stop_subqueue(dev, queue_index);
89e5785f 1279
92030908 1280unlock:
4871953c 1281 spin_unlock_irqrestore(&bp->lock, flags);
89e5785f 1282
6ed10654 1283 return NETDEV_TX_OK;
89e5785f
HS
1284}
1285
4df95131 1286static void macb_init_rx_buffer_size(struct macb *bp, size_t size)
1b44791a
NF
1287{
1288 if (!macb_is_gem(bp)) {
1289 bp->rx_buffer_size = MACB_RX_BUFFER_SIZE;
1290 } else {
4df95131 1291 bp->rx_buffer_size = size;
1b44791a 1292
1b44791a 1293 if (bp->rx_buffer_size % RX_BUFFER_MULTIPLE) {
4df95131
NF
1294 netdev_dbg(bp->dev,
1295 "RX buffer must be multiple of %d bytes, expanding\n",
1b44791a
NF
1296 RX_BUFFER_MULTIPLE);
1297 bp->rx_buffer_size =
4df95131 1298 roundup(bp->rx_buffer_size, RX_BUFFER_MULTIPLE);
1b44791a 1299 }
1b44791a 1300 }
4df95131
NF
1301
1302 netdev_dbg(bp->dev, "mtu [%u] rx_buffer_size [%Zu]\n",
1303 bp->dev->mtu, bp->rx_buffer_size);
1b44791a
NF
1304}
1305
4df95131
NF
1306static void gem_free_rx_buffers(struct macb *bp)
1307{
1308 struct sk_buff *skb;
1309 struct macb_dma_desc *desc;
1310 dma_addr_t addr;
1311 int i;
1312
1313 if (!bp->rx_skbuff)
1314 return;
1315
1316 for (i = 0; i < RX_RING_SIZE; i++) {
1317 skb = bp->rx_skbuff[i];
1318
1319 if (skb == NULL)
1320 continue;
1321
1322 desc = &bp->rx_ring[i];
1323 addr = MACB_BF(RX_WADDR, MACB_BFEXT(RX_WADDR, desc->addr));
ccd6d0a9 1324 dma_unmap_single(&bp->pdev->dev, addr, bp->rx_buffer_size,
4df95131
NF
1325 DMA_FROM_DEVICE);
1326 dev_kfree_skb_any(skb);
1327 skb = NULL;
1328 }
1329
1330 kfree(bp->rx_skbuff);
1331 bp->rx_skbuff = NULL;
1332}
1333
1334static void macb_free_rx_buffers(struct macb *bp)
1335{
1336 if (bp->rx_buffers) {
1337 dma_free_coherent(&bp->pdev->dev,
1338 RX_RING_SIZE * bp->rx_buffer_size,
1339 bp->rx_buffers, bp->rx_buffers_dma);
1340 bp->rx_buffers = NULL;
1341 }
1342}
1b44791a 1343
89e5785f
HS
1344static void macb_free_consistent(struct macb *bp)
1345{
02c958dd
CP
1346 struct macb_queue *queue;
1347 unsigned int q;
1348
4df95131 1349 bp->macbgem_ops.mog_free_rx_buffers(bp);
89e5785f
HS
1350 if (bp->rx_ring) {
1351 dma_free_coherent(&bp->pdev->dev, RX_RING_BYTES,
1352 bp->rx_ring, bp->rx_ring_dma);
1353 bp->rx_ring = NULL;
1354 }
02c958dd
CP
1355
1356 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
1357 kfree(queue->tx_skb);
1358 queue->tx_skb = NULL;
1359 if (queue->tx_ring) {
1360 dma_free_coherent(&bp->pdev->dev, TX_RING_BYTES,
1361 queue->tx_ring, queue->tx_ring_dma);
1362 queue->tx_ring = NULL;
1363 }
89e5785f 1364 }
4df95131
NF
1365}
1366
1367static int gem_alloc_rx_buffers(struct macb *bp)
1368{
1369 int size;
1370
1371 size = RX_RING_SIZE * sizeof(struct sk_buff *);
1372 bp->rx_skbuff = kzalloc(size, GFP_KERNEL);
1373 if (!bp->rx_skbuff)
1374 return -ENOMEM;
1375 else
1376 netdev_dbg(bp->dev,
1377 "Allocated %d RX struct sk_buff entries at %p\n",
1378 RX_RING_SIZE, bp->rx_skbuff);
1379 return 0;
1380}
1381
1382static int macb_alloc_rx_buffers(struct macb *bp)
1383{
1384 int size;
1385
1386 size = RX_RING_SIZE * bp->rx_buffer_size;
1387 bp->rx_buffers = dma_alloc_coherent(&bp->pdev->dev, size,
1388 &bp->rx_buffers_dma, GFP_KERNEL);
1389 if (!bp->rx_buffers)
1390 return -ENOMEM;
1391 else
1392 netdev_dbg(bp->dev,
1393 "Allocated RX buffers of %d bytes at %08lx (mapped %p)\n",
1394 size, (unsigned long)bp->rx_buffers_dma, bp->rx_buffers);
1395 return 0;
89e5785f
HS
1396}
1397
1398static int macb_alloc_consistent(struct macb *bp)
1399{
02c958dd
CP
1400 struct macb_queue *queue;
1401 unsigned int q;
89e5785f
HS
1402 int size;
1403
02c958dd
CP
1404 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
1405 size = TX_RING_BYTES;
1406 queue->tx_ring = dma_alloc_coherent(&bp->pdev->dev, size,
1407 &queue->tx_ring_dma,
1408 GFP_KERNEL);
1409 if (!queue->tx_ring)
1410 goto out_err;
1411 netdev_dbg(bp->dev,
1412 "Allocated TX ring for queue %u of %d bytes at %08lx (mapped %p)\n",
1413 q, size, (unsigned long)queue->tx_ring_dma,
1414 queue->tx_ring);
1415
1416 size = TX_RING_SIZE * sizeof(struct macb_tx_skb);
1417 queue->tx_skb = kmalloc(size, GFP_KERNEL);
1418 if (!queue->tx_skb)
1419 goto out_err;
1420 }
89e5785f
HS
1421
1422 size = RX_RING_BYTES;
1423 bp->rx_ring = dma_alloc_coherent(&bp->pdev->dev, size,
1424 &bp->rx_ring_dma, GFP_KERNEL);
1425 if (!bp->rx_ring)
1426 goto out_err;
c220f8cd
JI
1427 netdev_dbg(bp->dev,
1428 "Allocated RX ring of %d bytes at %08lx (mapped %p)\n",
1429 size, (unsigned long)bp->rx_ring_dma, bp->rx_ring);
89e5785f 1430
4df95131 1431 if (bp->macbgem_ops.mog_alloc_rx_buffers(bp))
89e5785f 1432 goto out_err;
89e5785f
HS
1433
1434 return 0;
1435
1436out_err:
1437 macb_free_consistent(bp);
1438 return -ENOMEM;
1439}
1440
4df95131
NF
1441static void gem_init_rings(struct macb *bp)
1442{
02c958dd
CP
1443 struct macb_queue *queue;
1444 unsigned int q;
4df95131
NF
1445 int i;
1446
02c958dd
CP
1447 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
1448 for (i = 0; i < TX_RING_SIZE; i++) {
1449 queue->tx_ring[i].addr = 0;
1450 queue->tx_ring[i].ctrl = MACB_BIT(TX_USED);
1451 }
1452 queue->tx_ring[TX_RING_SIZE - 1].ctrl |= MACB_BIT(TX_WRAP);
1453 queue->tx_head = 0;
1454 queue->tx_tail = 0;
4df95131 1455 }
4df95131 1456
02c958dd
CP
1457 bp->rx_tail = 0;
1458 bp->rx_prepared_head = 0;
4df95131
NF
1459
1460 gem_rx_refill(bp);
1461}
1462
89e5785f
HS
1463static void macb_init_rings(struct macb *bp)
1464{
1465 int i;
1466 dma_addr_t addr;
1467
1468 addr = bp->rx_buffers_dma;
1469 for (i = 0; i < RX_RING_SIZE; i++) {
1470 bp->rx_ring[i].addr = addr;
1471 bp->rx_ring[i].ctrl = 0;
1b44791a 1472 addr += bp->rx_buffer_size;
89e5785f
HS
1473 }
1474 bp->rx_ring[RX_RING_SIZE - 1].addr |= MACB_BIT(RX_WRAP);
1475
1476 for (i = 0; i < TX_RING_SIZE; i++) {
02c958dd
CP
1477 bp->queues[0].tx_ring[i].addr = 0;
1478 bp->queues[0].tx_ring[i].ctrl = MACB_BIT(TX_USED);
89e5785f 1479 }
21d3515c
BS
1480 bp->queues[0].tx_head = 0;
1481 bp->queues[0].tx_tail = 0;
02c958dd 1482 bp->queues[0].tx_ring[TX_RING_SIZE - 1].ctrl |= MACB_BIT(TX_WRAP);
89e5785f 1483
02c958dd 1484 bp->rx_tail = 0;
89e5785f
HS
1485}
1486
1487static void macb_reset_hw(struct macb *bp)
1488{
02c958dd
CP
1489 struct macb_queue *queue;
1490 unsigned int q;
1491
89e5785f
HS
1492 /*
1493 * Disable RX and TX (XXX: Should we halt the transmission
1494 * more gracefully?)
1495 */
1496 macb_writel(bp, NCR, 0);
1497
1498 /* Clear the stats registers (XXX: Update stats first?) */
1499 macb_writel(bp, NCR, MACB_BIT(CLRSTAT));
1500
1501 /* Clear all status flags */
95ebcea6
JE
1502 macb_writel(bp, TSR, -1);
1503 macb_writel(bp, RSR, -1);
89e5785f
HS
1504
1505 /* Disable all interrupts */
02c958dd
CP
1506 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
1507 queue_writel(queue, IDR, -1);
1508 queue_readl(queue, ISR);
1509 }
89e5785f
HS
1510}
1511
70c9f3d4
JI
1512static u32 gem_mdc_clk_div(struct macb *bp)
1513{
1514 u32 config;
1515 unsigned long pclk_hz = clk_get_rate(bp->pclk);
1516
1517 if (pclk_hz <= 20000000)
1518 config = GEM_BF(CLK, GEM_CLK_DIV8);
1519 else if (pclk_hz <= 40000000)
1520 config = GEM_BF(CLK, GEM_CLK_DIV16);
1521 else if (pclk_hz <= 80000000)
1522 config = GEM_BF(CLK, GEM_CLK_DIV32);
1523 else if (pclk_hz <= 120000000)
1524 config = GEM_BF(CLK, GEM_CLK_DIV48);
1525 else if (pclk_hz <= 160000000)
1526 config = GEM_BF(CLK, GEM_CLK_DIV64);
1527 else
1528 config = GEM_BF(CLK, GEM_CLK_DIV96);
1529
1530 return config;
1531}
1532
1533static u32 macb_mdc_clk_div(struct macb *bp)
1534{
1535 u32 config;
1536 unsigned long pclk_hz;
1537
1538 if (macb_is_gem(bp))
1539 return gem_mdc_clk_div(bp);
1540
1541 pclk_hz = clk_get_rate(bp->pclk);
1542 if (pclk_hz <= 20000000)
1543 config = MACB_BF(CLK, MACB_CLK_DIV8);
1544 else if (pclk_hz <= 40000000)
1545 config = MACB_BF(CLK, MACB_CLK_DIV16);
1546 else if (pclk_hz <= 80000000)
1547 config = MACB_BF(CLK, MACB_CLK_DIV32);
1548 else
1549 config = MACB_BF(CLK, MACB_CLK_DIV64);
1550
1551 return config;
1552}
1553
757a03c6
JI
1554/*
1555 * Get the DMA bus width field of the network configuration register that we
1556 * should program. We find the width from decoding the design configuration
1557 * register to find the maximum supported data bus width.
1558 */
1559static u32 macb_dbw(struct macb *bp)
1560{
1561 if (!macb_is_gem(bp))
1562 return 0;
1563
1564 switch (GEM_BFEXT(DBWDEF, gem_readl(bp, DCFG1))) {
1565 case 4:
1566 return GEM_BF(DBW, GEM_DBW128);
1567 case 2:
1568 return GEM_BF(DBW, GEM_DBW64);
1569 case 1:
1570 default:
1571 return GEM_BF(DBW, GEM_DBW32);
1572 }
1573}
1574
0116da4f 1575/*
b3e3bd71
NF
1576 * Configure the receive DMA engine
1577 * - use the correct receive buffer size
e175587f 1578 * - set best burst length for DMA operations
b3e3bd71
NF
1579 * (if not supported by FIFO, it will fallback to default)
1580 * - set both rx/tx packet buffers to full memory size
1581 * These are configurable parameters for GEM.
0116da4f
JI
1582 */
1583static void macb_configure_dma(struct macb *bp)
1584{
1585 u32 dmacfg;
62f6924c 1586 u32 tmp, ncr;
0116da4f
JI
1587
1588 if (macb_is_gem(bp)) {
1589 dmacfg = gem_readl(bp, DMACFG) & ~GEM_BF(RXBS, -1L);
1b44791a 1590 dmacfg |= GEM_BF(RXBS, bp->rx_buffer_size / RX_BUFFER_MULTIPLE);
e175587f
NF
1591 if (bp->dma_burst_length)
1592 dmacfg = GEM_BFINS(FBLDO, bp->dma_burst_length, dmacfg);
b3e3bd71 1593 dmacfg |= GEM_BIT(TXPBMS) | GEM_BF(RXBMS, -1L);
a50dad35 1594 dmacfg &= ~GEM_BIT(ENDIA_PKT);
62f6924c
AC
1595
1596 /* Find the CPU endianness by using the loopback bit of net_ctrl
1597 * register. save it first. When the CPU is in big endian we
1598 * need to program swaped mode for management descriptor access.
1599 */
1600 ncr = macb_readl(bp, NCR);
1601 __raw_writel(MACB_BIT(LLB), bp->regs + MACB_NCR);
1602 tmp = __raw_readl(bp->regs + MACB_NCR);
1603
1604 if (tmp == MACB_BIT(LLB))
1605 dmacfg &= ~GEM_BIT(ENDIA_DESC);
1606 else
1607 dmacfg |= GEM_BIT(ENDIA_DESC); /* CPU in big endian */
1608
1609 /* Restore net_ctrl */
1610 macb_writel(bp, NCR, ncr);
1611
85ff3d87
CP
1612 if (bp->dev->features & NETIF_F_HW_CSUM)
1613 dmacfg |= GEM_BIT(TXCOEN);
1614 else
1615 dmacfg &= ~GEM_BIT(TXCOEN);
e175587f
NF
1616 netdev_dbg(bp->dev, "Cadence configure DMA with 0x%08x\n",
1617 dmacfg);
0116da4f
JI
1618 gem_writel(bp, DMACFG, dmacfg);
1619 }
1620}
1621
89e5785f
HS
1622static void macb_init_hw(struct macb *bp)
1623{
02c958dd
CP
1624 struct macb_queue *queue;
1625 unsigned int q;
1626
89e5785f
HS
1627 u32 config;
1628
1629 macb_reset_hw(bp);
314bccc4 1630 macb_set_hwaddr(bp);
89e5785f 1631
70c9f3d4 1632 config = macb_mdc_clk_div(bp);
29bc2e1e 1633 config |= MACB_BF(RBOF, NET_IP_ALIGN); /* Make eth data aligned */
89e5785f
HS
1634 config |= MACB_BIT(PAE); /* PAuse Enable */
1635 config |= MACB_BIT(DRFCS); /* Discard Rx FCS */
8dd4bd00 1636 config |= MACB_BIT(BIG); /* Receive oversized frames */
89e5785f
HS
1637 if (bp->dev->flags & IFF_PROMISC)
1638 config |= MACB_BIT(CAF); /* Copy All Frames */
924ec53c
CP
1639 else if (macb_is_gem(bp) && bp->dev->features & NETIF_F_RXCSUM)
1640 config |= GEM_BIT(RXCOEN);
89e5785f
HS
1641 if (!(bp->dev->flags & IFF_BROADCAST))
1642 config |= MACB_BIT(NBC); /* No BroadCast */
757a03c6 1643 config |= macb_dbw(bp);
89e5785f 1644 macb_writel(bp, NCFGR, config);
26cdfb49
VD
1645 bp->speed = SPEED_10;
1646 bp->duplex = DUPLEX_HALF;
89e5785f 1647
0116da4f
JI
1648 macb_configure_dma(bp);
1649
89e5785f
HS
1650 /* Initialize TX and RX buffers */
1651 macb_writel(bp, RBQP, bp->rx_ring_dma);
02c958dd
CP
1652 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
1653 queue_writel(queue, TBQP, queue->tx_ring_dma);
1654
1655 /* Enable interrupts */
1656 queue_writel(queue, IER,
1657 MACB_RX_INT_FLAGS |
1658 MACB_TX_INT_FLAGS |
1659 MACB_BIT(HRESP));
1660 }
89e5785f
HS
1661
1662 /* Enable TX and RX */
6c36a707 1663 macb_writel(bp, NCR, MACB_BIT(RE) | MACB_BIT(TE) | MACB_BIT(MPE));
89e5785f
HS
1664}
1665
446ebd01
PV
1666/*
1667 * The hash address register is 64 bits long and takes up two
1668 * locations in the memory map. The least significant bits are stored
1669 * in EMAC_HSL and the most significant bits in EMAC_HSH.
1670 *
1671 * The unicast hash enable and the multicast hash enable bits in the
1672 * network configuration register enable the reception of hash matched
1673 * frames. The destination address is reduced to a 6 bit index into
1674 * the 64 bit hash register using the following hash function. The
1675 * hash function is an exclusive or of every sixth bit of the
1676 * destination address.
1677 *
1678 * hi[5] = da[5] ^ da[11] ^ da[17] ^ da[23] ^ da[29] ^ da[35] ^ da[41] ^ da[47]
1679 * hi[4] = da[4] ^ da[10] ^ da[16] ^ da[22] ^ da[28] ^ da[34] ^ da[40] ^ da[46]
1680 * hi[3] = da[3] ^ da[09] ^ da[15] ^ da[21] ^ da[27] ^ da[33] ^ da[39] ^ da[45]
1681 * hi[2] = da[2] ^ da[08] ^ da[14] ^ da[20] ^ da[26] ^ da[32] ^ da[38] ^ da[44]
1682 * hi[1] = da[1] ^ da[07] ^ da[13] ^ da[19] ^ da[25] ^ da[31] ^ da[37] ^ da[43]
1683 * hi[0] = da[0] ^ da[06] ^ da[12] ^ da[18] ^ da[24] ^ da[30] ^ da[36] ^ da[42]
1684 *
1685 * da[0] represents the least significant bit of the first byte
1686 * received, that is, the multicast/unicast indicator, and da[47]
1687 * represents the most significant bit of the last byte received. If
1688 * the hash index, hi[n], points to a bit that is set in the hash
1689 * register then the frame will be matched according to whether the
1690 * frame is multicast or unicast. A multicast match will be signalled
1691 * if the multicast hash enable bit is set, da[0] is 1 and the hash
1692 * index points to a bit set in the hash register. A unicast match
1693 * will be signalled if the unicast hash enable bit is set, da[0] is 0
1694 * and the hash index points to a bit set in the hash register. To
1695 * receive all multicast frames, the hash register should be set with
1696 * all ones and the multicast hash enable bit should be set in the
1697 * network configuration register.
1698 */
1699
1700static inline int hash_bit_value(int bitnr, __u8 *addr)
1701{
1702 if (addr[bitnr / 8] & (1 << (bitnr % 8)))
1703 return 1;
1704 return 0;
1705}
1706
1707/*
1708 * Return the hash index value for the specified address.
1709 */
1710static int hash_get_index(__u8 *addr)
1711{
1712 int i, j, bitval;
1713 int hash_index = 0;
1714
1715 for (j = 0; j < 6; j++) {
1716 for (i = 0, bitval = 0; i < 8; i++)
2fa45e22 1717 bitval ^= hash_bit_value(i * 6 + j, addr);
446ebd01
PV
1718
1719 hash_index |= (bitval << j);
1720 }
1721
1722 return hash_index;
1723}
1724
1725/*
1726 * Add multicast addresses to the internal multicast-hash table.
1727 */
1728static void macb_sethashtable(struct net_device *dev)
1729{
22bedad3 1730 struct netdev_hw_addr *ha;
446ebd01 1731 unsigned long mc_filter[2];
f9dcbcc9 1732 unsigned int bitnr;
446ebd01
PV
1733 struct macb *bp = netdev_priv(dev);
1734
1735 mc_filter[0] = mc_filter[1] = 0;
1736
22bedad3
JP
1737 netdev_for_each_mc_addr(ha, dev) {
1738 bitnr = hash_get_index(ha->addr);
446ebd01
PV
1739 mc_filter[bitnr >> 5] |= 1 << (bitnr & 31);
1740 }
1741
f75ba50b
JI
1742 macb_or_gem_writel(bp, HRB, mc_filter[0]);
1743 macb_or_gem_writel(bp, HRT, mc_filter[1]);
446ebd01
PV
1744}
1745
1746/*
1747 * Enable/Disable promiscuous and multicast modes.
1748 */
421d9df0 1749static void macb_set_rx_mode(struct net_device *dev)
446ebd01
PV
1750{
1751 unsigned long cfg;
1752 struct macb *bp = netdev_priv(dev);
1753
1754 cfg = macb_readl(bp, NCFGR);
1755
924ec53c 1756 if (dev->flags & IFF_PROMISC) {
446ebd01
PV
1757 /* Enable promiscuous mode */
1758 cfg |= MACB_BIT(CAF);
924ec53c
CP
1759
1760 /* Disable RX checksum offload */
1761 if (macb_is_gem(bp))
1762 cfg &= ~GEM_BIT(RXCOEN);
1763 } else {
1764 /* Disable promiscuous mode */
446ebd01
PV
1765 cfg &= ~MACB_BIT(CAF);
1766
924ec53c
CP
1767 /* Enable RX checksum offload only if requested */
1768 if (macb_is_gem(bp) && dev->features & NETIF_F_RXCSUM)
1769 cfg |= GEM_BIT(RXCOEN);
1770 }
1771
446ebd01
PV
1772 if (dev->flags & IFF_ALLMULTI) {
1773 /* Enable all multicast mode */
f75ba50b
JI
1774 macb_or_gem_writel(bp, HRB, -1);
1775 macb_or_gem_writel(bp, HRT, -1);
446ebd01 1776 cfg |= MACB_BIT(NCFGR_MTI);
4cd24eaf 1777 } else if (!netdev_mc_empty(dev)) {
446ebd01
PV
1778 /* Enable specific multicasts */
1779 macb_sethashtable(dev);
1780 cfg |= MACB_BIT(NCFGR_MTI);
1781 } else if (dev->flags & (~IFF_ALLMULTI)) {
1782 /* Disable all multicast mode */
f75ba50b
JI
1783 macb_or_gem_writel(bp, HRB, 0);
1784 macb_or_gem_writel(bp, HRT, 0);
446ebd01
PV
1785 cfg &= ~MACB_BIT(NCFGR_MTI);
1786 }
1787
1788 macb_writel(bp, NCFGR, cfg);
1789}
1790
89e5785f
HS
1791static int macb_open(struct net_device *dev)
1792{
1793 struct macb *bp = netdev_priv(dev);
4df95131 1794 size_t bufsz = dev->mtu + ETH_HLEN + ETH_FCS_LEN + NET_IP_ALIGN;
89e5785f
HS
1795 int err;
1796
c220f8cd 1797 netdev_dbg(bp->dev, "open\n");
89e5785f 1798
03fc4721
NF
1799 /* carrier starts down */
1800 netif_carrier_off(dev);
1801
6c36a707
R
1802 /* if the phy is not yet register, retry later*/
1803 if (!bp->phy_dev)
1804 return -EAGAIN;
1b44791a
NF
1805
1806 /* RX buffers initialization */
4df95131 1807 macb_init_rx_buffer_size(bp, bufsz);
6c36a707 1808
89e5785f
HS
1809 err = macb_alloc_consistent(bp);
1810 if (err) {
c220f8cd
JI
1811 netdev_err(dev, "Unable to allocate DMA memory (error %d)\n",
1812 err);
89e5785f
HS
1813 return err;
1814 }
1815
bea3348e
SH
1816 napi_enable(&bp->napi);
1817
4df95131 1818 bp->macbgem_ops.mog_init_rings(bp);
89e5785f 1819 macb_init_hw(bp);
89e5785f 1820
6c36a707
R
1821 /* schedule a link state check */
1822 phy_start(bp->phy_dev);
89e5785f 1823
02c958dd 1824 netif_tx_start_all_queues(dev);
89e5785f
HS
1825
1826 return 0;
1827}
1828
1829static int macb_close(struct net_device *dev)
1830{
1831 struct macb *bp = netdev_priv(dev);
1832 unsigned long flags;
1833
02c958dd 1834 netif_tx_stop_all_queues(dev);
bea3348e 1835 napi_disable(&bp->napi);
89e5785f 1836
6c36a707
R
1837 if (bp->phy_dev)
1838 phy_stop(bp->phy_dev);
1839
89e5785f
HS
1840 spin_lock_irqsave(&bp->lock, flags);
1841 macb_reset_hw(bp);
1842 netif_carrier_off(dev);
1843 spin_unlock_irqrestore(&bp->lock, flags);
1844
1845 macb_free_consistent(bp);
1846
1847 return 0;
1848}
1849
a494ed8e
JI
1850static void gem_update_stats(struct macb *bp)
1851{
3ff13f1c 1852 int i;
a494ed8e 1853 u32 *p = &bp->hw_stats.gem.tx_octets_31_0;
a494ed8e 1854
3ff13f1c
XH
1855 for (i = 0; i < GEM_STATS_LEN; ++i, ++p) {
1856 u32 offset = gem_statistics[i].offset;
a50dad35 1857 u64 val = readl_relaxed(bp->regs + offset);
3ff13f1c
XH
1858
1859 bp->ethtool_stats[i] += val;
1860 *p += val;
1861
1862 if (offset == GEM_OCTTXL || offset == GEM_OCTRXL) {
1863 /* Add GEM_OCTTXH, GEM_OCTRXH */
a50dad35 1864 val = readl_relaxed(bp->regs + offset + 4);
2fa45e22 1865 bp->ethtool_stats[i] += ((u64)val) << 32;
3ff13f1c
XH
1866 *(++p) += val;
1867 }
1868 }
a494ed8e
JI
1869}
1870
1871static struct net_device_stats *gem_get_stats(struct macb *bp)
1872{
1873 struct gem_stats *hwstat = &bp->hw_stats.gem;
1874 struct net_device_stats *nstat = &bp->stats;
1875
1876 gem_update_stats(bp);
1877
1878 nstat->rx_errors = (hwstat->rx_frame_check_sequence_errors +
1879 hwstat->rx_alignment_errors +
1880 hwstat->rx_resource_errors +
1881 hwstat->rx_overruns +
1882 hwstat->rx_oversize_frames +
1883 hwstat->rx_jabbers +
1884 hwstat->rx_undersized_frames +
1885 hwstat->rx_length_field_frame_errors);
1886 nstat->tx_errors = (hwstat->tx_late_collisions +
1887 hwstat->tx_excessive_collisions +
1888 hwstat->tx_underrun +
1889 hwstat->tx_carrier_sense_errors);
1890 nstat->multicast = hwstat->rx_multicast_frames;
1891 nstat->collisions = (hwstat->tx_single_collision_frames +
1892 hwstat->tx_multiple_collision_frames +
1893 hwstat->tx_excessive_collisions);
1894 nstat->rx_length_errors = (hwstat->rx_oversize_frames +
1895 hwstat->rx_jabbers +
1896 hwstat->rx_undersized_frames +
1897 hwstat->rx_length_field_frame_errors);
1898 nstat->rx_over_errors = hwstat->rx_resource_errors;
1899 nstat->rx_crc_errors = hwstat->rx_frame_check_sequence_errors;
1900 nstat->rx_frame_errors = hwstat->rx_alignment_errors;
1901 nstat->rx_fifo_errors = hwstat->rx_overruns;
1902 nstat->tx_aborted_errors = hwstat->tx_excessive_collisions;
1903 nstat->tx_carrier_errors = hwstat->tx_carrier_sense_errors;
1904 nstat->tx_fifo_errors = hwstat->tx_underrun;
1905
1906 return nstat;
1907}
1908
3ff13f1c
XH
1909static void gem_get_ethtool_stats(struct net_device *dev,
1910 struct ethtool_stats *stats, u64 *data)
1911{
1912 struct macb *bp;
1913
1914 bp = netdev_priv(dev);
1915 gem_update_stats(bp);
2fa45e22 1916 memcpy(data, &bp->ethtool_stats, sizeof(u64) * GEM_STATS_LEN);
3ff13f1c
XH
1917}
1918
1919static int gem_get_sset_count(struct net_device *dev, int sset)
1920{
1921 switch (sset) {
1922 case ETH_SS_STATS:
1923 return GEM_STATS_LEN;
1924 default:
1925 return -EOPNOTSUPP;
1926 }
1927}
1928
1929static void gem_get_ethtool_strings(struct net_device *dev, u32 sset, u8 *p)
1930{
1931 int i;
1932
1933 switch (sset) {
1934 case ETH_SS_STATS:
1935 for (i = 0; i < GEM_STATS_LEN; i++, p += ETH_GSTRING_LEN)
1936 memcpy(p, gem_statistics[i].stat_string,
1937 ETH_GSTRING_LEN);
1938 break;
1939 }
1940}
1941
421d9df0 1942static struct net_device_stats *macb_get_stats(struct net_device *dev)
89e5785f
HS
1943{
1944 struct macb *bp = netdev_priv(dev);
1945 struct net_device_stats *nstat = &bp->stats;
a494ed8e
JI
1946 struct macb_stats *hwstat = &bp->hw_stats.macb;
1947
1948 if (macb_is_gem(bp))
1949 return gem_get_stats(bp);
89e5785f 1950
6c36a707
R
1951 /* read stats from hardware */
1952 macb_update_stats(bp);
1953
89e5785f
HS
1954 /* Convert HW stats into netdevice stats */
1955 nstat->rx_errors = (hwstat->rx_fcs_errors +
1956 hwstat->rx_align_errors +
1957 hwstat->rx_resource_errors +
1958 hwstat->rx_overruns +
1959 hwstat->rx_oversize_pkts +
1960 hwstat->rx_jabbers +
1961 hwstat->rx_undersize_pkts +
89e5785f
HS
1962 hwstat->rx_length_mismatch);
1963 nstat->tx_errors = (hwstat->tx_late_cols +
1964 hwstat->tx_excessive_cols +
1965 hwstat->tx_underruns +
716723c2
WS
1966 hwstat->tx_carrier_errors +
1967 hwstat->sqe_test_errors);
89e5785f
HS
1968 nstat->collisions = (hwstat->tx_single_cols +
1969 hwstat->tx_multiple_cols +
1970 hwstat->tx_excessive_cols);
1971 nstat->rx_length_errors = (hwstat->rx_oversize_pkts +
1972 hwstat->rx_jabbers +
1973 hwstat->rx_undersize_pkts +
1974 hwstat->rx_length_mismatch);
b19f7f71
AS
1975 nstat->rx_over_errors = hwstat->rx_resource_errors +
1976 hwstat->rx_overruns;
89e5785f
HS
1977 nstat->rx_crc_errors = hwstat->rx_fcs_errors;
1978 nstat->rx_frame_errors = hwstat->rx_align_errors;
1979 nstat->rx_fifo_errors = hwstat->rx_overruns;
1980 /* XXX: What does "missed" mean? */
1981 nstat->tx_aborted_errors = hwstat->tx_excessive_cols;
1982 nstat->tx_carrier_errors = hwstat->tx_carrier_errors;
1983 nstat->tx_fifo_errors = hwstat->tx_underruns;
1984 /* Don't know about heartbeat or window errors... */
1985
1986 return nstat;
1987}
1988
1989static int macb_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1990{
1991 struct macb *bp = netdev_priv(dev);
6c36a707
R
1992 struct phy_device *phydev = bp->phy_dev;
1993
1994 if (!phydev)
1995 return -ENODEV;
89e5785f 1996
6c36a707 1997 return phy_ethtool_gset(phydev, cmd);
89e5785f
HS
1998}
1999
2000static int macb_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2001{
2002 struct macb *bp = netdev_priv(dev);
6c36a707 2003 struct phy_device *phydev = bp->phy_dev;
89e5785f 2004
6c36a707
R
2005 if (!phydev)
2006 return -ENODEV;
2007
2008 return phy_ethtool_sset(phydev, cmd);
89e5785f
HS
2009}
2010
d1d1b53d
NF
2011static int macb_get_regs_len(struct net_device *netdev)
2012{
2013 return MACB_GREGS_NBR * sizeof(u32);
2014}
2015
2016static void macb_get_regs(struct net_device *dev, struct ethtool_regs *regs,
2017 void *p)
2018{
2019 struct macb *bp = netdev_priv(dev);
2020 unsigned int tail, head;
2021 u32 *regs_buff = p;
2022
2023 regs->version = (macb_readl(bp, MID) & ((1 << MACB_REV_SIZE) - 1))
2024 | MACB_GREGS_VERSION;
2025
02c958dd
CP
2026 tail = macb_tx_ring_wrap(bp->queues[0].tx_tail);
2027 head = macb_tx_ring_wrap(bp->queues[0].tx_head);
d1d1b53d
NF
2028
2029 regs_buff[0] = macb_readl(bp, NCR);
2030 regs_buff[1] = macb_or_gem_readl(bp, NCFGR);
2031 regs_buff[2] = macb_readl(bp, NSR);
2032 regs_buff[3] = macb_readl(bp, TSR);
2033 regs_buff[4] = macb_readl(bp, RBQP);
2034 regs_buff[5] = macb_readl(bp, TBQP);
2035 regs_buff[6] = macb_readl(bp, RSR);
2036 regs_buff[7] = macb_readl(bp, IMR);
2037
2038 regs_buff[8] = tail;
2039 regs_buff[9] = head;
02c958dd
CP
2040 regs_buff[10] = macb_tx_dma(&bp->queues[0], tail);
2041 regs_buff[11] = macb_tx_dma(&bp->queues[0], head);
d1d1b53d 2042
7c39994f 2043 regs_buff[12] = macb_or_gem_readl(bp, USRIO);
d1d1b53d 2044 if (macb_is_gem(bp)) {
d1d1b53d
NF
2045 regs_buff[13] = gem_readl(bp, DMACFG);
2046 }
2047}
2048
421d9df0 2049static const struct ethtool_ops macb_ethtool_ops = {
89e5785f
HS
2050 .get_settings = macb_get_settings,
2051 .set_settings = macb_set_settings,
d1d1b53d
NF
2052 .get_regs_len = macb_get_regs_len,
2053 .get_regs = macb_get_regs,
89e5785f 2054 .get_link = ethtool_op_get_link,
17f393e8 2055 .get_ts_info = ethtool_op_get_ts_info,
8cd5a56c 2056};
8cd5a56c 2057
8093b1c3 2058static const struct ethtool_ops gem_ethtool_ops = {
8cd5a56c
XH
2059 .get_settings = macb_get_settings,
2060 .set_settings = macb_set_settings,
2061 .get_regs_len = macb_get_regs_len,
2062 .get_regs = macb_get_regs,
2063 .get_link = ethtool_op_get_link,
2064 .get_ts_info = ethtool_op_get_ts_info,
3ff13f1c
XH
2065 .get_ethtool_stats = gem_get_ethtool_stats,
2066 .get_strings = gem_get_ethtool_strings,
2067 .get_sset_count = gem_get_sset_count,
89e5785f
HS
2068};
2069
421d9df0 2070static int macb_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
89e5785f
HS
2071{
2072 struct macb *bp = netdev_priv(dev);
6c36a707 2073 struct phy_device *phydev = bp->phy_dev;
89e5785f
HS
2074
2075 if (!netif_running(dev))
2076 return -EINVAL;
2077
6c36a707
R
2078 if (!phydev)
2079 return -ENODEV;
89e5785f 2080
28b04113 2081 return phy_mii_ioctl(phydev, rq, cmd);
89e5785f
HS
2082}
2083
85ff3d87
CP
2084static int macb_set_features(struct net_device *netdev,
2085 netdev_features_t features)
2086{
2087 struct macb *bp = netdev_priv(netdev);
2088 netdev_features_t changed = features ^ netdev->features;
2089
2090 /* TX checksum offload */
2091 if ((changed & NETIF_F_HW_CSUM) && macb_is_gem(bp)) {
2092 u32 dmacfg;
2093
2094 dmacfg = gem_readl(bp, DMACFG);
2095 if (features & NETIF_F_HW_CSUM)
2096 dmacfg |= GEM_BIT(TXCOEN);
2097 else
2098 dmacfg &= ~GEM_BIT(TXCOEN);
2099 gem_writel(bp, DMACFG, dmacfg);
2100 }
2101
924ec53c
CP
2102 /* RX checksum offload */
2103 if ((changed & NETIF_F_RXCSUM) && macb_is_gem(bp)) {
2104 u32 netcfg;
2105
2106 netcfg = gem_readl(bp, NCFGR);
2107 if (features & NETIF_F_RXCSUM &&
2108 !(netdev->flags & IFF_PROMISC))
2109 netcfg |= GEM_BIT(RXCOEN);
2110 else
2111 netcfg &= ~GEM_BIT(RXCOEN);
2112 gem_writel(bp, NCFGR, netcfg);
2113 }
2114
85ff3d87
CP
2115 return 0;
2116}
2117
5f1fa992
AB
2118static const struct net_device_ops macb_netdev_ops = {
2119 .ndo_open = macb_open,
2120 .ndo_stop = macb_close,
2121 .ndo_start_xmit = macb_start_xmit,
afc4b13d 2122 .ndo_set_rx_mode = macb_set_rx_mode,
5f1fa992
AB
2123 .ndo_get_stats = macb_get_stats,
2124 .ndo_do_ioctl = macb_ioctl,
2125 .ndo_validate_addr = eth_validate_addr,
2126 .ndo_change_mtu = eth_change_mtu,
2127 .ndo_set_mac_address = eth_mac_addr,
6e8cf5c0
TP
2128#ifdef CONFIG_NET_POLL_CONTROLLER
2129 .ndo_poll_controller = macb_poll_controller,
2130#endif
85ff3d87 2131 .ndo_set_features = macb_set_features,
5f1fa992
AB
2132};
2133
e175587f 2134/*
ad78347f 2135 * Configure peripheral capabilities according to device tree
e175587f
NF
2136 * and integration options used
2137 */
f6970505 2138static void macb_configure_caps(struct macb *bp, const struct macb_config *dt_conf)
e175587f
NF
2139{
2140 u32 dcfg;
e175587f 2141
f6970505
NF
2142 if (dt_conf)
2143 bp->caps = dt_conf->caps;
2144
fa693598 2145 if (macb_is_gem_hw(bp->regs)) {
e175587f
NF
2146 bp->caps |= MACB_CAPS_MACB_IS_GEM;
2147
e175587f
NF
2148 dcfg = gem_readl(bp, DCFG1);
2149 if (GEM_BFEXT(IRQCOR, dcfg) == 0)
2150 bp->caps |= MACB_CAPS_ISR_CLEAR_ON_WRITE;
2151 dcfg = gem_readl(bp, DCFG2);
2152 if ((dcfg & (GEM_BIT(RX_PKT_BUFF) | GEM_BIT(TX_PKT_BUFF))) == 0)
2153 bp->caps |= MACB_CAPS_FIFO_MODE;
2154 }
2155
2156 netdev_dbg(bp->dev, "Cadence caps 0x%08x\n", bp->caps);
2157}
2158
02c958dd
CP
2159static void macb_probe_queues(void __iomem *mem,
2160 unsigned int *queue_mask,
2161 unsigned int *num_queues)
2162{
2163 unsigned int hw_q;
02c958dd
CP
2164
2165 *queue_mask = 0x1;
2166 *num_queues = 1;
2167
da120112
NF
2168 /* is it macb or gem ?
2169 *
2170 * We need to read directly from the hardware here because
2171 * we are early in the probe process and don't have the
2172 * MACB_CAPS_MACB_IS_GEM flag positioned
2173 */
fa693598 2174 if (!macb_is_gem_hw(mem))
02c958dd
CP
2175 return;
2176
2177 /* bit 0 is never set but queue 0 always exists */
a50dad35
AC
2178 *queue_mask = readl_relaxed(mem + GEM_DCFG6) & 0xff;
2179
02c958dd
CP
2180 *queue_mask |= 0x1;
2181
2182 for (hw_q = 1; hw_q < MACB_MAX_QUEUES; ++hw_q)
2183 if (*queue_mask & (1 << hw_q))
2184 (*num_queues)++;
2185}
2186
c69618b3
NF
2187static int macb_clk_init(struct platform_device *pdev, struct clk **pclk,
2188 struct clk **hclk, struct clk **tx_clk)
89e5785f 2189{
421d9df0 2190 int err;
89e5785f 2191
c69618b3
NF
2192 *pclk = devm_clk_get(&pdev->dev, "pclk");
2193 if (IS_ERR(*pclk)) {
2194 err = PTR_ERR(*pclk);
b48e0bab 2195 dev_err(&pdev->dev, "failed to get macb_clk (%u)\n", err);
421d9df0 2196 return err;
0cc8674f 2197 }
461845db 2198
c69618b3
NF
2199 *hclk = devm_clk_get(&pdev->dev, "hclk");
2200 if (IS_ERR(*hclk)) {
2201 err = PTR_ERR(*hclk);
b48e0bab 2202 dev_err(&pdev->dev, "failed to get hclk (%u)\n", err);
421d9df0 2203 return err;
b48e0bab
SB
2204 }
2205
c69618b3
NF
2206 *tx_clk = devm_clk_get(&pdev->dev, "tx_clk");
2207 if (IS_ERR(*tx_clk))
2208 *tx_clk = NULL;
e1824dfe 2209
c69618b3 2210 err = clk_prepare_enable(*pclk);
b48e0bab
SB
2211 if (err) {
2212 dev_err(&pdev->dev, "failed to enable pclk (%u)\n", err);
421d9df0 2213 return err;
b48e0bab
SB
2214 }
2215
c69618b3 2216 err = clk_prepare_enable(*hclk);
b48e0bab
SB
2217 if (err) {
2218 dev_err(&pdev->dev, "failed to enable hclk (%u)\n", err);
421d9df0 2219 goto err_disable_pclk;
89e5785f 2220 }
89e5785f 2221
c69618b3 2222 err = clk_prepare_enable(*tx_clk);
93b31f48
CP
2223 if (err) {
2224 dev_err(&pdev->dev, "failed to enable tx_clk (%u)\n", err);
421d9df0 2225 goto err_disable_hclk;
e1824dfe
SB
2226 }
2227
c69618b3
NF
2228 return 0;
2229
2230err_disable_hclk:
2231 clk_disable_unprepare(*hclk);
2232
2233err_disable_pclk:
2234 clk_disable_unprepare(*pclk);
2235
2236 return err;
2237}
2238
2239static int macb_init(struct platform_device *pdev)
2240{
2241 struct net_device *dev = platform_get_drvdata(pdev);
2242 unsigned int hw_q, q;
2243 struct macb *bp = netdev_priv(dev);
2244 struct macb_queue *queue;
2245 int err;
2246 u32 val;
2247
02c958dd
CP
2248 /* set the queue register mapping once for all: queue0 has a special
2249 * register mapping but we don't want to test the queue index then
2250 * compute the corresponding register offset at run time.
2251 */
cf250de0 2252 for (hw_q = 0, q = 0; hw_q < MACB_MAX_QUEUES; ++hw_q) {
bfa0914a 2253 if (!(bp->queue_mask & (1 << hw_q)))
02c958dd
CP
2254 continue;
2255
cf250de0 2256 queue = &bp->queues[q];
02c958dd
CP
2257 queue->bp = bp;
2258 if (hw_q) {
2259 queue->ISR = GEM_ISR(hw_q - 1);
2260 queue->IER = GEM_IER(hw_q - 1);
2261 queue->IDR = GEM_IDR(hw_q - 1);
2262 queue->IMR = GEM_IMR(hw_q - 1);
2263 queue->TBQP = GEM_TBQP(hw_q - 1);
2264 } else {
2265 /* queue0 uses legacy registers */
2266 queue->ISR = MACB_ISR;
2267 queue->IER = MACB_IER;
2268 queue->IDR = MACB_IDR;
2269 queue->IMR = MACB_IMR;
2270 queue->TBQP = MACB_TBQP;
2271 }
2272
2273 /* get irq: here we use the linux queue index, not the hardware
2274 * queue index. the queue irq definitions in the device tree
2275 * must remove the optional gaps that could exist in the
2276 * hardware queue mask.
2277 */
cf250de0 2278 queue->irq = platform_get_irq(pdev, q);
02c958dd 2279 err = devm_request_irq(&pdev->dev, queue->irq, macb_interrupt,
20488239 2280 IRQF_SHARED, dev->name, queue);
02c958dd
CP
2281 if (err) {
2282 dev_err(&pdev->dev,
2283 "Unable to request IRQ %d (error %d)\n",
2284 queue->irq, err);
c69618b3 2285 return err;
02c958dd
CP
2286 }
2287
2288 INIT_WORK(&queue->tx_error_task, macb_tx_error_task);
cf250de0 2289 q++;
89e5785f
HS
2290 }
2291
5f1fa992 2292 dev->netdev_ops = &macb_netdev_ops;
bea3348e 2293 netif_napi_add(dev, &bp->napi, macb_poll, 64);
89e5785f 2294
4df95131
NF
2295 /* setup appropriated routines according to adapter type */
2296 if (macb_is_gem(bp)) {
a4c35ed3 2297 bp->max_tx_length = GEM_MAX_TX_LEN;
4df95131
NF
2298 bp->macbgem_ops.mog_alloc_rx_buffers = gem_alloc_rx_buffers;
2299 bp->macbgem_ops.mog_free_rx_buffers = gem_free_rx_buffers;
2300 bp->macbgem_ops.mog_init_rings = gem_init_rings;
2301 bp->macbgem_ops.mog_rx = gem_rx;
8cd5a56c 2302 dev->ethtool_ops = &gem_ethtool_ops;
4df95131 2303 } else {
a4c35ed3 2304 bp->max_tx_length = MACB_MAX_TX_LEN;
4df95131
NF
2305 bp->macbgem_ops.mog_alloc_rx_buffers = macb_alloc_rx_buffers;
2306 bp->macbgem_ops.mog_free_rx_buffers = macb_free_rx_buffers;
2307 bp->macbgem_ops.mog_init_rings = macb_init_rings;
2308 bp->macbgem_ops.mog_rx = macb_rx;
8cd5a56c 2309 dev->ethtool_ops = &macb_ethtool_ops;
4df95131
NF
2310 }
2311
a4c35ed3
CP
2312 /* Set features */
2313 dev->hw_features = NETIF_F_SG;
85ff3d87
CP
2314 /* Checksum offload is only available on gem with packet buffer */
2315 if (macb_is_gem(bp) && !(bp->caps & MACB_CAPS_FIFO_MODE))
924ec53c 2316 dev->hw_features |= NETIF_F_HW_CSUM | NETIF_F_RXCSUM;
a4c35ed3
CP
2317 if (bp->caps & MACB_CAPS_SG_DISABLED)
2318 dev->hw_features &= ~NETIF_F_SG;
2319 dev->features = dev->hw_features;
2320
421d9df0
CP
2321 val = 0;
2322 if (bp->phy_interface == PHY_INTERFACE_MODE_RGMII)
2323 val = GEM_BIT(RGMII);
2324 else if (bp->phy_interface == PHY_INTERFACE_MODE_RMII &&
2325 (bp->caps & MACB_CAPS_USRIO_DEFAULT_IS_MII))
2326 val = MACB_BIT(RMII);
2327 else if (!(bp->caps & MACB_CAPS_USRIO_DEFAULT_IS_MII))
2328 val = MACB_BIT(MII);
2329
2330 if (bp->caps & MACB_CAPS_USRIO_HAS_CLKEN)
2331 val |= MACB_BIT(CLKEN);
2332
2333 macb_or_gem_writel(bp, USRIO, val);
2334
89e5785f 2335 /* Set MII management clock divider */
421d9df0
CP
2336 val = macb_mdc_clk_div(bp);
2337 val |= macb_dbw(bp);
2338 macb_writel(bp, NCFGR, val);
2339
2340 return 0;
421d9df0
CP
2341}
2342
2343#if defined(CONFIG_OF)
2344/* 1518 rounded up */
2345#define AT91ETHER_MAX_RBUFF_SZ 0x600
2346/* max number of receive buffers */
2347#define AT91ETHER_MAX_RX_DESCR 9
2348
2349/* Initialize and start the Receiver and Transmit subsystems */
2350static int at91ether_start(struct net_device *dev)
2351{
2352 struct macb *lp = netdev_priv(dev);
2353 dma_addr_t addr;
2354 u32 ctl;
2355 int i;
2356
2357 lp->rx_ring = dma_alloc_coherent(&lp->pdev->dev,
2358 (AT91ETHER_MAX_RX_DESCR *
2359 sizeof(struct macb_dma_desc)),
2360 &lp->rx_ring_dma, GFP_KERNEL);
2361 if (!lp->rx_ring)
2362 return -ENOMEM;
2363
2364 lp->rx_buffers = dma_alloc_coherent(&lp->pdev->dev,
2365 AT91ETHER_MAX_RX_DESCR *
2366 AT91ETHER_MAX_RBUFF_SZ,
2367 &lp->rx_buffers_dma, GFP_KERNEL);
2368 if (!lp->rx_buffers) {
2369 dma_free_coherent(&lp->pdev->dev,
2370 AT91ETHER_MAX_RX_DESCR *
2371 sizeof(struct macb_dma_desc),
2372 lp->rx_ring, lp->rx_ring_dma);
2373 lp->rx_ring = NULL;
2374 return -ENOMEM;
2375 }
2376
2377 addr = lp->rx_buffers_dma;
2378 for (i = 0; i < AT91ETHER_MAX_RX_DESCR; i++) {
2379 lp->rx_ring[i].addr = addr;
2380 lp->rx_ring[i].ctrl = 0;
2381 addr += AT91ETHER_MAX_RBUFF_SZ;
2382 }
2383
2384 /* Set the Wrap bit on the last descriptor */
2385 lp->rx_ring[AT91ETHER_MAX_RX_DESCR - 1].addr |= MACB_BIT(RX_WRAP);
2386
2387 /* Reset buffer index */
2388 lp->rx_tail = 0;
2389
2390 /* Program address of descriptor list in Rx Buffer Queue register */
2391 macb_writel(lp, RBQP, lp->rx_ring_dma);
2392
2393 /* Enable Receive and Transmit */
2394 ctl = macb_readl(lp, NCR);
2395 macb_writel(lp, NCR, ctl | MACB_BIT(RE) | MACB_BIT(TE));
2396
2397 return 0;
2398}
2399
2400/* Open the ethernet interface */
2401static int at91ether_open(struct net_device *dev)
2402{
2403 struct macb *lp = netdev_priv(dev);
2404 u32 ctl;
2405 int ret;
2406
2407 /* Clear internal statistics */
2408 ctl = macb_readl(lp, NCR);
2409 macb_writel(lp, NCR, ctl | MACB_BIT(CLRSTAT));
2410
2411 macb_set_hwaddr(lp);
2412
2413 ret = at91ether_start(dev);
2414 if (ret)
2415 return ret;
2416
2417 /* Enable MAC interrupts */
2418 macb_writel(lp, IER, MACB_BIT(RCOMP) |
2419 MACB_BIT(RXUBR) |
2420 MACB_BIT(ISR_TUND) |
2421 MACB_BIT(ISR_RLE) |
2422 MACB_BIT(TCOMP) |
2423 MACB_BIT(ISR_ROVR) |
2424 MACB_BIT(HRESP));
2425
2426 /* schedule a link state check */
2427 phy_start(lp->phy_dev);
2428
2429 netif_start_queue(dev);
2430
2431 return 0;
2432}
2433
2434/* Close the interface */
2435static int at91ether_close(struct net_device *dev)
2436{
2437 struct macb *lp = netdev_priv(dev);
2438 u32 ctl;
2439
2440 /* Disable Receiver and Transmitter */
2441 ctl = macb_readl(lp, NCR);
2442 macb_writel(lp, NCR, ctl & ~(MACB_BIT(TE) | MACB_BIT(RE)));
2443
2444 /* Disable MAC interrupts */
2445 macb_writel(lp, IDR, MACB_BIT(RCOMP) |
2446 MACB_BIT(RXUBR) |
2447 MACB_BIT(ISR_TUND) |
2448 MACB_BIT(ISR_RLE) |
2449 MACB_BIT(TCOMP) |
2450 MACB_BIT(ISR_ROVR) |
2451 MACB_BIT(HRESP));
2452
2453 netif_stop_queue(dev);
2454
2455 dma_free_coherent(&lp->pdev->dev,
2456 AT91ETHER_MAX_RX_DESCR *
2457 sizeof(struct macb_dma_desc),
2458 lp->rx_ring, lp->rx_ring_dma);
2459 lp->rx_ring = NULL;
2460
2461 dma_free_coherent(&lp->pdev->dev,
2462 AT91ETHER_MAX_RX_DESCR * AT91ETHER_MAX_RBUFF_SZ,
2463 lp->rx_buffers, lp->rx_buffers_dma);
2464 lp->rx_buffers = NULL;
2465
2466 return 0;
2467}
2468
2469/* Transmit packet */
2470static int at91ether_start_xmit(struct sk_buff *skb, struct net_device *dev)
2471{
2472 struct macb *lp = netdev_priv(dev);
2473
2474 if (macb_readl(lp, TSR) & MACB_BIT(RM9200_BNQ)) {
2475 netif_stop_queue(dev);
2476
2477 /* Store packet information (to free when Tx completed) */
2478 lp->skb = skb;
2479 lp->skb_length = skb->len;
2480 lp->skb_physaddr = dma_map_single(NULL, skb->data, skb->len,
2481 DMA_TO_DEVICE);
2482
2483 /* Set address of the data in the Transmit Address register */
2484 macb_writel(lp, TAR, lp->skb_physaddr);
2485 /* Set length of the packet in the Transmit Control register */
2486 macb_writel(lp, TCR, skb->len);
89e5785f 2487
421d9df0
CP
2488 } else {
2489 netdev_err(dev, "%s called, but device is busy!\n", __func__);
2490 return NETDEV_TX_BUSY;
2491 }
2492
2493 return NETDEV_TX_OK;
2494}
2495
2496/* Extract received frame from buffer descriptors and sent to upper layers.
2497 * (Called from interrupt context)
2498 */
2499static void at91ether_rx(struct net_device *dev)
2500{
2501 struct macb *lp = netdev_priv(dev);
2502 unsigned char *p_recv;
2503 struct sk_buff *skb;
2504 unsigned int pktlen;
2505
2506 while (lp->rx_ring[lp->rx_tail].addr & MACB_BIT(RX_USED)) {
2507 p_recv = lp->rx_buffers + lp->rx_tail * AT91ETHER_MAX_RBUFF_SZ;
2508 pktlen = MACB_BF(RX_FRMLEN, lp->rx_ring[lp->rx_tail].ctrl);
2509 skb = netdev_alloc_skb(dev, pktlen + 2);
2510 if (skb) {
2511 skb_reserve(skb, 2);
2512 memcpy(skb_put(skb, pktlen), p_recv, pktlen);
2513
2514 skb->protocol = eth_type_trans(skb, dev);
2515 lp->stats.rx_packets++;
2516 lp->stats.rx_bytes += pktlen;
2517 netif_rx(skb);
2518 } else {
2519 lp->stats.rx_dropped++;
2520 }
2521
2522 if (lp->rx_ring[lp->rx_tail].ctrl & MACB_BIT(RX_MHASH_MATCH))
2523 lp->stats.multicast++;
2524
2525 /* reset ownership bit */
2526 lp->rx_ring[lp->rx_tail].addr &= ~MACB_BIT(RX_USED);
2527
2528 /* wrap after last buffer */
2529 if (lp->rx_tail == AT91ETHER_MAX_RX_DESCR - 1)
2530 lp->rx_tail = 0;
2531 else
2532 lp->rx_tail++;
2533 }
2534}
2535
2536/* MAC interrupt handler */
2537static irqreturn_t at91ether_interrupt(int irq, void *dev_id)
2538{
2539 struct net_device *dev = dev_id;
2540 struct macb *lp = netdev_priv(dev);
2541 u32 intstatus, ctl;
2542
2543 /* MAC Interrupt Status register indicates what interrupts are pending.
2544 * It is automatically cleared once read.
2545 */
2546 intstatus = macb_readl(lp, ISR);
2547
2548 /* Receive complete */
2549 if (intstatus & MACB_BIT(RCOMP))
2550 at91ether_rx(dev);
2551
2552 /* Transmit complete */
2553 if (intstatus & MACB_BIT(TCOMP)) {
2554 /* The TCOM bit is set even if the transmission failed */
2555 if (intstatus & (MACB_BIT(ISR_TUND) | MACB_BIT(ISR_RLE)))
2556 lp->stats.tx_errors++;
2557
2558 if (lp->skb) {
2559 dev_kfree_skb_irq(lp->skb);
2560 lp->skb = NULL;
2561 dma_unmap_single(NULL, lp->skb_physaddr,
2562 lp->skb_length, DMA_TO_DEVICE);
2563 lp->stats.tx_packets++;
2564 lp->stats.tx_bytes += lp->skb_length;
2565 }
2566 netif_wake_queue(dev);
2567 }
2568
2569 /* Work-around for EMAC Errata section 41.3.1 */
2570 if (intstatus & MACB_BIT(RXUBR)) {
2571 ctl = macb_readl(lp, NCR);
2572 macb_writel(lp, NCR, ctl & ~MACB_BIT(RE));
2573 macb_writel(lp, NCR, ctl | MACB_BIT(RE));
2574 }
2575
2576 if (intstatus & MACB_BIT(ISR_ROVR))
2577 netdev_err(dev, "ROVR error\n");
2578
2579 return IRQ_HANDLED;
2580}
2581
2582#ifdef CONFIG_NET_POLL_CONTROLLER
2583static void at91ether_poll_controller(struct net_device *dev)
2584{
2585 unsigned long flags;
2586
2587 local_irq_save(flags);
2588 at91ether_interrupt(dev->irq, dev);
2589 local_irq_restore(flags);
2590}
2591#endif
2592
2593static const struct net_device_ops at91ether_netdev_ops = {
2594 .ndo_open = at91ether_open,
2595 .ndo_stop = at91ether_close,
2596 .ndo_start_xmit = at91ether_start_xmit,
2597 .ndo_get_stats = macb_get_stats,
2598 .ndo_set_rx_mode = macb_set_rx_mode,
2599 .ndo_set_mac_address = eth_mac_addr,
2600 .ndo_do_ioctl = macb_ioctl,
2601 .ndo_validate_addr = eth_validate_addr,
2602 .ndo_change_mtu = eth_change_mtu,
2603#ifdef CONFIG_NET_POLL_CONTROLLER
2604 .ndo_poll_controller = at91ether_poll_controller,
2605#endif
2606};
2607
c69618b3
NF
2608static int at91ether_clk_init(struct platform_device *pdev, struct clk **pclk,
2609 struct clk **hclk, struct clk **tx_clk)
421d9df0 2610{
421d9df0 2611 int err;
421d9df0 2612
c69618b3
NF
2613 *hclk = NULL;
2614 *tx_clk = NULL;
2615
2616 *pclk = devm_clk_get(&pdev->dev, "ether_clk");
2617 if (IS_ERR(*pclk))
2618 return PTR_ERR(*pclk);
421d9df0 2619
c69618b3 2620 err = clk_prepare_enable(*pclk);
421d9df0
CP
2621 if (err) {
2622 dev_err(&pdev->dev, "failed to enable pclk (%u)\n", err);
2623 return err;
2624 }
2625
c69618b3
NF
2626 return 0;
2627}
2628
2629static int at91ether_init(struct platform_device *pdev)
2630{
2631 struct net_device *dev = platform_get_drvdata(pdev);
2632 struct macb *bp = netdev_priv(dev);
2633 int err;
2634 u32 reg;
2635
421d9df0
CP
2636 dev->netdev_ops = &at91ether_netdev_ops;
2637 dev->ethtool_ops = &macb_ethtool_ops;
2638
2639 err = devm_request_irq(&pdev->dev, dev->irq, at91ether_interrupt,
2640 0, dev->name, dev);
2641 if (err)
c69618b3 2642 return err;
421d9df0
CP
2643
2644 macb_writel(bp, NCR, 0);
2645
2646 reg = MACB_BF(CLK, MACB_CLK_DIV32) | MACB_BIT(BIG);
2647 if (bp->phy_interface == PHY_INTERFACE_MODE_RMII)
2648 reg |= MACB_BIT(RM9200_RMII);
2649
2650 macb_writel(bp, NCFGR, reg);
2651
2652 return 0;
421d9df0
CP
2653}
2654
3cef5c5b 2655static const struct macb_config at91sam9260_config = {
421d9df0 2656 .caps = MACB_CAPS_USRIO_HAS_CLKEN | MACB_CAPS_USRIO_DEFAULT_IS_MII,
c69618b3 2657 .clk_init = macb_clk_init,
421d9df0
CP
2658 .init = macb_init,
2659};
2660
3cef5c5b 2661static const struct macb_config pc302gem_config = {
421d9df0
CP
2662 .caps = MACB_CAPS_SG_DISABLED | MACB_CAPS_GIGABIT_MODE_AVAILABLE,
2663 .dma_burst_length = 16,
c69618b3 2664 .clk_init = macb_clk_init,
421d9df0
CP
2665 .init = macb_init,
2666};
2667
3cef5c5b 2668static const struct macb_config sama5d3_config = {
421d9df0
CP
2669 .caps = MACB_CAPS_SG_DISABLED | MACB_CAPS_GIGABIT_MODE_AVAILABLE,
2670 .dma_burst_length = 16,
c69618b3 2671 .clk_init = macb_clk_init,
421d9df0
CP
2672 .init = macb_init,
2673};
2674
3cef5c5b 2675static const struct macb_config sama5d4_config = {
421d9df0
CP
2676 .caps = 0,
2677 .dma_burst_length = 4,
c69618b3 2678 .clk_init = macb_clk_init,
421d9df0
CP
2679 .init = macb_init,
2680};
2681
3cef5c5b 2682static const struct macb_config emac_config = {
c69618b3 2683 .clk_init = at91ether_clk_init,
421d9df0
CP
2684 .init = at91ether_init,
2685};
2686
7b61f9c1
HK
2687static const struct macb_config zynqmp_config = {
2688 .caps = MACB_CAPS_SG_DISABLED | MACB_CAPS_GIGABIT_MODE_AVAILABLE,
2689 .dma_burst_length = 16,
2690 .clk_init = macb_clk_init,
2691 .init = macb_init,
2692};
2693
421d9df0
CP
2694static const struct of_device_id macb_dt_ids[] = {
2695 { .compatible = "cdns,at32ap7000-macb" },
2696 { .compatible = "cdns,at91sam9260-macb", .data = &at91sam9260_config },
2697 { .compatible = "cdns,macb" },
2698 { .compatible = "cdns,pc302-gem", .data = &pc302gem_config },
2699 { .compatible = "cdns,gem", .data = &pc302gem_config },
2700 { .compatible = "atmel,sama5d3-gem", .data = &sama5d3_config },
2701 { .compatible = "atmel,sama5d4-gem", .data = &sama5d4_config },
2702 { .compatible = "cdns,at91rm9200-emac", .data = &emac_config },
2703 { .compatible = "cdns,emac", .data = &emac_config },
7b61f9c1 2704 { .compatible = "cdns,zynqmp-gem", .data = &zynqmp_config},
421d9df0
CP
2705 { /* sentinel */ }
2706};
2707MODULE_DEVICE_TABLE(of, macb_dt_ids);
2708#endif /* CONFIG_OF */
2709
2710static int macb_probe(struct platform_device *pdev)
2711{
c69618b3
NF
2712 int (*clk_init)(struct platform_device *, struct clk **,
2713 struct clk **, struct clk **)
2714 = macb_clk_init;
421d9df0
CP
2715 int (*init)(struct platform_device *) = macb_init;
2716 struct device_node *np = pdev->dev.of_node;
2717 const struct macb_config *macb_config = NULL;
c69618b3 2718 struct clk *pclk, *hclk, *tx_clk;
421d9df0
CP
2719 unsigned int queue_mask, num_queues;
2720 struct macb_platform_data *pdata;
2721 struct phy_device *phydev;
2722 struct net_device *dev;
2723 struct resource *regs;
2724 void __iomem *mem;
2725 const char *mac;
2726 struct macb *bp;
2727 int err;
2728
c69618b3
NF
2729 if (np) {
2730 const struct of_device_id *match;
2731
2732 match = of_match_node(macb_dt_ids, np);
2733 if (match && match->data) {
2734 macb_config = match->data;
2735 clk_init = macb_config->clk_init;
2736 init = macb_config->init;
2737 }
2738 }
2739
2740 err = clk_init(pdev, &pclk, &hclk, &tx_clk);
2741 if (err)
2742 return err;
2743
421d9df0
CP
2744 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2745 mem = devm_ioremap_resource(&pdev->dev, regs);
c69618b3
NF
2746 if (IS_ERR(mem)) {
2747 err = PTR_ERR(mem);
2748 goto err_disable_clocks;
2749 }
421d9df0
CP
2750
2751 macb_probe_queues(mem, &queue_mask, &num_queues);
2752 dev = alloc_etherdev_mq(sizeof(*bp), num_queues);
c69618b3
NF
2753 if (!dev) {
2754 err = -ENOMEM;
2755 goto err_disable_clocks;
2756 }
421d9df0
CP
2757
2758 dev->base_addr = regs->start;
2759
2760 SET_NETDEV_DEV(dev, &pdev->dev);
2761
2762 bp = netdev_priv(dev);
2763 bp->pdev = pdev;
2764 bp->dev = dev;
2765 bp->regs = mem;
2766 bp->num_queues = num_queues;
bfa0914a 2767 bp->queue_mask = queue_mask;
c69618b3
NF
2768 if (macb_config)
2769 bp->dma_burst_length = macb_config->dma_burst_length;
2770 bp->pclk = pclk;
2771 bp->hclk = hclk;
2772 bp->tx_clk = tx_clk;
421d9df0
CP
2773 spin_lock_init(&bp->lock);
2774
ad78347f 2775 /* setup capabilities */
f6970505
NF
2776 macb_configure_caps(bp, macb_config);
2777
421d9df0
CP
2778 platform_set_drvdata(pdev, dev);
2779
2780 dev->irq = platform_get_irq(pdev, 0);
c69618b3
NF
2781 if (dev->irq < 0) {
2782 err = dev->irq;
2783 goto err_disable_clocks;
2784 }
421d9df0
CP
2785
2786 mac = of_get_mac_address(np);
50907043
GR
2787 if (mac)
2788 memcpy(bp->dev->dev_addr, mac, ETH_ALEN);
2789 else
fb97a846
JCPV
2790 macb_get_hwaddr(bp);
2791
421d9df0 2792 err = of_get_phy_mode(np);
fb97a846 2793 if (err < 0) {
c607a0d9 2794 pdata = dev_get_platdata(&pdev->dev);
fb97a846
JCPV
2795 if (pdata && pdata->is_rmii)
2796 bp->phy_interface = PHY_INTERFACE_MODE_RMII;
2797 else
2798 bp->phy_interface = PHY_INTERFACE_MODE_MII;
2799 } else {
2800 bp->phy_interface = err;
2801 }
6c36a707 2802
421d9df0
CP
2803 /* IP specific init */
2804 err = init(pdev);
2805 if (err)
2806 goto err_out_free_netdev;
89e5785f 2807
89e5785f
HS
2808 err = register_netdev(dev);
2809 if (err) {
2810 dev_err(&pdev->dev, "Cannot register net device, aborting.\n");
c69618b3 2811 goto err_out_unregister_netdev;
89e5785f
HS
2812 }
2813
72ca820b
NF
2814 err = macb_mii_init(bp);
2815 if (err)
6c36a707 2816 goto err_out_unregister_netdev;
89e5785f 2817
03fc4721
NF
2818 netif_carrier_off(dev);
2819
5879823f
BS
2820 netdev_info(dev, "Cadence %s rev 0x%08x at 0x%08lx irq %d (%pM)\n",
2821 macb_is_gem(bp) ? "GEM" : "MACB", macb_readl(bp, MID),
2822 dev->base_addr, dev->irq, dev->dev_addr);
89e5785f 2823
6c36a707 2824 phydev = bp->phy_dev;
c220f8cd
JI
2825 netdev_info(dev, "attached PHY driver [%s] (mii_bus:phy_addr=%s, irq=%d)\n",
2826 phydev->drv->name, dev_name(&phydev->dev), phydev->irq);
6c36a707 2827
89e5785f
HS
2828 return 0;
2829
6c36a707
R
2830err_out_unregister_netdev:
2831 unregister_netdev(dev);
421d9df0 2832
cf250de0 2833err_out_free_netdev:
02c958dd 2834 free_netdev(dev);
421d9df0 2835
c69618b3
NF
2836err_disable_clocks:
2837 clk_disable_unprepare(tx_clk);
2838 clk_disable_unprepare(hclk);
2839 clk_disable_unprepare(pclk);
2840
89e5785f
HS
2841 return err;
2842}
2843
9e86d766 2844static int macb_remove(struct platform_device *pdev)
89e5785f
HS
2845{
2846 struct net_device *dev;
2847 struct macb *bp;
2848
2849 dev = platform_get_drvdata(pdev);
2850
2851 if (dev) {
2852 bp = netdev_priv(dev);
84b7901f
AN
2853 if (bp->phy_dev)
2854 phy_disconnect(bp->phy_dev);
298cf9be
LB
2855 mdiobus_unregister(bp->mii_bus);
2856 kfree(bp->mii_bus->irq);
2857 mdiobus_free(bp->mii_bus);
89e5785f 2858 unregister_netdev(dev);
93b31f48 2859 clk_disable_unprepare(bp->tx_clk);
ace58010 2860 clk_disable_unprepare(bp->hclk);
ace58010 2861 clk_disable_unprepare(bp->pclk);
e965be7d 2862 free_netdev(dev);
89e5785f
HS
2863 }
2864
2865 return 0;
2866}
2867
d23823dd 2868static int __maybe_unused macb_suspend(struct device *dev)
c1f598fd 2869{
0dfc3e18 2870 struct platform_device *pdev = to_platform_device(dev);
c1f598fd
HS
2871 struct net_device *netdev = platform_get_drvdata(pdev);
2872 struct macb *bp = netdev_priv(netdev);
2873
03fc4721 2874 netif_carrier_off(netdev);
c1f598fd
HS
2875 netif_device_detach(netdev);
2876
93b31f48 2877 clk_disable_unprepare(bp->tx_clk);
ace58010
ST
2878 clk_disable_unprepare(bp->hclk);
2879 clk_disable_unprepare(bp->pclk);
c1f598fd
HS
2880
2881 return 0;
2882}
2883
d23823dd 2884static int __maybe_unused macb_resume(struct device *dev)
c1f598fd 2885{
0dfc3e18 2886 struct platform_device *pdev = to_platform_device(dev);
c1f598fd
HS
2887 struct net_device *netdev = platform_get_drvdata(pdev);
2888 struct macb *bp = netdev_priv(netdev);
2889
ace58010
ST
2890 clk_prepare_enable(bp->pclk);
2891 clk_prepare_enable(bp->hclk);
93b31f48 2892 clk_prepare_enable(bp->tx_clk);
c1f598fd
HS
2893
2894 netif_device_attach(netdev);
2895
2896 return 0;
2897}
c1f598fd 2898
0dfc3e18
SB
2899static SIMPLE_DEV_PM_OPS(macb_pm_ops, macb_suspend, macb_resume);
2900
89e5785f 2901static struct platform_driver macb_driver = {
9e86d766
NR
2902 .probe = macb_probe,
2903 .remove = macb_remove,
89e5785f
HS
2904 .driver = {
2905 .name = "macb",
fb97a846 2906 .of_match_table = of_match_ptr(macb_dt_ids),
0dfc3e18 2907 .pm = &macb_pm_ops,
89e5785f
HS
2908 },
2909};
2910
9e86d766 2911module_platform_driver(macb_driver);
89e5785f
HS
2912
2913MODULE_LICENSE("GPL");
f75ba50b 2914MODULE_DESCRIPTION("Cadence MACB/GEM Ethernet driver");
e05503ef 2915MODULE_AUTHOR("Haavard Skinnemoen (Atmel)");
72abb461 2916MODULE_ALIAS("platform:macb");
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