Commit | Line | Data |
---|---|---|
89e5785f | 1 | /* |
f75ba50b | 2 | * Cadence MACB/GEM Ethernet Controller driver |
89e5785f HS |
3 | * |
4 | * Copyright (C) 2004-2006 Atmel Corporation | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | */ | |
10 | ||
c220f8cd | 11 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
89e5785f HS |
12 | #include <linux/clk.h> |
13 | #include <linux/module.h> | |
14 | #include <linux/moduleparam.h> | |
15 | #include <linux/kernel.h> | |
16 | #include <linux/types.h> | |
909a8583 | 17 | #include <linux/circ_buf.h> |
89e5785f HS |
18 | #include <linux/slab.h> |
19 | #include <linux/init.h> | |
60fe716f | 20 | #include <linux/io.h> |
2dbfdbb9 | 21 | #include <linux/gpio.h> |
270c499f | 22 | #include <linux/gpio/consumer.h> |
a6b7a407 | 23 | #include <linux/interrupt.h> |
89e5785f HS |
24 | #include <linux/netdevice.h> |
25 | #include <linux/etherdevice.h> | |
89e5785f | 26 | #include <linux/dma-mapping.h> |
84e0cdb0 | 27 | #include <linux/platform_data/macb.h> |
89e5785f | 28 | #include <linux/platform_device.h> |
6c36a707 | 29 | #include <linux/phy.h> |
b17471f5 | 30 | #include <linux/of.h> |
fb97a846 | 31 | #include <linux/of_device.h> |
270c499f | 32 | #include <linux/of_gpio.h> |
148cbb53 | 33 | #include <linux/of_mdio.h> |
fb97a846 | 34 | #include <linux/of_net.h> |
89e5785f | 35 | |
89e5785f HS |
36 | #include "macb.h" |
37 | ||
1b44791a | 38 | #define MACB_RX_BUFFER_SIZE 128 |
1b44791a | 39 | #define RX_BUFFER_MULTIPLE 64 /* bytes */ |
55054a16 HS |
40 | #define RX_RING_SIZE 512 /* must be power of 2 */ |
41 | #define RX_RING_BYTES (sizeof(struct macb_dma_desc) * RX_RING_SIZE) | |
89e5785f | 42 | |
55054a16 HS |
43 | #define TX_RING_SIZE 128 /* must be power of 2 */ |
44 | #define TX_RING_BYTES (sizeof(struct macb_dma_desc) * TX_RING_SIZE) | |
89e5785f | 45 | |
909a8583 NF |
46 | /* level of occupied TX descriptors under which we wake up TX process */ |
47 | #define MACB_TX_WAKEUP_THRESH (3 * TX_RING_SIZE / 4) | |
89e5785f HS |
48 | |
49 | #define MACB_RX_INT_FLAGS (MACB_BIT(RCOMP) | MACB_BIT(RXUBR) \ | |
50 | | MACB_BIT(ISR_ROVR)) | |
e86cd53a NF |
51 | #define MACB_TX_ERR_FLAGS (MACB_BIT(ISR_TUND) \ |
52 | | MACB_BIT(ISR_RLE) \ | |
53 | | MACB_BIT(TXERR)) | |
54 | #define MACB_TX_INT_FLAGS (MACB_TX_ERR_FLAGS | MACB_BIT(TCOMP)) | |
55 | ||
a4c35ed3 CP |
56 | #define MACB_MAX_TX_LEN ((unsigned int)((1 << MACB_TX_FRMLEN_SIZE) - 1)) |
57 | #define GEM_MAX_TX_LEN ((unsigned int)((1 << GEM_TX_FRMLEN_SIZE) - 1)) | |
58 | ||
a5898ea0 HK |
59 | #define GEM_MTU_MIN_SIZE 68 |
60 | ||
3e2a5e15 SP |
61 | #define MACB_WOL_HAS_MAGIC_PACKET (0x1 << 0) |
62 | #define MACB_WOL_ENABLED (0x1 << 1) | |
63 | ||
64ec42fe | 64 | /* Graceful stop timeouts in us. We should allow up to |
e86cd53a NF |
65 | * 1 frame time (10 Mbits/s, full-duplex, ignoring collisions) |
66 | */ | |
67 | #define MACB_HALT_TIMEOUT 1230 | |
89e5785f | 68 | |
55054a16 HS |
69 | /* Ring buffer accessors */ |
70 | static unsigned int macb_tx_ring_wrap(unsigned int index) | |
71 | { | |
72 | return index & (TX_RING_SIZE - 1); | |
73 | } | |
74 | ||
02c958dd CP |
75 | static struct macb_dma_desc *macb_tx_desc(struct macb_queue *queue, |
76 | unsigned int index) | |
55054a16 | 77 | { |
02c958dd | 78 | return &queue->tx_ring[macb_tx_ring_wrap(index)]; |
55054a16 HS |
79 | } |
80 | ||
02c958dd CP |
81 | static struct macb_tx_skb *macb_tx_skb(struct macb_queue *queue, |
82 | unsigned int index) | |
55054a16 | 83 | { |
02c958dd | 84 | return &queue->tx_skb[macb_tx_ring_wrap(index)]; |
55054a16 HS |
85 | } |
86 | ||
02c958dd | 87 | static dma_addr_t macb_tx_dma(struct macb_queue *queue, unsigned int index) |
55054a16 HS |
88 | { |
89 | dma_addr_t offset; | |
90 | ||
91 | offset = macb_tx_ring_wrap(index) * sizeof(struct macb_dma_desc); | |
92 | ||
02c958dd | 93 | return queue->tx_ring_dma + offset; |
55054a16 HS |
94 | } |
95 | ||
96 | static unsigned int macb_rx_ring_wrap(unsigned int index) | |
97 | { | |
98 | return index & (RX_RING_SIZE - 1); | |
99 | } | |
100 | ||
101 | static struct macb_dma_desc *macb_rx_desc(struct macb *bp, unsigned int index) | |
102 | { | |
103 | return &bp->rx_ring[macb_rx_ring_wrap(index)]; | |
104 | } | |
105 | ||
106 | static void *macb_rx_buffer(struct macb *bp, unsigned int index) | |
107 | { | |
1b44791a | 108 | return bp->rx_buffers + bp->rx_buffer_size * macb_rx_ring_wrap(index); |
55054a16 HS |
109 | } |
110 | ||
f2ce8a9e AS |
111 | /* I/O accessors */ |
112 | static u32 hw_readl_native(struct macb *bp, int offset) | |
113 | { | |
114 | return __raw_readl(bp->regs + offset); | |
115 | } | |
116 | ||
117 | static void hw_writel_native(struct macb *bp, int offset, u32 value) | |
118 | { | |
119 | __raw_writel(value, bp->regs + offset); | |
120 | } | |
121 | ||
122 | static u32 hw_readl(struct macb *bp, int offset) | |
123 | { | |
124 | return readl_relaxed(bp->regs + offset); | |
125 | } | |
126 | ||
127 | static void hw_writel(struct macb *bp, int offset, u32 value) | |
128 | { | |
129 | writel_relaxed(value, bp->regs + offset); | |
130 | } | |
131 | ||
64ec42fe | 132 | /* Find the CPU endianness by using the loopback bit of NCR register. When the |
88023beb | 133 | * CPU is in big endian we need to program swapped mode for management |
f2ce8a9e AS |
134 | * descriptor access. |
135 | */ | |
136 | static bool hw_is_native_io(void __iomem *addr) | |
137 | { | |
138 | u32 value = MACB_BIT(LLB); | |
139 | ||
140 | __raw_writel(value, addr + MACB_NCR); | |
141 | value = __raw_readl(addr + MACB_NCR); | |
142 | ||
143 | /* Write 0 back to disable everything */ | |
144 | __raw_writel(0, addr + MACB_NCR); | |
145 | ||
146 | return value == MACB_BIT(LLB); | |
147 | } | |
148 | ||
149 | static bool hw_is_gem(void __iomem *addr, bool native_io) | |
150 | { | |
151 | u32 id; | |
152 | ||
153 | if (native_io) | |
154 | id = __raw_readl(addr + MACB_MID); | |
155 | else | |
156 | id = readl_relaxed(addr + MACB_MID); | |
157 | ||
158 | return MACB_BFEXT(IDNUM, id) >= 0x2; | |
159 | } | |
160 | ||
421d9df0 | 161 | static void macb_set_hwaddr(struct macb *bp) |
89e5785f HS |
162 | { |
163 | u32 bottom; | |
164 | u16 top; | |
165 | ||
166 | bottom = cpu_to_le32(*((u32 *)bp->dev->dev_addr)); | |
f75ba50b | 167 | macb_or_gem_writel(bp, SA1B, bottom); |
89e5785f | 168 | top = cpu_to_le16(*((u16 *)(bp->dev->dev_addr + 4))); |
f75ba50b | 169 | macb_or_gem_writel(bp, SA1T, top); |
3629a6ce JE |
170 | |
171 | /* Clear unused address register sets */ | |
172 | macb_or_gem_writel(bp, SA2B, 0); | |
173 | macb_or_gem_writel(bp, SA2T, 0); | |
174 | macb_or_gem_writel(bp, SA3B, 0); | |
175 | macb_or_gem_writel(bp, SA3T, 0); | |
176 | macb_or_gem_writel(bp, SA4B, 0); | |
177 | macb_or_gem_writel(bp, SA4T, 0); | |
89e5785f HS |
178 | } |
179 | ||
421d9df0 | 180 | static void macb_get_hwaddr(struct macb *bp) |
89e5785f | 181 | { |
d25e78aa | 182 | struct macb_platform_data *pdata; |
89e5785f HS |
183 | u32 bottom; |
184 | u16 top; | |
185 | u8 addr[6]; | |
17b8bb3e JE |
186 | int i; |
187 | ||
c607a0d9 | 188 | pdata = dev_get_platdata(&bp->pdev->dev); |
d25e78aa | 189 | |
aa50b552 | 190 | /* Check all 4 address register for valid address */ |
17b8bb3e JE |
191 | for (i = 0; i < 4; i++) { |
192 | bottom = macb_or_gem_readl(bp, SA1B + i * 8); | |
193 | top = macb_or_gem_readl(bp, SA1T + i * 8); | |
194 | ||
d25e78aa JE |
195 | if (pdata && pdata->rev_eth_addr) { |
196 | addr[5] = bottom & 0xff; | |
197 | addr[4] = (bottom >> 8) & 0xff; | |
198 | addr[3] = (bottom >> 16) & 0xff; | |
199 | addr[2] = (bottom >> 24) & 0xff; | |
200 | addr[1] = top & 0xff; | |
201 | addr[0] = (top & 0xff00) >> 8; | |
202 | } else { | |
203 | addr[0] = bottom & 0xff; | |
204 | addr[1] = (bottom >> 8) & 0xff; | |
205 | addr[2] = (bottom >> 16) & 0xff; | |
206 | addr[3] = (bottom >> 24) & 0xff; | |
207 | addr[4] = top & 0xff; | |
208 | addr[5] = (top >> 8) & 0xff; | |
209 | } | |
17b8bb3e JE |
210 | |
211 | if (is_valid_ether_addr(addr)) { | |
212 | memcpy(bp->dev->dev_addr, addr, sizeof(addr)); | |
213 | return; | |
214 | } | |
d1d5741d | 215 | } |
17b8bb3e | 216 | |
a35919e1 | 217 | dev_info(&bp->pdev->dev, "invalid hw address, using random\n"); |
17b8bb3e | 218 | eth_hw_addr_random(bp->dev); |
89e5785f HS |
219 | } |
220 | ||
6c36a707 | 221 | static int macb_mdio_read(struct mii_bus *bus, int mii_id, int regnum) |
89e5785f | 222 | { |
6c36a707 | 223 | struct macb *bp = bus->priv; |
89e5785f HS |
224 | int value; |
225 | ||
89e5785f HS |
226 | macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_SOF) |
227 | | MACB_BF(RW, MACB_MAN_READ) | |
6c36a707 R |
228 | | MACB_BF(PHYA, mii_id) |
229 | | MACB_BF(REGA, regnum) | |
89e5785f HS |
230 | | MACB_BF(CODE, MACB_MAN_CODE))); |
231 | ||
6c36a707 R |
232 | /* wait for end of transfer */ |
233 | while (!MACB_BFEXT(IDLE, macb_readl(bp, NSR))) | |
234 | cpu_relax(); | |
89e5785f HS |
235 | |
236 | value = MACB_BFEXT(DATA, macb_readl(bp, MAN)); | |
89e5785f HS |
237 | |
238 | return value; | |
239 | } | |
240 | ||
6c36a707 R |
241 | static int macb_mdio_write(struct mii_bus *bus, int mii_id, int regnum, |
242 | u16 value) | |
89e5785f | 243 | { |
6c36a707 | 244 | struct macb *bp = bus->priv; |
89e5785f HS |
245 | |
246 | macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_SOF) | |
247 | | MACB_BF(RW, MACB_MAN_WRITE) | |
6c36a707 R |
248 | | MACB_BF(PHYA, mii_id) |
249 | | MACB_BF(REGA, regnum) | |
89e5785f | 250 | | MACB_BF(CODE, MACB_MAN_CODE) |
6c36a707 | 251 | | MACB_BF(DATA, value))); |
89e5785f | 252 | |
6c36a707 R |
253 | /* wait for end of transfer */ |
254 | while (!MACB_BFEXT(IDLE, macb_readl(bp, NSR))) | |
255 | cpu_relax(); | |
256 | ||
257 | return 0; | |
258 | } | |
89e5785f | 259 | |
e1824dfe SB |
260 | /** |
261 | * macb_set_tx_clk() - Set a clock to a new frequency | |
262 | * @clk Pointer to the clock to change | |
263 | * @rate New frequency in Hz | |
264 | * @dev Pointer to the struct net_device | |
265 | */ | |
266 | static void macb_set_tx_clk(struct clk *clk, int speed, struct net_device *dev) | |
267 | { | |
268 | long ferr, rate, rate_rounded; | |
269 | ||
93b31f48 CP |
270 | if (!clk) |
271 | return; | |
272 | ||
e1824dfe SB |
273 | switch (speed) { |
274 | case SPEED_10: | |
275 | rate = 2500000; | |
276 | break; | |
277 | case SPEED_100: | |
278 | rate = 25000000; | |
279 | break; | |
280 | case SPEED_1000: | |
281 | rate = 125000000; | |
282 | break; | |
283 | default: | |
9319e47c | 284 | return; |
e1824dfe SB |
285 | } |
286 | ||
287 | rate_rounded = clk_round_rate(clk, rate); | |
288 | if (rate_rounded < 0) | |
289 | return; | |
290 | ||
291 | /* RGMII allows 50 ppm frequency error. Test and warn if this limit | |
292 | * is not satisfied. | |
293 | */ | |
294 | ferr = abs(rate_rounded - rate); | |
295 | ferr = DIV_ROUND_UP(ferr, rate / 100000); | |
296 | if (ferr > 5) | |
297 | netdev_warn(dev, "unable to generate target frequency: %ld Hz\n", | |
aa50b552 | 298 | rate); |
e1824dfe SB |
299 | |
300 | if (clk_set_rate(clk, rate_rounded)) | |
301 | netdev_err(dev, "adjusting tx_clk failed.\n"); | |
302 | } | |
303 | ||
6c36a707 | 304 | static void macb_handle_link_change(struct net_device *dev) |
89e5785f | 305 | { |
6c36a707 | 306 | struct macb *bp = netdev_priv(dev); |
0a91281e | 307 | struct phy_device *phydev = dev->phydev; |
6c36a707 | 308 | unsigned long flags; |
6c36a707 | 309 | int status_change = 0; |
89e5785f | 310 | |
6c36a707 R |
311 | spin_lock_irqsave(&bp->lock, flags); |
312 | ||
313 | if (phydev->link) { | |
314 | if ((bp->speed != phydev->speed) || | |
315 | (bp->duplex != phydev->duplex)) { | |
316 | u32 reg; | |
317 | ||
318 | reg = macb_readl(bp, NCFGR); | |
319 | reg &= ~(MACB_BIT(SPD) | MACB_BIT(FD)); | |
140b7552 PV |
320 | if (macb_is_gem(bp)) |
321 | reg &= ~GEM_BIT(GBE); | |
6c36a707 R |
322 | |
323 | if (phydev->duplex) | |
324 | reg |= MACB_BIT(FD); | |
179956f4 | 325 | if (phydev->speed == SPEED_100) |
6c36a707 | 326 | reg |= MACB_BIT(SPD); |
e175587f NF |
327 | if (phydev->speed == SPEED_1000 && |
328 | bp->caps & MACB_CAPS_GIGABIT_MODE_AVAILABLE) | |
140b7552 | 329 | reg |= GEM_BIT(GBE); |
6c36a707 | 330 | |
140b7552 | 331 | macb_or_gem_writel(bp, NCFGR, reg); |
6c36a707 R |
332 | |
333 | bp->speed = phydev->speed; | |
334 | bp->duplex = phydev->duplex; | |
335 | status_change = 1; | |
336 | } | |
89e5785f HS |
337 | } |
338 | ||
6c36a707 | 339 | if (phydev->link != bp->link) { |
c8f15686 | 340 | if (!phydev->link) { |
6c36a707 R |
341 | bp->speed = 0; |
342 | bp->duplex = -1; | |
343 | } | |
344 | bp->link = phydev->link; | |
89e5785f | 345 | |
6c36a707 R |
346 | status_change = 1; |
347 | } | |
89e5785f | 348 | |
6c36a707 R |
349 | spin_unlock_irqrestore(&bp->lock, flags); |
350 | ||
351 | if (status_change) { | |
03fc4721 | 352 | if (phydev->link) { |
2c29b235 JA |
353 | /* Update the TX clock rate if and only if the link is |
354 | * up and there has been a link change. | |
355 | */ | |
356 | macb_set_tx_clk(bp->tx_clk, phydev->speed, dev); | |
357 | ||
03fc4721 | 358 | netif_carrier_on(dev); |
c220f8cd JI |
359 | netdev_info(dev, "link up (%d/%s)\n", |
360 | phydev->speed, | |
361 | phydev->duplex == DUPLEX_FULL ? | |
362 | "Full" : "Half"); | |
03fc4721 NF |
363 | } else { |
364 | netif_carrier_off(dev); | |
c220f8cd | 365 | netdev_info(dev, "link down\n"); |
03fc4721 | 366 | } |
6c36a707 | 367 | } |
89e5785f HS |
368 | } |
369 | ||
6c36a707 R |
370 | /* based on au1000_eth. c*/ |
371 | static int macb_mii_probe(struct net_device *dev) | |
89e5785f | 372 | { |
6c36a707 | 373 | struct macb *bp = netdev_priv(dev); |
2dbfdbb9 | 374 | struct macb_platform_data *pdata; |
7455a76f | 375 | struct phy_device *phydev; |
2dbfdbb9 | 376 | int phy_irq; |
7455a76f | 377 | int ret; |
6c36a707 | 378 | |
7455a76f | 379 | phydev = phy_find_first(bp->mii_bus); |
6c36a707 | 380 | if (!phydev) { |
c220f8cd | 381 | netdev_err(dev, "no PHY found\n"); |
7daa78e3 | 382 | return -ENXIO; |
6c36a707 R |
383 | } |
384 | ||
2dbfdbb9 JE |
385 | pdata = dev_get_platdata(&bp->pdev->dev); |
386 | if (pdata && gpio_is_valid(pdata->phy_irq_pin)) { | |
64ec42fe MF |
387 | ret = devm_gpio_request(&bp->pdev->dev, pdata->phy_irq_pin, |
388 | "phy int"); | |
2dbfdbb9 JE |
389 | if (!ret) { |
390 | phy_irq = gpio_to_irq(pdata->phy_irq_pin); | |
391 | phydev->irq = (phy_irq < 0) ? PHY_POLL : phy_irq; | |
392 | } | |
393 | } | |
6c36a707 R |
394 | |
395 | /* attach the mac to the phy */ | |
f9a8f83b | 396 | ret = phy_connect_direct(dev, phydev, &macb_handle_link_change, |
fb97a846 | 397 | bp->phy_interface); |
7455a76f | 398 | if (ret) { |
c220f8cd | 399 | netdev_err(dev, "Could not attach to PHY\n"); |
7455a76f | 400 | return ret; |
6c36a707 R |
401 | } |
402 | ||
403 | /* mask with MAC supported features */ | |
e175587f | 404 | if (macb_is_gem(bp) && bp->caps & MACB_CAPS_GIGABIT_MODE_AVAILABLE) |
140b7552 PV |
405 | phydev->supported &= PHY_GBIT_FEATURES; |
406 | else | |
407 | phydev->supported &= PHY_BASIC_FEATURES; | |
6c36a707 | 408 | |
222ca8e0 NS |
409 | if (bp->caps & MACB_CAPS_NO_GIGABIT_HALF) |
410 | phydev->supported &= ~SUPPORTED_1000baseT_Half; | |
411 | ||
6c36a707 R |
412 | phydev->advertising = phydev->supported; |
413 | ||
414 | bp->link = 0; | |
415 | bp->speed = 0; | |
416 | bp->duplex = -1; | |
6c36a707 R |
417 | |
418 | return 0; | |
89e5785f HS |
419 | } |
420 | ||
421d9df0 | 421 | static int macb_mii_init(struct macb *bp) |
89e5785f | 422 | { |
84e0cdb0 | 423 | struct macb_platform_data *pdata; |
148cbb53 | 424 | struct device_node *np; |
6c36a707 | 425 | int err = -ENXIO, i; |
89e5785f | 426 | |
3dbda77e | 427 | /* Enable management port */ |
6c36a707 | 428 | macb_writel(bp, NCR, MACB_BIT(MPE)); |
89e5785f | 429 | |
298cf9be | 430 | bp->mii_bus = mdiobus_alloc(); |
aa50b552 | 431 | if (!bp->mii_bus) { |
298cf9be LB |
432 | err = -ENOMEM; |
433 | goto err_out; | |
434 | } | |
435 | ||
436 | bp->mii_bus->name = "MACB_mii_bus"; | |
437 | bp->mii_bus->read = &macb_mdio_read; | |
438 | bp->mii_bus->write = &macb_mdio_write; | |
98d5e57e | 439 | snprintf(bp->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x", |
aa50b552 | 440 | bp->pdev->name, bp->pdev->id); |
298cf9be | 441 | bp->mii_bus->priv = bp; |
cf669660 | 442 | bp->mii_bus->parent = &bp->pdev->dev; |
c607a0d9 | 443 | pdata = dev_get_platdata(&bp->pdev->dev); |
89e5785f | 444 | |
91523947 | 445 | dev_set_drvdata(&bp->dev->dev, bp->mii_bus); |
89e5785f | 446 | |
148cbb53 BB |
447 | np = bp->pdev->dev.of_node; |
448 | if (np) { | |
449 | /* try dt phy registration */ | |
450 | err = of_mdiobus_register(bp->mii_bus, np); | |
451 | ||
452 | /* fallback to standard phy registration if no phy were | |
64ec42fe MF |
453 | * found during dt phy registration |
454 | */ | |
148cbb53 BB |
455 | if (!err && !phy_find_first(bp->mii_bus)) { |
456 | for (i = 0; i < PHY_MAX_ADDR; i++) { | |
457 | struct phy_device *phydev; | |
458 | ||
459 | phydev = mdiobus_scan(bp->mii_bus, i); | |
ce24c2b8 SS |
460 | if (IS_ERR(phydev) && |
461 | PTR_ERR(phydev) != -ENODEV) { | |
148cbb53 BB |
462 | err = PTR_ERR(phydev); |
463 | break; | |
464 | } | |
465 | } | |
466 | ||
467 | if (err) | |
468 | goto err_out_unregister_bus; | |
469 | } | |
470 | } else { | |
148cbb53 BB |
471 | if (pdata) |
472 | bp->mii_bus->phy_mask = pdata->phy_mask; | |
473 | ||
474 | err = mdiobus_register(bp->mii_bus); | |
475 | } | |
476 | ||
477 | if (err) | |
e7f4dc35 | 478 | goto err_out_free_mdiobus; |
89e5785f | 479 | |
7daa78e3 BB |
480 | err = macb_mii_probe(bp->dev); |
481 | if (err) | |
6c36a707 | 482 | goto err_out_unregister_bus; |
89e5785f | 483 | |
6c36a707 | 484 | return 0; |
89e5785f | 485 | |
6c36a707 | 486 | err_out_unregister_bus: |
298cf9be | 487 | mdiobus_unregister(bp->mii_bus); |
298cf9be LB |
488 | err_out_free_mdiobus: |
489 | mdiobus_free(bp->mii_bus); | |
6c36a707 R |
490 | err_out: |
491 | return err; | |
89e5785f HS |
492 | } |
493 | ||
494 | static void macb_update_stats(struct macb *bp) | |
495 | { | |
a494ed8e JI |
496 | u32 *p = &bp->hw_stats.macb.rx_pause_frames; |
497 | u32 *end = &bp->hw_stats.macb.tx_pause_frames + 1; | |
f2ce8a9e | 498 | int offset = MACB_PFR; |
89e5785f HS |
499 | |
500 | WARN_ON((unsigned long)(end - p - 1) != (MACB_TPF - MACB_PFR) / 4); | |
501 | ||
96ec6310 | 502 | for (; p < end; p++, offset += 4) |
7a6e0706 | 503 | *p += bp->macb_reg_readl(bp, offset); |
89e5785f HS |
504 | } |
505 | ||
e86cd53a | 506 | static int macb_halt_tx(struct macb *bp) |
89e5785f | 507 | { |
e86cd53a NF |
508 | unsigned long halt_time, timeout; |
509 | u32 status; | |
89e5785f | 510 | |
e86cd53a | 511 | macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(THALT)); |
89e5785f | 512 | |
e86cd53a NF |
513 | timeout = jiffies + usecs_to_jiffies(MACB_HALT_TIMEOUT); |
514 | do { | |
515 | halt_time = jiffies; | |
516 | status = macb_readl(bp, TSR); | |
517 | if (!(status & MACB_BIT(TGO))) | |
518 | return 0; | |
89e5785f | 519 | |
e86cd53a NF |
520 | usleep_range(10, 250); |
521 | } while (time_before(halt_time, timeout)); | |
bdcba151 | 522 | |
e86cd53a NF |
523 | return -ETIMEDOUT; |
524 | } | |
39eddb4c | 525 | |
a4c35ed3 CP |
526 | static void macb_tx_unmap(struct macb *bp, struct macb_tx_skb *tx_skb) |
527 | { | |
528 | if (tx_skb->mapping) { | |
529 | if (tx_skb->mapped_as_page) | |
530 | dma_unmap_page(&bp->pdev->dev, tx_skb->mapping, | |
531 | tx_skb->size, DMA_TO_DEVICE); | |
532 | else | |
533 | dma_unmap_single(&bp->pdev->dev, tx_skb->mapping, | |
534 | tx_skb->size, DMA_TO_DEVICE); | |
535 | tx_skb->mapping = 0; | |
536 | } | |
537 | ||
538 | if (tx_skb->skb) { | |
539 | dev_kfree_skb_any(tx_skb->skb); | |
540 | tx_skb->skb = NULL; | |
541 | } | |
542 | } | |
543 | ||
fff8019a HK |
544 | static inline void macb_set_addr(struct macb_dma_desc *desc, dma_addr_t addr) |
545 | { | |
546 | desc->addr = (u32)addr; | |
547 | #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT | |
548 | desc->addrh = (u32)(addr >> 32); | |
549 | #endif | |
550 | } | |
551 | ||
e86cd53a NF |
552 | static void macb_tx_error_task(struct work_struct *work) |
553 | { | |
02c958dd CP |
554 | struct macb_queue *queue = container_of(work, struct macb_queue, |
555 | tx_error_task); | |
556 | struct macb *bp = queue->bp; | |
e86cd53a | 557 | struct macb_tx_skb *tx_skb; |
02c958dd | 558 | struct macb_dma_desc *desc; |
e86cd53a NF |
559 | struct sk_buff *skb; |
560 | unsigned int tail; | |
02c958dd CP |
561 | unsigned long flags; |
562 | ||
563 | netdev_vdbg(bp->dev, "macb_tx_error_task: q = %u, t = %u, h = %u\n", | |
564 | (unsigned int)(queue - bp->queues), | |
565 | queue->tx_tail, queue->tx_head); | |
bdcba151 | 566 | |
02c958dd CP |
567 | /* Prevent the queue IRQ handlers from running: each of them may call |
568 | * macb_tx_interrupt(), which in turn may call netif_wake_subqueue(). | |
569 | * As explained below, we have to halt the transmission before updating | |
570 | * TBQP registers so we call netif_tx_stop_all_queues() to notify the | |
571 | * network engine about the macb/gem being halted. | |
572 | */ | |
573 | spin_lock_irqsave(&bp->lock, flags); | |
bdcba151 | 574 | |
e86cd53a | 575 | /* Make sure nobody is trying to queue up new packets */ |
02c958dd | 576 | netif_tx_stop_all_queues(bp->dev); |
d3e61457 | 577 | |
64ec42fe | 578 | /* Stop transmission now |
e86cd53a | 579 | * (in case we have just queued new packets) |
02c958dd | 580 | * macb/gem must be halted to write TBQP register |
e86cd53a NF |
581 | */ |
582 | if (macb_halt_tx(bp)) | |
583 | /* Just complain for now, reinitializing TX path can be good */ | |
584 | netdev_err(bp->dev, "BUG: halt tx timed out\n"); | |
bdcba151 | 585 | |
64ec42fe | 586 | /* Treat frames in TX queue including the ones that caused the error. |
e86cd53a NF |
587 | * Free transmit buffers in upper layer. |
588 | */ | |
02c958dd CP |
589 | for (tail = queue->tx_tail; tail != queue->tx_head; tail++) { |
590 | u32 ctrl; | |
55054a16 | 591 | |
02c958dd | 592 | desc = macb_tx_desc(queue, tail); |
e86cd53a | 593 | ctrl = desc->ctrl; |
02c958dd | 594 | tx_skb = macb_tx_skb(queue, tail); |
e86cd53a | 595 | skb = tx_skb->skb; |
bdcba151 | 596 | |
e86cd53a | 597 | if (ctrl & MACB_BIT(TX_USED)) { |
a4c35ed3 CP |
598 | /* skb is set for the last buffer of the frame */ |
599 | while (!skb) { | |
600 | macb_tx_unmap(bp, tx_skb); | |
601 | tail++; | |
02c958dd | 602 | tx_skb = macb_tx_skb(queue, tail); |
a4c35ed3 CP |
603 | skb = tx_skb->skb; |
604 | } | |
605 | ||
606 | /* ctrl still refers to the first buffer descriptor | |
607 | * since it's the only one written back by the hardware | |
608 | */ | |
609 | if (!(ctrl & MACB_BIT(TX_BUF_EXHAUSTED))) { | |
610 | netdev_vdbg(bp->dev, "txerr skb %u (data %p) TX complete\n", | |
611 | macb_tx_ring_wrap(tail), skb->data); | |
612 | bp->stats.tx_packets++; | |
613 | bp->stats.tx_bytes += skb->len; | |
614 | } | |
e86cd53a | 615 | } else { |
64ec42fe MF |
616 | /* "Buffers exhausted mid-frame" errors may only happen |
617 | * if the driver is buggy, so complain loudly about | |
618 | * those. Statistics are updated by hardware. | |
e86cd53a NF |
619 | */ |
620 | if (ctrl & MACB_BIT(TX_BUF_EXHAUSTED)) | |
621 | netdev_err(bp->dev, | |
622 | "BUG: TX buffers exhausted mid-frame\n"); | |
39eddb4c | 623 | |
e86cd53a NF |
624 | desc->ctrl = ctrl | MACB_BIT(TX_USED); |
625 | } | |
626 | ||
a4c35ed3 | 627 | macb_tx_unmap(bp, tx_skb); |
89e5785f HS |
628 | } |
629 | ||
02c958dd CP |
630 | /* Set end of TX queue */ |
631 | desc = macb_tx_desc(queue, 0); | |
fff8019a | 632 | macb_set_addr(desc, 0); |
02c958dd CP |
633 | desc->ctrl = MACB_BIT(TX_USED); |
634 | ||
e86cd53a NF |
635 | /* Make descriptor updates visible to hardware */ |
636 | wmb(); | |
637 | ||
638 | /* Reinitialize the TX desc queue */ | |
fff8019a HK |
639 | queue_writel(queue, TBQP, (u32)(queue->tx_ring_dma)); |
640 | #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT | |
641 | queue_writel(queue, TBQPH, (u32)(queue->tx_ring_dma >> 32)); | |
642 | #endif | |
e86cd53a | 643 | /* Make TX ring reflect state of hardware */ |
02c958dd CP |
644 | queue->tx_head = 0; |
645 | queue->tx_tail = 0; | |
e86cd53a NF |
646 | |
647 | /* Housework before enabling TX IRQ */ | |
648 | macb_writel(bp, TSR, macb_readl(bp, TSR)); | |
02c958dd CP |
649 | queue_writel(queue, IER, MACB_TX_INT_FLAGS); |
650 | ||
651 | /* Now we are ready to start transmission again */ | |
652 | netif_tx_start_all_queues(bp->dev); | |
653 | macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(TSTART)); | |
654 | ||
655 | spin_unlock_irqrestore(&bp->lock, flags); | |
e86cd53a NF |
656 | } |
657 | ||
02c958dd | 658 | static void macb_tx_interrupt(struct macb_queue *queue) |
e86cd53a NF |
659 | { |
660 | unsigned int tail; | |
661 | unsigned int head; | |
662 | u32 status; | |
02c958dd CP |
663 | struct macb *bp = queue->bp; |
664 | u16 queue_index = queue - bp->queues; | |
e86cd53a NF |
665 | |
666 | status = macb_readl(bp, TSR); | |
667 | macb_writel(bp, TSR, status); | |
668 | ||
581df9e1 | 669 | if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE) |
02c958dd | 670 | queue_writel(queue, ISR, MACB_BIT(TCOMP)); |
749a2b66 | 671 | |
e86cd53a | 672 | netdev_vdbg(bp->dev, "macb_tx_interrupt status = 0x%03lx\n", |
aa50b552 | 673 | (unsigned long)status); |
89e5785f | 674 | |
02c958dd CP |
675 | head = queue->tx_head; |
676 | for (tail = queue->tx_tail; tail != head; tail++) { | |
55054a16 HS |
677 | struct macb_tx_skb *tx_skb; |
678 | struct sk_buff *skb; | |
679 | struct macb_dma_desc *desc; | |
680 | u32 ctrl; | |
89e5785f | 681 | |
02c958dd | 682 | desc = macb_tx_desc(queue, tail); |
89e5785f | 683 | |
03dbe05f | 684 | /* Make hw descriptor updates visible to CPU */ |
89e5785f | 685 | rmb(); |
03dbe05f | 686 | |
55054a16 | 687 | ctrl = desc->ctrl; |
89e5785f | 688 | |
a4c35ed3 CP |
689 | /* TX_USED bit is only set by hardware on the very first buffer |
690 | * descriptor of the transmitted frame. | |
691 | */ | |
55054a16 | 692 | if (!(ctrl & MACB_BIT(TX_USED))) |
89e5785f HS |
693 | break; |
694 | ||
a4c35ed3 CP |
695 | /* Process all buffers of the current transmitted frame */ |
696 | for (;; tail++) { | |
02c958dd | 697 | tx_skb = macb_tx_skb(queue, tail); |
a4c35ed3 CP |
698 | skb = tx_skb->skb; |
699 | ||
700 | /* First, update TX stats if needed */ | |
701 | if (skb) { | |
702 | netdev_vdbg(bp->dev, "skb %u (data %p) TX complete\n", | |
703 | macb_tx_ring_wrap(tail), skb->data); | |
704 | bp->stats.tx_packets++; | |
705 | bp->stats.tx_bytes += skb->len; | |
706 | } | |
55054a16 | 707 | |
a4c35ed3 CP |
708 | /* Now we can safely release resources */ |
709 | macb_tx_unmap(bp, tx_skb); | |
710 | ||
711 | /* skb is set only for the last buffer of the frame. | |
712 | * WARNING: at this point skb has been freed by | |
713 | * macb_tx_unmap(). | |
714 | */ | |
715 | if (skb) | |
716 | break; | |
717 | } | |
89e5785f HS |
718 | } |
719 | ||
02c958dd CP |
720 | queue->tx_tail = tail; |
721 | if (__netif_subqueue_stopped(bp->dev, queue_index) && | |
722 | CIRC_CNT(queue->tx_head, queue->tx_tail, | |
723 | TX_RING_SIZE) <= MACB_TX_WAKEUP_THRESH) | |
724 | netif_wake_subqueue(bp->dev, queue_index); | |
89e5785f HS |
725 | } |
726 | ||
4df95131 NF |
727 | static void gem_rx_refill(struct macb *bp) |
728 | { | |
729 | unsigned int entry; | |
730 | struct sk_buff *skb; | |
4df95131 NF |
731 | dma_addr_t paddr; |
732 | ||
64ec42fe MF |
733 | while (CIRC_SPACE(bp->rx_prepared_head, bp->rx_tail, |
734 | RX_RING_SIZE) > 0) { | |
4df95131 | 735 | entry = macb_rx_ring_wrap(bp->rx_prepared_head); |
4df95131 NF |
736 | |
737 | /* Make hw descriptor updates visible to CPU */ | |
738 | rmb(); | |
739 | ||
4df95131 NF |
740 | bp->rx_prepared_head++; |
741 | ||
aa50b552 | 742 | if (!bp->rx_skbuff[entry]) { |
4df95131 NF |
743 | /* allocate sk_buff for this free entry in ring */ |
744 | skb = netdev_alloc_skb(bp->dev, bp->rx_buffer_size); | |
aa50b552 | 745 | if (unlikely(!skb)) { |
4df95131 NF |
746 | netdev_err(bp->dev, |
747 | "Unable to allocate sk_buff\n"); | |
748 | break; | |
749 | } | |
4df95131 NF |
750 | |
751 | /* now fill corresponding descriptor entry */ | |
752 | paddr = dma_map_single(&bp->pdev->dev, skb->data, | |
64ec42fe MF |
753 | bp->rx_buffer_size, |
754 | DMA_FROM_DEVICE); | |
92030908 SB |
755 | if (dma_mapping_error(&bp->pdev->dev, paddr)) { |
756 | dev_kfree_skb(skb); | |
757 | break; | |
758 | } | |
759 | ||
760 | bp->rx_skbuff[entry] = skb; | |
4df95131 NF |
761 | |
762 | if (entry == RX_RING_SIZE - 1) | |
763 | paddr |= MACB_BIT(RX_WRAP); | |
fff8019a | 764 | macb_set_addr(&(bp->rx_ring[entry]), paddr); |
4df95131 NF |
765 | bp->rx_ring[entry].ctrl = 0; |
766 | ||
767 | /* properly align Ethernet header */ | |
768 | skb_reserve(skb, NET_IP_ALIGN); | |
d4c216c5 PCK |
769 | } else { |
770 | bp->rx_ring[entry].addr &= ~MACB_BIT(RX_USED); | |
771 | bp->rx_ring[entry].ctrl = 0; | |
4df95131 NF |
772 | } |
773 | } | |
774 | ||
775 | /* Make descriptor updates visible to hardware */ | |
776 | wmb(); | |
777 | ||
778 | netdev_vdbg(bp->dev, "rx ring: prepared head %d, tail %d\n", | |
aa50b552 | 779 | bp->rx_prepared_head, bp->rx_tail); |
4df95131 NF |
780 | } |
781 | ||
782 | /* Mark DMA descriptors from begin up to and not including end as unused */ | |
783 | static void discard_partial_frame(struct macb *bp, unsigned int begin, | |
784 | unsigned int end) | |
785 | { | |
786 | unsigned int frag; | |
787 | ||
788 | for (frag = begin; frag != end; frag++) { | |
789 | struct macb_dma_desc *desc = macb_rx_desc(bp, frag); | |
64ec42fe | 790 | |
4df95131 NF |
791 | desc->addr &= ~MACB_BIT(RX_USED); |
792 | } | |
793 | ||
794 | /* Make descriptor updates visible to hardware */ | |
795 | wmb(); | |
796 | ||
64ec42fe | 797 | /* When this happens, the hardware stats registers for |
4df95131 NF |
798 | * whatever caused this is updated, so we don't have to record |
799 | * anything. | |
800 | */ | |
801 | } | |
802 | ||
803 | static int gem_rx(struct macb *bp, int budget) | |
804 | { | |
805 | unsigned int len; | |
806 | unsigned int entry; | |
807 | struct sk_buff *skb; | |
808 | struct macb_dma_desc *desc; | |
809 | int count = 0; | |
810 | ||
811 | while (count < budget) { | |
fff8019a HK |
812 | u32 ctrl; |
813 | dma_addr_t addr; | |
814 | bool rxused; | |
4df95131 NF |
815 | |
816 | entry = macb_rx_ring_wrap(bp->rx_tail); | |
817 | desc = &bp->rx_ring[entry]; | |
818 | ||
819 | /* Make hw descriptor updates visible to CPU */ | |
820 | rmb(); | |
821 | ||
fff8019a HK |
822 | rxused = (desc->addr & MACB_BIT(RX_USED)) ? true : false; |
823 | addr = MACB_BF(RX_WADDR, MACB_BFEXT(RX_WADDR, desc->addr)); | |
824 | #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT | |
825 | addr |= ((u64)(desc->addrh) << 32); | |
826 | #endif | |
4df95131 NF |
827 | ctrl = desc->ctrl; |
828 | ||
fff8019a | 829 | if (!rxused) |
4df95131 NF |
830 | break; |
831 | ||
4df95131 NF |
832 | bp->rx_tail++; |
833 | count++; | |
834 | ||
835 | if (!(ctrl & MACB_BIT(RX_SOF) && ctrl & MACB_BIT(RX_EOF))) { | |
836 | netdev_err(bp->dev, | |
837 | "not whole frame pointed by descriptor\n"); | |
838 | bp->stats.rx_dropped++; | |
839 | break; | |
840 | } | |
841 | skb = bp->rx_skbuff[entry]; | |
842 | if (unlikely(!skb)) { | |
843 | netdev_err(bp->dev, | |
844 | "inconsistent Rx descriptor chain\n"); | |
845 | bp->stats.rx_dropped++; | |
846 | break; | |
847 | } | |
848 | /* now everything is ready for receiving packet */ | |
849 | bp->rx_skbuff[entry] = NULL; | |
98b5a0f4 | 850 | len = ctrl & bp->rx_frm_len_mask; |
4df95131 NF |
851 | |
852 | netdev_vdbg(bp->dev, "gem_rx %u (len %u)\n", entry, len); | |
853 | ||
854 | skb_put(skb, len); | |
4df95131 | 855 | dma_unmap_single(&bp->pdev->dev, addr, |
48330e08 | 856 | bp->rx_buffer_size, DMA_FROM_DEVICE); |
4df95131 NF |
857 | |
858 | skb->protocol = eth_type_trans(skb, bp->dev); | |
859 | skb_checksum_none_assert(skb); | |
924ec53c CP |
860 | if (bp->dev->features & NETIF_F_RXCSUM && |
861 | !(bp->dev->flags & IFF_PROMISC) && | |
862 | GEM_BFEXT(RX_CSUM, ctrl) & GEM_RX_CSUM_CHECKED_MASK) | |
863 | skb->ip_summed = CHECKSUM_UNNECESSARY; | |
4df95131 NF |
864 | |
865 | bp->stats.rx_packets++; | |
866 | bp->stats.rx_bytes += skb->len; | |
867 | ||
868 | #if defined(DEBUG) && defined(VERBOSE_DEBUG) | |
869 | netdev_vdbg(bp->dev, "received skb of length %u, csum: %08x\n", | |
870 | skb->len, skb->csum); | |
871 | print_hex_dump(KERN_DEBUG, " mac: ", DUMP_PREFIX_ADDRESS, 16, 1, | |
51f83014 | 872 | skb_mac_header(skb), 16, true); |
4df95131 NF |
873 | print_hex_dump(KERN_DEBUG, "data: ", DUMP_PREFIX_ADDRESS, 16, 1, |
874 | skb->data, 32, true); | |
875 | #endif | |
876 | ||
877 | netif_receive_skb(skb); | |
878 | } | |
879 | ||
880 | gem_rx_refill(bp); | |
881 | ||
882 | return count; | |
883 | } | |
884 | ||
89e5785f HS |
885 | static int macb_rx_frame(struct macb *bp, unsigned int first_frag, |
886 | unsigned int last_frag) | |
887 | { | |
888 | unsigned int len; | |
889 | unsigned int frag; | |
29bc2e1e | 890 | unsigned int offset; |
89e5785f | 891 | struct sk_buff *skb; |
55054a16 | 892 | struct macb_dma_desc *desc; |
89e5785f | 893 | |
55054a16 | 894 | desc = macb_rx_desc(bp, last_frag); |
98b5a0f4 | 895 | len = desc->ctrl & bp->rx_frm_len_mask; |
89e5785f | 896 | |
a268adb1 | 897 | netdev_vdbg(bp->dev, "macb_rx_frame frags %u - %u (len %u)\n", |
aa50b552 MF |
898 | macb_rx_ring_wrap(first_frag), |
899 | macb_rx_ring_wrap(last_frag), len); | |
89e5785f | 900 | |
64ec42fe | 901 | /* The ethernet header starts NET_IP_ALIGN bytes into the |
29bc2e1e HS |
902 | * first buffer. Since the header is 14 bytes, this makes the |
903 | * payload word-aligned. | |
904 | * | |
905 | * Instead of calling skb_reserve(NET_IP_ALIGN), we just copy | |
906 | * the two padding bytes into the skb so that we avoid hitting | |
907 | * the slowpath in memcpy(), and pull them off afterwards. | |
908 | */ | |
909 | skb = netdev_alloc_skb(bp->dev, len + NET_IP_ALIGN); | |
89e5785f HS |
910 | if (!skb) { |
911 | bp->stats.rx_dropped++; | |
55054a16 HS |
912 | for (frag = first_frag; ; frag++) { |
913 | desc = macb_rx_desc(bp, frag); | |
914 | desc->addr &= ~MACB_BIT(RX_USED); | |
89e5785f HS |
915 | if (frag == last_frag) |
916 | break; | |
917 | } | |
03dbe05f HS |
918 | |
919 | /* Make descriptor updates visible to hardware */ | |
89e5785f | 920 | wmb(); |
03dbe05f | 921 | |
89e5785f HS |
922 | return 1; |
923 | } | |
924 | ||
29bc2e1e HS |
925 | offset = 0; |
926 | len += NET_IP_ALIGN; | |
bc8acf2c | 927 | skb_checksum_none_assert(skb); |
89e5785f HS |
928 | skb_put(skb, len); |
929 | ||
55054a16 | 930 | for (frag = first_frag; ; frag++) { |
1b44791a | 931 | unsigned int frag_len = bp->rx_buffer_size; |
89e5785f HS |
932 | |
933 | if (offset + frag_len > len) { | |
9ba723b0 CP |
934 | if (unlikely(frag != last_frag)) { |
935 | dev_kfree_skb_any(skb); | |
936 | return -1; | |
937 | } | |
89e5785f HS |
938 | frag_len = len - offset; |
939 | } | |
27d7ff46 | 940 | skb_copy_to_linear_data_offset(skb, offset, |
aa50b552 MF |
941 | macb_rx_buffer(bp, frag), |
942 | frag_len); | |
1b44791a | 943 | offset += bp->rx_buffer_size; |
55054a16 HS |
944 | desc = macb_rx_desc(bp, frag); |
945 | desc->addr &= ~MACB_BIT(RX_USED); | |
89e5785f HS |
946 | |
947 | if (frag == last_frag) | |
948 | break; | |
949 | } | |
950 | ||
03dbe05f HS |
951 | /* Make descriptor updates visible to hardware */ |
952 | wmb(); | |
953 | ||
29bc2e1e | 954 | __skb_pull(skb, NET_IP_ALIGN); |
89e5785f HS |
955 | skb->protocol = eth_type_trans(skb, bp->dev); |
956 | ||
957 | bp->stats.rx_packets++; | |
29bc2e1e | 958 | bp->stats.rx_bytes += skb->len; |
a268adb1 | 959 | netdev_vdbg(bp->dev, "received skb of length %u, csum: %08x\n", |
aa50b552 | 960 | skb->len, skb->csum); |
89e5785f HS |
961 | netif_receive_skb(skb); |
962 | ||
963 | return 0; | |
964 | } | |
965 | ||
9ba723b0 CP |
966 | static inline void macb_init_rx_ring(struct macb *bp) |
967 | { | |
968 | dma_addr_t addr; | |
969 | int i; | |
970 | ||
971 | addr = bp->rx_buffers_dma; | |
972 | for (i = 0; i < RX_RING_SIZE; i++) { | |
973 | bp->rx_ring[i].addr = addr; | |
974 | bp->rx_ring[i].ctrl = 0; | |
975 | addr += bp->rx_buffer_size; | |
976 | } | |
977 | bp->rx_ring[RX_RING_SIZE - 1].addr |= MACB_BIT(RX_WRAP); | |
978 | } | |
979 | ||
89e5785f HS |
980 | static int macb_rx(struct macb *bp, int budget) |
981 | { | |
9ba723b0 | 982 | bool reset_rx_queue = false; |
89e5785f | 983 | int received = 0; |
55054a16 | 984 | unsigned int tail; |
89e5785f HS |
985 | int first_frag = -1; |
986 | ||
55054a16 HS |
987 | for (tail = bp->rx_tail; budget > 0; tail++) { |
988 | struct macb_dma_desc *desc = macb_rx_desc(bp, tail); | |
89e5785f HS |
989 | u32 addr, ctrl; |
990 | ||
03dbe05f | 991 | /* Make hw descriptor updates visible to CPU */ |
89e5785f | 992 | rmb(); |
03dbe05f | 993 | |
55054a16 HS |
994 | addr = desc->addr; |
995 | ctrl = desc->ctrl; | |
89e5785f HS |
996 | |
997 | if (!(addr & MACB_BIT(RX_USED))) | |
998 | break; | |
999 | ||
1000 | if (ctrl & MACB_BIT(RX_SOF)) { | |
1001 | if (first_frag != -1) | |
1002 | discard_partial_frame(bp, first_frag, tail); | |
1003 | first_frag = tail; | |
1004 | } | |
1005 | ||
1006 | if (ctrl & MACB_BIT(RX_EOF)) { | |
1007 | int dropped; | |
9ba723b0 CP |
1008 | |
1009 | if (unlikely(first_frag == -1)) { | |
1010 | reset_rx_queue = true; | |
1011 | continue; | |
1012 | } | |
89e5785f HS |
1013 | |
1014 | dropped = macb_rx_frame(bp, first_frag, tail); | |
1015 | first_frag = -1; | |
9ba723b0 CP |
1016 | if (unlikely(dropped < 0)) { |
1017 | reset_rx_queue = true; | |
1018 | continue; | |
1019 | } | |
89e5785f HS |
1020 | if (!dropped) { |
1021 | received++; | |
1022 | budget--; | |
1023 | } | |
1024 | } | |
1025 | } | |
1026 | ||
9ba723b0 CP |
1027 | if (unlikely(reset_rx_queue)) { |
1028 | unsigned long flags; | |
1029 | u32 ctrl; | |
1030 | ||
1031 | netdev_err(bp->dev, "RX queue corruption: reset it\n"); | |
1032 | ||
1033 | spin_lock_irqsave(&bp->lock, flags); | |
1034 | ||
1035 | ctrl = macb_readl(bp, NCR); | |
1036 | macb_writel(bp, NCR, ctrl & ~MACB_BIT(RE)); | |
1037 | ||
1038 | macb_init_rx_ring(bp); | |
1039 | macb_writel(bp, RBQP, bp->rx_ring_dma); | |
1040 | ||
1041 | macb_writel(bp, NCR, ctrl | MACB_BIT(RE)); | |
1042 | ||
1043 | spin_unlock_irqrestore(&bp->lock, flags); | |
1044 | return received; | |
1045 | } | |
1046 | ||
89e5785f HS |
1047 | if (first_frag != -1) |
1048 | bp->rx_tail = first_frag; | |
1049 | else | |
1050 | bp->rx_tail = tail; | |
1051 | ||
1052 | return received; | |
1053 | } | |
1054 | ||
bea3348e | 1055 | static int macb_poll(struct napi_struct *napi, int budget) |
89e5785f | 1056 | { |
bea3348e | 1057 | struct macb *bp = container_of(napi, struct macb, napi); |
bea3348e | 1058 | int work_done; |
89e5785f HS |
1059 | u32 status; |
1060 | ||
1061 | status = macb_readl(bp, RSR); | |
1062 | macb_writel(bp, RSR, status); | |
1063 | ||
bea3348e | 1064 | work_done = 0; |
89e5785f | 1065 | |
a268adb1 | 1066 | netdev_vdbg(bp->dev, "poll: status = %08lx, budget = %d\n", |
aa50b552 | 1067 | (unsigned long)status, budget); |
89e5785f | 1068 | |
4df95131 | 1069 | work_done = bp->macbgem_ops.mog_rx(bp, budget); |
b336369c | 1070 | if (work_done < budget) { |
288379f0 | 1071 | napi_complete(napi); |
89e5785f | 1072 | |
8770e91a NF |
1073 | /* Packets received while interrupts were disabled */ |
1074 | status = macb_readl(bp, RSR); | |
504ad98d | 1075 | if (status) { |
02f7a34f SB |
1076 | if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE) |
1077 | macb_writel(bp, ISR, MACB_BIT(RCOMP)); | |
8770e91a | 1078 | napi_reschedule(napi); |
02f7a34f SB |
1079 | } else { |
1080 | macb_writel(bp, IER, MACB_RX_INT_FLAGS); | |
1081 | } | |
b336369c | 1082 | } |
89e5785f HS |
1083 | |
1084 | /* TODO: Handle errors */ | |
1085 | ||
bea3348e | 1086 | return work_done; |
89e5785f HS |
1087 | } |
1088 | ||
1089 | static irqreturn_t macb_interrupt(int irq, void *dev_id) | |
1090 | { | |
02c958dd CP |
1091 | struct macb_queue *queue = dev_id; |
1092 | struct macb *bp = queue->bp; | |
1093 | struct net_device *dev = bp->dev; | |
bfbb92c4 | 1094 | u32 status, ctrl; |
89e5785f | 1095 | |
02c958dd | 1096 | status = queue_readl(queue, ISR); |
89e5785f HS |
1097 | |
1098 | if (unlikely(!status)) | |
1099 | return IRQ_NONE; | |
1100 | ||
1101 | spin_lock(&bp->lock); | |
1102 | ||
1103 | while (status) { | |
89e5785f HS |
1104 | /* close possible race with dev_close */ |
1105 | if (unlikely(!netif_running(dev))) { | |
02c958dd | 1106 | queue_writel(queue, IDR, -1); |
24468374 NS |
1107 | if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE) |
1108 | queue_writel(queue, ISR, -1); | |
89e5785f HS |
1109 | break; |
1110 | } | |
1111 | ||
02c958dd CP |
1112 | netdev_vdbg(bp->dev, "queue = %u, isr = 0x%08lx\n", |
1113 | (unsigned int)(queue - bp->queues), | |
1114 | (unsigned long)status); | |
a268adb1 | 1115 | |
89e5785f | 1116 | if (status & MACB_RX_INT_FLAGS) { |
64ec42fe | 1117 | /* There's no point taking any more interrupts |
b336369c JH |
1118 | * until we have processed the buffers. The |
1119 | * scheduling call may fail if the poll routine | |
1120 | * is already scheduled, so disable interrupts | |
1121 | * now. | |
1122 | */ | |
02c958dd | 1123 | queue_writel(queue, IDR, MACB_RX_INT_FLAGS); |
581df9e1 | 1124 | if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE) |
02c958dd | 1125 | queue_writel(queue, ISR, MACB_BIT(RCOMP)); |
b336369c | 1126 | |
288379f0 | 1127 | if (napi_schedule_prep(&bp->napi)) { |
a268adb1 | 1128 | netdev_vdbg(bp->dev, "scheduling RX softirq\n"); |
288379f0 | 1129 | __napi_schedule(&bp->napi); |
89e5785f HS |
1130 | } |
1131 | } | |
1132 | ||
e86cd53a | 1133 | if (unlikely(status & (MACB_TX_ERR_FLAGS))) { |
02c958dd CP |
1134 | queue_writel(queue, IDR, MACB_TX_INT_FLAGS); |
1135 | schedule_work(&queue->tx_error_task); | |
6a027b70 SB |
1136 | |
1137 | if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE) | |
02c958dd | 1138 | queue_writel(queue, ISR, MACB_TX_ERR_FLAGS); |
6a027b70 | 1139 | |
e86cd53a NF |
1140 | break; |
1141 | } | |
1142 | ||
1143 | if (status & MACB_BIT(TCOMP)) | |
02c958dd | 1144 | macb_tx_interrupt(queue); |
89e5785f | 1145 | |
64ec42fe | 1146 | /* Link change detection isn't possible with RMII, so we'll |
89e5785f HS |
1147 | * add that if/when we get our hands on a full-blown MII PHY. |
1148 | */ | |
1149 | ||
86b5e7de NS |
1150 | /* There is a hardware issue under heavy load where DMA can |
1151 | * stop, this causes endless "used buffer descriptor read" | |
1152 | * interrupts but it can be cleared by re-enabling RX. See | |
1153 | * the at91 manual, section 41.3.1 or the Zynq manual | |
1154 | * section 16.7.4 for details. | |
1155 | */ | |
bfbb92c4 NS |
1156 | if (status & MACB_BIT(RXUBR)) { |
1157 | ctrl = macb_readl(bp, NCR); | |
1158 | macb_writel(bp, NCR, ctrl & ~MACB_BIT(RE)); | |
1159 | macb_writel(bp, NCR, ctrl | MACB_BIT(RE)); | |
1160 | ||
1161 | if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE) | |
ba504994 | 1162 | queue_writel(queue, ISR, MACB_BIT(RXUBR)); |
bfbb92c4 NS |
1163 | } |
1164 | ||
b19f7f71 AS |
1165 | if (status & MACB_BIT(ISR_ROVR)) { |
1166 | /* We missed at least one packet */ | |
f75ba50b JI |
1167 | if (macb_is_gem(bp)) |
1168 | bp->hw_stats.gem.rx_overruns++; | |
1169 | else | |
1170 | bp->hw_stats.macb.rx_overruns++; | |
6a027b70 SB |
1171 | |
1172 | if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE) | |
02c958dd | 1173 | queue_writel(queue, ISR, MACB_BIT(ISR_ROVR)); |
b19f7f71 AS |
1174 | } |
1175 | ||
89e5785f | 1176 | if (status & MACB_BIT(HRESP)) { |
64ec42fe | 1177 | /* TODO: Reset the hardware, and maybe move the |
c220f8cd JI |
1178 | * netdev_err to a lower-priority context as well |
1179 | * (work queue?) | |
89e5785f | 1180 | */ |
c220f8cd | 1181 | netdev_err(dev, "DMA bus error: HRESP not OK\n"); |
6a027b70 SB |
1182 | |
1183 | if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE) | |
02c958dd | 1184 | queue_writel(queue, ISR, MACB_BIT(HRESP)); |
89e5785f HS |
1185 | } |
1186 | ||
02c958dd | 1187 | status = queue_readl(queue, ISR); |
89e5785f HS |
1188 | } |
1189 | ||
1190 | spin_unlock(&bp->lock); | |
1191 | ||
1192 | return IRQ_HANDLED; | |
1193 | } | |
1194 | ||
6e8cf5c0 | 1195 | #ifdef CONFIG_NET_POLL_CONTROLLER |
64ec42fe | 1196 | /* Polling receive - used by netconsole and other diagnostic tools |
6e8cf5c0 TP |
1197 | * to allow network i/o with interrupts disabled. |
1198 | */ | |
1199 | static void macb_poll_controller(struct net_device *dev) | |
1200 | { | |
02c958dd CP |
1201 | struct macb *bp = netdev_priv(dev); |
1202 | struct macb_queue *queue; | |
6e8cf5c0 | 1203 | unsigned long flags; |
02c958dd | 1204 | unsigned int q; |
6e8cf5c0 TP |
1205 | |
1206 | local_irq_save(flags); | |
02c958dd CP |
1207 | for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) |
1208 | macb_interrupt(dev->irq, queue); | |
6e8cf5c0 TP |
1209 | local_irq_restore(flags); |
1210 | } | |
1211 | #endif | |
1212 | ||
a4c35ed3 | 1213 | static unsigned int macb_tx_map(struct macb *bp, |
02c958dd | 1214 | struct macb_queue *queue, |
a4c35ed3 | 1215 | struct sk_buff *skb) |
89e5785f | 1216 | { |
89e5785f | 1217 | dma_addr_t mapping; |
02c958dd | 1218 | unsigned int len, entry, i, tx_head = queue->tx_head; |
a4c35ed3 | 1219 | struct macb_tx_skb *tx_skb = NULL; |
55054a16 | 1220 | struct macb_dma_desc *desc; |
a4c35ed3 CP |
1221 | unsigned int offset, size, count = 0; |
1222 | unsigned int f, nr_frags = skb_shinfo(skb)->nr_frags; | |
1223 | unsigned int eof = 1; | |
89e5785f | 1224 | u32 ctrl; |
a4c35ed3 CP |
1225 | |
1226 | /* First, map non-paged data */ | |
1227 | len = skb_headlen(skb); | |
1228 | offset = 0; | |
1229 | while (len) { | |
1230 | size = min(len, bp->max_tx_length); | |
1231 | entry = macb_tx_ring_wrap(tx_head); | |
02c958dd | 1232 | tx_skb = &queue->tx_skb[entry]; |
a4c35ed3 CP |
1233 | |
1234 | mapping = dma_map_single(&bp->pdev->dev, | |
1235 | skb->data + offset, | |
1236 | size, DMA_TO_DEVICE); | |
1237 | if (dma_mapping_error(&bp->pdev->dev, mapping)) | |
1238 | goto dma_error; | |
1239 | ||
1240 | /* Save info to properly release resources */ | |
1241 | tx_skb->skb = NULL; | |
1242 | tx_skb->mapping = mapping; | |
1243 | tx_skb->size = size; | |
1244 | tx_skb->mapped_as_page = false; | |
1245 | ||
1246 | len -= size; | |
1247 | offset += size; | |
1248 | count++; | |
1249 | tx_head++; | |
1250 | } | |
1251 | ||
1252 | /* Then, map paged data from fragments */ | |
1253 | for (f = 0; f < nr_frags; f++) { | |
1254 | const skb_frag_t *frag = &skb_shinfo(skb)->frags[f]; | |
1255 | ||
1256 | len = skb_frag_size(frag); | |
1257 | offset = 0; | |
1258 | while (len) { | |
1259 | size = min(len, bp->max_tx_length); | |
1260 | entry = macb_tx_ring_wrap(tx_head); | |
02c958dd | 1261 | tx_skb = &queue->tx_skb[entry]; |
a4c35ed3 CP |
1262 | |
1263 | mapping = skb_frag_dma_map(&bp->pdev->dev, frag, | |
1264 | offset, size, DMA_TO_DEVICE); | |
1265 | if (dma_mapping_error(&bp->pdev->dev, mapping)) | |
1266 | goto dma_error; | |
1267 | ||
1268 | /* Save info to properly release resources */ | |
1269 | tx_skb->skb = NULL; | |
1270 | tx_skb->mapping = mapping; | |
1271 | tx_skb->size = size; | |
1272 | tx_skb->mapped_as_page = true; | |
1273 | ||
1274 | len -= size; | |
1275 | offset += size; | |
1276 | count++; | |
1277 | tx_head++; | |
1278 | } | |
1279 | } | |
1280 | ||
1281 | /* Should never happen */ | |
aa50b552 | 1282 | if (unlikely(!tx_skb)) { |
a4c35ed3 CP |
1283 | netdev_err(bp->dev, "BUG! empty skb!\n"); |
1284 | return 0; | |
1285 | } | |
1286 | ||
1287 | /* This is the last buffer of the frame: save socket buffer */ | |
1288 | tx_skb->skb = skb; | |
1289 | ||
1290 | /* Update TX ring: update buffer descriptors in reverse order | |
1291 | * to avoid race condition | |
1292 | */ | |
1293 | ||
1294 | /* Set 'TX_USED' bit in buffer descriptor at tx_head position | |
1295 | * to set the end of TX queue | |
1296 | */ | |
1297 | i = tx_head; | |
1298 | entry = macb_tx_ring_wrap(i); | |
1299 | ctrl = MACB_BIT(TX_USED); | |
02c958dd | 1300 | desc = &queue->tx_ring[entry]; |
a4c35ed3 CP |
1301 | desc->ctrl = ctrl; |
1302 | ||
1303 | do { | |
1304 | i--; | |
1305 | entry = macb_tx_ring_wrap(i); | |
02c958dd CP |
1306 | tx_skb = &queue->tx_skb[entry]; |
1307 | desc = &queue->tx_ring[entry]; | |
a4c35ed3 CP |
1308 | |
1309 | ctrl = (u32)tx_skb->size; | |
1310 | if (eof) { | |
1311 | ctrl |= MACB_BIT(TX_LAST); | |
1312 | eof = 0; | |
1313 | } | |
1314 | if (unlikely(entry == (TX_RING_SIZE - 1))) | |
1315 | ctrl |= MACB_BIT(TX_WRAP); | |
1316 | ||
1317 | /* Set TX buffer descriptor */ | |
fff8019a | 1318 | macb_set_addr(desc, tx_skb->mapping); |
a4c35ed3 CP |
1319 | /* desc->addr must be visible to hardware before clearing |
1320 | * 'TX_USED' bit in desc->ctrl. | |
1321 | */ | |
1322 | wmb(); | |
1323 | desc->ctrl = ctrl; | |
02c958dd | 1324 | } while (i != queue->tx_head); |
a4c35ed3 | 1325 | |
02c958dd | 1326 | queue->tx_head = tx_head; |
a4c35ed3 CP |
1327 | |
1328 | return count; | |
1329 | ||
1330 | dma_error: | |
1331 | netdev_err(bp->dev, "TX DMA map failed\n"); | |
1332 | ||
02c958dd CP |
1333 | for (i = queue->tx_head; i != tx_head; i++) { |
1334 | tx_skb = macb_tx_skb(queue, i); | |
a4c35ed3 CP |
1335 | |
1336 | macb_tx_unmap(bp, tx_skb); | |
1337 | } | |
1338 | ||
1339 | return 0; | |
1340 | } | |
1341 | ||
007e4ba3 HB |
1342 | static inline int macb_clear_csum(struct sk_buff *skb) |
1343 | { | |
1344 | /* no change for packets without checksum offloading */ | |
1345 | if (skb->ip_summed != CHECKSUM_PARTIAL) | |
1346 | return 0; | |
1347 | ||
1348 | /* make sure we can modify the header */ | |
1349 | if (unlikely(skb_cow_head(skb, 0))) | |
1350 | return -1; | |
1351 | ||
1352 | /* initialize checksum field | |
1353 | * This is required - at least for Zynq, which otherwise calculates | |
1354 | * wrong UDP header checksums for UDP packets with UDP data len <=2 | |
1355 | */ | |
1356 | *(__sum16 *)(skb_checksum_start(skb) + skb->csum_offset) = 0; | |
1357 | return 0; | |
1358 | } | |
1359 | ||
a4c35ed3 CP |
1360 | static int macb_start_xmit(struct sk_buff *skb, struct net_device *dev) |
1361 | { | |
02c958dd | 1362 | u16 queue_index = skb_get_queue_mapping(skb); |
a4c35ed3 | 1363 | struct macb *bp = netdev_priv(dev); |
02c958dd | 1364 | struct macb_queue *queue = &bp->queues[queue_index]; |
4871953c | 1365 | unsigned long flags; |
a4c35ed3 | 1366 | unsigned int count, nr_frags, frag_size, f; |
89e5785f | 1367 | |
a268adb1 HS |
1368 | #if defined(DEBUG) && defined(VERBOSE_DEBUG) |
1369 | netdev_vdbg(bp->dev, | |
aa50b552 MF |
1370 | "start_xmit: queue %hu len %u head %p data %p tail %p end %p\n", |
1371 | queue_index, skb->len, skb->head, skb->data, | |
1372 | skb_tail_pointer(skb), skb_end_pointer(skb)); | |
c220f8cd JI |
1373 | print_hex_dump(KERN_DEBUG, "data: ", DUMP_PREFIX_OFFSET, 16, 1, |
1374 | skb->data, 16, true); | |
89e5785f HS |
1375 | #endif |
1376 | ||
a4c35ed3 CP |
1377 | /* Count how many TX buffer descriptors are needed to send this |
1378 | * socket buffer: skb fragments of jumbo frames may need to be | |
aa50b552 | 1379 | * split into many buffer descriptors. |
a4c35ed3 | 1380 | */ |
94b295ed | 1381 | count = DIV_ROUND_UP(skb_headlen(skb), bp->max_tx_length); |
a4c35ed3 CP |
1382 | nr_frags = skb_shinfo(skb)->nr_frags; |
1383 | for (f = 0; f < nr_frags; f++) { | |
1384 | frag_size = skb_frag_size(&skb_shinfo(skb)->frags[f]); | |
94b295ed | 1385 | count += DIV_ROUND_UP(frag_size, bp->max_tx_length); |
a4c35ed3 CP |
1386 | } |
1387 | ||
4871953c | 1388 | spin_lock_irqsave(&bp->lock, flags); |
89e5785f HS |
1389 | |
1390 | /* This is a hard error, log it. */ | |
02c958dd CP |
1391 | if (CIRC_SPACE(queue->tx_head, queue->tx_tail, TX_RING_SIZE) < count) { |
1392 | netif_stop_subqueue(dev, queue_index); | |
4871953c | 1393 | spin_unlock_irqrestore(&bp->lock, flags); |
c220f8cd | 1394 | netdev_dbg(bp->dev, "tx_head = %u, tx_tail = %u\n", |
02c958dd | 1395 | queue->tx_head, queue->tx_tail); |
5b548140 | 1396 | return NETDEV_TX_BUSY; |
89e5785f HS |
1397 | } |
1398 | ||
007e4ba3 HB |
1399 | if (macb_clear_csum(skb)) { |
1400 | dev_kfree_skb_any(skb); | |
1401 | return NETDEV_TX_OK; | |
1402 | } | |
1403 | ||
a4c35ed3 | 1404 | /* Map socket buffer for DMA transfer */ |
02c958dd | 1405 | if (!macb_tx_map(bp, queue, skb)) { |
c88b5b6a | 1406 | dev_kfree_skb_any(skb); |
92030908 SB |
1407 | goto unlock; |
1408 | } | |
55054a16 | 1409 | |
03dbe05f | 1410 | /* Make newly initialized descriptor visible to hardware */ |
89e5785f HS |
1411 | wmb(); |
1412 | ||
e072092f RC |
1413 | skb_tx_timestamp(skb); |
1414 | ||
89e5785f HS |
1415 | macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(TSTART)); |
1416 | ||
02c958dd CP |
1417 | if (CIRC_SPACE(queue->tx_head, queue->tx_tail, TX_RING_SIZE) < 1) |
1418 | netif_stop_subqueue(dev, queue_index); | |
89e5785f | 1419 | |
92030908 | 1420 | unlock: |
4871953c | 1421 | spin_unlock_irqrestore(&bp->lock, flags); |
89e5785f | 1422 | |
6ed10654 | 1423 | return NETDEV_TX_OK; |
89e5785f HS |
1424 | } |
1425 | ||
4df95131 | 1426 | static void macb_init_rx_buffer_size(struct macb *bp, size_t size) |
1b44791a NF |
1427 | { |
1428 | if (!macb_is_gem(bp)) { | |
1429 | bp->rx_buffer_size = MACB_RX_BUFFER_SIZE; | |
1430 | } else { | |
4df95131 | 1431 | bp->rx_buffer_size = size; |
1b44791a | 1432 | |
1b44791a | 1433 | if (bp->rx_buffer_size % RX_BUFFER_MULTIPLE) { |
4df95131 | 1434 | netdev_dbg(bp->dev, |
aa50b552 MF |
1435 | "RX buffer must be multiple of %d bytes, expanding\n", |
1436 | RX_BUFFER_MULTIPLE); | |
1b44791a | 1437 | bp->rx_buffer_size = |
4df95131 | 1438 | roundup(bp->rx_buffer_size, RX_BUFFER_MULTIPLE); |
1b44791a | 1439 | } |
1b44791a | 1440 | } |
4df95131 NF |
1441 | |
1442 | netdev_dbg(bp->dev, "mtu [%u] rx_buffer_size [%Zu]\n", | |
1443 | bp->dev->mtu, bp->rx_buffer_size); | |
1b44791a NF |
1444 | } |
1445 | ||
4df95131 NF |
1446 | static void gem_free_rx_buffers(struct macb *bp) |
1447 | { | |
1448 | struct sk_buff *skb; | |
1449 | struct macb_dma_desc *desc; | |
1450 | dma_addr_t addr; | |
1451 | int i; | |
1452 | ||
1453 | if (!bp->rx_skbuff) | |
1454 | return; | |
1455 | ||
1456 | for (i = 0; i < RX_RING_SIZE; i++) { | |
1457 | skb = bp->rx_skbuff[i]; | |
1458 | ||
aa50b552 | 1459 | if (!skb) |
4df95131 NF |
1460 | continue; |
1461 | ||
1462 | desc = &bp->rx_ring[i]; | |
1463 | addr = MACB_BF(RX_WADDR, MACB_BFEXT(RX_WADDR, desc->addr)); | |
fff8019a HK |
1464 | #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT |
1465 | addr |= ((u64)(desc->addrh) << 32); | |
1466 | #endif | |
ccd6d0a9 | 1467 | dma_unmap_single(&bp->pdev->dev, addr, bp->rx_buffer_size, |
4df95131 NF |
1468 | DMA_FROM_DEVICE); |
1469 | dev_kfree_skb_any(skb); | |
1470 | skb = NULL; | |
1471 | } | |
1472 | ||
1473 | kfree(bp->rx_skbuff); | |
1474 | bp->rx_skbuff = NULL; | |
1475 | } | |
1476 | ||
1477 | static void macb_free_rx_buffers(struct macb *bp) | |
1478 | { | |
1479 | if (bp->rx_buffers) { | |
1480 | dma_free_coherent(&bp->pdev->dev, | |
1481 | RX_RING_SIZE * bp->rx_buffer_size, | |
1482 | bp->rx_buffers, bp->rx_buffers_dma); | |
1483 | bp->rx_buffers = NULL; | |
1484 | } | |
1485 | } | |
1b44791a | 1486 | |
89e5785f HS |
1487 | static void macb_free_consistent(struct macb *bp) |
1488 | { | |
02c958dd CP |
1489 | struct macb_queue *queue; |
1490 | unsigned int q; | |
1491 | ||
4df95131 | 1492 | bp->macbgem_ops.mog_free_rx_buffers(bp); |
89e5785f HS |
1493 | if (bp->rx_ring) { |
1494 | dma_free_coherent(&bp->pdev->dev, RX_RING_BYTES, | |
1495 | bp->rx_ring, bp->rx_ring_dma); | |
1496 | bp->rx_ring = NULL; | |
1497 | } | |
02c958dd CP |
1498 | |
1499 | for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) { | |
1500 | kfree(queue->tx_skb); | |
1501 | queue->tx_skb = NULL; | |
1502 | if (queue->tx_ring) { | |
1503 | dma_free_coherent(&bp->pdev->dev, TX_RING_BYTES, | |
1504 | queue->tx_ring, queue->tx_ring_dma); | |
1505 | queue->tx_ring = NULL; | |
1506 | } | |
89e5785f | 1507 | } |
4df95131 NF |
1508 | } |
1509 | ||
1510 | static int gem_alloc_rx_buffers(struct macb *bp) | |
1511 | { | |
1512 | int size; | |
1513 | ||
1514 | size = RX_RING_SIZE * sizeof(struct sk_buff *); | |
1515 | bp->rx_skbuff = kzalloc(size, GFP_KERNEL); | |
1516 | if (!bp->rx_skbuff) | |
1517 | return -ENOMEM; | |
64ec42fe MF |
1518 | |
1519 | netdev_dbg(bp->dev, | |
1520 | "Allocated %d RX struct sk_buff entries at %p\n", | |
1521 | RX_RING_SIZE, bp->rx_skbuff); | |
4df95131 NF |
1522 | return 0; |
1523 | } | |
1524 | ||
1525 | static int macb_alloc_rx_buffers(struct macb *bp) | |
1526 | { | |
1527 | int size; | |
1528 | ||
1529 | size = RX_RING_SIZE * bp->rx_buffer_size; | |
1530 | bp->rx_buffers = dma_alloc_coherent(&bp->pdev->dev, size, | |
1531 | &bp->rx_buffers_dma, GFP_KERNEL); | |
1532 | if (!bp->rx_buffers) | |
1533 | return -ENOMEM; | |
64ec42fe MF |
1534 | |
1535 | netdev_dbg(bp->dev, | |
1536 | "Allocated RX buffers of %d bytes at %08lx (mapped %p)\n", | |
1537 | size, (unsigned long)bp->rx_buffers_dma, bp->rx_buffers); | |
4df95131 | 1538 | return 0; |
89e5785f HS |
1539 | } |
1540 | ||
1541 | static int macb_alloc_consistent(struct macb *bp) | |
1542 | { | |
02c958dd CP |
1543 | struct macb_queue *queue; |
1544 | unsigned int q; | |
89e5785f HS |
1545 | int size; |
1546 | ||
02c958dd CP |
1547 | for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) { |
1548 | size = TX_RING_BYTES; | |
1549 | queue->tx_ring = dma_alloc_coherent(&bp->pdev->dev, size, | |
1550 | &queue->tx_ring_dma, | |
1551 | GFP_KERNEL); | |
1552 | if (!queue->tx_ring) | |
1553 | goto out_err; | |
1554 | netdev_dbg(bp->dev, | |
1555 | "Allocated TX ring for queue %u of %d bytes at %08lx (mapped %p)\n", | |
1556 | q, size, (unsigned long)queue->tx_ring_dma, | |
1557 | queue->tx_ring); | |
1558 | ||
1559 | size = TX_RING_SIZE * sizeof(struct macb_tx_skb); | |
1560 | queue->tx_skb = kmalloc(size, GFP_KERNEL); | |
1561 | if (!queue->tx_skb) | |
1562 | goto out_err; | |
1563 | } | |
89e5785f HS |
1564 | |
1565 | size = RX_RING_BYTES; | |
1566 | bp->rx_ring = dma_alloc_coherent(&bp->pdev->dev, size, | |
1567 | &bp->rx_ring_dma, GFP_KERNEL); | |
1568 | if (!bp->rx_ring) | |
1569 | goto out_err; | |
c220f8cd JI |
1570 | netdev_dbg(bp->dev, |
1571 | "Allocated RX ring of %d bytes at %08lx (mapped %p)\n", | |
1572 | size, (unsigned long)bp->rx_ring_dma, bp->rx_ring); | |
89e5785f | 1573 | |
4df95131 | 1574 | if (bp->macbgem_ops.mog_alloc_rx_buffers(bp)) |
89e5785f | 1575 | goto out_err; |
89e5785f HS |
1576 | |
1577 | return 0; | |
1578 | ||
1579 | out_err: | |
1580 | macb_free_consistent(bp); | |
1581 | return -ENOMEM; | |
1582 | } | |
1583 | ||
4df95131 NF |
1584 | static void gem_init_rings(struct macb *bp) |
1585 | { | |
02c958dd CP |
1586 | struct macb_queue *queue; |
1587 | unsigned int q; | |
4df95131 NF |
1588 | int i; |
1589 | ||
02c958dd CP |
1590 | for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) { |
1591 | for (i = 0; i < TX_RING_SIZE; i++) { | |
fff8019a | 1592 | macb_set_addr(&(queue->tx_ring[i]), 0); |
02c958dd CP |
1593 | queue->tx_ring[i].ctrl = MACB_BIT(TX_USED); |
1594 | } | |
1595 | queue->tx_ring[TX_RING_SIZE - 1].ctrl |= MACB_BIT(TX_WRAP); | |
1596 | queue->tx_head = 0; | |
1597 | queue->tx_tail = 0; | |
4df95131 | 1598 | } |
4df95131 | 1599 | |
02c958dd CP |
1600 | bp->rx_tail = 0; |
1601 | bp->rx_prepared_head = 0; | |
4df95131 NF |
1602 | |
1603 | gem_rx_refill(bp); | |
1604 | } | |
1605 | ||
89e5785f HS |
1606 | static void macb_init_rings(struct macb *bp) |
1607 | { | |
1608 | int i; | |
89e5785f | 1609 | |
9ba723b0 | 1610 | macb_init_rx_ring(bp); |
89e5785f HS |
1611 | |
1612 | for (i = 0; i < TX_RING_SIZE; i++) { | |
02c958dd CP |
1613 | bp->queues[0].tx_ring[i].addr = 0; |
1614 | bp->queues[0].tx_ring[i].ctrl = MACB_BIT(TX_USED); | |
89e5785f | 1615 | } |
21d3515c BS |
1616 | bp->queues[0].tx_head = 0; |
1617 | bp->queues[0].tx_tail = 0; | |
02c958dd | 1618 | bp->queues[0].tx_ring[TX_RING_SIZE - 1].ctrl |= MACB_BIT(TX_WRAP); |
89e5785f | 1619 | |
02c958dd | 1620 | bp->rx_tail = 0; |
89e5785f HS |
1621 | } |
1622 | ||
1623 | static void macb_reset_hw(struct macb *bp) | |
1624 | { | |
02c958dd CP |
1625 | struct macb_queue *queue; |
1626 | unsigned int q; | |
1627 | ||
64ec42fe | 1628 | /* Disable RX and TX (XXX: Should we halt the transmission |
89e5785f HS |
1629 | * more gracefully?) |
1630 | */ | |
1631 | macb_writel(bp, NCR, 0); | |
1632 | ||
1633 | /* Clear the stats registers (XXX: Update stats first?) */ | |
1634 | macb_writel(bp, NCR, MACB_BIT(CLRSTAT)); | |
1635 | ||
1636 | /* Clear all status flags */ | |
95ebcea6 JE |
1637 | macb_writel(bp, TSR, -1); |
1638 | macb_writel(bp, RSR, -1); | |
89e5785f HS |
1639 | |
1640 | /* Disable all interrupts */ | |
02c958dd CP |
1641 | for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) { |
1642 | queue_writel(queue, IDR, -1); | |
1643 | queue_readl(queue, ISR); | |
24468374 NS |
1644 | if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE) |
1645 | queue_writel(queue, ISR, -1); | |
02c958dd | 1646 | } |
89e5785f HS |
1647 | } |
1648 | ||
70c9f3d4 JI |
1649 | static u32 gem_mdc_clk_div(struct macb *bp) |
1650 | { | |
1651 | u32 config; | |
1652 | unsigned long pclk_hz = clk_get_rate(bp->pclk); | |
1653 | ||
1654 | if (pclk_hz <= 20000000) | |
1655 | config = GEM_BF(CLK, GEM_CLK_DIV8); | |
1656 | else if (pclk_hz <= 40000000) | |
1657 | config = GEM_BF(CLK, GEM_CLK_DIV16); | |
1658 | else if (pclk_hz <= 80000000) | |
1659 | config = GEM_BF(CLK, GEM_CLK_DIV32); | |
1660 | else if (pclk_hz <= 120000000) | |
1661 | config = GEM_BF(CLK, GEM_CLK_DIV48); | |
1662 | else if (pclk_hz <= 160000000) | |
1663 | config = GEM_BF(CLK, GEM_CLK_DIV64); | |
1664 | else | |
1665 | config = GEM_BF(CLK, GEM_CLK_DIV96); | |
1666 | ||
1667 | return config; | |
1668 | } | |
1669 | ||
1670 | static u32 macb_mdc_clk_div(struct macb *bp) | |
1671 | { | |
1672 | u32 config; | |
1673 | unsigned long pclk_hz; | |
1674 | ||
1675 | if (macb_is_gem(bp)) | |
1676 | return gem_mdc_clk_div(bp); | |
1677 | ||
1678 | pclk_hz = clk_get_rate(bp->pclk); | |
1679 | if (pclk_hz <= 20000000) | |
1680 | config = MACB_BF(CLK, MACB_CLK_DIV8); | |
1681 | else if (pclk_hz <= 40000000) | |
1682 | config = MACB_BF(CLK, MACB_CLK_DIV16); | |
1683 | else if (pclk_hz <= 80000000) | |
1684 | config = MACB_BF(CLK, MACB_CLK_DIV32); | |
1685 | else | |
1686 | config = MACB_BF(CLK, MACB_CLK_DIV64); | |
1687 | ||
1688 | return config; | |
1689 | } | |
1690 | ||
64ec42fe | 1691 | /* Get the DMA bus width field of the network configuration register that we |
757a03c6 JI |
1692 | * should program. We find the width from decoding the design configuration |
1693 | * register to find the maximum supported data bus width. | |
1694 | */ | |
1695 | static u32 macb_dbw(struct macb *bp) | |
1696 | { | |
1697 | if (!macb_is_gem(bp)) | |
1698 | return 0; | |
1699 | ||
1700 | switch (GEM_BFEXT(DBWDEF, gem_readl(bp, DCFG1))) { | |
1701 | case 4: | |
1702 | return GEM_BF(DBW, GEM_DBW128); | |
1703 | case 2: | |
1704 | return GEM_BF(DBW, GEM_DBW64); | |
1705 | case 1: | |
1706 | default: | |
1707 | return GEM_BF(DBW, GEM_DBW32); | |
1708 | } | |
1709 | } | |
1710 | ||
64ec42fe | 1711 | /* Configure the receive DMA engine |
b3e3bd71 | 1712 | * - use the correct receive buffer size |
e175587f | 1713 | * - set best burst length for DMA operations |
b3e3bd71 NF |
1714 | * (if not supported by FIFO, it will fallback to default) |
1715 | * - set both rx/tx packet buffers to full memory size | |
1716 | * These are configurable parameters for GEM. | |
0116da4f JI |
1717 | */ |
1718 | static void macb_configure_dma(struct macb *bp) | |
1719 | { | |
1720 | u32 dmacfg; | |
1721 | ||
1722 | if (macb_is_gem(bp)) { | |
1723 | dmacfg = gem_readl(bp, DMACFG) & ~GEM_BF(RXBS, -1L); | |
1b44791a | 1724 | dmacfg |= GEM_BF(RXBS, bp->rx_buffer_size / RX_BUFFER_MULTIPLE); |
e175587f NF |
1725 | if (bp->dma_burst_length) |
1726 | dmacfg = GEM_BFINS(FBLDO, bp->dma_burst_length, dmacfg); | |
b3e3bd71 | 1727 | dmacfg |= GEM_BIT(TXPBMS) | GEM_BF(RXBMS, -1L); |
a50dad35 | 1728 | dmacfg &= ~GEM_BIT(ENDIA_PKT); |
62f6924c | 1729 | |
f2ce8a9e | 1730 | if (bp->native_io) |
62f6924c AC |
1731 | dmacfg &= ~GEM_BIT(ENDIA_DESC); |
1732 | else | |
1733 | dmacfg |= GEM_BIT(ENDIA_DESC); /* CPU in big endian */ | |
1734 | ||
85ff3d87 CP |
1735 | if (bp->dev->features & NETIF_F_HW_CSUM) |
1736 | dmacfg |= GEM_BIT(TXCOEN); | |
1737 | else | |
1738 | dmacfg &= ~GEM_BIT(TXCOEN); | |
fff8019a HK |
1739 | |
1740 | #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT | |
1741 | dmacfg |= GEM_BIT(ADDR64); | |
1742 | #endif | |
e175587f NF |
1743 | netdev_dbg(bp->dev, "Cadence configure DMA with 0x%08x\n", |
1744 | dmacfg); | |
0116da4f JI |
1745 | gem_writel(bp, DMACFG, dmacfg); |
1746 | } | |
1747 | } | |
1748 | ||
89e5785f HS |
1749 | static void macb_init_hw(struct macb *bp) |
1750 | { | |
02c958dd CP |
1751 | struct macb_queue *queue; |
1752 | unsigned int q; | |
1753 | ||
89e5785f HS |
1754 | u32 config; |
1755 | ||
1756 | macb_reset_hw(bp); | |
314bccc4 | 1757 | macb_set_hwaddr(bp); |
89e5785f | 1758 | |
70c9f3d4 | 1759 | config = macb_mdc_clk_div(bp); |
022be25c PCK |
1760 | if (bp->phy_interface == PHY_INTERFACE_MODE_SGMII) |
1761 | config |= GEM_BIT(SGMIIEN) | GEM_BIT(PCSSEL); | |
29bc2e1e | 1762 | config |= MACB_BF(RBOF, NET_IP_ALIGN); /* Make eth data aligned */ |
89e5785f HS |
1763 | config |= MACB_BIT(PAE); /* PAuse Enable */ |
1764 | config |= MACB_BIT(DRFCS); /* Discard Rx FCS */ | |
a104a6b3 | 1765 | if (bp->caps & MACB_CAPS_JUMBO) |
98b5a0f4 HK |
1766 | config |= MACB_BIT(JFRAME); /* Enable jumbo frames */ |
1767 | else | |
1768 | config |= MACB_BIT(BIG); /* Receive oversized frames */ | |
89e5785f HS |
1769 | if (bp->dev->flags & IFF_PROMISC) |
1770 | config |= MACB_BIT(CAF); /* Copy All Frames */ | |
924ec53c CP |
1771 | else if (macb_is_gem(bp) && bp->dev->features & NETIF_F_RXCSUM) |
1772 | config |= GEM_BIT(RXCOEN); | |
89e5785f HS |
1773 | if (!(bp->dev->flags & IFF_BROADCAST)) |
1774 | config |= MACB_BIT(NBC); /* No BroadCast */ | |
757a03c6 | 1775 | config |= macb_dbw(bp); |
89e5785f | 1776 | macb_writel(bp, NCFGR, config); |
a104a6b3 | 1777 | if ((bp->caps & MACB_CAPS_JUMBO) && bp->jumbo_max_len) |
98b5a0f4 | 1778 | gem_writel(bp, JML, bp->jumbo_max_len); |
26cdfb49 VD |
1779 | bp->speed = SPEED_10; |
1780 | bp->duplex = DUPLEX_HALF; | |
98b5a0f4 | 1781 | bp->rx_frm_len_mask = MACB_RX_FRMLEN_MASK; |
a104a6b3 | 1782 | if (bp->caps & MACB_CAPS_JUMBO) |
98b5a0f4 | 1783 | bp->rx_frm_len_mask = MACB_RX_JFRMLEN_MASK; |
89e5785f | 1784 | |
0116da4f JI |
1785 | macb_configure_dma(bp); |
1786 | ||
89e5785f | 1787 | /* Initialize TX and RX buffers */ |
fff8019a HK |
1788 | macb_writel(bp, RBQP, (u32)(bp->rx_ring_dma)); |
1789 | #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT | |
1790 | macb_writel(bp, RBQPH, (u32)(bp->rx_ring_dma >> 32)); | |
1791 | #endif | |
02c958dd | 1792 | for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) { |
fff8019a HK |
1793 | queue_writel(queue, TBQP, (u32)(queue->tx_ring_dma)); |
1794 | #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT | |
1795 | queue_writel(queue, TBQPH, (u32)(queue->tx_ring_dma >> 32)); | |
1796 | #endif | |
02c958dd CP |
1797 | |
1798 | /* Enable interrupts */ | |
1799 | queue_writel(queue, IER, | |
1800 | MACB_RX_INT_FLAGS | | |
1801 | MACB_TX_INT_FLAGS | | |
1802 | MACB_BIT(HRESP)); | |
1803 | } | |
89e5785f HS |
1804 | |
1805 | /* Enable TX and RX */ | |
6c36a707 | 1806 | macb_writel(bp, NCR, MACB_BIT(RE) | MACB_BIT(TE) | MACB_BIT(MPE)); |
89e5785f HS |
1807 | } |
1808 | ||
64ec42fe | 1809 | /* The hash address register is 64 bits long and takes up two |
446ebd01 PV |
1810 | * locations in the memory map. The least significant bits are stored |
1811 | * in EMAC_HSL and the most significant bits in EMAC_HSH. | |
1812 | * | |
1813 | * The unicast hash enable and the multicast hash enable bits in the | |
1814 | * network configuration register enable the reception of hash matched | |
1815 | * frames. The destination address is reduced to a 6 bit index into | |
1816 | * the 64 bit hash register using the following hash function. The | |
1817 | * hash function is an exclusive or of every sixth bit of the | |
1818 | * destination address. | |
1819 | * | |
1820 | * hi[5] = da[5] ^ da[11] ^ da[17] ^ da[23] ^ da[29] ^ da[35] ^ da[41] ^ da[47] | |
1821 | * hi[4] = da[4] ^ da[10] ^ da[16] ^ da[22] ^ da[28] ^ da[34] ^ da[40] ^ da[46] | |
1822 | * hi[3] = da[3] ^ da[09] ^ da[15] ^ da[21] ^ da[27] ^ da[33] ^ da[39] ^ da[45] | |
1823 | * hi[2] = da[2] ^ da[08] ^ da[14] ^ da[20] ^ da[26] ^ da[32] ^ da[38] ^ da[44] | |
1824 | * hi[1] = da[1] ^ da[07] ^ da[13] ^ da[19] ^ da[25] ^ da[31] ^ da[37] ^ da[43] | |
1825 | * hi[0] = da[0] ^ da[06] ^ da[12] ^ da[18] ^ da[24] ^ da[30] ^ da[36] ^ da[42] | |
1826 | * | |
1827 | * da[0] represents the least significant bit of the first byte | |
1828 | * received, that is, the multicast/unicast indicator, and da[47] | |
1829 | * represents the most significant bit of the last byte received. If | |
1830 | * the hash index, hi[n], points to a bit that is set in the hash | |
1831 | * register then the frame will be matched according to whether the | |
1832 | * frame is multicast or unicast. A multicast match will be signalled | |
1833 | * if the multicast hash enable bit is set, da[0] is 1 and the hash | |
1834 | * index points to a bit set in the hash register. A unicast match | |
1835 | * will be signalled if the unicast hash enable bit is set, da[0] is 0 | |
1836 | * and the hash index points to a bit set in the hash register. To | |
1837 | * receive all multicast frames, the hash register should be set with | |
1838 | * all ones and the multicast hash enable bit should be set in the | |
1839 | * network configuration register. | |
1840 | */ | |
1841 | ||
1842 | static inline int hash_bit_value(int bitnr, __u8 *addr) | |
1843 | { | |
1844 | if (addr[bitnr / 8] & (1 << (bitnr % 8))) | |
1845 | return 1; | |
1846 | return 0; | |
1847 | } | |
1848 | ||
64ec42fe | 1849 | /* Return the hash index value for the specified address. */ |
446ebd01 PV |
1850 | static int hash_get_index(__u8 *addr) |
1851 | { | |
1852 | int i, j, bitval; | |
1853 | int hash_index = 0; | |
1854 | ||
1855 | for (j = 0; j < 6; j++) { | |
1856 | for (i = 0, bitval = 0; i < 8; i++) | |
2fa45e22 | 1857 | bitval ^= hash_bit_value(i * 6 + j, addr); |
446ebd01 PV |
1858 | |
1859 | hash_index |= (bitval << j); | |
1860 | } | |
1861 | ||
1862 | return hash_index; | |
1863 | } | |
1864 | ||
64ec42fe | 1865 | /* Add multicast addresses to the internal multicast-hash table. */ |
446ebd01 PV |
1866 | static void macb_sethashtable(struct net_device *dev) |
1867 | { | |
22bedad3 | 1868 | struct netdev_hw_addr *ha; |
446ebd01 | 1869 | unsigned long mc_filter[2]; |
f9dcbcc9 | 1870 | unsigned int bitnr; |
446ebd01 PV |
1871 | struct macb *bp = netdev_priv(dev); |
1872 | ||
aa50b552 MF |
1873 | mc_filter[0] = 0; |
1874 | mc_filter[1] = 0; | |
446ebd01 | 1875 | |
22bedad3 JP |
1876 | netdev_for_each_mc_addr(ha, dev) { |
1877 | bitnr = hash_get_index(ha->addr); | |
446ebd01 PV |
1878 | mc_filter[bitnr >> 5] |= 1 << (bitnr & 31); |
1879 | } | |
1880 | ||
f75ba50b JI |
1881 | macb_or_gem_writel(bp, HRB, mc_filter[0]); |
1882 | macb_or_gem_writel(bp, HRT, mc_filter[1]); | |
446ebd01 PV |
1883 | } |
1884 | ||
64ec42fe | 1885 | /* Enable/Disable promiscuous and multicast modes. */ |
421d9df0 | 1886 | static void macb_set_rx_mode(struct net_device *dev) |
446ebd01 PV |
1887 | { |
1888 | unsigned long cfg; | |
1889 | struct macb *bp = netdev_priv(dev); | |
1890 | ||
1891 | cfg = macb_readl(bp, NCFGR); | |
1892 | ||
924ec53c | 1893 | if (dev->flags & IFF_PROMISC) { |
446ebd01 PV |
1894 | /* Enable promiscuous mode */ |
1895 | cfg |= MACB_BIT(CAF); | |
924ec53c CP |
1896 | |
1897 | /* Disable RX checksum offload */ | |
1898 | if (macb_is_gem(bp)) | |
1899 | cfg &= ~GEM_BIT(RXCOEN); | |
1900 | } else { | |
1901 | /* Disable promiscuous mode */ | |
446ebd01 PV |
1902 | cfg &= ~MACB_BIT(CAF); |
1903 | ||
924ec53c CP |
1904 | /* Enable RX checksum offload only if requested */ |
1905 | if (macb_is_gem(bp) && dev->features & NETIF_F_RXCSUM) | |
1906 | cfg |= GEM_BIT(RXCOEN); | |
1907 | } | |
1908 | ||
446ebd01 PV |
1909 | if (dev->flags & IFF_ALLMULTI) { |
1910 | /* Enable all multicast mode */ | |
f75ba50b JI |
1911 | macb_or_gem_writel(bp, HRB, -1); |
1912 | macb_or_gem_writel(bp, HRT, -1); | |
446ebd01 | 1913 | cfg |= MACB_BIT(NCFGR_MTI); |
4cd24eaf | 1914 | } else if (!netdev_mc_empty(dev)) { |
446ebd01 PV |
1915 | /* Enable specific multicasts */ |
1916 | macb_sethashtable(dev); | |
1917 | cfg |= MACB_BIT(NCFGR_MTI); | |
1918 | } else if (dev->flags & (~IFF_ALLMULTI)) { | |
1919 | /* Disable all multicast mode */ | |
f75ba50b JI |
1920 | macb_or_gem_writel(bp, HRB, 0); |
1921 | macb_or_gem_writel(bp, HRT, 0); | |
446ebd01 PV |
1922 | cfg &= ~MACB_BIT(NCFGR_MTI); |
1923 | } | |
1924 | ||
1925 | macb_writel(bp, NCFGR, cfg); | |
1926 | } | |
1927 | ||
89e5785f HS |
1928 | static int macb_open(struct net_device *dev) |
1929 | { | |
1930 | struct macb *bp = netdev_priv(dev); | |
4df95131 | 1931 | size_t bufsz = dev->mtu + ETH_HLEN + ETH_FCS_LEN + NET_IP_ALIGN; |
89e5785f HS |
1932 | int err; |
1933 | ||
c220f8cd | 1934 | netdev_dbg(bp->dev, "open\n"); |
89e5785f | 1935 | |
03fc4721 NF |
1936 | /* carrier starts down */ |
1937 | netif_carrier_off(dev); | |
1938 | ||
6c36a707 | 1939 | /* if the phy is not yet register, retry later*/ |
0a91281e | 1940 | if (!dev->phydev) |
6c36a707 | 1941 | return -EAGAIN; |
1b44791a NF |
1942 | |
1943 | /* RX buffers initialization */ | |
4df95131 | 1944 | macb_init_rx_buffer_size(bp, bufsz); |
6c36a707 | 1945 | |
89e5785f HS |
1946 | err = macb_alloc_consistent(bp); |
1947 | if (err) { | |
c220f8cd JI |
1948 | netdev_err(dev, "Unable to allocate DMA memory (error %d)\n", |
1949 | err); | |
89e5785f HS |
1950 | return err; |
1951 | } | |
1952 | ||
bea3348e SH |
1953 | napi_enable(&bp->napi); |
1954 | ||
4df95131 | 1955 | bp->macbgem_ops.mog_init_rings(bp); |
89e5785f | 1956 | macb_init_hw(bp); |
89e5785f | 1957 | |
6c36a707 | 1958 | /* schedule a link state check */ |
0a91281e | 1959 | phy_start(dev->phydev); |
89e5785f | 1960 | |
02c958dd | 1961 | netif_tx_start_all_queues(dev); |
89e5785f HS |
1962 | |
1963 | return 0; | |
1964 | } | |
1965 | ||
1966 | static int macb_close(struct net_device *dev) | |
1967 | { | |
1968 | struct macb *bp = netdev_priv(dev); | |
1969 | unsigned long flags; | |
1970 | ||
02c958dd | 1971 | netif_tx_stop_all_queues(dev); |
bea3348e | 1972 | napi_disable(&bp->napi); |
89e5785f | 1973 | |
0a91281e PR |
1974 | if (dev->phydev) |
1975 | phy_stop(dev->phydev); | |
6c36a707 | 1976 | |
89e5785f HS |
1977 | spin_lock_irqsave(&bp->lock, flags); |
1978 | macb_reset_hw(bp); | |
1979 | netif_carrier_off(dev); | |
1980 | spin_unlock_irqrestore(&bp->lock, flags); | |
1981 | ||
1982 | macb_free_consistent(bp); | |
1983 | ||
1984 | return 0; | |
1985 | } | |
1986 | ||
a5898ea0 HK |
1987 | static int macb_change_mtu(struct net_device *dev, int new_mtu) |
1988 | { | |
1989 | struct macb *bp = netdev_priv(dev); | |
1990 | u32 max_mtu; | |
1991 | ||
1992 | if (netif_running(dev)) | |
1993 | return -EBUSY; | |
1994 | ||
1995 | max_mtu = ETH_DATA_LEN; | |
a104a6b3 | 1996 | if (bp->caps & MACB_CAPS_JUMBO) |
a5898ea0 HK |
1997 | max_mtu = gem_readl(bp, JML) - ETH_HLEN - ETH_FCS_LEN; |
1998 | ||
1999 | if ((new_mtu > max_mtu) || (new_mtu < GEM_MTU_MIN_SIZE)) | |
2000 | return -EINVAL; | |
2001 | ||
2002 | dev->mtu = new_mtu; | |
2003 | ||
2004 | return 0; | |
2005 | } | |
2006 | ||
a494ed8e JI |
2007 | static void gem_update_stats(struct macb *bp) |
2008 | { | |
8bcbf82f | 2009 | unsigned int i; |
a494ed8e | 2010 | u32 *p = &bp->hw_stats.gem.tx_octets_31_0; |
a494ed8e | 2011 | |
3ff13f1c XH |
2012 | for (i = 0; i < GEM_STATS_LEN; ++i, ++p) { |
2013 | u32 offset = gem_statistics[i].offset; | |
7a6e0706 | 2014 | u64 val = bp->macb_reg_readl(bp, offset); |
3ff13f1c XH |
2015 | |
2016 | bp->ethtool_stats[i] += val; | |
2017 | *p += val; | |
2018 | ||
2019 | if (offset == GEM_OCTTXL || offset == GEM_OCTRXL) { | |
2020 | /* Add GEM_OCTTXH, GEM_OCTRXH */ | |
7a6e0706 | 2021 | val = bp->macb_reg_readl(bp, offset + 4); |
2fa45e22 | 2022 | bp->ethtool_stats[i] += ((u64)val) << 32; |
3ff13f1c XH |
2023 | *(++p) += val; |
2024 | } | |
2025 | } | |
a494ed8e JI |
2026 | } |
2027 | ||
2028 | static struct net_device_stats *gem_get_stats(struct macb *bp) | |
2029 | { | |
2030 | struct gem_stats *hwstat = &bp->hw_stats.gem; | |
2031 | struct net_device_stats *nstat = &bp->stats; | |
2032 | ||
2033 | gem_update_stats(bp); | |
2034 | ||
2035 | nstat->rx_errors = (hwstat->rx_frame_check_sequence_errors + | |
2036 | hwstat->rx_alignment_errors + | |
2037 | hwstat->rx_resource_errors + | |
2038 | hwstat->rx_overruns + | |
2039 | hwstat->rx_oversize_frames + | |
2040 | hwstat->rx_jabbers + | |
2041 | hwstat->rx_undersized_frames + | |
2042 | hwstat->rx_length_field_frame_errors); | |
2043 | nstat->tx_errors = (hwstat->tx_late_collisions + | |
2044 | hwstat->tx_excessive_collisions + | |
2045 | hwstat->tx_underrun + | |
2046 | hwstat->tx_carrier_sense_errors); | |
2047 | nstat->multicast = hwstat->rx_multicast_frames; | |
2048 | nstat->collisions = (hwstat->tx_single_collision_frames + | |
2049 | hwstat->tx_multiple_collision_frames + | |
2050 | hwstat->tx_excessive_collisions); | |
2051 | nstat->rx_length_errors = (hwstat->rx_oversize_frames + | |
2052 | hwstat->rx_jabbers + | |
2053 | hwstat->rx_undersized_frames + | |
2054 | hwstat->rx_length_field_frame_errors); | |
2055 | nstat->rx_over_errors = hwstat->rx_resource_errors; | |
2056 | nstat->rx_crc_errors = hwstat->rx_frame_check_sequence_errors; | |
2057 | nstat->rx_frame_errors = hwstat->rx_alignment_errors; | |
2058 | nstat->rx_fifo_errors = hwstat->rx_overruns; | |
2059 | nstat->tx_aborted_errors = hwstat->tx_excessive_collisions; | |
2060 | nstat->tx_carrier_errors = hwstat->tx_carrier_sense_errors; | |
2061 | nstat->tx_fifo_errors = hwstat->tx_underrun; | |
2062 | ||
2063 | return nstat; | |
2064 | } | |
2065 | ||
3ff13f1c XH |
2066 | static void gem_get_ethtool_stats(struct net_device *dev, |
2067 | struct ethtool_stats *stats, u64 *data) | |
2068 | { | |
2069 | struct macb *bp; | |
2070 | ||
2071 | bp = netdev_priv(dev); | |
2072 | gem_update_stats(bp); | |
2fa45e22 | 2073 | memcpy(data, &bp->ethtool_stats, sizeof(u64) * GEM_STATS_LEN); |
3ff13f1c XH |
2074 | } |
2075 | ||
2076 | static int gem_get_sset_count(struct net_device *dev, int sset) | |
2077 | { | |
2078 | switch (sset) { | |
2079 | case ETH_SS_STATS: | |
2080 | return GEM_STATS_LEN; | |
2081 | default: | |
2082 | return -EOPNOTSUPP; | |
2083 | } | |
2084 | } | |
2085 | ||
2086 | static void gem_get_ethtool_strings(struct net_device *dev, u32 sset, u8 *p) | |
2087 | { | |
8bcbf82f | 2088 | unsigned int i; |
3ff13f1c XH |
2089 | |
2090 | switch (sset) { | |
2091 | case ETH_SS_STATS: | |
2092 | for (i = 0; i < GEM_STATS_LEN; i++, p += ETH_GSTRING_LEN) | |
2093 | memcpy(p, gem_statistics[i].stat_string, | |
2094 | ETH_GSTRING_LEN); | |
2095 | break; | |
2096 | } | |
2097 | } | |
2098 | ||
421d9df0 | 2099 | static struct net_device_stats *macb_get_stats(struct net_device *dev) |
89e5785f HS |
2100 | { |
2101 | struct macb *bp = netdev_priv(dev); | |
2102 | struct net_device_stats *nstat = &bp->stats; | |
a494ed8e JI |
2103 | struct macb_stats *hwstat = &bp->hw_stats.macb; |
2104 | ||
2105 | if (macb_is_gem(bp)) | |
2106 | return gem_get_stats(bp); | |
89e5785f | 2107 | |
6c36a707 R |
2108 | /* read stats from hardware */ |
2109 | macb_update_stats(bp); | |
2110 | ||
89e5785f HS |
2111 | /* Convert HW stats into netdevice stats */ |
2112 | nstat->rx_errors = (hwstat->rx_fcs_errors + | |
2113 | hwstat->rx_align_errors + | |
2114 | hwstat->rx_resource_errors + | |
2115 | hwstat->rx_overruns + | |
2116 | hwstat->rx_oversize_pkts + | |
2117 | hwstat->rx_jabbers + | |
2118 | hwstat->rx_undersize_pkts + | |
89e5785f HS |
2119 | hwstat->rx_length_mismatch); |
2120 | nstat->tx_errors = (hwstat->tx_late_cols + | |
2121 | hwstat->tx_excessive_cols + | |
2122 | hwstat->tx_underruns + | |
716723c2 WS |
2123 | hwstat->tx_carrier_errors + |
2124 | hwstat->sqe_test_errors); | |
89e5785f HS |
2125 | nstat->collisions = (hwstat->tx_single_cols + |
2126 | hwstat->tx_multiple_cols + | |
2127 | hwstat->tx_excessive_cols); | |
2128 | nstat->rx_length_errors = (hwstat->rx_oversize_pkts + | |
2129 | hwstat->rx_jabbers + | |
2130 | hwstat->rx_undersize_pkts + | |
2131 | hwstat->rx_length_mismatch); | |
b19f7f71 AS |
2132 | nstat->rx_over_errors = hwstat->rx_resource_errors + |
2133 | hwstat->rx_overruns; | |
89e5785f HS |
2134 | nstat->rx_crc_errors = hwstat->rx_fcs_errors; |
2135 | nstat->rx_frame_errors = hwstat->rx_align_errors; | |
2136 | nstat->rx_fifo_errors = hwstat->rx_overruns; | |
2137 | /* XXX: What does "missed" mean? */ | |
2138 | nstat->tx_aborted_errors = hwstat->tx_excessive_cols; | |
2139 | nstat->tx_carrier_errors = hwstat->tx_carrier_errors; | |
2140 | nstat->tx_fifo_errors = hwstat->tx_underruns; | |
2141 | /* Don't know about heartbeat or window errors... */ | |
2142 | ||
2143 | return nstat; | |
2144 | } | |
2145 | ||
d1d1b53d NF |
2146 | static int macb_get_regs_len(struct net_device *netdev) |
2147 | { | |
2148 | return MACB_GREGS_NBR * sizeof(u32); | |
2149 | } | |
2150 | ||
2151 | static void macb_get_regs(struct net_device *dev, struct ethtool_regs *regs, | |
2152 | void *p) | |
2153 | { | |
2154 | struct macb *bp = netdev_priv(dev); | |
2155 | unsigned int tail, head; | |
2156 | u32 *regs_buff = p; | |
2157 | ||
2158 | regs->version = (macb_readl(bp, MID) & ((1 << MACB_REV_SIZE) - 1)) | |
2159 | | MACB_GREGS_VERSION; | |
2160 | ||
02c958dd CP |
2161 | tail = macb_tx_ring_wrap(bp->queues[0].tx_tail); |
2162 | head = macb_tx_ring_wrap(bp->queues[0].tx_head); | |
d1d1b53d NF |
2163 | |
2164 | regs_buff[0] = macb_readl(bp, NCR); | |
2165 | regs_buff[1] = macb_or_gem_readl(bp, NCFGR); | |
2166 | regs_buff[2] = macb_readl(bp, NSR); | |
2167 | regs_buff[3] = macb_readl(bp, TSR); | |
2168 | regs_buff[4] = macb_readl(bp, RBQP); | |
2169 | regs_buff[5] = macb_readl(bp, TBQP); | |
2170 | regs_buff[6] = macb_readl(bp, RSR); | |
2171 | regs_buff[7] = macb_readl(bp, IMR); | |
2172 | ||
2173 | regs_buff[8] = tail; | |
2174 | regs_buff[9] = head; | |
02c958dd CP |
2175 | regs_buff[10] = macb_tx_dma(&bp->queues[0], tail); |
2176 | regs_buff[11] = macb_tx_dma(&bp->queues[0], head); | |
d1d1b53d | 2177 | |
ce721a70 NA |
2178 | if (!(bp->caps & MACB_CAPS_USRIO_DISABLED)) |
2179 | regs_buff[12] = macb_or_gem_readl(bp, USRIO); | |
64ec42fe | 2180 | if (macb_is_gem(bp)) |
d1d1b53d | 2181 | regs_buff[13] = gem_readl(bp, DMACFG); |
d1d1b53d NF |
2182 | } |
2183 | ||
3e2a5e15 SP |
2184 | static void macb_get_wol(struct net_device *netdev, struct ethtool_wolinfo *wol) |
2185 | { | |
2186 | struct macb *bp = netdev_priv(netdev); | |
2187 | ||
2188 | wol->supported = 0; | |
2189 | wol->wolopts = 0; | |
2190 | ||
2191 | if (bp->wol & MACB_WOL_HAS_MAGIC_PACKET) { | |
2192 | wol->supported = WAKE_MAGIC; | |
2193 | ||
2194 | if (bp->wol & MACB_WOL_ENABLED) | |
2195 | wol->wolopts |= WAKE_MAGIC; | |
2196 | } | |
2197 | } | |
2198 | ||
2199 | static int macb_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol) | |
2200 | { | |
2201 | struct macb *bp = netdev_priv(netdev); | |
2202 | ||
2203 | if (!(bp->wol & MACB_WOL_HAS_MAGIC_PACKET) || | |
2204 | (wol->wolopts & ~WAKE_MAGIC)) | |
2205 | return -EOPNOTSUPP; | |
2206 | ||
2207 | if (wol->wolopts & WAKE_MAGIC) | |
2208 | bp->wol |= MACB_WOL_ENABLED; | |
2209 | else | |
2210 | bp->wol &= ~MACB_WOL_ENABLED; | |
2211 | ||
2212 | device_set_wakeup_enable(&bp->pdev->dev, bp->wol & MACB_WOL_ENABLED); | |
2213 | ||
2214 | return 0; | |
2215 | } | |
2216 | ||
421d9df0 | 2217 | static const struct ethtool_ops macb_ethtool_ops = { |
d1d1b53d NF |
2218 | .get_regs_len = macb_get_regs_len, |
2219 | .get_regs = macb_get_regs, | |
89e5785f | 2220 | .get_link = ethtool_op_get_link, |
17f393e8 | 2221 | .get_ts_info = ethtool_op_get_ts_info, |
3e2a5e15 SP |
2222 | .get_wol = macb_get_wol, |
2223 | .set_wol = macb_set_wol, | |
176275a2 PR |
2224 | .get_link_ksettings = phy_ethtool_get_link_ksettings, |
2225 | .set_link_ksettings = phy_ethtool_set_link_ksettings, | |
8cd5a56c | 2226 | }; |
8cd5a56c | 2227 | |
8093b1c3 | 2228 | static const struct ethtool_ops gem_ethtool_ops = { |
8cd5a56c XH |
2229 | .get_regs_len = macb_get_regs_len, |
2230 | .get_regs = macb_get_regs, | |
2231 | .get_link = ethtool_op_get_link, | |
2232 | .get_ts_info = ethtool_op_get_ts_info, | |
3ff13f1c XH |
2233 | .get_ethtool_stats = gem_get_ethtool_stats, |
2234 | .get_strings = gem_get_ethtool_strings, | |
2235 | .get_sset_count = gem_get_sset_count, | |
176275a2 PR |
2236 | .get_link_ksettings = phy_ethtool_get_link_ksettings, |
2237 | .set_link_ksettings = phy_ethtool_set_link_ksettings, | |
89e5785f HS |
2238 | }; |
2239 | ||
421d9df0 | 2240 | static int macb_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) |
89e5785f | 2241 | { |
0a91281e | 2242 | struct phy_device *phydev = dev->phydev; |
89e5785f HS |
2243 | |
2244 | if (!netif_running(dev)) | |
2245 | return -EINVAL; | |
2246 | ||
6c36a707 R |
2247 | if (!phydev) |
2248 | return -ENODEV; | |
89e5785f | 2249 | |
28b04113 | 2250 | return phy_mii_ioctl(phydev, rq, cmd); |
89e5785f HS |
2251 | } |
2252 | ||
85ff3d87 CP |
2253 | static int macb_set_features(struct net_device *netdev, |
2254 | netdev_features_t features) | |
2255 | { | |
2256 | struct macb *bp = netdev_priv(netdev); | |
2257 | netdev_features_t changed = features ^ netdev->features; | |
2258 | ||
2259 | /* TX checksum offload */ | |
2260 | if ((changed & NETIF_F_HW_CSUM) && macb_is_gem(bp)) { | |
2261 | u32 dmacfg; | |
2262 | ||
2263 | dmacfg = gem_readl(bp, DMACFG); | |
2264 | if (features & NETIF_F_HW_CSUM) | |
2265 | dmacfg |= GEM_BIT(TXCOEN); | |
2266 | else | |
2267 | dmacfg &= ~GEM_BIT(TXCOEN); | |
2268 | gem_writel(bp, DMACFG, dmacfg); | |
2269 | } | |
2270 | ||
924ec53c CP |
2271 | /* RX checksum offload */ |
2272 | if ((changed & NETIF_F_RXCSUM) && macb_is_gem(bp)) { | |
2273 | u32 netcfg; | |
2274 | ||
2275 | netcfg = gem_readl(bp, NCFGR); | |
2276 | if (features & NETIF_F_RXCSUM && | |
2277 | !(netdev->flags & IFF_PROMISC)) | |
2278 | netcfg |= GEM_BIT(RXCOEN); | |
2279 | else | |
2280 | netcfg &= ~GEM_BIT(RXCOEN); | |
2281 | gem_writel(bp, NCFGR, netcfg); | |
2282 | } | |
2283 | ||
85ff3d87 CP |
2284 | return 0; |
2285 | } | |
2286 | ||
5f1fa992 AB |
2287 | static const struct net_device_ops macb_netdev_ops = { |
2288 | .ndo_open = macb_open, | |
2289 | .ndo_stop = macb_close, | |
2290 | .ndo_start_xmit = macb_start_xmit, | |
afc4b13d | 2291 | .ndo_set_rx_mode = macb_set_rx_mode, |
5f1fa992 AB |
2292 | .ndo_get_stats = macb_get_stats, |
2293 | .ndo_do_ioctl = macb_ioctl, | |
2294 | .ndo_validate_addr = eth_validate_addr, | |
a5898ea0 | 2295 | .ndo_change_mtu = macb_change_mtu, |
5f1fa992 | 2296 | .ndo_set_mac_address = eth_mac_addr, |
6e8cf5c0 TP |
2297 | #ifdef CONFIG_NET_POLL_CONTROLLER |
2298 | .ndo_poll_controller = macb_poll_controller, | |
2299 | #endif | |
85ff3d87 | 2300 | .ndo_set_features = macb_set_features, |
5f1fa992 AB |
2301 | }; |
2302 | ||
64ec42fe | 2303 | /* Configure peripheral capabilities according to device tree |
e175587f NF |
2304 | * and integration options used |
2305 | */ | |
64ec42fe MF |
2306 | static void macb_configure_caps(struct macb *bp, |
2307 | const struct macb_config *dt_conf) | |
e175587f NF |
2308 | { |
2309 | u32 dcfg; | |
e175587f | 2310 | |
f6970505 NF |
2311 | if (dt_conf) |
2312 | bp->caps = dt_conf->caps; | |
2313 | ||
f2ce8a9e | 2314 | if (hw_is_gem(bp->regs, bp->native_io)) { |
e175587f NF |
2315 | bp->caps |= MACB_CAPS_MACB_IS_GEM; |
2316 | ||
e175587f NF |
2317 | dcfg = gem_readl(bp, DCFG1); |
2318 | if (GEM_BFEXT(IRQCOR, dcfg) == 0) | |
2319 | bp->caps |= MACB_CAPS_ISR_CLEAR_ON_WRITE; | |
2320 | dcfg = gem_readl(bp, DCFG2); | |
2321 | if ((dcfg & (GEM_BIT(RX_PKT_BUFF) | GEM_BIT(TX_PKT_BUFF))) == 0) | |
2322 | bp->caps |= MACB_CAPS_FIFO_MODE; | |
2323 | } | |
2324 | ||
a35919e1 | 2325 | dev_dbg(&bp->pdev->dev, "Cadence caps 0x%08x\n", bp->caps); |
e175587f NF |
2326 | } |
2327 | ||
02c958dd | 2328 | static void macb_probe_queues(void __iomem *mem, |
f2ce8a9e | 2329 | bool native_io, |
02c958dd CP |
2330 | unsigned int *queue_mask, |
2331 | unsigned int *num_queues) | |
2332 | { | |
2333 | unsigned int hw_q; | |
02c958dd CP |
2334 | |
2335 | *queue_mask = 0x1; | |
2336 | *num_queues = 1; | |
2337 | ||
da120112 NF |
2338 | /* is it macb or gem ? |
2339 | * | |
2340 | * We need to read directly from the hardware here because | |
2341 | * we are early in the probe process and don't have the | |
2342 | * MACB_CAPS_MACB_IS_GEM flag positioned | |
2343 | */ | |
f2ce8a9e | 2344 | if (!hw_is_gem(mem, native_io)) |
02c958dd CP |
2345 | return; |
2346 | ||
2347 | /* bit 0 is never set but queue 0 always exists */ | |
a50dad35 AC |
2348 | *queue_mask = readl_relaxed(mem + GEM_DCFG6) & 0xff; |
2349 | ||
02c958dd CP |
2350 | *queue_mask |= 0x1; |
2351 | ||
2352 | for (hw_q = 1; hw_q < MACB_MAX_QUEUES; ++hw_q) | |
2353 | if (*queue_mask & (1 << hw_q)) | |
2354 | (*num_queues)++; | |
2355 | } | |
2356 | ||
c69618b3 | 2357 | static int macb_clk_init(struct platform_device *pdev, struct clk **pclk, |
aead88bd | 2358 | struct clk **hclk, struct clk **tx_clk, |
2359 | struct clk **rx_clk) | |
89e5785f | 2360 | { |
421d9df0 | 2361 | int err; |
89e5785f | 2362 | |
c69618b3 NF |
2363 | *pclk = devm_clk_get(&pdev->dev, "pclk"); |
2364 | if (IS_ERR(*pclk)) { | |
2365 | err = PTR_ERR(*pclk); | |
b48e0bab | 2366 | dev_err(&pdev->dev, "failed to get macb_clk (%u)\n", err); |
421d9df0 | 2367 | return err; |
0cc8674f | 2368 | } |
461845db | 2369 | |
c69618b3 NF |
2370 | *hclk = devm_clk_get(&pdev->dev, "hclk"); |
2371 | if (IS_ERR(*hclk)) { | |
2372 | err = PTR_ERR(*hclk); | |
b48e0bab | 2373 | dev_err(&pdev->dev, "failed to get hclk (%u)\n", err); |
421d9df0 | 2374 | return err; |
b48e0bab SB |
2375 | } |
2376 | ||
c69618b3 NF |
2377 | *tx_clk = devm_clk_get(&pdev->dev, "tx_clk"); |
2378 | if (IS_ERR(*tx_clk)) | |
2379 | *tx_clk = NULL; | |
e1824dfe | 2380 | |
aead88bd | 2381 | *rx_clk = devm_clk_get(&pdev->dev, "rx_clk"); |
2382 | if (IS_ERR(*rx_clk)) | |
2383 | *rx_clk = NULL; | |
2384 | ||
c69618b3 | 2385 | err = clk_prepare_enable(*pclk); |
b48e0bab SB |
2386 | if (err) { |
2387 | dev_err(&pdev->dev, "failed to enable pclk (%u)\n", err); | |
421d9df0 | 2388 | return err; |
b48e0bab SB |
2389 | } |
2390 | ||
c69618b3 | 2391 | err = clk_prepare_enable(*hclk); |
b48e0bab SB |
2392 | if (err) { |
2393 | dev_err(&pdev->dev, "failed to enable hclk (%u)\n", err); | |
421d9df0 | 2394 | goto err_disable_pclk; |
89e5785f | 2395 | } |
89e5785f | 2396 | |
c69618b3 | 2397 | err = clk_prepare_enable(*tx_clk); |
93b31f48 CP |
2398 | if (err) { |
2399 | dev_err(&pdev->dev, "failed to enable tx_clk (%u)\n", err); | |
421d9df0 | 2400 | goto err_disable_hclk; |
e1824dfe SB |
2401 | } |
2402 | ||
aead88bd | 2403 | err = clk_prepare_enable(*rx_clk); |
2404 | if (err) { | |
2405 | dev_err(&pdev->dev, "failed to enable rx_clk (%u)\n", err); | |
2406 | goto err_disable_txclk; | |
2407 | } | |
2408 | ||
c69618b3 NF |
2409 | return 0; |
2410 | ||
aead88bd | 2411 | err_disable_txclk: |
2412 | clk_disable_unprepare(*tx_clk); | |
2413 | ||
c69618b3 NF |
2414 | err_disable_hclk: |
2415 | clk_disable_unprepare(*hclk); | |
2416 | ||
2417 | err_disable_pclk: | |
2418 | clk_disable_unprepare(*pclk); | |
2419 | ||
2420 | return err; | |
2421 | } | |
2422 | ||
2423 | static int macb_init(struct platform_device *pdev) | |
2424 | { | |
2425 | struct net_device *dev = platform_get_drvdata(pdev); | |
2426 | unsigned int hw_q, q; | |
2427 | struct macb *bp = netdev_priv(dev); | |
2428 | struct macb_queue *queue; | |
2429 | int err; | |
2430 | u32 val; | |
2431 | ||
02c958dd CP |
2432 | /* set the queue register mapping once for all: queue0 has a special |
2433 | * register mapping but we don't want to test the queue index then | |
2434 | * compute the corresponding register offset at run time. | |
2435 | */ | |
cf250de0 | 2436 | for (hw_q = 0, q = 0; hw_q < MACB_MAX_QUEUES; ++hw_q) { |
bfa0914a | 2437 | if (!(bp->queue_mask & (1 << hw_q))) |
02c958dd CP |
2438 | continue; |
2439 | ||
cf250de0 | 2440 | queue = &bp->queues[q]; |
02c958dd CP |
2441 | queue->bp = bp; |
2442 | if (hw_q) { | |
2443 | queue->ISR = GEM_ISR(hw_q - 1); | |
2444 | queue->IER = GEM_IER(hw_q - 1); | |
2445 | queue->IDR = GEM_IDR(hw_q - 1); | |
2446 | queue->IMR = GEM_IMR(hw_q - 1); | |
2447 | queue->TBQP = GEM_TBQP(hw_q - 1); | |
fff8019a HK |
2448 | #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT |
2449 | queue->TBQPH = GEM_TBQPH(hw_q -1); | |
2450 | #endif | |
02c958dd CP |
2451 | } else { |
2452 | /* queue0 uses legacy registers */ | |
2453 | queue->ISR = MACB_ISR; | |
2454 | queue->IER = MACB_IER; | |
2455 | queue->IDR = MACB_IDR; | |
2456 | queue->IMR = MACB_IMR; | |
2457 | queue->TBQP = MACB_TBQP; | |
fff8019a HK |
2458 | #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT |
2459 | queue->TBQPH = MACB_TBQPH; | |
2460 | #endif | |
02c958dd CP |
2461 | } |
2462 | ||
2463 | /* get irq: here we use the linux queue index, not the hardware | |
2464 | * queue index. the queue irq definitions in the device tree | |
2465 | * must remove the optional gaps that could exist in the | |
2466 | * hardware queue mask. | |
2467 | */ | |
cf250de0 | 2468 | queue->irq = platform_get_irq(pdev, q); |
02c958dd | 2469 | err = devm_request_irq(&pdev->dev, queue->irq, macb_interrupt, |
20488239 | 2470 | IRQF_SHARED, dev->name, queue); |
02c958dd CP |
2471 | if (err) { |
2472 | dev_err(&pdev->dev, | |
2473 | "Unable to request IRQ %d (error %d)\n", | |
2474 | queue->irq, err); | |
c69618b3 | 2475 | return err; |
02c958dd CP |
2476 | } |
2477 | ||
2478 | INIT_WORK(&queue->tx_error_task, macb_tx_error_task); | |
cf250de0 | 2479 | q++; |
89e5785f HS |
2480 | } |
2481 | ||
5f1fa992 | 2482 | dev->netdev_ops = &macb_netdev_ops; |
bea3348e | 2483 | netif_napi_add(dev, &bp->napi, macb_poll, 64); |
89e5785f | 2484 | |
4df95131 NF |
2485 | /* setup appropriated routines according to adapter type */ |
2486 | if (macb_is_gem(bp)) { | |
a4c35ed3 | 2487 | bp->max_tx_length = GEM_MAX_TX_LEN; |
4df95131 NF |
2488 | bp->macbgem_ops.mog_alloc_rx_buffers = gem_alloc_rx_buffers; |
2489 | bp->macbgem_ops.mog_free_rx_buffers = gem_free_rx_buffers; | |
2490 | bp->macbgem_ops.mog_init_rings = gem_init_rings; | |
2491 | bp->macbgem_ops.mog_rx = gem_rx; | |
8cd5a56c | 2492 | dev->ethtool_ops = &gem_ethtool_ops; |
4df95131 | 2493 | } else { |
a4c35ed3 | 2494 | bp->max_tx_length = MACB_MAX_TX_LEN; |
4df95131 NF |
2495 | bp->macbgem_ops.mog_alloc_rx_buffers = macb_alloc_rx_buffers; |
2496 | bp->macbgem_ops.mog_free_rx_buffers = macb_free_rx_buffers; | |
2497 | bp->macbgem_ops.mog_init_rings = macb_init_rings; | |
2498 | bp->macbgem_ops.mog_rx = macb_rx; | |
8cd5a56c | 2499 | dev->ethtool_ops = &macb_ethtool_ops; |
4df95131 NF |
2500 | } |
2501 | ||
a4c35ed3 CP |
2502 | /* Set features */ |
2503 | dev->hw_features = NETIF_F_SG; | |
85ff3d87 CP |
2504 | /* Checksum offload is only available on gem with packet buffer */ |
2505 | if (macb_is_gem(bp) && !(bp->caps & MACB_CAPS_FIFO_MODE)) | |
924ec53c | 2506 | dev->hw_features |= NETIF_F_HW_CSUM | NETIF_F_RXCSUM; |
a4c35ed3 CP |
2507 | if (bp->caps & MACB_CAPS_SG_DISABLED) |
2508 | dev->hw_features &= ~NETIF_F_SG; | |
2509 | dev->features = dev->hw_features; | |
2510 | ||
ce721a70 NA |
2511 | if (!(bp->caps & MACB_CAPS_USRIO_DISABLED)) { |
2512 | val = 0; | |
2513 | if (bp->phy_interface == PHY_INTERFACE_MODE_RGMII) | |
2514 | val = GEM_BIT(RGMII); | |
2515 | else if (bp->phy_interface == PHY_INTERFACE_MODE_RMII && | |
6bdaa5e9 | 2516 | (bp->caps & MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII)) |
ce721a70 | 2517 | val = MACB_BIT(RMII); |
6bdaa5e9 | 2518 | else if (!(bp->caps & MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII)) |
ce721a70 | 2519 | val = MACB_BIT(MII); |
421d9df0 | 2520 | |
ce721a70 NA |
2521 | if (bp->caps & MACB_CAPS_USRIO_HAS_CLKEN) |
2522 | val |= MACB_BIT(CLKEN); | |
421d9df0 | 2523 | |
ce721a70 NA |
2524 | macb_or_gem_writel(bp, USRIO, val); |
2525 | } | |
421d9df0 | 2526 | |
89e5785f | 2527 | /* Set MII management clock divider */ |
421d9df0 CP |
2528 | val = macb_mdc_clk_div(bp); |
2529 | val |= macb_dbw(bp); | |
022be25c PCK |
2530 | if (bp->phy_interface == PHY_INTERFACE_MODE_SGMII) |
2531 | val |= GEM_BIT(SGMIIEN) | GEM_BIT(PCSSEL); | |
421d9df0 CP |
2532 | macb_writel(bp, NCFGR, val); |
2533 | ||
2534 | return 0; | |
421d9df0 CP |
2535 | } |
2536 | ||
2537 | #if defined(CONFIG_OF) | |
2538 | /* 1518 rounded up */ | |
2539 | #define AT91ETHER_MAX_RBUFF_SZ 0x600 | |
2540 | /* max number of receive buffers */ | |
2541 | #define AT91ETHER_MAX_RX_DESCR 9 | |
2542 | ||
2543 | /* Initialize and start the Receiver and Transmit subsystems */ | |
2544 | static int at91ether_start(struct net_device *dev) | |
2545 | { | |
2546 | struct macb *lp = netdev_priv(dev); | |
2547 | dma_addr_t addr; | |
2548 | u32 ctl; | |
2549 | int i; | |
2550 | ||
2551 | lp->rx_ring = dma_alloc_coherent(&lp->pdev->dev, | |
2552 | (AT91ETHER_MAX_RX_DESCR * | |
2553 | sizeof(struct macb_dma_desc)), | |
2554 | &lp->rx_ring_dma, GFP_KERNEL); | |
2555 | if (!lp->rx_ring) | |
2556 | return -ENOMEM; | |
2557 | ||
2558 | lp->rx_buffers = dma_alloc_coherent(&lp->pdev->dev, | |
2559 | AT91ETHER_MAX_RX_DESCR * | |
2560 | AT91ETHER_MAX_RBUFF_SZ, | |
2561 | &lp->rx_buffers_dma, GFP_KERNEL); | |
2562 | if (!lp->rx_buffers) { | |
2563 | dma_free_coherent(&lp->pdev->dev, | |
2564 | AT91ETHER_MAX_RX_DESCR * | |
2565 | sizeof(struct macb_dma_desc), | |
2566 | lp->rx_ring, lp->rx_ring_dma); | |
2567 | lp->rx_ring = NULL; | |
2568 | return -ENOMEM; | |
2569 | } | |
2570 | ||
2571 | addr = lp->rx_buffers_dma; | |
2572 | for (i = 0; i < AT91ETHER_MAX_RX_DESCR; i++) { | |
2573 | lp->rx_ring[i].addr = addr; | |
2574 | lp->rx_ring[i].ctrl = 0; | |
2575 | addr += AT91ETHER_MAX_RBUFF_SZ; | |
2576 | } | |
2577 | ||
2578 | /* Set the Wrap bit on the last descriptor */ | |
2579 | lp->rx_ring[AT91ETHER_MAX_RX_DESCR - 1].addr |= MACB_BIT(RX_WRAP); | |
2580 | ||
2581 | /* Reset buffer index */ | |
2582 | lp->rx_tail = 0; | |
2583 | ||
2584 | /* Program address of descriptor list in Rx Buffer Queue register */ | |
2585 | macb_writel(lp, RBQP, lp->rx_ring_dma); | |
2586 | ||
2587 | /* Enable Receive and Transmit */ | |
2588 | ctl = macb_readl(lp, NCR); | |
2589 | macb_writel(lp, NCR, ctl | MACB_BIT(RE) | MACB_BIT(TE)); | |
2590 | ||
2591 | return 0; | |
2592 | } | |
2593 | ||
2594 | /* Open the ethernet interface */ | |
2595 | static int at91ether_open(struct net_device *dev) | |
2596 | { | |
2597 | struct macb *lp = netdev_priv(dev); | |
2598 | u32 ctl; | |
2599 | int ret; | |
2600 | ||
2601 | /* Clear internal statistics */ | |
2602 | ctl = macb_readl(lp, NCR); | |
2603 | macb_writel(lp, NCR, ctl | MACB_BIT(CLRSTAT)); | |
2604 | ||
2605 | macb_set_hwaddr(lp); | |
2606 | ||
2607 | ret = at91ether_start(dev); | |
2608 | if (ret) | |
2609 | return ret; | |
2610 | ||
2611 | /* Enable MAC interrupts */ | |
2612 | macb_writel(lp, IER, MACB_BIT(RCOMP) | | |
2613 | MACB_BIT(RXUBR) | | |
2614 | MACB_BIT(ISR_TUND) | | |
2615 | MACB_BIT(ISR_RLE) | | |
2616 | MACB_BIT(TCOMP) | | |
2617 | MACB_BIT(ISR_ROVR) | | |
2618 | MACB_BIT(HRESP)); | |
2619 | ||
2620 | /* schedule a link state check */ | |
0a91281e | 2621 | phy_start(dev->phydev); |
421d9df0 CP |
2622 | |
2623 | netif_start_queue(dev); | |
2624 | ||
2625 | return 0; | |
2626 | } | |
2627 | ||
2628 | /* Close the interface */ | |
2629 | static int at91ether_close(struct net_device *dev) | |
2630 | { | |
2631 | struct macb *lp = netdev_priv(dev); | |
2632 | u32 ctl; | |
2633 | ||
2634 | /* Disable Receiver and Transmitter */ | |
2635 | ctl = macb_readl(lp, NCR); | |
2636 | macb_writel(lp, NCR, ctl & ~(MACB_BIT(TE) | MACB_BIT(RE))); | |
2637 | ||
2638 | /* Disable MAC interrupts */ | |
2639 | macb_writel(lp, IDR, MACB_BIT(RCOMP) | | |
2640 | MACB_BIT(RXUBR) | | |
2641 | MACB_BIT(ISR_TUND) | | |
2642 | MACB_BIT(ISR_RLE) | | |
2643 | MACB_BIT(TCOMP) | | |
2644 | MACB_BIT(ISR_ROVR) | | |
2645 | MACB_BIT(HRESP)); | |
2646 | ||
2647 | netif_stop_queue(dev); | |
2648 | ||
2649 | dma_free_coherent(&lp->pdev->dev, | |
2650 | AT91ETHER_MAX_RX_DESCR * | |
2651 | sizeof(struct macb_dma_desc), | |
2652 | lp->rx_ring, lp->rx_ring_dma); | |
2653 | lp->rx_ring = NULL; | |
2654 | ||
2655 | dma_free_coherent(&lp->pdev->dev, | |
2656 | AT91ETHER_MAX_RX_DESCR * AT91ETHER_MAX_RBUFF_SZ, | |
2657 | lp->rx_buffers, lp->rx_buffers_dma); | |
2658 | lp->rx_buffers = NULL; | |
2659 | ||
2660 | return 0; | |
2661 | } | |
2662 | ||
2663 | /* Transmit packet */ | |
2664 | static int at91ether_start_xmit(struct sk_buff *skb, struct net_device *dev) | |
2665 | { | |
2666 | struct macb *lp = netdev_priv(dev); | |
2667 | ||
2668 | if (macb_readl(lp, TSR) & MACB_BIT(RM9200_BNQ)) { | |
2669 | netif_stop_queue(dev); | |
2670 | ||
2671 | /* Store packet information (to free when Tx completed) */ | |
2672 | lp->skb = skb; | |
2673 | lp->skb_length = skb->len; | |
2674 | lp->skb_physaddr = dma_map_single(NULL, skb->data, skb->len, | |
2675 | DMA_TO_DEVICE); | |
2676 | ||
2677 | /* Set address of the data in the Transmit Address register */ | |
2678 | macb_writel(lp, TAR, lp->skb_physaddr); | |
2679 | /* Set length of the packet in the Transmit Control register */ | |
2680 | macb_writel(lp, TCR, skb->len); | |
89e5785f | 2681 | |
421d9df0 CP |
2682 | } else { |
2683 | netdev_err(dev, "%s called, but device is busy!\n", __func__); | |
2684 | return NETDEV_TX_BUSY; | |
2685 | } | |
2686 | ||
2687 | return NETDEV_TX_OK; | |
2688 | } | |
2689 | ||
2690 | /* Extract received frame from buffer descriptors and sent to upper layers. | |
2691 | * (Called from interrupt context) | |
2692 | */ | |
2693 | static void at91ether_rx(struct net_device *dev) | |
2694 | { | |
2695 | struct macb *lp = netdev_priv(dev); | |
2696 | unsigned char *p_recv; | |
2697 | struct sk_buff *skb; | |
2698 | unsigned int pktlen; | |
2699 | ||
2700 | while (lp->rx_ring[lp->rx_tail].addr & MACB_BIT(RX_USED)) { | |
2701 | p_recv = lp->rx_buffers + lp->rx_tail * AT91ETHER_MAX_RBUFF_SZ; | |
2702 | pktlen = MACB_BF(RX_FRMLEN, lp->rx_ring[lp->rx_tail].ctrl); | |
2703 | skb = netdev_alloc_skb(dev, pktlen + 2); | |
2704 | if (skb) { | |
2705 | skb_reserve(skb, 2); | |
2706 | memcpy(skb_put(skb, pktlen), p_recv, pktlen); | |
2707 | ||
2708 | skb->protocol = eth_type_trans(skb, dev); | |
2709 | lp->stats.rx_packets++; | |
2710 | lp->stats.rx_bytes += pktlen; | |
2711 | netif_rx(skb); | |
2712 | } else { | |
2713 | lp->stats.rx_dropped++; | |
2714 | } | |
2715 | ||
2716 | if (lp->rx_ring[lp->rx_tail].ctrl & MACB_BIT(RX_MHASH_MATCH)) | |
2717 | lp->stats.multicast++; | |
2718 | ||
2719 | /* reset ownership bit */ | |
2720 | lp->rx_ring[lp->rx_tail].addr &= ~MACB_BIT(RX_USED); | |
2721 | ||
2722 | /* wrap after last buffer */ | |
2723 | if (lp->rx_tail == AT91ETHER_MAX_RX_DESCR - 1) | |
2724 | lp->rx_tail = 0; | |
2725 | else | |
2726 | lp->rx_tail++; | |
2727 | } | |
2728 | } | |
2729 | ||
2730 | /* MAC interrupt handler */ | |
2731 | static irqreturn_t at91ether_interrupt(int irq, void *dev_id) | |
2732 | { | |
2733 | struct net_device *dev = dev_id; | |
2734 | struct macb *lp = netdev_priv(dev); | |
2735 | u32 intstatus, ctl; | |
2736 | ||
2737 | /* MAC Interrupt Status register indicates what interrupts are pending. | |
2738 | * It is automatically cleared once read. | |
2739 | */ | |
2740 | intstatus = macb_readl(lp, ISR); | |
2741 | ||
2742 | /* Receive complete */ | |
2743 | if (intstatus & MACB_BIT(RCOMP)) | |
2744 | at91ether_rx(dev); | |
2745 | ||
2746 | /* Transmit complete */ | |
2747 | if (intstatus & MACB_BIT(TCOMP)) { | |
2748 | /* The TCOM bit is set even if the transmission failed */ | |
2749 | if (intstatus & (MACB_BIT(ISR_TUND) | MACB_BIT(ISR_RLE))) | |
2750 | lp->stats.tx_errors++; | |
2751 | ||
2752 | if (lp->skb) { | |
2753 | dev_kfree_skb_irq(lp->skb); | |
2754 | lp->skb = NULL; | |
2755 | dma_unmap_single(NULL, lp->skb_physaddr, | |
2756 | lp->skb_length, DMA_TO_DEVICE); | |
2757 | lp->stats.tx_packets++; | |
2758 | lp->stats.tx_bytes += lp->skb_length; | |
2759 | } | |
2760 | netif_wake_queue(dev); | |
2761 | } | |
2762 | ||
2763 | /* Work-around for EMAC Errata section 41.3.1 */ | |
2764 | if (intstatus & MACB_BIT(RXUBR)) { | |
2765 | ctl = macb_readl(lp, NCR); | |
2766 | macb_writel(lp, NCR, ctl & ~MACB_BIT(RE)); | |
2767 | macb_writel(lp, NCR, ctl | MACB_BIT(RE)); | |
2768 | } | |
2769 | ||
2770 | if (intstatus & MACB_BIT(ISR_ROVR)) | |
2771 | netdev_err(dev, "ROVR error\n"); | |
2772 | ||
2773 | return IRQ_HANDLED; | |
2774 | } | |
2775 | ||
2776 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
2777 | static void at91ether_poll_controller(struct net_device *dev) | |
2778 | { | |
2779 | unsigned long flags; | |
2780 | ||
2781 | local_irq_save(flags); | |
2782 | at91ether_interrupt(dev->irq, dev); | |
2783 | local_irq_restore(flags); | |
2784 | } | |
2785 | #endif | |
2786 | ||
2787 | static const struct net_device_ops at91ether_netdev_ops = { | |
2788 | .ndo_open = at91ether_open, | |
2789 | .ndo_stop = at91ether_close, | |
2790 | .ndo_start_xmit = at91ether_start_xmit, | |
2791 | .ndo_get_stats = macb_get_stats, | |
2792 | .ndo_set_rx_mode = macb_set_rx_mode, | |
2793 | .ndo_set_mac_address = eth_mac_addr, | |
2794 | .ndo_do_ioctl = macb_ioctl, | |
2795 | .ndo_validate_addr = eth_validate_addr, | |
2796 | .ndo_change_mtu = eth_change_mtu, | |
2797 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
2798 | .ndo_poll_controller = at91ether_poll_controller, | |
2799 | #endif | |
2800 | }; | |
2801 | ||
c69618b3 | 2802 | static int at91ether_clk_init(struct platform_device *pdev, struct clk **pclk, |
aead88bd | 2803 | struct clk **hclk, struct clk **tx_clk, |
2804 | struct clk **rx_clk) | |
421d9df0 | 2805 | { |
421d9df0 | 2806 | int err; |
421d9df0 | 2807 | |
c69618b3 NF |
2808 | *hclk = NULL; |
2809 | *tx_clk = NULL; | |
aead88bd | 2810 | *rx_clk = NULL; |
c69618b3 NF |
2811 | |
2812 | *pclk = devm_clk_get(&pdev->dev, "ether_clk"); | |
2813 | if (IS_ERR(*pclk)) | |
2814 | return PTR_ERR(*pclk); | |
421d9df0 | 2815 | |
c69618b3 | 2816 | err = clk_prepare_enable(*pclk); |
421d9df0 CP |
2817 | if (err) { |
2818 | dev_err(&pdev->dev, "failed to enable pclk (%u)\n", err); | |
2819 | return err; | |
2820 | } | |
2821 | ||
c69618b3 NF |
2822 | return 0; |
2823 | } | |
2824 | ||
2825 | static int at91ether_init(struct platform_device *pdev) | |
2826 | { | |
2827 | struct net_device *dev = platform_get_drvdata(pdev); | |
2828 | struct macb *bp = netdev_priv(dev); | |
2829 | int err; | |
2830 | u32 reg; | |
2831 | ||
421d9df0 CP |
2832 | dev->netdev_ops = &at91ether_netdev_ops; |
2833 | dev->ethtool_ops = &macb_ethtool_ops; | |
2834 | ||
2835 | err = devm_request_irq(&pdev->dev, dev->irq, at91ether_interrupt, | |
2836 | 0, dev->name, dev); | |
2837 | if (err) | |
c69618b3 | 2838 | return err; |
421d9df0 CP |
2839 | |
2840 | macb_writel(bp, NCR, 0); | |
2841 | ||
2842 | reg = MACB_BF(CLK, MACB_CLK_DIV32) | MACB_BIT(BIG); | |
2843 | if (bp->phy_interface == PHY_INTERFACE_MODE_RMII) | |
2844 | reg |= MACB_BIT(RM9200_RMII); | |
2845 | ||
2846 | macb_writel(bp, NCFGR, reg); | |
2847 | ||
2848 | return 0; | |
421d9df0 CP |
2849 | } |
2850 | ||
3cef5c5b | 2851 | static const struct macb_config at91sam9260_config = { |
6bdaa5e9 | 2852 | .caps = MACB_CAPS_USRIO_HAS_CLKEN | MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII, |
c69618b3 | 2853 | .clk_init = macb_clk_init, |
421d9df0 CP |
2854 | .init = macb_init, |
2855 | }; | |
2856 | ||
3cef5c5b | 2857 | static const struct macb_config pc302gem_config = { |
421d9df0 CP |
2858 | .caps = MACB_CAPS_SG_DISABLED | MACB_CAPS_GIGABIT_MODE_AVAILABLE, |
2859 | .dma_burst_length = 16, | |
c69618b3 | 2860 | .clk_init = macb_clk_init, |
421d9df0 CP |
2861 | .init = macb_init, |
2862 | }; | |
2863 | ||
5c8fe711 | 2864 | static const struct macb_config sama5d2_config = { |
6bdaa5e9 | 2865 | .caps = MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII, |
5c8fe711 CP |
2866 | .dma_burst_length = 16, |
2867 | .clk_init = macb_clk_init, | |
2868 | .init = macb_init, | |
2869 | }; | |
2870 | ||
3cef5c5b | 2871 | static const struct macb_config sama5d3_config = { |
6bdaa5e9 NF |
2872 | .caps = MACB_CAPS_SG_DISABLED | MACB_CAPS_GIGABIT_MODE_AVAILABLE |
2873 | | MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII, | |
421d9df0 | 2874 | .dma_burst_length = 16, |
c69618b3 | 2875 | .clk_init = macb_clk_init, |
421d9df0 CP |
2876 | .init = macb_init, |
2877 | }; | |
2878 | ||
3cef5c5b | 2879 | static const struct macb_config sama5d4_config = { |
6bdaa5e9 | 2880 | .caps = MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII, |
421d9df0 | 2881 | .dma_burst_length = 4, |
c69618b3 | 2882 | .clk_init = macb_clk_init, |
421d9df0 CP |
2883 | .init = macb_init, |
2884 | }; | |
2885 | ||
3cef5c5b | 2886 | static const struct macb_config emac_config = { |
c69618b3 | 2887 | .clk_init = at91ether_clk_init, |
421d9df0 CP |
2888 | .init = at91ether_init, |
2889 | }; | |
2890 | ||
e611b5b8 NA |
2891 | static const struct macb_config np4_config = { |
2892 | .caps = MACB_CAPS_USRIO_DISABLED, | |
2893 | .clk_init = macb_clk_init, | |
2894 | .init = macb_init, | |
2895 | }; | |
36583eb5 | 2896 | |
7b61f9c1 | 2897 | static const struct macb_config zynqmp_config = { |
7baaa909 | 2898 | .caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE | MACB_CAPS_JUMBO, |
7b61f9c1 HK |
2899 | .dma_burst_length = 16, |
2900 | .clk_init = macb_clk_init, | |
2901 | .init = macb_init, | |
98b5a0f4 | 2902 | .jumbo_max_len = 10240, |
7b61f9c1 HK |
2903 | }; |
2904 | ||
222ca8e0 | 2905 | static const struct macb_config zynq_config = { |
7baaa909 | 2906 | .caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE | MACB_CAPS_NO_GIGABIT_HALF, |
222ca8e0 NS |
2907 | .dma_burst_length = 16, |
2908 | .clk_init = macb_clk_init, | |
2909 | .init = macb_init, | |
2910 | }; | |
2911 | ||
421d9df0 CP |
2912 | static const struct of_device_id macb_dt_ids[] = { |
2913 | { .compatible = "cdns,at32ap7000-macb" }, | |
2914 | { .compatible = "cdns,at91sam9260-macb", .data = &at91sam9260_config }, | |
2915 | { .compatible = "cdns,macb" }, | |
e611b5b8 | 2916 | { .compatible = "cdns,np4-macb", .data = &np4_config }, |
421d9df0 CP |
2917 | { .compatible = "cdns,pc302-gem", .data = &pc302gem_config }, |
2918 | { .compatible = "cdns,gem", .data = &pc302gem_config }, | |
5c8fe711 | 2919 | { .compatible = "atmel,sama5d2-gem", .data = &sama5d2_config }, |
421d9df0 CP |
2920 | { .compatible = "atmel,sama5d3-gem", .data = &sama5d3_config }, |
2921 | { .compatible = "atmel,sama5d4-gem", .data = &sama5d4_config }, | |
2922 | { .compatible = "cdns,at91rm9200-emac", .data = &emac_config }, | |
2923 | { .compatible = "cdns,emac", .data = &emac_config }, | |
7b61f9c1 | 2924 | { .compatible = "cdns,zynqmp-gem", .data = &zynqmp_config}, |
222ca8e0 | 2925 | { .compatible = "cdns,zynq-gem", .data = &zynq_config }, |
421d9df0 CP |
2926 | { /* sentinel */ } |
2927 | }; | |
2928 | MODULE_DEVICE_TABLE(of, macb_dt_ids); | |
2929 | #endif /* CONFIG_OF */ | |
2930 | ||
2931 | static int macb_probe(struct platform_device *pdev) | |
2932 | { | |
c69618b3 | 2933 | int (*clk_init)(struct platform_device *, struct clk **, |
aead88bd | 2934 | struct clk **, struct clk **, struct clk **) |
c69618b3 | 2935 | = macb_clk_init; |
421d9df0 CP |
2936 | int (*init)(struct platform_device *) = macb_init; |
2937 | struct device_node *np = pdev->dev.of_node; | |
270c499f | 2938 | struct device_node *phy_node; |
421d9df0 | 2939 | const struct macb_config *macb_config = NULL; |
aead88bd | 2940 | struct clk *pclk, *hclk = NULL, *tx_clk = NULL, *rx_clk = NULL; |
421d9df0 CP |
2941 | unsigned int queue_mask, num_queues; |
2942 | struct macb_platform_data *pdata; | |
f2ce8a9e | 2943 | bool native_io; |
421d9df0 CP |
2944 | struct phy_device *phydev; |
2945 | struct net_device *dev; | |
2946 | struct resource *regs; | |
2947 | void __iomem *mem; | |
2948 | const char *mac; | |
2949 | struct macb *bp; | |
2950 | int err; | |
2951 | ||
f2ce8a9e AS |
2952 | regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
2953 | mem = devm_ioremap_resource(&pdev->dev, regs); | |
2954 | if (IS_ERR(mem)) | |
2955 | return PTR_ERR(mem); | |
2956 | ||
c69618b3 NF |
2957 | if (np) { |
2958 | const struct of_device_id *match; | |
2959 | ||
2960 | match = of_match_node(macb_dt_ids, np); | |
2961 | if (match && match->data) { | |
2962 | macb_config = match->data; | |
2963 | clk_init = macb_config->clk_init; | |
2964 | init = macb_config->init; | |
2965 | } | |
2966 | } | |
2967 | ||
aead88bd | 2968 | err = clk_init(pdev, &pclk, &hclk, &tx_clk, &rx_clk); |
c69618b3 NF |
2969 | if (err) |
2970 | return err; | |
2971 | ||
f2ce8a9e | 2972 | native_io = hw_is_native_io(mem); |
421d9df0 | 2973 | |
f2ce8a9e | 2974 | macb_probe_queues(mem, native_io, &queue_mask, &num_queues); |
421d9df0 | 2975 | dev = alloc_etherdev_mq(sizeof(*bp), num_queues); |
c69618b3 NF |
2976 | if (!dev) { |
2977 | err = -ENOMEM; | |
2978 | goto err_disable_clocks; | |
2979 | } | |
421d9df0 CP |
2980 | |
2981 | dev->base_addr = regs->start; | |
2982 | ||
2983 | SET_NETDEV_DEV(dev, &pdev->dev); | |
2984 | ||
2985 | bp = netdev_priv(dev); | |
2986 | bp->pdev = pdev; | |
2987 | bp->dev = dev; | |
2988 | bp->regs = mem; | |
f2ce8a9e AS |
2989 | bp->native_io = native_io; |
2990 | if (native_io) { | |
7a6e0706 DM |
2991 | bp->macb_reg_readl = hw_readl_native; |
2992 | bp->macb_reg_writel = hw_writel_native; | |
f2ce8a9e | 2993 | } else { |
7a6e0706 DM |
2994 | bp->macb_reg_readl = hw_readl; |
2995 | bp->macb_reg_writel = hw_writel; | |
f2ce8a9e | 2996 | } |
421d9df0 | 2997 | bp->num_queues = num_queues; |
bfa0914a | 2998 | bp->queue_mask = queue_mask; |
c69618b3 NF |
2999 | if (macb_config) |
3000 | bp->dma_burst_length = macb_config->dma_burst_length; | |
3001 | bp->pclk = pclk; | |
3002 | bp->hclk = hclk; | |
3003 | bp->tx_clk = tx_clk; | |
aead88bd | 3004 | bp->rx_clk = rx_clk; |
f36dbe6a | 3005 | if (macb_config) |
98b5a0f4 | 3006 | bp->jumbo_max_len = macb_config->jumbo_max_len; |
98b5a0f4 | 3007 | |
3e2a5e15 | 3008 | bp->wol = 0; |
7c4a1d0c | 3009 | if (of_get_property(np, "magic-packet", NULL)) |
3e2a5e15 SP |
3010 | bp->wol |= MACB_WOL_HAS_MAGIC_PACKET; |
3011 | device_init_wakeup(&pdev->dev, bp->wol & MACB_WOL_HAS_MAGIC_PACKET); | |
3012 | ||
fff8019a HK |
3013 | #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT |
3014 | if (GEM_BFEXT(DBWDEF, gem_readl(bp, DCFG1)) > GEM_DBW32) | |
3015 | dma_set_mask(&pdev->dev, DMA_BIT_MASK(44)); | |
3016 | #endif | |
3017 | ||
421d9df0 CP |
3018 | spin_lock_init(&bp->lock); |
3019 | ||
ad78347f | 3020 | /* setup capabilities */ |
f6970505 NF |
3021 | macb_configure_caps(bp, macb_config); |
3022 | ||
421d9df0 CP |
3023 | platform_set_drvdata(pdev, dev); |
3024 | ||
3025 | dev->irq = platform_get_irq(pdev, 0); | |
c69618b3 NF |
3026 | if (dev->irq < 0) { |
3027 | err = dev->irq; | |
b22ae0b4 | 3028 | goto err_out_free_netdev; |
c69618b3 | 3029 | } |
421d9df0 CP |
3030 | |
3031 | mac = of_get_mac_address(np); | |
50907043 | 3032 | if (mac) |
eefb52d1 | 3033 | ether_addr_copy(bp->dev->dev_addr, mac); |
50907043 | 3034 | else |
fb97a846 JCPV |
3035 | macb_get_hwaddr(bp); |
3036 | ||
5833e052 | 3037 | /* Power up the PHY if there is a GPIO reset */ |
270c499f GC |
3038 | phy_node = of_get_next_available_child(np, NULL); |
3039 | if (phy_node) { | |
3040 | int gpio = of_get_named_gpio(phy_node, "reset-gpios", 0); | |
64ec42fe | 3041 | |
0e3e7999 | 3042 | if (gpio_is_valid(gpio)) { |
270c499f | 3043 | bp->reset_gpio = gpio_to_desc(gpio); |
0e3e7999 CK |
3044 | gpiod_direction_output(bp->reset_gpio, 1); |
3045 | } | |
270c499f GC |
3046 | } |
3047 | of_node_put(phy_node); | |
5833e052 | 3048 | |
421d9df0 | 3049 | err = of_get_phy_mode(np); |
fb97a846 | 3050 | if (err < 0) { |
c607a0d9 | 3051 | pdata = dev_get_platdata(&pdev->dev); |
fb97a846 JCPV |
3052 | if (pdata && pdata->is_rmii) |
3053 | bp->phy_interface = PHY_INTERFACE_MODE_RMII; | |
3054 | else | |
3055 | bp->phy_interface = PHY_INTERFACE_MODE_MII; | |
3056 | } else { | |
3057 | bp->phy_interface = err; | |
3058 | } | |
6c36a707 | 3059 | |
421d9df0 CP |
3060 | /* IP specific init */ |
3061 | err = init(pdev); | |
3062 | if (err) | |
3063 | goto err_out_free_netdev; | |
89e5785f | 3064 | |
cf669660 FF |
3065 | err = macb_mii_init(bp); |
3066 | if (err) | |
3067 | goto err_out_free_netdev; | |
3068 | ||
0a91281e | 3069 | phydev = dev->phydev; |
cf669660 FF |
3070 | |
3071 | netif_carrier_off(dev); | |
3072 | ||
89e5785f HS |
3073 | err = register_netdev(dev); |
3074 | if (err) { | |
3075 | dev_err(&pdev->dev, "Cannot register net device, aborting.\n"); | |
cf669660 | 3076 | goto err_out_unregister_mdio; |
89e5785f HS |
3077 | } |
3078 | ||
cf669660 | 3079 | phy_attached_info(phydev); |
03fc4721 | 3080 | |
5879823f BS |
3081 | netdev_info(dev, "Cadence %s rev 0x%08x at 0x%08lx irq %d (%pM)\n", |
3082 | macb_is_gem(bp) ? "GEM" : "MACB", macb_readl(bp, MID), | |
3083 | dev->base_addr, dev->irq, dev->dev_addr); | |
89e5785f HS |
3084 | |
3085 | return 0; | |
3086 | ||
cf669660 | 3087 | err_out_unregister_mdio: |
0a91281e | 3088 | phy_disconnect(dev->phydev); |
cf669660 FF |
3089 | mdiobus_unregister(bp->mii_bus); |
3090 | mdiobus_free(bp->mii_bus); | |
3091 | ||
3092 | /* Shutdown the PHY if there is a GPIO reset */ | |
3093 | if (bp->reset_gpio) | |
3094 | gpiod_set_value(bp->reset_gpio, 0); | |
421d9df0 | 3095 | |
cf250de0 | 3096 | err_out_free_netdev: |
02c958dd | 3097 | free_netdev(dev); |
421d9df0 | 3098 | |
c69618b3 NF |
3099 | err_disable_clocks: |
3100 | clk_disable_unprepare(tx_clk); | |
3101 | clk_disable_unprepare(hclk); | |
3102 | clk_disable_unprepare(pclk); | |
aead88bd | 3103 | clk_disable_unprepare(rx_clk); |
c69618b3 | 3104 | |
89e5785f HS |
3105 | return err; |
3106 | } | |
3107 | ||
9e86d766 | 3108 | static int macb_remove(struct platform_device *pdev) |
89e5785f HS |
3109 | { |
3110 | struct net_device *dev; | |
3111 | struct macb *bp; | |
3112 | ||
3113 | dev = platform_get_drvdata(pdev); | |
3114 | ||
3115 | if (dev) { | |
3116 | bp = netdev_priv(dev); | |
0a91281e PR |
3117 | if (dev->phydev) |
3118 | phy_disconnect(dev->phydev); | |
298cf9be | 3119 | mdiobus_unregister(bp->mii_bus); |
298cf9be | 3120 | mdiobus_free(bp->mii_bus); |
5833e052 GC |
3121 | |
3122 | /* Shutdown the PHY if there is a GPIO reset */ | |
0e3e7999 CK |
3123 | if (bp->reset_gpio) |
3124 | gpiod_set_value(bp->reset_gpio, 0); | |
5833e052 | 3125 | |
89e5785f | 3126 | unregister_netdev(dev); |
93b31f48 | 3127 | clk_disable_unprepare(bp->tx_clk); |
ace58010 | 3128 | clk_disable_unprepare(bp->hclk); |
ace58010 | 3129 | clk_disable_unprepare(bp->pclk); |
aead88bd | 3130 | clk_disable_unprepare(bp->rx_clk); |
e965be7d | 3131 | free_netdev(dev); |
89e5785f HS |
3132 | } |
3133 | ||
3134 | return 0; | |
3135 | } | |
3136 | ||
d23823dd | 3137 | static int __maybe_unused macb_suspend(struct device *dev) |
c1f598fd | 3138 | { |
0dfc3e18 | 3139 | struct platform_device *pdev = to_platform_device(dev); |
c1f598fd HS |
3140 | struct net_device *netdev = platform_get_drvdata(pdev); |
3141 | struct macb *bp = netdev_priv(netdev); | |
3142 | ||
03fc4721 | 3143 | netif_carrier_off(netdev); |
c1f598fd HS |
3144 | netif_device_detach(netdev); |
3145 | ||
3e2a5e15 SP |
3146 | if (bp->wol & MACB_WOL_ENABLED) { |
3147 | macb_writel(bp, IER, MACB_BIT(WOL)); | |
3148 | macb_writel(bp, WOL, MACB_BIT(MAG)); | |
3149 | enable_irq_wake(bp->queues[0].irq); | |
3150 | } else { | |
3151 | clk_disable_unprepare(bp->tx_clk); | |
3152 | clk_disable_unprepare(bp->hclk); | |
3153 | clk_disable_unprepare(bp->pclk); | |
aead88bd | 3154 | clk_disable_unprepare(bp->rx_clk); |
3e2a5e15 | 3155 | } |
c1f598fd HS |
3156 | |
3157 | return 0; | |
3158 | } | |
3159 | ||
d23823dd | 3160 | static int __maybe_unused macb_resume(struct device *dev) |
c1f598fd | 3161 | { |
0dfc3e18 | 3162 | struct platform_device *pdev = to_platform_device(dev); |
c1f598fd HS |
3163 | struct net_device *netdev = platform_get_drvdata(pdev); |
3164 | struct macb *bp = netdev_priv(netdev); | |
3165 | ||
3e2a5e15 SP |
3166 | if (bp->wol & MACB_WOL_ENABLED) { |
3167 | macb_writel(bp, IDR, MACB_BIT(WOL)); | |
3168 | macb_writel(bp, WOL, 0); | |
3169 | disable_irq_wake(bp->queues[0].irq); | |
3170 | } else { | |
3171 | clk_prepare_enable(bp->pclk); | |
3172 | clk_prepare_enable(bp->hclk); | |
3173 | clk_prepare_enable(bp->tx_clk); | |
aead88bd | 3174 | clk_prepare_enable(bp->rx_clk); |
3e2a5e15 | 3175 | } |
c1f598fd HS |
3176 | |
3177 | netif_device_attach(netdev); | |
3178 | ||
3179 | return 0; | |
3180 | } | |
c1f598fd | 3181 | |
0dfc3e18 SB |
3182 | static SIMPLE_DEV_PM_OPS(macb_pm_ops, macb_suspend, macb_resume); |
3183 | ||
89e5785f | 3184 | static struct platform_driver macb_driver = { |
9e86d766 NR |
3185 | .probe = macb_probe, |
3186 | .remove = macb_remove, | |
89e5785f HS |
3187 | .driver = { |
3188 | .name = "macb", | |
fb97a846 | 3189 | .of_match_table = of_match_ptr(macb_dt_ids), |
0dfc3e18 | 3190 | .pm = &macb_pm_ops, |
89e5785f HS |
3191 | }, |
3192 | }; | |
3193 | ||
9e86d766 | 3194 | module_platform_driver(macb_driver); |
89e5785f HS |
3195 | |
3196 | MODULE_LICENSE("GPL"); | |
f75ba50b | 3197 | MODULE_DESCRIPTION("Cadence MACB/GEM Ethernet driver"); |
e05503ef | 3198 | MODULE_AUTHOR("Haavard Skinnemoen (Atmel)"); |
72abb461 | 3199 | MODULE_ALIAS("platform:macb"); |