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f21fb3ed RV |
1 | /********************************************************************** |
2 | * Author: Cavium, Inc. | |
3 | * | |
4 | * Contact: support@cavium.com | |
5 | * Please include "LiquidIO" in the subject. | |
6 | * | |
7 | * Copyright (c) 2003-2015 Cavium, Inc. | |
8 | * | |
9 | * This file is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License, Version 2, as | |
11 | * published by the Free Software Foundation. | |
12 | * | |
13 | * This file is distributed in the hope that it will be useful, but | |
14 | * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty | |
15 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or | |
16 | * NONINFRINGEMENT. See the GNU General Public License for more | |
17 | * details. | |
18 | * | |
19 | * This file may also be available under a different license from Cavium. | |
20 | * Contact Cavium, Inc. for more information | |
21 | **********************************************************************/ | |
22 | ||
23 | /*! \file octeon_config.h | |
24 | * \brief Host Driver: Configuration data structures for the host driver. | |
25 | */ | |
26 | ||
27 | #ifndef __OCTEON_CONFIG_H__ | |
28 | #define __OCTEON_CONFIG_H__ | |
29 | ||
30 | /*--------------------------CONFIG VALUES------------------------*/ | |
31 | ||
32 | /* The following macros affect the way the driver data structures | |
33 | * are generated for Octeon devices. | |
34 | * They can be modified. | |
35 | */ | |
36 | ||
37 | /* Maximum octeon devices defined as MAX_OCTEON_NICIF to support | |
38 | * multiple(<= MAX_OCTEON_NICIF) Miniports | |
39 | */ | |
63da8404 | 40 | #define MAX_OCTEON_NICIF 128 |
f21fb3ed RV |
41 | #define MAX_OCTEON_DEVICES MAX_OCTEON_NICIF |
42 | #define MAX_OCTEON_LINKS MAX_OCTEON_NICIF | |
43 | #define MAX_OCTEON_MULTICAST_ADDR 32 | |
44 | ||
45 | /* CN6xxx IQ configuration macros */ | |
46 | #define CN6XXX_MAX_INPUT_QUEUES 32 | |
47 | #define CN6XXX_MAX_IQ_DESCRIPTORS 2048 | |
48 | #define CN6XXX_DB_MIN 1 | |
49 | #define CN6XXX_DB_MAX 8 | |
50 | #define CN6XXX_DB_TIMEOUT 1 | |
51 | ||
52 | /* CN6xxx OQ configuration macros */ | |
53 | #define CN6XXX_MAX_OUTPUT_QUEUES 32 | |
54 | #define CN6XXX_MAX_OQ_DESCRIPTORS 2048 | |
55 | #define CN6XXX_OQ_BUF_SIZE 1536 | |
56 | #define CN6XXX_OQ_PKTSPER_INTR ((CN6XXX_MAX_OQ_DESCRIPTORS < 512) ? \ | |
57 | (CN6XXX_MAX_OQ_DESCRIPTORS / 4) : 128) | |
58 | #define CN6XXX_OQ_REFIL_THRESHOLD ((CN6XXX_MAX_OQ_DESCRIPTORS < 512) ? \ | |
59 | (CN6XXX_MAX_OQ_DESCRIPTORS / 4) : 128) | |
60 | ||
61 | #define CN6XXX_OQ_INTR_PKT 64 | |
62 | #define CN6XXX_OQ_INTR_TIME 100 | |
63 | #define DEFAULT_NUM_NIC_PORTS_66XX 2 | |
64 | #define DEFAULT_NUM_NIC_PORTS_68XX 4 | |
65 | #define DEFAULT_NUM_NIC_PORTS_68XX_210NV 2 | |
66 | ||
e86b1ab6 RV |
67 | /* CN23xx IQ configuration macros */ |
68 | #define CN23XX_MAX_RINGS_PER_PF_PASS_1_0 12 | |
69 | #define CN23XX_MAX_RINGS_PER_PF_PASS_1_1 32 | |
70 | #define CN23XX_MAX_RINGS_PER_PF 64 | |
71 | ||
72 | #define CN23XX_MAX_INPUT_QUEUES CN23XX_MAX_RINGS_PER_PF | |
73 | #define CN23XX_MAX_IQ_DESCRIPTORS 2048 | |
74 | #define CN23XX_DB_MIN 1 | |
75 | #define CN23XX_DB_MAX 8 | |
76 | #define CN23XX_DB_TIMEOUT 1 | |
77 | ||
78 | #define CN23XX_MAX_OUTPUT_QUEUES CN23XX_MAX_RINGS_PER_PF | |
79 | #define CN23XX_MAX_OQ_DESCRIPTORS 2048 | |
80 | #define CN23XX_OQ_BUF_SIZE 1536 | |
81 | #define CN23XX_OQ_PKTSPER_INTR 128 | |
82 | /*#define CAVIUM_ONLY_CN23XX_RX_PERF*/ | |
83 | #define CN23XX_OQ_REFIL_THRESHOLD 128 | |
84 | ||
85 | #define CN23XX_OQ_INTR_PKT 64 | |
86 | #define CN23XX_OQ_INTR_TIME 100 | |
87 | #define DEFAULT_NUM_NIC_PORTS_23XX 1 | |
88 | ||
89 | #define CN23XX_CFG_IO_QUEUES CN23XX_MAX_RINGS_PER_PF | |
90 | /* PEMs count */ | |
91 | #define CN23XX_MAX_MACS 4 | |
92 | ||
93 | #define CN23XX_DEF_IQ_INTR_THRESHOLD 32 | |
94 | #define CN23XX_DEF_IQ_INTR_BYTE_THRESHOLD (64 * 1024) | |
f21fb3ed RV |
95 | /* common OCTEON configuration macros */ |
96 | #define CN6XXX_CFG_IO_QUEUES 32 | |
97 | #define OCTEON_32BYTE_INSTR 32 | |
98 | #define OCTEON_64BYTE_INSTR 64 | |
99 | #define OCTEON_MAX_BASE_IOQ 4 | |
100 | #define OCTEON_OQ_BUFPTR_MODE 0 | |
101 | #define OCTEON_OQ_INFOPTR_MODE 1 | |
102 | ||
103 | #define OCTEON_DMA_INTR_PKT 64 | |
104 | #define OCTEON_DMA_INTR_TIME 1000 | |
105 | ||
106 | #define MAX_TXQS_PER_INTF 8 | |
107 | #define MAX_RXQS_PER_INTF 8 | |
108 | #define DEF_TXQS_PER_INTF 4 | |
109 | #define DEF_RXQS_PER_INTF 4 | |
110 | ||
111 | #define INVALID_IOQ_NO 0xff | |
112 | ||
113 | #define DEFAULT_POW_GRP 0 | |
114 | ||
115 | /* Macros to get octeon config params */ | |
116 | #define CFG_GET_IQ_CFG(cfg) ((cfg)->iq) | |
117 | #define CFG_GET_IQ_MAX_Q(cfg) ((cfg)->iq.max_iqs) | |
118 | #define CFG_GET_IQ_PENDING_LIST_SIZE(cfg) ((cfg)->iq.pending_list_size) | |
119 | #define CFG_GET_IQ_INSTR_TYPE(cfg) ((cfg)->iq.instr_type) | |
120 | #define CFG_GET_IQ_DB_MIN(cfg) ((cfg)->iq.db_min) | |
121 | #define CFG_GET_IQ_DB_TIMEOUT(cfg) ((cfg)->iq.db_timeout) | |
122 | ||
3451b97c RV |
123 | #define CFG_GET_IQ_INTR_PKT(cfg) ((cfg)->iq.iq_intr_pkt) |
124 | #define CFG_SET_IQ_INTR_PKT(cfg, val) (cfg)->iq.iq_intr_pkt = val | |
125 | ||
f21fb3ed RV |
126 | #define CFG_GET_OQ_MAX_Q(cfg) ((cfg)->oq.max_oqs) |
127 | #define CFG_GET_OQ_INFO_PTR(cfg) ((cfg)->oq.info_ptr) | |
128 | #define CFG_GET_OQ_PKTS_PER_INTR(cfg) ((cfg)->oq.pkts_per_intr) | |
129 | #define CFG_GET_OQ_REFILL_THRESHOLD(cfg) ((cfg)->oq.refill_threshold) | |
130 | #define CFG_GET_OQ_INTR_PKT(cfg) ((cfg)->oq.oq_intr_pkt) | |
131 | #define CFG_GET_OQ_INTR_TIME(cfg) ((cfg)->oq.oq_intr_time) | |
132 | #define CFG_SET_OQ_INTR_PKT(cfg, val) (cfg)->oq.oq_intr_pkt = val | |
133 | #define CFG_SET_OQ_INTR_TIME(cfg, val) (cfg)->oq.oq_intr_time = val | |
134 | ||
135 | #define CFG_GET_DMA_INTR_PKT(cfg) ((cfg)->dma.dma_intr_pkt) | |
136 | #define CFG_GET_DMA_INTR_TIME(cfg) ((cfg)->dma.dma_intr_time) | |
137 | #define CFG_GET_NUM_NIC_PORTS(cfg) ((cfg)->num_nic_ports) | |
138 | #define CFG_GET_NUM_DEF_TX_DESCS(cfg) ((cfg)->num_def_tx_descs) | |
139 | #define CFG_GET_NUM_DEF_RX_DESCS(cfg) ((cfg)->num_def_rx_descs) | |
140 | #define CFG_GET_DEF_RX_BUF_SIZE(cfg) ((cfg)->def_rx_buf_size) | |
141 | ||
142 | #define CFG_GET_MAX_TXQS_NIC_IF(cfg, idx) \ | |
143 | ((cfg)->nic_if_cfg[idx].max_txqs) | |
144 | #define CFG_GET_NUM_TXQS_NIC_IF(cfg, idx) \ | |
145 | ((cfg)->nic_if_cfg[idx].num_txqs) | |
146 | #define CFG_GET_MAX_RXQS_NIC_IF(cfg, idx) \ | |
147 | ((cfg)->nic_if_cfg[idx].max_rxqs) | |
148 | #define CFG_GET_NUM_RXQS_NIC_IF(cfg, idx) \ | |
149 | ((cfg)->nic_if_cfg[idx].num_rxqs) | |
150 | #define CFG_GET_NUM_RX_DESCS_NIC_IF(cfg, idx) \ | |
151 | ((cfg)->nic_if_cfg[idx].num_rx_descs) | |
152 | #define CFG_GET_NUM_TX_DESCS_NIC_IF(cfg, idx) \ | |
153 | ((cfg)->nic_if_cfg[idx].num_tx_descs) | |
154 | #define CFG_GET_NUM_RX_BUF_SIZE_NIC_IF(cfg, idx) \ | |
155 | ((cfg)->nic_if_cfg[idx].rx_buf_size) | |
156 | #define CFG_GET_BASE_QUE_NIC_IF(cfg, idx) \ | |
157 | ((cfg)->nic_if_cfg[idx].base_queue) | |
158 | #define CFG_GET_GMXID_NIC_IF(cfg, idx) \ | |
159 | ((cfg)->nic_if_cfg[idx].gmx_port_id) | |
160 | ||
161 | #define CFG_GET_CTRL_Q_GRP(cfg) ((cfg)->misc.ctrlq_grp) | |
162 | #define CFG_GET_HOST_LINK_QUERY_INTERVAL(cfg) \ | |
163 | ((cfg)->misc.host_link_query_interval) | |
164 | #define CFG_GET_OCT_LINK_QUERY_INTERVAL(cfg) \ | |
165 | ((cfg)->misc.oct_link_query_interval) | |
166 | #define CFG_GET_IS_SLI_BP_ON(cfg) ((cfg)->misc.enable_sli_oq_bp) | |
167 | ||
168 | /* Max IOQs per OCTEON Link */ | |
63da8404 | 169 | #define MAX_IOQS_PER_NICIF 64 |
f21fb3ed RV |
170 | |
171 | enum lio_card_type { | |
172 | LIO_210SV = 0, /* Two port, 66xx */ | |
173 | LIO_210NV, /* Two port, 68xx */ | |
e86b1ab6 RV |
174 | LIO_410NV, /* Four port, 68xx */ |
175 | LIO_23XX /* 23xx */ | |
f21fb3ed RV |
176 | }; |
177 | ||
178 | #define LIO_210SV_NAME "210sv" | |
179 | #define LIO_210NV_NAME "210nv" | |
180 | #define LIO_410NV_NAME "410nv" | |
e86b1ab6 | 181 | #define LIO_23XX_NAME "23xx" |
f21fb3ed RV |
182 | |
183 | /** Structure to define the configuration attributes for each Input queue. | |
184 | * Applicable to all Octeon processors | |
185 | **/ | |
186 | struct octeon_iq_config { | |
187 | #ifdef __BIG_ENDIAN_BITFIELD | |
e86b1ab6 RV |
188 | u64 reserved:16; |
189 | ||
190 | /** Tx interrupt packets. Applicable to 23xx only */ | |
191 | u64 iq_intr_pkt:16; | |
f21fb3ed RV |
192 | |
193 | /** Minimum ticks to wait before checking for pending instructions. */ | |
194 | u64 db_timeout:16; | |
195 | ||
196 | /** Minimum number of commands pending to be posted to Octeon | |
197 | * before driver hits the Input queue doorbell. | |
198 | */ | |
199 | u64 db_min:8; | |
200 | ||
201 | /** Command size - 32 or 64 bytes */ | |
202 | u64 instr_type:32; | |
203 | ||
204 | /** Pending list size (usually set to the sum of the size of all Input | |
205 | * queues) | |
206 | */ | |
207 | u64 pending_list_size:32; | |
208 | ||
209 | /* Max number of IQs available */ | |
210 | u64 max_iqs:8; | |
211 | #else | |
212 | /* Max number of IQs available */ | |
213 | u64 max_iqs:8; | |
214 | ||
215 | /** Pending list size (usually set to the sum of the size of all Input | |
216 | * queues) | |
217 | */ | |
218 | u64 pending_list_size:32; | |
219 | ||
220 | /** Command size - 32 or 64 bytes */ | |
221 | u64 instr_type:32; | |
222 | ||
223 | /** Minimum number of commands pending to be posted to Octeon | |
224 | * before driver hits the Input queue doorbell. | |
225 | */ | |
226 | u64 db_min:8; | |
227 | ||
228 | /** Minimum ticks to wait before checking for pending instructions. */ | |
229 | u64 db_timeout:16; | |
230 | ||
e86b1ab6 RV |
231 | /** Tx interrupt packets. Applicable to 23xx only */ |
232 | u64 iq_intr_pkt:16; | |
233 | ||
234 | u64 reserved:16; | |
f21fb3ed RV |
235 | #endif |
236 | }; | |
237 | ||
238 | /** Structure to define the configuration attributes for each Output queue. | |
239 | * Applicable to all Octeon processors | |
240 | **/ | |
241 | struct octeon_oq_config { | |
242 | #ifdef __BIG_ENDIAN_BITFIELD | |
243 | u64 reserved:16; | |
244 | ||
245 | u64 pkts_per_intr:16; | |
246 | ||
247 | /** Interrupt Coalescing (Time Interval). Octeon will interrupt the | |
248 | * host if atleast one packet was sent in the time interval specified | |
249 | * by this field. The driver uses time interval interrupt coalescing | |
250 | * by default. The time is specified in microseconds. | |
251 | */ | |
252 | u64 oq_intr_time:16; | |
253 | ||
254 | /** Interrupt Coalescing (Packet Count). Octeon will interrupt the host | |
255 | * only if it sent as many packets as specified by this field. | |
256 | * The driver | |
257 | * usually does not use packet count interrupt coalescing. | |
258 | */ | |
259 | u64 oq_intr_pkt:16; | |
260 | ||
261 | /** The number of buffers that were consumed during packet processing by | |
262 | * the driver on this Output queue before the driver attempts to | |
263 | * replenish | |
264 | * the descriptor ring with new buffers. | |
265 | */ | |
266 | u64 refill_threshold:16; | |
267 | ||
a2c64b67 | 268 | /** If set, the Output queue uses info-pointer mode. (Default: 1) */ |
f21fb3ed RV |
269 | u64 info_ptr:32; |
270 | ||
271 | /* Max number of OQs available */ | |
272 | u64 max_oqs:8; | |
273 | ||
274 | #else | |
275 | /* Max number of OQs available */ | |
276 | u64 max_oqs:8; | |
277 | ||
a2c64b67 | 278 | /** If set, the Output queue uses info-pointer mode. (Default: 1) */ |
f21fb3ed RV |
279 | u64 info_ptr:32; |
280 | ||
281 | /** The number of buffers that were consumed during packet processing by | |
282 | * the driver on this Output queue before the driver attempts to | |
283 | * replenish | |
284 | * the descriptor ring with new buffers. | |
285 | */ | |
286 | u64 refill_threshold:16; | |
287 | ||
288 | /** Interrupt Coalescing (Packet Count). Octeon will interrupt the host | |
289 | * only if it sent as many packets as specified by this field. | |
290 | * The driver | |
291 | * usually does not use packet count interrupt coalescing. | |
292 | */ | |
293 | u64 oq_intr_pkt:16; | |
294 | ||
295 | /** Interrupt Coalescing (Time Interval). Octeon will interrupt the | |
296 | * host if atleast one packet was sent in the time interval specified | |
297 | * by this field. The driver uses time interval interrupt coalescing | |
298 | * by default. The time is specified in microseconds. | |
299 | */ | |
300 | u64 oq_intr_time:16; | |
301 | ||
302 | u64 pkts_per_intr:16; | |
303 | ||
304 | u64 reserved:16; | |
305 | #endif | |
306 | ||
307 | }; | |
308 | ||
309 | /** This structure conatins the NIC link configuration attributes, | |
310 | * common for all the OCTEON Modles. | |
311 | */ | |
312 | struct octeon_nic_if_config { | |
313 | #ifdef __BIG_ENDIAN_BITFIELD | |
314 | u64 reserved:56; | |
315 | ||
316 | u64 base_queue:16; | |
317 | ||
318 | u64 gmx_port_id:8; | |
319 | ||
320 | /* SKB size, We need not change buf size even for Jumbo frames. | |
321 | * Octeon can send jumbo frames in 4 consecutive descriptors, | |
322 | */ | |
323 | u64 rx_buf_size:16; | |
324 | ||
325 | /* Num of desc for tx rings */ | |
326 | u64 num_tx_descs:16; | |
327 | ||
328 | /* Num of desc for rx rings */ | |
329 | u64 num_rx_descs:16; | |
330 | ||
331 | /* Actual configured value. Range could be: 1...max_rxqs */ | |
332 | u64 num_rxqs:16; | |
333 | ||
334 | /* Max Rxqs: Half for each of the two ports :max_oq/2 */ | |
335 | u64 max_rxqs:16; | |
336 | ||
337 | /* Actual configured value. Range could be: 1...max_txqs */ | |
338 | u64 num_txqs:16; | |
339 | ||
340 | /* Max Txqs: Half for each of the two ports :max_iq/2 */ | |
341 | u64 max_txqs:16; | |
342 | #else | |
343 | /* Max Txqs: Half for each of the two ports :max_iq/2 */ | |
344 | u64 max_txqs:16; | |
345 | ||
346 | /* Actual configured value. Range could be: 1...max_txqs */ | |
347 | u64 num_txqs:16; | |
348 | ||
349 | /* Max Rxqs: Half for each of the two ports :max_oq/2 */ | |
350 | u64 max_rxqs:16; | |
351 | ||
352 | /* Actual configured value. Range could be: 1...max_rxqs */ | |
353 | u64 num_rxqs:16; | |
354 | ||
355 | /* Num of desc for rx rings */ | |
356 | u64 num_rx_descs:16; | |
357 | ||
358 | /* Num of desc for tx rings */ | |
359 | u64 num_tx_descs:16; | |
360 | ||
361 | /* SKB size, We need not change buf size even for Jumbo frames. | |
362 | * Octeon can send jumbo frames in 4 consecutive descriptors, | |
363 | */ | |
364 | u64 rx_buf_size:16; | |
365 | ||
366 | u64 gmx_port_id:8; | |
367 | ||
368 | u64 base_queue:16; | |
369 | ||
370 | u64 reserved:56; | |
371 | #endif | |
372 | ||
373 | }; | |
374 | ||
375 | /** Structure to define the configuration attributes for meta data. | |
376 | * Applicable to all Octeon processors. | |
377 | */ | |
378 | ||
379 | struct octeon_misc_config { | |
380 | #ifdef __BIG_ENDIAN_BITFIELD | |
381 | /** Host link status polling period */ | |
382 | u64 host_link_query_interval:32; | |
383 | /** Oct link status polling period */ | |
384 | u64 oct_link_query_interval:32; | |
385 | ||
386 | u64 enable_sli_oq_bp:1; | |
387 | /** Control IQ Group */ | |
388 | u64 ctrlq_grp:4; | |
389 | #else | |
390 | /** Control IQ Group */ | |
391 | u64 ctrlq_grp:4; | |
392 | /** BP for SLI OQ */ | |
393 | u64 enable_sli_oq_bp:1; | |
394 | /** Host link status polling period */ | |
395 | u64 oct_link_query_interval:32; | |
396 | /** Oct link status polling period */ | |
397 | u64 host_link_query_interval:32; | |
398 | #endif | |
399 | }; | |
400 | ||
401 | /** Structure to define the configuration for all OCTEON processors. */ | |
402 | struct octeon_config { | |
403 | u16 card_type; | |
404 | char *card_name; | |
405 | ||
406 | /** Input Queue attributes. */ | |
407 | struct octeon_iq_config iq; | |
408 | ||
409 | /** Output Queue attributes. */ | |
410 | struct octeon_oq_config oq; | |
411 | ||
412 | /** NIC Port Configuration */ | |
413 | struct octeon_nic_if_config nic_if_cfg[MAX_OCTEON_NICIF]; | |
414 | ||
415 | /** Miscellaneous attributes */ | |
416 | struct octeon_misc_config misc; | |
417 | ||
418 | int num_nic_ports; | |
419 | ||
420 | int num_def_tx_descs; | |
421 | ||
422 | /* Num of desc for rx rings */ | |
423 | int num_def_rx_descs; | |
424 | ||
425 | int def_rx_buf_size; | |
426 | ||
427 | }; | |
428 | ||
429 | /* The following config values are fixed and should not be modified. */ | |
430 | ||
431 | /* Maximum address space to be mapped for Octeon's BAR1 index-based access. */ | |
432 | #define MAX_BAR1_MAP_INDEX 2 | |
433 | #define OCTEON_BAR1_ENTRY_SIZE (4 * 1024 * 1024) | |
434 | ||
435 | /* BAR1 Index 0 to (MAX_BAR1_MAP_INDEX - 1) for normal mapped memory access. | |
436 | * Bar1 register at MAX_BAR1_MAP_INDEX used by driver for dynamic access. | |
437 | */ | |
438 | #define MAX_BAR1_IOREMAP_SIZE ((MAX_BAR1_MAP_INDEX + 1) * \ | |
439 | OCTEON_BAR1_ENTRY_SIZE) | |
440 | ||
441 | /* Response lists - 1 ordered, 1 unordered-blocking, 1 unordered-nonblocking | |
442 | * NoResponse Lists are now maintained with each IQ. (Dec' 2007). | |
443 | */ | |
444 | #define MAX_RESPONSE_LISTS 4 | |
445 | ||
446 | /* Opcode hash bits. The opcode is hashed on the lower 6-bits to lookup the | |
447 | * dispatch table. | |
448 | */ | |
449 | #define OPCODE_MASK_BITS 6 | |
450 | ||
451 | /* Mask for the 6-bit lookup hash */ | |
452 | #define OCTEON_OPCODE_MASK 0x3f | |
453 | ||
454 | /* Size of the dispatch table. The 6-bit hash can index into 2^6 entries */ | |
455 | #define DISPATCH_LIST_SIZE BIT(OPCODE_MASK_BITS) | |
456 | ||
457 | /* Maximum number of Octeon Instruction (command) queues */ | |
e86b1ab6 RV |
458 | #define MAX_OCTEON_INSTR_QUEUES(oct) \ |
459 | (OCTEON_CN23XX_PF(oct) ? CN23XX_MAX_INPUT_QUEUES : \ | |
460 | CN6XXX_MAX_INPUT_QUEUES) | |
f21fb3ed | 461 | |
e86b1ab6 RV |
462 | /* Maximum number of Octeon Instruction (command) queues */ |
463 | #define MAX_OCTEON_OUTPUT_QUEUES(oct) \ | |
464 | (OCTEON_CN23XX_PF(oct) ? CN23XX_MAX_OUTPUT_QUEUES : \ | |
465 | CN6XXX_MAX_OUTPUT_QUEUES) | |
f21fb3ed | 466 | |
e86b1ab6 RV |
467 | #define MAX_POSSIBLE_OCTEON_INSTR_QUEUES CN23XX_MAX_INPUT_QUEUES |
468 | #define MAX_POSSIBLE_OCTEON_OUTPUT_QUEUES CN23XX_MAX_OUTPUT_QUEUES | |
f21fb3ed | 469 | #endif /* __OCTEON_CONFIG_H__ */ |