projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 4863dea3 SG |
1 | /* |
| 2 | * Copyright (C) 2015 Cavium, Inc. | |
| 3 | * | |
| 4 | * This program is free software; you can redistribute it and/or modify it | |
| 5 | * under the terms of version 2 of the GNU General Public License | |
| 6 | * as published by the Free Software Foundation. | |
| 7 | */ | |
| 8 | ||
| 9 | #ifndef NIC_H | |
| 10 | #define NIC_H | |
| 11 | ||
| 12 | #include <linux/netdevice.h> | |
| 13 | #include <linux/interrupt.h> | |
| d768b678 | 14 | #include <linux/pci.h> |
| 4863dea3 SG |
15 | #include "thunder_bgx.h" |
| 16 | ||
| 17 | /* PCI device IDs */ | |
| 18 | #define PCI_DEVICE_ID_THUNDER_NIC_PF 0xA01E | |
| 19 | #define PCI_DEVICE_ID_THUNDER_PASS1_NIC_VF 0x0011 | |
| 20 | #define PCI_DEVICE_ID_THUNDER_NIC_VF 0xA034 | |
| 21 | #define PCI_DEVICE_ID_THUNDER_BGX 0xA026 | |
| 22 | ||
| 23 | /* PCI BAR nos */ | |
| 24 | #define PCI_CFG_REG_BAR_NUM 0 | |
| 25 | #define PCI_MSIX_REG_BAR_NUM 4 | |
| 26 | ||
| 27 | /* NIC SRIOV VF count */ | |
| 28 | #define MAX_NUM_VFS_SUPPORTED 128 | |
| 29 | #define DEFAULT_NUM_VF_ENABLED 8 | |
| 30 | ||
| 31 | #define NIC_TNS_BYPASS_MODE 0 | |
| 32 | #define NIC_TNS_MODE 1 | |
| 33 | ||
| 34 | /* NIC priv flags */ | |
| 35 | #define NIC_SRIOV_ENABLED BIT(0) | |
| 36 | ||
| 37 | /* Min/Max packet size */ | |
| 38 | #define NIC_HW_MIN_FRS 64 | |
| 39 | #define NIC_HW_MAX_FRS 9200 /* 9216 max packet including FCS */ | |
| 40 | ||
| 41 | /* Max pkinds */ | |
| 42 | #define NIC_MAX_PKIND 16 | |
| 43 | ||
| 44 | /* Rx Channels */ | |
| 45 | /* Receive channel configuration in TNS bypass mode | |
| 46 | * Below is configuration in TNS bypass mode | |
| 47 | * BGX0-LMAC0-CHAN0 - VNIC CHAN0 | |
| 48 | * BGX0-LMAC1-CHAN0 - VNIC CHAN16 | |
| 49 | * ... | |
| 50 | * BGX1-LMAC0-CHAN0 - VNIC CHAN128 | |
| 51 | * ... | |
| 52 | * BGX1-LMAC3-CHAN0 - VNIC CHAN174 | |
| 53 | */ | |
| 54 | #define NIC_INTF_COUNT 2 /* Interfaces btw VNIC and TNS/BGX */ | |
| 55 | #define NIC_CHANS_PER_INF 128 | |
| 56 | #define NIC_MAX_CHANS (NIC_INTF_COUNT * NIC_CHANS_PER_INF) | |
| 57 | #define NIC_CPI_COUNT 2048 /* No of channel parse indices */ | |
| 58 | ||
| 59 | /* TNS bypass mode: 1-1 mapping between VNIC and BGX:LMAC */ | |
| 60 | #define NIC_MAX_BGX MAX_BGX_PER_CN88XX | |
| 61 | #define NIC_CPI_PER_BGX (NIC_CPI_COUNT / NIC_MAX_BGX) | |
| 62 | #define NIC_MAX_CPI_PER_LMAC 64 /* Max when CPI_ALG is IP diffserv */ | |
| 63 | #define NIC_RSSI_PER_BGX (NIC_RSSI_COUNT / NIC_MAX_BGX) | |
| 64 | ||
| 65 | /* Tx scheduling */ | |
| 66 | #define NIC_MAX_TL4 1024 | |
| 67 | #define NIC_MAX_TL4_SHAPERS 256 /* 1 shaper for 4 TL4s */ | |
| 68 | #define NIC_MAX_TL3 256 | |
| 69 | #define NIC_MAX_TL3_SHAPERS 64 /* 1 shaper for 4 TL3s */ | |
| 70 | #define NIC_MAX_TL2 64 | |
| 71 | #define NIC_MAX_TL2_SHAPERS 2 /* 1 shaper for 32 TL2s */ | |
| 72 | #define NIC_MAX_TL1 2 | |
| 73 | ||
| 74 | /* TNS bypass mode */ | |
| 75 | #define NIC_TL2_PER_BGX 32 | |
| 76 | #define NIC_TL4_PER_BGX (NIC_MAX_TL4 / NIC_MAX_BGX) | |
| 77 | #define NIC_TL4_PER_LMAC (NIC_MAX_TL4 / NIC_CHANS_PER_INF) | |
| 78 | ||
| 79 | /* NIC VF Interrupts */ | |
| 80 | #define NICVF_INTR_CQ 0 | |
| 81 | #define NICVF_INTR_SQ 1 | |
| 82 | #define NICVF_INTR_RBDR 2 | |
| 83 | #define NICVF_INTR_PKT_DROP 3 | |
| 84 | #define NICVF_INTR_TCP_TIMER 4 | |
| 85 | #define NICVF_INTR_MBOX 5 | |
| 86 | #define NICVF_INTR_QS_ERR 6 | |
| 87 | ||
| 88 | #define NICVF_INTR_CQ_SHIFT 0 | |
| 89 | #define NICVF_INTR_SQ_SHIFT 8 | |
| 90 | #define NICVF_INTR_RBDR_SHIFT 16 | |
| 91 | #define NICVF_INTR_PKT_DROP_SHIFT 20 | |
| 92 | #define NICVF_INTR_TCP_TIMER_SHIFT 21 | |
| 93 | #define NICVF_INTR_MBOX_SHIFT 22 | |
| 94 | #define NICVF_INTR_QS_ERR_SHIFT 23 | |
| 95 | ||
| 96 | #define NICVF_INTR_CQ_MASK (0xFF << NICVF_INTR_CQ_SHIFT) | |
| 97 | #define NICVF_INTR_SQ_MASK (0xFF << NICVF_INTR_SQ_SHIFT) | |
| 98 | #define NICVF_INTR_RBDR_MASK (0x03 << NICVF_INTR_RBDR_SHIFT) | |
| 99 | #define NICVF_INTR_PKT_DROP_MASK BIT(NICVF_INTR_PKT_DROP_SHIFT) | |
| 100 | #define NICVF_INTR_TCP_TIMER_MASK BIT(NICVF_INTR_TCP_TIMER_SHIFT) | |
| 101 | #define NICVF_INTR_MBOX_MASK BIT(NICVF_INTR_MBOX_SHIFT) | |
| 102 | #define NICVF_INTR_QS_ERR_MASK BIT(NICVF_INTR_QS_ERR_SHIFT) | |
| 103 | ||
| 104 | /* MSI-X interrupts */ | |
| 105 | #define NIC_PF_MSIX_VECTORS 10 | |
| 106 | #define NIC_VF_MSIX_VECTORS 20 | |
| 107 | ||
| 108 | #define NIC_PF_INTR_ID_ECC0_SBE 0 | |
| 109 | #define NIC_PF_INTR_ID_ECC0_DBE 1 | |
| 110 | #define NIC_PF_INTR_ID_ECC1_SBE 2 | |
| 111 | #define NIC_PF_INTR_ID_ECC1_DBE 3 | |
| 112 | #define NIC_PF_INTR_ID_ECC2_SBE 4 | |
| 113 | #define NIC_PF_INTR_ID_ECC2_DBE 5 | |
| 114 | #define NIC_PF_INTR_ID_ECC3_SBE 6 | |
| 115 | #define NIC_PF_INTR_ID_ECC3_DBE 7 | |
| 116 | #define NIC_PF_INTR_ID_MBOX0 8 | |
| 117 | #define NIC_PF_INTR_ID_MBOX1 9 | |
| 118 | ||
| 119 | /* Global timer for CQ timer thresh interrupts | |
| 120 | * Calculated for SCLK of 700Mhz | |
| 121 | * value written should be a 1/16th of what is expected | |
| 122 | * | |
| 123 | * 1 tick per 0.05usec = value of 2.2 | |
| 124 | * This 10% would be covered in CQ timer thresh value | |
| 125 | */ | |
| 126 | #define NICPF_CLK_PER_INT_TICK 2 | |
| 127 | ||
| 3d7a8aaa SG |
128 | /* Time to wait before we decide that a SQ is stuck. |
| 129 | * | |
| 130 | * Since both pkt rx and tx notifications are done with same CQ, | |
| 131 | * when packets are being received at very high rate (eg: L2 forwarding) | |
| 132 | * then freeing transmitted skbs will be delayed and watchdog | |
| 133 | * will kick in, resetting interface. Hence keeping this value high. | |
| 134 | */ | |
| 135 | #define NICVF_TX_TIMEOUT (50 * HZ) | |
| 136 | ||
| 4863dea3 SG |
137 | struct nicvf_cq_poll { |
| 138 | u8 cq_idx; /* Completion queue index */ | |
| 139 | struct napi_struct napi; | |
| 140 | }; | |
| 141 | ||
| 142 | #define NIC_RSSI_COUNT 4096 /* Total no of RSS indices */ | |
| 143 | #define NIC_MAX_RSS_HASH_BITS 8 | |
| 144 | #define NIC_MAX_RSS_IDR_TBL_SIZE (1 << NIC_MAX_RSS_HASH_BITS) | |
| 145 | #define RSS_HASH_KEY_SIZE 5 /* 320 bit key */ | |
| 146 | ||
| 147 | struct nicvf_rss_info { | |
| 148 | bool enable; | |
| 149 | #define RSS_L2_EXTENDED_HASH_ENA BIT(0) | |
| 150 | #define RSS_IP_HASH_ENA BIT(1) | |
| 151 | #define RSS_TCP_HASH_ENA BIT(2) | |
| 152 | #define RSS_TCP_SYN_DIS BIT(3) | |
| 153 | #define RSS_UDP_HASH_ENA BIT(4) | |
| 154 | #define RSS_L4_EXTENDED_HASH_ENA BIT(5) | |
| 155 | #define RSS_ROCE_ENA BIT(6) | |
| 156 | #define RSS_L3_BI_DIRECTION_ENA BIT(7) | |
| 157 | #define RSS_L4_BI_DIRECTION_ENA BIT(8) | |
| 158 | u64 cfg; | |
| 159 | u8 hash_bits; | |
| 160 | u16 rss_size; | |
| 161 | u8 ind_tbl[NIC_MAX_RSS_IDR_TBL_SIZE]; | |
| 162 | u64 key[RSS_HASH_KEY_SIZE]; | |
| 163 | } ____cacheline_aligned_in_smp; | |
| 164 | ||
| 165 | enum rx_stats_reg_offset { | |
| 166 | RX_OCTS = 0x0, | |
| 167 | RX_UCAST = 0x1, | |
| 168 | RX_BCAST = 0x2, | |
| 169 | RX_MCAST = 0x3, | |
| 170 | RX_RED = 0x4, | |
| 171 | RX_RED_OCTS = 0x5, | |
| 172 | RX_ORUN = 0x6, | |
| 173 | RX_ORUN_OCTS = 0x7, | |
| 174 | RX_FCS = 0x8, | |
| 175 | RX_L2ERR = 0x9, | |
| 176 | RX_DRP_BCAST = 0xa, | |
| 177 | RX_DRP_MCAST = 0xb, | |
| 178 | RX_DRP_L3BCAST = 0xc, | |
| 179 | RX_DRP_L3MCAST = 0xd, | |
| 180 | RX_STATS_ENUM_LAST, | |
| 181 | }; | |
| 182 | ||
| 183 | enum tx_stats_reg_offset { | |
| 184 | TX_OCTS = 0x0, | |
| 185 | TX_UCAST = 0x1, | |
| 186 | TX_BCAST = 0x2, | |
| 187 | TX_MCAST = 0x3, | |
| 188 | TX_DROP = 0x4, | |
| 189 | TX_STATS_ENUM_LAST, | |
| 190 | }; | |
| 191 | ||
| 192 | struct nicvf_hw_stats { | |
| 193 | u64 rx_bytes_ok; | |
| 194 | u64 rx_ucast_frames_ok; | |
| 195 | u64 rx_bcast_frames_ok; | |
| 196 | u64 rx_mcast_frames_ok; | |
| 197 | u64 rx_fcs_errors; | |
| 198 | u64 rx_l2_errors; | |
| 199 | u64 rx_drop_red; | |
| 200 | u64 rx_drop_red_bytes; | |
| 201 | u64 rx_drop_overrun; | |
| 202 | u64 rx_drop_overrun_bytes; | |
| 203 | u64 rx_drop_bcast; | |
| 204 | u64 rx_drop_mcast; | |
| 205 | u64 rx_drop_l3_bcast; | |
| 206 | u64 rx_drop_l3_mcast; | |
| 207 | u64 tx_bytes_ok; | |
| 208 | u64 tx_ucast_frames_ok; | |
| 209 | u64 tx_bcast_frames_ok; | |
| 210 | u64 tx_mcast_frames_ok; | |
| 211 | u64 tx_drops; | |
| 212 | }; | |
| 213 | ||
| 214 | struct nicvf_drv_stats { | |
| 215 | /* Rx */ | |
| 216 | u64 rx_frames_ok; | |
| 217 | u64 rx_frames_64; | |
| 218 | u64 rx_frames_127; | |
| 219 | u64 rx_frames_255; | |
| 220 | u64 rx_frames_511; | |
| 221 | u64 rx_frames_1023; | |
| 222 | u64 rx_frames_1518; | |
| 223 | u64 rx_frames_jumbo; | |
| 224 | u64 rx_drops; | |
| 225 | /* Tx */ | |
| 226 | u64 tx_frames_ok; | |
| 227 | u64 tx_drops; | |
| 4863dea3 | 228 | u64 tx_tso; |
| 74840b83 SG |
229 | u64 txq_stop; |
| 230 | u64 txq_wake; | |
| 4863dea3 SG |
231 | }; |
| 232 | ||
| 233 | struct nicvf { | |
| 234 | struct net_device *netdev; | |
| 235 | struct pci_dev *pdev; | |
| 236 | u8 vf_id; | |
| 237 | u8 node; | |
| 238 | u8 tns_mode; | |
| 239 | u16 mtu; | |
| 240 | struct queue_set *qs; | |
| 241 | void __iomem *reg_base; | |
| 242 | bool link_up; | |
| 243 | u8 duplex; | |
| 244 | u32 speed; | |
| 245 | struct page *rb_page; | |
| 246 | u32 rb_page_offset; | |
| 247 | bool rb_alloc_fail; | |
| 248 | bool rb_work_scheduled; | |
| 249 | struct delayed_work rbdr_work; | |
| 250 | struct tasklet_struct rbdr_task; | |
| 251 | struct tasklet_struct qs_err_task; | |
| 252 | struct tasklet_struct cq_task; | |
| 253 | struct nicvf_cq_poll *napi[8]; | |
| 254 | struct nicvf_rss_info rss_info; | |
| 255 | u8 cpi_alg; | |
| 256 | /* Interrupt coalescing settings */ | |
| 257 | u32 cq_coalesce_usecs; | |
| 258 | ||
| 259 | u32 msg_enable; | |
| 260 | struct nicvf_hw_stats stats; | |
| 261 | struct nicvf_drv_stats drv_stats; | |
| 262 | struct bgx_stats bgx_stats; | |
| 263 | struct work_struct reset_task; | |
| 264 | ||
| 265 | /* MSI-X */ | |
| 266 | bool msix_enabled; | |
| 267 | u8 num_vec; | |
| 268 | struct msix_entry msix_entries[NIC_VF_MSIX_VECTORS]; | |
| 269 | char irq_name[NIC_VF_MSIX_VECTORS][20]; | |
| 270 | bool irq_allocated[NIC_VF_MSIX_VECTORS]; | |
| 271 | ||
| 272 | bool pf_ready_to_rcv_msg; | |
| 273 | bool pf_acked; | |
| 274 | bool pf_nacked; | |
| 275 | bool bgx_stats_acked; | |
| bd049a90 | 276 | bool set_mac_pending; |
| 4863dea3 SG |
277 | } ____cacheline_aligned_in_smp; |
| 278 | ||
| 279 | /* PF <--> VF Mailbox communication | |
| 280 | * Eight 64bit registers are shared between PF and VF. | |
| 281 | * Separate set for each VF. | |
| 282 | * Writing '1' into last register mbx7 means end of message. | |
| 283 | */ | |
| 284 | ||
| 285 | /* PF <--> VF mailbox communication */ | |
| 286 | #define NIC_PF_VF_MAILBOX_SIZE 2 | |
| 287 | #define NIC_MBOX_MSG_TIMEOUT 2000 /* ms */ | |
| 288 | ||
| 289 | /* Mailbox message types */ | |
| 290 | #define NIC_MBOX_MSG_READY 0x01 /* Is PF ready to rcv msgs */ | |
| 291 | #define NIC_MBOX_MSG_ACK 0x02 /* ACK the message received */ | |
| 292 | #define NIC_MBOX_MSG_NACK 0x03 /* NACK the message received */ | |
| 293 | #define NIC_MBOX_MSG_QS_CFG 0x04 /* Configure Qset */ | |
| 294 | #define NIC_MBOX_MSG_RQ_CFG 0x05 /* Configure receive queue */ | |
| 295 | #define NIC_MBOX_MSG_SQ_CFG 0x06 /* Configure Send queue */ | |
| 296 | #define NIC_MBOX_MSG_RQ_DROP_CFG 0x07 /* Configure receive queue */ | |
| 297 | #define NIC_MBOX_MSG_SET_MAC 0x08 /* Add MAC ID to DMAC filter */ | |
| 298 | #define NIC_MBOX_MSG_SET_MAX_FRS 0x09 /* Set max frame size */ | |
| 299 | #define NIC_MBOX_MSG_CPI_CFG 0x0A /* Config CPI, RSSI */ | |
| 300 | #define NIC_MBOX_MSG_RSS_SIZE 0x0B /* Get RSS indir_tbl size */ | |
| 301 | #define NIC_MBOX_MSG_RSS_CFG 0x0C /* Config RSS table */ | |
| 302 | #define NIC_MBOX_MSG_RSS_CFG_CONT 0x0D /* RSS config continuation */ | |
| 303 | #define NIC_MBOX_MSG_RQ_BP_CFG 0x0E /* RQ backpressure config */ | |
| 304 | #define NIC_MBOX_MSG_RQ_SW_SYNC 0x0F /* Flush inflight pkts to RQ */ | |
| 305 | #define NIC_MBOX_MSG_BGX_STATS 0x10 /* Get stats from BGX */ | |
| 306 | #define NIC_MBOX_MSG_BGX_LINK_CHANGE 0x11 /* BGX:LMAC link status */ | |
| 307 | #define NIC_MBOX_MSG_CFG_DONE 0x12 /* VF configuration done */ | |
| 308 | #define NIC_MBOX_MSG_SHUTDOWN 0x13 /* VF is being shutdown */ | |
| 309 | ||
| 310 | struct nic_cfg_msg { | |
| 311 | u8 msg; | |
| 312 | u8 vf_id; | |
| 313 | u8 tns_mode; | |
| 314 | u8 node_id; | |
| e610cb32 | 315 | u8 mac_addr[ETH_ALEN]; |
| 4863dea3 SG |
316 | }; |
| 317 | ||
| 318 | /* Qset configuration */ | |
| 319 | struct qs_cfg_msg { | |
| 320 | u8 msg; | |
| 321 | u8 num; | |
| 322 | u64 cfg; | |
| 323 | }; | |
| 324 | ||
| 325 | /* Receive queue configuration */ | |
| 326 | struct rq_cfg_msg { | |
| 327 | u8 msg; | |
| 328 | u8 qs_num; | |
| 329 | u8 rq_num; | |
| 330 | u64 cfg; | |
| 331 | }; | |
| 332 | ||
| 333 | /* Send queue configuration */ | |
| 334 | struct sq_cfg_msg { | |
| 335 | u8 msg; | |
| 336 | u8 qs_num; | |
| 337 | u8 sq_num; | |
| 338 | u64 cfg; | |
| 339 | }; | |
| 340 | ||
| 341 | /* Set VF's MAC address */ | |
| 342 | struct set_mac_msg { | |
| 343 | u8 msg; | |
| 344 | u8 vf_id; | |
| e610cb32 | 345 | u8 mac_addr[ETH_ALEN]; |
| 4863dea3 SG |
346 | }; |
| 347 | ||
| 348 | /* Set Maximum frame size */ | |
| 349 | struct set_frs_msg { | |
| 350 | u8 msg; | |
| 351 | u8 vf_id; | |
| 352 | u16 max_frs; | |
| 353 | }; | |
| 354 | ||
| 355 | /* Set CPI algorithm type */ | |
| 356 | struct cpi_cfg_msg { | |
| 357 | u8 msg; | |
| 358 | u8 vf_id; | |
| 359 | u8 rq_cnt; | |
| 360 | u8 cpi_alg; | |
| 361 | }; | |
| 362 | ||
| 363 | /* Get RSS table size */ | |
| 364 | struct rss_sz_msg { | |
| 365 | u8 msg; | |
| 366 | u8 vf_id; | |
| 367 | u16 ind_tbl_size; | |
| 368 | }; | |
| 369 | ||
| 370 | /* Set RSS configuration */ | |
| 371 | struct rss_cfg_msg { | |
| 372 | u8 msg; | |
| 373 | u8 vf_id; | |
| 374 | u8 hash_bits; | |
| 375 | u8 tbl_len; | |
| 376 | u8 tbl_offset; | |
| 377 | #define RSS_IND_TBL_LEN_PER_MBX_MSG 8 | |
| 378 | u8 ind_tbl[RSS_IND_TBL_LEN_PER_MBX_MSG]; | |
| 379 | }; | |
| 380 | ||
| 381 | struct bgx_stats_msg { | |
| 382 | u8 msg; | |
| 383 | u8 vf_id; | |
| 384 | u8 rx; | |
| 385 | u8 idx; | |
| 386 | u64 stats; | |
| 387 | }; | |
| 388 | ||
| 389 | /* Physical interface link status */ | |
| 390 | struct bgx_link_status { | |
| 391 | u8 msg; | |
| 392 | u8 link_up; | |
| 393 | u8 duplex; | |
| 394 | u32 speed; | |
| 395 | }; | |
| 396 | ||
| 397 | /* 128 bit shared memory between PF and each VF */ | |
| 398 | union nic_mbx { | |
| 399 | struct { u8 msg; } msg; | |
| 400 | struct nic_cfg_msg nic_cfg; | |
| 401 | struct qs_cfg_msg qs; | |
| 402 | struct rq_cfg_msg rq; | |
| 403 | struct sq_cfg_msg sq; | |
| 404 | struct set_mac_msg mac; | |
| 405 | struct set_frs_msg frs; | |
| 406 | struct cpi_cfg_msg cpi_cfg; | |
| 407 | struct rss_sz_msg rss_size; | |
| 408 | struct rss_cfg_msg rss_cfg; | |
| 409 | struct bgx_stats_msg bgx_stats; | |
| 410 | struct bgx_link_status link_status; | |
| 411 | }; | |
| 412 | ||
| d768b678 RR |
413 | #define NIC_NODE_ID_MASK 0x03 |
| 414 | #define NIC_NODE_ID_SHIFT 44 | |
| 415 | ||
| 416 | static inline int nic_get_node_id(struct pci_dev *pdev) | |
| 417 | { | |
| 418 | u64 addr = pci_resource_start(pdev, PCI_CFG_REG_BAR_NUM); | |
| 419 | return ((addr >> NIC_NODE_ID_SHIFT) & NIC_NODE_ID_MASK); | |
| 420 | } | |
| 421 | ||
| 4863dea3 SG |
422 | int nicvf_set_real_num_queues(struct net_device *netdev, |
| 423 | int tx_queues, int rx_queues); | |
| 424 | int nicvf_open(struct net_device *netdev); | |
| 425 | int nicvf_stop(struct net_device *netdev); | |
| 426 | int nicvf_send_msg_to_pf(struct nicvf *vf, union nic_mbx *mbx); | |
| 4863dea3 SG |
427 | void nicvf_config_rss(struct nicvf *nic); |
| 428 | void nicvf_set_rss_key(struct nicvf *nic); | |
| 4863dea3 SG |
429 | void nicvf_set_ethtool_ops(struct net_device *netdev); |
| 430 | void nicvf_update_stats(struct nicvf *nic); | |
| 431 | void nicvf_update_lmac_stats(struct nicvf *nic); | |
| 432 | ||
| 433 | #endif /* NIC_H */ |