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net: thunderx: introduce a function for mailbox access
[deliverable/linux.git] / drivers / net / ethernet / cavium / thunder / nicvf_main.c
CommitLineData
4863dea3
SG		 1/*
2 * Copyright (C) 2015 Cavium, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of version 2 of the GNU General Public License
6 * as published by the Free Software Foundation.
7 */
8
9#include <linux/module.h>
10#include <linux/interrupt.h>
11#include <linux/pci.h>
12#include <linux/netdevice.h>
13#include <linux/etherdevice.h>
14#include <linux/ethtool.h>
15#include <linux/log2.h>
16#include <linux/prefetch.h>
17#include <linux/irq.h>
18
19#include "nic_reg.h"
20#include "nic.h"
21#include "nicvf_queues.h"
22#include "thunder_bgx.h"
23
24#define DRV_NAME "thunder-nicvf"
25#define DRV_VERSION "1.0"
26
27/* Supported devices */
28static const struct pci_device_id nicvf_id_table[] = {
29 { PCI_DEVICE_SUB(PCI_VENDOR_ID_CAVIUM,
30 PCI_DEVICE_ID_THUNDER_NIC_VF,
31 PCI_VENDOR_ID_CAVIUM, 0xA11E) },
32 { PCI_DEVICE_SUB(PCI_VENDOR_ID_CAVIUM,
33 PCI_DEVICE_ID_THUNDER_PASS1_NIC_VF,
34 PCI_VENDOR_ID_CAVIUM, 0xA11E) },
35 { 0, } /* end of table */
36};
37
38MODULE_AUTHOR("Sunil Goutham");
39MODULE_DESCRIPTION("Cavium Thunder NIC Virtual Function Driver");
40MODULE_LICENSE("GPL v2");
41MODULE_VERSION(DRV_VERSION);
42MODULE_DEVICE_TABLE(pci, nicvf_id_table);
43
44static int debug = 0x00;
45module_param(debug, int, 0644);
46MODULE_PARM_DESC(debug, "Debug message level bitmap");
47
48static int cpi_alg = CPI_ALG_NONE;
49module_param(cpi_alg, int, S_IRUGO);
50MODULE_PARM_DESC(cpi_alg,
51 "PFC algorithm (0=none, 1=VLAN, 2=VLAN16, 3=IP Diffserv)");
52
53static int nicvf_enable_msix(struct nicvf *nic);
54static netdev_tx_t nicvf_xmit(struct sk_buff *skb, struct net_device *netdev);
55static void nicvf_read_bgx_stats(struct nicvf *nic, struct bgx_stats_msg *bgx);
56
57static inline void nicvf_set_rx_frame_cnt(struct nicvf *nic,
58 struct sk_buff *skb)
59{
60 if (skb->len <= 64)
61 nic->drv_stats.rx_frames_64++;
62 else if (skb->len <= 127)
63 nic->drv_stats.rx_frames_127++;
64 else if (skb->len <= 255)
65 nic->drv_stats.rx_frames_255++;
66 else if (skb->len <= 511)
67 nic->drv_stats.rx_frames_511++;
68 else if (skb->len <= 1023)
69 nic->drv_stats.rx_frames_1023++;
70 else if (skb->len <= 1518)
71 nic->drv_stats.rx_frames_1518++;
72 else
73 nic->drv_stats.rx_frames_jumbo++;
74}
75
76/* The Cavium ThunderX network controller can *only* be found in SoCs
77 * containing the ThunderX ARM64 CPU implementation. All accesses to the device
78 * registers on this platform are implicitly strongly ordered with respect
79 * to memory accesses. So writeq_relaxed() and readq_relaxed() are safe to use
80 * with no memory barriers in this driver. The readq()/writeq() functions add
81 * explicit ordering operation which in this case are redundant, and only
82 * add overhead.
83 */
84
85/* Register read/write APIs */
86void nicvf_reg_write(struct nicvf *nic, u64 offset, u64 val)
87{
88 writeq_relaxed(val, nic->reg_base + offset);
89}
90
91u64 nicvf_reg_read(struct nicvf *nic, u64 offset)
92{
93 return readq_relaxed(nic->reg_base + offset);
94}
95
96void nicvf_queue_reg_write(struct nicvf *nic, u64 offset,
97 u64 qidx, u64 val)
98{
99 void __iomem *addr = nic->reg_base + offset;
100
101 writeq_relaxed(val, addr + (qidx << NIC_Q_NUM_SHIFT));
102}
103
104u64 nicvf_queue_reg_read(struct nicvf *nic, u64 offset, u64 qidx)
105{
106 void __iomem *addr = nic->reg_base + offset;
107
108 return readq_relaxed(addr + (qidx << NIC_Q_NUM_SHIFT));
109}
110
111/* VF -> PF mailbox communication */
112
2cd2a196
AM		 113static void nicvf_write_to_mbx(struct nicvf *nic, union nic_mbx *mbx)
114{
115 u64 *msg = (u64 *)mbx;
116
117 nicvf_reg_write(nic, NIC_VF_PF_MAILBOX_0_1 + 0, msg[0]);
118 nicvf_reg_write(nic, NIC_VF_PF_MAILBOX_0_1 + 8, msg[1]);
119}
120
4863dea3
SG		 121int nicvf_send_msg_to_pf(struct nicvf *nic, union nic_mbx *mbx)
122{
123 int timeout = NIC_MBOX_MSG_TIMEOUT;
124 int sleep = 10;
4863dea3
SG		 125
126 nic->pf_acked = false;
127 nic->pf_nacked = false;
128
2cd2a196 129 nicvf_write_to_mbx(nic, mbx);
4863dea3
SG		 130
131 /* Wait for previous message to be acked, timeout 2sec */
132 while (!nic->pf_acked) {
133 if (nic->pf_nacked)
134 return -EINVAL;
135 msleep(sleep);
136 if (nic->pf_acked)
137 break;
138 timeout -= sleep;
139 if (!timeout) {
140 netdev_err(nic->netdev,
141 "PF didn't ack to mbox msg %d from VF%d\n",
142 (mbx->msg.msg & 0xFF), nic->vf_id);
143 return -EBUSY;
144 }
145 }
146 return 0;
147}
148
149/* Checks if VF is able to comminicate with PF
150* and also gets the VNIC number this VF is associated to.
151*/
152static int nicvf_check_pf_ready(struct nicvf *nic)
153{
154 int timeout = 5000, sleep = 20;
2cd2a196
AM		 155 union nic_mbx mbx = {};
156
157 mbx.msg.msg = NIC_MBOX_MSG_READY;
4863dea3
SG		 158
159 nic->pf_ready_to_rcv_msg = false;
160
2cd2a196 161 nicvf_write_to_mbx(nic, &mbx);
4863dea3
SG		 162
163 while (!nic->pf_ready_to_rcv_msg) {
164 msleep(sleep);
165 if (nic->pf_ready_to_rcv_msg)
166 break;
167 timeout -= sleep;
168 if (!timeout) {
169 netdev_err(nic->netdev,
170 "PF didn't respond to READY msg\n");
171 return 0;
172 }
173 }
174 return 1;
175}
176
177static void nicvf_handle_mbx_intr(struct nicvf *nic)
178{
179 union nic_mbx mbx = {};
180 u64 *mbx_data;
181 u64 mbx_addr;
182 int i;
183
184 mbx_addr = NIC_VF_PF_MAILBOX_0_1;
185 mbx_data = (u64 *)&mbx;
186
187 for (i = 0; i < NIC_PF_VF_MAILBOX_SIZE; i++) {
188 *mbx_data = nicvf_reg_read(nic, mbx_addr);
189 mbx_data++;
190 mbx_addr += sizeof(u64);
191 }
192
193 netdev_dbg(nic->netdev, "Mbox message: msg: 0x%x\n", mbx.msg.msg);
194 switch (mbx.msg.msg) {
195 case NIC_MBOX_MSG_READY:
196 nic->pf_ready_to_rcv_msg = true;
197 nic->vf_id = mbx.nic_cfg.vf_id & 0x7F;
198 nic->tns_mode = mbx.nic_cfg.tns_mode & 0x7F;
199 nic->node = mbx.nic_cfg.node_id;
200 ether_addr_copy(nic->netdev->dev_addr,
201 (u8 *)&mbx.nic_cfg.mac_addr);
202 nic->link_up = false;
203 nic->duplex = 0;
204 nic->speed = 0;
205 break;
206 case NIC_MBOX_MSG_ACK:
207 nic->pf_acked = true;
208 break;
209 case NIC_MBOX_MSG_NACK:
210 nic->pf_nacked = true;
211 break;
212 case NIC_MBOX_MSG_RSS_SIZE:
213 nic->rss_info.rss_size = mbx.rss_size.ind_tbl_size;
214 nic->pf_acked = true;
215 break;
216 case NIC_MBOX_MSG_BGX_STATS:
217 nicvf_read_bgx_stats(nic, &mbx.bgx_stats);
218 nic->pf_acked = true;
219 nic->bgx_stats_acked = true;
220 break;
221 case NIC_MBOX_MSG_BGX_LINK_CHANGE:
222 nic->pf_acked = true;
223 nic->link_up = mbx.link_status.link_up;
224 nic->duplex = mbx.link_status.duplex;
225 nic->speed = mbx.link_status.speed;
226 if (nic->link_up) {
227 netdev_info(nic->netdev, "%s: Link is Up %d Mbps %s\n",
228 nic->netdev->name, nic->speed,
229 nic->duplex == DUPLEX_FULL ?
230 "Full duplex" : "Half duplex");
231 netif_carrier_on(nic->netdev);
232 netif_tx_wake_all_queues(nic->netdev);
233 } else {
234 netdev_info(nic->netdev, "%s: Link is Down\n",
235 nic->netdev->name);
236 netif_carrier_off(nic->netdev);
237 netif_tx_stop_all_queues(nic->netdev);
238 }
239 break;
240 default:
241 netdev_err(nic->netdev,
242 "Invalid message from PF, msg 0x%x\n", mbx.msg.msg);
243 break;
244 }
245 nicvf_clear_intr(nic, NICVF_INTR_MBOX, 0);
246}
247
248static int nicvf_hw_set_mac_addr(struct nicvf *nic, struct net_device *netdev)
249{
250 union nic_mbx mbx = {};
251 int i;
252
253 mbx.mac.msg = NIC_MBOX_MSG_SET_MAC;
254 mbx.mac.vf_id = nic->vf_id;
255 for (i = 0; i < ETH_ALEN; i++)
256 mbx.mac.addr = (mbx.mac.addr << 8) |
257 netdev->dev_addr[i];
258
259 return nicvf_send_msg_to_pf(nic, &mbx);
260}
261
262void nicvf_config_cpi(struct nicvf *nic)
263{
264 union nic_mbx mbx = {};
265
266 mbx.cpi_cfg.msg = NIC_MBOX_MSG_CPI_CFG;
267 mbx.cpi_cfg.vf_id = nic->vf_id;
268 mbx.cpi_cfg.cpi_alg = nic->cpi_alg;
269 mbx.cpi_cfg.rq_cnt = nic->qs->rq_cnt;
270
271 nicvf_send_msg_to_pf(nic, &mbx);
272}
273
274void nicvf_get_rss_size(struct nicvf *nic)
275{
276 union nic_mbx mbx = {};
277
278 mbx.rss_size.msg = NIC_MBOX_MSG_RSS_SIZE;
279 mbx.rss_size.vf_id = nic->vf_id;
280 nicvf_send_msg_to_pf(nic, &mbx);
281}
282
283void nicvf_config_rss(struct nicvf *nic)
284{
285 union nic_mbx mbx = {};
286 struct nicvf_rss_info *rss = &nic->rss_info;
287 int ind_tbl_len = rss->rss_size;
288 int i, nextq = 0;
289
290 mbx.rss_cfg.vf_id = nic->vf_id;
291 mbx.rss_cfg.hash_bits = rss->hash_bits;
292 while (ind_tbl_len) {
293 mbx.rss_cfg.tbl_offset = nextq;
294 mbx.rss_cfg.tbl_len = min(ind_tbl_len,
295 RSS_IND_TBL_LEN_PER_MBX_MSG);
296 mbx.rss_cfg.msg = mbx.rss_cfg.tbl_offset ?
297 NIC_MBOX_MSG_RSS_CFG_CONT : NIC_MBOX_MSG_RSS_CFG;
298
299 for (i = 0; i < mbx.rss_cfg.tbl_len; i++)
300 mbx.rss_cfg.ind_tbl[i] = rss->ind_tbl[nextq++];
301
302 nicvf_send_msg_to_pf(nic, &mbx);
303
304 ind_tbl_len -= mbx.rss_cfg.tbl_len;
305 }
306}
307
308void nicvf_set_rss_key(struct nicvf *nic)
309{
310 struct nicvf_rss_info *rss = &nic->rss_info;
311 u64 key_addr = NIC_VNIC_RSS_KEY_0_4;
312 int idx;
313
314 for (idx = 0; idx < RSS_HASH_KEY_SIZE; idx++) {
315 nicvf_reg_write(nic, key_addr, rss->key[idx]);
316 key_addr += sizeof(u64);
317 }
318}
319
320static int nicvf_rss_init(struct nicvf *nic)
321{
322 struct nicvf_rss_info *rss = &nic->rss_info;
323 int idx;
324
325 nicvf_get_rss_size(nic);
326
327 if ((nic->qs->rq_cnt <= 1) || (cpi_alg != CPI_ALG_NONE)) {
328 rss->enable = false;
329 rss->hash_bits = 0;
330 return 0;
331 }
332
333 rss->enable = true;
334
335 /* Using the HW reset value for now */
4a4f87d8
AM		 336 rss->key[0] = 0xFEED0BADFEED0BADULL;
337 rss->key[1] = 0xFEED0BADFEED0BADULL;
338 rss->key[2] = 0xFEED0BADFEED0BADULL;
339 rss->key[3] = 0xFEED0BADFEED0BADULL;
340 rss->key[4] = 0xFEED0BADFEED0BADULL;
4863dea3
SG		 341
342 nicvf_set_rss_key(nic);
343
344 rss->cfg = RSS_IP_HASH_ENA | RSS_TCP_HASH_ENA | RSS_UDP_HASH_ENA;
345 nicvf_reg_write(nic, NIC_VNIC_RSS_CFG, rss->cfg);
346
347 rss->hash_bits = ilog2(rounddown_pow_of_two(rss->rss_size));
348
349 for (idx = 0; idx < rss->rss_size; idx++)
350 rss->ind_tbl[idx] = ethtool_rxfh_indir_default(idx,
351 nic->qs->rq_cnt);
352 nicvf_config_rss(nic);
353 return 1;
354}
355
356int nicvf_set_real_num_queues(struct net_device *netdev,
357 int tx_queues, int rx_queues)
358{
359 int err = 0;
360
361 err = netif_set_real_num_tx_queues(netdev, tx_queues);
362 if (err) {
363 netdev_err(netdev,
364 "Failed to set no of Tx queues: %d\n", tx_queues);
365 return err;
366 }
367
368 err = netif_set_real_num_rx_queues(netdev, rx_queues);
369 if (err)
370 netdev_err(netdev,
371 "Failed to set no of Rx queues: %d\n", rx_queues);
372 return err;
373}
374
375static int nicvf_init_resources(struct nicvf *nic)
376{
377 int err;
2cd2a196
AM		 378 union nic_mbx mbx = {};
379
380 mbx.msg.msg = NIC_MBOX_MSG_CFG_DONE;
4863dea3
SG		 381
382 /* Enable Qset */
383 nicvf_qset_config(nic, true);
384
385 /* Initialize queues and HW for data transfer */
386 err = nicvf_config_data_transfer(nic, true);
387 if (err) {
388 netdev_err(nic->netdev,
389 "Failed to alloc/config VF's QSet resources\n");
390 return err;
391 }
392
393 /* Send VF config done msg to PF */
2cd2a196 394 nicvf_write_to_mbx(nic, &mbx);
4863dea3
SG		 395
396 return 0;
397}
398
399static void nicvf_snd_pkt_handler(struct net_device *netdev,
400 struct cmp_queue *cq,
401 struct cqe_send_t *cqe_tx, int cqe_type)
402{
403 struct sk_buff *skb = NULL;
404 struct nicvf *nic = netdev_priv(netdev);
405 struct snd_queue *sq;
406 struct sq_hdr_subdesc *hdr;
407
408 sq = &nic->qs->sq[cqe_tx->sq_idx];
409
410 hdr = (struct sq_hdr_subdesc *)GET_SQ_DESC(sq, cqe_tx->sqe_ptr);
411 if (hdr->subdesc_type != SQ_DESC_TYPE_HEADER)
412 return;
413
414 netdev_dbg(nic->netdev,
415 "%s Qset #%d SQ #%d SQ ptr #%d subdesc count %d\n",
416 __func__, cqe_tx->sq_qs, cqe_tx->sq_idx,
417 cqe_tx->sqe_ptr, hdr->subdesc_cnt);
418
419 nicvf_put_sq_desc(sq, hdr->subdesc_cnt + 1);
420 nicvf_check_cqe_tx_errs(nic, cq, cqe_tx);
421 skb = (struct sk_buff *)sq->skbuff[cqe_tx->sqe_ptr];
422 /* For TSO offloaded packets only one head SKB needs to be freed */
423 if (skb) {
424 prefetch(skb);
425 dev_consume_skb_any(skb);
426 }
427}
428
429static void nicvf_rcv_pkt_handler(struct net_device *netdev,
430 struct napi_struct *napi,
431 struct cmp_queue *cq,
432 struct cqe_rx_t *cqe_rx, int cqe_type)
433{
434 struct sk_buff *skb;
435 struct nicvf *nic = netdev_priv(netdev);
436 int err = 0;
437
438 /* Check for errors */
439 err = nicvf_check_cqe_rx_errs(nic, cq, cqe_rx);
440 if (err && !cqe_rx->rb_cnt)
441 return;
442
443 skb = nicvf_get_rcv_skb(nic, cqe_rx);
444 if (!skb) {
445 netdev_dbg(nic->netdev, "Packet not received\n");
446 return;
447 }
448
449 if (netif_msg_pktdata(nic)) {
450 netdev_info(nic->netdev, "%s: skb 0x%p, len=%d\n", netdev->name,
451 skb, skb->len);
452 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_OFFSET, 16, 1,
453 skb->data, skb->len, true);
454 }
455
456 nicvf_set_rx_frame_cnt(nic, skb);
457
458 skb_record_rx_queue(skb, cqe_rx->rq_idx);
459 if (netdev->hw_features & NETIF_F_RXCSUM) {
460 /* HW by default verifies TCP/UDP/SCTP checksums */
461 skb->ip_summed = CHECKSUM_UNNECESSARY;
462 } else {
463 skb_checksum_none_assert(skb);
464 }
465
466 skb->protocol = eth_type_trans(skb, netdev);
467
468 if (napi && (netdev->features & NETIF_F_GRO))
469 napi_gro_receive(napi, skb);
470 else
471 netif_receive_skb(skb);
472}
473
474static int nicvf_cq_intr_handler(struct net_device *netdev, u8 cq_idx,
475 struct napi_struct *napi, int budget)
476{
477 int processed_cqe, work_done = 0;
478 int cqe_count, cqe_head;
479 struct nicvf *nic = netdev_priv(netdev);
480 struct queue_set *qs = nic->qs;
481 struct cmp_queue *cq = &qs->cq[cq_idx];
482 struct cqe_rx_t *cq_desc;
483
484 spin_lock_bh(&cq->lock);
485loop:
486 processed_cqe = 0;
487 /* Get no of valid CQ entries to process */
488 cqe_count = nicvf_queue_reg_read(nic, NIC_QSET_CQ_0_7_STATUS, cq_idx);
489 cqe_count &= CQ_CQE_COUNT;
490 if (!cqe_count)
491 goto done;
492
493 /* Get head of the valid CQ entries */
494 cqe_head = nicvf_queue_reg_read(nic, NIC_QSET_CQ_0_7_HEAD, cq_idx) >> 9;
495 cqe_head &= 0xFFFF;
496
497 netdev_dbg(nic->netdev, "%s cqe_count %d cqe_head %d\n",
498 __func__, cqe_count, cqe_head);
499 while (processed_cqe < cqe_count) {
500 /* Get the CQ descriptor */
501 cq_desc = (struct cqe_rx_t *)GET_CQ_DESC(cq, cqe_head);
502 cqe_head++;
503 cqe_head &= (cq->dmem.q_len - 1);
504 /* Initiate prefetch for next descriptor */
505 prefetch((struct cqe_rx_t *)GET_CQ_DESC(cq, cqe_head));
506
507 if ((work_done >= budget) && napi &&
508 (cq_desc->cqe_type != CQE_TYPE_SEND)) {
509 break;
510 }
511
512 netdev_dbg(nic->netdev, "cq_desc->cqe_type %d\n",
513 cq_desc->cqe_type);
514 switch (cq_desc->cqe_type) {
515 case CQE_TYPE_RX:
516 nicvf_rcv_pkt_handler(netdev, napi, cq,
517 cq_desc, CQE_TYPE_RX);
518 work_done++;
519 break;
520 case CQE_TYPE_SEND:
521 nicvf_snd_pkt_handler(netdev, cq,
522 (void *)cq_desc, CQE_TYPE_SEND);
523 break;
524 case CQE_TYPE_INVALID:
525 case CQE_TYPE_RX_SPLIT:
526 case CQE_TYPE_RX_TCP:
527 case CQE_TYPE_SEND_PTP:
528 /* Ignore for now */
529 break;
530 }
531 processed_cqe++;
532 }
533 netdev_dbg(nic->netdev, "%s processed_cqe %d work_done %d budget %d\n",
534 __func__, processed_cqe, work_done, budget);
535
536 /* Ring doorbell to inform H/W to reuse processed CQEs */
537 nicvf_queue_reg_write(nic, NIC_QSET_CQ_0_7_DOOR,
538 cq_idx, processed_cqe);
539
540 if ((work_done < budget) && napi)
541 goto loop;
542
543done:
544 spin_unlock_bh(&cq->lock);
545 return work_done;
546}
547
548static int nicvf_poll(struct napi_struct *napi, int budget)
549{
550 u64 cq_head;
551 int work_done = 0;
552 struct net_device *netdev = napi->dev;
553 struct nicvf *nic = netdev_priv(netdev);
554 struct nicvf_cq_poll *cq;
555 struct netdev_queue *txq;
556
557 cq = container_of(napi, struct nicvf_cq_poll, napi);
558 work_done = nicvf_cq_intr_handler(netdev, cq->cq_idx, napi, budget);
559
560 txq = netdev_get_tx_queue(netdev, cq->cq_idx);
561 if (netif_tx_queue_stopped(txq))
562 netif_tx_wake_queue(txq);
563
564 if (work_done < budget) {
565 /* Slow packet rate, exit polling */
566 napi_complete(napi);
567 /* Re-enable interrupts */
568 cq_head = nicvf_queue_reg_read(nic, NIC_QSET_CQ_0_7_HEAD,
569 cq->cq_idx);
570 nicvf_clear_intr(nic, NICVF_INTR_CQ, cq->cq_idx);
571 nicvf_queue_reg_write(nic, NIC_QSET_CQ_0_7_HEAD,
572 cq->cq_idx, cq_head);
573 nicvf_enable_intr(nic, NICVF_INTR_CQ, cq->cq_idx);
574 }
575 return work_done;
576}
577
578/* Qset error interrupt handler
579 *
580 * As of now only CQ errors are handled
581 */
582void nicvf_handle_qs_err(unsigned long data)
583{
584 struct nicvf *nic = (struct nicvf *)data;
585 struct queue_set *qs = nic->qs;
586 int qidx;
587 u64 status;
588
589 netif_tx_disable(nic->netdev);
590
591 /* Check if it is CQ err */
592 for (qidx = 0; qidx < qs->cq_cnt; qidx++) {
593 status = nicvf_queue_reg_read(nic, NIC_QSET_CQ_0_7_STATUS,
594 qidx);
595 if (!(status & CQ_ERR_MASK))
596 continue;
597 /* Process already queued CQEs and reconfig CQ */
598 nicvf_disable_intr(nic, NICVF_INTR_CQ, qidx);
599 nicvf_sq_disable(nic, qidx);
600 nicvf_cq_intr_handler(nic->netdev, qidx, NULL, 0);
601 nicvf_cmp_queue_config(nic, qs, qidx, true);
602 nicvf_sq_free_used_descs(nic->netdev, &qs->sq[qidx], qidx);
603 nicvf_sq_enable(nic, &qs->sq[qidx], qidx);
604
605 nicvf_enable_intr(nic, NICVF_INTR_CQ, qidx);
606 }
607
608 netif_tx_start_all_queues(nic->netdev);
609 /* Re-enable Qset error interrupt */
610 nicvf_enable_intr(nic, NICVF_INTR_QS_ERR, 0);
611}
612
613static irqreturn_t nicvf_misc_intr_handler(int irq, void *nicvf_irq)
614{
615 struct nicvf *nic = (struct nicvf *)nicvf_irq;
616 u64 intr;
617
618 intr = nicvf_reg_read(nic, NIC_VF_INT);
619 /* Check for spurious interrupt */
620 if (!(intr & NICVF_INTR_MBOX_MASK))
621 return IRQ_HANDLED;
622
623 nicvf_handle_mbx_intr(nic);
624
625 return IRQ_HANDLED;
626}
627
628static irqreturn_t nicvf_intr_handler(int irq, void *nicvf_irq)
629{
630 u64 qidx, intr, clear_intr = 0;
631 u64 cq_intr, rbdr_intr, qs_err_intr;
632 struct nicvf *nic = (struct nicvf *)nicvf_irq;
633 struct queue_set *qs = nic->qs;
634 struct nicvf_cq_poll *cq_poll = NULL;
635
636 intr = nicvf_reg_read(nic, NIC_VF_INT);
637 if (netif_msg_intr(nic))
638 netdev_info(nic->netdev, "%s: interrupt status 0x%llx\n",
639 nic->netdev->name, intr);
640
641 qs_err_intr = intr & NICVF_INTR_QS_ERR_MASK;
642 if (qs_err_intr) {
643 /* Disable Qset err interrupt and schedule softirq */
644 nicvf_disable_intr(nic, NICVF_INTR_QS_ERR, 0);
645 tasklet_hi_schedule(&nic->qs_err_task);
646 clear_intr |= qs_err_intr;
647 }
648
649 /* Disable interrupts and start polling */
650 cq_intr = (intr & NICVF_INTR_CQ_MASK) >> NICVF_INTR_CQ_SHIFT;
651 for (qidx = 0; qidx < qs->cq_cnt; qidx++) {
652 if (!(cq_intr & (1 << qidx)))
653 continue;
654 if (!nicvf_is_intr_enabled(nic, NICVF_INTR_CQ, qidx))
655 continue;
656
657 nicvf_disable_intr(nic, NICVF_INTR_CQ, qidx);
658 clear_intr |= ((1 << qidx) << NICVF_INTR_CQ_SHIFT);
659
660 cq_poll = nic->napi[qidx];
661 /* Schedule NAPI */
662 if (cq_poll)
663 napi_schedule(&cq_poll->napi);
664 }
665
666 /* Handle RBDR interrupts */
667 rbdr_intr = (intr & NICVF_INTR_RBDR_MASK) >> NICVF_INTR_RBDR_SHIFT;
668 if (rbdr_intr) {
669 /* Disable RBDR interrupt and schedule softirq */
670 for (qidx = 0; qidx < qs->rbdr_cnt; qidx++) {
671 if (!nicvf_is_intr_enabled(nic, NICVF_INTR_RBDR, qidx))
672 continue;
673 nicvf_disable_intr(nic, NICVF_INTR_RBDR, qidx);
674 tasklet_hi_schedule(&nic->rbdr_task);
675 clear_intr |= ((1 << qidx) << NICVF_INTR_RBDR_SHIFT);
676 }
677 }
678
679 /* Clear interrupts */
680 nicvf_reg_write(nic, NIC_VF_INT, clear_intr);
681 return IRQ_HANDLED;
682}
683
684static int nicvf_enable_msix(struct nicvf *nic)
685{
686 int ret, vec;
687
688 nic->num_vec = NIC_VF_MSIX_VECTORS;
689
690 for (vec = 0; vec < nic->num_vec; vec++)
691 nic->msix_entries[vec].entry = vec;
692
693 ret = pci_enable_msix(nic->pdev, nic->msix_entries, nic->num_vec);
694 if (ret) {
695 netdev_err(nic->netdev,
696 "Req for #%d msix vectors failed\n", nic->num_vec);
697 return 0;
698 }
699 nic->msix_enabled = 1;
700 return 1;
701}
702
703static void nicvf_disable_msix(struct nicvf *nic)
704{
705 if (nic->msix_enabled) {
706 pci_disable_msix(nic->pdev);
707 nic->msix_enabled = 0;
708 nic->num_vec = 0;
709 }
710}
711
712static int nicvf_register_interrupts(struct nicvf *nic)
713{
714 int irq, free, ret = 0;
715 int vector;
716
717 for_each_cq_irq(irq)
718 sprintf(nic->irq_name[irq], "NICVF%d CQ%d",
719 nic->vf_id, irq);
720
721 for_each_sq_irq(irq)
722 sprintf(nic->irq_name[irq], "NICVF%d SQ%d",
723 nic->vf_id, irq - NICVF_INTR_ID_SQ);
724
725 for_each_rbdr_irq(irq)
726 sprintf(nic->irq_name[irq], "NICVF%d RBDR%d",
727 nic->vf_id, irq - NICVF_INTR_ID_RBDR);
728
729 /* Register all interrupts except mailbox */
730 for (irq = 0; irq < NICVF_INTR_ID_SQ; irq++) {
731 vector = nic->msix_entries[irq].vector;
732 ret = request_irq(vector, nicvf_intr_handler,
733 0, nic->irq_name[irq], nic);
734 if (ret)
735 break;
736 nic->irq_allocated[irq] = true;
737 }
738
739 for (irq = NICVF_INTR_ID_SQ; irq < NICVF_INTR_ID_MISC; irq++) {
740 vector = nic->msix_entries[irq].vector;
741 ret = request_irq(vector, nicvf_intr_handler,
742 0, nic->irq_name[irq], nic);
743 if (ret)
744 break;
745 nic->irq_allocated[irq] = true;
746 }
747
748 sprintf(nic->irq_name[NICVF_INTR_ID_QS_ERR],
749 "NICVF%d Qset error", nic->vf_id);
750 if (!ret) {
751 vector = nic->msix_entries[NICVF_INTR_ID_QS_ERR].vector;
752 irq = NICVF_INTR_ID_QS_ERR;
753 ret = request_irq(vector, nicvf_intr_handler,
754 0, nic->irq_name[irq], nic);
755 if (!ret)
756 nic->irq_allocated[irq] = true;
757 }
758
759 if (ret) {
760 netdev_err(nic->netdev, "Request irq failed\n");
761 for (free = 0; free < irq; free++)
762 free_irq(nic->msix_entries[free].vector, nic);
763 return ret;
764 }
765
766 return 0;
767}
768
769static void nicvf_unregister_interrupts(struct nicvf *nic)
770{
771 int irq;
772
773 /* Free registered interrupts */
774 for (irq = 0; irq < nic->num_vec; irq++) {
775 if (nic->irq_allocated[irq])
776 free_irq(nic->msix_entries[irq].vector, nic);
777 nic->irq_allocated[irq] = false;
778 }
779
780 /* Disable MSI-X */
781 nicvf_disable_msix(nic);
782}
783
784/* Initialize MSIX vectors and register MISC interrupt.
785 * Send READY message to PF to check if its alive
786 */
787static int nicvf_register_misc_interrupt(struct nicvf *nic)
788{
789 int ret = 0;
790 int irq = NICVF_INTR_ID_MISC;
791
792 /* Return if mailbox interrupt is already registered */
793 if (nic->msix_enabled)
794 return 0;
795
796 /* Enable MSI-X */
797 if (!nicvf_enable_msix(nic))
798 return 1;
799
800 sprintf(nic->irq_name[irq], "%s Mbox", "NICVF");
801 /* Register Misc interrupt */
802 ret = request_irq(nic->msix_entries[irq].vector,
803 nicvf_misc_intr_handler, 0, nic->irq_name[irq], nic);
804
805 if (ret)
806 return ret;
807 nic->irq_allocated[irq] = true;
808
809 /* Enable mailbox interrupt */
810 nicvf_enable_intr(nic, NICVF_INTR_MBOX, 0);
811
812 /* Check if VF is able to communicate with PF */
813 if (!nicvf_check_pf_ready(nic)) {
814 nicvf_disable_intr(nic, NICVF_INTR_MBOX, 0);
815 nicvf_unregister_interrupts(nic);
816 return 1;
817 }
818
819 return 0;
820}
821
822static netdev_tx_t nicvf_xmit(struct sk_buff *skb, struct net_device *netdev)
823{
824 struct nicvf *nic = netdev_priv(netdev);
825 int qid = skb_get_queue_mapping(skb);
826 struct netdev_queue *txq = netdev_get_tx_queue(netdev, qid);
827
828 /* Check for minimum packet length */
829 if (skb->len <= ETH_HLEN) {
830 dev_kfree_skb(skb);
831 return NETDEV_TX_OK;
832 }
833
834 if (!nicvf_sq_append_skb(nic, skb) && !netif_tx_queue_stopped(txq)) {
835 netif_tx_stop_queue(txq);
836 nic->drv_stats.tx_busy++;
837 if (netif_msg_tx_err(nic))
838 netdev_warn(netdev,
839 "%s: Transmit ring full, stopping SQ%d\n",
840 netdev->name, qid);
841
842 return NETDEV_TX_BUSY;
843 }
844
845 return NETDEV_TX_OK;
846}
847
848int nicvf_stop(struct net_device *netdev)
849{
850 int irq, qidx;
851 struct nicvf *nic = netdev_priv(netdev);
852 struct queue_set *qs = nic->qs;
853 struct nicvf_cq_poll *cq_poll = NULL;
854 union nic_mbx mbx = {};
855
856 mbx.msg.msg = NIC_MBOX_MSG_SHUTDOWN;
857 nicvf_send_msg_to_pf(nic, &mbx);
858
859 netif_carrier_off(netdev);
860 netif_tx_disable(netdev);
861
862 /* Disable RBDR & QS error interrupts */
863 for (qidx = 0; qidx < qs->rbdr_cnt; qidx++) {
864 nicvf_disable_intr(nic, NICVF_INTR_RBDR, qidx);
865 nicvf_clear_intr(nic, NICVF_INTR_RBDR, qidx);
866 }
867 nicvf_disable_intr(nic, NICVF_INTR_QS_ERR, 0);
868 nicvf_clear_intr(nic, NICVF_INTR_QS_ERR, 0);
869
870 /* Wait for pending IRQ handlers to finish */
871 for (irq = 0; irq < nic->num_vec; irq++)
872 synchronize_irq(nic->msix_entries[irq].vector);
873
874 tasklet_kill(&nic->rbdr_task);
875 tasklet_kill(&nic->qs_err_task);
876 if (nic->rb_work_scheduled)
877 cancel_delayed_work_sync(&nic->rbdr_work);
878
879 for (qidx = 0; qidx < nic->qs->cq_cnt; qidx++) {
880 cq_poll = nic->napi[qidx];
881 if (!cq_poll)
882 continue;
883 nic->napi[qidx] = NULL;
884 napi_synchronize(&cq_poll->napi);
885 /* CQ intr is enabled while napi_complete,
886 * so disable it now
887 */
888 nicvf_disable_intr(nic, NICVF_INTR_CQ, qidx);
889 nicvf_clear_intr(nic, NICVF_INTR_CQ, qidx);
890 napi_disable(&cq_poll->napi);
891 netif_napi_del(&cq_poll->napi);
892 kfree(cq_poll);
893 }
894
895 /* Free resources */
896 nicvf_config_data_transfer(nic, false);
897
898 /* Disable HW Qset */
899 nicvf_qset_config(nic, false);
900
901 /* disable mailbox interrupt */
902 nicvf_disable_intr(nic, NICVF_INTR_MBOX, 0);
903
904 nicvf_unregister_interrupts(nic);
905
906 return 0;
907}
908
909int nicvf_open(struct net_device *netdev)
910{
911 int err, qidx;
912 struct nicvf *nic = netdev_priv(netdev);
913 struct queue_set *qs = nic->qs;
914 struct nicvf_cq_poll *cq_poll = NULL;
915
916 nic->mtu = netdev->mtu;
917
918 netif_carrier_off(netdev);
919
920 err = nicvf_register_misc_interrupt(nic);
921 if (err)
922 return err;
923
924 /* Register NAPI handler for processing CQEs */
925 for (qidx = 0; qidx < qs->cq_cnt; qidx++) {
926 cq_poll = kzalloc(sizeof(*cq_poll), GFP_KERNEL);
927 if (!cq_poll) {
928 err = -ENOMEM;
929 goto napi_del;
930 }
931 cq_poll->cq_idx = qidx;
932 netif_napi_add(netdev, &cq_poll->napi, nicvf_poll,
933 NAPI_POLL_WEIGHT);
934 napi_enable(&cq_poll->napi);
935 nic->napi[qidx] = cq_poll;
936 }
937
938 /* Check if we got MAC address from PF or else generate a radom MAC */
939 if (is_zero_ether_addr(netdev->dev_addr)) {
940 eth_hw_addr_random(netdev);
941 nicvf_hw_set_mac_addr(nic, netdev);
942 }
943
944 /* Init tasklet for handling Qset err interrupt */
945 tasklet_init(&nic->qs_err_task, nicvf_handle_qs_err,
946 (unsigned long)nic);
947
948 /* Init RBDR tasklet which will refill RBDR */
949 tasklet_init(&nic->rbdr_task, nicvf_rbdr_task,
950 (unsigned long)nic);
951 INIT_DELAYED_WORK(&nic->rbdr_work, nicvf_rbdr_work);
952
953 /* Configure CPI alorithm */
954 nic->cpi_alg = cpi_alg;
955 nicvf_config_cpi(nic);
956
957 /* Configure receive side scaling */
958 nicvf_rss_init(nic);
959
960 err = nicvf_register_interrupts(nic);
961 if (err)
962 goto cleanup;
963
964 /* Initialize the queues */
965 err = nicvf_init_resources(nic);
966 if (err)
967 goto cleanup;
968
969 /* Make sure queue initialization is written */
970 wmb();
971
972 nicvf_reg_write(nic, NIC_VF_INT, -1);
973 /* Enable Qset err interrupt */
974 nicvf_enable_intr(nic, NICVF_INTR_QS_ERR, 0);
975
976 /* Enable completion queue interrupt */
977 for (qidx = 0; qidx < qs->cq_cnt; qidx++)
978 nicvf_enable_intr(nic, NICVF_INTR_CQ, qidx);
979
980 /* Enable RBDR threshold interrupt */
981 for (qidx = 0; qidx < qs->rbdr_cnt; qidx++)
982 nicvf_enable_intr(nic, NICVF_INTR_RBDR, qidx);
983
984 netif_carrier_on(netdev);
985 netif_tx_start_all_queues(netdev);
986
987 return 0;
988cleanup:
989 nicvf_disable_intr(nic, NICVF_INTR_MBOX, 0);
990 nicvf_unregister_interrupts(nic);
991napi_del:
992 for (qidx = 0; qidx < qs->cq_cnt; qidx++) {
993 cq_poll = nic->napi[qidx];
994 if (!cq_poll)
995 continue;
996 napi_disable(&cq_poll->napi);
997 netif_napi_del(&cq_poll->napi);
998 kfree(cq_poll);
999 nic->napi[qidx] = NULL;
1000 }
1001 return err;
1002}
1003
1004static int nicvf_update_hw_max_frs(struct nicvf *nic, int mtu)
1005{
1006 union nic_mbx mbx = {};
1007
1008 mbx.frs.msg = NIC_MBOX_MSG_SET_MAX_FRS;
1009 mbx.frs.max_frs = mtu;
1010 mbx.frs.vf_id = nic->vf_id;
1011
1012 return nicvf_send_msg_to_pf(nic, &mbx);
1013}
1014
1015static int nicvf_change_mtu(struct net_device *netdev, int new_mtu)
1016{
1017 struct nicvf *nic = netdev_priv(netdev);
1018
1019 if (new_mtu > NIC_HW_MAX_FRS)
1020 return -EINVAL;
1021
1022 if (new_mtu < NIC_HW_MIN_FRS)
1023 return -EINVAL;
1024
1025 if (nicvf_update_hw_max_frs(nic, new_mtu))
1026 return -EINVAL;
1027 netdev->mtu = new_mtu;
1028 nic->mtu = new_mtu;
1029
1030 return 0;
1031}
1032
1033static int nicvf_set_mac_address(struct net_device *netdev, void *p)
1034{
1035 struct sockaddr *addr = p;
1036 struct nicvf *nic = netdev_priv(netdev);
1037
1038 if (!is_valid_ether_addr(addr->sa_data))
1039 return -EADDRNOTAVAIL;
1040
1041 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
1042
1043 if (nic->msix_enabled)
1044 if (nicvf_hw_set_mac_addr(nic, netdev))
1045 return -EBUSY;
1046
1047 return 0;
1048}
1049
1050static void nicvf_read_bgx_stats(struct nicvf *nic, struct bgx_stats_msg *bgx)
1051{
1052 if (bgx->rx)
1053 nic->bgx_stats.rx_stats[bgx->idx] = bgx->stats;
1054 else
1055 nic->bgx_stats.tx_stats[bgx->idx] = bgx->stats;
1056}
1057
1058void nicvf_update_lmac_stats(struct nicvf *nic)
1059{
1060 int stat = 0;
1061 union nic_mbx mbx = {};
1062 int timeout;
1063
1064 if (!netif_running(nic->netdev))
1065 return;
1066
1067 mbx.bgx_stats.msg = NIC_MBOX_MSG_BGX_STATS;
1068 mbx.bgx_stats.vf_id = nic->vf_id;
1069 /* Rx stats */
1070 mbx.bgx_stats.rx = 1;
1071 while (stat < BGX_RX_STATS_COUNT) {
1072 nic->bgx_stats_acked = 0;
1073 mbx.bgx_stats.idx = stat;
1074 nicvf_send_msg_to_pf(nic, &mbx);
1075 timeout = 0;
1076 while ((!nic->bgx_stats_acked) && (timeout < 10)) {
1077 msleep(2);
1078 timeout++;
1079 }
1080 stat++;
1081 }
1082
1083 stat = 0;
1084
1085 /* Tx stats */
1086 mbx.bgx_stats.rx = 0;
1087 while (stat < BGX_TX_STATS_COUNT) {
1088 nic->bgx_stats_acked = 0;
1089 mbx.bgx_stats.idx = stat;
1090 nicvf_send_msg_to_pf(nic, &mbx);
1091 timeout = 0;
1092 while ((!nic->bgx_stats_acked) && (timeout < 10)) {
1093 msleep(2);
1094 timeout++;
1095 }
1096 stat++;
1097 }
1098}
1099
1100void nicvf_update_stats(struct nicvf *nic)
1101{
1102 int qidx;
1103 struct nicvf_hw_stats *stats = &nic->stats;
1104 struct nicvf_drv_stats *drv_stats = &nic->drv_stats;
1105 struct queue_set *qs = nic->qs;
1106
1107#define GET_RX_STATS(reg) \
1108 nicvf_reg_read(nic, NIC_VNIC_RX_STAT_0_13 | (reg << 3))
1109#define GET_TX_STATS(reg) \
1110 nicvf_reg_read(nic, NIC_VNIC_TX_STAT_0_4 | (reg << 3))
1111
1112 stats->rx_bytes_ok = GET_RX_STATS(RX_OCTS);
1113 stats->rx_ucast_frames_ok = GET_RX_STATS(RX_UCAST);
1114 stats->rx_bcast_frames_ok = GET_RX_STATS(RX_BCAST);
1115 stats->rx_mcast_frames_ok = GET_RX_STATS(RX_MCAST);
1116 stats->rx_fcs_errors = GET_RX_STATS(RX_FCS);
1117 stats->rx_l2_errors = GET_RX_STATS(RX_L2ERR);
1118 stats->rx_drop_red = GET_RX_STATS(RX_RED);
1119 stats->rx_drop_overrun = GET_RX_STATS(RX_ORUN);
1120 stats->rx_drop_bcast = GET_RX_STATS(RX_DRP_BCAST);
1121 stats->rx_drop_mcast = GET_RX_STATS(RX_DRP_MCAST);
1122 stats->rx_drop_l3_bcast = GET_RX_STATS(RX_DRP_L3BCAST);
1123 stats->rx_drop_l3_mcast = GET_RX_STATS(RX_DRP_L3MCAST);
1124
1125 stats->tx_bytes_ok = GET_TX_STATS(TX_OCTS);
1126 stats->tx_ucast_frames_ok = GET_TX_STATS(TX_UCAST);
1127 stats->tx_bcast_frames_ok = GET_TX_STATS(TX_BCAST);
1128 stats->tx_mcast_frames_ok = GET_TX_STATS(TX_MCAST);
1129 stats->tx_drops = GET_TX_STATS(TX_DROP);
1130
1131 drv_stats->rx_frames_ok = stats->rx_ucast_frames_ok +
1132 stats->rx_bcast_frames_ok +
1133 stats->rx_mcast_frames_ok;
1134 drv_stats->tx_frames_ok = stats->tx_ucast_frames_ok +
1135 stats->tx_bcast_frames_ok +
1136 stats->tx_mcast_frames_ok;
1137 drv_stats->rx_drops = stats->rx_drop_red +
1138 stats->rx_drop_overrun;
1139 drv_stats->tx_drops = stats->tx_drops;
1140
1141 /* Update RQ and SQ stats */
1142 for (qidx = 0; qidx < qs->rq_cnt; qidx++)
1143 nicvf_update_rq_stats(nic, qidx);
1144 for (qidx = 0; qidx < qs->sq_cnt; qidx++)
1145 nicvf_update_sq_stats(nic, qidx);
1146}
1147
1148struct rtnl_link_stats64 *nicvf_get_stats64(struct net_device *netdev,
1149 struct rtnl_link_stats64 *stats)
1150{
1151 struct nicvf *nic = netdev_priv(netdev);
1152 struct nicvf_hw_stats *hw_stats = &nic->stats;
1153 struct nicvf_drv_stats *drv_stats = &nic->drv_stats;
1154
1155 nicvf_update_stats(nic);
1156
1157 stats->rx_bytes = hw_stats->rx_bytes_ok;
1158 stats->rx_packets = drv_stats->rx_frames_ok;
1159 stats->rx_dropped = drv_stats->rx_drops;
1160
1161 stats->tx_bytes = hw_stats->tx_bytes_ok;
1162 stats->tx_packets = drv_stats->tx_frames_ok;
1163 stats->tx_dropped = drv_stats->tx_drops;
1164
1165 return stats;
1166}
1167
1168static void nicvf_tx_timeout(struct net_device *dev)
1169{
1170 struct nicvf *nic = netdev_priv(dev);
1171
1172 if (netif_msg_tx_err(nic))
1173 netdev_warn(dev, "%s: Transmit timed out, resetting\n",
1174 dev->name);
1175
1176 schedule_work(&nic->reset_task);
1177}
1178
1179static void nicvf_reset_task(struct work_struct *work)
1180{
1181 struct nicvf *nic;
1182
1183 nic = container_of(work, struct nicvf, reset_task);
1184
1185 if (!netif_running(nic->netdev))
1186 return;
1187
1188 nicvf_stop(nic->netdev);
1189 nicvf_open(nic->netdev);
1190 nic->netdev->trans_start = jiffies;
1191}
1192
1193static const struct net_device_ops nicvf_netdev_ops = {
1194 .ndo_open = nicvf_open,
1195 .ndo_stop = nicvf_stop,
1196 .ndo_start_xmit = nicvf_xmit,
1197 .ndo_change_mtu = nicvf_change_mtu,
1198 .ndo_set_mac_address = nicvf_set_mac_address,
1199 .ndo_get_stats64 = nicvf_get_stats64,
1200 .ndo_tx_timeout = nicvf_tx_timeout,
1201};
1202
1203static int nicvf_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
1204{
1205 struct device *dev = &pdev->dev;
1206 struct net_device *netdev;
1207 struct nicvf *nic;
1208 struct queue_set *qs;
1209 int err;
1210
1211 err = pci_enable_device(pdev);
1212 if (err) {
1213 dev_err(dev, "Failed to enable PCI device\n");
1214 return err;
1215 }
1216
1217 err = pci_request_regions(pdev, DRV_NAME);
1218 if (err) {
1219 dev_err(dev, "PCI request regions failed 0x%x\n", err);
1220 goto err_disable_device;
1221 }
1222
1223 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(48));
1224 if (err) {
1225 dev_err(dev, "Unable to get usable DMA configuration\n");
1226 goto err_release_regions;
1227 }
1228
1229 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(48));
1230 if (err) {
1231 dev_err(dev, "unable to get 48-bit DMA for consistent allocations\n");
1232 goto err_release_regions;
1233 }
1234
1235 netdev = alloc_etherdev_mqs(sizeof(struct nicvf),
1236 MAX_RCV_QUEUES_PER_QS,
1237 MAX_SND_QUEUES_PER_QS);
1238 if (!netdev) {
1239 err = -ENOMEM;
1240 goto err_release_regions;
1241 }
1242
1243 pci_set_drvdata(pdev, netdev);
1244
1245 SET_NETDEV_DEV(netdev, &pdev->dev);
1246
1247 nic = netdev_priv(netdev);
1248 nic->netdev = netdev;
1249 nic->pdev = pdev;
1250
1251 /* MAP VF's configuration registers */
1252 nic->reg_base = pcim_iomap(pdev, PCI_CFG_REG_BAR_NUM, 0);
1253 if (!nic->reg_base) {
1254 dev_err(dev, "Cannot map config register space, aborting\n");
1255 err = -ENOMEM;
1256 goto err_free_netdev;
1257 }
1258
1259 err = nicvf_set_qset_resources(nic);
1260 if (err)
1261 goto err_free_netdev;
1262
1263 qs = nic->qs;
1264
1265 err = nicvf_set_real_num_queues(netdev, qs->sq_cnt, qs->rq_cnt);
1266 if (err)
1267 goto err_free_netdev;
1268
1269 /* Check if PF is alive and get MAC address for this VF */
1270 err = nicvf_register_misc_interrupt(nic);
1271 if (err)
1272 goto err_free_netdev;
1273
1274 netdev->features |= (NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG |
1275 NETIF_F_TSO | NETIF_F_GRO);
1276 netdev->hw_features = netdev->features;
1277
1278 netdev->netdev_ops = &nicvf_netdev_ops;
1279
1280 INIT_WORK(&nic->reset_task, nicvf_reset_task);
1281
1282 err = register_netdev(netdev);
1283 if (err) {
1284 dev_err(dev, "Failed to register netdevice\n");
1285 goto err_unregister_interrupts;
1286 }
1287
1288 nic->msg_enable = debug;
1289
1290 nicvf_set_ethtool_ops(netdev);
1291
1292 return 0;
1293
1294err_unregister_interrupts:
1295 nicvf_unregister_interrupts(nic);
1296err_free_netdev:
1297 pci_set_drvdata(pdev, NULL);
1298 free_netdev(netdev);
1299err_release_regions:
1300 pci_release_regions(pdev);
1301err_disable_device:
1302 pci_disable_device(pdev);
1303 return err;
1304}
1305
1306static void nicvf_remove(struct pci_dev *pdev)
1307{
1308 struct net_device *netdev = pci_get_drvdata(pdev);
1309 struct nicvf *nic = netdev_priv(netdev);
1310
1311 unregister_netdev(netdev);
1312 nicvf_unregister_interrupts(nic);
1313 pci_set_drvdata(pdev, NULL);
1314 free_netdev(netdev);
1315 pci_release_regions(pdev);
1316 pci_disable_device(pdev);
1317}
1318
1319static struct pci_driver nicvf_driver = {
1320 .name = DRV_NAME,
1321 .id_table = nicvf_id_table,
1322 .probe = nicvf_probe,
1323 .remove = nicvf_remove,
1324};
1325
1326static int __init nicvf_init_module(void)
1327{
1328 pr_info("%s, ver %s\n", DRV_NAME, DRV_VERSION);
1329
1330 return pci_register_driver(&nicvf_driver);
1331}
1332
1333static void __exit nicvf_cleanup_module(void)
1334{
1335 pci_unregister_driver(&nicvf_driver);
1336}
1337
1338module_init(nicvf_init_module);
1339module_exit(nicvf_cleanup_module);
Linux kernel - Deliverables
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