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8199d3a7 CL |
1 | /***************************************************************************** |
2 | * * | |
3 | * File: sge.c * | |
559fb51b SB |
4 | * $Revision: 1.26 $ * |
5 | * $Date: 2005/06/21 18:29:48 $ * | |
8199d3a7 CL |
6 | * Description: * |
7 | * DMA engine. * | |
8 | * part of the Chelsio 10Gb Ethernet Driver. * | |
9 | * * | |
10 | * This program is free software; you can redistribute it and/or modify * | |
11 | * it under the terms of the GNU General Public License, version 2, as * | |
12 | * published by the Free Software Foundation. * | |
13 | * * | |
14 | * You should have received a copy of the GNU General Public License along * | |
15 | * with this program; if not, write to the Free Software Foundation, Inc., * | |
16 | * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * | |
17 | * * | |
18 | * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR IMPLIED * | |
19 | * WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF * | |
20 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. * | |
21 | * * | |
22 | * http://www.chelsio.com * | |
23 | * * | |
24 | * Copyright (c) 2003 - 2005 Chelsio Communications, Inc. * | |
25 | * All rights reserved. * | |
26 | * * | |
27 | * Maintainers: maintainers@chelsio.com * | |
28 | * * | |
29 | * Authors: Dimitrios Michailidis <dm@chelsio.com> * | |
30 | * Tina Yang <tainay@chelsio.com> * | |
31 | * Felix Marti <felix@chelsio.com> * | |
32 | * Scott Bardone <sbardone@chelsio.com> * | |
33 | * Kurt Ottaway <kottaway@chelsio.com> * | |
34 | * Frank DiMambro <frank@chelsio.com> * | |
35 | * * | |
36 | * History: * | |
37 | * * | |
38 | ****************************************************************************/ | |
39 | ||
40 | #include "common.h" | |
41 | ||
8199d3a7 CL |
42 | #include <linux/types.h> |
43 | #include <linux/errno.h> | |
44 | #include <linux/pci.h> | |
f1d3d38a | 45 | #include <linux/ktime.h> |
8199d3a7 CL |
46 | #include <linux/netdevice.h> |
47 | #include <linux/etherdevice.h> | |
48 | #include <linux/if_vlan.h> | |
49 | #include <linux/skbuff.h> | |
50 | #include <linux/init.h> | |
51 | #include <linux/mm.h> | |
f1d3d38a | 52 | #include <linux/tcp.h> |
8199d3a7 CL |
53 | #include <linux/ip.h> |
54 | #include <linux/in.h> | |
55 | #include <linux/if_arp.h> | |
5a0e3ad6 | 56 | #include <linux/slab.h> |
70c71606 | 57 | #include <linux/prefetch.h> |
8199d3a7 CL |
58 | |
59 | #include "cpl5_cmd.h" | |
60 | #include "sge.h" | |
61 | #include "regs.h" | |
62 | #include "espi.h" | |
63 | ||
f1d3d38a SH |
64 | /* This belongs in if_ether.h */ |
65 | #define ETH_P_CPL5 0xf | |
8199d3a7 CL |
66 | |
67 | #define SGE_CMDQ_N 2 | |
68 | #define SGE_FREELQ_N 2 | |
559fb51b | 69 | #define SGE_CMDQ0_E_N 1024 |
8199d3a7 CL |
70 | #define SGE_CMDQ1_E_N 128 |
71 | #define SGE_FREEL_SIZE 4096 | |
72 | #define SGE_JUMBO_FREEL_SIZE 512 | |
73 | #define SGE_FREEL_REFILL_THRESH 16 | |
74 | #define SGE_RESPQ_E_N 1024 | |
559fb51b | 75 | #define SGE_INTRTIMER_NRES 1000 |
8199d3a7 | 76 | #define SGE_RX_SM_BUF_SIZE 1536 |
f1d3d38a | 77 | #define SGE_TX_DESC_MAX_PLEN 16384 |
8199d3a7 | 78 | |
559fb51b SB |
79 | #define SGE_RESPQ_REPLENISH_THRES (SGE_RESPQ_E_N / 4) |
80 | ||
81 | /* | |
82 | * Period of the TX buffer reclaim timer. This timer does not need to run | |
83 | * frequently as TX buffers are usually reclaimed by new TX packets. | |
84 | */ | |
85 | #define TX_RECLAIM_PERIOD (HZ / 4) | |
8199d3a7 | 86 | |
559fb51b SB |
87 | #define M_CMD_LEN 0x7fffffff |
88 | #define V_CMD_LEN(v) (v) | |
89 | #define G_CMD_LEN(v) ((v) & M_CMD_LEN) | |
90 | #define V_CMD_GEN1(v) ((v) << 31) | |
91 | #define V_CMD_GEN2(v) (v) | |
92 | #define F_CMD_DATAVALID (1 << 1) | |
93 | #define F_CMD_SOP (1 << 2) | |
94 | #define V_CMD_EOP(v) ((v) << 3) | |
95 | ||
8199d3a7 | 96 | /* |
559fb51b | 97 | * Command queue, receive buffer list, and response queue descriptors. |
8199d3a7 CL |
98 | */ |
99 | #if defined(__BIG_ENDIAN_BITFIELD) | |
100 | struct cmdQ_e { | |
559fb51b SB |
101 | u32 addr_lo; |
102 | u32 len_gen; | |
103 | u32 flags; | |
104 | u32 addr_hi; | |
8199d3a7 CL |
105 | }; |
106 | ||
107 | struct freelQ_e { | |
559fb51b SB |
108 | u32 addr_lo; |
109 | u32 len_gen; | |
110 | u32 gen2; | |
111 | u32 addr_hi; | |
8199d3a7 CL |
112 | }; |
113 | ||
114 | struct respQ_e { | |
115 | u32 Qsleeping : 4; | |
116 | u32 Cmdq1CreditReturn : 5; | |
117 | u32 Cmdq1DmaComplete : 5; | |
118 | u32 Cmdq0CreditReturn : 5; | |
119 | u32 Cmdq0DmaComplete : 5; | |
120 | u32 FreelistQid : 2; | |
121 | u32 CreditValid : 1; | |
122 | u32 DataValid : 1; | |
123 | u32 Offload : 1; | |
124 | u32 Eop : 1; | |
125 | u32 Sop : 1; | |
126 | u32 GenerationBit : 1; | |
127 | u32 BufferLength; | |
128 | }; | |
8199d3a7 CL |
129 | #elif defined(__LITTLE_ENDIAN_BITFIELD) |
130 | struct cmdQ_e { | |
559fb51b SB |
131 | u32 len_gen; |
132 | u32 addr_lo; | |
133 | u32 addr_hi; | |
134 | u32 flags; | |
8199d3a7 CL |
135 | }; |
136 | ||
137 | struct freelQ_e { | |
559fb51b SB |
138 | u32 len_gen; |
139 | u32 addr_lo; | |
140 | u32 addr_hi; | |
141 | u32 gen2; | |
8199d3a7 CL |
142 | }; |
143 | ||
144 | struct respQ_e { | |
145 | u32 BufferLength; | |
146 | u32 GenerationBit : 1; | |
147 | u32 Sop : 1; | |
148 | u32 Eop : 1; | |
149 | u32 Offload : 1; | |
150 | u32 DataValid : 1; | |
151 | u32 CreditValid : 1; | |
152 | u32 FreelistQid : 2; | |
153 | u32 Cmdq0DmaComplete : 5; | |
154 | u32 Cmdq0CreditReturn : 5; | |
155 | u32 Cmdq1DmaComplete : 5; | |
156 | u32 Cmdq1CreditReturn : 5; | |
157 | u32 Qsleeping : 4; | |
158 | } ; | |
159 | #endif | |
160 | ||
161 | /* | |
162 | * SW Context Command and Freelist Queue Descriptors | |
163 | */ | |
164 | struct cmdQ_ce { | |
165 | struct sk_buff *skb; | |
094f92a6 FT |
166 | DEFINE_DMA_UNMAP_ADDR(dma_addr); |
167 | DEFINE_DMA_UNMAP_LEN(dma_len); | |
8199d3a7 CL |
168 | }; |
169 | ||
170 | struct freelQ_ce { | |
171 | struct sk_buff *skb; | |
094f92a6 FT |
172 | DEFINE_DMA_UNMAP_ADDR(dma_addr); |
173 | DEFINE_DMA_UNMAP_LEN(dma_len); | |
8199d3a7 CL |
174 | }; |
175 | ||
176 | /* | |
559fb51b | 177 | * SW command, freelist and response rings |
8199d3a7 CL |
178 | */ |
179 | struct cmdQ { | |
559fb51b SB |
180 | unsigned long status; /* HW DMA fetch status */ |
181 | unsigned int in_use; /* # of in-use command descriptors */ | |
182 | unsigned int size; /* # of descriptors */ | |
f1d3d38a SH |
183 | unsigned int processed; /* total # of descs HW has processed */ |
184 | unsigned int cleaned; /* total # of descs SW has reclaimed */ | |
185 | unsigned int stop_thres; /* SW TX queue suspend threshold */ | |
559fb51b SB |
186 | u16 pidx; /* producer index (SW) */ |
187 | u16 cidx; /* consumer index (HW) */ | |
188 | u8 genbit; /* current generation (=valid) bit */ | |
f1d3d38a | 189 | u8 sop; /* is next entry start of packet? */ |
559fb51b SB |
190 | struct cmdQ_e *entries; /* HW command descriptor Q */ |
191 | struct cmdQ_ce *centries; /* SW command context descriptor Q */ | |
559fb51b | 192 | dma_addr_t dma_addr; /* DMA addr HW command descriptor Q */ |
356bd146 | 193 | spinlock_t lock; /* Lock to protect cmdQ enqueuing */ |
8199d3a7 CL |
194 | }; |
195 | ||
196 | struct freelQ { | |
559fb51b SB |
197 | unsigned int credits; /* # of available RX buffers */ |
198 | unsigned int size; /* free list capacity */ | |
199 | u16 pidx; /* producer index (SW) */ | |
200 | u16 cidx; /* consumer index (HW) */ | |
8199d3a7 | 201 | u16 rx_buffer_size; /* Buffer size on this free list */ |
f1d3d38a SH |
202 | u16 dma_offset; /* DMA offset to align IP headers */ |
203 | u16 recycleq_idx; /* skb recycle q to use */ | |
559fb51b SB |
204 | u8 genbit; /* current generation (=valid) bit */ |
205 | struct freelQ_e *entries; /* HW freelist descriptor Q */ | |
206 | struct freelQ_ce *centries; /* SW freelist context descriptor Q */ | |
207 | dma_addr_t dma_addr; /* DMA addr HW freelist descriptor Q */ | |
8199d3a7 CL |
208 | }; |
209 | ||
210 | struct respQ { | |
559fb51b SB |
211 | unsigned int credits; /* credits to be returned to SGE */ |
212 | unsigned int size; /* # of response Q descriptors */ | |
213 | u16 cidx; /* consumer index (SW) */ | |
214 | u8 genbit; /* current generation(=valid) bit */ | |
8199d3a7 | 215 | struct respQ_e *entries; /* HW response descriptor Q */ |
559fb51b SB |
216 | dma_addr_t dma_addr; /* DMA addr HW response descriptor Q */ |
217 | }; | |
218 | ||
219 | /* Bit flags for cmdQ.status */ | |
220 | enum { | |
221 | CMDQ_STAT_RUNNING = 1, /* fetch engine is running */ | |
222 | CMDQ_STAT_LAST_PKT_DB = 2 /* last packet rung the doorbell */ | |
8199d3a7 CL |
223 | }; |
224 | ||
f1d3d38a SH |
225 | /* T204 TX SW scheduler */ |
226 | ||
227 | /* Per T204 TX port */ | |
228 | struct sched_port { | |
229 | unsigned int avail; /* available bits - quota */ | |
230 | unsigned int drain_bits_per_1024ns; /* drain rate */ | |
231 | unsigned int speed; /* drain rate, mbps */ | |
232 | unsigned int mtu; /* mtu size */ | |
233 | struct sk_buff_head skbq; /* pending skbs */ | |
234 | }; | |
235 | ||
236 | /* Per T204 device */ | |
237 | struct sched { | |
238 | ktime_t last_updated; /* last time quotas were computed */ | |
356bd146 FR |
239 | unsigned int max_avail; /* max bits to be sent to any port */ |
240 | unsigned int port; /* port index (round robin ports) */ | |
241 | unsigned int num; /* num skbs in per port queues */ | |
f1d3d38a SH |
242 | struct sched_port p[MAX_NPORTS]; |
243 | struct tasklet_struct sched_tsk;/* tasklet used to run scheduler */ | |
244 | }; | |
245 | static void restart_sched(unsigned long); | |
246 | ||
247 | ||
8199d3a7 CL |
248 | /* |
249 | * Main SGE data structure | |
250 | * | |
251 | * Interrupts are handled by a single CPU and it is likely that on a MP system | |
252 | * the application is migrated to another CPU. In that scenario, we try to | |
3ad2f3fb | 253 | * separate the RX(in irq context) and TX state in order to decrease memory |
8199d3a7 CL |
254 | * contention. |
255 | */ | |
256 | struct sge { | |
356bd146 | 257 | struct adapter *adapter; /* adapter backpointer */ |
559fb51b | 258 | struct net_device *netdev; /* netdevice backpointer */ |
356bd146 FR |
259 | struct freelQ freelQ[SGE_FREELQ_N]; /* buffer free lists */ |
260 | struct respQ respQ; /* response Q */ | |
559fb51b | 261 | unsigned long stopped_tx_queues; /* bitmap of suspended Tx queues */ |
8199d3a7 CL |
262 | unsigned int rx_pkt_pad; /* RX padding for L2 packets */ |
263 | unsigned int jumbo_fl; /* jumbo freelist Q index */ | |
559fb51b | 264 | unsigned int intrtimer_nres; /* no-resource interrupt timer */ |
f1d3d38a | 265 | unsigned int fixed_intrtimer;/* non-adaptive interrupt timer */ |
559fb51b SB |
266 | struct timer_list tx_reclaim_timer; /* reclaims TX buffers */ |
267 | struct timer_list espibug_timer; | |
f1d3d38a SH |
268 | unsigned long espibug_timeout; |
269 | struct sk_buff *espibug_skb[MAX_NPORTS]; | |
559fb51b SB |
270 | u32 sge_control; /* shadow value of sge control reg */ |
271 | struct sge_intr_counts stats; | |
47d74275 | 272 | struct sge_port_stats __percpu *port_stats[MAX_NPORTS]; |
f1d3d38a | 273 | struct sched *tx_sched; |
559fb51b | 274 | struct cmdQ cmdQ[SGE_CMDQ_N] ____cacheline_aligned_in_smp; |
8199d3a7 CL |
275 | }; |
276 | ||
215faf9c JP |
277 | static const u8 ch_mac_addr[ETH_ALEN] = { |
278 | 0x0, 0x7, 0x43, 0x0, 0x0, 0x0 | |
279 | }; | |
280 | ||
f1d3d38a SH |
281 | /* |
282 | * stop tasklet and free all pending skb's | |
283 | */ | |
284 | static void tx_sched_stop(struct sge *sge) | |
285 | { | |
286 | struct sched *s = sge->tx_sched; | |
287 | int i; | |
288 | ||
289 | tasklet_kill(&s->sched_tsk); | |
290 | ||
291 | for (i = 0; i < MAX_NPORTS; i++) | |
292 | __skb_queue_purge(&s->p[s->port].skbq); | |
293 | } | |
294 | ||
295 | /* | |
296 | * t1_sched_update_parms() is called when the MTU or link speed changes. It | |
297 | * re-computes scheduler parameters to scope with the change. | |
298 | */ | |
299 | unsigned int t1_sched_update_parms(struct sge *sge, unsigned int port, | |
300 | unsigned int mtu, unsigned int speed) | |
301 | { | |
302 | struct sched *s = sge->tx_sched; | |
303 | struct sched_port *p = &s->p[port]; | |
304 | unsigned int max_avail_segs; | |
305 | ||
306 | pr_debug("t1_sched_update_params mtu=%d speed=%d\n", mtu, speed); | |
307 | if (speed) | |
308 | p->speed = speed; | |
309 | if (mtu) | |
310 | p->mtu = mtu; | |
311 | ||
312 | if (speed || mtu) { | |
313 | unsigned long long drain = 1024ULL * p->speed * (p->mtu - 40); | |
314 | do_div(drain, (p->mtu + 50) * 1000); | |
315 | p->drain_bits_per_1024ns = (unsigned int) drain; | |
316 | ||
317 | if (p->speed < 1000) | |
318 | p->drain_bits_per_1024ns = | |
319 | 90 * p->drain_bits_per_1024ns / 100; | |
320 | } | |
321 | ||
322 | if (board_info(sge->adapter)->board == CHBT_BOARD_CHT204) { | |
323 | p->drain_bits_per_1024ns -= 16; | |
324 | s->max_avail = max(4096U, p->mtu + 16 + 14 + 4); | |
325 | max_avail_segs = max(1U, 4096 / (p->mtu - 40)); | |
326 | } else { | |
327 | s->max_avail = 16384; | |
328 | max_avail_segs = max(1U, 9000 / (p->mtu - 40)); | |
329 | } | |
330 | ||
331 | pr_debug("t1_sched_update_parms: mtu %u speed %u max_avail %u " | |
332 | "max_avail_segs %u drain_bits_per_1024ns %u\n", p->mtu, | |
333 | p->speed, s->max_avail, max_avail_segs, | |
334 | p->drain_bits_per_1024ns); | |
335 | ||
336 | return max_avail_segs * (p->mtu - 40); | |
337 | } | |
338 | ||
68d579fb AB |
339 | #if 0 |
340 | ||
f1d3d38a SH |
341 | /* |
342 | * t1_sched_max_avail_bytes() tells the scheduler the maximum amount of | |
343 | * data that can be pushed per port. | |
344 | */ | |
345 | void t1_sched_set_max_avail_bytes(struct sge *sge, unsigned int val) | |
346 | { | |
347 | struct sched *s = sge->tx_sched; | |
348 | unsigned int i; | |
349 | ||
350 | s->max_avail = val; | |
351 | for (i = 0; i < MAX_NPORTS; i++) | |
352 | t1_sched_update_parms(sge, i, 0, 0); | |
353 | } | |
354 | ||
355 | /* | |
356 | * t1_sched_set_drain_bits_per_us() tells the scheduler at which rate a port | |
357 | * is draining. | |
358 | */ | |
359 | void t1_sched_set_drain_bits_per_us(struct sge *sge, unsigned int port, | |
360 | unsigned int val) | |
361 | { | |
362 | struct sched *s = sge->tx_sched; | |
363 | struct sched_port *p = &s->p[port]; | |
364 | p->drain_bits_per_1024ns = val * 1024 / 1000; | |
365 | t1_sched_update_parms(sge, port, 0, 0); | |
366 | } | |
367 | ||
68d579fb AB |
368 | #endif /* 0 */ |
369 | ||
f1d3d38a SH |
370 | /* |
371 | * tx_sched_init() allocates resources and does basic initialization. | |
372 | */ | |
373 | static int tx_sched_init(struct sge *sge) | |
374 | { | |
375 | struct sched *s; | |
376 | int i; | |
377 | ||
378 | s = kzalloc(sizeof (struct sched), GFP_KERNEL); | |
379 | if (!s) | |
380 | return -ENOMEM; | |
381 | ||
382 | pr_debug("tx_sched_init\n"); | |
383 | tasklet_init(&s->sched_tsk, restart_sched, (unsigned long) sge); | |
384 | sge->tx_sched = s; | |
385 | ||
386 | for (i = 0; i < MAX_NPORTS; i++) { | |
387 | skb_queue_head_init(&s->p[i].skbq); | |
388 | t1_sched_update_parms(sge, i, 1500, 1000); | |
389 | } | |
390 | ||
391 | return 0; | |
392 | } | |
393 | ||
394 | /* | |
395 | * sched_update_avail() computes the delta since the last time it was called | |
396 | * and updates the per port quota (number of bits that can be sent to the any | |
397 | * port). | |
398 | */ | |
399 | static inline int sched_update_avail(struct sge *sge) | |
400 | { | |
401 | struct sched *s = sge->tx_sched; | |
fd3065b2 | 402 | ktime_t now = ktime_get(); |
f1d3d38a SH |
403 | unsigned int i; |
404 | long long delta_time_ns; | |
405 | ||
406 | delta_time_ns = ktime_to_ns(ktime_sub(now, s->last_updated)); | |
407 | ||
408 | pr_debug("sched_update_avail delta=%lld\n", delta_time_ns); | |
409 | if (delta_time_ns < 15000) | |
410 | return 0; | |
411 | ||
412 | for (i = 0; i < MAX_NPORTS; i++) { | |
413 | struct sched_port *p = &s->p[i]; | |
414 | unsigned int delta_avail; | |
415 | ||
416 | delta_avail = (p->drain_bits_per_1024ns * delta_time_ns) >> 13; | |
417 | p->avail = min(p->avail + delta_avail, s->max_avail); | |
418 | } | |
419 | ||
420 | s->last_updated = now; | |
421 | ||
422 | return 1; | |
423 | } | |
424 | ||
425 | /* | |
426 | * sched_skb() is called from two different places. In the tx path, any | |
427 | * packet generating load on an output port will call sched_skb() | |
428 | * (skb != NULL). In addition, sched_skb() is called from the irq/soft irq | |
429 | * context (skb == NULL). | |
430 | * The scheduler only returns a skb (which will then be sent) if the | |
431 | * length of the skb is <= the current quota of the output port. | |
432 | */ | |
433 | static struct sk_buff *sched_skb(struct sge *sge, struct sk_buff *skb, | |
434 | unsigned int credits) | |
435 | { | |
436 | struct sched *s = sge->tx_sched; | |
437 | struct sk_buff_head *skbq; | |
438 | unsigned int i, len, update = 1; | |
439 | ||
440 | pr_debug("sched_skb %p\n", skb); | |
441 | if (!skb) { | |
442 | if (!s->num) | |
443 | return NULL; | |
444 | } else { | |
445 | skbq = &s->p[skb->dev->if_port].skbq; | |
446 | __skb_queue_tail(skbq, skb); | |
447 | s->num++; | |
448 | skb = NULL; | |
449 | } | |
450 | ||
451 | if (credits < MAX_SKB_FRAGS + 1) | |
452 | goto out; | |
453 | ||
356bd146 | 454 | again: |
f1d3d38a | 455 | for (i = 0; i < MAX_NPORTS; i++) { |
18d777a5 | 456 | s->port = (s->port + 1) & (MAX_NPORTS - 1); |
f1d3d38a SH |
457 | skbq = &s->p[s->port].skbq; |
458 | ||
459 | skb = skb_peek(skbq); | |
460 | ||
461 | if (!skb) | |
462 | continue; | |
463 | ||
464 | len = skb->len; | |
465 | if (len <= s->p[s->port].avail) { | |
466 | s->p[s->port].avail -= len; | |
467 | s->num--; | |
468 | __skb_unlink(skb, skbq); | |
469 | goto out; | |
470 | } | |
471 | skb = NULL; | |
472 | } | |
473 | ||
474 | if (update-- && sched_update_avail(sge)) | |
475 | goto again; | |
476 | ||
356bd146 FR |
477 | out: |
478 | /* If there are more pending skbs, we use the hardware to schedule us | |
f1d3d38a SH |
479 | * again. |
480 | */ | |
481 | if (s->num && !skb) { | |
482 | struct cmdQ *q = &sge->cmdQ[0]; | |
483 | clear_bit(CMDQ_STAT_LAST_PKT_DB, &q->status); | |
484 | if (test_and_set_bit(CMDQ_STAT_RUNNING, &q->status) == 0) { | |
485 | set_bit(CMDQ_STAT_LAST_PKT_DB, &q->status); | |
486 | writel(F_CMDQ0_ENABLE, sge->adapter->regs + A_SG_DOORBELL); | |
487 | } | |
488 | } | |
489 | pr_debug("sched_skb ret %p\n", skb); | |
490 | ||
491 | return skb; | |
492 | } | |
493 | ||
8199d3a7 CL |
494 | /* |
495 | * PIO to indicate that memory mapped Q contains valid descriptor(s). | |
496 | */ | |
559fb51b | 497 | static inline void doorbell_pio(struct adapter *adapter, u32 val) |
8199d3a7 CL |
498 | { |
499 | wmb(); | |
559fb51b | 500 | writel(val, adapter->regs + A_SG_DOORBELL); |
8199d3a7 CL |
501 | } |
502 | ||
503 | /* | |
504 | * Frees all RX buffers on the freelist Q. The caller must make sure that | |
505 | * the SGE is turned off before calling this function. | |
506 | */ | |
559fb51b | 507 | static void free_freelQ_buffers(struct pci_dev *pdev, struct freelQ *q) |
8199d3a7 | 508 | { |
559fb51b | 509 | unsigned int cidx = q->cidx; |
8199d3a7 | 510 | |
559fb51b SB |
511 | while (q->credits--) { |
512 | struct freelQ_ce *ce = &q->centries[cidx]; | |
8199d3a7 | 513 | |
094f92a6 FT |
514 | pci_unmap_single(pdev, dma_unmap_addr(ce, dma_addr), |
515 | dma_unmap_len(ce, dma_len), | |
8199d3a7 CL |
516 | PCI_DMA_FROMDEVICE); |
517 | dev_kfree_skb(ce->skb); | |
518 | ce->skb = NULL; | |
559fb51b | 519 | if (++cidx == q->size) |
8199d3a7 CL |
520 | cidx = 0; |
521 | } | |
522 | } | |
523 | ||
524 | /* | |
525 | * Free RX free list and response queue resources. | |
526 | */ | |
527 | static void free_rx_resources(struct sge *sge) | |
528 | { | |
529 | struct pci_dev *pdev = sge->adapter->pdev; | |
530 | unsigned int size, i; | |
531 | ||
532 | if (sge->respQ.entries) { | |
559fb51b | 533 | size = sizeof(struct respQ_e) * sge->respQ.size; |
8199d3a7 CL |
534 | pci_free_consistent(pdev, size, sge->respQ.entries, |
535 | sge->respQ.dma_addr); | |
536 | } | |
537 | ||
538 | for (i = 0; i < SGE_FREELQ_N; i++) { | |
559fb51b | 539 | struct freelQ *q = &sge->freelQ[i]; |
8199d3a7 | 540 | |
559fb51b SB |
541 | if (q->centries) { |
542 | free_freelQ_buffers(pdev, q); | |
543 | kfree(q->centries); | |
8199d3a7 | 544 | } |
559fb51b SB |
545 | if (q->entries) { |
546 | size = sizeof(struct freelQ_e) * q->size; | |
547 | pci_free_consistent(pdev, size, q->entries, | |
548 | q->dma_addr); | |
8199d3a7 CL |
549 | } |
550 | } | |
551 | } | |
552 | ||
553 | /* | |
554 | * Allocates basic RX resources, consisting of memory mapped freelist Qs and a | |
559fb51b | 555 | * response queue. |
8199d3a7 CL |
556 | */ |
557 | static int alloc_rx_resources(struct sge *sge, struct sge_params *p) | |
558 | { | |
559 | struct pci_dev *pdev = sge->adapter->pdev; | |
560 | unsigned int size, i; | |
561 | ||
562 | for (i = 0; i < SGE_FREELQ_N; i++) { | |
559fb51b SB |
563 | struct freelQ *q = &sge->freelQ[i]; |
564 | ||
565 | q->genbit = 1; | |
566 | q->size = p->freelQ_size[i]; | |
567 | q->dma_offset = sge->rx_pkt_pad ? 0 : NET_IP_ALIGN; | |
568 | size = sizeof(struct freelQ_e) * q->size; | |
3e0f75be | 569 | q->entries = pci_alloc_consistent(pdev, size, &q->dma_addr); |
559fb51b | 570 | if (!q->entries) |
8199d3a7 | 571 | goto err_no_mem; |
3e0f75be | 572 | |
559fb51b | 573 | size = sizeof(struct freelQ_ce) * q->size; |
cbee9f91 | 574 | q->centries = kzalloc(size, GFP_KERNEL); |
559fb51b | 575 | if (!q->centries) |
8199d3a7 CL |
576 | goto err_no_mem; |
577 | } | |
578 | ||
579 | /* | |
580 | * Calculate the buffer sizes for the two free lists. FL0 accommodates | |
581 | * regular sized Ethernet frames, FL1 is sized not to exceed 16K, | |
582 | * including all the sk_buff overhead. | |
583 | * | |
584 | * Note: For T2 FL0 and FL1 are reversed. | |
585 | */ | |
586 | sge->freelQ[!sge->jumbo_fl].rx_buffer_size = SGE_RX_SM_BUF_SIZE + | |
587 | sizeof(struct cpl_rx_data) + | |
588 | sge->freelQ[!sge->jumbo_fl].dma_offset; | |
f1d3d38a SH |
589 | |
590 | size = (16 * 1024) - | |
591 | SKB_DATA_ALIGN(sizeof(struct skb_shared_info)); | |
592 | ||
593 | sge->freelQ[sge->jumbo_fl].rx_buffer_size = size; | |
8199d3a7 | 594 | |
559fb51b SB |
595 | /* |
596 | * Setup which skb recycle Q should be used when recycling buffers from | |
597 | * each free list. | |
598 | */ | |
599 | sge->freelQ[!sge->jumbo_fl].recycleq_idx = 0; | |
600 | sge->freelQ[sge->jumbo_fl].recycleq_idx = 1; | |
601 | ||
8199d3a7 | 602 | sge->respQ.genbit = 1; |
559fb51b SB |
603 | sge->respQ.size = SGE_RESPQ_E_N; |
604 | sge->respQ.credits = 0; | |
605 | size = sizeof(struct respQ_e) * sge->respQ.size; | |
3e0f75be | 606 | sge->respQ.entries = |
8199d3a7 CL |
607 | pci_alloc_consistent(pdev, size, &sge->respQ.dma_addr); |
608 | if (!sge->respQ.entries) | |
609 | goto err_no_mem; | |
8199d3a7 CL |
610 | return 0; |
611 | ||
612 | err_no_mem: | |
613 | free_rx_resources(sge); | |
614 | return -ENOMEM; | |
615 | } | |
616 | ||
617 | /* | |
559fb51b | 618 | * Reclaims n TX descriptors and frees the buffers associated with them. |
8199d3a7 | 619 | */ |
559fb51b | 620 | static void free_cmdQ_buffers(struct sge *sge, struct cmdQ *q, unsigned int n) |
8199d3a7 | 621 | { |
559fb51b | 622 | struct cmdQ_ce *ce; |
8199d3a7 | 623 | struct pci_dev *pdev = sge->adapter->pdev; |
559fb51b | 624 | unsigned int cidx = q->cidx; |
8199d3a7 | 625 | |
559fb51b SB |
626 | q->in_use -= n; |
627 | ce = &q->centries[cidx]; | |
628 | while (n--) { | |
094f92a6 FT |
629 | if (likely(dma_unmap_len(ce, dma_len))) { |
630 | pci_unmap_single(pdev, dma_unmap_addr(ce, dma_addr), | |
631 | dma_unmap_len(ce, dma_len), | |
3e0f75be FR |
632 | PCI_DMA_TODEVICE); |
633 | if (q->sop) | |
f1d3d38a | 634 | q->sop = 0; |
f1d3d38a | 635 | } |
559fb51b | 636 | if (ce->skb) { |
f1d3d38a | 637 | dev_kfree_skb_any(ce->skb); |
559fb51b SB |
638 | q->sop = 1; |
639 | } | |
8199d3a7 | 640 | ce++; |
559fb51b | 641 | if (++cidx == q->size) { |
8199d3a7 | 642 | cidx = 0; |
559fb51b | 643 | ce = q->centries; |
8199d3a7 CL |
644 | } |
645 | } | |
559fb51b | 646 | q->cidx = cidx; |
8199d3a7 CL |
647 | } |
648 | ||
649 | /* | |
650 | * Free TX resources. | |
651 | * | |
652 | * Assumes that SGE is stopped and all interrupts are disabled. | |
653 | */ | |
654 | static void free_tx_resources(struct sge *sge) | |
655 | { | |
656 | struct pci_dev *pdev = sge->adapter->pdev; | |
657 | unsigned int size, i; | |
658 | ||
659 | for (i = 0; i < SGE_CMDQ_N; i++) { | |
559fb51b | 660 | struct cmdQ *q = &sge->cmdQ[i]; |
8199d3a7 | 661 | |
559fb51b SB |
662 | if (q->centries) { |
663 | if (q->in_use) | |
664 | free_cmdQ_buffers(sge, q, q->in_use); | |
665 | kfree(q->centries); | |
8199d3a7 | 666 | } |
559fb51b SB |
667 | if (q->entries) { |
668 | size = sizeof(struct cmdQ_e) * q->size; | |
669 | pci_free_consistent(pdev, size, q->entries, | |
670 | q->dma_addr); | |
8199d3a7 CL |
671 | } |
672 | } | |
673 | } | |
674 | ||
675 | /* | |
676 | * Allocates basic TX resources, consisting of memory mapped command Qs. | |
677 | */ | |
678 | static int alloc_tx_resources(struct sge *sge, struct sge_params *p) | |
679 | { | |
680 | struct pci_dev *pdev = sge->adapter->pdev; | |
681 | unsigned int size, i; | |
682 | ||
683 | for (i = 0; i < SGE_CMDQ_N; i++) { | |
559fb51b SB |
684 | struct cmdQ *q = &sge->cmdQ[i]; |
685 | ||
686 | q->genbit = 1; | |
687 | q->sop = 1; | |
688 | q->size = p->cmdQ_size[i]; | |
689 | q->in_use = 0; | |
690 | q->status = 0; | |
691 | q->processed = q->cleaned = 0; | |
692 | q->stop_thres = 0; | |
693 | spin_lock_init(&q->lock); | |
694 | size = sizeof(struct cmdQ_e) * q->size; | |
3e0f75be | 695 | q->entries = pci_alloc_consistent(pdev, size, &q->dma_addr); |
559fb51b | 696 | if (!q->entries) |
8199d3a7 | 697 | goto err_no_mem; |
3e0f75be | 698 | |
559fb51b | 699 | size = sizeof(struct cmdQ_ce) * q->size; |
cbee9f91 | 700 | q->centries = kzalloc(size, GFP_KERNEL); |
559fb51b | 701 | if (!q->centries) |
8199d3a7 CL |
702 | goto err_no_mem; |
703 | } | |
704 | ||
559fb51b SB |
705 | /* |
706 | * CommandQ 0 handles Ethernet and TOE packets, while queue 1 is TOE | |
707 | * only. For queue 0 set the stop threshold so we can handle one more | |
708 | * packet from each port, plus reserve an additional 24 entries for | |
709 | * Ethernet packets only. Queue 1 never suspends nor do we reserve | |
710 | * space for Ethernet packets. | |
711 | */ | |
712 | sge->cmdQ[0].stop_thres = sge->adapter->params.nports * | |
713 | (MAX_SKB_FRAGS + 1); | |
8199d3a7 CL |
714 | return 0; |
715 | ||
716 | err_no_mem: | |
717 | free_tx_resources(sge); | |
718 | return -ENOMEM; | |
719 | } | |
720 | ||
721 | static inline void setup_ring_params(struct adapter *adapter, u64 addr, | |
722 | u32 size, int base_reg_lo, | |
723 | int base_reg_hi, int size_reg) | |
724 | { | |
559fb51b SB |
725 | writel((u32)addr, adapter->regs + base_reg_lo); |
726 | writel(addr >> 32, adapter->regs + base_reg_hi); | |
727 | writel(size, adapter->regs + size_reg); | |
8199d3a7 CL |
728 | } |
729 | ||
730 | /* | |
731 | * Enable/disable VLAN acceleration. | |
732 | */ | |
c8f44aff | 733 | void t1_vlan_mode(struct adapter *adapter, netdev_features_t features) |
8199d3a7 CL |
734 | { |
735 | struct sge *sge = adapter->sge; | |
736 | ||
f646968f | 737 | if (features & NETIF_F_HW_VLAN_CTAG_RX) |
8199d3a7 | 738 | sge->sge_control |= F_VLAN_XTRACT; |
133b0851 JP |
739 | else |
740 | sge->sge_control &= ~F_VLAN_XTRACT; | |
8199d3a7 | 741 | if (adapter->open_device_map) { |
559fb51b | 742 | writel(sge->sge_control, adapter->regs + A_SG_CONTROL); |
f1d3d38a | 743 | readl(adapter->regs + A_SG_CONTROL); /* flush */ |
8199d3a7 CL |
744 | } |
745 | } | |
746 | ||
8199d3a7 CL |
747 | /* |
748 | * Programs the various SGE registers. However, the engine is not yet enabled, | |
749 | * but sge->sge_control is setup and ready to go. | |
750 | */ | |
751 | static void configure_sge(struct sge *sge, struct sge_params *p) | |
752 | { | |
753 | struct adapter *ap = sge->adapter; | |
356bd146 | 754 | |
559fb51b SB |
755 | writel(0, ap->regs + A_SG_CONTROL); |
756 | setup_ring_params(ap, sge->cmdQ[0].dma_addr, sge->cmdQ[0].size, | |
8199d3a7 | 757 | A_SG_CMD0BASELWR, A_SG_CMD0BASEUPR, A_SG_CMD0SIZE); |
559fb51b | 758 | setup_ring_params(ap, sge->cmdQ[1].dma_addr, sge->cmdQ[1].size, |
8199d3a7 CL |
759 | A_SG_CMD1BASELWR, A_SG_CMD1BASEUPR, A_SG_CMD1SIZE); |
760 | setup_ring_params(ap, sge->freelQ[0].dma_addr, | |
559fb51b | 761 | sge->freelQ[0].size, A_SG_FL0BASELWR, |
8199d3a7 CL |
762 | A_SG_FL0BASEUPR, A_SG_FL0SIZE); |
763 | setup_ring_params(ap, sge->freelQ[1].dma_addr, | |
559fb51b | 764 | sge->freelQ[1].size, A_SG_FL1BASELWR, |
8199d3a7 CL |
765 | A_SG_FL1BASEUPR, A_SG_FL1SIZE); |
766 | ||
767 | /* The threshold comparison uses <. */ | |
559fb51b | 768 | writel(SGE_RX_SM_BUF_SIZE + 1, ap->regs + A_SG_FLTHRESHOLD); |
8199d3a7 | 769 | |
559fb51b SB |
770 | setup_ring_params(ap, sge->respQ.dma_addr, sge->respQ.size, |
771 | A_SG_RSPBASELWR, A_SG_RSPBASEUPR, A_SG_RSPSIZE); | |
772 | writel((u32)sge->respQ.size - 1, ap->regs + A_SG_RSPQUEUECREDIT); | |
8199d3a7 CL |
773 | |
774 | sge->sge_control = F_CMDQ0_ENABLE | F_CMDQ1_ENABLE | F_FL0_ENABLE | | |
775 | F_FL1_ENABLE | F_CPL_ENABLE | F_RESPONSE_QUEUE_ENABLE | | |
776 | V_CMDQ_PRIORITY(2) | F_DISABLE_CMDQ1_GTS | F_ISCSI_COALESCE | | |
777 | V_RX_PKT_OFFSET(sge->rx_pkt_pad); | |
778 | ||
779 | #if defined(__BIG_ENDIAN_BITFIELD) | |
780 | sge->sge_control |= F_ENABLE_BIG_ENDIAN; | |
781 | #endif | |
782 | ||
559fb51b SB |
783 | /* Initialize no-resource timer */ |
784 | sge->intrtimer_nres = SGE_INTRTIMER_NRES * core_ticks_per_usec(ap); | |
785 | ||
786 | t1_sge_set_coalesce_params(sge, p); | |
8199d3a7 CL |
787 | } |
788 | ||
789 | /* | |
790 | * Return the payload capacity of the jumbo free-list buffers. | |
791 | */ | |
792 | static inline unsigned int jumbo_payload_capacity(const struct sge *sge) | |
793 | { | |
794 | return sge->freelQ[sge->jumbo_fl].rx_buffer_size - | |
559fb51b SB |
795 | sge->freelQ[sge->jumbo_fl].dma_offset - |
796 | sizeof(struct cpl_rx_data); | |
8199d3a7 CL |
797 | } |
798 | ||
799 | /* | |
800 | * Frees all SGE related resources and the sge structure itself | |
801 | */ | |
802 | void t1_sge_destroy(struct sge *sge) | |
803 | { | |
56f643c2 SH |
804 | int i; |
805 | ||
806 | for_each_port(sge->adapter, i) | |
807 | free_percpu(sge->port_stats[i]); | |
808 | ||
f1d3d38a | 809 | kfree(sge->tx_sched); |
8199d3a7 CL |
810 | free_tx_resources(sge); |
811 | free_rx_resources(sge); | |
812 | kfree(sge); | |
813 | } | |
814 | ||
815 | /* | |
816 | * Allocates new RX buffers on the freelist Q (and tracks them on the freelist | |
817 | * context Q) until the Q is full or alloc_skb fails. | |
818 | * | |
819 | * It is possible that the generation bits already match, indicating that the | |
820 | * buffer is already valid and nothing needs to be done. This happens when we | |
821 | * copied a received buffer into a new sk_buff during the interrupt processing. | |
822 | * | |
823 | * If the SGE doesn't automatically align packets properly (!sge->rx_pkt_pad), | |
824 | * we specify a RX_OFFSET in order to make sure that the IP header is 4B | |
825 | * aligned. | |
826 | */ | |
559fb51b | 827 | static void refill_free_list(struct sge *sge, struct freelQ *q) |
8199d3a7 CL |
828 | { |
829 | struct pci_dev *pdev = sge->adapter->pdev; | |
559fb51b SB |
830 | struct freelQ_ce *ce = &q->centries[q->pidx]; |
831 | struct freelQ_e *e = &q->entries[q->pidx]; | |
832 | unsigned int dma_len = q->rx_buffer_size - q->dma_offset; | |
8199d3a7 | 833 | |
559fb51b SB |
834 | while (q->credits < q->size) { |
835 | struct sk_buff *skb; | |
836 | dma_addr_t mapping; | |
8199d3a7 | 837 | |
70386d40 | 838 | skb = dev_alloc_skb(q->rx_buffer_size); |
559fb51b SB |
839 | if (!skb) |
840 | break; | |
841 | ||
842 | skb_reserve(skb, q->dma_offset); | |
843 | mapping = pci_map_single(pdev, skb->data, dma_len, | |
844 | PCI_DMA_FROMDEVICE); | |
24a427cf SH |
845 | skb_reserve(skb, sge->rx_pkt_pad); |
846 | ||
559fb51b | 847 | ce->skb = skb; |
094f92a6 FT |
848 | dma_unmap_addr_set(ce, dma_addr, mapping); |
849 | dma_unmap_len_set(ce, dma_len, dma_len); | |
559fb51b SB |
850 | e->addr_lo = (u32)mapping; |
851 | e->addr_hi = (u64)mapping >> 32; | |
852 | e->len_gen = V_CMD_LEN(dma_len) | V_CMD_GEN1(q->genbit); | |
853 | wmb(); | |
854 | e->gen2 = V_CMD_GEN2(q->genbit); | |
8199d3a7 CL |
855 | |
856 | e++; | |
857 | ce++; | |
559fb51b SB |
858 | if (++q->pidx == q->size) { |
859 | q->pidx = 0; | |
860 | q->genbit ^= 1; | |
861 | ce = q->centries; | |
862 | e = q->entries; | |
8199d3a7 | 863 | } |
559fb51b | 864 | q->credits++; |
8199d3a7 | 865 | } |
8199d3a7 CL |
866 | } |
867 | ||
868 | /* | |
559fb51b SB |
869 | * Calls refill_free_list for both free lists. If we cannot fill at least 1/4 |
870 | * of both rings, we go into 'few interrupt mode' in order to give the system | |
871 | * time to free up resources. | |
8199d3a7 CL |
872 | */ |
873 | static void freelQs_empty(struct sge *sge) | |
874 | { | |
559fb51b SB |
875 | struct adapter *adapter = sge->adapter; |
876 | u32 irq_reg = readl(adapter->regs + A_SG_INT_ENABLE); | |
8199d3a7 CL |
877 | u32 irqholdoff_reg; |
878 | ||
879 | refill_free_list(sge, &sge->freelQ[0]); | |
880 | refill_free_list(sge, &sge->freelQ[1]); | |
881 | ||
559fb51b SB |
882 | if (sge->freelQ[0].credits > (sge->freelQ[0].size >> 2) && |
883 | sge->freelQ[1].credits > (sge->freelQ[1].size >> 2)) { | |
8199d3a7 | 884 | irq_reg |= F_FL_EXHAUSTED; |
559fb51b | 885 | irqholdoff_reg = sge->fixed_intrtimer; |
8199d3a7 CL |
886 | } else { |
887 | /* Clear the F_FL_EXHAUSTED interrupts for now */ | |
888 | irq_reg &= ~F_FL_EXHAUSTED; | |
889 | irqholdoff_reg = sge->intrtimer_nres; | |
890 | } | |
559fb51b SB |
891 | writel(irqholdoff_reg, adapter->regs + A_SG_INTRTIMER); |
892 | writel(irq_reg, adapter->regs + A_SG_INT_ENABLE); | |
8199d3a7 CL |
893 | |
894 | /* We reenable the Qs to force a freelist GTS interrupt later */ | |
559fb51b | 895 | doorbell_pio(adapter, F_FL0_ENABLE | F_FL1_ENABLE); |
8199d3a7 CL |
896 | } |
897 | ||
898 | #define SGE_PL_INTR_MASK (F_PL_INTR_SGE_ERR | F_PL_INTR_SGE_DATA) | |
899 | #define SGE_INT_FATAL (F_RESPQ_OVERFLOW | F_PACKET_TOO_BIG | F_PACKET_MISMATCH) | |
900 | #define SGE_INT_ENABLE (F_RESPQ_EXHAUSTED | F_RESPQ_OVERFLOW | \ | |
901 | F_FL_EXHAUSTED | F_PACKET_TOO_BIG | F_PACKET_MISMATCH) | |
902 | ||
903 | /* | |
904 | * Disable SGE Interrupts | |
905 | */ | |
906 | void t1_sge_intr_disable(struct sge *sge) | |
907 | { | |
559fb51b | 908 | u32 val = readl(sge->adapter->regs + A_PL_ENABLE); |
8199d3a7 | 909 | |
559fb51b SB |
910 | writel(val & ~SGE_PL_INTR_MASK, sge->adapter->regs + A_PL_ENABLE); |
911 | writel(0, sge->adapter->regs + A_SG_INT_ENABLE); | |
8199d3a7 CL |
912 | } |
913 | ||
914 | /* | |
915 | * Enable SGE interrupts. | |
916 | */ | |
917 | void t1_sge_intr_enable(struct sge *sge) | |
918 | { | |
919 | u32 en = SGE_INT_ENABLE; | |
559fb51b | 920 | u32 val = readl(sge->adapter->regs + A_PL_ENABLE); |
8199d3a7 | 921 | |
30f554f9 | 922 | if (sge->adapter->port[0].dev->hw_features & NETIF_F_TSO) |
8199d3a7 | 923 | en &= ~F_PACKET_TOO_BIG; |
559fb51b SB |
924 | writel(en, sge->adapter->regs + A_SG_INT_ENABLE); |
925 | writel(val | SGE_PL_INTR_MASK, sge->adapter->regs + A_PL_ENABLE); | |
8199d3a7 CL |
926 | } |
927 | ||
928 | /* | |
929 | * Clear SGE interrupts. | |
930 | */ | |
931 | void t1_sge_intr_clear(struct sge *sge) | |
932 | { | |
559fb51b SB |
933 | writel(SGE_PL_INTR_MASK, sge->adapter->regs + A_PL_CAUSE); |
934 | writel(0xffffffff, sge->adapter->regs + A_SG_INT_CAUSE); | |
8199d3a7 CL |
935 | } |
936 | ||
937 | /* | |
938 | * SGE 'Error' interrupt handler | |
939 | */ | |
940 | int t1_sge_intr_error_handler(struct sge *sge) | |
941 | { | |
942 | struct adapter *adapter = sge->adapter; | |
559fb51b | 943 | u32 cause = readl(adapter->regs + A_SG_INT_CAUSE); |
8199d3a7 | 944 | |
30f554f9 | 945 | if (adapter->port[0].dev->hw_features & NETIF_F_TSO) |
8199d3a7 CL |
946 | cause &= ~F_PACKET_TOO_BIG; |
947 | if (cause & F_RESPQ_EXHAUSTED) | |
559fb51b | 948 | sge->stats.respQ_empty++; |
8199d3a7 | 949 | if (cause & F_RESPQ_OVERFLOW) { |
559fb51b | 950 | sge->stats.respQ_overflow++; |
c1f51212 | 951 | pr_alert("%s: SGE response queue overflow\n", |
8199d3a7 CL |
952 | adapter->name); |
953 | } | |
954 | if (cause & F_FL_EXHAUSTED) { | |
559fb51b | 955 | sge->stats.freelistQ_empty++; |
8199d3a7 CL |
956 | freelQs_empty(sge); |
957 | } | |
958 | if (cause & F_PACKET_TOO_BIG) { | |
559fb51b | 959 | sge->stats.pkt_too_big++; |
c1f51212 | 960 | pr_alert("%s: SGE max packet size exceeded\n", |
8199d3a7 CL |
961 | adapter->name); |
962 | } | |
963 | if (cause & F_PACKET_MISMATCH) { | |
559fb51b | 964 | sge->stats.pkt_mismatch++; |
c1f51212 | 965 | pr_alert("%s: SGE packet mismatch\n", adapter->name); |
8199d3a7 CL |
966 | } |
967 | if (cause & SGE_INT_FATAL) | |
968 | t1_fatal_err(adapter); | |
969 | ||
559fb51b | 970 | writel(cause, adapter->regs + A_SG_INT_CAUSE); |
8199d3a7 CL |
971 | return 0; |
972 | } | |
973 | ||
56f643c2 | 974 | const struct sge_intr_counts *t1_sge_get_intr_counts(const struct sge *sge) |
559fb51b SB |
975 | { |
976 | return &sge->stats; | |
977 | } | |
978 | ||
56f643c2 SH |
979 | void t1_sge_get_port_stats(const struct sge *sge, int port, |
980 | struct sge_port_stats *ss) | |
559fb51b | 981 | { |
56f643c2 SH |
982 | int cpu; |
983 | ||
984 | memset(ss, 0, sizeof(*ss)); | |
985 | for_each_possible_cpu(cpu) { | |
986 | struct sge_port_stats *st = per_cpu_ptr(sge->port_stats[port], cpu); | |
987 | ||
56f643c2 | 988 | ss->rx_cso_good += st->rx_cso_good; |
56f643c2 SH |
989 | ss->tx_cso += st->tx_cso; |
990 | ss->tx_tso += st->tx_tso; | |
7832ee03 | 991 | ss->tx_need_hdrroom += st->tx_need_hdrroom; |
56f643c2 SH |
992 | ss->vlan_xtract += st->vlan_xtract; |
993 | ss->vlan_insert += st->vlan_insert; | |
994 | } | |
559fb51b SB |
995 | } |
996 | ||
997 | /** | |
998 | * recycle_fl_buf - recycle a free list buffer | |
999 | * @fl: the free list | |
1000 | * @idx: index of buffer to recycle | |
8199d3a7 | 1001 | * |
559fb51b SB |
1002 | * Recycles the specified buffer on the given free list by adding it at |
1003 | * the next available slot on the list. | |
8199d3a7 | 1004 | */ |
559fb51b | 1005 | static void recycle_fl_buf(struct freelQ *fl, int idx) |
8199d3a7 | 1006 | { |
559fb51b SB |
1007 | struct freelQ_e *from = &fl->entries[idx]; |
1008 | struct freelQ_e *to = &fl->entries[fl->pidx]; | |
8199d3a7 | 1009 | |
559fb51b SB |
1010 | fl->centries[fl->pidx] = fl->centries[idx]; |
1011 | to->addr_lo = from->addr_lo; | |
1012 | to->addr_hi = from->addr_hi; | |
1013 | to->len_gen = G_CMD_LEN(from->len_gen) | V_CMD_GEN1(fl->genbit); | |
1014 | wmb(); | |
1015 | to->gen2 = V_CMD_GEN2(fl->genbit); | |
1016 | fl->credits++; | |
8199d3a7 | 1017 | |
559fb51b SB |
1018 | if (++fl->pidx == fl->size) { |
1019 | fl->pidx = 0; | |
1020 | fl->genbit ^= 1; | |
8199d3a7 | 1021 | } |
559fb51b | 1022 | } |
8199d3a7 | 1023 | |
24a427cf SH |
1024 | static int copybreak __read_mostly = 256; |
1025 | module_param(copybreak, int, 0); | |
1026 | MODULE_PARM_DESC(copybreak, "Receive copy threshold"); | |
1027 | ||
559fb51b SB |
1028 | /** |
1029 | * get_packet - return the next ingress packet buffer | |
1030 | * @pdev: the PCI device that received the packet | |
1031 | * @fl: the SGE free list holding the packet | |
1032 | * @len: the actual packet length, excluding any SGE padding | |
559fb51b SB |
1033 | * |
1034 | * Get the next packet from a free list and complete setup of the | |
1035 | * sk_buff. If the packet is small we make a copy and recycle the | |
1036 | * original buffer, otherwise we use the original buffer itself. If a | |
1037 | * positive drop threshold is supplied packets are dropped and their | |
1038 | * buffers recycled if (a) the number of remaining buffers is under the | |
1039 | * threshold and the packet is too big to copy, or (b) the packet should | |
1040 | * be copied but there is no memory for the copy. | |
1041 | */ | |
1042 | static inline struct sk_buff *get_packet(struct pci_dev *pdev, | |
24a427cf | 1043 | struct freelQ *fl, unsigned int len) |
559fb51b SB |
1044 | { |
1045 | struct sk_buff *skb; | |
24a427cf | 1046 | const struct freelQ_ce *ce = &fl->centries[fl->cidx]; |
559fb51b | 1047 | |
24a427cf | 1048 | if (len < copybreak) { |
e76d120b | 1049 | skb = netdev_alloc_skb_ip_align(NULL, len); |
24a427cf SH |
1050 | if (!skb) |
1051 | goto use_orig_buf; | |
1052 | ||
24a427cf SH |
1053 | skb_put(skb, len); |
1054 | pci_dma_sync_single_for_cpu(pdev, | |
094f92a6 FT |
1055 | dma_unmap_addr(ce, dma_addr), |
1056 | dma_unmap_len(ce, dma_len), | |
559fb51b | 1057 | PCI_DMA_FROMDEVICE); |
d626f62b | 1058 | skb_copy_from_linear_data(ce->skb, skb->data, len); |
24a427cf | 1059 | pci_dma_sync_single_for_device(pdev, |
094f92a6 FT |
1060 | dma_unmap_addr(ce, dma_addr), |
1061 | dma_unmap_len(ce, dma_len), | |
24a427cf | 1062 | PCI_DMA_FROMDEVICE); |
559fb51b SB |
1063 | recycle_fl_buf(fl, fl->cidx); |
1064 | return skb; | |
8199d3a7 CL |
1065 | } |
1066 | ||
24a427cf SH |
1067 | use_orig_buf: |
1068 | if (fl->credits < 2) { | |
559fb51b SB |
1069 | recycle_fl_buf(fl, fl->cidx); |
1070 | return NULL; | |
1071 | } | |
8199d3a7 | 1072 | |
094f92a6 FT |
1073 | pci_unmap_single(pdev, dma_unmap_addr(ce, dma_addr), |
1074 | dma_unmap_len(ce, dma_len), PCI_DMA_FROMDEVICE); | |
559fb51b | 1075 | skb = ce->skb; |
24a427cf SH |
1076 | prefetch(skb->data); |
1077 | ||
559fb51b SB |
1078 | skb_put(skb, len); |
1079 | return skb; | |
1080 | } | |
8199d3a7 | 1081 | |
559fb51b SB |
1082 | /** |
1083 | * unexpected_offload - handle an unexpected offload packet | |
1084 | * @adapter: the adapter | |
1085 | * @fl: the free list that received the packet | |
1086 | * | |
1087 | * Called when we receive an unexpected offload packet (e.g., the TOE | |
1088 | * function is disabled or the card is a NIC). Prints a message and | |
1089 | * recycles the buffer. | |
1090 | */ | |
1091 | static void unexpected_offload(struct adapter *adapter, struct freelQ *fl) | |
1092 | { | |
1093 | struct freelQ_ce *ce = &fl->centries[fl->cidx]; | |
1094 | struct sk_buff *skb = ce->skb; | |
1095 | ||
094f92a6 FT |
1096 | pci_dma_sync_single_for_cpu(adapter->pdev, dma_unmap_addr(ce, dma_addr), |
1097 | dma_unmap_len(ce, dma_len), PCI_DMA_FROMDEVICE); | |
c1f51212 | 1098 | pr_err("%s: unexpected offload packet, cmd %u\n", |
559fb51b SB |
1099 | adapter->name, *skb->data); |
1100 | recycle_fl_buf(fl, fl->cidx); | |
8199d3a7 CL |
1101 | } |
1102 | ||
f1d3d38a SH |
1103 | /* |
1104 | * T1/T2 SGE limits the maximum DMA size per TX descriptor to | |
1105 | * SGE_TX_DESC_MAX_PLEN (16KB). If the PAGE_SIZE is larger than 16KB, the | |
1106 | * stack might send more than SGE_TX_DESC_MAX_PLEN in a contiguous manner. | |
1107 | * Note that the *_large_page_tx_descs stuff will be optimized out when | |
1108 | * PAGE_SIZE <= SGE_TX_DESC_MAX_PLEN. | |
1109 | * | |
1110 | * compute_large_page_descs() computes how many additional descriptors are | |
1111 | * required to break down the stack's request. | |
1112 | */ | |
1113 | static inline unsigned int compute_large_page_tx_descs(struct sk_buff *skb) | |
1114 | { | |
1115 | unsigned int count = 0; | |
356bd146 | 1116 | |
f1d3d38a SH |
1117 | if (PAGE_SIZE > SGE_TX_DESC_MAX_PLEN) { |
1118 | unsigned int nfrags = skb_shinfo(skb)->nr_frags; | |
e743d313 | 1119 | unsigned int i, len = skb_headlen(skb); |
f1d3d38a SH |
1120 | while (len > SGE_TX_DESC_MAX_PLEN) { |
1121 | count++; | |
1122 | len -= SGE_TX_DESC_MAX_PLEN; | |
1123 | } | |
1124 | for (i = 0; nfrags--; i++) { | |
9e903e08 ED |
1125 | const skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; |
1126 | len = skb_frag_size(frag); | |
f1d3d38a SH |
1127 | while (len > SGE_TX_DESC_MAX_PLEN) { |
1128 | count++; | |
1129 | len -= SGE_TX_DESC_MAX_PLEN; | |
1130 | } | |
1131 | } | |
1132 | } | |
1133 | return count; | |
1134 | } | |
1135 | ||
1136 | /* | |
1137 | * Write a cmdQ entry. | |
1138 | * | |
1139 | * Since this function writes the 'flags' field, it must not be used to | |
1140 | * write the first cmdQ entry. | |
1141 | */ | |
1142 | static inline void write_tx_desc(struct cmdQ_e *e, dma_addr_t mapping, | |
1143 | unsigned int len, unsigned int gen, | |
1144 | unsigned int eop) | |
1145 | { | |
0ee904c3 AB |
1146 | BUG_ON(len > SGE_TX_DESC_MAX_PLEN); |
1147 | ||
f1d3d38a SH |
1148 | e->addr_lo = (u32)mapping; |
1149 | e->addr_hi = (u64)mapping >> 32; | |
1150 | e->len_gen = V_CMD_LEN(len) | V_CMD_GEN1(gen); | |
1151 | e->flags = F_CMD_DATAVALID | V_CMD_EOP(eop) | V_CMD_GEN2(gen); | |
1152 | } | |
1153 | ||
1154 | /* | |
1155 | * See comment for previous function. | |
1156 | * | |
1157 | * write_tx_descs_large_page() writes additional SGE tx descriptors if | |
1158 | * *desc_len exceeds HW's capability. | |
1159 | */ | |
1160 | static inline unsigned int write_large_page_tx_descs(unsigned int pidx, | |
1161 | struct cmdQ_e **e, | |
1162 | struct cmdQ_ce **ce, | |
1163 | unsigned int *gen, | |
1164 | dma_addr_t *desc_mapping, | |
1165 | unsigned int *desc_len, | |
1166 | unsigned int nfrags, | |
1167 | struct cmdQ *q) | |
1168 | { | |
1169 | if (PAGE_SIZE > SGE_TX_DESC_MAX_PLEN) { | |
1170 | struct cmdQ_e *e1 = *e; | |
1171 | struct cmdQ_ce *ce1 = *ce; | |
1172 | ||
1173 | while (*desc_len > SGE_TX_DESC_MAX_PLEN) { | |
1174 | *desc_len -= SGE_TX_DESC_MAX_PLEN; | |
1175 | write_tx_desc(e1, *desc_mapping, SGE_TX_DESC_MAX_PLEN, | |
1176 | *gen, nfrags == 0 && *desc_len == 0); | |
1177 | ce1->skb = NULL; | |
094f92a6 | 1178 | dma_unmap_len_set(ce1, dma_len, 0); |
f1d3d38a SH |
1179 | *desc_mapping += SGE_TX_DESC_MAX_PLEN; |
1180 | if (*desc_len) { | |
1181 | ce1++; | |
1182 | e1++; | |
1183 | if (++pidx == q->size) { | |
1184 | pidx = 0; | |
1185 | *gen ^= 1; | |
1186 | ce1 = q->centries; | |
1187 | e1 = q->entries; | |
1188 | } | |
1189 | } | |
1190 | } | |
1191 | *e = e1; | |
1192 | *ce = ce1; | |
1193 | } | |
1194 | return pidx; | |
1195 | } | |
1196 | ||
8199d3a7 | 1197 | /* |
559fb51b SB |
1198 | * Write the command descriptors to transmit the given skb starting at |
1199 | * descriptor pidx with the given generation. | |
8199d3a7 | 1200 | */ |
559fb51b SB |
1201 | static inline void write_tx_descs(struct adapter *adapter, struct sk_buff *skb, |
1202 | unsigned int pidx, unsigned int gen, | |
1203 | struct cmdQ *q) | |
8199d3a7 | 1204 | { |
f1d3d38a | 1205 | dma_addr_t mapping, desc_mapping; |
559fb51b SB |
1206 | struct cmdQ_e *e, *e1; |
1207 | struct cmdQ_ce *ce; | |
f1d3d38a SH |
1208 | unsigned int i, flags, first_desc_len, desc_len, |
1209 | nfrags = skb_shinfo(skb)->nr_frags; | |
559fb51b | 1210 | |
f1d3d38a | 1211 | e = e1 = &q->entries[pidx]; |
559fb51b | 1212 | ce = &q->centries[pidx]; |
f1d3d38a SH |
1213 | |
1214 | mapping = pci_map_single(adapter->pdev, skb->data, | |
e743d313 | 1215 | skb_headlen(skb), PCI_DMA_TODEVICE); |
f1d3d38a SH |
1216 | |
1217 | desc_mapping = mapping; | |
e743d313 | 1218 | desc_len = skb_headlen(skb); |
f1d3d38a SH |
1219 | |
1220 | flags = F_CMD_DATAVALID | F_CMD_SOP | | |
1221 | V_CMD_EOP(nfrags == 0 && desc_len <= SGE_TX_DESC_MAX_PLEN) | | |
1222 | V_CMD_GEN2(gen); | |
1223 | first_desc_len = (desc_len <= SGE_TX_DESC_MAX_PLEN) ? | |
1224 | desc_len : SGE_TX_DESC_MAX_PLEN; | |
1225 | e->addr_lo = (u32)desc_mapping; | |
1226 | e->addr_hi = (u64)desc_mapping >> 32; | |
1227 | e->len_gen = V_CMD_LEN(first_desc_len) | V_CMD_GEN1(gen); | |
1228 | ce->skb = NULL; | |
094f92a6 | 1229 | dma_unmap_len_set(ce, dma_len, 0); |
f1d3d38a SH |
1230 | |
1231 | if (PAGE_SIZE > SGE_TX_DESC_MAX_PLEN && | |
1232 | desc_len > SGE_TX_DESC_MAX_PLEN) { | |
1233 | desc_mapping += first_desc_len; | |
1234 | desc_len -= first_desc_len; | |
1235 | e1++; | |
1236 | ce++; | |
1237 | if (++pidx == q->size) { | |
1238 | pidx = 0; | |
1239 | gen ^= 1; | |
1240 | e1 = q->entries; | |
1241 | ce = q->centries; | |
1242 | } | |
1243 | pidx = write_large_page_tx_descs(pidx, &e1, &ce, &gen, | |
1244 | &desc_mapping, &desc_len, | |
1245 | nfrags, q); | |
1246 | ||
1247 | if (likely(desc_len)) | |
1248 | write_tx_desc(e1, desc_mapping, desc_len, gen, | |
1249 | nfrags == 0); | |
1250 | } | |
1251 | ||
559fb51b | 1252 | ce->skb = NULL; |
094f92a6 | 1253 | dma_unmap_addr_set(ce, dma_addr, mapping); |
e743d313 | 1254 | dma_unmap_len_set(ce, dma_len, skb_headlen(skb)); |
8199d3a7 | 1255 | |
f1d3d38a | 1256 | for (i = 0; nfrags--; i++) { |
559fb51b | 1257 | skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; |
559fb51b | 1258 | e1++; |
f1d3d38a | 1259 | ce++; |
559fb51b SB |
1260 | if (++pidx == q->size) { |
1261 | pidx = 0; | |
1262 | gen ^= 1; | |
559fb51b | 1263 | e1 = q->entries; |
f1d3d38a | 1264 | ce = q->centries; |
8199d3a7 | 1265 | } |
8199d3a7 | 1266 | |
01139222 | 1267 | mapping = skb_frag_dma_map(&adapter->pdev->dev, frag, 0, |
9e903e08 | 1268 | skb_frag_size(frag), DMA_TO_DEVICE); |
f1d3d38a | 1269 | desc_mapping = mapping; |
9e903e08 | 1270 | desc_len = skb_frag_size(frag); |
f1d3d38a SH |
1271 | |
1272 | pidx = write_large_page_tx_descs(pidx, &e1, &ce, &gen, | |
1273 | &desc_mapping, &desc_len, | |
1274 | nfrags, q); | |
1275 | if (likely(desc_len)) | |
1276 | write_tx_desc(e1, desc_mapping, desc_len, gen, | |
1277 | nfrags == 0); | |
559fb51b | 1278 | ce->skb = NULL; |
094f92a6 | 1279 | dma_unmap_addr_set(ce, dma_addr, mapping); |
9e903e08 | 1280 | dma_unmap_len_set(ce, dma_len, skb_frag_size(frag)); |
8199d3a7 | 1281 | } |
559fb51b SB |
1282 | ce->skb = skb; |
1283 | wmb(); | |
1284 | e->flags = flags; | |
1285 | } | |
8199d3a7 | 1286 | |
559fb51b SB |
1287 | /* |
1288 | * Clean up completed Tx buffers. | |
1289 | */ | |
1290 | static inline void reclaim_completed_tx(struct sge *sge, struct cmdQ *q) | |
1291 | { | |
1292 | unsigned int reclaim = q->processed - q->cleaned; | |
8199d3a7 | 1293 | |
559fb51b | 1294 | if (reclaim) { |
f1d3d38a SH |
1295 | pr_debug("reclaim_completed_tx processed:%d cleaned:%d\n", |
1296 | q->processed, q->cleaned); | |
559fb51b SB |
1297 | free_cmdQ_buffers(sge, q, reclaim); |
1298 | q->cleaned += reclaim; | |
8199d3a7 | 1299 | } |
559fb51b | 1300 | } |
8199d3a7 | 1301 | |
f1d3d38a SH |
1302 | /* |
1303 | * Called from tasklet. Checks the scheduler for any | |
1304 | * pending skbs that can be sent. | |
1305 | */ | |
1306 | static void restart_sched(unsigned long arg) | |
1307 | { | |
1308 | struct sge *sge = (struct sge *) arg; | |
1309 | struct adapter *adapter = sge->adapter; | |
1310 | struct cmdQ *q = &sge->cmdQ[0]; | |
1311 | struct sk_buff *skb; | |
1312 | unsigned int credits, queued_skb = 0; | |
1313 | ||
1314 | spin_lock(&q->lock); | |
1315 | reclaim_completed_tx(sge, q); | |
1316 | ||
1317 | credits = q->size - q->in_use; | |
1318 | pr_debug("restart_sched credits=%d\n", credits); | |
1319 | while ((skb = sched_skb(sge, NULL, credits)) != NULL) { | |
1320 | unsigned int genbit, pidx, count; | |
1321 | count = 1 + skb_shinfo(skb)->nr_frags; | |
356bd146 | 1322 | count += compute_large_page_tx_descs(skb); |
f1d3d38a SH |
1323 | q->in_use += count; |
1324 | genbit = q->genbit; | |
1325 | pidx = q->pidx; | |
1326 | q->pidx += count; | |
1327 | if (q->pidx >= q->size) { | |
1328 | q->pidx -= q->size; | |
1329 | q->genbit ^= 1; | |
1330 | } | |
1331 | write_tx_descs(adapter, skb, pidx, genbit, q); | |
1332 | credits = q->size - q->in_use; | |
1333 | queued_skb = 1; | |
1334 | } | |
1335 | ||
1336 | if (queued_skb) { | |
1337 | clear_bit(CMDQ_STAT_LAST_PKT_DB, &q->status); | |
1338 | if (test_and_set_bit(CMDQ_STAT_RUNNING, &q->status) == 0) { | |
1339 | set_bit(CMDQ_STAT_LAST_PKT_DB, &q->status); | |
1340 | writel(F_CMDQ0_ENABLE, adapter->regs + A_SG_DOORBELL); | |
1341 | } | |
1342 | } | |
1343 | spin_unlock(&q->lock); | |
1344 | } | |
8199d3a7 | 1345 | |
559fb51b SB |
1346 | /** |
1347 | * sge_rx - process an ingress ethernet packet | |
1348 | * @sge: the sge structure | |
1349 | * @fl: the free list that contains the packet buffer | |
1350 | * @len: the packet length | |
8199d3a7 | 1351 | * |
559fb51b | 1352 | * Process an ingress ethernet pakcet and deliver it to the stack. |
8199d3a7 | 1353 | */ |
24a427cf | 1354 | static void sge_rx(struct sge *sge, struct freelQ *fl, unsigned int len) |
8199d3a7 | 1355 | { |
559fb51b | 1356 | struct sk_buff *skb; |
24a427cf | 1357 | const struct cpl_rx_pkt *p; |
559fb51b | 1358 | struct adapter *adapter = sge->adapter; |
56f643c2 | 1359 | struct sge_port_stats *st; |
30f554f9 | 1360 | struct net_device *dev; |
8199d3a7 | 1361 | |
24a427cf | 1362 | skb = get_packet(adapter->pdev, fl, len - sge->rx_pkt_pad); |
56f643c2 SH |
1363 | if (unlikely(!skb)) { |
1364 | sge->stats.rx_drops++; | |
24a427cf | 1365 | return; |
8199d3a7 | 1366 | } |
559fb51b | 1367 | |
24a427cf | 1368 | p = (const struct cpl_rx_pkt *) skb->data; |
f1d3d38a SH |
1369 | if (p->iff >= adapter->params.nports) { |
1370 | kfree_skb(skb); | |
24a427cf | 1371 | return; |
f1d3d38a | 1372 | } |
24a427cf | 1373 | __skb_pull(skb, sizeof(*p)); |
f1d3d38a | 1374 | |
ca0c9584 | 1375 | st = this_cpu_ptr(sge->port_stats[p->iff]); |
30f554f9 | 1376 | dev = adapter->port[p->iff].dev; |
56f643c2 | 1377 | |
30f554f9 MM |
1378 | skb->protocol = eth_type_trans(skb, dev); |
1379 | if ((dev->features & NETIF_F_RXCSUM) && p->csum == 0xffff && | |
559fb51b SB |
1380 | skb->protocol == htons(ETH_P_IP) && |
1381 | (skb->data[9] == IPPROTO_TCP || skb->data[9] == IPPROTO_UDP)) { | |
56f643c2 | 1382 | ++st->rx_cso_good; |
559fb51b SB |
1383 | skb->ip_summed = CHECKSUM_UNNECESSARY; |
1384 | } else | |
bc8acf2c | 1385 | skb_checksum_none_assert(skb); |
559fb51b | 1386 | |
133b0851 | 1387 | if (p->vlan_valid) { |
56f643c2 | 1388 | st->vlan_xtract++; |
133b0851 JP |
1389 | __vlan_hwaccel_put_tag(skb, ntohs(p->vlan)); |
1390 | } | |
1391 | netif_receive_skb(skb); | |
8199d3a7 CL |
1392 | } |
1393 | ||
1394 | /* | |
559fb51b | 1395 | * Returns true if a command queue has enough available descriptors that |
8199d3a7 CL |
1396 | * we can resume Tx operation after temporarily disabling its packet queue. |
1397 | */ | |
559fb51b | 1398 | static inline int enough_free_Tx_descs(const struct cmdQ *q) |
8199d3a7 | 1399 | { |
559fb51b SB |
1400 | unsigned int r = q->processed - q->cleaned; |
1401 | ||
1402 | return q->in_use - r < (q->size >> 1); | |
8199d3a7 CL |
1403 | } |
1404 | ||
1405 | /* | |
559fb51b SB |
1406 | * Called when sufficient space has become available in the SGE command queues |
1407 | * after the Tx packet schedulers have been suspended to restart the Tx path. | |
8199d3a7 | 1408 | */ |
559fb51b | 1409 | static void restart_tx_queues(struct sge *sge) |
8199d3a7 | 1410 | { |
559fb51b | 1411 | struct adapter *adap = sge->adapter; |
3e0f75be | 1412 | int i; |
8199d3a7 | 1413 | |
3e0f75be FR |
1414 | if (!enough_free_Tx_descs(&sge->cmdQ[0])) |
1415 | return; | |
559fb51b | 1416 | |
3e0f75be FR |
1417 | for_each_port(adap, i) { |
1418 | struct net_device *nd = adap->port[i].dev; | |
559fb51b | 1419 | |
3e0f75be FR |
1420 | if (test_and_clear_bit(nd->if_port, &sge->stopped_tx_queues) && |
1421 | netif_running(nd)) { | |
1422 | sge->stats.cmdQ_restarted[2]++; | |
1423 | netif_wake_queue(nd); | |
559fb51b SB |
1424 | } |
1425 | } | |
1426 | } | |
1427 | ||
1428 | /* | |
356bd146 | 1429 | * update_tx_info is called from the interrupt handler/NAPI to return cmdQ0 |
559fb51b SB |
1430 | * information. |
1431 | */ | |
356bd146 FR |
1432 | static unsigned int update_tx_info(struct adapter *adapter, |
1433 | unsigned int flags, | |
559fb51b SB |
1434 | unsigned int pr0) |
1435 | { | |
1436 | struct sge *sge = adapter->sge; | |
1437 | struct cmdQ *cmdq = &sge->cmdQ[0]; | |
8199d3a7 | 1438 | |
559fb51b | 1439 | cmdq->processed += pr0; |
f1d3d38a SH |
1440 | if (flags & (F_FL0_ENABLE | F_FL1_ENABLE)) { |
1441 | freelQs_empty(sge); | |
1442 | flags &= ~(F_FL0_ENABLE | F_FL1_ENABLE); | |
1443 | } | |
559fb51b SB |
1444 | if (flags & F_CMDQ0_ENABLE) { |
1445 | clear_bit(CMDQ_STAT_RUNNING, &cmdq->status); | |
f1d3d38a | 1446 | |
559fb51b SB |
1447 | if (cmdq->cleaned + cmdq->in_use != cmdq->processed && |
1448 | !test_and_set_bit(CMDQ_STAT_LAST_PKT_DB, &cmdq->status)) { | |
1449 | set_bit(CMDQ_STAT_RUNNING, &cmdq->status); | |
1450 | writel(F_CMDQ0_ENABLE, adapter->regs + A_SG_DOORBELL); | |
1451 | } | |
f1d3d38a SH |
1452 | if (sge->tx_sched) |
1453 | tasklet_hi_schedule(&sge->tx_sched->sched_tsk); | |
1454 | ||
1455 | flags &= ~F_CMDQ0_ENABLE; | |
559fb51b | 1456 | } |
f1d3d38a | 1457 | |
559fb51b SB |
1458 | if (unlikely(sge->stopped_tx_queues != 0)) |
1459 | restart_tx_queues(sge); | |
8199d3a7 | 1460 | |
559fb51b SB |
1461 | return flags; |
1462 | } | |
8199d3a7 | 1463 | |
559fb51b SB |
1464 | /* |
1465 | * Process SGE responses, up to the supplied budget. Returns the number of | |
1466 | * responses processed. A negative budget is effectively unlimited. | |
1467 | */ | |
1468 | static int process_responses(struct adapter *adapter, int budget) | |
1469 | { | |
1470 | struct sge *sge = adapter->sge; | |
1471 | struct respQ *q = &sge->respQ; | |
1472 | struct respQ_e *e = &q->entries[q->cidx]; | |
24a427cf | 1473 | int done = 0; |
559fb51b SB |
1474 | unsigned int flags = 0; |
1475 | unsigned int cmdq_processed[SGE_CMDQ_N] = {0, 0}; | |
356bd146 | 1476 | |
24a427cf | 1477 | while (done < budget && e->GenerationBit == q->genbit) { |
559fb51b | 1478 | flags |= e->Qsleeping; |
356bd146 | 1479 | |
559fb51b SB |
1480 | cmdq_processed[0] += e->Cmdq0CreditReturn; |
1481 | cmdq_processed[1] += e->Cmdq1CreditReturn; | |
356bd146 | 1482 | |
559fb51b SB |
1483 | /* We batch updates to the TX side to avoid cacheline |
1484 | * ping-pong of TX state information on MP where the sender | |
1485 | * might run on a different CPU than this function... | |
1486 | */ | |
24a427cf | 1487 | if (unlikely((flags & F_CMDQ0_ENABLE) || cmdq_processed[0] > 64)) { |
559fb51b SB |
1488 | flags = update_tx_info(adapter, flags, cmdq_processed[0]); |
1489 | cmdq_processed[0] = 0; | |
1490 | } | |
24a427cf | 1491 | |
559fb51b SB |
1492 | if (unlikely(cmdq_processed[1] > 16)) { |
1493 | sge->cmdQ[1].processed += cmdq_processed[1]; | |
1494 | cmdq_processed[1] = 0; | |
8199d3a7 | 1495 | } |
24a427cf | 1496 | |
8199d3a7 | 1497 | if (likely(e->DataValid)) { |
559fb51b SB |
1498 | struct freelQ *fl = &sge->freelQ[e->FreelistQid]; |
1499 | ||
5d9428de | 1500 | BUG_ON(!e->Sop || !e->Eop); |
559fb51b SB |
1501 | if (unlikely(e->Offload)) |
1502 | unexpected_offload(adapter, fl); | |
1503 | else | |
1504 | sge_rx(sge, fl, e->BufferLength); | |
1505 | ||
24a427cf SH |
1506 | ++done; |
1507 | ||
559fb51b SB |
1508 | /* |
1509 | * Note: this depends on each packet consuming a | |
1510 | * single free-list buffer; cf. the BUG above. | |
1511 | */ | |
1512 | if (++fl->cidx == fl->size) | |
1513 | fl->cidx = 0; | |
24a427cf SH |
1514 | prefetch(fl->centries[fl->cidx].skb); |
1515 | ||
559fb51b SB |
1516 | if (unlikely(--fl->credits < |
1517 | fl->size - SGE_FREEL_REFILL_THRESH)) | |
1518 | refill_free_list(sge, fl); | |
1519 | } else | |
1520 | sge->stats.pure_rsps++; | |
8199d3a7 | 1521 | |
8199d3a7 | 1522 | e++; |
559fb51b SB |
1523 | if (unlikely(++q->cidx == q->size)) { |
1524 | q->cidx = 0; | |
1525 | q->genbit ^= 1; | |
1526 | e = q->entries; | |
1527 | } | |
1528 | prefetch(e); | |
1529 | ||
1530 | if (++q->credits > SGE_RESPQ_REPLENISH_THRES) { | |
1531 | writel(q->credits, adapter->regs + A_SG_RSPQUEUECREDIT); | |
1532 | q->credits = 0; | |
8199d3a7 CL |
1533 | } |
1534 | } | |
1535 | ||
356bd146 | 1536 | flags = update_tx_info(adapter, flags, cmdq_processed[0]); |
559fb51b | 1537 | sge->cmdQ[1].processed += cmdq_processed[1]; |
8199d3a7 | 1538 | |
24a427cf | 1539 | return done; |
559fb51b | 1540 | } |
8199d3a7 | 1541 | |
3de00b89 SH |
1542 | static inline int responses_pending(const struct adapter *adapter) |
1543 | { | |
1544 | const struct respQ *Q = &adapter->sge->respQ; | |
1545 | const struct respQ_e *e = &Q->entries[Q->cidx]; | |
1546 | ||
807540ba | 1547 | return e->GenerationBit == Q->genbit; |
3de00b89 SH |
1548 | } |
1549 | ||
559fb51b SB |
1550 | /* |
1551 | * A simpler version of process_responses() that handles only pure (i.e., | |
1552 | * non data-carrying) responses. Such respones are too light-weight to justify | |
1553 | * calling a softirq when using NAPI, so we handle them specially in hard | |
1554 | * interrupt context. The function is called with a pointer to a response, | |
1555 | * which the caller must ensure is a valid pure response. Returns 1 if it | |
1556 | * encounters a valid data-carrying response, 0 otherwise. | |
1557 | */ | |
3de00b89 | 1558 | static int process_pure_responses(struct adapter *adapter) |
559fb51b SB |
1559 | { |
1560 | struct sge *sge = adapter->sge; | |
1561 | struct respQ *q = &sge->respQ; | |
3de00b89 | 1562 | struct respQ_e *e = &q->entries[q->cidx]; |
24a427cf | 1563 | const struct freelQ *fl = &sge->freelQ[e->FreelistQid]; |
559fb51b SB |
1564 | unsigned int flags = 0; |
1565 | unsigned int cmdq_processed[SGE_CMDQ_N] = {0, 0}; | |
8199d3a7 | 1566 | |
24a427cf | 1567 | prefetch(fl->centries[fl->cidx].skb); |
3de00b89 SH |
1568 | if (e->DataValid) |
1569 | return 1; | |
24a427cf | 1570 | |
559fb51b SB |
1571 | do { |
1572 | flags |= e->Qsleeping; | |
8199d3a7 | 1573 | |
559fb51b SB |
1574 | cmdq_processed[0] += e->Cmdq0CreditReturn; |
1575 | cmdq_processed[1] += e->Cmdq1CreditReturn; | |
356bd146 | 1576 | |
559fb51b SB |
1577 | e++; |
1578 | if (unlikely(++q->cidx == q->size)) { | |
1579 | q->cidx = 0; | |
1580 | q->genbit ^= 1; | |
1581 | e = q->entries; | |
8199d3a7 | 1582 | } |
559fb51b | 1583 | prefetch(e); |
8199d3a7 | 1584 | |
559fb51b SB |
1585 | if (++q->credits > SGE_RESPQ_REPLENISH_THRES) { |
1586 | writel(q->credits, adapter->regs + A_SG_RSPQUEUECREDIT); | |
1587 | q->credits = 0; | |
8199d3a7 | 1588 | } |
559fb51b SB |
1589 | sge->stats.pure_rsps++; |
1590 | } while (e->GenerationBit == q->genbit && !e->DataValid); | |
8199d3a7 | 1591 | |
356bd146 | 1592 | flags = update_tx_info(adapter, flags, cmdq_processed[0]); |
559fb51b | 1593 | sge->cmdQ[1].processed += cmdq_processed[1]; |
8199d3a7 | 1594 | |
559fb51b | 1595 | return e->GenerationBit == q->genbit; |
8199d3a7 CL |
1596 | } |
1597 | ||
1598 | /* | |
559fb51b SB |
1599 | * Handler for new data events when using NAPI. This does not need any locking |
1600 | * or protection from interrupts as data interrupts are off at this point and | |
1601 | * other adapter interrupts do not interfere. | |
8199d3a7 | 1602 | */ |
bea3348e | 1603 | int t1_poll(struct napi_struct *napi, int budget) |
8199d3a7 | 1604 | { |
bea3348e | 1605 | struct adapter *adapter = container_of(napi, struct adapter, napi); |
445cf803 | 1606 | int work_done = process_responses(adapter, budget); |
7fe26a60 | 1607 | |
445cf803 | 1608 | if (likely(work_done < budget)) { |
288379f0 | 1609 | napi_complete(napi); |
bea3348e SH |
1610 | writel(adapter->sge->respQ.cidx, |
1611 | adapter->regs + A_SG_SLEEPING); | |
1612 | } | |
1613 | return work_done; | |
559fb51b | 1614 | } |
8199d3a7 | 1615 | |
7fe26a60 | 1616 | irqreturn_t t1_interrupt(int irq, void *data) |
559fb51b | 1617 | { |
559fb51b SB |
1618 | struct adapter *adapter = data; |
1619 | struct sge *sge = adapter->sge; | |
3de00b89 | 1620 | int handled; |
559fb51b | 1621 | |
3de00b89 | 1622 | if (likely(responses_pending(adapter))) { |
356bd146 | 1623 | writel(F_PL_INTR_SGE_DATA, adapter->regs + A_PL_CAUSE); |
7fe26a60 | 1624 | |
bea3348e | 1625 | if (napi_schedule_prep(&adapter->napi)) { |
3de00b89 | 1626 | if (process_pure_responses(adapter)) |
288379f0 | 1627 | __napi_schedule(&adapter->napi); |
3de00b89 SH |
1628 | else { |
1629 | /* no data, no NAPI needed */ | |
1630 | writel(sge->respQ.cidx, adapter->regs + A_SG_SLEEPING); | |
4422b003 FR |
1631 | /* undo schedule_prep */ |
1632 | napi_enable(&adapter->napi); | |
7fe26a60 | 1633 | } |
7fe26a60 | 1634 | } |
3de00b89 SH |
1635 | return IRQ_HANDLED; |
1636 | } | |
1637 | ||
1638 | spin_lock(&adapter->async_lock); | |
1639 | handled = t1_slow_intr_handler(adapter); | |
1640 | spin_unlock(&adapter->async_lock); | |
7fe26a60 | 1641 | |
559fb51b SB |
1642 | if (!handled) |
1643 | sge->stats.unhandled_irqs++; | |
3de00b89 | 1644 | |
559fb51b SB |
1645 | return IRQ_RETVAL(handled != 0); |
1646 | } | |
8199d3a7 | 1647 | |
559fb51b SB |
1648 | /* |
1649 | * Enqueues the sk_buff onto the cmdQ[qid] and has hardware fetch it. | |
1650 | * | |
1651 | * The code figures out how many entries the sk_buff will require in the | |
1652 | * cmdQ and updates the cmdQ data structure with the state once the enqueue | |
1653 | * has complete. Then, it doesn't access the global structure anymore, but | |
25985edc | 1654 | * uses the corresponding fields on the stack. In conjunction with a spinlock |
559fb51b SB |
1655 | * around that code, we can make the function reentrant without holding the |
1656 | * lock when we actually enqueue (which might be expensive, especially on | |
1657 | * architectures with IO MMUs). | |
1658 | * | |
1659 | * This runs with softirqs disabled. | |
1660 | */ | |
aa84505f SH |
1661 | static int t1_sge_tx(struct sk_buff *skb, struct adapter *adapter, |
1662 | unsigned int qid, struct net_device *dev) | |
559fb51b SB |
1663 | { |
1664 | struct sge *sge = adapter->sge; | |
1665 | struct cmdQ *q = &sge->cmdQ[qid]; | |
f1d3d38a | 1666 | unsigned int credits, pidx, genbit, count, use_sched_skb = 0; |
559fb51b | 1667 | |
cabdfb37 SH |
1668 | if (!spin_trylock(&q->lock)) |
1669 | return NETDEV_TX_LOCKED; | |
1670 | ||
559fb51b SB |
1671 | reclaim_completed_tx(sge, q); |
1672 | ||
1673 | pidx = q->pidx; | |
1674 | credits = q->size - q->in_use; | |
1675 | count = 1 + skb_shinfo(skb)->nr_frags; | |
f1d3d38a | 1676 | count += compute_large_page_tx_descs(skb); |
559fb51b | 1677 | |
f1d3d38a SH |
1678 | /* Ethernet packet */ |
1679 | if (unlikely(credits < count)) { | |
1680 | if (!netif_queue_stopped(dev)) { | |
559fb51b SB |
1681 | netif_stop_queue(dev); |
1682 | set_bit(dev->if_port, &sge->stopped_tx_queues); | |
232a347a | 1683 | sge->stats.cmdQ_full[2]++; |
c1f51212 | 1684 | pr_err("%s: Tx ring full while queue awake!\n", |
f1d3d38a | 1685 | adapter->name); |
8199d3a7 | 1686 | } |
f1d3d38a SH |
1687 | spin_unlock(&q->lock); |
1688 | return NETDEV_TX_BUSY; | |
1689 | } | |
1690 | ||
1691 | if (unlikely(credits - count < q->stop_thres)) { | |
1692 | netif_stop_queue(dev); | |
1693 | set_bit(dev->if_port, &sge->stopped_tx_queues); | |
1694 | sge->stats.cmdQ_full[2]++; | |
1695 | } | |
1696 | ||
1697 | /* T204 cmdQ0 skbs that are destined for a certain port have to go | |
1698 | * through the scheduler. | |
1699 | */ | |
1700 | if (sge->tx_sched && !qid && skb->dev) { | |
356bd146 | 1701 | use_sched: |
f1d3d38a SH |
1702 | use_sched_skb = 1; |
1703 | /* Note that the scheduler might return a different skb than | |
1704 | * the one passed in. | |
1705 | */ | |
1706 | skb = sched_skb(sge, skb, credits); | |
1707 | if (!skb) { | |
1708 | spin_unlock(&q->lock); | |
1709 | return NETDEV_TX_OK; | |
559fb51b | 1710 | } |
f1d3d38a SH |
1711 | pidx = q->pidx; |
1712 | count = 1 + skb_shinfo(skb)->nr_frags; | |
1713 | count += compute_large_page_tx_descs(skb); | |
559fb51b | 1714 | } |
f1d3d38a | 1715 | |
559fb51b SB |
1716 | q->in_use += count; |
1717 | genbit = q->genbit; | |
f1d3d38a | 1718 | pidx = q->pidx; |
559fb51b SB |
1719 | q->pidx += count; |
1720 | if (q->pidx >= q->size) { | |
1721 | q->pidx -= q->size; | |
1722 | q->genbit ^= 1; | |
8199d3a7 | 1723 | } |
559fb51b | 1724 | spin_unlock(&q->lock); |
8199d3a7 | 1725 | |
559fb51b | 1726 | write_tx_descs(adapter, skb, pidx, genbit, q); |
8199d3a7 CL |
1727 | |
1728 | /* | |
1729 | * We always ring the doorbell for cmdQ1. For cmdQ0, we only ring | |
1730 | * the doorbell if the Q is asleep. There is a natural race, where | |
1731 | * the hardware is going to sleep just after we checked, however, | |
1732 | * then the interrupt handler will detect the outstanding TX packet | |
1733 | * and ring the doorbell for us. | |
1734 | */ | |
559fb51b SB |
1735 | if (qid) |
1736 | doorbell_pio(adapter, F_CMDQ1_ENABLE); | |
1737 | else { | |
1738 | clear_bit(CMDQ_STAT_LAST_PKT_DB, &q->status); | |
1739 | if (test_and_set_bit(CMDQ_STAT_RUNNING, &q->status) == 0) { | |
1740 | set_bit(CMDQ_STAT_LAST_PKT_DB, &q->status); | |
1741 | writel(F_CMDQ0_ENABLE, adapter->regs + A_SG_DOORBELL); | |
1742 | } | |
8199d3a7 | 1743 | } |
f1d3d38a SH |
1744 | |
1745 | if (use_sched_skb) { | |
1746 | if (spin_trylock(&q->lock)) { | |
1747 | credits = q->size - q->in_use; | |
1748 | skb = NULL; | |
1749 | goto use_sched; | |
1750 | } | |
1751 | } | |
aa84505f | 1752 | return NETDEV_TX_OK; |
8199d3a7 CL |
1753 | } |
1754 | ||
1755 | #define MK_ETH_TYPE_MSS(type, mss) (((mss) & 0x3FFF) | ((type) << 14)) | |
1756 | ||
559fb51b SB |
1757 | /* |
1758 | * eth_hdr_len - return the length of an Ethernet header | |
1759 | * @data: pointer to the start of the Ethernet header | |
1760 | * | |
1761 | * Returns the length of an Ethernet header, including optional VLAN tag. | |
1762 | */ | |
1763 | static inline int eth_hdr_len(const void *data) | |
1764 | { | |
1765 | const struct ethhdr *e = data; | |
1766 | ||
1767 | return e->h_proto == htons(ETH_P_8021Q) ? VLAN_ETH_HLEN : ETH_HLEN; | |
1768 | } | |
1769 | ||
8199d3a7 CL |
1770 | /* |
1771 | * Adds the CPL header to the sk_buff and passes it to t1_sge_tx. | |
1772 | */ | |
61357325 | 1773 | netdev_tx_t t1_start_xmit(struct sk_buff *skb, struct net_device *dev) |
8199d3a7 | 1774 | { |
c3ccc123 | 1775 | struct adapter *adapter = dev->ml_priv; |
559fb51b | 1776 | struct sge *sge = adapter->sge; |
ca0c9584 | 1777 | struct sge_port_stats *st = this_cpu_ptr(sge->port_stats[dev->if_port]); |
8199d3a7 | 1778 | struct cpl_tx_pkt *cpl; |
cabdfb37 SH |
1779 | struct sk_buff *orig_skb = skb; |
1780 | int ret; | |
8199d3a7 | 1781 | |
f1d3d38a SH |
1782 | if (skb->protocol == htons(ETH_P_CPL5)) |
1783 | goto send; | |
1784 | ||
7832ee03 DLR |
1785 | /* |
1786 | * We are using a non-standard hard_header_len. | |
1787 | * Allocate more header room in the rare cases it is not big enough. | |
1788 | */ | |
1789 | if (unlikely(skb_headroom(skb) < dev->hard_header_len - ETH_HLEN)) { | |
1790 | skb = skb_realloc_headroom(skb, sizeof(struct cpl_tx_pkt_lso)); | |
1791 | ++st->tx_need_hdrroom; | |
1792 | dev_kfree_skb_any(orig_skb); | |
1793 | if (!skb) | |
1794 | return NETDEV_TX_OK; | |
1795 | } | |
1796 | ||
f1d3d38a | 1797 | if (skb_shinfo(skb)->gso_size) { |
8199d3a7 CL |
1798 | int eth_type; |
1799 | struct cpl_tx_pkt_lso *hdr; | |
1800 | ||
56f643c2 | 1801 | ++st->tx_tso; |
559fb51b | 1802 | |
bbe735e4 | 1803 | eth_type = skb_network_offset(skb) == ETH_HLEN ? |
8199d3a7 CL |
1804 | CPL_ETH_II : CPL_ETH_II_VLAN; |
1805 | ||
1806 | hdr = (struct cpl_tx_pkt_lso *)skb_push(skb, sizeof(*hdr)); | |
1807 | hdr->opcode = CPL_TX_PKT_LSO; | |
1808 | hdr->ip_csum_dis = hdr->l4_csum_dis = 0; | |
eddc9ec5 | 1809 | hdr->ip_hdr_words = ip_hdr(skb)->ihl; |
aa8223c7 | 1810 | hdr->tcp_hdr_words = tcp_hdr(skb)->doff; |
8199d3a7 | 1811 | hdr->eth_type_mss = htons(MK_ETH_TYPE_MSS(eth_type, |
f1d3d38a | 1812 | skb_shinfo(skb)->gso_size)); |
8199d3a7 CL |
1813 | hdr->len = htonl(skb->len - sizeof(*hdr)); |
1814 | cpl = (struct cpl_tx_pkt *)hdr; | |
f1d3d38a | 1815 | } else { |
8199d3a7 | 1816 | /* |
356bd146 | 1817 | * Packets shorter than ETH_HLEN can break the MAC, drop them |
559fb51b SB |
1818 | * early. Also, we may get oversized packets because some |
1819 | * parts of the kernel don't handle our unusual hard_header_len | |
1820 | * right, drop those too. | |
8199d3a7 | 1821 | */ |
559fb51b SB |
1822 | if (unlikely(skb->len < ETH_HLEN || |
1823 | skb->len > dev->mtu + eth_hdr_len(skb->data))) { | |
428ac43f JP |
1824 | netdev_dbg(dev, "packet size %d hdr %d mtu%d\n", |
1825 | skb->len, eth_hdr_len(skb->data), dev->mtu); | |
559fb51b | 1826 | dev_kfree_skb_any(skb); |
aa84505f | 1827 | return NETDEV_TX_OK; |
559fb51b SB |
1828 | } |
1829 | ||
30f554f9 | 1830 | if (skb->ip_summed == CHECKSUM_PARTIAL && |
eddc9ec5 | 1831 | ip_hdr(skb)->protocol == IPPROTO_UDP) { |
84fa7933 | 1832 | if (unlikely(skb_checksum_help(skb))) { |
428ac43f | 1833 | netdev_dbg(dev, "unable to do udp checksum\n"); |
559fb51b | 1834 | dev_kfree_skb_any(skb); |
aa84505f | 1835 | return NETDEV_TX_OK; |
559fb51b | 1836 | } |
f1d3d38a | 1837 | } |
8199d3a7 | 1838 | |
559fb51b SB |
1839 | /* Hmmm, assuming to catch the gratious arp... and we'll use |
1840 | * it to flush out stuck espi packets... | |
f1d3d38a SH |
1841 | */ |
1842 | if ((unlikely(!adapter->sge->espibug_skb[dev->if_port]))) { | |
8199d3a7 | 1843 | if (skb->protocol == htons(ETH_P_ARP) && |
d0a92be0 | 1844 | arp_hdr(skb)->ar_op == htons(ARPOP_REQUEST)) { |
f1d3d38a | 1845 | adapter->sge->espibug_skb[dev->if_port] = skb; |
559fb51b SB |
1846 | /* We want to re-use this skb later. We |
1847 | * simply bump the reference count and it | |
1848 | * will not be freed... | |
1849 | */ | |
1850 | skb = skb_get(skb); | |
1851 | } | |
8199d3a7 | 1852 | } |
559fb51b SB |
1853 | |
1854 | cpl = (struct cpl_tx_pkt *)__skb_push(skb, sizeof(*cpl)); | |
8199d3a7 CL |
1855 | cpl->opcode = CPL_TX_PKT; |
1856 | cpl->ip_csum_dis = 1; /* SW calculates IP csum */ | |
84fa7933 | 1857 | cpl->l4_csum_dis = skb->ip_summed == CHECKSUM_PARTIAL ? 0 : 1; |
8199d3a7 | 1858 | /* the length field isn't used so don't bother setting it */ |
559fb51b | 1859 | |
84fa7933 | 1860 | st->tx_cso += (skb->ip_summed == CHECKSUM_PARTIAL); |
8199d3a7 CL |
1861 | } |
1862 | cpl->iff = dev->if_port; | |
1863 | ||
eab6d18d | 1864 | if (vlan_tx_tag_present(skb)) { |
8199d3a7 CL |
1865 | cpl->vlan_valid = 1; |
1866 | cpl->vlan = htons(vlan_tx_tag_get(skb)); | |
559fb51b | 1867 | st->vlan_insert++; |
8199d3a7 | 1868 | } else |
8199d3a7 CL |
1869 | cpl->vlan_valid = 0; |
1870 | ||
f1d3d38a | 1871 | send: |
cabdfb37 SH |
1872 | ret = t1_sge_tx(skb, adapter, 0, dev); |
1873 | ||
1874 | /* If transmit busy, and we reallocated skb's due to headroom limit, | |
1875 | * then silently discard to avoid leak. | |
1876 | */ | |
1877 | if (unlikely(ret != NETDEV_TX_OK && skb != orig_skb)) { | |
356bd146 | 1878 | dev_kfree_skb_any(skb); |
cabdfb37 | 1879 | ret = NETDEV_TX_OK; |
356bd146 | 1880 | } |
cabdfb37 | 1881 | return ret; |
559fb51b | 1882 | } |
8199d3a7 | 1883 | |
559fb51b SB |
1884 | /* |
1885 | * Callback for the Tx buffer reclaim timer. Runs with softirqs disabled. | |
1886 | */ | |
1887 | static void sge_tx_reclaim_cb(unsigned long data) | |
1888 | { | |
1889 | int i; | |
1890 | struct sge *sge = (struct sge *)data; | |
1891 | ||
1892 | for (i = 0; i < SGE_CMDQ_N; ++i) { | |
1893 | struct cmdQ *q = &sge->cmdQ[i]; | |
1894 | ||
1895 | if (!spin_trylock(&q->lock)) | |
1896 | continue; | |
8199d3a7 | 1897 | |
559fb51b | 1898 | reclaim_completed_tx(sge, q); |
f1d3d38a SH |
1899 | if (i == 0 && q->in_use) { /* flush pending credits */ |
1900 | writel(F_CMDQ0_ENABLE, sge->adapter->regs + A_SG_DOORBELL); | |
1901 | } | |
559fb51b SB |
1902 | spin_unlock(&q->lock); |
1903 | } | |
1904 | mod_timer(&sge->tx_reclaim_timer, jiffies + TX_RECLAIM_PERIOD); | |
1905 | } | |
1906 | ||
1907 | /* | |
1908 | * Propagate changes of the SGE coalescing parameters to the HW. | |
1909 | */ | |
1910 | int t1_sge_set_coalesce_params(struct sge *sge, struct sge_params *p) | |
1911 | { | |
559fb51b SB |
1912 | sge->fixed_intrtimer = p->rx_coalesce_usecs * |
1913 | core_ticks_per_usec(sge->adapter); | |
1914 | writel(sge->fixed_intrtimer, sge->adapter->regs + A_SG_INTRTIMER); | |
8199d3a7 CL |
1915 | return 0; |
1916 | } | |
1917 | ||
559fb51b SB |
1918 | /* |
1919 | * Allocates both RX and TX resources and configures the SGE. However, | |
1920 | * the hardware is not enabled yet. | |
1921 | */ | |
1922 | int t1_sge_configure(struct sge *sge, struct sge_params *p) | |
8199d3a7 | 1923 | { |
559fb51b SB |
1924 | if (alloc_rx_resources(sge, p)) |
1925 | return -ENOMEM; | |
1926 | if (alloc_tx_resources(sge, p)) { | |
1927 | free_rx_resources(sge); | |
1928 | return -ENOMEM; | |
1929 | } | |
1930 | configure_sge(sge, p); | |
1931 | ||
1932 | /* | |
1933 | * Now that we have sized the free lists calculate the payload | |
1934 | * capacity of the large buffers. Other parts of the driver use | |
1935 | * this to set the max offload coalescing size so that RX packets | |
1936 | * do not overflow our large buffers. | |
1937 | */ | |
1938 | p->large_buf_capacity = jumbo_payload_capacity(sge); | |
1939 | return 0; | |
1940 | } | |
8199d3a7 | 1941 | |
559fb51b SB |
1942 | /* |
1943 | * Disables the DMA engine. | |
1944 | */ | |
1945 | void t1_sge_stop(struct sge *sge) | |
1946 | { | |
f1d3d38a | 1947 | int i; |
559fb51b | 1948 | writel(0, sge->adapter->regs + A_SG_CONTROL); |
f1d3d38a SH |
1949 | readl(sge->adapter->regs + A_SG_CONTROL); /* flush */ |
1950 | ||
559fb51b SB |
1951 | if (is_T2(sge->adapter)) |
1952 | del_timer_sync(&sge->espibug_timer); | |
f1d3d38a | 1953 | |
559fb51b | 1954 | del_timer_sync(&sge->tx_reclaim_timer); |
f1d3d38a SH |
1955 | if (sge->tx_sched) |
1956 | tx_sched_stop(sge); | |
1957 | ||
1958 | for (i = 0; i < MAX_NPORTS; i++) | |
f4fe5a9c | 1959 | kfree_skb(sge->espibug_skb[i]); |
8199d3a7 CL |
1960 | } |
1961 | ||
559fb51b SB |
1962 | /* |
1963 | * Enables the DMA engine. | |
1964 | */ | |
1965 | void t1_sge_start(struct sge *sge) | |
8199d3a7 | 1966 | { |
559fb51b SB |
1967 | refill_free_list(sge, &sge->freelQ[0]); |
1968 | refill_free_list(sge, &sge->freelQ[1]); | |
1969 | ||
1970 | writel(sge->sge_control, sge->adapter->regs + A_SG_CONTROL); | |
1971 | doorbell_pio(sge->adapter, F_FL0_ENABLE | F_FL1_ENABLE); | |
f1d3d38a | 1972 | readl(sge->adapter->regs + A_SG_CONTROL); /* flush */ |
559fb51b SB |
1973 | |
1974 | mod_timer(&sge->tx_reclaim_timer, jiffies + TX_RECLAIM_PERIOD); | |
1975 | ||
f1d3d38a | 1976 | if (is_T2(sge->adapter)) |
559fb51b SB |
1977 | mod_timer(&sge->espibug_timer, jiffies + sge->espibug_timeout); |
1978 | } | |
1979 | ||
1980 | /* | |
1981 | * Callback for the T2 ESPI 'stuck packet feature' workaorund | |
1982 | */ | |
f1d3d38a | 1983 | static void espibug_workaround_t204(unsigned long data) |
559fb51b SB |
1984 | { |
1985 | struct adapter *adapter = (struct adapter *)data; | |
8199d3a7 | 1986 | struct sge *sge = adapter->sge; |
f1d3d38a SH |
1987 | unsigned int nports = adapter->params.nports; |
1988 | u32 seop[MAX_NPORTS]; | |
8199d3a7 | 1989 | |
f1d3d38a SH |
1990 | if (adapter->open_device_map & PORT_MASK) { |
1991 | int i; | |
356bd146 FR |
1992 | |
1993 | if (t1_espi_get_mon_t204(adapter, &(seop[0]), 0) < 0) | |
f1d3d38a | 1994 | return; |
356bd146 | 1995 | |
f1d3d38a | 1996 | for (i = 0; i < nports; i++) { |
356bd146 FR |
1997 | struct sk_buff *skb = sge->espibug_skb[i]; |
1998 | ||
1999 | if (!netif_running(adapter->port[i].dev) || | |
2000 | netif_queue_stopped(adapter->port[i].dev) || | |
2001 | !seop[i] || ((seop[i] & 0xfff) != 0) || !skb) | |
2002 | continue; | |
2003 | ||
2004 | if (!skb->cb[0]) { | |
27d7ff46 ACM |
2005 | skb_copy_to_linear_data_offset(skb, |
2006 | sizeof(struct cpl_tx_pkt), | |
2007 | ch_mac_addr, | |
2008 | ETH_ALEN); | |
2009 | skb_copy_to_linear_data_offset(skb, | |
2010 | skb->len - 10, | |
2011 | ch_mac_addr, | |
2012 | ETH_ALEN); | |
356bd146 | 2013 | skb->cb[0] = 0xff; |
559fb51b | 2014 | } |
356bd146 FR |
2015 | |
2016 | /* bump the reference count to avoid freeing of | |
2017 | * the skb once the DMA has completed. | |
2018 | */ | |
2019 | skb = skb_get(skb); | |
2020 | t1_sge_tx(skb, adapter, 0, adapter->port[i].dev); | |
559fb51b SB |
2021 | } |
2022 | } | |
2023 | mod_timer(&sge->espibug_timer, jiffies + sge->espibug_timeout); | |
8199d3a7 CL |
2024 | } |
2025 | ||
f1d3d38a SH |
2026 | static void espibug_workaround(unsigned long data) |
2027 | { | |
2028 | struct adapter *adapter = (struct adapter *)data; | |
2029 | struct sge *sge = adapter->sge; | |
2030 | ||
2031 | if (netif_running(adapter->port[0].dev)) { | |
2032 | struct sk_buff *skb = sge->espibug_skb[0]; | |
2033 | u32 seop = t1_espi_get_mon(adapter, 0x930, 0); | |
2034 | ||
2035 | if ((seop & 0xfff0fff) == 0xfff && skb) { | |
2036 | if (!skb->cb[0]) { | |
27d7ff46 ACM |
2037 | skb_copy_to_linear_data_offset(skb, |
2038 | sizeof(struct cpl_tx_pkt), | |
2039 | ch_mac_addr, | |
2040 | ETH_ALEN); | |
2041 | skb_copy_to_linear_data_offset(skb, | |
2042 | skb->len - 10, | |
2043 | ch_mac_addr, | |
2044 | ETH_ALEN); | |
f1d3d38a SH |
2045 | skb->cb[0] = 0xff; |
2046 | } | |
2047 | ||
2048 | /* bump the reference count to avoid freeing of the | |
2049 | * skb once the DMA has completed. | |
2050 | */ | |
2051 | skb = skb_get(skb); | |
2052 | t1_sge_tx(skb, adapter, 0, adapter->port[0].dev); | |
2053 | } | |
2054 | } | |
2055 | mod_timer(&sge->espibug_timer, jiffies + sge->espibug_timeout); | |
2056 | } | |
2057 | ||
559fb51b SB |
2058 | /* |
2059 | * Creates a t1_sge structure and returns suggested resource parameters. | |
2060 | */ | |
1dd06ae8 | 2061 | struct sge *t1_sge_create(struct adapter *adapter, struct sge_params *p) |
559fb51b | 2062 | { |
cbee9f91 | 2063 | struct sge *sge = kzalloc(sizeof(*sge), GFP_KERNEL); |
56f643c2 | 2064 | int i; |
559fb51b SB |
2065 | |
2066 | if (!sge) | |
2067 | return NULL; | |
559fb51b SB |
2068 | |
2069 | sge->adapter = adapter; | |
2070 | sge->netdev = adapter->port[0].dev; | |
2071 | sge->rx_pkt_pad = t1_is_T1B(adapter) ? 0 : 2; | |
2072 | sge->jumbo_fl = t1_is_T1B(adapter) ? 1 : 0; | |
2073 | ||
56f643c2 SH |
2074 | for_each_port(adapter, i) { |
2075 | sge->port_stats[i] = alloc_percpu(struct sge_port_stats); | |
2076 | if (!sge->port_stats[i]) | |
2077 | goto nomem_port; | |
2078 | } | |
2079 | ||
559fb51b SB |
2080 | init_timer(&sge->tx_reclaim_timer); |
2081 | sge->tx_reclaim_timer.data = (unsigned long)sge; | |
2082 | sge->tx_reclaim_timer.function = sge_tx_reclaim_cb; | |
2083 | ||
2084 | if (is_T2(sge->adapter)) { | |
2085 | init_timer(&sge->espibug_timer); | |
f1d3d38a SH |
2086 | |
2087 | if (adapter->params.nports > 1) { | |
2088 | tx_sched_init(sge); | |
2089 | sge->espibug_timer.function = espibug_workaround_t204; | |
d7487421 | 2090 | } else |
f1d3d38a | 2091 | sge->espibug_timer.function = espibug_workaround; |
559fb51b | 2092 | sge->espibug_timer.data = (unsigned long)sge->adapter; |
f1d3d38a | 2093 | |
559fb51b | 2094 | sge->espibug_timeout = 1; |
f1d3d38a SH |
2095 | /* for T204, every 10ms */ |
2096 | if (adapter->params.nports > 1) | |
2097 | sge->espibug_timeout = HZ/100; | |
559fb51b | 2098 | } |
356bd146 | 2099 | |
559fb51b SB |
2100 | |
2101 | p->cmdQ_size[0] = SGE_CMDQ0_E_N; | |
2102 | p->cmdQ_size[1] = SGE_CMDQ1_E_N; | |
2103 | p->freelQ_size[!sge->jumbo_fl] = SGE_FREEL_SIZE; | |
2104 | p->freelQ_size[sge->jumbo_fl] = SGE_JUMBO_FREEL_SIZE; | |
f1d3d38a SH |
2105 | if (sge->tx_sched) { |
2106 | if (board_info(sge->adapter)->board == CHBT_BOARD_CHT204) | |
2107 | p->rx_coalesce_usecs = 15; | |
2108 | else | |
2109 | p->rx_coalesce_usecs = 50; | |
2110 | } else | |
2111 | p->rx_coalesce_usecs = 50; | |
2112 | ||
559fb51b SB |
2113 | p->coalesce_enable = 0; |
2114 | p->sample_interval_usecs = 0; | |
559fb51b SB |
2115 | |
2116 | return sge; | |
56f643c2 SH |
2117 | nomem_port: |
2118 | while (i >= 0) { | |
2119 | free_percpu(sge->port_stats[i]); | |
2120 | --i; | |
2121 | } | |
2122 | kfree(sge); | |
2123 | return NULL; | |
2124 | ||
559fb51b | 2125 | } |