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cxgb4: Account for stid entries properly in case of IPv6
[deliverable/linux.git] / drivers / net / ethernet / chelsio / cxgb4 / cxgb4.h
CommitLineData
625ba2c2
DM		 1/*
2 * This file is part of the Chelsio T4 Ethernet driver for Linux.
3 *
4 * Copyright (c) 2003-2010 Chelsio Communications, Inc. All rights reserved.
5 *
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
11 *
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
14 * conditions are met:
15 *
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
18 * disclaimer.
19 *
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
24 *
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
32 * SOFTWARE.
33 */
34
35#ifndef __CXGB4_H__
36#define __CXGB4_H__
37
dca4faeb
VP		 38#include "t4_hw.h"
39
625ba2c2
DM		 40#include <linux/bitops.h>
41#include <linux/cache.h>
42#include <linux/interrupt.h>
43#include <linux/list.h>
44#include <linux/netdevice.h>
45#include <linux/pci.h>
46#include <linux/spinlock.h>
47#include <linux/timer.h>
c0b8b992 48#include <linux/vmalloc.h>
625ba2c2
DM		 49#include <asm/io.h>
50#include "cxgb4_uld.h"
625ba2c2 51
16e47624
HS		 52#define T4FW_VERSION_MAJOR 0x01
53#define T4FW_VERSION_MINOR 0x06
54#define T4FW_VERSION_MICRO 0x18
55#define T4FW_VERSION_BUILD 0x00
625ba2c2 56
16e47624
HS		 57#define T5FW_VERSION_MAJOR 0x01
58#define T5FW_VERSION_MINOR 0x08
59#define T5FW_VERSION_MICRO 0x1C
60#define T5FW_VERSION_BUILD 0x00
2422d9a3 61
3069ee9b
VP		 62#define CH_WARN(adap, fmt, ...) dev_warn(adap->pdev_dev, fmt, ## __VA_ARGS__)
63
625ba2c2
DM		 64enum {
65 MAX_NPORTS = 4, /* max # of ports */
47d54d65 66 SERNUM_LEN = 24, /* Serial # length */
625ba2c2
DM		 67 EC_LEN = 16, /* E/C length */
68 ID_LEN = 16, /* ID length */
69};
70
71enum {
72 MEM_EDC0,
73 MEM_EDC1,
2422d9a3
SR		 74 MEM_MC,
75 MEM_MC0 = MEM_MC,
76 MEM_MC1
625ba2c2
DM		 77};
78
3069ee9b 79enum {
3eb4afbf
VP		 80 MEMWIN0_APERTURE = 2048,
81 MEMWIN0_BASE = 0x1b800,
3069ee9b
VP		 82 MEMWIN1_APERTURE = 32768,
83 MEMWIN1_BASE = 0x28000,
2422d9a3 84 MEMWIN1_BASE_T5 = 0x52000,
3eb4afbf
VP		 85 MEMWIN2_APERTURE = 65536,
86 MEMWIN2_BASE = 0x30000,
2422d9a3 87 MEMWIN2_BASE_T5 = 0x54000,
3069ee9b
VP		 88};
89
625ba2c2
DM		 90enum dev_master {
91 MASTER_CANT,
92 MASTER_MAY,
93 MASTER_MUST
94};
95
96enum dev_state {
97 DEV_STATE_UNINIT,
98 DEV_STATE_INIT,
99 DEV_STATE_ERR
100};
101
102enum {
103 PAUSE_RX = 1 << 0,
104 PAUSE_TX = 1 << 1,
105 PAUSE_AUTONEG = 1 << 2
106};
107
108struct port_stats {
109 u64 tx_octets; /* total # of octets in good frames */
110 u64 tx_frames; /* all good frames */
111 u64 tx_bcast_frames; /* all broadcast frames */
112 u64 tx_mcast_frames; /* all multicast frames */
113 u64 tx_ucast_frames; /* all unicast frames */
114 u64 tx_error_frames; /* all error frames */
115
116 u64 tx_frames_64; /* # of Tx frames in a particular range */
117 u64 tx_frames_65_127;
118 u64 tx_frames_128_255;
119 u64 tx_frames_256_511;
120 u64 tx_frames_512_1023;
121 u64 tx_frames_1024_1518;
122 u64 tx_frames_1519_max;
123
124 u64 tx_drop; /* # of dropped Tx frames */
125 u64 tx_pause; /* # of transmitted pause frames */
126 u64 tx_ppp0; /* # of transmitted PPP prio 0 frames */
127 u64 tx_ppp1; /* # of transmitted PPP prio 1 frames */
128 u64 tx_ppp2; /* # of transmitted PPP prio 2 frames */
129 u64 tx_ppp3; /* # of transmitted PPP prio 3 frames */
130 u64 tx_ppp4; /* # of transmitted PPP prio 4 frames */
131 u64 tx_ppp5; /* # of transmitted PPP prio 5 frames */
132 u64 tx_ppp6; /* # of transmitted PPP prio 6 frames */
133 u64 tx_ppp7; /* # of transmitted PPP prio 7 frames */
134
135 u64 rx_octets; /* total # of octets in good frames */
136 u64 rx_frames; /* all good frames */
137 u64 rx_bcast_frames; /* all broadcast frames */
138 u64 rx_mcast_frames; /* all multicast frames */
139 u64 rx_ucast_frames; /* all unicast frames */
140 u64 rx_too_long; /* # of frames exceeding MTU */
141 u64 rx_jabber; /* # of jabber frames */
142 u64 rx_fcs_err; /* # of received frames with bad FCS */
143 u64 rx_len_err; /* # of received frames with length error */
144 u64 rx_symbol_err; /* symbol errors */
145 u64 rx_runt; /* # of short frames */
146
147 u64 rx_frames_64; /* # of Rx frames in a particular range */
148 u64 rx_frames_65_127;
149 u64 rx_frames_128_255;
150 u64 rx_frames_256_511;
151 u64 rx_frames_512_1023;
152 u64 rx_frames_1024_1518;
153 u64 rx_frames_1519_max;
154
155 u64 rx_pause; /* # of received pause frames */
156 u64 rx_ppp0; /* # of received PPP prio 0 frames */
157 u64 rx_ppp1; /* # of received PPP prio 1 frames */
158 u64 rx_ppp2; /* # of received PPP prio 2 frames */
159 u64 rx_ppp3; /* # of received PPP prio 3 frames */
160 u64 rx_ppp4; /* # of received PPP prio 4 frames */
161 u64 rx_ppp5; /* # of received PPP prio 5 frames */
162 u64 rx_ppp6; /* # of received PPP prio 6 frames */
163 u64 rx_ppp7; /* # of received PPP prio 7 frames */
164
165 u64 rx_ovflow0; /* drops due to buffer-group 0 overflows */
166 u64 rx_ovflow1; /* drops due to buffer-group 1 overflows */
167 u64 rx_ovflow2; /* drops due to buffer-group 2 overflows */
168 u64 rx_ovflow3; /* drops due to buffer-group 3 overflows */
169 u64 rx_trunc0; /* buffer-group 0 truncated packets */
170 u64 rx_trunc1; /* buffer-group 1 truncated packets */
171 u64 rx_trunc2; /* buffer-group 2 truncated packets */
172 u64 rx_trunc3; /* buffer-group 3 truncated packets */
173};
174
175struct lb_port_stats {
176 u64 octets;
177 u64 frames;
178 u64 bcast_frames;
179 u64 mcast_frames;
180 u64 ucast_frames;
181 u64 error_frames;
182
183 u64 frames_64;
184 u64 frames_65_127;
185 u64 frames_128_255;
186 u64 frames_256_511;
187 u64 frames_512_1023;
188 u64 frames_1024_1518;
189 u64 frames_1519_max;
190
191 u64 drop;
192
193 u64 ovflow0;
194 u64 ovflow1;
195 u64 ovflow2;
196 u64 ovflow3;
197 u64 trunc0;
198 u64 trunc1;
199 u64 trunc2;
200 u64 trunc3;
201};
202
203struct tp_tcp_stats {
204 u32 tcpOutRsts;
205 u64 tcpInSegs;
206 u64 tcpOutSegs;
207 u64 tcpRetransSegs;
208};
209
210struct tp_err_stats {
211 u32 macInErrs[4];
212 u32 hdrInErrs[4];
213 u32 tcpInErrs[4];
214 u32 tnlCongDrops[4];
215 u32 ofldChanDrops[4];
216 u32 tnlTxDrops[4];
217 u32 ofldVlanDrops[4];
218 u32 tcp6InErrs[4];
219 u32 ofldNoNeigh;
220 u32 ofldCongDefer;
221};
222
223struct tp_params {
224 unsigned int ntxchan; /* # of Tx channels */
225 unsigned int tre; /* log2 of core clocks per TP tick */
dca4faeb
VP		 226 unsigned short tx_modq_map; /* TX modulation scheduler queue to */
227 /* channel map */
636f9d37
VP		 228
229 uint32_t dack_re; /* DACK timer resolution */
230 unsigned short tx_modq[NCHAN]; /* channel to modulation queue map */
625ba2c2
DM		 231};
232
233struct vpd_params {
234 unsigned int cclk;
235 u8 ec[EC_LEN + 1];
236 u8 sn[SERNUM_LEN + 1];
237 u8 id[ID_LEN + 1];
238};
239
240struct pci_params {
241 unsigned char speed;
242 unsigned char width;
243};
244
d14807dd
HS		 245#define CHELSIO_CHIP_CODE(version, revision) (((version) << 4) | (revision))
246#define CHELSIO_CHIP_FPGA 0x100
247#define CHELSIO_CHIP_VERSION(code) (((code) >> 4) & 0xf)
248#define CHELSIO_CHIP_RELEASE(code) ((code) & 0xf)
249
250#define CHELSIO_T4 0x4
251#define CHELSIO_T5 0x5
252
253enum chip_type {
254 T4_A1 = CHELSIO_CHIP_CODE(CHELSIO_T4, 1),
255 T4_A2 = CHELSIO_CHIP_CODE(CHELSIO_T4, 2),
256 T4_FIRST_REV = T4_A1,
257 T4_LAST_REV = T4_A2,
258
259 T5_A0 = CHELSIO_CHIP_CODE(CHELSIO_T5, 0),
260 T5_A1 = CHELSIO_CHIP_CODE(CHELSIO_T5, 1),
261 T5_FIRST_REV = T5_A0,
262 T5_LAST_REV = T5_A1,
263};
264
625ba2c2
DM		 265struct adapter_params {
266 struct tp_params tp;
267 struct vpd_params vpd;
268 struct pci_params pci;
269
900a6596
DM		 270 unsigned int sf_size; /* serial flash size in bytes */
271 unsigned int sf_nsec; /* # of flash sectors */
272 unsigned int sf_fw_start; /* start of FW image in flash */
273
625ba2c2
DM		 274 unsigned int fw_vers;
275 unsigned int tp_vers;
276 u8 api_vers[7];
277
278 unsigned short mtus[NMTUS];
279 unsigned short a_wnd[NCCTRL_WIN];
280 unsigned short b_wnd[NCCTRL_WIN];
281
282 unsigned char nports; /* # of ethernet ports */
283 unsigned char portvec;
d14807dd 284 enum chip_type chip; /* chip code */
625ba2c2
DM		 285 unsigned char offload;
286
9a4da2cd
VP		 287 unsigned char bypass;
288
625ba2c2
DM		 289 unsigned int ofldq_wr_cred;
290};
291
16e47624
HS		 292#include "t4fw_api.h"
293
294#define FW_VERSION(chip) ( \
295 FW_HDR_FW_VER_MAJOR_GET(chip##FW_VERSION_MAJOR) | \
296 FW_HDR_FW_VER_MINOR_GET(chip##FW_VERSION_MINOR) | \
297 FW_HDR_FW_VER_MICRO_GET(chip##FW_VERSION_MICRO) | \
298 FW_HDR_FW_VER_BUILD_GET(chip##FW_VERSION_BUILD))
299#define FW_INTFVER(chip, intf) (FW_HDR_INTFVER_##intf)
300
301struct fw_info {
302 u8 chip;
303 char *fs_name;
304 char *fw_mod_name;
305 struct fw_hdr fw_hdr;
306};
307
308
625ba2c2
DM		 309struct trace_params {
310 u32 data[TRACE_LEN / 4];
311 u32 mask[TRACE_LEN / 4];
312 unsigned short snap_len;
313 unsigned short min_len;
314 unsigned char skip_ofst;
315 unsigned char skip_len;
316 unsigned char invert;
317 unsigned char port;
318};
319
320struct link_config {
321 unsigned short supported; /* link capabilities */
322 unsigned short advertising; /* advertised capabilities */
323 unsigned short requested_speed; /* speed user has requested */
324 unsigned short speed; /* actual link speed */
325 unsigned char requested_fc; /* flow control user has requested */
326 unsigned char fc; /* actual link flow control */
327 unsigned char autoneg; /* autonegotiating? */
328 unsigned char link_ok; /* link up? */
329};
330
331#define FW_LEN16(fw_struct) FW_CMD_LEN16(sizeof(fw_struct) / 16)
332
333enum {
334 MAX_ETH_QSETS = 32, /* # of Ethernet Tx/Rx queue sets */
335 MAX_OFLD_QSETS = 16, /* # of offload Tx/Rx queue sets */
336 MAX_CTRL_QUEUES = NCHAN, /* # of control Tx queues */
337 MAX_RDMA_QUEUES = NCHAN, /* # of streaming RDMA Rx queues */
338};
339
340enum {
341 MAX_EGRQ = 128, /* max # of egress queues, including FLs */
342 MAX_INGQ = 64 /* max # of interrupt-capable ingress queues */
343};
344
345struct adapter;
625ba2c2
DM		 346struct sge_rspq;
347
348struct port_info {
349 struct adapter *adapter;
625ba2c2
DM		 350 u16 viid;
351 s16 xact_addr_filt; /* index of exact MAC address filter */
352 u16 rss_size; /* size of VI's RSS table slice */
353 s8 mdio_addr;
354 u8 port_type;
355 u8 mod_type;
356 u8 port_id;
357 u8 tx_chan;
358 u8 lport; /* associated offload logical port */
625ba2c2
DM		 359 u8 nqsets; /* # of qsets */
360 u8 first_qset; /* index of first qset */
f796564a 361 u8 rss_mode;
625ba2c2 362 struct link_config link_cfg;
671b0060 363 u16 *rss;
625ba2c2
DM		 364};
365
625ba2c2
DM		 366struct dentry;
367struct work_struct;
368
369enum { /* adapter flags */
370 FULL_INIT_DONE = (1 << 0),
371 USING_MSI = (1 << 1),
372 USING_MSIX = (1 << 2),
625ba2c2 373 FW_OK = (1 << 4),
13ee15d3 374 RSS_TNLALLLOOKUP = (1 << 5),
52367a76
VP		 375 USING_SOFT_PARAMS = (1 << 6),
376 MASTER_PF = (1 << 7),
377 FW_OFLD_CONN = (1 << 9),
625ba2c2
DM		 378};
379
380struct rx_sw_desc;
381
382struct sge_fl { /* SGE free-buffer queue state */
383 unsigned int avail; /* # of available Rx buffers */
384 unsigned int pend_cred; /* new buffers since last FL DB ring */
385 unsigned int cidx; /* consumer index */
386 unsigned int pidx; /* producer index */
387 unsigned long alloc_failed; /* # of times buffer allocation failed */
388 unsigned long large_alloc_failed;
389 unsigned long starving;
390 /* RO fields */
391 unsigned int cntxt_id; /* SGE context id for the free list */
392 unsigned int size; /* capacity of free list */
393 struct rx_sw_desc *sdesc; /* address of SW Rx descriptor ring */
394 __be64 *desc; /* address of HW Rx descriptor ring */
395 dma_addr_t addr; /* bus address of HW ring start */
396};
397
398/* A packet gather list */
399struct pkt_gl {
e91b0f24 400 struct page_frag frags[MAX_SKB_FRAGS];
625ba2c2
DM		 401 void *va; /* virtual address of first byte */
402 unsigned int nfrags; /* # of fragments */
403 unsigned int tot_len; /* total length of fragments */
404};
405
406typedef int (*rspq_handler_t)(struct sge_rspq *q, const __be64 *rsp,
407 const struct pkt_gl *gl);
408
409struct sge_rspq { /* state for an SGE response queue */
410 struct napi_struct napi;
411 const __be64 *cur_desc; /* current descriptor in queue */
412 unsigned int cidx; /* consumer index */
413 u8 gen; /* current generation bit */
414 u8 intr_params; /* interrupt holdoff parameters */
415 u8 next_intr_params; /* holdoff params for next interrupt */
416 u8 pktcnt_idx; /* interrupt packet threshold */
417 u8 uld; /* ULD handling this queue */
418 u8 idx; /* queue index within its group */
419 int offset; /* offset into current Rx buffer */
420 u16 cntxt_id; /* SGE context id for the response q */
421 u16 abs_id; /* absolute SGE id for the response q */
422 __be64 *desc; /* address of HW response ring */
423 dma_addr_t phys_addr; /* physical address of the ring */
424 unsigned int iqe_len; /* entry size */
425 unsigned int size; /* capacity of response queue */
426 struct adapter *adap;
427 struct net_device *netdev; /* associated net device */
428 rspq_handler_t handler;
429};
430
431struct sge_eth_stats { /* Ethernet queue statistics */
432 unsigned long pkts; /* # of ethernet packets */
433 unsigned long lro_pkts; /* # of LRO super packets */
434 unsigned long lro_merged; /* # of wire packets merged by LRO */
435 unsigned long rx_cso; /* # of Rx checksum offloads */
436 unsigned long vlan_ex; /* # of Rx VLAN extractions */
437 unsigned long rx_drops; /* # of packets dropped due to no mem */
438};
439
440struct sge_eth_rxq { /* SW Ethernet Rx queue */
441 struct sge_rspq rspq;
442 struct sge_fl fl;
443 struct sge_eth_stats stats;
444} ____cacheline_aligned_in_smp;
445
446struct sge_ofld_stats { /* offload queue statistics */
447 unsigned long pkts; /* # of packets */
448 unsigned long imm; /* # of immediate-data packets */
449 unsigned long an; /* # of asynchronous notifications */
450 unsigned long nomem; /* # of responses deferred due to no mem */
451};
452
453struct sge_ofld_rxq { /* SW offload Rx queue */
454 struct sge_rspq rspq;
455 struct sge_fl fl;
456 struct sge_ofld_stats stats;
457} ____cacheline_aligned_in_smp;
458
459struct tx_desc {
460 __be64 flit[8];
461};
462
463struct tx_sw_desc;
464
465struct sge_txq {
466 unsigned int in_use; /* # of in-use Tx descriptors */
467 unsigned int size; /* # of descriptors */
468 unsigned int cidx; /* SW consumer index */
469 unsigned int pidx; /* producer index */
470 unsigned long stops; /* # of times q has been stopped */
471 unsigned long restarts; /* # of queue restarts */
472 unsigned int cntxt_id; /* SGE context id for the Tx q */
473 struct tx_desc *desc; /* address of HW Tx descriptor ring */
474 struct tx_sw_desc *sdesc; /* address of SW Tx descriptor ring */
475 struct sge_qstat *stat; /* queue status entry */
476 dma_addr_t phys_addr; /* physical address of the ring */
3069ee9b
VP		 477 spinlock_t db_lock;
478 int db_disabled;
479 unsigned short db_pidx;
22adfe0a 480 u64 udb;
625ba2c2
DM		 481};
482
483struct sge_eth_txq { /* state for an SGE Ethernet Tx queue */
484 struct sge_txq q;
485 struct netdev_queue *txq; /* associated netdev TX queue */
486 unsigned long tso; /* # of TSO requests */
487 unsigned long tx_cso; /* # of Tx checksum offloads */
488 unsigned long vlan_ins; /* # of Tx VLAN insertions */
489 unsigned long mapping_err; /* # of I/O MMU packet mapping errors */
490} ____cacheline_aligned_in_smp;
491
492struct sge_ofld_txq { /* state for an SGE offload Tx queue */
493 struct sge_txq q;
494 struct adapter *adap;
495 struct sk_buff_head sendq; /* list of backpressured packets */
496 struct tasklet_struct qresume_tsk; /* restarts the queue */
497 u8 full; /* the Tx ring is full */
498 unsigned long mapping_err; /* # of I/O MMU packet mapping errors */
499} ____cacheline_aligned_in_smp;
500
501struct sge_ctrl_txq { /* state for an SGE control Tx queue */
502 struct sge_txq q;
503 struct adapter *adap;
504 struct sk_buff_head sendq; /* list of backpressured packets */
505 struct tasklet_struct qresume_tsk; /* restarts the queue */
506 u8 full; /* the Tx ring is full */
507} ____cacheline_aligned_in_smp;
508
509struct sge {
510 struct sge_eth_txq ethtxq[MAX_ETH_QSETS];
511 struct sge_ofld_txq ofldtxq[MAX_OFLD_QSETS];
512 struct sge_ctrl_txq ctrlq[MAX_CTRL_QUEUES];
513
514 struct sge_eth_rxq ethrxq[MAX_ETH_QSETS];
515 struct sge_ofld_rxq ofldrxq[MAX_OFLD_QSETS];
516 struct sge_ofld_rxq rdmarxq[MAX_RDMA_QUEUES];
517 struct sge_rspq fw_evtq ____cacheline_aligned_in_smp;
518
519 struct sge_rspq intrq ____cacheline_aligned_in_smp;
520 spinlock_t intrq_lock;
521
522 u16 max_ethqsets; /* # of available Ethernet queue sets */
523 u16 ethqsets; /* # of active Ethernet queue sets */
524 u16 ethtxq_rover; /* Tx queue to clean up next */
525 u16 ofldqsets; /* # of active offload queue sets */
526 u16 rdmaqs; /* # of available RDMA Rx queues */
527 u16 ofld_rxq[MAX_OFLD_QSETS];
528 u16 rdma_rxq[NCHAN];
529 u16 timer_val[SGE_NTIMERS];
530 u8 counter_val[SGE_NCOUNTERS];
52367a76
VP		 531 u32 fl_pg_order; /* large page allocation size */
532 u32 stat_len; /* length of status page at ring end */
533 u32 pktshift; /* padding between CPL & packet data */
534 u32 fl_align; /* response queue message alignment */
535 u32 fl_starve_thres; /* Free List starvation threshold */
625ba2c2
DM		 536 unsigned int starve_thres;
537 u8 idma_state[2];
e46dab4d
DM		 538 unsigned int egr_start;
539 unsigned int ingr_start;
625ba2c2
DM		 540 void *egr_map[MAX_EGRQ]; /* qid->queue egress queue map */
541 struct sge_rspq *ingr_map[MAX_INGQ]; /* qid->queue ingress queue map */
542 DECLARE_BITMAP(starving_fl, MAX_EGRQ);
543 DECLARE_BITMAP(txq_maperr, MAX_EGRQ);
544 struct timer_list rx_timer; /* refills starving FLs */
545 struct timer_list tx_timer; /* checks Tx queues */
546};
547
548#define for_each_ethrxq(sge, i) for (i = 0; i < (sge)->ethqsets; i++)
549#define for_each_ofldrxq(sge, i) for (i = 0; i < (sge)->ofldqsets; i++)
550#define for_each_rdmarxq(sge, i) for (i = 0; i < (sge)->rdmaqs; i++)
551
552struct l2t_data;
553
2422d9a3
SR		 554#ifdef CONFIG_PCI_IOV
555
7d6727cf
SR		 556/* T4 supports SRIOV on PF0-3 and T5 on PF0-7. However, the Serial
557 * Configuration initialization for T5 only has SR-IOV functionality enabled
558 * on PF0-3 in order to simplify everything.
2422d9a3 559 */
7d6727cf 560#define NUM_OF_PF_WITH_SRIOV 4
2422d9a3
SR		 561
562#endif
563
625ba2c2
DM		 564struct adapter {
565 void __iomem *regs;
22adfe0a 566 void __iomem *bar2;
625ba2c2
DM		 567 struct pci_dev *pdev;
568 struct device *pdev_dev;
3069ee9b 569 unsigned int mbox;
060e0c75
DM		 570 unsigned int fn;
571 unsigned int flags;
2422d9a3 572 enum chip_type chip;
625ba2c2 573
625ba2c2
DM		 574 int msg_enable;
575
576 struct adapter_params params;
577 struct cxgb4_virt_res vres;
578 unsigned int swintr;
579
580 unsigned int wol;
581
582 struct {
583 unsigned short vec;
8cd18ac4 584 char desc[IFNAMSIZ + 10];
625ba2c2
DM		 585 } msix_info[MAX_INGQ + 1];
586
587 struct sge sge;
588
589 struct net_device *port[MAX_NPORTS];
590 u8 chan_map[NCHAN]; /* channel -> port map */
591
793dad94 592 u32 filter_mode;
636f9d37
VP		 593 unsigned int l2t_start;
594 unsigned int l2t_end;
625ba2c2
DM		 595 struct l2t_data *l2t;
596 void *uld_handle[CXGB4_ULD_MAX];
597 struct list_head list_node;
01bcca68 598 struct list_head rcu_node;
625ba2c2
DM		 599
600 struct tid_info tids;
601 void **tid_release_head;
602 spinlock_t tid_release_lock;
603 struct work_struct tid_release_task;
881806bc
VP		 604 struct work_struct db_full_task;
605 struct work_struct db_drop_task;
625ba2c2
DM		 606 bool tid_release_task_busy;
607
608 struct dentry *debugfs_root;
609
610 spinlock_t stats_lock;
611};
612
f2b7e78d
VP		 613/* Defined bit width of user definable filter tuples
614 */
615#define ETHTYPE_BITWIDTH 16
616#define FRAG_BITWIDTH 1
617#define MACIDX_BITWIDTH 9
618#define FCOE_BITWIDTH 1
619#define IPORT_BITWIDTH 3
620#define MATCHTYPE_BITWIDTH 3
621#define PROTO_BITWIDTH 8
622#define TOS_BITWIDTH 8
623#define PF_BITWIDTH 8
624#define VF_BITWIDTH 8
625#define IVLAN_BITWIDTH 16
626#define OVLAN_BITWIDTH 16
627
628/* Filter matching rules. These consist of a set of ingress packet field
629 * (value, mask) tuples. The associated ingress packet field matches the
630 * tuple when ((field & mask) == value). (Thus a wildcard "don't care" field
631 * rule can be constructed by specifying a tuple of (0, 0).) A filter rule
632 * matches an ingress packet when all of the individual individual field
633 * matching rules are true.
634 *
635 * Partial field masks are always valid, however, while it may be easy to
636 * understand their meanings for some fields (e.g. IP address to match a
637 * subnet), for others making sensible partial masks is less intuitive (e.g.
638 * MPS match type) ...
639 *
640 * Most of the following data structures are modeled on T4 capabilities.
641 * Drivers for earlier chips use the subsets which make sense for those chips.
642 * We really need to come up with a hardware-independent mechanism to
643 * represent hardware filter capabilities ...
644 */
645struct ch_filter_tuple {
646 /* Compressed header matching field rules. The TP_VLAN_PRI_MAP
647 * register selects which of these fields will participate in the
648 * filter match rules -- up to a maximum of 36 bits. Because
649 * TP_VLAN_PRI_MAP is a global register, all filters must use the same
650 * set of fields.
651 */
652 uint32_t ethtype:ETHTYPE_BITWIDTH; /* Ethernet type */
653 uint32_t frag:FRAG_BITWIDTH; /* IP fragmentation header */
654 uint32_t ivlan_vld:1; /* inner VLAN valid */
655 uint32_t ovlan_vld:1; /* outer VLAN valid */
656 uint32_t pfvf_vld:1; /* PF/VF valid */
657 uint32_t macidx:MACIDX_BITWIDTH; /* exact match MAC index */
658 uint32_t fcoe:FCOE_BITWIDTH; /* FCoE packet */
659 uint32_t iport:IPORT_BITWIDTH; /* ingress port */
660 uint32_t matchtype:MATCHTYPE_BITWIDTH; /* MPS match type */
661 uint32_t proto:PROTO_BITWIDTH; /* protocol type */
662 uint32_t tos:TOS_BITWIDTH; /* TOS/Traffic Type */
663 uint32_t pf:PF_BITWIDTH; /* PCI-E PF ID */
664 uint32_t vf:VF_BITWIDTH; /* PCI-E VF ID */
665 uint32_t ivlan:IVLAN_BITWIDTH; /* inner VLAN */
666 uint32_t ovlan:OVLAN_BITWIDTH; /* outer VLAN */
667
668 /* Uncompressed header matching field rules. These are always
669 * available for field rules.
670 */
671 uint8_t lip[16]; /* local IP address (IPv4 in [3:0]) */
672 uint8_t fip[16]; /* foreign IP address (IPv4 in [3:0]) */
673 uint16_t lport; /* local port */
674 uint16_t fport; /* foreign port */
675};
676
677/* A filter ioctl command.
678 */
679struct ch_filter_specification {
680 /* Administrative fields for filter.
681 */
682 uint32_t hitcnts:1; /* count filter hits in TCB */
683 uint32_t prio:1; /* filter has priority over active/server */
684
685 /* Fundamental filter typing. This is the one element of filter
686 * matching that doesn't exist as a (value, mask) tuple.
687 */
688 uint32_t type:1; /* 0 => IPv4, 1 => IPv6 */
689
690 /* Packet dispatch information. Ingress packets which match the
691 * filter rules will be dropped, passed to the host or switched back
692 * out as egress packets.
693 */
694 uint32_t action:2; /* drop, pass, switch */
695
696 uint32_t rpttid:1; /* report TID in RSS hash field */
697
698 uint32_t dirsteer:1; /* 0 => RSS, 1 => steer to iq */
699 uint32_t iq:10; /* ingress queue */
700
701 uint32_t maskhash:1; /* dirsteer=0: store RSS hash in TCB */
702 uint32_t dirsteerhash:1;/* dirsteer=1: 0 => TCB contains RSS hash */
703 /* 1 => TCB contains IQ ID */
704
705 /* Switch proxy/rewrite fields. An ingress packet which matches a
706 * filter with "switch" set will be looped back out as an egress
707 * packet -- potentially with some Ethernet header rewriting.
708 */
709 uint32_t eport:2; /* egress port to switch packet out */
710 uint32_t newdmac:1; /* rewrite destination MAC address */
711 uint32_t newsmac:1; /* rewrite source MAC address */
712 uint32_t newvlan:2; /* rewrite VLAN Tag */
713 uint8_t dmac[ETH_ALEN]; /* new destination MAC address */
714 uint8_t smac[ETH_ALEN]; /* new source MAC address */
715 uint16_t vlan; /* VLAN Tag to insert */
716
717 /* Filter rule value/mask pairs.
718 */
719 struct ch_filter_tuple val;
720 struct ch_filter_tuple mask;
721};
722
723enum {
724 FILTER_PASS = 0, /* default */
725 FILTER_DROP,
726 FILTER_SWITCH
727};
728
729enum {
730 VLAN_NOCHANGE = 0, /* default */
731 VLAN_REMOVE,
732 VLAN_INSERT,
733 VLAN_REWRITE
734};
735
2422d9a3
SR		 736static inline int is_t5(enum chip_type chip)
737{
d14807dd 738 return CHELSIO_CHIP_VERSION(chip) == CHELSIO_T5;
2422d9a3
SR		 739}
740
741static inline int is_t4(enum chip_type chip)
742{
d14807dd 743 return CHELSIO_CHIP_VERSION(chip) == CHELSIO_T4;
2422d9a3
SR		 744}
745
625ba2c2
DM		 746static inline u32 t4_read_reg(struct adapter *adap, u32 reg_addr)
747{
748 return readl(adap->regs + reg_addr);
749}
750
751static inline void t4_write_reg(struct adapter *adap, u32 reg_addr, u32 val)
752{
753 writel(val, adap->regs + reg_addr);
754}
755
756#ifndef readq
757static inline u64 readq(const volatile void __iomem *addr)
758{
759 return readl(addr) + ((u64)readl(addr + 4) << 32);
760}
761
762static inline void writeq(u64 val, volatile void __iomem *addr)
763{
764 writel(val, addr);
765 writel(val >> 32, addr + 4);
766}
767#endif
768
769static inline u64 t4_read_reg64(struct adapter *adap, u32 reg_addr)
770{
771 return readq(adap->regs + reg_addr);
772}
773
774static inline void t4_write_reg64(struct adapter *adap, u32 reg_addr, u64 val)
775{
776 writeq(val, adap->regs + reg_addr);
777}
778
779/**
780 * netdev2pinfo - return the port_info structure associated with a net_device
781 * @dev: the netdev
782 *
783 * Return the struct port_info associated with a net_device
784 */
785static inline struct port_info *netdev2pinfo(const struct net_device *dev)
786{
787 return netdev_priv(dev);
788}
789
790/**
791 * adap2pinfo - return the port_info of a port
792 * @adap: the adapter
793 * @idx: the port index
794 *
795 * Return the port_info structure for the port of the given index.
796 */
797static inline struct port_info *adap2pinfo(struct adapter *adap, int idx)
798{
799 return netdev_priv(adap->port[idx]);
800}
801
802/**
803 * netdev2adap - return the adapter structure associated with a net_device
804 * @dev: the netdev
805 *
806 * Return the struct adapter associated with a net_device
807 */
808static inline struct adapter *netdev2adap(const struct net_device *dev)
809{
810 return netdev2pinfo(dev)->adapter;
811}
812
813void t4_os_portmod_changed(const struct adapter *adap, int port_id);
814void t4_os_link_changed(struct adapter *adap, int port_id, int link_stat);
815
816void *t4_alloc_mem(size_t size);
625ba2c2
DM		 817
818void t4_free_sge_resources(struct adapter *adap);
819irq_handler_t t4_intr_handler(struct adapter *adap);
820netdev_tx_t t4_eth_xmit(struct sk_buff *skb, struct net_device *dev);
821int t4_ethrx_handler(struct sge_rspq *q, const __be64 *rsp,
822 const struct pkt_gl *gl);
823int t4_mgmt_tx(struct adapter *adap, struct sk_buff *skb);
824int t4_ofld_send(struct adapter *adap, struct sk_buff *skb);
825int t4_sge_alloc_rxq(struct adapter *adap, struct sge_rspq *iq, bool fwevtq,
826 struct net_device *dev, int intr_idx,
827 struct sge_fl *fl, rspq_handler_t hnd);
828int t4_sge_alloc_eth_txq(struct adapter *adap, struct sge_eth_txq *txq,
829 struct net_device *dev, struct netdev_queue *netdevq,
830 unsigned int iqid);
831int t4_sge_alloc_ctrl_txq(struct adapter *adap, struct sge_ctrl_txq *txq,
832 struct net_device *dev, unsigned int iqid,
833 unsigned int cmplqid);
834int t4_sge_alloc_ofld_txq(struct adapter *adap, struct sge_ofld_txq *txq,
835 struct net_device *dev, unsigned int iqid);
836irqreturn_t t4_sge_intr_msix(int irq, void *cookie);
52367a76 837int t4_sge_init(struct adapter *adap);
625ba2c2
DM		 838void t4_sge_start(struct adapter *adap);
839void t4_sge_stop(struct adapter *adap);
3069ee9b 840extern int dbfifo_int_thresh;
625ba2c2
DM		 841
842#define for_each_port(adapter, iter) \
843 for (iter = 0; iter < (adapter)->params.nports; ++iter)
844
9a4da2cd
VP		 845static inline int is_bypass(struct adapter *adap)
846{
847 return adap->params.bypass;
848}
849
850static inline int is_bypass_device(int device)
851{
852 /* this should be set based upon device capabilities */
853 switch (device) {
854 case 0x440b:
855 case 0x440c:
856 return 1;
857 default:
858 return 0;
859 }
860}
861
625ba2c2
DM		 862static inline unsigned int core_ticks_per_usec(const struct adapter *adap)
863{
864 return adap->params.vpd.cclk / 1000;
865}
866
867static inline unsigned int us_to_core_ticks(const struct adapter *adap,
868 unsigned int us)
869{
870 return (us * adap->params.vpd.cclk) / 1000;
871}
872
52367a76
VP		 873static inline unsigned int core_ticks_to_us(const struct adapter *adapter,
874 unsigned int ticks)
875{
876 /* add Core Clock / 2 to round ticks to nearest uS */
877 return ((ticks * 1000 + adapter->params.vpd.cclk/2) /
878 adapter->params.vpd.cclk);
879}
880
625ba2c2
DM		 881void t4_set_reg_field(struct adapter *adap, unsigned int addr, u32 mask,
882 u32 val);
883
884int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size,
885 void *rpl, bool sleep_ok);
886
887static inline int t4_wr_mbox(struct adapter *adap, int mbox, const void *cmd,
888 int size, void *rpl)
889{
890 return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, true);
891}
892
893static inline int t4_wr_mbox_ns(struct adapter *adap, int mbox, const void *cmd,
894 int size, void *rpl)
895{
896 return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, false);
897}
898
13ee15d3
VP		 899void t4_write_indirect(struct adapter *adap, unsigned int addr_reg,
900 unsigned int data_reg, const u32 *vals,
901 unsigned int nregs, unsigned int start_idx);
f2b7e78d
VP		 902void t4_read_indirect(struct adapter *adap, unsigned int addr_reg,
903 unsigned int data_reg, u32 *vals, unsigned int nregs,
904 unsigned int start_idx);
905
906struct fw_filter_wr;
907
625ba2c2
DM		 908void t4_intr_enable(struct adapter *adapter);
909void t4_intr_disable(struct adapter *adapter);
625ba2c2
DM		 910int t4_slow_intr_handler(struct adapter *adapter);
911
204dc3c0 912int t4_wait_dev_ready(struct adapter *adap);
625ba2c2
DM		 913int t4_link_start(struct adapter *adap, unsigned int mbox, unsigned int port,
914 struct link_config *lc);
915int t4_restart_aneg(struct adapter *adap, unsigned int mbox, unsigned int port);
5afc8b84
VP		 916int t4_memory_write(struct adapter *adap, int mtype, u32 addr, u32 len,
917 __be32 *buf);
625ba2c2 918int t4_seeprom_wp(struct adapter *adapter, bool enable);
636f9d37 919int get_vpd_params(struct adapter *adapter, struct vpd_params *p);
625ba2c2 920int t4_load_fw(struct adapter *adapter, const u8 *fw_data, unsigned int size);
636f9d37 921unsigned int t4_flash_cfg_addr(struct adapter *adapter);
404d9e3f 922int t4_load_cfg(struct adapter *adapter, const u8 *cfg_data, unsigned int size);
16e47624
HS		 923int t4_get_fw_version(struct adapter *adapter, u32 *vers);
924int t4_get_tp_version(struct adapter *adapter, u32 *vers);
925int t4_prep_fw(struct adapter *adap, struct fw_info *fw_info,
926 const u8 *fw_data, unsigned int fw_size,
927 struct fw_hdr *card_fw, enum dev_state state, int *reset);
625ba2c2
DM		 928int t4_prep_adapter(struct adapter *adapter);
929int t4_port_init(struct adapter *adap, int mbox, int pf, int vf);
930void t4_fatal_err(struct adapter *adapter);
625ba2c2
DM		 931int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid,
932 int start, int n, const u16 *rspq, unsigned int nrspq);
933int t4_config_glbl_rss(struct adapter *adapter, int mbox, unsigned int mode,
934 unsigned int flags);
19dd37ba
SR		 935int t4_mc_read(struct adapter *adap, int idx, u32 addr, __be32 *data,
936 u64 *parity);
625ba2c2
DM		 937int t4_edc_read(struct adapter *adap, int idx, u32 addr, __be32 *data,
938 u64 *parity);
939
940void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p);
625ba2c2 941void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log);
636f9d37
VP		 942void t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr,
943 unsigned int mask, unsigned int val);
625ba2c2
DM		 944void t4_tp_get_tcp_stats(struct adapter *adap, struct tp_tcp_stats *v4,
945 struct tp_tcp_stats *v6);
946void t4_load_mtus(struct adapter *adap, const unsigned short *mtus,
947 const unsigned short *alpha, const unsigned short *beta);
948
f2b7e78d
VP		 949void t4_mk_filtdelwr(unsigned int ftid, struct fw_filter_wr *wr, int qid);
950
625ba2c2
DM		 951void t4_wol_magic_enable(struct adapter *adap, unsigned int port,
952 const u8 *addr);
953int t4_wol_pat_enable(struct adapter *adap, unsigned int port, unsigned int map,
954 u64 mask0, u64 mask1, unsigned int crc, bool enable);
955
956int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox,
957 enum dev_master master, enum dev_state *state);
958int t4_fw_bye(struct adapter *adap, unsigned int mbox);
959int t4_early_init(struct adapter *adap, unsigned int mbox);
960int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset);
26f7cbc0
VP		 961int t4_fw_halt(struct adapter *adap, unsigned int mbox, int force);
962int t4_fw_restart(struct adapter *adap, unsigned int mbox, int reset);
963int t4_fw_upgrade(struct adapter *adap, unsigned int mbox,
964 const u8 *fw_data, unsigned int size, int force);
636f9d37
VP		 965int t4_fw_config_file(struct adapter *adap, unsigned int mbox,
966 unsigned int mtype, unsigned int maddr,
967 u32 *finiver, u32 *finicsum, u32 *cfcsum);
968int t4_fixup_host_params(struct adapter *adap, unsigned int page_size,
969 unsigned int cache_line_size);
970int t4_fw_initialize(struct adapter *adap, unsigned int mbox);
625ba2c2
DM		 971int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
972 unsigned int vf, unsigned int nparams, const u32 *params,
973 u32 *val);
974int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
975 unsigned int vf, unsigned int nparams, const u32 *params,
976 const u32 *val);
977int t4_cfg_pfvf(struct adapter *adap, unsigned int mbox, unsigned int pf,
978 unsigned int vf, unsigned int txq, unsigned int txq_eth_ctrl,
979 unsigned int rxqi, unsigned int rxq, unsigned int tc,
980 unsigned int vi, unsigned int cmask, unsigned int pmask,
981 unsigned int nexact, unsigned int rcaps, unsigned int wxcaps);
982int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port,
983 unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac,
984 unsigned int *rss_size);
625ba2c2 985int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid,
f8f5aafa
DM		 986 int mtu, int promisc, int all_multi, int bcast, int vlanex,
987 bool sleep_ok);
625ba2c2
DM		 988int t4_alloc_mac_filt(struct adapter *adap, unsigned int mbox,
989 unsigned int viid, bool free, unsigned int naddr,
990 const u8 **addr, u16 *idx, u64 *hash, bool sleep_ok);
991int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid,
992 int idx, const u8 *addr, bool persist, bool add_smt);
993int t4_set_addr_hash(struct adapter *adap, unsigned int mbox, unsigned int viid,
994 bool ucast, u64 vec, bool sleep_ok);
995int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid,
996 bool rx_en, bool tx_en);
997int t4_identify_port(struct adapter *adap, unsigned int mbox, unsigned int viid,
998 unsigned int nblinks);
999int t4_mdio_rd(struct adapter *adap, unsigned int mbox, unsigned int phy_addr,
1000 unsigned int mmd, unsigned int reg, u16 *valp);
1001int t4_mdio_wr(struct adapter *adap, unsigned int mbox, unsigned int phy_addr,
1002 unsigned int mmd, unsigned int reg, u16 val);
625ba2c2
DM		 1003int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
1004 unsigned int vf, unsigned int iqtype, unsigned int iqid,
1005 unsigned int fl0id, unsigned int fl1id);
1006int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
1007 unsigned int vf, unsigned int eqid);
1008int t4_ctrl_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
1009 unsigned int vf, unsigned int eqid);
1010int t4_ofld_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
1011 unsigned int vf, unsigned int eqid);
1012int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl);
881806bc
VP		 1013void t4_db_full(struct adapter *adapter);
1014void t4_db_dropped(struct adapter *adapter);
8caa1e84
VP		 1015int t4_mem_win_read_len(struct adapter *adap, u32 addr, __be32 *data, int len);
1016int t4_fwaddrspace_write(struct adapter *adap, unsigned int mbox,
1017 u32 addr, u32 val);
625ba2c2 1018#endif /* __CXGB4_H__ */
Linux kernel - Deliverables
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