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cxgb4/cxgb4vf: Code cleanup to enable T4 Configuration File support
[deliverable/linux.git] / drivers / net / ethernet / chelsio / cxgb4 / cxgb4.h
CommitLineData
625ba2c2
DM		 1/*
2 * This file is part of the Chelsio T4 Ethernet driver for Linux.
3 *
4 * Copyright (c) 2003-2010 Chelsio Communications, Inc. All rights reserved.
5 *
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
11 *
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
14 * conditions are met:
15 *
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
18 * disclaimer.
19 *
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
24 *
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
32 * SOFTWARE.
33 */
34
35#ifndef __CXGB4_H__
36#define __CXGB4_H__
37
38#include <linux/bitops.h>
39#include <linux/cache.h>
40#include <linux/interrupt.h>
41#include <linux/list.h>
42#include <linux/netdevice.h>
43#include <linux/pci.h>
44#include <linux/spinlock.h>
45#include <linux/timer.h>
46#include <asm/io.h>
47#include "cxgb4_uld.h"
48#include "t4_hw.h"
49
50#define FW_VERSION_MAJOR 1
51#define FW_VERSION_MINOR 1
52#define FW_VERSION_MICRO 0
53
3069ee9b
VP		 54#define CH_WARN(adap, fmt, ...) dev_warn(adap->pdev_dev, fmt, ## __VA_ARGS__)
55
625ba2c2
DM		 56enum {
57 MAX_NPORTS = 4, /* max # of ports */
47d54d65 58 SERNUM_LEN = 24, /* Serial # length */
625ba2c2
DM		 59 EC_LEN = 16, /* E/C length */
60 ID_LEN = 16, /* ID length */
61};
62
63enum {
64 MEM_EDC0,
65 MEM_EDC1,
66 MEM_MC
67};
68
3069ee9b 69enum {
3eb4afbf
VP		 70 MEMWIN0_APERTURE = 2048,
71 MEMWIN0_BASE = 0x1b800,
3069ee9b
VP		 72 MEMWIN1_APERTURE = 32768,
73 MEMWIN1_BASE = 0x28000,
3eb4afbf
VP		 74 MEMWIN2_APERTURE = 65536,
75 MEMWIN2_BASE = 0x30000,
3069ee9b
VP		 76};
77
625ba2c2
DM		 78enum dev_master {
79 MASTER_CANT,
80 MASTER_MAY,
81 MASTER_MUST
82};
83
84enum dev_state {
85 DEV_STATE_UNINIT,
86 DEV_STATE_INIT,
87 DEV_STATE_ERR
88};
89
90enum {
91 PAUSE_RX = 1 << 0,
92 PAUSE_TX = 1 << 1,
93 PAUSE_AUTONEG = 1 << 2
94};
95
96struct port_stats {
97 u64 tx_octets; /* total # of octets in good frames */
98 u64 tx_frames; /* all good frames */
99 u64 tx_bcast_frames; /* all broadcast frames */
100 u64 tx_mcast_frames; /* all multicast frames */
101 u64 tx_ucast_frames; /* all unicast frames */
102 u64 tx_error_frames; /* all error frames */
103
104 u64 tx_frames_64; /* # of Tx frames in a particular range */
105 u64 tx_frames_65_127;
106 u64 tx_frames_128_255;
107 u64 tx_frames_256_511;
108 u64 tx_frames_512_1023;
109 u64 tx_frames_1024_1518;
110 u64 tx_frames_1519_max;
111
112 u64 tx_drop; /* # of dropped Tx frames */
113 u64 tx_pause; /* # of transmitted pause frames */
114 u64 tx_ppp0; /* # of transmitted PPP prio 0 frames */
115 u64 tx_ppp1; /* # of transmitted PPP prio 1 frames */
116 u64 tx_ppp2; /* # of transmitted PPP prio 2 frames */
117 u64 tx_ppp3; /* # of transmitted PPP prio 3 frames */
118 u64 tx_ppp4; /* # of transmitted PPP prio 4 frames */
119 u64 tx_ppp5; /* # of transmitted PPP prio 5 frames */
120 u64 tx_ppp6; /* # of transmitted PPP prio 6 frames */
121 u64 tx_ppp7; /* # of transmitted PPP prio 7 frames */
122
123 u64 rx_octets; /* total # of octets in good frames */
124 u64 rx_frames; /* all good frames */
125 u64 rx_bcast_frames; /* all broadcast frames */
126 u64 rx_mcast_frames; /* all multicast frames */
127 u64 rx_ucast_frames; /* all unicast frames */
128 u64 rx_too_long; /* # of frames exceeding MTU */
129 u64 rx_jabber; /* # of jabber frames */
130 u64 rx_fcs_err; /* # of received frames with bad FCS */
131 u64 rx_len_err; /* # of received frames with length error */
132 u64 rx_symbol_err; /* symbol errors */
133 u64 rx_runt; /* # of short frames */
134
135 u64 rx_frames_64; /* # of Rx frames in a particular range */
136 u64 rx_frames_65_127;
137 u64 rx_frames_128_255;
138 u64 rx_frames_256_511;
139 u64 rx_frames_512_1023;
140 u64 rx_frames_1024_1518;
141 u64 rx_frames_1519_max;
142
143 u64 rx_pause; /* # of received pause frames */
144 u64 rx_ppp0; /* # of received PPP prio 0 frames */
145 u64 rx_ppp1; /* # of received PPP prio 1 frames */
146 u64 rx_ppp2; /* # of received PPP prio 2 frames */
147 u64 rx_ppp3; /* # of received PPP prio 3 frames */
148 u64 rx_ppp4; /* # of received PPP prio 4 frames */
149 u64 rx_ppp5; /* # of received PPP prio 5 frames */
150 u64 rx_ppp6; /* # of received PPP prio 6 frames */
151 u64 rx_ppp7; /* # of received PPP prio 7 frames */
152
153 u64 rx_ovflow0; /* drops due to buffer-group 0 overflows */
154 u64 rx_ovflow1; /* drops due to buffer-group 1 overflows */
155 u64 rx_ovflow2; /* drops due to buffer-group 2 overflows */
156 u64 rx_ovflow3; /* drops due to buffer-group 3 overflows */
157 u64 rx_trunc0; /* buffer-group 0 truncated packets */
158 u64 rx_trunc1; /* buffer-group 1 truncated packets */
159 u64 rx_trunc2; /* buffer-group 2 truncated packets */
160 u64 rx_trunc3; /* buffer-group 3 truncated packets */
161};
162
163struct lb_port_stats {
164 u64 octets;
165 u64 frames;
166 u64 bcast_frames;
167 u64 mcast_frames;
168 u64 ucast_frames;
169 u64 error_frames;
170
171 u64 frames_64;
172 u64 frames_65_127;
173 u64 frames_128_255;
174 u64 frames_256_511;
175 u64 frames_512_1023;
176 u64 frames_1024_1518;
177 u64 frames_1519_max;
178
179 u64 drop;
180
181 u64 ovflow0;
182 u64 ovflow1;
183 u64 ovflow2;
184 u64 ovflow3;
185 u64 trunc0;
186 u64 trunc1;
187 u64 trunc2;
188 u64 trunc3;
189};
190
191struct tp_tcp_stats {
192 u32 tcpOutRsts;
193 u64 tcpInSegs;
194 u64 tcpOutSegs;
195 u64 tcpRetransSegs;
196};
197
198struct tp_err_stats {
199 u32 macInErrs[4];
200 u32 hdrInErrs[4];
201 u32 tcpInErrs[4];
202 u32 tnlCongDrops[4];
203 u32 ofldChanDrops[4];
204 u32 tnlTxDrops[4];
205 u32 ofldVlanDrops[4];
206 u32 tcp6InErrs[4];
207 u32 ofldNoNeigh;
208 u32 ofldCongDefer;
209};
210
211struct tp_params {
212 unsigned int ntxchan; /* # of Tx channels */
213 unsigned int tre; /* log2 of core clocks per TP tick */
214};
215
216struct vpd_params {
217 unsigned int cclk;
218 u8 ec[EC_LEN + 1];
219 u8 sn[SERNUM_LEN + 1];
220 u8 id[ID_LEN + 1];
221};
222
223struct pci_params {
224 unsigned char speed;
225 unsigned char width;
226};
227
228struct adapter_params {
229 struct tp_params tp;
230 struct vpd_params vpd;
231 struct pci_params pci;
232
900a6596
DM		 233 unsigned int sf_size; /* serial flash size in bytes */
234 unsigned int sf_nsec; /* # of flash sectors */
235 unsigned int sf_fw_start; /* start of FW image in flash */
236
625ba2c2
DM		 237 unsigned int fw_vers;
238 unsigned int tp_vers;
239 u8 api_vers[7];
240
241 unsigned short mtus[NMTUS];
242 unsigned short a_wnd[NCCTRL_WIN];
243 unsigned short b_wnd[NCCTRL_WIN];
244
245 unsigned char nports; /* # of ethernet ports */
246 unsigned char portvec;
247 unsigned char rev; /* chip revision */
248 unsigned char offload;
249
250 unsigned int ofldq_wr_cred;
251};
252
253struct trace_params {
254 u32 data[TRACE_LEN / 4];
255 u32 mask[TRACE_LEN / 4];
256 unsigned short snap_len;
257 unsigned short min_len;
258 unsigned char skip_ofst;
259 unsigned char skip_len;
260 unsigned char invert;
261 unsigned char port;
262};
263
264struct link_config {
265 unsigned short supported; /* link capabilities */
266 unsigned short advertising; /* advertised capabilities */
267 unsigned short requested_speed; /* speed user has requested */
268 unsigned short speed; /* actual link speed */
269 unsigned char requested_fc; /* flow control user has requested */
270 unsigned char fc; /* actual link flow control */
271 unsigned char autoneg; /* autonegotiating? */
272 unsigned char link_ok; /* link up? */
273};
274
275#define FW_LEN16(fw_struct) FW_CMD_LEN16(sizeof(fw_struct) / 16)
276
277enum {
278 MAX_ETH_QSETS = 32, /* # of Ethernet Tx/Rx queue sets */
279 MAX_OFLD_QSETS = 16, /* # of offload Tx/Rx queue sets */
280 MAX_CTRL_QUEUES = NCHAN, /* # of control Tx queues */
281 MAX_RDMA_QUEUES = NCHAN, /* # of streaming RDMA Rx queues */
282};
283
284enum {
285 MAX_EGRQ = 128, /* max # of egress queues, including FLs */
286 MAX_INGQ = 64 /* max # of interrupt-capable ingress queues */
287};
288
289struct adapter;
625ba2c2
DM		 290struct sge_rspq;
291
292struct port_info {
293 struct adapter *adapter;
625ba2c2
DM		 294 u16 viid;
295 s16 xact_addr_filt; /* index of exact MAC address filter */
296 u16 rss_size; /* size of VI's RSS table slice */
297 s8 mdio_addr;
298 u8 port_type;
299 u8 mod_type;
300 u8 port_id;
301 u8 tx_chan;
302 u8 lport; /* associated offload logical port */
625ba2c2
DM		 303 u8 nqsets; /* # of qsets */
304 u8 first_qset; /* index of first qset */
f796564a 305 u8 rss_mode;
625ba2c2 306 struct link_config link_cfg;
671b0060 307 u16 *rss;
625ba2c2
DM		 308};
309
625ba2c2
DM		 310struct dentry;
311struct work_struct;
312
313enum { /* adapter flags */
314 FULL_INIT_DONE = (1 << 0),
315 USING_MSI = (1 << 1),
316 USING_MSIX = (1 << 2),
625ba2c2 317 FW_OK = (1 << 4),
52367a76
VP		 318 USING_SOFT_PARAMS = (1 << 6),
319 MASTER_PF = (1 << 7),
320 FW_OFLD_CONN = (1 << 9),
625ba2c2
DM		 321};
322
323struct rx_sw_desc;
324
325struct sge_fl { /* SGE free-buffer queue state */
326 unsigned int avail; /* # of available Rx buffers */
327 unsigned int pend_cred; /* new buffers since last FL DB ring */
328 unsigned int cidx; /* consumer index */
329 unsigned int pidx; /* producer index */
330 unsigned long alloc_failed; /* # of times buffer allocation failed */
331 unsigned long large_alloc_failed;
332 unsigned long starving;
333 /* RO fields */
334 unsigned int cntxt_id; /* SGE context id for the free list */
335 unsigned int size; /* capacity of free list */
336 struct rx_sw_desc *sdesc; /* address of SW Rx descriptor ring */
337 __be64 *desc; /* address of HW Rx descriptor ring */
338 dma_addr_t addr; /* bus address of HW ring start */
339};
340
341/* A packet gather list */
342struct pkt_gl {
e91b0f24 343 struct page_frag frags[MAX_SKB_FRAGS];
625ba2c2
DM		 344 void *va; /* virtual address of first byte */
345 unsigned int nfrags; /* # of fragments */
346 unsigned int tot_len; /* total length of fragments */
347};
348
349typedef int (*rspq_handler_t)(struct sge_rspq *q, const __be64 *rsp,
350 const struct pkt_gl *gl);
351
352struct sge_rspq { /* state for an SGE response queue */
353 struct napi_struct napi;
354 const __be64 *cur_desc; /* current descriptor in queue */
355 unsigned int cidx; /* consumer index */
356 u8 gen; /* current generation bit */
357 u8 intr_params; /* interrupt holdoff parameters */
358 u8 next_intr_params; /* holdoff params for next interrupt */
359 u8 pktcnt_idx; /* interrupt packet threshold */
360 u8 uld; /* ULD handling this queue */
361 u8 idx; /* queue index within its group */
362 int offset; /* offset into current Rx buffer */
363 u16 cntxt_id; /* SGE context id for the response q */
364 u16 abs_id; /* absolute SGE id for the response q */
365 __be64 *desc; /* address of HW response ring */
366 dma_addr_t phys_addr; /* physical address of the ring */
367 unsigned int iqe_len; /* entry size */
368 unsigned int size; /* capacity of response queue */
369 struct adapter *adap;
370 struct net_device *netdev; /* associated net device */
371 rspq_handler_t handler;
372};
373
374struct sge_eth_stats { /* Ethernet queue statistics */
375 unsigned long pkts; /* # of ethernet packets */
376 unsigned long lro_pkts; /* # of LRO super packets */
377 unsigned long lro_merged; /* # of wire packets merged by LRO */
378 unsigned long rx_cso; /* # of Rx checksum offloads */
379 unsigned long vlan_ex; /* # of Rx VLAN extractions */
380 unsigned long rx_drops; /* # of packets dropped due to no mem */
381};
382
383struct sge_eth_rxq { /* SW Ethernet Rx queue */
384 struct sge_rspq rspq;
385 struct sge_fl fl;
386 struct sge_eth_stats stats;
387} ____cacheline_aligned_in_smp;
388
389struct sge_ofld_stats { /* offload queue statistics */
390 unsigned long pkts; /* # of packets */
391 unsigned long imm; /* # of immediate-data packets */
392 unsigned long an; /* # of asynchronous notifications */
393 unsigned long nomem; /* # of responses deferred due to no mem */
394};
395
396struct sge_ofld_rxq { /* SW offload Rx queue */
397 struct sge_rspq rspq;
398 struct sge_fl fl;
399 struct sge_ofld_stats stats;
400} ____cacheline_aligned_in_smp;
401
402struct tx_desc {
403 __be64 flit[8];
404};
405
406struct tx_sw_desc;
407
408struct sge_txq {
409 unsigned int in_use; /* # of in-use Tx descriptors */
410 unsigned int size; /* # of descriptors */
411 unsigned int cidx; /* SW consumer index */
412 unsigned int pidx; /* producer index */
413 unsigned long stops; /* # of times q has been stopped */
414 unsigned long restarts; /* # of queue restarts */
415 unsigned int cntxt_id; /* SGE context id for the Tx q */
416 struct tx_desc *desc; /* address of HW Tx descriptor ring */
417 struct tx_sw_desc *sdesc; /* address of SW Tx descriptor ring */
418 struct sge_qstat *stat; /* queue status entry */
419 dma_addr_t phys_addr; /* physical address of the ring */
3069ee9b
VP		 420 spinlock_t db_lock;
421 int db_disabled;
422 unsigned short db_pidx;
625ba2c2
DM		 423};
424
425struct sge_eth_txq { /* state for an SGE Ethernet Tx queue */
426 struct sge_txq q;
427 struct netdev_queue *txq; /* associated netdev TX queue */
428 unsigned long tso; /* # of TSO requests */
429 unsigned long tx_cso; /* # of Tx checksum offloads */
430 unsigned long vlan_ins; /* # of Tx VLAN insertions */
431 unsigned long mapping_err; /* # of I/O MMU packet mapping errors */
432} ____cacheline_aligned_in_smp;
433
434struct sge_ofld_txq { /* state for an SGE offload Tx queue */
435 struct sge_txq q;
436 struct adapter *adap;
437 struct sk_buff_head sendq; /* list of backpressured packets */
438 struct tasklet_struct qresume_tsk; /* restarts the queue */
439 u8 full; /* the Tx ring is full */
440 unsigned long mapping_err; /* # of I/O MMU packet mapping errors */
441} ____cacheline_aligned_in_smp;
442
443struct sge_ctrl_txq { /* state for an SGE control Tx queue */
444 struct sge_txq q;
445 struct adapter *adap;
446 struct sk_buff_head sendq; /* list of backpressured packets */
447 struct tasklet_struct qresume_tsk; /* restarts the queue */
448 u8 full; /* the Tx ring is full */
449} ____cacheline_aligned_in_smp;
450
451struct sge {
452 struct sge_eth_txq ethtxq[MAX_ETH_QSETS];
453 struct sge_ofld_txq ofldtxq[MAX_OFLD_QSETS];
454 struct sge_ctrl_txq ctrlq[MAX_CTRL_QUEUES];
455
456 struct sge_eth_rxq ethrxq[MAX_ETH_QSETS];
457 struct sge_ofld_rxq ofldrxq[MAX_OFLD_QSETS];
458 struct sge_ofld_rxq rdmarxq[MAX_RDMA_QUEUES];
459 struct sge_rspq fw_evtq ____cacheline_aligned_in_smp;
460
461 struct sge_rspq intrq ____cacheline_aligned_in_smp;
462 spinlock_t intrq_lock;
463
464 u16 max_ethqsets; /* # of available Ethernet queue sets */
465 u16 ethqsets; /* # of active Ethernet queue sets */
466 u16 ethtxq_rover; /* Tx queue to clean up next */
467 u16 ofldqsets; /* # of active offload queue sets */
468 u16 rdmaqs; /* # of available RDMA Rx queues */
469 u16 ofld_rxq[MAX_OFLD_QSETS];
470 u16 rdma_rxq[NCHAN];
471 u16 timer_val[SGE_NTIMERS];
472 u8 counter_val[SGE_NCOUNTERS];
52367a76
VP		 473 u32 fl_pg_order; /* large page allocation size */
474 u32 stat_len; /* length of status page at ring end */
475 u32 pktshift; /* padding between CPL & packet data */
476 u32 fl_align; /* response queue message alignment */
477 u32 fl_starve_thres; /* Free List starvation threshold */
625ba2c2
DM		 478 unsigned int starve_thres;
479 u8 idma_state[2];
e46dab4d
DM		 480 unsigned int egr_start;
481 unsigned int ingr_start;
625ba2c2
DM		 482 void *egr_map[MAX_EGRQ]; /* qid->queue egress queue map */
483 struct sge_rspq *ingr_map[MAX_INGQ]; /* qid->queue ingress queue map */
484 DECLARE_BITMAP(starving_fl, MAX_EGRQ);
485 DECLARE_BITMAP(txq_maperr, MAX_EGRQ);
486 struct timer_list rx_timer; /* refills starving FLs */
487 struct timer_list tx_timer; /* checks Tx queues */
488};
489
490#define for_each_ethrxq(sge, i) for (i = 0; i < (sge)->ethqsets; i++)
491#define for_each_ofldrxq(sge, i) for (i = 0; i < (sge)->ofldqsets; i++)
492#define for_each_rdmarxq(sge, i) for (i = 0; i < (sge)->rdmaqs; i++)
493
494struct l2t_data;
495
496struct adapter {
497 void __iomem *regs;
498 struct pci_dev *pdev;
499 struct device *pdev_dev;
3069ee9b 500 unsigned int mbox;
060e0c75
DM		 501 unsigned int fn;
502 unsigned int flags;
625ba2c2 503
625ba2c2
DM		 504 int msg_enable;
505
506 struct adapter_params params;
507 struct cxgb4_virt_res vres;
508 unsigned int swintr;
509
510 unsigned int wol;
511
512 struct {
513 unsigned short vec;
8cd18ac4 514 char desc[IFNAMSIZ + 10];
625ba2c2
DM		 515 } msix_info[MAX_INGQ + 1];
516
517 struct sge sge;
518
519 struct net_device *port[MAX_NPORTS];
520 u8 chan_map[NCHAN]; /* channel -> port map */
521
522 struct l2t_data *l2t;
523 void *uld_handle[CXGB4_ULD_MAX];
524 struct list_head list_node;
525
526 struct tid_info tids;
527 void **tid_release_head;
528 spinlock_t tid_release_lock;
529 struct work_struct tid_release_task;
881806bc
VP		 530 struct work_struct db_full_task;
531 struct work_struct db_drop_task;
625ba2c2
DM		 532 bool tid_release_task_busy;
533
534 struct dentry *debugfs_root;
535
536 spinlock_t stats_lock;
537};
538
539static inline u32 t4_read_reg(struct adapter *adap, u32 reg_addr)
540{
541 return readl(adap->regs + reg_addr);
542}
543
544static inline void t4_write_reg(struct adapter *adap, u32 reg_addr, u32 val)
545{
546 writel(val, adap->regs + reg_addr);
547}
548
549#ifndef readq
550static inline u64 readq(const volatile void __iomem *addr)
551{
552 return readl(addr) + ((u64)readl(addr + 4) << 32);
553}
554
555static inline void writeq(u64 val, volatile void __iomem *addr)
556{
557 writel(val, addr);
558 writel(val >> 32, addr + 4);
559}
560#endif
561
562static inline u64 t4_read_reg64(struct adapter *adap, u32 reg_addr)
563{
564 return readq(adap->regs + reg_addr);
565}
566
567static inline void t4_write_reg64(struct adapter *adap, u32 reg_addr, u64 val)
568{
569 writeq(val, adap->regs + reg_addr);
570}
571
572/**
573 * netdev2pinfo - return the port_info structure associated with a net_device
574 * @dev: the netdev
575 *
576 * Return the struct port_info associated with a net_device
577 */
578static inline struct port_info *netdev2pinfo(const struct net_device *dev)
579{
580 return netdev_priv(dev);
581}
582
583/**
584 * adap2pinfo - return the port_info of a port
585 * @adap: the adapter
586 * @idx: the port index
587 *
588 * Return the port_info structure for the port of the given index.
589 */
590static inline struct port_info *adap2pinfo(struct adapter *adap, int idx)
591{
592 return netdev_priv(adap->port[idx]);
593}
594
595/**
596 * netdev2adap - return the adapter structure associated with a net_device
597 * @dev: the netdev
598 *
599 * Return the struct adapter associated with a net_device
600 */
601static inline struct adapter *netdev2adap(const struct net_device *dev)
602{
603 return netdev2pinfo(dev)->adapter;
604}
605
606void t4_os_portmod_changed(const struct adapter *adap, int port_id);
607void t4_os_link_changed(struct adapter *adap, int port_id, int link_stat);
608
609void *t4_alloc_mem(size_t size);
625ba2c2
DM		 610
611void t4_free_sge_resources(struct adapter *adap);
612irq_handler_t t4_intr_handler(struct adapter *adap);
613netdev_tx_t t4_eth_xmit(struct sk_buff *skb, struct net_device *dev);
614int t4_ethrx_handler(struct sge_rspq *q, const __be64 *rsp,
615 const struct pkt_gl *gl);
616int t4_mgmt_tx(struct adapter *adap, struct sk_buff *skb);
617int t4_ofld_send(struct adapter *adap, struct sk_buff *skb);
618int t4_sge_alloc_rxq(struct adapter *adap, struct sge_rspq *iq, bool fwevtq,
619 struct net_device *dev, int intr_idx,
620 struct sge_fl *fl, rspq_handler_t hnd);
621int t4_sge_alloc_eth_txq(struct adapter *adap, struct sge_eth_txq *txq,
622 struct net_device *dev, struct netdev_queue *netdevq,
623 unsigned int iqid);
624int t4_sge_alloc_ctrl_txq(struct adapter *adap, struct sge_ctrl_txq *txq,
625 struct net_device *dev, unsigned int iqid,
626 unsigned int cmplqid);
627int t4_sge_alloc_ofld_txq(struct adapter *adap, struct sge_ofld_txq *txq,
628 struct net_device *dev, unsigned int iqid);
629irqreturn_t t4_sge_intr_msix(int irq, void *cookie);
52367a76 630int t4_sge_init(struct adapter *adap);
625ba2c2
DM		 631void t4_sge_start(struct adapter *adap);
632void t4_sge_stop(struct adapter *adap);
3069ee9b 633extern int dbfifo_int_thresh;
625ba2c2
DM		 634
635#define for_each_port(adapter, iter) \
636 for (iter = 0; iter < (adapter)->params.nports; ++iter)
637
638static inline unsigned int core_ticks_per_usec(const struct adapter *adap)
639{
640 return adap->params.vpd.cclk / 1000;
641}
642
643static inline unsigned int us_to_core_ticks(const struct adapter *adap,
644 unsigned int us)
645{
646 return (us * adap->params.vpd.cclk) / 1000;
647}
648
52367a76
VP		 649static inline unsigned int core_ticks_to_us(const struct adapter *adapter,
650 unsigned int ticks)
651{
652 /* add Core Clock / 2 to round ticks to nearest uS */
653 return ((ticks * 1000 + adapter->params.vpd.cclk/2) /
654 adapter->params.vpd.cclk);
655}
656
625ba2c2
DM		 657void t4_set_reg_field(struct adapter *adap, unsigned int addr, u32 mask,
658 u32 val);
659
660int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size,
661 void *rpl, bool sleep_ok);
662
663static inline int t4_wr_mbox(struct adapter *adap, int mbox, const void *cmd,
664 int size, void *rpl)
665{
666 return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, true);
667}
668
669static inline int t4_wr_mbox_ns(struct adapter *adap, int mbox, const void *cmd,
670 int size, void *rpl)
671{
672 return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, false);
673}
674
675void t4_intr_enable(struct adapter *adapter);
676void t4_intr_disable(struct adapter *adapter);
625ba2c2
DM		 677int t4_slow_intr_handler(struct adapter *adapter);
678
204dc3c0 679int t4_wait_dev_ready(struct adapter *adap);
625ba2c2
DM		 680int t4_link_start(struct adapter *adap, unsigned int mbox, unsigned int port,
681 struct link_config *lc);
682int t4_restart_aneg(struct adapter *adap, unsigned int mbox, unsigned int port);
5afc8b84
VP		 683int t4_memory_write(struct adapter *adap, int mtype, u32 addr, u32 len,
684 __be32 *buf);
625ba2c2 685int t4_seeprom_wp(struct adapter *adapter, bool enable);
625ba2c2
DM		 686int t4_load_fw(struct adapter *adapter, const u8 *fw_data, unsigned int size);
687int t4_check_fw_version(struct adapter *adapter);
688int t4_prep_adapter(struct adapter *adapter);
689int t4_port_init(struct adapter *adap, int mbox, int pf, int vf);
690void t4_fatal_err(struct adapter *adapter);
625ba2c2
DM		 691int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid,
692 int start, int n, const u16 *rspq, unsigned int nrspq);
693int t4_config_glbl_rss(struct adapter *adapter, int mbox, unsigned int mode,
694 unsigned int flags);
625ba2c2
DM		 695int t4_mc_read(struct adapter *adap, u32 addr, __be32 *data, u64 *parity);
696int t4_edc_read(struct adapter *adap, int idx, u32 addr, __be32 *data,
697 u64 *parity);
698
699void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p);
625ba2c2 700void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log);
625ba2c2
DM		 701void t4_tp_get_tcp_stats(struct adapter *adap, struct tp_tcp_stats *v4,
702 struct tp_tcp_stats *v6);
703void t4_load_mtus(struct adapter *adap, const unsigned short *mtus,
704 const unsigned short *alpha, const unsigned short *beta);
705
706void t4_wol_magic_enable(struct adapter *adap, unsigned int port,
707 const u8 *addr);
708int t4_wol_pat_enable(struct adapter *adap, unsigned int port, unsigned int map,
709 u64 mask0, u64 mask1, unsigned int crc, bool enable);
710
711int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox,
712 enum dev_master master, enum dev_state *state);
713int t4_fw_bye(struct adapter *adap, unsigned int mbox);
714int t4_early_init(struct adapter *adap, unsigned int mbox);
715int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset);
716int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
717 unsigned int vf, unsigned int nparams, const u32 *params,
718 u32 *val);
719int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
720 unsigned int vf, unsigned int nparams, const u32 *params,
721 const u32 *val);
722int t4_cfg_pfvf(struct adapter *adap, unsigned int mbox, unsigned int pf,
723 unsigned int vf, unsigned int txq, unsigned int txq_eth_ctrl,
724 unsigned int rxqi, unsigned int rxq, unsigned int tc,
725 unsigned int vi, unsigned int cmask, unsigned int pmask,
726 unsigned int nexact, unsigned int rcaps, unsigned int wxcaps);
727int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port,
728 unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac,
729 unsigned int *rss_size);
625ba2c2 730int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid,
f8f5aafa
DM		 731 int mtu, int promisc, int all_multi, int bcast, int vlanex,
732 bool sleep_ok);
625ba2c2
DM		 733int t4_alloc_mac_filt(struct adapter *adap, unsigned int mbox,
734 unsigned int viid, bool free, unsigned int naddr,
735 const u8 **addr, u16 *idx, u64 *hash, bool sleep_ok);
736int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid,
737 int idx, const u8 *addr, bool persist, bool add_smt);
738int t4_set_addr_hash(struct adapter *adap, unsigned int mbox, unsigned int viid,
739 bool ucast, u64 vec, bool sleep_ok);
740int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid,
741 bool rx_en, bool tx_en);
742int t4_identify_port(struct adapter *adap, unsigned int mbox, unsigned int viid,
743 unsigned int nblinks);
744int t4_mdio_rd(struct adapter *adap, unsigned int mbox, unsigned int phy_addr,
745 unsigned int mmd, unsigned int reg, u16 *valp);
746int t4_mdio_wr(struct adapter *adap, unsigned int mbox, unsigned int phy_addr,
747 unsigned int mmd, unsigned int reg, u16 val);
625ba2c2
DM		 748int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
749 unsigned int vf, unsigned int iqtype, unsigned int iqid,
750 unsigned int fl0id, unsigned int fl1id);
751int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
752 unsigned int vf, unsigned int eqid);
753int t4_ctrl_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
754 unsigned int vf, unsigned int eqid);
755int t4_ofld_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
756 unsigned int vf, unsigned int eqid);
757int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl);
881806bc
VP		 758void t4_db_full(struct adapter *adapter);
759void t4_db_dropped(struct adapter *adapter);
8caa1e84
VP		 760int t4_mem_win_read_len(struct adapter *adap, u32 addr, __be32 *data, int len);
761int t4_fwaddrspace_write(struct adapter *adap, unsigned int mbox,
762 u32 addr, u32 val);
625ba2c2 763#endif /* __CXGB4_H__ */
Linux kernel - Deliverables
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