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cxgb4vf: added much cleaner implementation of is_t4()
[deliverable/linux.git] / drivers / net / ethernet / chelsio / cxgb4 / cxgb4.h
CommitLineData
625ba2c2
DM		 1/*
2 * This file is part of the Chelsio T4 Ethernet driver for Linux.
3 *
4 * Copyright (c) 2003-2010 Chelsio Communications, Inc. All rights reserved.
5 *
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
11 *
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
14 * conditions are met:
15 *
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
18 * disclaimer.
19 *
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
24 *
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
32 * SOFTWARE.
33 */
34
35#ifndef __CXGB4_H__
36#define __CXGB4_H__
37
dca4faeb
VP		 38#include "t4_hw.h"
39
625ba2c2
DM		 40#include <linux/bitops.h>
41#include <linux/cache.h>
42#include <linux/interrupt.h>
43#include <linux/list.h>
44#include <linux/netdevice.h>
45#include <linux/pci.h>
46#include <linux/spinlock.h>
47#include <linux/timer.h>
c0b8b992 48#include <linux/vmalloc.h>
625ba2c2
DM		 49#include <asm/io.h>
50#include "cxgb4_uld.h"
625ba2c2
DM		 51
52#define FW_VERSION_MAJOR 1
e69972f5 53#define FW_VERSION_MINOR 4
625ba2c2
DM		 54#define FW_VERSION_MICRO 0
55
2422d9a3
SR		 56#define FW_VERSION_MAJOR_T5 0
57#define FW_VERSION_MINOR_T5 0
58#define FW_VERSION_MICRO_T5 0
59
3069ee9b
VP		 60#define CH_WARN(adap, fmt, ...) dev_warn(adap->pdev_dev, fmt, ## __VA_ARGS__)
61
625ba2c2
DM		 62enum {
63 MAX_NPORTS = 4, /* max # of ports */
47d54d65 64 SERNUM_LEN = 24, /* Serial # length */
625ba2c2
DM		 65 EC_LEN = 16, /* E/C length */
66 ID_LEN = 16, /* ID length */
67};
68
69enum {
70 MEM_EDC0,
71 MEM_EDC1,
2422d9a3
SR		 72 MEM_MC,
73 MEM_MC0 = MEM_MC,
74 MEM_MC1
625ba2c2
DM		 75};
76
3069ee9b 77enum {
3eb4afbf
VP		 78 MEMWIN0_APERTURE = 2048,
79 MEMWIN0_BASE = 0x1b800,
3069ee9b
VP		 80 MEMWIN1_APERTURE = 32768,
81 MEMWIN1_BASE = 0x28000,
2422d9a3 82 MEMWIN1_BASE_T5 = 0x52000,
3eb4afbf
VP		 83 MEMWIN2_APERTURE = 65536,
84 MEMWIN2_BASE = 0x30000,
2422d9a3 85 MEMWIN2_BASE_T5 = 0x54000,
3069ee9b
VP		 86};
87
625ba2c2
DM		 88enum dev_master {
89 MASTER_CANT,
90 MASTER_MAY,
91 MASTER_MUST
92};
93
94enum dev_state {
95 DEV_STATE_UNINIT,
96 DEV_STATE_INIT,
97 DEV_STATE_ERR
98};
99
100enum {
101 PAUSE_RX = 1 << 0,
102 PAUSE_TX = 1 << 1,
103 PAUSE_AUTONEG = 1 << 2
104};
105
106struct port_stats {
107 u64 tx_octets; /* total # of octets in good frames */
108 u64 tx_frames; /* all good frames */
109 u64 tx_bcast_frames; /* all broadcast frames */
110 u64 tx_mcast_frames; /* all multicast frames */
111 u64 tx_ucast_frames; /* all unicast frames */
112 u64 tx_error_frames; /* all error frames */
113
114 u64 tx_frames_64; /* # of Tx frames in a particular range */
115 u64 tx_frames_65_127;
116 u64 tx_frames_128_255;
117 u64 tx_frames_256_511;
118 u64 tx_frames_512_1023;
119 u64 tx_frames_1024_1518;
120 u64 tx_frames_1519_max;
121
122 u64 tx_drop; /* # of dropped Tx frames */
123 u64 tx_pause; /* # of transmitted pause frames */
124 u64 tx_ppp0; /* # of transmitted PPP prio 0 frames */
125 u64 tx_ppp1; /* # of transmitted PPP prio 1 frames */
126 u64 tx_ppp2; /* # of transmitted PPP prio 2 frames */
127 u64 tx_ppp3; /* # of transmitted PPP prio 3 frames */
128 u64 tx_ppp4; /* # of transmitted PPP prio 4 frames */
129 u64 tx_ppp5; /* # of transmitted PPP prio 5 frames */
130 u64 tx_ppp6; /* # of transmitted PPP prio 6 frames */
131 u64 tx_ppp7; /* # of transmitted PPP prio 7 frames */
132
133 u64 rx_octets; /* total # of octets in good frames */
134 u64 rx_frames; /* all good frames */
135 u64 rx_bcast_frames; /* all broadcast frames */
136 u64 rx_mcast_frames; /* all multicast frames */
137 u64 rx_ucast_frames; /* all unicast frames */
138 u64 rx_too_long; /* # of frames exceeding MTU */
139 u64 rx_jabber; /* # of jabber frames */
140 u64 rx_fcs_err; /* # of received frames with bad FCS */
141 u64 rx_len_err; /* # of received frames with length error */
142 u64 rx_symbol_err; /* symbol errors */
143 u64 rx_runt; /* # of short frames */
144
145 u64 rx_frames_64; /* # of Rx frames in a particular range */
146 u64 rx_frames_65_127;
147 u64 rx_frames_128_255;
148 u64 rx_frames_256_511;
149 u64 rx_frames_512_1023;
150 u64 rx_frames_1024_1518;
151 u64 rx_frames_1519_max;
152
153 u64 rx_pause; /* # of received pause frames */
154 u64 rx_ppp0; /* # of received PPP prio 0 frames */
155 u64 rx_ppp1; /* # of received PPP prio 1 frames */
156 u64 rx_ppp2; /* # of received PPP prio 2 frames */
157 u64 rx_ppp3; /* # of received PPP prio 3 frames */
158 u64 rx_ppp4; /* # of received PPP prio 4 frames */
159 u64 rx_ppp5; /* # of received PPP prio 5 frames */
160 u64 rx_ppp6; /* # of received PPP prio 6 frames */
161 u64 rx_ppp7; /* # of received PPP prio 7 frames */
162
163 u64 rx_ovflow0; /* drops due to buffer-group 0 overflows */
164 u64 rx_ovflow1; /* drops due to buffer-group 1 overflows */
165 u64 rx_ovflow2; /* drops due to buffer-group 2 overflows */
166 u64 rx_ovflow3; /* drops due to buffer-group 3 overflows */
167 u64 rx_trunc0; /* buffer-group 0 truncated packets */
168 u64 rx_trunc1; /* buffer-group 1 truncated packets */
169 u64 rx_trunc2; /* buffer-group 2 truncated packets */
170 u64 rx_trunc3; /* buffer-group 3 truncated packets */
171};
172
173struct lb_port_stats {
174 u64 octets;
175 u64 frames;
176 u64 bcast_frames;
177 u64 mcast_frames;
178 u64 ucast_frames;
179 u64 error_frames;
180
181 u64 frames_64;
182 u64 frames_65_127;
183 u64 frames_128_255;
184 u64 frames_256_511;
185 u64 frames_512_1023;
186 u64 frames_1024_1518;
187 u64 frames_1519_max;
188
189 u64 drop;
190
191 u64 ovflow0;
192 u64 ovflow1;
193 u64 ovflow2;
194 u64 ovflow3;
195 u64 trunc0;
196 u64 trunc1;
197 u64 trunc2;
198 u64 trunc3;
199};
200
201struct tp_tcp_stats {
202 u32 tcpOutRsts;
203 u64 tcpInSegs;
204 u64 tcpOutSegs;
205 u64 tcpRetransSegs;
206};
207
208struct tp_err_stats {
209 u32 macInErrs[4];
210 u32 hdrInErrs[4];
211 u32 tcpInErrs[4];
212 u32 tnlCongDrops[4];
213 u32 ofldChanDrops[4];
214 u32 tnlTxDrops[4];
215 u32 ofldVlanDrops[4];
216 u32 tcp6InErrs[4];
217 u32 ofldNoNeigh;
218 u32 ofldCongDefer;
219};
220
221struct tp_params {
222 unsigned int ntxchan; /* # of Tx channels */
223 unsigned int tre; /* log2 of core clocks per TP tick */
dca4faeb
VP		 224 unsigned short tx_modq_map; /* TX modulation scheduler queue to */
225 /* channel map */
636f9d37
VP		 226
227 uint32_t dack_re; /* DACK timer resolution */
228 unsigned short tx_modq[NCHAN]; /* channel to modulation queue map */
625ba2c2
DM		 229};
230
231struct vpd_params {
232 unsigned int cclk;
233 u8 ec[EC_LEN + 1];
234 u8 sn[SERNUM_LEN + 1];
235 u8 id[ID_LEN + 1];
236};
237
238struct pci_params {
239 unsigned char speed;
240 unsigned char width;
241};
242
d14807dd
HS		 243#define CHELSIO_CHIP_CODE(version, revision) (((version) << 4) | (revision))
244#define CHELSIO_CHIP_FPGA 0x100
245#define CHELSIO_CHIP_VERSION(code) (((code) >> 4) & 0xf)
246#define CHELSIO_CHIP_RELEASE(code) ((code) & 0xf)
247
248#define CHELSIO_T4 0x4
249#define CHELSIO_T5 0x5
250
251enum chip_type {
252 T4_A1 = CHELSIO_CHIP_CODE(CHELSIO_T4, 1),
253 T4_A2 = CHELSIO_CHIP_CODE(CHELSIO_T4, 2),
254 T4_FIRST_REV = T4_A1,
255 T4_LAST_REV = T4_A2,
256
257 T5_A0 = CHELSIO_CHIP_CODE(CHELSIO_T5, 0),
258 T5_A1 = CHELSIO_CHIP_CODE(CHELSIO_T5, 1),
259 T5_FIRST_REV = T5_A0,
260 T5_LAST_REV = T5_A1,
261};
262
625ba2c2
DM		 263struct adapter_params {
264 struct tp_params tp;
265 struct vpd_params vpd;
266 struct pci_params pci;
267
900a6596
DM		 268 unsigned int sf_size; /* serial flash size in bytes */
269 unsigned int sf_nsec; /* # of flash sectors */
270 unsigned int sf_fw_start; /* start of FW image in flash */
271
625ba2c2
DM		 272 unsigned int fw_vers;
273 unsigned int tp_vers;
274 u8 api_vers[7];
275
276 unsigned short mtus[NMTUS];
277 unsigned short a_wnd[NCCTRL_WIN];
278 unsigned short b_wnd[NCCTRL_WIN];
279
280 unsigned char nports; /* # of ethernet ports */
281 unsigned char portvec;
d14807dd 282 enum chip_type chip; /* chip code */
625ba2c2
DM		 283 unsigned char offload;
284
9a4da2cd
VP		 285 unsigned char bypass;
286
625ba2c2
DM		 287 unsigned int ofldq_wr_cred;
288};
289
290struct trace_params {
291 u32 data[TRACE_LEN / 4];
292 u32 mask[TRACE_LEN / 4];
293 unsigned short snap_len;
294 unsigned short min_len;
295 unsigned char skip_ofst;
296 unsigned char skip_len;
297 unsigned char invert;
298 unsigned char port;
299};
300
301struct link_config {
302 unsigned short supported; /* link capabilities */
303 unsigned short advertising; /* advertised capabilities */
304 unsigned short requested_speed; /* speed user has requested */
305 unsigned short speed; /* actual link speed */
306 unsigned char requested_fc; /* flow control user has requested */
307 unsigned char fc; /* actual link flow control */
308 unsigned char autoneg; /* autonegotiating? */
309 unsigned char link_ok; /* link up? */
310};
311
312#define FW_LEN16(fw_struct) FW_CMD_LEN16(sizeof(fw_struct) / 16)
313
314enum {
315 MAX_ETH_QSETS = 32, /* # of Ethernet Tx/Rx queue sets */
316 MAX_OFLD_QSETS = 16, /* # of offload Tx/Rx queue sets */
317 MAX_CTRL_QUEUES = NCHAN, /* # of control Tx queues */
318 MAX_RDMA_QUEUES = NCHAN, /* # of streaming RDMA Rx queues */
319};
320
321enum {
322 MAX_EGRQ = 128, /* max # of egress queues, including FLs */
323 MAX_INGQ = 64 /* max # of interrupt-capable ingress queues */
324};
325
326struct adapter;
625ba2c2
DM		 327struct sge_rspq;
328
329struct port_info {
330 struct adapter *adapter;
625ba2c2
DM		 331 u16 viid;
332 s16 xact_addr_filt; /* index of exact MAC address filter */
333 u16 rss_size; /* size of VI's RSS table slice */
334 s8 mdio_addr;
335 u8 port_type;
336 u8 mod_type;
337 u8 port_id;
338 u8 tx_chan;
339 u8 lport; /* associated offload logical port */
625ba2c2
DM		 340 u8 nqsets; /* # of qsets */
341 u8 first_qset; /* index of first qset */
f796564a 342 u8 rss_mode;
625ba2c2 343 struct link_config link_cfg;
671b0060 344 u16 *rss;
625ba2c2
DM		 345};
346
625ba2c2
DM		 347struct dentry;
348struct work_struct;
349
350enum { /* adapter flags */
351 FULL_INIT_DONE = (1 << 0),
352 USING_MSI = (1 << 1),
353 USING_MSIX = (1 << 2),
625ba2c2 354 FW_OK = (1 << 4),
13ee15d3 355 RSS_TNLALLLOOKUP = (1 << 5),
52367a76
VP		 356 USING_SOFT_PARAMS = (1 << 6),
357 MASTER_PF = (1 << 7),
358 FW_OFLD_CONN = (1 << 9),
625ba2c2
DM		 359};
360
361struct rx_sw_desc;
362
363struct sge_fl { /* SGE free-buffer queue state */
364 unsigned int avail; /* # of available Rx buffers */
365 unsigned int pend_cred; /* new buffers since last FL DB ring */
366 unsigned int cidx; /* consumer index */
367 unsigned int pidx; /* producer index */
368 unsigned long alloc_failed; /* # of times buffer allocation failed */
369 unsigned long large_alloc_failed;
370 unsigned long starving;
371 /* RO fields */
372 unsigned int cntxt_id; /* SGE context id for the free list */
373 unsigned int size; /* capacity of free list */
374 struct rx_sw_desc *sdesc; /* address of SW Rx descriptor ring */
375 __be64 *desc; /* address of HW Rx descriptor ring */
376 dma_addr_t addr; /* bus address of HW ring start */
377};
378
379/* A packet gather list */
380struct pkt_gl {
e91b0f24 381 struct page_frag frags[MAX_SKB_FRAGS];
625ba2c2
DM		 382 void *va; /* virtual address of first byte */
383 unsigned int nfrags; /* # of fragments */
384 unsigned int tot_len; /* total length of fragments */
385};
386
387typedef int (*rspq_handler_t)(struct sge_rspq *q, const __be64 *rsp,
388 const struct pkt_gl *gl);
389
390struct sge_rspq { /* state for an SGE response queue */
391 struct napi_struct napi;
392 const __be64 *cur_desc; /* current descriptor in queue */
393 unsigned int cidx; /* consumer index */
394 u8 gen; /* current generation bit */
395 u8 intr_params; /* interrupt holdoff parameters */
396 u8 next_intr_params; /* holdoff params for next interrupt */
397 u8 pktcnt_idx; /* interrupt packet threshold */
398 u8 uld; /* ULD handling this queue */
399 u8 idx; /* queue index within its group */
400 int offset; /* offset into current Rx buffer */
401 u16 cntxt_id; /* SGE context id for the response q */
402 u16 abs_id; /* absolute SGE id for the response q */
403 __be64 *desc; /* address of HW response ring */
404 dma_addr_t phys_addr; /* physical address of the ring */
405 unsigned int iqe_len; /* entry size */
406 unsigned int size; /* capacity of response queue */
407 struct adapter *adap;
408 struct net_device *netdev; /* associated net device */
409 rspq_handler_t handler;
410};
411
412struct sge_eth_stats { /* Ethernet queue statistics */
413 unsigned long pkts; /* # of ethernet packets */
414 unsigned long lro_pkts; /* # of LRO super packets */
415 unsigned long lro_merged; /* # of wire packets merged by LRO */
416 unsigned long rx_cso; /* # of Rx checksum offloads */
417 unsigned long vlan_ex; /* # of Rx VLAN extractions */
418 unsigned long rx_drops; /* # of packets dropped due to no mem */
419};
420
421struct sge_eth_rxq { /* SW Ethernet Rx queue */
422 struct sge_rspq rspq;
423 struct sge_fl fl;
424 struct sge_eth_stats stats;
425} ____cacheline_aligned_in_smp;
426
427struct sge_ofld_stats { /* offload queue statistics */
428 unsigned long pkts; /* # of packets */
429 unsigned long imm; /* # of immediate-data packets */
430 unsigned long an; /* # of asynchronous notifications */
431 unsigned long nomem; /* # of responses deferred due to no mem */
432};
433
434struct sge_ofld_rxq { /* SW offload Rx queue */
435 struct sge_rspq rspq;
436 struct sge_fl fl;
437 struct sge_ofld_stats stats;
438} ____cacheline_aligned_in_smp;
439
440struct tx_desc {
441 __be64 flit[8];
442};
443
444struct tx_sw_desc;
445
446struct sge_txq {
447 unsigned int in_use; /* # of in-use Tx descriptors */
448 unsigned int size; /* # of descriptors */
449 unsigned int cidx; /* SW consumer index */
450 unsigned int pidx; /* producer index */
451 unsigned long stops; /* # of times q has been stopped */
452 unsigned long restarts; /* # of queue restarts */
453 unsigned int cntxt_id; /* SGE context id for the Tx q */
454 struct tx_desc *desc; /* address of HW Tx descriptor ring */
455 struct tx_sw_desc *sdesc; /* address of SW Tx descriptor ring */
456 struct sge_qstat *stat; /* queue status entry */
457 dma_addr_t phys_addr; /* physical address of the ring */
3069ee9b
VP		 458 spinlock_t db_lock;
459 int db_disabled;
460 unsigned short db_pidx;
22adfe0a 461 u64 udb;
625ba2c2
DM		 462};
463
464struct sge_eth_txq { /* state for an SGE Ethernet Tx queue */
465 struct sge_txq q;
466 struct netdev_queue *txq; /* associated netdev TX queue */
467 unsigned long tso; /* # of TSO requests */
468 unsigned long tx_cso; /* # of Tx checksum offloads */
469 unsigned long vlan_ins; /* # of Tx VLAN insertions */
470 unsigned long mapping_err; /* # of I/O MMU packet mapping errors */
471} ____cacheline_aligned_in_smp;
472
473struct sge_ofld_txq { /* state for an SGE offload Tx queue */
474 struct sge_txq q;
475 struct adapter *adap;
476 struct sk_buff_head sendq; /* list of backpressured packets */
477 struct tasklet_struct qresume_tsk; /* restarts the queue */
478 u8 full; /* the Tx ring is full */
479 unsigned long mapping_err; /* # of I/O MMU packet mapping errors */
480} ____cacheline_aligned_in_smp;
481
482struct sge_ctrl_txq { /* state for an SGE control Tx queue */
483 struct sge_txq q;
484 struct adapter *adap;
485 struct sk_buff_head sendq; /* list of backpressured packets */
486 struct tasklet_struct qresume_tsk; /* restarts the queue */
487 u8 full; /* the Tx ring is full */
488} ____cacheline_aligned_in_smp;
489
490struct sge {
491 struct sge_eth_txq ethtxq[MAX_ETH_QSETS];
492 struct sge_ofld_txq ofldtxq[MAX_OFLD_QSETS];
493 struct sge_ctrl_txq ctrlq[MAX_CTRL_QUEUES];
494
495 struct sge_eth_rxq ethrxq[MAX_ETH_QSETS];
496 struct sge_ofld_rxq ofldrxq[MAX_OFLD_QSETS];
497 struct sge_ofld_rxq rdmarxq[MAX_RDMA_QUEUES];
498 struct sge_rspq fw_evtq ____cacheline_aligned_in_smp;
499
500 struct sge_rspq intrq ____cacheline_aligned_in_smp;
501 spinlock_t intrq_lock;
502
503 u16 max_ethqsets; /* # of available Ethernet queue sets */
504 u16 ethqsets; /* # of active Ethernet queue sets */
505 u16 ethtxq_rover; /* Tx queue to clean up next */
506 u16 ofldqsets; /* # of active offload queue sets */
507 u16 rdmaqs; /* # of available RDMA Rx queues */
508 u16 ofld_rxq[MAX_OFLD_QSETS];
509 u16 rdma_rxq[NCHAN];
510 u16 timer_val[SGE_NTIMERS];
511 u8 counter_val[SGE_NCOUNTERS];
52367a76
VP		 512 u32 fl_pg_order; /* large page allocation size */
513 u32 stat_len; /* length of status page at ring end */
514 u32 pktshift; /* padding between CPL & packet data */
515 u32 fl_align; /* response queue message alignment */
516 u32 fl_starve_thres; /* Free List starvation threshold */
625ba2c2
DM		 517 unsigned int starve_thres;
518 u8 idma_state[2];
e46dab4d
DM		 519 unsigned int egr_start;
520 unsigned int ingr_start;
625ba2c2
DM		 521 void *egr_map[MAX_EGRQ]; /* qid->queue egress queue map */
522 struct sge_rspq *ingr_map[MAX_INGQ]; /* qid->queue ingress queue map */
523 DECLARE_BITMAP(starving_fl, MAX_EGRQ);
524 DECLARE_BITMAP(txq_maperr, MAX_EGRQ);
525 struct timer_list rx_timer; /* refills starving FLs */
526 struct timer_list tx_timer; /* checks Tx queues */
527};
528
529#define for_each_ethrxq(sge, i) for (i = 0; i < (sge)->ethqsets; i++)
530#define for_each_ofldrxq(sge, i) for (i = 0; i < (sge)->ofldqsets; i++)
531#define for_each_rdmarxq(sge, i) for (i = 0; i < (sge)->rdmaqs; i++)
532
533struct l2t_data;
534
2422d9a3
SR		 535#ifdef CONFIG_PCI_IOV
536
7d6727cf
SR		 537/* T4 supports SRIOV on PF0-3 and T5 on PF0-7. However, the Serial
538 * Configuration initialization for T5 only has SR-IOV functionality enabled
539 * on PF0-3 in order to simplify everything.
2422d9a3 540 */
7d6727cf 541#define NUM_OF_PF_WITH_SRIOV 4
2422d9a3
SR		 542
543#endif
544
625ba2c2
DM		 545struct adapter {
546 void __iomem *regs;
22adfe0a 547 void __iomem *bar2;
625ba2c2
DM		 548 struct pci_dev *pdev;
549 struct device *pdev_dev;
3069ee9b 550 unsigned int mbox;
060e0c75
DM		 551 unsigned int fn;
552 unsigned int flags;
2422d9a3 553 enum chip_type chip;
625ba2c2 554
625ba2c2
DM		 555 int msg_enable;
556
557 struct adapter_params params;
558 struct cxgb4_virt_res vres;
559 unsigned int swintr;
560
561 unsigned int wol;
562
563 struct {
564 unsigned short vec;
8cd18ac4 565 char desc[IFNAMSIZ + 10];
625ba2c2
DM		 566 } msix_info[MAX_INGQ + 1];
567
568 struct sge sge;
569
570 struct net_device *port[MAX_NPORTS];
571 u8 chan_map[NCHAN]; /* channel -> port map */
572
793dad94 573 u32 filter_mode;
636f9d37
VP		 574 unsigned int l2t_start;
575 unsigned int l2t_end;
625ba2c2
DM		 576 struct l2t_data *l2t;
577 void *uld_handle[CXGB4_ULD_MAX];
578 struct list_head list_node;
01bcca68 579 struct list_head rcu_node;
625ba2c2
DM		 580
581 struct tid_info tids;
582 void **tid_release_head;
583 spinlock_t tid_release_lock;
584 struct work_struct tid_release_task;
881806bc
VP		 585 struct work_struct db_full_task;
586 struct work_struct db_drop_task;
625ba2c2
DM		 587 bool tid_release_task_busy;
588
589 struct dentry *debugfs_root;
590
591 spinlock_t stats_lock;
592};
593
f2b7e78d
VP		 594/* Defined bit width of user definable filter tuples
595 */
596#define ETHTYPE_BITWIDTH 16
597#define FRAG_BITWIDTH 1
598#define MACIDX_BITWIDTH 9
599#define FCOE_BITWIDTH 1
600#define IPORT_BITWIDTH 3
601#define MATCHTYPE_BITWIDTH 3
602#define PROTO_BITWIDTH 8
603#define TOS_BITWIDTH 8
604#define PF_BITWIDTH 8
605#define VF_BITWIDTH 8
606#define IVLAN_BITWIDTH 16
607#define OVLAN_BITWIDTH 16
608
609/* Filter matching rules. These consist of a set of ingress packet field
610 * (value, mask) tuples. The associated ingress packet field matches the
611 * tuple when ((field & mask) == value). (Thus a wildcard "don't care" field
612 * rule can be constructed by specifying a tuple of (0, 0).) A filter rule
613 * matches an ingress packet when all of the individual individual field
614 * matching rules are true.
615 *
616 * Partial field masks are always valid, however, while it may be easy to
617 * understand their meanings for some fields (e.g. IP address to match a
618 * subnet), for others making sensible partial masks is less intuitive (e.g.
619 * MPS match type) ...
620 *
621 * Most of the following data structures are modeled on T4 capabilities.
622 * Drivers for earlier chips use the subsets which make sense for those chips.
623 * We really need to come up with a hardware-independent mechanism to
624 * represent hardware filter capabilities ...
625 */
626struct ch_filter_tuple {
627 /* Compressed header matching field rules. The TP_VLAN_PRI_MAP
628 * register selects which of these fields will participate in the
629 * filter match rules -- up to a maximum of 36 bits. Because
630 * TP_VLAN_PRI_MAP is a global register, all filters must use the same
631 * set of fields.
632 */
633 uint32_t ethtype:ETHTYPE_BITWIDTH; /* Ethernet type */
634 uint32_t frag:FRAG_BITWIDTH; /* IP fragmentation header */
635 uint32_t ivlan_vld:1; /* inner VLAN valid */
636 uint32_t ovlan_vld:1; /* outer VLAN valid */
637 uint32_t pfvf_vld:1; /* PF/VF valid */
638 uint32_t macidx:MACIDX_BITWIDTH; /* exact match MAC index */
639 uint32_t fcoe:FCOE_BITWIDTH; /* FCoE packet */
640 uint32_t iport:IPORT_BITWIDTH; /* ingress port */
641 uint32_t matchtype:MATCHTYPE_BITWIDTH; /* MPS match type */
642 uint32_t proto:PROTO_BITWIDTH; /* protocol type */
643 uint32_t tos:TOS_BITWIDTH; /* TOS/Traffic Type */
644 uint32_t pf:PF_BITWIDTH; /* PCI-E PF ID */
645 uint32_t vf:VF_BITWIDTH; /* PCI-E VF ID */
646 uint32_t ivlan:IVLAN_BITWIDTH; /* inner VLAN */
647 uint32_t ovlan:OVLAN_BITWIDTH; /* outer VLAN */
648
649 /* Uncompressed header matching field rules. These are always
650 * available for field rules.
651 */
652 uint8_t lip[16]; /* local IP address (IPv4 in [3:0]) */
653 uint8_t fip[16]; /* foreign IP address (IPv4 in [3:0]) */
654 uint16_t lport; /* local port */
655 uint16_t fport; /* foreign port */
656};
657
658/* A filter ioctl command.
659 */
660struct ch_filter_specification {
661 /* Administrative fields for filter.
662 */
663 uint32_t hitcnts:1; /* count filter hits in TCB */
664 uint32_t prio:1; /* filter has priority over active/server */
665
666 /* Fundamental filter typing. This is the one element of filter
667 * matching that doesn't exist as a (value, mask) tuple.
668 */
669 uint32_t type:1; /* 0 => IPv4, 1 => IPv6 */
670
671 /* Packet dispatch information. Ingress packets which match the
672 * filter rules will be dropped, passed to the host or switched back
673 * out as egress packets.
674 */
675 uint32_t action:2; /* drop, pass, switch */
676
677 uint32_t rpttid:1; /* report TID in RSS hash field */
678
679 uint32_t dirsteer:1; /* 0 => RSS, 1 => steer to iq */
680 uint32_t iq:10; /* ingress queue */
681
682 uint32_t maskhash:1; /* dirsteer=0: store RSS hash in TCB */
683 uint32_t dirsteerhash:1;/* dirsteer=1: 0 => TCB contains RSS hash */
684 /* 1 => TCB contains IQ ID */
685
686 /* Switch proxy/rewrite fields. An ingress packet which matches a
687 * filter with "switch" set will be looped back out as an egress
688 * packet -- potentially with some Ethernet header rewriting.
689 */
690 uint32_t eport:2; /* egress port to switch packet out */
691 uint32_t newdmac:1; /* rewrite destination MAC address */
692 uint32_t newsmac:1; /* rewrite source MAC address */
693 uint32_t newvlan:2; /* rewrite VLAN Tag */
694 uint8_t dmac[ETH_ALEN]; /* new destination MAC address */
695 uint8_t smac[ETH_ALEN]; /* new source MAC address */
696 uint16_t vlan; /* VLAN Tag to insert */
697
698 /* Filter rule value/mask pairs.
699 */
700 struct ch_filter_tuple val;
701 struct ch_filter_tuple mask;
702};
703
704enum {
705 FILTER_PASS = 0, /* default */
706 FILTER_DROP,
707 FILTER_SWITCH
708};
709
710enum {
711 VLAN_NOCHANGE = 0, /* default */
712 VLAN_REMOVE,
713 VLAN_INSERT,
714 VLAN_REWRITE
715};
716
2422d9a3
SR		 717static inline int is_t5(enum chip_type chip)
718{
d14807dd 719 return CHELSIO_CHIP_VERSION(chip) == CHELSIO_T5;
2422d9a3
SR		 720}
721
722static inline int is_t4(enum chip_type chip)
723{
d14807dd 724 return CHELSIO_CHIP_VERSION(chip) == CHELSIO_T4;
2422d9a3
SR		 725}
726
625ba2c2
DM		 727static inline u32 t4_read_reg(struct adapter *adap, u32 reg_addr)
728{
729 return readl(adap->regs + reg_addr);
730}
731
732static inline void t4_write_reg(struct adapter *adap, u32 reg_addr, u32 val)
733{
734 writel(val, adap->regs + reg_addr);
735}
736
737#ifndef readq
738static inline u64 readq(const volatile void __iomem *addr)
739{
740 return readl(addr) + ((u64)readl(addr + 4) << 32);
741}
742
743static inline void writeq(u64 val, volatile void __iomem *addr)
744{
745 writel(val, addr);
746 writel(val >> 32, addr + 4);
747}
748#endif
749
750static inline u64 t4_read_reg64(struct adapter *adap, u32 reg_addr)
751{
752 return readq(adap->regs + reg_addr);
753}
754
755static inline void t4_write_reg64(struct adapter *adap, u32 reg_addr, u64 val)
756{
757 writeq(val, adap->regs + reg_addr);
758}
759
760/**
761 * netdev2pinfo - return the port_info structure associated with a net_device
762 * @dev: the netdev
763 *
764 * Return the struct port_info associated with a net_device
765 */
766static inline struct port_info *netdev2pinfo(const struct net_device *dev)
767{
768 return netdev_priv(dev);
769}
770
771/**
772 * adap2pinfo - return the port_info of a port
773 * @adap: the adapter
774 * @idx: the port index
775 *
776 * Return the port_info structure for the port of the given index.
777 */
778static inline struct port_info *adap2pinfo(struct adapter *adap, int idx)
779{
780 return netdev_priv(adap->port[idx]);
781}
782
783/**
784 * netdev2adap - return the adapter structure associated with a net_device
785 * @dev: the netdev
786 *
787 * Return the struct adapter associated with a net_device
788 */
789static inline struct adapter *netdev2adap(const struct net_device *dev)
790{
791 return netdev2pinfo(dev)->adapter;
792}
793
794void t4_os_portmod_changed(const struct adapter *adap, int port_id);
795void t4_os_link_changed(struct adapter *adap, int port_id, int link_stat);
796
797void *t4_alloc_mem(size_t size);
625ba2c2
DM		 798
799void t4_free_sge_resources(struct adapter *adap);
800irq_handler_t t4_intr_handler(struct adapter *adap);
801netdev_tx_t t4_eth_xmit(struct sk_buff *skb, struct net_device *dev);
802int t4_ethrx_handler(struct sge_rspq *q, const __be64 *rsp,
803 const struct pkt_gl *gl);
804int t4_mgmt_tx(struct adapter *adap, struct sk_buff *skb);
805int t4_ofld_send(struct adapter *adap, struct sk_buff *skb);
806int t4_sge_alloc_rxq(struct adapter *adap, struct sge_rspq *iq, bool fwevtq,
807 struct net_device *dev, int intr_idx,
808 struct sge_fl *fl, rspq_handler_t hnd);
809int t4_sge_alloc_eth_txq(struct adapter *adap, struct sge_eth_txq *txq,
810 struct net_device *dev, struct netdev_queue *netdevq,
811 unsigned int iqid);
812int t4_sge_alloc_ctrl_txq(struct adapter *adap, struct sge_ctrl_txq *txq,
813 struct net_device *dev, unsigned int iqid,
814 unsigned int cmplqid);
815int t4_sge_alloc_ofld_txq(struct adapter *adap, struct sge_ofld_txq *txq,
816 struct net_device *dev, unsigned int iqid);
817irqreturn_t t4_sge_intr_msix(int irq, void *cookie);
52367a76 818int t4_sge_init(struct adapter *adap);
625ba2c2
DM		 819void t4_sge_start(struct adapter *adap);
820void t4_sge_stop(struct adapter *adap);
3069ee9b 821extern int dbfifo_int_thresh;
625ba2c2
DM		 822
823#define for_each_port(adapter, iter) \
824 for (iter = 0; iter < (adapter)->params.nports; ++iter)
825
9a4da2cd
VP		 826static inline int is_bypass(struct adapter *adap)
827{
828 return adap->params.bypass;
829}
830
831static inline int is_bypass_device(int device)
832{
833 /* this should be set based upon device capabilities */
834 switch (device) {
835 case 0x440b:
836 case 0x440c:
837 return 1;
838 default:
839 return 0;
840 }
841}
842
625ba2c2
DM		 843static inline unsigned int core_ticks_per_usec(const struct adapter *adap)
844{
845 return adap->params.vpd.cclk / 1000;
846}
847
848static inline unsigned int us_to_core_ticks(const struct adapter *adap,
849 unsigned int us)
850{
851 return (us * adap->params.vpd.cclk) / 1000;
852}
853
52367a76
VP		 854static inline unsigned int core_ticks_to_us(const struct adapter *adapter,
855 unsigned int ticks)
856{
857 /* add Core Clock / 2 to round ticks to nearest uS */
858 return ((ticks * 1000 + adapter->params.vpd.cclk/2) /
859 adapter->params.vpd.cclk);
860}
861
625ba2c2
DM		 862void t4_set_reg_field(struct adapter *adap, unsigned int addr, u32 mask,
863 u32 val);
864
865int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size,
866 void *rpl, bool sleep_ok);
867
868static inline int t4_wr_mbox(struct adapter *adap, int mbox, const void *cmd,
869 int size, void *rpl)
870{
871 return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, true);
872}
873
874static inline int t4_wr_mbox_ns(struct adapter *adap, int mbox, const void *cmd,
875 int size, void *rpl)
876{
877 return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, false);
878}
879
13ee15d3
VP		 880void t4_write_indirect(struct adapter *adap, unsigned int addr_reg,
881 unsigned int data_reg, const u32 *vals,
882 unsigned int nregs, unsigned int start_idx);
f2b7e78d
VP		 883void t4_read_indirect(struct adapter *adap, unsigned int addr_reg,
884 unsigned int data_reg, u32 *vals, unsigned int nregs,
885 unsigned int start_idx);
886
887struct fw_filter_wr;
888
625ba2c2
DM		 889void t4_intr_enable(struct adapter *adapter);
890void t4_intr_disable(struct adapter *adapter);
625ba2c2
DM		 891int t4_slow_intr_handler(struct adapter *adapter);
892
204dc3c0 893int t4_wait_dev_ready(struct adapter *adap);
625ba2c2
DM		 894int t4_link_start(struct adapter *adap, unsigned int mbox, unsigned int port,
895 struct link_config *lc);
896int t4_restart_aneg(struct adapter *adap, unsigned int mbox, unsigned int port);
5afc8b84
VP		 897int t4_memory_write(struct adapter *adap, int mtype, u32 addr, u32 len,
898 __be32 *buf);
625ba2c2 899int t4_seeprom_wp(struct adapter *adapter, bool enable);
636f9d37 900int get_vpd_params(struct adapter *adapter, struct vpd_params *p);
625ba2c2 901int t4_load_fw(struct adapter *adapter, const u8 *fw_data, unsigned int size);
636f9d37 902unsigned int t4_flash_cfg_addr(struct adapter *adapter);
404d9e3f 903int t4_load_cfg(struct adapter *adapter, const u8 *cfg_data, unsigned int size);
625ba2c2
DM		 904int t4_check_fw_version(struct adapter *adapter);
905int t4_prep_adapter(struct adapter *adapter);
906int t4_port_init(struct adapter *adap, int mbox, int pf, int vf);
907void t4_fatal_err(struct adapter *adapter);
625ba2c2
DM		 908int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid,
909 int start, int n, const u16 *rspq, unsigned int nrspq);
910int t4_config_glbl_rss(struct adapter *adapter, int mbox, unsigned int mode,
911 unsigned int flags);
19dd37ba
SR		 912int t4_mc_read(struct adapter *adap, int idx, u32 addr, __be32 *data,
913 u64 *parity);
625ba2c2
DM		 914int t4_edc_read(struct adapter *adap, int idx, u32 addr, __be32 *data,
915 u64 *parity);
916
917void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p);
625ba2c2 918void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log);
636f9d37
VP		 919void t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr,
920 unsigned int mask, unsigned int val);
625ba2c2
DM		 921void t4_tp_get_tcp_stats(struct adapter *adap, struct tp_tcp_stats *v4,
922 struct tp_tcp_stats *v6);
923void t4_load_mtus(struct adapter *adap, const unsigned short *mtus,
924 const unsigned short *alpha, const unsigned short *beta);
925
f2b7e78d
VP		 926void t4_mk_filtdelwr(unsigned int ftid, struct fw_filter_wr *wr, int qid);
927
625ba2c2
DM		 928void t4_wol_magic_enable(struct adapter *adap, unsigned int port,
929 const u8 *addr);
930int t4_wol_pat_enable(struct adapter *adap, unsigned int port, unsigned int map,
931 u64 mask0, u64 mask1, unsigned int crc, bool enable);
932
933int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox,
934 enum dev_master master, enum dev_state *state);
935int t4_fw_bye(struct adapter *adap, unsigned int mbox);
936int t4_early_init(struct adapter *adap, unsigned int mbox);
937int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset);
26f7cbc0
VP		 938int t4_fw_halt(struct adapter *adap, unsigned int mbox, int force);
939int t4_fw_restart(struct adapter *adap, unsigned int mbox, int reset);
940int t4_fw_upgrade(struct adapter *adap, unsigned int mbox,
941 const u8 *fw_data, unsigned int size, int force);
636f9d37
VP		 942int t4_fw_config_file(struct adapter *adap, unsigned int mbox,
943 unsigned int mtype, unsigned int maddr,
944 u32 *finiver, u32 *finicsum, u32 *cfcsum);
945int t4_fixup_host_params(struct adapter *adap, unsigned int page_size,
946 unsigned int cache_line_size);
947int t4_fw_initialize(struct adapter *adap, unsigned int mbox);
625ba2c2
DM		 948int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
949 unsigned int vf, unsigned int nparams, const u32 *params,
950 u32 *val);
951int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
952 unsigned int vf, unsigned int nparams, const u32 *params,
953 const u32 *val);
954int t4_cfg_pfvf(struct adapter *adap, unsigned int mbox, unsigned int pf,
955 unsigned int vf, unsigned int txq, unsigned int txq_eth_ctrl,
956 unsigned int rxqi, unsigned int rxq, unsigned int tc,
957 unsigned int vi, unsigned int cmask, unsigned int pmask,
958 unsigned int nexact, unsigned int rcaps, unsigned int wxcaps);
959int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port,
960 unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac,
961 unsigned int *rss_size);
625ba2c2 962int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid,
f8f5aafa
DM		 963 int mtu, int promisc, int all_multi, int bcast, int vlanex,
964 bool sleep_ok);
625ba2c2
DM		 965int t4_alloc_mac_filt(struct adapter *adap, unsigned int mbox,
966 unsigned int viid, bool free, unsigned int naddr,
967 const u8 **addr, u16 *idx, u64 *hash, bool sleep_ok);
968int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid,
969 int idx, const u8 *addr, bool persist, bool add_smt);
970int t4_set_addr_hash(struct adapter *adap, unsigned int mbox, unsigned int viid,
971 bool ucast, u64 vec, bool sleep_ok);
972int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid,
973 bool rx_en, bool tx_en);
974int t4_identify_port(struct adapter *adap, unsigned int mbox, unsigned int viid,
975 unsigned int nblinks);
976int t4_mdio_rd(struct adapter *adap, unsigned int mbox, unsigned int phy_addr,
977 unsigned int mmd, unsigned int reg, u16 *valp);
978int t4_mdio_wr(struct adapter *adap, unsigned int mbox, unsigned int phy_addr,
979 unsigned int mmd, unsigned int reg, u16 val);
625ba2c2
DM		 980int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
981 unsigned int vf, unsigned int iqtype, unsigned int iqid,
982 unsigned int fl0id, unsigned int fl1id);
983int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
984 unsigned int vf, unsigned int eqid);
985int t4_ctrl_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
986 unsigned int vf, unsigned int eqid);
987int t4_ofld_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
988 unsigned int vf, unsigned int eqid);
989int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl);
881806bc
VP		 990void t4_db_full(struct adapter *adapter);
991void t4_db_dropped(struct adapter *adapter);
8caa1e84
VP		 992int t4_mem_win_read_len(struct adapter *adap, u32 addr, __be32 *data, int len);
993int t4_fwaddrspace_write(struct adapter *adap, unsigned int mbox,
994 u32 addr, u32 val);
625ba2c2 995#endif /* __CXGB4_H__ */
Linux kernel - Deliverables
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