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cxgb4 : Add DCBx support codebase and dcbnl_ops
[deliverable/linux.git] / drivers / net / ethernet / chelsio / cxgb4 / cxgb4.h
CommitLineData
625ba2c2
DM		 1/*
2 * This file is part of the Chelsio T4 Ethernet driver for Linux.
3 *
4 * Copyright (c) 2003-2010 Chelsio Communications, Inc. All rights reserved.
5 *
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
11 *
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
14 * conditions are met:
15 *
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
18 * disclaimer.
19 *
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
24 *
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
32 * SOFTWARE.
33 */
34
35#ifndef __CXGB4_H__
36#define __CXGB4_H__
37
dca4faeb
VP		 38#include "t4_hw.h"
39
625ba2c2
DM		 40#include <linux/bitops.h>
41#include <linux/cache.h>
42#include <linux/interrupt.h>
43#include <linux/list.h>
44#include <linux/netdevice.h>
45#include <linux/pci.h>
46#include <linux/spinlock.h>
47#include <linux/timer.h>
c0b8b992 48#include <linux/vmalloc.h>
625ba2c2
DM		 49#include <asm/io.h>
50#include "cxgb4_uld.h"
625ba2c2 51
16e47624 52#define T4FW_VERSION_MAJOR 0x01
451cd14e
HS		 53#define T4FW_VERSION_MINOR 0x09
54#define T4FW_VERSION_MICRO 0x17
16e47624 55#define T4FW_VERSION_BUILD 0x00
625ba2c2 56
16e47624 57#define T5FW_VERSION_MAJOR 0x01
451cd14e
HS		 58#define T5FW_VERSION_MINOR 0x09
59#define T5FW_VERSION_MICRO 0x17
16e47624 60#define T5FW_VERSION_BUILD 0x00
2422d9a3 61
3069ee9b
VP		 62#define CH_WARN(adap, fmt, ...) dev_warn(adap->pdev_dev, fmt, ## __VA_ARGS__)
63
625ba2c2
DM		 64enum {
65 MAX_NPORTS = 4, /* max # of ports */
47d54d65 66 SERNUM_LEN = 24, /* Serial # length */
625ba2c2
DM		 67 EC_LEN = 16, /* E/C length */
68 ID_LEN = 16, /* ID length */
a94cd705 69 PN_LEN = 16, /* Part Number length */
625ba2c2
DM		 70};
71
72enum {
73 MEM_EDC0,
74 MEM_EDC1,
2422d9a3
SR		 75 MEM_MC,
76 MEM_MC0 = MEM_MC,
77 MEM_MC1
625ba2c2
DM		 78};
79
3069ee9b 80enum {
3eb4afbf
VP		 81 MEMWIN0_APERTURE = 2048,
82 MEMWIN0_BASE = 0x1b800,
3069ee9b
VP		 83 MEMWIN1_APERTURE = 32768,
84 MEMWIN1_BASE = 0x28000,
2422d9a3 85 MEMWIN1_BASE_T5 = 0x52000,
3eb4afbf
VP		 86 MEMWIN2_APERTURE = 65536,
87 MEMWIN2_BASE = 0x30000,
2422d9a3 88 MEMWIN2_BASE_T5 = 0x54000,
3069ee9b
VP		 89};
90
625ba2c2
DM		 91enum dev_master {
92 MASTER_CANT,
93 MASTER_MAY,
94 MASTER_MUST
95};
96
97enum dev_state {
98 DEV_STATE_UNINIT,
99 DEV_STATE_INIT,
100 DEV_STATE_ERR
101};
102
103enum {
104 PAUSE_RX = 1 << 0,
105 PAUSE_TX = 1 << 1,
106 PAUSE_AUTONEG = 1 << 2
107};
108
109struct port_stats {
110 u64 tx_octets; /* total # of octets in good frames */
111 u64 tx_frames; /* all good frames */
112 u64 tx_bcast_frames; /* all broadcast frames */
113 u64 tx_mcast_frames; /* all multicast frames */
114 u64 tx_ucast_frames; /* all unicast frames */
115 u64 tx_error_frames; /* all error frames */
116
117 u64 tx_frames_64; /* # of Tx frames in a particular range */
118 u64 tx_frames_65_127;
119 u64 tx_frames_128_255;
120 u64 tx_frames_256_511;
121 u64 tx_frames_512_1023;
122 u64 tx_frames_1024_1518;
123 u64 tx_frames_1519_max;
124
125 u64 tx_drop; /* # of dropped Tx frames */
126 u64 tx_pause; /* # of transmitted pause frames */
127 u64 tx_ppp0; /* # of transmitted PPP prio 0 frames */
128 u64 tx_ppp1; /* # of transmitted PPP prio 1 frames */
129 u64 tx_ppp2; /* # of transmitted PPP prio 2 frames */
130 u64 tx_ppp3; /* # of transmitted PPP prio 3 frames */
131 u64 tx_ppp4; /* # of transmitted PPP prio 4 frames */
132 u64 tx_ppp5; /* # of transmitted PPP prio 5 frames */
133 u64 tx_ppp6; /* # of transmitted PPP prio 6 frames */
134 u64 tx_ppp7; /* # of transmitted PPP prio 7 frames */
135
136 u64 rx_octets; /* total # of octets in good frames */
137 u64 rx_frames; /* all good frames */
138 u64 rx_bcast_frames; /* all broadcast frames */
139 u64 rx_mcast_frames; /* all multicast frames */
140 u64 rx_ucast_frames; /* all unicast frames */
141 u64 rx_too_long; /* # of frames exceeding MTU */
142 u64 rx_jabber; /* # of jabber frames */
143 u64 rx_fcs_err; /* # of received frames with bad FCS */
144 u64 rx_len_err; /* # of received frames with length error */
145 u64 rx_symbol_err; /* symbol errors */
146 u64 rx_runt; /* # of short frames */
147
148 u64 rx_frames_64; /* # of Rx frames in a particular range */
149 u64 rx_frames_65_127;
150 u64 rx_frames_128_255;
151 u64 rx_frames_256_511;
152 u64 rx_frames_512_1023;
153 u64 rx_frames_1024_1518;
154 u64 rx_frames_1519_max;
155
156 u64 rx_pause; /* # of received pause frames */
157 u64 rx_ppp0; /* # of received PPP prio 0 frames */
158 u64 rx_ppp1; /* # of received PPP prio 1 frames */
159 u64 rx_ppp2; /* # of received PPP prio 2 frames */
160 u64 rx_ppp3; /* # of received PPP prio 3 frames */
161 u64 rx_ppp4; /* # of received PPP prio 4 frames */
162 u64 rx_ppp5; /* # of received PPP prio 5 frames */
163 u64 rx_ppp6; /* # of received PPP prio 6 frames */
164 u64 rx_ppp7; /* # of received PPP prio 7 frames */
165
166 u64 rx_ovflow0; /* drops due to buffer-group 0 overflows */
167 u64 rx_ovflow1; /* drops due to buffer-group 1 overflows */
168 u64 rx_ovflow2; /* drops due to buffer-group 2 overflows */
169 u64 rx_ovflow3; /* drops due to buffer-group 3 overflows */
170 u64 rx_trunc0; /* buffer-group 0 truncated packets */
171 u64 rx_trunc1; /* buffer-group 1 truncated packets */
172 u64 rx_trunc2; /* buffer-group 2 truncated packets */
173 u64 rx_trunc3; /* buffer-group 3 truncated packets */
174};
175
176struct lb_port_stats {
177 u64 octets;
178 u64 frames;
179 u64 bcast_frames;
180 u64 mcast_frames;
181 u64 ucast_frames;
182 u64 error_frames;
183
184 u64 frames_64;
185 u64 frames_65_127;
186 u64 frames_128_255;
187 u64 frames_256_511;
188 u64 frames_512_1023;
189 u64 frames_1024_1518;
190 u64 frames_1519_max;
191
192 u64 drop;
193
194 u64 ovflow0;
195 u64 ovflow1;
196 u64 ovflow2;
197 u64 ovflow3;
198 u64 trunc0;
199 u64 trunc1;
200 u64 trunc2;
201 u64 trunc3;
202};
203
204struct tp_tcp_stats {
205 u32 tcpOutRsts;
206 u64 tcpInSegs;
207 u64 tcpOutSegs;
208 u64 tcpRetransSegs;
209};
210
211struct tp_err_stats {
212 u32 macInErrs[4];
213 u32 hdrInErrs[4];
214 u32 tcpInErrs[4];
215 u32 tnlCongDrops[4];
216 u32 ofldChanDrops[4];
217 u32 tnlTxDrops[4];
218 u32 ofldVlanDrops[4];
219 u32 tcp6InErrs[4];
220 u32 ofldNoNeigh;
221 u32 ofldCongDefer;
222};
223
224struct tp_params {
225 unsigned int ntxchan; /* # of Tx channels */
226 unsigned int tre; /* log2 of core clocks per TP tick */
dca4faeb
VP		 227 unsigned short tx_modq_map; /* TX modulation scheduler queue to */
228 /* channel map */
636f9d37
VP		 229
230 uint32_t dack_re; /* DACK timer resolution */
231 unsigned short tx_modq[NCHAN]; /* channel to modulation queue map */
dcf7b6f5
KS		 232
233 u32 vlan_pri_map; /* cached TP_VLAN_PRI_MAP */
234 u32 ingress_config; /* cached TP_INGRESS_CONFIG */
235
236 /* TP_VLAN_PRI_MAP Compressed Filter Tuple field offsets. This is a
237 * subset of the set of fields which may be present in the Compressed
238 * Filter Tuple portion of filters and TCP TCB connections. The
239 * fields which are present are controlled by the TP_VLAN_PRI_MAP.
240 * Since a variable number of fields may or may not be present, their
241 * shifted field positions within the Compressed Filter Tuple may
242 * vary, or not even be present if the field isn't selected in
243 * TP_VLAN_PRI_MAP. Since some of these fields are needed in various
244 * places we store their offsets here, or a -1 if the field isn't
245 * present.
246 */
247 int vlan_shift;
248 int vnic_shift;
249 int port_shift;
250 int protocol_shift;
625ba2c2
DM		 251};
252
253struct vpd_params {
254 unsigned int cclk;
255 u8 ec[EC_LEN + 1];
256 u8 sn[SERNUM_LEN + 1];
257 u8 id[ID_LEN + 1];
a94cd705 258 u8 pn[PN_LEN + 1];
625ba2c2
DM		 259};
260
261struct pci_params {
262 unsigned char speed;
263 unsigned char width;
264};
265
d14807dd
HS		 266#define CHELSIO_CHIP_CODE(version, revision) (((version) << 4) | (revision))
267#define CHELSIO_CHIP_FPGA 0x100
268#define CHELSIO_CHIP_VERSION(code) (((code) >> 4) & 0xf)
269#define CHELSIO_CHIP_RELEASE(code) ((code) & 0xf)
270
271#define CHELSIO_T4 0x4
272#define CHELSIO_T5 0x5
273
274enum chip_type {
275 T4_A1 = CHELSIO_CHIP_CODE(CHELSIO_T4, 1),
276 T4_A2 = CHELSIO_CHIP_CODE(CHELSIO_T4, 2),
277 T4_FIRST_REV = T4_A1,
278 T4_LAST_REV = T4_A2,
279
280 T5_A0 = CHELSIO_CHIP_CODE(CHELSIO_T5, 0),
281 T5_A1 = CHELSIO_CHIP_CODE(CHELSIO_T5, 1),
282 T5_FIRST_REV = T5_A0,
283 T5_LAST_REV = T5_A1,
284};
285
625ba2c2
DM		 286struct adapter_params {
287 struct tp_params tp;
288 struct vpd_params vpd;
289 struct pci_params pci;
290
900a6596
DM		 291 unsigned int sf_size; /* serial flash size in bytes */
292 unsigned int sf_nsec; /* # of flash sectors */
293 unsigned int sf_fw_start; /* start of FW image in flash */
294
625ba2c2
DM		 295 unsigned int fw_vers;
296 unsigned int tp_vers;
297 u8 api_vers[7];
298
299 unsigned short mtus[NMTUS];
300 unsigned short a_wnd[NCCTRL_WIN];
301 unsigned short b_wnd[NCCTRL_WIN];
302
303 unsigned char nports; /* # of ethernet ports */
304 unsigned char portvec;
d14807dd 305 enum chip_type chip; /* chip code */
625ba2c2
DM		 306 unsigned char offload;
307
9a4da2cd
VP		 308 unsigned char bypass;
309
625ba2c2 310 unsigned int ofldq_wr_cred;
1ac0f095 311 bool ulptx_memwrite_dsgl; /* use of T5 DSGL allowed */
625ba2c2
DM		 312};
313
16e47624
HS		 314#include "t4fw_api.h"
315
316#define FW_VERSION(chip) ( \
317 FW_HDR_FW_VER_MAJOR_GET(chip##FW_VERSION_MAJOR) | \
318 FW_HDR_FW_VER_MINOR_GET(chip##FW_VERSION_MINOR) | \
319 FW_HDR_FW_VER_MICRO_GET(chip##FW_VERSION_MICRO) | \
320 FW_HDR_FW_VER_BUILD_GET(chip##FW_VERSION_BUILD))
321#define FW_INTFVER(chip, intf) (FW_HDR_INTFVER_##intf)
322
323struct fw_info {
324 u8 chip;
325 char *fs_name;
326 char *fw_mod_name;
327 struct fw_hdr fw_hdr;
328};
329
330
625ba2c2
DM		 331struct trace_params {
332 u32 data[TRACE_LEN / 4];
333 u32 mask[TRACE_LEN / 4];
334 unsigned short snap_len;
335 unsigned short min_len;
336 unsigned char skip_ofst;
337 unsigned char skip_len;
338 unsigned char invert;
339 unsigned char port;
340};
341
342struct link_config {
343 unsigned short supported; /* link capabilities */
344 unsigned short advertising; /* advertised capabilities */
345 unsigned short requested_speed; /* speed user has requested */
346 unsigned short speed; /* actual link speed */
347 unsigned char requested_fc; /* flow control user has requested */
348 unsigned char fc; /* actual link flow control */
349 unsigned char autoneg; /* autonegotiating? */
350 unsigned char link_ok; /* link up? */
351};
352
353#define FW_LEN16(fw_struct) FW_CMD_LEN16(sizeof(fw_struct) / 16)
354
355enum {
356 MAX_ETH_QSETS = 32, /* # of Ethernet Tx/Rx queue sets */
357 MAX_OFLD_QSETS = 16, /* # of offload Tx/Rx queue sets */
358 MAX_CTRL_QUEUES = NCHAN, /* # of control Tx queues */
359 MAX_RDMA_QUEUES = NCHAN, /* # of streaming RDMA Rx queues */
cf38be6d
HS		 360 MAX_RDMA_CIQS = NCHAN, /* # of RDMA concentrator IQs */
361 MAX_ISCSI_QUEUES = NCHAN, /* # of streaming iSCSI Rx queues */
625ba2c2
DM		 362};
363
364enum {
cf38be6d
HS		 365 INGQ_EXTRAS = 2, /* firmware event queue and */
366 /* forwarded interrupts */
367 MAX_EGRQ = MAX_ETH_QSETS*2 + MAX_OFLD_QSETS*2
368 + MAX_CTRL_QUEUES + MAX_RDMA_QUEUES + MAX_ISCSI_QUEUES,
369 MAX_INGQ = MAX_ETH_QSETS + MAX_OFLD_QSETS + MAX_RDMA_QUEUES
370 + MAX_RDMA_CIQS + MAX_ISCSI_QUEUES + INGQ_EXTRAS,
625ba2c2
DM		 371};
372
373struct adapter;
625ba2c2
DM		 374struct sge_rspq;
375
376struct port_info {
377 struct adapter *adapter;
625ba2c2
DM		 378 u16 viid;
379 s16 xact_addr_filt; /* index of exact MAC address filter */
380 u16 rss_size; /* size of VI's RSS table slice */
381 s8 mdio_addr;
382 u8 port_type;
383 u8 mod_type;
384 u8 port_id;
385 u8 tx_chan;
386 u8 lport; /* associated offload logical port */
625ba2c2
DM		 387 u8 nqsets; /* # of qsets */
388 u8 first_qset; /* index of first qset */
f796564a 389 u8 rss_mode;
625ba2c2 390 struct link_config link_cfg;
671b0060 391 u16 *rss;
625ba2c2
DM		 392};
393
625ba2c2
DM		 394struct dentry;
395struct work_struct;
396
397enum { /* adapter flags */
398 FULL_INIT_DONE = (1 << 0),
144be3d9
GS		 399 DEV_ENABLED = (1 << 1),
400 USING_MSI = (1 << 2),
401 USING_MSIX = (1 << 3),
625ba2c2 402 FW_OK = (1 << 4),
13ee15d3 403 RSS_TNLALLLOOKUP = (1 << 5),
52367a76
VP		 404 USING_SOFT_PARAMS = (1 << 6),
405 MASTER_PF = (1 << 7),
406 FW_OFLD_CONN = (1 << 9),
625ba2c2
DM		 407};
408
409struct rx_sw_desc;
410
411struct sge_fl { /* SGE free-buffer queue state */
412 unsigned int avail; /* # of available Rx buffers */
413 unsigned int pend_cred; /* new buffers since last FL DB ring */
414 unsigned int cidx; /* consumer index */
415 unsigned int pidx; /* producer index */
416 unsigned long alloc_failed; /* # of times buffer allocation failed */
417 unsigned long large_alloc_failed;
418 unsigned long starving;
419 /* RO fields */
420 unsigned int cntxt_id; /* SGE context id for the free list */
421 unsigned int size; /* capacity of free list */
422 struct rx_sw_desc *sdesc; /* address of SW Rx descriptor ring */
423 __be64 *desc; /* address of HW Rx descriptor ring */
424 dma_addr_t addr; /* bus address of HW ring start */
425};
426
427/* A packet gather list */
428struct pkt_gl {
e91b0f24 429 struct page_frag frags[MAX_SKB_FRAGS];
625ba2c2
DM		 430 void *va; /* virtual address of first byte */
431 unsigned int nfrags; /* # of fragments */
432 unsigned int tot_len; /* total length of fragments */
433};
434
435typedef int (*rspq_handler_t)(struct sge_rspq *q, const __be64 *rsp,
436 const struct pkt_gl *gl);
437
438struct sge_rspq { /* state for an SGE response queue */
439 struct napi_struct napi;
440 const __be64 *cur_desc; /* current descriptor in queue */
441 unsigned int cidx; /* consumer index */
442 u8 gen; /* current generation bit */
443 u8 intr_params; /* interrupt holdoff parameters */
444 u8 next_intr_params; /* holdoff params for next interrupt */
445 u8 pktcnt_idx; /* interrupt packet threshold */
446 u8 uld; /* ULD handling this queue */
447 u8 idx; /* queue index within its group */
448 int offset; /* offset into current Rx buffer */
449 u16 cntxt_id; /* SGE context id for the response q */
450 u16 abs_id; /* absolute SGE id for the response q */
451 __be64 *desc; /* address of HW response ring */
452 dma_addr_t phys_addr; /* physical address of the ring */
453 unsigned int iqe_len; /* entry size */
454 unsigned int size; /* capacity of response queue */
455 struct adapter *adap;
456 struct net_device *netdev; /* associated net device */
457 rspq_handler_t handler;
458};
459
460struct sge_eth_stats { /* Ethernet queue statistics */
461 unsigned long pkts; /* # of ethernet packets */
462 unsigned long lro_pkts; /* # of LRO super packets */
463 unsigned long lro_merged; /* # of wire packets merged by LRO */
464 unsigned long rx_cso; /* # of Rx checksum offloads */
465 unsigned long vlan_ex; /* # of Rx VLAN extractions */
466 unsigned long rx_drops; /* # of packets dropped due to no mem */
467};
468
469struct sge_eth_rxq { /* SW Ethernet Rx queue */
470 struct sge_rspq rspq;
471 struct sge_fl fl;
472 struct sge_eth_stats stats;
473} ____cacheline_aligned_in_smp;
474
475struct sge_ofld_stats { /* offload queue statistics */
476 unsigned long pkts; /* # of packets */
477 unsigned long imm; /* # of immediate-data packets */
478 unsigned long an; /* # of asynchronous notifications */
479 unsigned long nomem; /* # of responses deferred due to no mem */
480};
481
482struct sge_ofld_rxq { /* SW offload Rx queue */
483 struct sge_rspq rspq;
484 struct sge_fl fl;
485 struct sge_ofld_stats stats;
486} ____cacheline_aligned_in_smp;
487
488struct tx_desc {
489 __be64 flit[8];
490};
491
492struct tx_sw_desc;
493
494struct sge_txq {
495 unsigned int in_use; /* # of in-use Tx descriptors */
496 unsigned int size; /* # of descriptors */
497 unsigned int cidx; /* SW consumer index */
498 unsigned int pidx; /* producer index */
499 unsigned long stops; /* # of times q has been stopped */
500 unsigned long restarts; /* # of queue restarts */
501 unsigned int cntxt_id; /* SGE context id for the Tx q */
502 struct tx_desc *desc; /* address of HW Tx descriptor ring */
503 struct tx_sw_desc *sdesc; /* address of SW Tx descriptor ring */
504 struct sge_qstat *stat; /* queue status entry */
505 dma_addr_t phys_addr; /* physical address of the ring */
3069ee9b
VP		 506 spinlock_t db_lock;
507 int db_disabled;
508 unsigned short db_pidx;
05eb2389 509 unsigned short db_pidx_inc;
22adfe0a 510 u64 udb;
625ba2c2
DM		 511};
512
513struct sge_eth_txq { /* state for an SGE Ethernet Tx queue */
514 struct sge_txq q;
515 struct netdev_queue *txq; /* associated netdev TX queue */
516 unsigned long tso; /* # of TSO requests */
517 unsigned long tx_cso; /* # of Tx checksum offloads */
518 unsigned long vlan_ins; /* # of Tx VLAN insertions */
519 unsigned long mapping_err; /* # of I/O MMU packet mapping errors */
520} ____cacheline_aligned_in_smp;
521
522struct sge_ofld_txq { /* state for an SGE offload Tx queue */
523 struct sge_txq q;
524 struct adapter *adap;
525 struct sk_buff_head sendq; /* list of backpressured packets */
526 struct tasklet_struct qresume_tsk; /* restarts the queue */
527 u8 full; /* the Tx ring is full */
528 unsigned long mapping_err; /* # of I/O MMU packet mapping errors */
529} ____cacheline_aligned_in_smp;
530
531struct sge_ctrl_txq { /* state for an SGE control Tx queue */
532 struct sge_txq q;
533 struct adapter *adap;
534 struct sk_buff_head sendq; /* list of backpressured packets */
535 struct tasklet_struct qresume_tsk; /* restarts the queue */
536 u8 full; /* the Tx ring is full */
537} ____cacheline_aligned_in_smp;
538
539struct sge {
540 struct sge_eth_txq ethtxq[MAX_ETH_QSETS];
541 struct sge_ofld_txq ofldtxq[MAX_OFLD_QSETS];
542 struct sge_ctrl_txq ctrlq[MAX_CTRL_QUEUES];
543
544 struct sge_eth_rxq ethrxq[MAX_ETH_QSETS];
545 struct sge_ofld_rxq ofldrxq[MAX_OFLD_QSETS];
546 struct sge_ofld_rxq rdmarxq[MAX_RDMA_QUEUES];
cf38be6d 547 struct sge_ofld_rxq rdmaciq[MAX_RDMA_CIQS];
625ba2c2
DM		 548 struct sge_rspq fw_evtq ____cacheline_aligned_in_smp;
549
550 struct sge_rspq intrq ____cacheline_aligned_in_smp;
551 spinlock_t intrq_lock;
552
553 u16 max_ethqsets; /* # of available Ethernet queue sets */
554 u16 ethqsets; /* # of active Ethernet queue sets */
555 u16 ethtxq_rover; /* Tx queue to clean up next */
556 u16 ofldqsets; /* # of active offload queue sets */
557 u16 rdmaqs; /* # of available RDMA Rx queues */
cf38be6d 558 u16 rdmaciqs; /* # of available RDMA concentrator IQs */
625ba2c2
DM		 559 u16 ofld_rxq[MAX_OFLD_QSETS];
560 u16 rdma_rxq[NCHAN];
cf38be6d 561 u16 rdma_ciq[NCHAN];
625ba2c2
DM		 562 u16 timer_val[SGE_NTIMERS];
563 u8 counter_val[SGE_NCOUNTERS];
52367a76
VP		 564 u32 fl_pg_order; /* large page allocation size */
565 u32 stat_len; /* length of status page at ring end */
566 u32 pktshift; /* padding between CPL & packet data */
567 u32 fl_align; /* response queue message alignment */
568 u32 fl_starve_thres; /* Free List starvation threshold */
0f4d201f
KS		 569
570 /* State variables for detecting an SGE Ingress DMA hang */
571 unsigned int idma_1s_thresh;/* SGE same State Counter 1s threshold */
572 unsigned int idma_stalled[2];/* SGE synthesized stalled timers in HZ */
573 unsigned int idma_state[2]; /* SGE IDMA Hang detect state */
574 unsigned int idma_qid[2]; /* SGE IDMA Hung Ingress Queue ID */
575
e46dab4d
DM		 576 unsigned int egr_start;
577 unsigned int ingr_start;
625ba2c2
DM		 578 void *egr_map[MAX_EGRQ]; /* qid->queue egress queue map */
579 struct sge_rspq *ingr_map[MAX_INGQ]; /* qid->queue ingress queue map */
580 DECLARE_BITMAP(starving_fl, MAX_EGRQ);
581 DECLARE_BITMAP(txq_maperr, MAX_EGRQ);
582 struct timer_list rx_timer; /* refills starving FLs */
583 struct timer_list tx_timer; /* checks Tx queues */
584};
585
586#define for_each_ethrxq(sge, i) for (i = 0; i < (sge)->ethqsets; i++)
587#define for_each_ofldrxq(sge, i) for (i = 0; i < (sge)->ofldqsets; i++)
588#define for_each_rdmarxq(sge, i) for (i = 0; i < (sge)->rdmaqs; i++)
cf38be6d 589#define for_each_rdmaciq(sge, i) for (i = 0; i < (sge)->rdmaciqs; i++)
625ba2c2
DM		 590
591struct l2t_data;
592
2422d9a3
SR		 593#ifdef CONFIG_PCI_IOV
594
7d6727cf
SR		 595/* T4 supports SRIOV on PF0-3 and T5 on PF0-7. However, the Serial
596 * Configuration initialization for T5 only has SR-IOV functionality enabled
597 * on PF0-3 in order to simplify everything.
2422d9a3 598 */
7d6727cf 599#define NUM_OF_PF_WITH_SRIOV 4
2422d9a3
SR		 600
601#endif
602
625ba2c2
DM		 603struct adapter {
604 void __iomem *regs;
22adfe0a 605 void __iomem *bar2;
625ba2c2
DM		 606 struct pci_dev *pdev;
607 struct device *pdev_dev;
3069ee9b 608 unsigned int mbox;
060e0c75
DM		 609 unsigned int fn;
610 unsigned int flags;
2422d9a3 611 enum chip_type chip;
625ba2c2 612
625ba2c2
DM		 613 int msg_enable;
614
615 struct adapter_params params;
616 struct cxgb4_virt_res vres;
617 unsigned int swintr;
618
619 unsigned int wol;
620
621 struct {
622 unsigned short vec;
8cd18ac4 623 char desc[IFNAMSIZ + 10];
625ba2c2
DM		 624 } msix_info[MAX_INGQ + 1];
625
626 struct sge sge;
627
628 struct net_device *port[MAX_NPORTS];
629 u8 chan_map[NCHAN]; /* channel -> port map */
630
793dad94 631 u32 filter_mode;
636f9d37
VP		 632 unsigned int l2t_start;
633 unsigned int l2t_end;
625ba2c2
DM		 634 struct l2t_data *l2t;
635 void *uld_handle[CXGB4_ULD_MAX];
636 struct list_head list_node;
01bcca68 637 struct list_head rcu_node;
625ba2c2
DM		 638
639 struct tid_info tids;
640 void **tid_release_head;
641 spinlock_t tid_release_lock;
642 struct work_struct tid_release_task;
881806bc
VP		 643 struct work_struct db_full_task;
644 struct work_struct db_drop_task;
625ba2c2
DM		 645 bool tid_release_task_busy;
646
647 struct dentry *debugfs_root;
648
649 spinlock_t stats_lock;
650};
651
f2b7e78d
VP		 652/* Defined bit width of user definable filter tuples
653 */
654#define ETHTYPE_BITWIDTH 16
655#define FRAG_BITWIDTH 1
656#define MACIDX_BITWIDTH 9
657#define FCOE_BITWIDTH 1
658#define IPORT_BITWIDTH 3
659#define MATCHTYPE_BITWIDTH 3
660#define PROTO_BITWIDTH 8
661#define TOS_BITWIDTH 8
662#define PF_BITWIDTH 8
663#define VF_BITWIDTH 8
664#define IVLAN_BITWIDTH 16
665#define OVLAN_BITWIDTH 16
666
667/* Filter matching rules. These consist of a set of ingress packet field
668 * (value, mask) tuples. The associated ingress packet field matches the
669 * tuple when ((field & mask) == value). (Thus a wildcard "don't care" field
670 * rule can be constructed by specifying a tuple of (0, 0).) A filter rule
671 * matches an ingress packet when all of the individual individual field
672 * matching rules are true.
673 *
674 * Partial field masks are always valid, however, while it may be easy to
675 * understand their meanings for some fields (e.g. IP address to match a
676 * subnet), for others making sensible partial masks is less intuitive (e.g.
677 * MPS match type) ...
678 *
679 * Most of the following data structures are modeled on T4 capabilities.
680 * Drivers for earlier chips use the subsets which make sense for those chips.
681 * We really need to come up with a hardware-independent mechanism to
682 * represent hardware filter capabilities ...
683 */
684struct ch_filter_tuple {
685 /* Compressed header matching field rules. The TP_VLAN_PRI_MAP
686 * register selects which of these fields will participate in the
687 * filter match rules -- up to a maximum of 36 bits. Because
688 * TP_VLAN_PRI_MAP is a global register, all filters must use the same
689 * set of fields.
690 */
691 uint32_t ethtype:ETHTYPE_BITWIDTH; /* Ethernet type */
692 uint32_t frag:FRAG_BITWIDTH; /* IP fragmentation header */
693 uint32_t ivlan_vld:1; /* inner VLAN valid */
694 uint32_t ovlan_vld:1; /* outer VLAN valid */
695 uint32_t pfvf_vld:1; /* PF/VF valid */
696 uint32_t macidx:MACIDX_BITWIDTH; /* exact match MAC index */
697 uint32_t fcoe:FCOE_BITWIDTH; /* FCoE packet */
698 uint32_t iport:IPORT_BITWIDTH; /* ingress port */
699 uint32_t matchtype:MATCHTYPE_BITWIDTH; /* MPS match type */
700 uint32_t proto:PROTO_BITWIDTH; /* protocol type */
701 uint32_t tos:TOS_BITWIDTH; /* TOS/Traffic Type */
702 uint32_t pf:PF_BITWIDTH; /* PCI-E PF ID */
703 uint32_t vf:VF_BITWIDTH; /* PCI-E VF ID */
704 uint32_t ivlan:IVLAN_BITWIDTH; /* inner VLAN */
705 uint32_t ovlan:OVLAN_BITWIDTH; /* outer VLAN */
706
707 /* Uncompressed header matching field rules. These are always
708 * available for field rules.
709 */
710 uint8_t lip[16]; /* local IP address (IPv4 in [3:0]) */
711 uint8_t fip[16]; /* foreign IP address (IPv4 in [3:0]) */
712 uint16_t lport; /* local port */
713 uint16_t fport; /* foreign port */
714};
715
716/* A filter ioctl command.
717 */
718struct ch_filter_specification {
719 /* Administrative fields for filter.
720 */
721 uint32_t hitcnts:1; /* count filter hits in TCB */
722 uint32_t prio:1; /* filter has priority over active/server */
723
724 /* Fundamental filter typing. This is the one element of filter
725 * matching that doesn't exist as a (value, mask) tuple.
726 */
727 uint32_t type:1; /* 0 => IPv4, 1 => IPv6 */
728
729 /* Packet dispatch information. Ingress packets which match the
730 * filter rules will be dropped, passed to the host or switched back
731 * out as egress packets.
732 */
733 uint32_t action:2; /* drop, pass, switch */
734
735 uint32_t rpttid:1; /* report TID in RSS hash field */
736
737 uint32_t dirsteer:1; /* 0 => RSS, 1 => steer to iq */
738 uint32_t iq:10; /* ingress queue */
739
740 uint32_t maskhash:1; /* dirsteer=0: store RSS hash in TCB */
741 uint32_t dirsteerhash:1;/* dirsteer=1: 0 => TCB contains RSS hash */
742 /* 1 => TCB contains IQ ID */
743
744 /* Switch proxy/rewrite fields. An ingress packet which matches a
745 * filter with "switch" set will be looped back out as an egress
746 * packet -- potentially with some Ethernet header rewriting.
747 */
748 uint32_t eport:2; /* egress port to switch packet out */
749 uint32_t newdmac:1; /* rewrite destination MAC address */
750 uint32_t newsmac:1; /* rewrite source MAC address */
751 uint32_t newvlan:2; /* rewrite VLAN Tag */
752 uint8_t dmac[ETH_ALEN]; /* new destination MAC address */
753 uint8_t smac[ETH_ALEN]; /* new source MAC address */
754 uint16_t vlan; /* VLAN Tag to insert */
755
756 /* Filter rule value/mask pairs.
757 */
758 struct ch_filter_tuple val;
759 struct ch_filter_tuple mask;
760};
761
762enum {
763 FILTER_PASS = 0, /* default */
764 FILTER_DROP,
765 FILTER_SWITCH
766};
767
768enum {
769 VLAN_NOCHANGE = 0, /* default */
770 VLAN_REMOVE,
771 VLAN_INSERT,
772 VLAN_REWRITE
773};
774
2422d9a3
SR		 775static inline int is_t5(enum chip_type chip)
776{
d14807dd 777 return CHELSIO_CHIP_VERSION(chip) == CHELSIO_T5;
2422d9a3
SR		 778}
779
780static inline int is_t4(enum chip_type chip)
781{
d14807dd 782 return CHELSIO_CHIP_VERSION(chip) == CHELSIO_T4;
2422d9a3
SR		 783}
784
625ba2c2
DM		 785static inline u32 t4_read_reg(struct adapter *adap, u32 reg_addr)
786{
787 return readl(adap->regs + reg_addr);
788}
789
790static inline void t4_write_reg(struct adapter *adap, u32 reg_addr, u32 val)
791{
792 writel(val, adap->regs + reg_addr);
793}
794
795#ifndef readq
796static inline u64 readq(const volatile void __iomem *addr)
797{
798 return readl(addr) + ((u64)readl(addr + 4) << 32);
799}
800
801static inline void writeq(u64 val, volatile void __iomem *addr)
802{
803 writel(val, addr);
804 writel(val >> 32, addr + 4);
805}
806#endif
807
808static inline u64 t4_read_reg64(struct adapter *adap, u32 reg_addr)
809{
810 return readq(adap->regs + reg_addr);
811}
812
813static inline void t4_write_reg64(struct adapter *adap, u32 reg_addr, u64 val)
814{
815 writeq(val, adap->regs + reg_addr);
816}
817
818/**
819 * netdev2pinfo - return the port_info structure associated with a net_device
820 * @dev: the netdev
821 *
822 * Return the struct port_info associated with a net_device
823 */
824static inline struct port_info *netdev2pinfo(const struct net_device *dev)
825{
826 return netdev_priv(dev);
827}
828
829/**
830 * adap2pinfo - return the port_info of a port
831 * @adap: the adapter
832 * @idx: the port index
833 *
834 * Return the port_info structure for the port of the given index.
835 */
836static inline struct port_info *adap2pinfo(struct adapter *adap, int idx)
837{
838 return netdev_priv(adap->port[idx]);
839}
840
841/**
842 * netdev2adap - return the adapter structure associated with a net_device
843 * @dev: the netdev
844 *
845 * Return the struct adapter associated with a net_device
846 */
847static inline struct adapter *netdev2adap(const struct net_device *dev)
848{
849 return netdev2pinfo(dev)->adapter;
850}
851
852void t4_os_portmod_changed(const struct adapter *adap, int port_id);
853void t4_os_link_changed(struct adapter *adap, int port_id, int link_stat);
854
855void *t4_alloc_mem(size_t size);
625ba2c2
DM		 856
857void t4_free_sge_resources(struct adapter *adap);
858irq_handler_t t4_intr_handler(struct adapter *adap);
859netdev_tx_t t4_eth_xmit(struct sk_buff *skb, struct net_device *dev);
860int t4_ethrx_handler(struct sge_rspq *q, const __be64 *rsp,
861 const struct pkt_gl *gl);
862int t4_mgmt_tx(struct adapter *adap, struct sk_buff *skb);
863int t4_ofld_send(struct adapter *adap, struct sk_buff *skb);
864int t4_sge_alloc_rxq(struct adapter *adap, struct sge_rspq *iq, bool fwevtq,
865 struct net_device *dev, int intr_idx,
866 struct sge_fl *fl, rspq_handler_t hnd);
867int t4_sge_alloc_eth_txq(struct adapter *adap, struct sge_eth_txq *txq,
868 struct net_device *dev, struct netdev_queue *netdevq,
869 unsigned int iqid);
870int t4_sge_alloc_ctrl_txq(struct adapter *adap, struct sge_ctrl_txq *txq,
871 struct net_device *dev, unsigned int iqid,
872 unsigned int cmplqid);
873int t4_sge_alloc_ofld_txq(struct adapter *adap, struct sge_ofld_txq *txq,
874 struct net_device *dev, unsigned int iqid);
875irqreturn_t t4_sge_intr_msix(int irq, void *cookie);
52367a76 876int t4_sge_init(struct adapter *adap);
625ba2c2
DM		 877void t4_sge_start(struct adapter *adap);
878void t4_sge_stop(struct adapter *adap);
3069ee9b 879extern int dbfifo_int_thresh;
625ba2c2
DM		 880
881#define for_each_port(adapter, iter) \
882 for (iter = 0; iter < (adapter)->params.nports; ++iter)
883
9a4da2cd
VP		 884static inline int is_bypass(struct adapter *adap)
885{
886 return adap->params.bypass;
887}
888
889static inline int is_bypass_device(int device)
890{
891 /* this should be set based upon device capabilities */
892 switch (device) {
893 case 0x440b:
894 case 0x440c:
895 return 1;
896 default:
897 return 0;
898 }
899}
900
625ba2c2
DM		 901static inline unsigned int core_ticks_per_usec(const struct adapter *adap)
902{
903 return adap->params.vpd.cclk / 1000;
904}
905
906static inline unsigned int us_to_core_ticks(const struct adapter *adap,
907 unsigned int us)
908{
909 return (us * adap->params.vpd.cclk) / 1000;
910}
911
52367a76
VP		 912static inline unsigned int core_ticks_to_us(const struct adapter *adapter,
913 unsigned int ticks)
914{
915 /* add Core Clock / 2 to round ticks to nearest uS */
916 return ((ticks * 1000 + adapter->params.vpd.cclk/2) /
917 adapter->params.vpd.cclk);
918}
919
625ba2c2
DM		 920void t4_set_reg_field(struct adapter *adap, unsigned int addr, u32 mask,
921 u32 val);
922
923int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size,
924 void *rpl, bool sleep_ok);
925
926static inline int t4_wr_mbox(struct adapter *adap, int mbox, const void *cmd,
927 int size, void *rpl)
928{
929 return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, true);
930}
931
932static inline int t4_wr_mbox_ns(struct adapter *adap, int mbox, const void *cmd,
933 int size, void *rpl)
934{
935 return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, false);
936}
937
13ee15d3
VP		 938void t4_write_indirect(struct adapter *adap, unsigned int addr_reg,
939 unsigned int data_reg, const u32 *vals,
940 unsigned int nregs, unsigned int start_idx);
f2b7e78d
VP		 941void t4_read_indirect(struct adapter *adap, unsigned int addr_reg,
942 unsigned int data_reg, u32 *vals, unsigned int nregs,
943 unsigned int start_idx);
944
945struct fw_filter_wr;
946
625ba2c2
DM		 947void t4_intr_enable(struct adapter *adapter);
948void t4_intr_disable(struct adapter *adapter);
625ba2c2
DM		 949int t4_slow_intr_handler(struct adapter *adapter);
950
204dc3c0 951int t4_wait_dev_ready(struct adapter *adap);
625ba2c2
DM		 952int t4_link_start(struct adapter *adap, unsigned int mbox, unsigned int port,
953 struct link_config *lc);
954int t4_restart_aneg(struct adapter *adap, unsigned int mbox, unsigned int port);
5afc8b84
VP		 955int t4_memory_write(struct adapter *adap, int mtype, u32 addr, u32 len,
956 __be32 *buf);
625ba2c2 957int t4_seeprom_wp(struct adapter *adapter, bool enable);
636f9d37 958int get_vpd_params(struct adapter *adapter, struct vpd_params *p);
625ba2c2 959int t4_load_fw(struct adapter *adapter, const u8 *fw_data, unsigned int size);
636f9d37 960unsigned int t4_flash_cfg_addr(struct adapter *adapter);
16e47624
HS		 961int t4_get_fw_version(struct adapter *adapter, u32 *vers);
962int t4_get_tp_version(struct adapter *adapter, u32 *vers);
963int t4_prep_fw(struct adapter *adap, struct fw_info *fw_info,
964 const u8 *fw_data, unsigned int fw_size,
965 struct fw_hdr *card_fw, enum dev_state state, int *reset);
625ba2c2 966int t4_prep_adapter(struct adapter *adapter);
dcf7b6f5
KS		 967int t4_init_tp_params(struct adapter *adap);
968int t4_filter_field_shift(const struct adapter *adap, int filter_sel);
625ba2c2
DM		 969int t4_port_init(struct adapter *adap, int mbox, int pf, int vf);
970void t4_fatal_err(struct adapter *adapter);
625ba2c2
DM		 971int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid,
972 int start, int n, const u16 *rspq, unsigned int nrspq);
973int t4_config_glbl_rss(struct adapter *adapter, int mbox, unsigned int mode,
974 unsigned int flags);
19dd37ba
SR		 975int t4_mc_read(struct adapter *adap, int idx, u32 addr, __be32 *data,
976 u64 *parity);
625ba2c2
DM		 977int t4_edc_read(struct adapter *adap, int idx, u32 addr, __be32 *data,
978 u64 *parity);
72aca4bf 979const char *t4_get_port_type_description(enum fw_port_type port_type);
625ba2c2 980void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p);
625ba2c2 981void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log);
636f9d37
VP		 982void t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr,
983 unsigned int mask, unsigned int val);
625ba2c2
DM		 984void t4_tp_get_tcp_stats(struct adapter *adap, struct tp_tcp_stats *v4,
985 struct tp_tcp_stats *v6);
986void t4_load_mtus(struct adapter *adap, const unsigned short *mtus,
987 const unsigned short *alpha, const unsigned short *beta);
988
f2b7e78d
VP		 989void t4_mk_filtdelwr(unsigned int ftid, struct fw_filter_wr *wr, int qid);
990
625ba2c2
DM		 991void t4_wol_magic_enable(struct adapter *adap, unsigned int port,
992 const u8 *addr);
993int t4_wol_pat_enable(struct adapter *adap, unsigned int port, unsigned int map,
994 u64 mask0, u64 mask1, unsigned int crc, bool enable);
995
996int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox,
997 enum dev_master master, enum dev_state *state);
998int t4_fw_bye(struct adapter *adap, unsigned int mbox);
999int t4_early_init(struct adapter *adap, unsigned int mbox);
1000int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset);
636f9d37
VP		 1001int t4_fixup_host_params(struct adapter *adap, unsigned int page_size,
1002 unsigned int cache_line_size);
1003int t4_fw_initialize(struct adapter *adap, unsigned int mbox);
625ba2c2
DM		 1004int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
1005 unsigned int vf, unsigned int nparams, const u32 *params,
1006 u32 *val);
1007int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
1008 unsigned int vf, unsigned int nparams, const u32 *params,
1009 const u32 *val);
1010int t4_cfg_pfvf(struct adapter *adap, unsigned int mbox, unsigned int pf,
1011 unsigned int vf, unsigned int txq, unsigned int txq_eth_ctrl,
1012 unsigned int rxqi, unsigned int rxq, unsigned int tc,
1013 unsigned int vi, unsigned int cmask, unsigned int pmask,
1014 unsigned int nexact, unsigned int rcaps, unsigned int wxcaps);
1015int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port,
1016 unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac,
1017 unsigned int *rss_size);
625ba2c2 1018int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid,
f8f5aafa
DM		 1019 int mtu, int promisc, int all_multi, int bcast, int vlanex,
1020 bool sleep_ok);
625ba2c2
DM		 1021int t4_alloc_mac_filt(struct adapter *adap, unsigned int mbox,
1022 unsigned int viid, bool free, unsigned int naddr,
1023 const u8 **addr, u16 *idx, u64 *hash, bool sleep_ok);
1024int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid,
1025 int idx, const u8 *addr, bool persist, bool add_smt);
1026int t4_set_addr_hash(struct adapter *adap, unsigned int mbox, unsigned int viid,
1027 bool ucast, u64 vec, bool sleep_ok);
1028int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid,
1029 bool rx_en, bool tx_en);
1030int t4_identify_port(struct adapter *adap, unsigned int mbox, unsigned int viid,
1031 unsigned int nblinks);
1032int t4_mdio_rd(struct adapter *adap, unsigned int mbox, unsigned int phy_addr,
1033 unsigned int mmd, unsigned int reg, u16 *valp);
1034int t4_mdio_wr(struct adapter *adap, unsigned int mbox, unsigned int phy_addr,
1035 unsigned int mmd, unsigned int reg, u16 val);
625ba2c2
DM		 1036int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
1037 unsigned int vf, unsigned int iqtype, unsigned int iqid,
1038 unsigned int fl0id, unsigned int fl1id);
1039int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
1040 unsigned int vf, unsigned int eqid);
1041int t4_ctrl_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
1042 unsigned int vf, unsigned int eqid);
1043int t4_ofld_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
1044 unsigned int vf, unsigned int eqid);
1045int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl);
881806bc
VP		 1046void t4_db_full(struct adapter *adapter);
1047void t4_db_dropped(struct adapter *adapter);
8caa1e84
VP		 1048int t4_mem_win_read_len(struct adapter *adap, u32 addr, __be32 *data, int len);
1049int t4_fwaddrspace_write(struct adapter *adap, unsigned int mbox,
1050 u32 addr, u32 val);
68bce192 1051void t4_sge_decode_idma_state(struct adapter *adapter, int state);
625ba2c2 1052#endif /* __CXGB4_H__ */
Linux kernel - Deliverables
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