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cxgb4: update struct cxgb4_lld_info definition
[deliverable/linux.git] / drivers / net / ethernet / chelsio / cxgb4 / cxgb4.h
CommitLineData
625ba2c2
DM		 1/*
2 * This file is part of the Chelsio T4 Ethernet driver for Linux.
3 *
ce100b8b 4 * Copyright (c) 2003-2014 Chelsio Communications, Inc. All rights reserved.
625ba2c2
DM		 5 *
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
11 *
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
14 * conditions are met:
15 *
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
18 * disclaimer.
19 *
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
24 *
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
32 * SOFTWARE.
33 */
34
35#ifndef __CXGB4_H__
36#define __CXGB4_H__
37
dca4faeb
VP		 38#include "t4_hw.h"
39
625ba2c2
DM		 40#include <linux/bitops.h>
41#include <linux/cache.h>
42#include <linux/interrupt.h>
43#include <linux/list.h>
44#include <linux/netdevice.h>
45#include <linux/pci.h>
46#include <linux/spinlock.h>
47#include <linux/timer.h>
c0b8b992 48#include <linux/vmalloc.h>
098ef6c2 49#include <linux/etherdevice.h>
5e2a5ebc 50#include <linux/net_tstamp.h>
625ba2c2 51#include <asm/io.h>
27999805 52#include "t4_chip_type.h"
625ba2c2 53#include "cxgb4_uld.h"
625ba2c2 54
3069ee9b
VP		 55#define CH_WARN(adap, fmt, ...) dev_warn(adap->pdev_dev, fmt, ## __VA_ARGS__)
56
625ba2c2 57enum {
098ef6c2
HS		 58 MAX_NPORTS = 4, /* max # of ports */
59 SERNUM_LEN = 24, /* Serial # length */
60 EC_LEN = 16, /* E/C length */
61 ID_LEN = 16, /* ID length */
62 PN_LEN = 16, /* Part Number length */
63 MACADDR_LEN = 12, /* MAC Address length */
625ba2c2
DM		 64};
65
812034f1
HS		 66enum {
67 T4_REGMAP_SIZE = (160 * 1024),
68 T5_REGMAP_SIZE = (332 * 1024),
69};
70
625ba2c2
DM		 71enum {
72 MEM_EDC0,
73 MEM_EDC1,
2422d9a3
SR		 74 MEM_MC,
75 MEM_MC0 = MEM_MC,
76 MEM_MC1
625ba2c2
DM		 77};
78
3069ee9b 79enum {
3eb4afbf
VP		 80 MEMWIN0_APERTURE = 2048,
81 MEMWIN0_BASE = 0x1b800,
3069ee9b
VP		 82 MEMWIN1_APERTURE = 32768,
83 MEMWIN1_BASE = 0x28000,
2422d9a3 84 MEMWIN1_BASE_T5 = 0x52000,
3eb4afbf
VP		 85 MEMWIN2_APERTURE = 65536,
86 MEMWIN2_BASE = 0x30000,
0abfd152
HS		 87 MEMWIN2_APERTURE_T5 = 131072,
88 MEMWIN2_BASE_T5 = 0x60000,
3069ee9b
VP		 89};
90
625ba2c2
DM		 91enum dev_master {
92 MASTER_CANT,
93 MASTER_MAY,
94 MASTER_MUST
95};
96
97enum dev_state {
98 DEV_STATE_UNINIT,
99 DEV_STATE_INIT,
100 DEV_STATE_ERR
101};
102
103enum {
104 PAUSE_RX = 1 << 0,
105 PAUSE_TX = 1 << 1,
106 PAUSE_AUTONEG = 1 << 2
107};
108
109struct port_stats {
110 u64 tx_octets; /* total # of octets in good frames */
111 u64 tx_frames; /* all good frames */
112 u64 tx_bcast_frames; /* all broadcast frames */
113 u64 tx_mcast_frames; /* all multicast frames */
114 u64 tx_ucast_frames; /* all unicast frames */
115 u64 tx_error_frames; /* all error frames */
116
117 u64 tx_frames_64; /* # of Tx frames in a particular range */
118 u64 tx_frames_65_127;
119 u64 tx_frames_128_255;
120 u64 tx_frames_256_511;
121 u64 tx_frames_512_1023;
122 u64 tx_frames_1024_1518;
123 u64 tx_frames_1519_max;
124
125 u64 tx_drop; /* # of dropped Tx frames */
126 u64 tx_pause; /* # of transmitted pause frames */
127 u64 tx_ppp0; /* # of transmitted PPP prio 0 frames */
128 u64 tx_ppp1; /* # of transmitted PPP prio 1 frames */
129 u64 tx_ppp2; /* # of transmitted PPP prio 2 frames */
130 u64 tx_ppp3; /* # of transmitted PPP prio 3 frames */
131 u64 tx_ppp4; /* # of transmitted PPP prio 4 frames */
132 u64 tx_ppp5; /* # of transmitted PPP prio 5 frames */
133 u64 tx_ppp6; /* # of transmitted PPP prio 6 frames */
134 u64 tx_ppp7; /* # of transmitted PPP prio 7 frames */
135
136 u64 rx_octets; /* total # of octets in good frames */
137 u64 rx_frames; /* all good frames */
138 u64 rx_bcast_frames; /* all broadcast frames */
139 u64 rx_mcast_frames; /* all multicast frames */
140 u64 rx_ucast_frames; /* all unicast frames */
141 u64 rx_too_long; /* # of frames exceeding MTU */
142 u64 rx_jabber; /* # of jabber frames */
143 u64 rx_fcs_err; /* # of received frames with bad FCS */
144 u64 rx_len_err; /* # of received frames with length error */
145 u64 rx_symbol_err; /* symbol errors */
146 u64 rx_runt; /* # of short frames */
147
148 u64 rx_frames_64; /* # of Rx frames in a particular range */
149 u64 rx_frames_65_127;
150 u64 rx_frames_128_255;
151 u64 rx_frames_256_511;
152 u64 rx_frames_512_1023;
153 u64 rx_frames_1024_1518;
154 u64 rx_frames_1519_max;
155
156 u64 rx_pause; /* # of received pause frames */
157 u64 rx_ppp0; /* # of received PPP prio 0 frames */
158 u64 rx_ppp1; /* # of received PPP prio 1 frames */
159 u64 rx_ppp2; /* # of received PPP prio 2 frames */
160 u64 rx_ppp3; /* # of received PPP prio 3 frames */
161 u64 rx_ppp4; /* # of received PPP prio 4 frames */
162 u64 rx_ppp5; /* # of received PPP prio 5 frames */
163 u64 rx_ppp6; /* # of received PPP prio 6 frames */
164 u64 rx_ppp7; /* # of received PPP prio 7 frames */
165
166 u64 rx_ovflow0; /* drops due to buffer-group 0 overflows */
167 u64 rx_ovflow1; /* drops due to buffer-group 1 overflows */
168 u64 rx_ovflow2; /* drops due to buffer-group 2 overflows */
169 u64 rx_ovflow3; /* drops due to buffer-group 3 overflows */
170 u64 rx_trunc0; /* buffer-group 0 truncated packets */
171 u64 rx_trunc1; /* buffer-group 1 truncated packets */
172 u64 rx_trunc2; /* buffer-group 2 truncated packets */
173 u64 rx_trunc3; /* buffer-group 3 truncated packets */
174};
175
176struct lb_port_stats {
177 u64 octets;
178 u64 frames;
179 u64 bcast_frames;
180 u64 mcast_frames;
181 u64 ucast_frames;
182 u64 error_frames;
183
184 u64 frames_64;
185 u64 frames_65_127;
186 u64 frames_128_255;
187 u64 frames_256_511;
188 u64 frames_512_1023;
189 u64 frames_1024_1518;
190 u64 frames_1519_max;
191
192 u64 drop;
193
194 u64 ovflow0;
195 u64 ovflow1;
196 u64 ovflow2;
197 u64 ovflow3;
198 u64 trunc0;
199 u64 trunc1;
200 u64 trunc2;
201 u64 trunc3;
202};
203
204struct tp_tcp_stats {
a4cfd929
HS		 205 u32 tcp_out_rsts;
206 u64 tcp_in_segs;
207 u64 tcp_out_segs;
208 u64 tcp_retrans_segs;
209};
210
211struct tp_usm_stats {
212 u32 frames;
213 u32 drops;
214 u64 octets;
625ba2c2
DM		 215};
216
a6222975
HS		 217struct tp_fcoe_stats {
218 u32 frames_ddp;
219 u32 frames_drop;
220 u64 octets_ddp;
625ba2c2
DM		 221};
222
223struct tp_err_stats {
a4cfd929
HS		 224 u32 mac_in_errs[4];
225 u32 hdr_in_errs[4];
226 u32 tcp_in_errs[4];
227 u32 tnl_cong_drops[4];
228 u32 ofld_chan_drops[4];
229 u32 tnl_tx_drops[4];
230 u32 ofld_vlan_drops[4];
231 u32 tcp6_in_errs[4];
232 u32 ofld_no_neigh;
233 u32 ofld_cong_defer;
234};
235
a6222975
HS		 236struct tp_cpl_stats {
237 u32 req[4];
238 u32 rsp[4];
239};
240
a4cfd929
HS		 241struct tp_rdma_stats {
242 u32 rqe_dfr_pkt;
243 u32 rqe_dfr_mod;
625ba2c2
DM		 244};
245
e85c9a7a
HS		 246struct sge_params {
247 u32 hps; /* host page size for our PF/VF */
248 u32 eq_qpp; /* egress queues/page for our PF/VF */
249 u32 iq_qpp; /* egress queues/page for our PF/VF */
250};
251
625ba2c2 252struct tp_params {
625ba2c2 253 unsigned int tre; /* log2 of core clocks per TP tick */
2d277b3b 254 unsigned int la_mask; /* what events are recorded by TP LA */
dca4faeb
VP		 255 unsigned short tx_modq_map; /* TX modulation scheduler queue to */
256 /* channel map */
636f9d37
VP		 257
258 uint32_t dack_re; /* DACK timer resolution */
259 unsigned short tx_modq[NCHAN]; /* channel to modulation queue map */
dcf7b6f5
KS		 260
261 u32 vlan_pri_map; /* cached TP_VLAN_PRI_MAP */
262 u32 ingress_config; /* cached TP_INGRESS_CONFIG */
263
264 /* TP_VLAN_PRI_MAP Compressed Filter Tuple field offsets. This is a
265 * subset of the set of fields which may be present in the Compressed
266 * Filter Tuple portion of filters and TCP TCB connections. The
267 * fields which are present are controlled by the TP_VLAN_PRI_MAP.
268 * Since a variable number of fields may or may not be present, their
269 * shifted field positions within the Compressed Filter Tuple may
270 * vary, or not even be present if the field isn't selected in
271 * TP_VLAN_PRI_MAP. Since some of these fields are needed in various
272 * places we store their offsets here, or a -1 if the field isn't
273 * present.
274 */
275 int vlan_shift;
276 int vnic_shift;
277 int port_shift;
278 int protocol_shift;
625ba2c2
DM		 279};
280
281struct vpd_params {
282 unsigned int cclk;
283 u8 ec[EC_LEN + 1];
284 u8 sn[SERNUM_LEN + 1];
285 u8 id[ID_LEN + 1];
a94cd705 286 u8 pn[PN_LEN + 1];
098ef6c2 287 u8 na[MACADDR_LEN + 1];
625ba2c2
DM		 288};
289
290struct pci_params {
291 unsigned char speed;
292 unsigned char width;
293};
294
49aa284f
HS		 295struct devlog_params {
296 u32 memtype; /* which memory (EDC0, EDC1, MC) */
297 u32 start; /* start of log in firmware memory */
298 u32 size; /* size of log */
299};
300
3ccc6cf7
HS		 301/* Stores chip specific parameters */
302struct arch_specific_params {
303 u8 nchan;
44588560 304 u8 pm_stats_cnt;
2216d014 305 u8 cng_ch_bits_log; /* congestion channel map bits width */
3ccc6cf7
HS		 306 u16 mps_rplc_size;
307 u16 vfcount;
308 u32 sge_fl_db;
309 u16 mps_tcam_size;
310};
311
625ba2c2 312struct adapter_params {
e85c9a7a 313 struct sge_params sge;
625ba2c2
DM		 314 struct tp_params tp;
315 struct vpd_params vpd;
316 struct pci_params pci;
49aa284f
HS		 317 struct devlog_params devlog;
318 enum pcie_memwin drv_memwin;
625ba2c2 319
f1ff24aa
HS		 320 unsigned int cim_la_size;
321
900a6596
DM		 322 unsigned int sf_size; /* serial flash size in bytes */
323 unsigned int sf_nsec; /* # of flash sectors */
324 unsigned int sf_fw_start; /* start of FW image in flash */
325
625ba2c2
DM		 326 unsigned int fw_vers;
327 unsigned int tp_vers;
328 u8 api_vers[7];
329
330 unsigned short mtus[NMTUS];
331 unsigned short a_wnd[NCCTRL_WIN];
332 unsigned short b_wnd[NCCTRL_WIN];
333
334 unsigned char nports; /* # of ethernet ports */
335 unsigned char portvec;
d14807dd 336 enum chip_type chip; /* chip code */
3ccc6cf7 337 struct arch_specific_params arch; /* chip specific params */
625ba2c2
DM		 338 unsigned char offload;
339
9a4da2cd
VP		 340 unsigned char bypass;
341
625ba2c2 342 unsigned int ofldq_wr_cred;
1ac0f095 343 bool ulptx_memwrite_dsgl; /* use of T5 DSGL allowed */
4c2c5763
HS		 344
345 unsigned int max_ordird_qp; /* Max read depth per RDMA QP */
346 unsigned int max_ird_adapter; /* Max read depth per adapter */
625ba2c2
DM		 347};
348
a3bfb617
HS		 349/* State needed to monitor the forward progress of SGE Ingress DMA activities
350 * and possible hangs.
351 */
352struct sge_idma_monitor_state {
353 unsigned int idma_1s_thresh; /* 1s threshold in Core Clock ticks */
354 unsigned int idma_stalled[2]; /* synthesized stalled timers in HZ */
355 unsigned int idma_state[2]; /* IDMA Hang detect state */
356 unsigned int idma_qid[2]; /* IDMA Hung Ingress Queue ID */
357 unsigned int idma_warn[2]; /* time to warning in HZ */
358};
359
16e47624
HS		 360#include "t4fw_api.h"
361
362#define FW_VERSION(chip) ( \
b2e1a3f0
HS		 363 FW_HDR_FW_VER_MAJOR_G(chip##FW_VERSION_MAJOR) | \
364 FW_HDR_FW_VER_MINOR_G(chip##FW_VERSION_MINOR) | \
365 FW_HDR_FW_VER_MICRO_G(chip##FW_VERSION_MICRO) | \
366 FW_HDR_FW_VER_BUILD_G(chip##FW_VERSION_BUILD))
16e47624
HS		 367#define FW_INTFVER(chip, intf) (FW_HDR_INTFVER_##intf)
368
369struct fw_info {
370 u8 chip;
371 char *fs_name;
372 char *fw_mod_name;
373 struct fw_hdr fw_hdr;
374};
375
376
625ba2c2
DM		 377struct trace_params {
378 u32 data[TRACE_LEN / 4];
379 u32 mask[TRACE_LEN / 4];
380 unsigned short snap_len;
381 unsigned short min_len;
382 unsigned char skip_ofst;
383 unsigned char skip_len;
384 unsigned char invert;
385 unsigned char port;
386};
387
388struct link_config {
389 unsigned short supported; /* link capabilities */
390 unsigned short advertising; /* advertised capabilities */
391 unsigned short requested_speed; /* speed user has requested */
392 unsigned short speed; /* actual link speed */
393 unsigned char requested_fc; /* flow control user has requested */
394 unsigned char fc; /* actual link flow control */
395 unsigned char autoneg; /* autonegotiating? */
396 unsigned char link_ok; /* link up? */
397};
398
e2ac9628 399#define FW_LEN16(fw_struct) FW_CMD_LEN16_V(sizeof(fw_struct) / 16)
625ba2c2
DM		 400
401enum {
402 MAX_ETH_QSETS = 32, /* # of Ethernet Tx/Rx queue sets */
f90ce561 403 MAX_OFLD_QSETS = 16, /* # of offload Tx, iscsi Rx queue sets */
625ba2c2
DM		 404 MAX_CTRL_QUEUES = NCHAN, /* # of control Tx queues */
405 MAX_RDMA_QUEUES = NCHAN, /* # of streaming RDMA Rx queues */
f36e58e5 406 MAX_RDMA_CIQS = 32, /* # of RDMA concentrator IQs */
f2692d16
VP		 407
408 /* # of streaming iSCSIT Rx queues */
409 MAX_ISCSIT_QUEUES = MAX_OFLD_QSETS,
625ba2c2
DM		 410};
411
812034f1
HS		 412enum {
413 MAX_TXQ_ENTRIES = 16384,
414 MAX_CTRL_TXQ_ENTRIES = 1024,
415 MAX_RSPQ_ENTRIES = 16384,
416 MAX_RX_BUFFERS = 16384,
417 MIN_TXQ_ENTRIES = 32,
418 MIN_CTRL_TXQ_ENTRIES = 32,
419 MIN_RSPQ_ENTRIES = 128,
420 MIN_FL_ENTRIES = 16
421};
422
625ba2c2 423enum {
cf38be6d
HS		 424 INGQ_EXTRAS = 2, /* firmware event queue and */
425 /* forwarded interrupts */
f2692d16
VP		 426 MAX_INGQ = MAX_ETH_QSETS + MAX_OFLD_QSETS + MAX_RDMA_QUEUES +
427 MAX_RDMA_CIQS + MAX_ISCSIT_QUEUES + INGQ_EXTRAS,
625ba2c2
DM		 428};
429
430struct adapter;
625ba2c2
DM		 431struct sge_rspq;
432
688848b1
AB		 433#include "cxgb4_dcb.h"
434
76fed8a9
VP		 435#ifdef CONFIG_CHELSIO_T4_FCOE
436#include "cxgb4_fcoe.h"
437#endif /* CONFIG_CHELSIO_T4_FCOE */
438
625ba2c2
DM		 439struct port_info {
440 struct adapter *adapter;
625ba2c2
DM		 441 u16 viid;
442 s16 xact_addr_filt; /* index of exact MAC address filter */
443 u16 rss_size; /* size of VI's RSS table slice */
444 s8 mdio_addr;
40e9de4b 445 enum fw_port_type port_type;
625ba2c2
DM		 446 u8 mod_type;
447 u8 port_id;
448 u8 tx_chan;
449 u8 lport; /* associated offload logical port */
625ba2c2
DM		 450 u8 nqsets; /* # of qsets */
451 u8 first_qset; /* index of first qset */
f796564a 452 u8 rss_mode;
625ba2c2 453 struct link_config link_cfg;
671b0060 454 u16 *rss;
a4cfd929 455 struct port_stats stats_base;
688848b1
AB		 456#ifdef CONFIG_CHELSIO_T4_DCB
457 struct port_dcb_info dcb; /* Data Center Bridging support */
458#endif
76fed8a9
VP		 459#ifdef CONFIG_CHELSIO_T4_FCOE
460 struct cxgb_fcoe fcoe;
461#endif /* CONFIG_CHELSIO_T4_FCOE */
5e2a5ebc
HS		 462 bool rxtstamp; /* Enable TS */
463 struct hwtstamp_config tstamp_config;
625ba2c2
DM		 464};
465
625ba2c2
DM		 466struct dentry;
467struct work_struct;
468
469enum { /* adapter flags */
470 FULL_INIT_DONE = (1 << 0),
144be3d9
GS		 471 DEV_ENABLED = (1 << 1),
472 USING_MSI = (1 << 2),
473 USING_MSIX = (1 << 3),
625ba2c2 474 FW_OK = (1 << 4),
13ee15d3 475 RSS_TNLALLLOOKUP = (1 << 5),
52367a76
VP		 476 USING_SOFT_PARAMS = (1 << 6),
477 MASTER_PF = (1 << 7),
478 FW_OFLD_CONN = (1 << 9),
625ba2c2
DM		 479};
480
481struct rx_sw_desc;
482
483struct sge_fl { /* SGE free-buffer queue state */
484 unsigned int avail; /* # of available Rx buffers */
485 unsigned int pend_cred; /* new buffers since last FL DB ring */
486 unsigned int cidx; /* consumer index */
487 unsigned int pidx; /* producer index */
488 unsigned long alloc_failed; /* # of times buffer allocation failed */
489 unsigned long large_alloc_failed;
70055dd0
HS		 490 unsigned long mapping_err; /* # of RX Buffer DMA Mapping failures */
491 unsigned long low; /* # of times momentarily starving */
625ba2c2
DM		 492 unsigned long starving;
493 /* RO fields */
494 unsigned int cntxt_id; /* SGE context id for the free list */
495 unsigned int size; /* capacity of free list */
496 struct rx_sw_desc *sdesc; /* address of SW Rx descriptor ring */
497 __be64 *desc; /* address of HW Rx descriptor ring */
498 dma_addr_t addr; /* bus address of HW ring start */
df64e4d3
HS		 499 void __iomem *bar2_addr; /* address of BAR2 Queue registers */
500 unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */
625ba2c2
DM		 501};
502
503/* A packet gather list */
504struct pkt_gl {
5e2a5ebc 505 u64 sgetstamp; /* SGE Time Stamp for Ingress Packet */
e91b0f24 506 struct page_frag frags[MAX_SKB_FRAGS];
625ba2c2
DM		 507 void *va; /* virtual address of first byte */
508 unsigned int nfrags; /* # of fragments */
509 unsigned int tot_len; /* total length of fragments */
510};
511
512typedef int (*rspq_handler_t)(struct sge_rspq *q, const __be64 *rsp,
513 const struct pkt_gl *gl);
2337ba42
VP		 514typedef void (*rspq_flush_handler_t)(struct sge_rspq *q);
515/* LRO related declarations for ULD */
516struct t4_lro_mgr {
517#define MAX_LRO_SESSIONS 64
518 u8 lro_session_cnt; /* # of sessions to aggregate */
519 unsigned long lro_pkts; /* # of LRO super packets */
520 unsigned long lro_merged; /* # of wire packets merged by LRO */
521 struct sk_buff_head lroq; /* list of aggregated sessions */
522};
625ba2c2
DM		 523
524struct sge_rspq { /* state for an SGE response queue */
525 struct napi_struct napi;
526 const __be64 *cur_desc; /* current descriptor in queue */
527 unsigned int cidx; /* consumer index */
528 u8 gen; /* current generation bit */
529 u8 intr_params; /* interrupt holdoff parameters */
530 u8 next_intr_params; /* holdoff params for next interrupt */
e553ec3f 531 u8 adaptive_rx;
625ba2c2
DM		 532 u8 pktcnt_idx; /* interrupt packet threshold */
533 u8 uld; /* ULD handling this queue */
534 u8 idx; /* queue index within its group */
535 int offset; /* offset into current Rx buffer */
536 u16 cntxt_id; /* SGE context id for the response q */
537 u16 abs_id; /* absolute SGE id for the response q */
538 __be64 *desc; /* address of HW response ring */
539 dma_addr_t phys_addr; /* physical address of the ring */
df64e4d3
HS		 540 void __iomem *bar2_addr; /* address of BAR2 Queue registers */
541 unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */
625ba2c2
DM		 542 unsigned int iqe_len; /* entry size */
543 unsigned int size; /* capacity of response queue */
544 struct adapter *adap;
545 struct net_device *netdev; /* associated net device */
546 rspq_handler_t handler;
2337ba42
VP		 547 rspq_flush_handler_t flush_handler;
548 struct t4_lro_mgr lro_mgr;
3a336cb1
HS		 549#ifdef CONFIG_NET_RX_BUSY_POLL
550#define CXGB_POLL_STATE_IDLE 0
551#define CXGB_POLL_STATE_NAPI BIT(0) /* NAPI owns this poll */
552#define CXGB_POLL_STATE_POLL BIT(1) /* poll owns this poll */
553#define CXGB_POLL_STATE_NAPI_YIELD BIT(2) /* NAPI yielded this poll */
554#define CXGB_POLL_STATE_POLL_YIELD BIT(3) /* poll yielded this poll */
555#define CXGB_POLL_YIELD (CXGB_POLL_STATE_NAPI_YIELD | \
556 CXGB_POLL_STATE_POLL_YIELD)
557#define CXGB_POLL_LOCKED (CXGB_POLL_STATE_NAPI | \
558 CXGB_POLL_STATE_POLL)
559#define CXGB_POLL_USER_PEND (CXGB_POLL_STATE_POLL | \
560 CXGB_POLL_STATE_POLL_YIELD)
561 unsigned int bpoll_state;
562 spinlock_t bpoll_lock; /* lock for busy poll */
563#endif /* CONFIG_NET_RX_BUSY_POLL */
564
625ba2c2
DM		 565};
566
567struct sge_eth_stats { /* Ethernet queue statistics */
568 unsigned long pkts; /* # of ethernet packets */
569 unsigned long lro_pkts; /* # of LRO super packets */
570 unsigned long lro_merged; /* # of wire packets merged by LRO */
571 unsigned long rx_cso; /* # of Rx checksum offloads */
572 unsigned long vlan_ex; /* # of Rx VLAN extractions */
573 unsigned long rx_drops; /* # of packets dropped due to no mem */
574};
575
576struct sge_eth_rxq { /* SW Ethernet Rx queue */
577 struct sge_rspq rspq;
578 struct sge_fl fl;
579 struct sge_eth_stats stats;
580} ____cacheline_aligned_in_smp;
581
582struct sge_ofld_stats { /* offload queue statistics */
583 unsigned long pkts; /* # of packets */
584 unsigned long imm; /* # of immediate-data packets */
585 unsigned long an; /* # of asynchronous notifications */
586 unsigned long nomem; /* # of responses deferred due to no mem */
587};
588
589struct sge_ofld_rxq { /* SW offload Rx queue */
590 struct sge_rspq rspq;
591 struct sge_fl fl;
592 struct sge_ofld_stats stats;
593} ____cacheline_aligned_in_smp;
594
595struct tx_desc {
596 __be64 flit[8];
597};
598
599struct tx_sw_desc;
600
601struct sge_txq {
602 unsigned int in_use; /* # of in-use Tx descriptors */
603 unsigned int size; /* # of descriptors */
604 unsigned int cidx; /* SW consumer index */
605 unsigned int pidx; /* producer index */
606 unsigned long stops; /* # of times q has been stopped */
607 unsigned long restarts; /* # of queue restarts */
608 unsigned int cntxt_id; /* SGE context id for the Tx q */
609 struct tx_desc *desc; /* address of HW Tx descriptor ring */
610 struct tx_sw_desc *sdesc; /* address of SW Tx descriptor ring */
611 struct sge_qstat *stat; /* queue status entry */
612 dma_addr_t phys_addr; /* physical address of the ring */
3069ee9b
VP		 613 spinlock_t db_lock;
614 int db_disabled;
615 unsigned short db_pidx;
05eb2389 616 unsigned short db_pidx_inc;
df64e4d3
HS		 617 void __iomem *bar2_addr; /* address of BAR2 Queue registers */
618 unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */
625ba2c2
DM		 619};
620
621struct sge_eth_txq { /* state for an SGE Ethernet Tx queue */
622 struct sge_txq q;
623 struct netdev_queue *txq; /* associated netdev TX queue */
10b00466
AB		 624#ifdef CONFIG_CHELSIO_T4_DCB
625 u8 dcb_prio; /* DCB Priority bound to queue */
626#endif
625ba2c2
DM		 627 unsigned long tso; /* # of TSO requests */
628 unsigned long tx_cso; /* # of Tx checksum offloads */
629 unsigned long vlan_ins; /* # of Tx VLAN insertions */
630 unsigned long mapping_err; /* # of I/O MMU packet mapping errors */
631} ____cacheline_aligned_in_smp;
632
633struct sge_ofld_txq { /* state for an SGE offload Tx queue */
634 struct sge_txq q;
635 struct adapter *adap;
636 struct sk_buff_head sendq; /* list of backpressured packets */
637 struct tasklet_struct qresume_tsk; /* restarts the queue */
126fca64 638 bool service_ofldq_running; /* service_ofldq() is processing sendq */
625ba2c2
DM		 639 u8 full; /* the Tx ring is full */
640 unsigned long mapping_err; /* # of I/O MMU packet mapping errors */
641} ____cacheline_aligned_in_smp;
642
643struct sge_ctrl_txq { /* state for an SGE control Tx queue */
644 struct sge_txq q;
645 struct adapter *adap;
646 struct sk_buff_head sendq; /* list of backpressured packets */
647 struct tasklet_struct qresume_tsk; /* restarts the queue */
648 u8 full; /* the Tx ring is full */
649} ____cacheline_aligned_in_smp;
650
651struct sge {
652 struct sge_eth_txq ethtxq[MAX_ETH_QSETS];
653 struct sge_ofld_txq ofldtxq[MAX_OFLD_QSETS];
654 struct sge_ctrl_txq ctrlq[MAX_CTRL_QUEUES];
655
656 struct sge_eth_rxq ethrxq[MAX_ETH_QSETS];
f90ce561 657 struct sge_ofld_rxq iscsirxq[MAX_OFLD_QSETS];
f2692d16 658 struct sge_ofld_rxq iscsitrxq[MAX_ISCSIT_QUEUES];
625ba2c2 659 struct sge_ofld_rxq rdmarxq[MAX_RDMA_QUEUES];
cf38be6d 660 struct sge_ofld_rxq rdmaciq[MAX_RDMA_CIQS];
625ba2c2
DM		 661 struct sge_rspq fw_evtq ____cacheline_aligned_in_smp;
662
663 struct sge_rspq intrq ____cacheline_aligned_in_smp;
664 spinlock_t intrq_lock;
665
666 u16 max_ethqsets; /* # of available Ethernet queue sets */
667 u16 ethqsets; /* # of active Ethernet queue sets */
668 u16 ethtxq_rover; /* Tx queue to clean up next */
f90ce561 669 u16 iscsiqsets; /* # of active iSCSI queue sets */
f2692d16 670 u16 niscsitq; /* # of available iSCST Rx queues */
625ba2c2 671 u16 rdmaqs; /* # of available RDMA Rx queues */
cf38be6d 672 u16 rdmaciqs; /* # of available RDMA concentrator IQs */
f90ce561 673 u16 iscsi_rxq[MAX_OFLD_QSETS];
f2692d16 674 u16 iscsit_rxq[MAX_ISCSIT_QUEUES];
f36e58e5
HS		 675 u16 rdma_rxq[MAX_RDMA_QUEUES];
676 u16 rdma_ciq[MAX_RDMA_CIQS];
625ba2c2
DM		 677 u16 timer_val[SGE_NTIMERS];
678 u8 counter_val[SGE_NCOUNTERS];
52367a76
VP		 679 u32 fl_pg_order; /* large page allocation size */
680 u32 stat_len; /* length of status page at ring end */
681 u32 pktshift; /* padding between CPL & packet data */
682 u32 fl_align; /* response queue message alignment */
683 u32 fl_starve_thres; /* Free List starvation threshold */
0f4d201f 684
a3bfb617 685 struct sge_idma_monitor_state idma_monitor;
e46dab4d 686 unsigned int egr_start;
4b8e27a8 687 unsigned int egr_sz;
e46dab4d 688 unsigned int ingr_start;
4b8e27a8
HS		 689 unsigned int ingr_sz;
690 void **egr_map; /* qid->queue egress queue map */
691 struct sge_rspq **ingr_map; /* qid->queue ingress queue map */
692 unsigned long *starving_fl;
693 unsigned long *txq_maperr;
5b377d11 694 unsigned long *blocked_fl;
625ba2c2
DM		 695 struct timer_list rx_timer; /* refills starving FLs */
696 struct timer_list tx_timer; /* checks Tx queues */
697};
698
699#define for_each_ethrxq(sge, i) for (i = 0; i < (sge)->ethqsets; i++)
f90ce561 700#define for_each_iscsirxq(sge, i) for (i = 0; i < (sge)->iscsiqsets; i++)
f2692d16 701#define for_each_iscsitrxq(sge, i) for (i = 0; i < (sge)->niscsitq; i++)
625ba2c2 702#define for_each_rdmarxq(sge, i) for (i = 0; i < (sge)->rdmaqs; i++)
cf38be6d 703#define for_each_rdmaciq(sge, i) for (i = 0; i < (sge)->rdmaciqs; i++)
625ba2c2
DM		 704
705struct l2t_data;
706
2422d9a3
SR		 707#ifdef CONFIG_PCI_IOV
708
7d6727cf
SR		 709/* T4 supports SRIOV on PF0-3 and T5 on PF0-7. However, the Serial
710 * Configuration initialization for T5 only has SR-IOV functionality enabled
711 * on PF0-3 in order to simplify everything.
2422d9a3 712 */
7d6727cf 713#define NUM_OF_PF_WITH_SRIOV 4
2422d9a3
SR		 714
715#endif
716
a4cfd929
HS		 717struct doorbell_stats {
718 u32 db_drop;
719 u32 db_empty;
720 u32 db_full;
721};
722
625ba2c2
DM		 723struct adapter {
724 void __iomem *regs;
22adfe0a 725 void __iomem *bar2;
0abfd152 726 u32 t4_bar0;
625ba2c2
DM		 727 struct pci_dev *pdev;
728 struct device *pdev_dev;
3069ee9b 729 unsigned int mbox;
b2612722 730 unsigned int pf;
060e0c75 731 unsigned int flags;
2422d9a3 732 enum chip_type chip;
625ba2c2 733
625ba2c2
DM		 734 int msg_enable;
735
736 struct adapter_params params;
737 struct cxgb4_virt_res vres;
738 unsigned int swintr;
739
625ba2c2
DM		 740 struct {
741 unsigned short vec;
8cd18ac4 742 char desc[IFNAMSIZ + 10];
625ba2c2
DM		 743 } msix_info[MAX_INGQ + 1];
744
a4cfd929 745 struct doorbell_stats db_stats;
625ba2c2
DM		 746 struct sge sge;
747
748 struct net_device *port[MAX_NPORTS];
749 u8 chan_map[NCHAN]; /* channel -> port map */
750
793dad94 751 u32 filter_mode;
636f9d37
VP		 752 unsigned int l2t_start;
753 unsigned int l2t_end;
625ba2c2 754 struct l2t_data *l2t;
b5a02f50
AB		 755 unsigned int clipt_start;
756 unsigned int clipt_end;
757 struct clip_tbl *clipt;
625ba2c2
DM		 758 void *uld_handle[CXGB4_ULD_MAX];
759 struct list_head list_node;
01bcca68 760 struct list_head rcu_node;
625ba2c2 761
7714cb9e
VP		 762 void *iscsi_ppm;
763
625ba2c2
DM		 764 struct tid_info tids;
765 void **tid_release_head;
766 spinlock_t tid_release_lock;
29aaee65 767 struct workqueue_struct *workq;
625ba2c2 768 struct work_struct tid_release_task;
881806bc
VP		 769 struct work_struct db_full_task;
770 struct work_struct db_drop_task;
625ba2c2
DM		 771 bool tid_release_task_busy;
772
773 struct dentry *debugfs_root;
621a5f7a
VK		 774 bool use_bd; /* Use SGE Back Door intfc for reading SGE Contexts */
775 bool trace_rss; /* 1 implies that different RSS flit per filter is
8e3d04fd
HS		 776 * used per filter else if 0 default RSS flit is
777 * used for all 4 filters.
778 */
625ba2c2
DM		 779
780 spinlock_t stats_lock;
fc5ab020 781 spinlock_t win0_lock ____cacheline_aligned_in_smp;
625ba2c2
DM		 782};
783
f2b7e78d
VP		 784/* Defined bit width of user definable filter tuples
785 */
786#define ETHTYPE_BITWIDTH 16
787#define FRAG_BITWIDTH 1
788#define MACIDX_BITWIDTH 9
789#define FCOE_BITWIDTH 1
790#define IPORT_BITWIDTH 3
791#define MATCHTYPE_BITWIDTH 3
792#define PROTO_BITWIDTH 8
793#define TOS_BITWIDTH 8
794#define PF_BITWIDTH 8
795#define VF_BITWIDTH 8
796#define IVLAN_BITWIDTH 16
797#define OVLAN_BITWIDTH 16
798
799/* Filter matching rules. These consist of a set of ingress packet field
800 * (value, mask) tuples. The associated ingress packet field matches the
801 * tuple when ((field & mask) == value). (Thus a wildcard "don't care" field
802 * rule can be constructed by specifying a tuple of (0, 0).) A filter rule
803 * matches an ingress packet when all of the individual individual field
804 * matching rules are true.
805 *
806 * Partial field masks are always valid, however, while it may be easy to
807 * understand their meanings for some fields (e.g. IP address to match a
808 * subnet), for others making sensible partial masks is less intuitive (e.g.
809 * MPS match type) ...
810 *
811 * Most of the following data structures are modeled on T4 capabilities.
812 * Drivers for earlier chips use the subsets which make sense for those chips.
813 * We really need to come up with a hardware-independent mechanism to
814 * represent hardware filter capabilities ...
815 */
816struct ch_filter_tuple {
817 /* Compressed header matching field rules. The TP_VLAN_PRI_MAP
818 * register selects which of these fields will participate in the
819 * filter match rules -- up to a maximum of 36 bits. Because
820 * TP_VLAN_PRI_MAP is a global register, all filters must use the same
821 * set of fields.
822 */
823 uint32_t ethtype:ETHTYPE_BITWIDTH; /* Ethernet type */
824 uint32_t frag:FRAG_BITWIDTH; /* IP fragmentation header */
825 uint32_t ivlan_vld:1; /* inner VLAN valid */
826 uint32_t ovlan_vld:1; /* outer VLAN valid */
827 uint32_t pfvf_vld:1; /* PF/VF valid */
828 uint32_t macidx:MACIDX_BITWIDTH; /* exact match MAC index */
829 uint32_t fcoe:FCOE_BITWIDTH; /* FCoE packet */
830 uint32_t iport:IPORT_BITWIDTH; /* ingress port */
831 uint32_t matchtype:MATCHTYPE_BITWIDTH; /* MPS match type */
832 uint32_t proto:PROTO_BITWIDTH; /* protocol type */
833 uint32_t tos:TOS_BITWIDTH; /* TOS/Traffic Type */
834 uint32_t pf:PF_BITWIDTH; /* PCI-E PF ID */
835 uint32_t vf:VF_BITWIDTH; /* PCI-E VF ID */
836 uint32_t ivlan:IVLAN_BITWIDTH; /* inner VLAN */
837 uint32_t ovlan:OVLAN_BITWIDTH; /* outer VLAN */
838
839 /* Uncompressed header matching field rules. These are always
840 * available for field rules.
841 */
842 uint8_t lip[16]; /* local IP address (IPv4 in [3:0]) */
843 uint8_t fip[16]; /* foreign IP address (IPv4 in [3:0]) */
844 uint16_t lport; /* local port */
845 uint16_t fport; /* foreign port */
846};
847
848/* A filter ioctl command.
849 */
850struct ch_filter_specification {
851 /* Administrative fields for filter.
852 */
853 uint32_t hitcnts:1; /* count filter hits in TCB */
854 uint32_t prio:1; /* filter has priority over active/server */
855
856 /* Fundamental filter typing. This is the one element of filter
857 * matching that doesn't exist as a (value, mask) tuple.
858 */
859 uint32_t type:1; /* 0 => IPv4, 1 => IPv6 */
860
861 /* Packet dispatch information. Ingress packets which match the
862 * filter rules will be dropped, passed to the host or switched back
863 * out as egress packets.
864 */
865 uint32_t action:2; /* drop, pass, switch */
866
867 uint32_t rpttid:1; /* report TID in RSS hash field */
868
869 uint32_t dirsteer:1; /* 0 => RSS, 1 => steer to iq */
870 uint32_t iq:10; /* ingress queue */
871
872 uint32_t maskhash:1; /* dirsteer=0: store RSS hash in TCB */
873 uint32_t dirsteerhash:1;/* dirsteer=1: 0 => TCB contains RSS hash */
874 /* 1 => TCB contains IQ ID */
875
876 /* Switch proxy/rewrite fields. An ingress packet which matches a
877 * filter with "switch" set will be looped back out as an egress
878 * packet -- potentially with some Ethernet header rewriting.
879 */
880 uint32_t eport:2; /* egress port to switch packet out */
881 uint32_t newdmac:1; /* rewrite destination MAC address */
882 uint32_t newsmac:1; /* rewrite source MAC address */
883 uint32_t newvlan:2; /* rewrite VLAN Tag */
884 uint8_t dmac[ETH_ALEN]; /* new destination MAC address */
885 uint8_t smac[ETH_ALEN]; /* new source MAC address */
886 uint16_t vlan; /* VLAN Tag to insert */
887
888 /* Filter rule value/mask pairs.
889 */
890 struct ch_filter_tuple val;
891 struct ch_filter_tuple mask;
892};
893
894enum {
895 FILTER_PASS = 0, /* default */
896 FILTER_DROP,
897 FILTER_SWITCH
898};
899
900enum {
901 VLAN_NOCHANGE = 0, /* default */
902 VLAN_REMOVE,
903 VLAN_INSERT,
904 VLAN_REWRITE
905};
906
a4cfd929
HS		 907static inline int is_offload(const struct adapter *adap)
908{
909 return adap->params.offload;
910}
911
625ba2c2
DM		 912static inline u32 t4_read_reg(struct adapter *adap, u32 reg_addr)
913{
914 return readl(adap->regs + reg_addr);
915}
916
917static inline void t4_write_reg(struct adapter *adap, u32 reg_addr, u32 val)
918{
919 writel(val, adap->regs + reg_addr);
920}
921
922#ifndef readq
923static inline u64 readq(const volatile void __iomem *addr)
924{
925 return readl(addr) + ((u64)readl(addr + 4) << 32);
926}
927
928static inline void writeq(u64 val, volatile void __iomem *addr)
929{
930 writel(val, addr);
931 writel(val >> 32, addr + 4);
932}
933#endif
934
935static inline u64 t4_read_reg64(struct adapter *adap, u32 reg_addr)
936{
937 return readq(adap->regs + reg_addr);
938}
939
940static inline void t4_write_reg64(struct adapter *adap, u32 reg_addr, u64 val)
941{
942 writeq(val, adap->regs + reg_addr);
943}
944
098ef6c2
HS		 945/**
946 * t4_set_hw_addr - store a port's MAC address in SW
947 * @adapter: the adapter
948 * @port_idx: the port index
949 * @hw_addr: the Ethernet address
950 *
951 * Store the Ethernet address of the given port in SW. Called by the common
952 * code when it retrieves a port's Ethernet address from EEPROM.
953 */
954static inline void t4_set_hw_addr(struct adapter *adapter, int port_idx,
955 u8 hw_addr[])
956{
957 ether_addr_copy(adapter->port[port_idx]->dev_addr, hw_addr);
958 ether_addr_copy(adapter->port[port_idx]->perm_addr, hw_addr);
959}
960
625ba2c2
DM		 961/**
962 * netdev2pinfo - return the port_info structure associated with a net_device
963 * @dev: the netdev
964 *
965 * Return the struct port_info associated with a net_device
966 */
967static inline struct port_info *netdev2pinfo(const struct net_device *dev)
968{
969 return netdev_priv(dev);
970}
971
972/**
973 * adap2pinfo - return the port_info of a port
974 * @adap: the adapter
975 * @idx: the port index
976 *
977 * Return the port_info structure for the port of the given index.
978 */
979static inline struct port_info *adap2pinfo(struct adapter *adap, int idx)
980{
981 return netdev_priv(adap->port[idx]);
982}
983
984/**
985 * netdev2adap - return the adapter structure associated with a net_device
986 * @dev: the netdev
987 *
988 * Return the struct adapter associated with a net_device
989 */
990static inline struct adapter *netdev2adap(const struct net_device *dev)
991{
992 return netdev2pinfo(dev)->adapter;
993}
994
3a336cb1
HS		 995#ifdef CONFIG_NET_RX_BUSY_POLL
996static inline void cxgb_busy_poll_init_lock(struct sge_rspq *q)
997{
998 spin_lock_init(&q->bpoll_lock);
999 q->bpoll_state = CXGB_POLL_STATE_IDLE;
1000}
1001
1002static inline bool cxgb_poll_lock_napi(struct sge_rspq *q)
1003{
1004 bool rc = true;
1005
1006 spin_lock(&q->bpoll_lock);
1007 if (q->bpoll_state & CXGB_POLL_LOCKED) {
1008 q->bpoll_state |= CXGB_POLL_STATE_NAPI_YIELD;
1009 rc = false;
1010 } else {
1011 q->bpoll_state = CXGB_POLL_STATE_NAPI;
1012 }
1013 spin_unlock(&q->bpoll_lock);
1014 return rc;
1015}
1016
1017static inline bool cxgb_poll_unlock_napi(struct sge_rspq *q)
1018{
1019 bool rc = false;
1020
1021 spin_lock(&q->bpoll_lock);
1022 if (q->bpoll_state & CXGB_POLL_STATE_POLL_YIELD)
1023 rc = true;
1024 q->bpoll_state = CXGB_POLL_STATE_IDLE;
1025 spin_unlock(&q->bpoll_lock);
1026 return rc;
1027}
1028
1029static inline bool cxgb_poll_lock_poll(struct sge_rspq *q)
1030{
1031 bool rc = true;
1032
1033 spin_lock_bh(&q->bpoll_lock);
1034 if (q->bpoll_state & CXGB_POLL_LOCKED) {
1035 q->bpoll_state |= CXGB_POLL_STATE_POLL_YIELD;
1036 rc = false;
1037 } else {
1038 q->bpoll_state |= CXGB_POLL_STATE_POLL;
1039 }
1040 spin_unlock_bh(&q->bpoll_lock);
1041 return rc;
1042}
1043
1044static inline bool cxgb_poll_unlock_poll(struct sge_rspq *q)
1045{
1046 bool rc = false;
1047
1048 spin_lock_bh(&q->bpoll_lock);
1049 if (q->bpoll_state & CXGB_POLL_STATE_POLL_YIELD)
1050 rc = true;
1051 q->bpoll_state = CXGB_POLL_STATE_IDLE;
1052 spin_unlock_bh(&q->bpoll_lock);
1053 return rc;
1054}
1055
1056static inline bool cxgb_poll_busy_polling(struct sge_rspq *q)
1057{
1058 return q->bpoll_state & CXGB_POLL_USER_PEND;
1059}
1060#else
1061static inline void cxgb_busy_poll_init_lock(struct sge_rspq *q)
1062{
1063}
1064
1065static inline bool cxgb_poll_lock_napi(struct sge_rspq *q)
1066{
1067 return true;
1068}
1069
1070static inline bool cxgb_poll_unlock_napi(struct sge_rspq *q)
1071{
1072 return false;
1073}
1074
1075static inline bool cxgb_poll_lock_poll(struct sge_rspq *q)
1076{
1077 return false;
1078}
1079
1080static inline bool cxgb_poll_unlock_poll(struct sge_rspq *q)
1081{
1082 return false;
1083}
1084
1085static inline bool cxgb_poll_busy_polling(struct sge_rspq *q)
1086{
1087 return false;
1088}
1089#endif /* CONFIG_NET_RX_BUSY_POLL */
1090
812034f1
HS		 1091/* Return a version number to identify the type of adapter. The scheme is:
1092 * - bits 0..9: chip version
1093 * - bits 10..15: chip revision
1094 * - bits 16..23: register dump version
1095 */
1096static inline unsigned int mk_adap_vers(struct adapter *ap)
1097{
1098 return CHELSIO_CHIP_VERSION(ap->params.chip) |
1099 (CHELSIO_CHIP_RELEASE(ap->params.chip) << 10) | (1 << 16);
1100}
1101
1102/* Return a queue's interrupt hold-off time in us. 0 means no timer. */
1103static inline unsigned int qtimer_val(const struct adapter *adap,
1104 const struct sge_rspq *q)
1105{
1106 unsigned int idx = q->intr_params >> 1;
1107
1108 return idx < SGE_NTIMERS ? adap->sge.timer_val[idx] : 0;
1109}
1110
1111/* driver version & name used for ethtool_drvinfo */
1112extern char cxgb4_driver_name[];
1113extern const char cxgb4_driver_version[];
1114
625ba2c2
DM		 1115void t4_os_portmod_changed(const struct adapter *adap, int port_id);
1116void t4_os_link_changed(struct adapter *adap, int port_id, int link_stat);
1117
1118void *t4_alloc_mem(size_t size);
625ba2c2
DM		 1119
1120void t4_free_sge_resources(struct adapter *adap);
5fa76694 1121void t4_free_ofld_rxqs(struct adapter *adap, int n, struct sge_ofld_rxq *q);
625ba2c2
DM		 1122irq_handler_t t4_intr_handler(struct adapter *adap);
1123netdev_tx_t t4_eth_xmit(struct sk_buff *skb, struct net_device *dev);
1124int t4_ethrx_handler(struct sge_rspq *q, const __be64 *rsp,
1125 const struct pkt_gl *gl);
1126int t4_mgmt_tx(struct adapter *adap, struct sk_buff *skb);
1127int t4_ofld_send(struct adapter *adap, struct sk_buff *skb);
1128int t4_sge_alloc_rxq(struct adapter *adap, struct sge_rspq *iq, bool fwevtq,
1129 struct net_device *dev, int intr_idx,
2337ba42
VP		 1130 struct sge_fl *fl, rspq_handler_t hnd,
1131 rspq_flush_handler_t flush_handler, int cong);
625ba2c2
DM		 1132int t4_sge_alloc_eth_txq(struct adapter *adap, struct sge_eth_txq *txq,
1133 struct net_device *dev, struct netdev_queue *netdevq,
1134 unsigned int iqid);
1135int t4_sge_alloc_ctrl_txq(struct adapter *adap, struct sge_ctrl_txq *txq,
1136 struct net_device *dev, unsigned int iqid,
1137 unsigned int cmplqid);
1138int t4_sge_alloc_ofld_txq(struct adapter *adap, struct sge_ofld_txq *txq,
1139 struct net_device *dev, unsigned int iqid);
1140irqreturn_t t4_sge_intr_msix(int irq, void *cookie);
52367a76 1141int t4_sge_init(struct adapter *adap);
625ba2c2
DM		 1142void t4_sge_start(struct adapter *adap);
1143void t4_sge_stop(struct adapter *adap);
3a336cb1 1144int cxgb_busy_poll(struct napi_struct *napi);
812034f1
HS		 1145int cxgb4_set_rspq_intr_params(struct sge_rspq *q, unsigned int us,
1146 unsigned int cnt);
1147void cxgb4_set_ethtool_ops(struct net_device *netdev);
1148int cxgb4_write_rss(const struct port_info *pi, const u16 *queues);
3069ee9b 1149extern int dbfifo_int_thresh;
625ba2c2
DM		 1150
1151#define for_each_port(adapter, iter) \
1152 for (iter = 0; iter < (adapter)->params.nports; ++iter)
1153
9a4da2cd
VP		 1154static inline int is_bypass(struct adapter *adap)
1155{
1156 return adap->params.bypass;
1157}
1158
1159static inline int is_bypass_device(int device)
1160{
1161 /* this should be set based upon device capabilities */
1162 switch (device) {
1163 case 0x440b:
1164 case 0x440c:
1165 return 1;
1166 default:
1167 return 0;
1168 }
1169}
1170
01b69614
HS		 1171static inline int is_10gbt_device(int device)
1172{
1173 /* this should be set based upon device capabilities */
1174 switch (device) {
1175 case 0x4409:
1176 case 0x4486:
1177 return 1;
1178
1179 default:
1180 return 0;
1181 }
1182}
1183
625ba2c2
DM		 1184static inline unsigned int core_ticks_per_usec(const struct adapter *adap)
1185{
1186 return adap->params.vpd.cclk / 1000;
1187}
1188
1189static inline unsigned int us_to_core_ticks(const struct adapter *adap,
1190 unsigned int us)
1191{
1192 return (us * adap->params.vpd.cclk) / 1000;
1193}
1194
52367a76
VP		 1195static inline unsigned int core_ticks_to_us(const struct adapter *adapter,
1196 unsigned int ticks)
1197{
1198 /* add Core Clock / 2 to round ticks to nearest uS */
1199 return ((ticks * 1000 + adapter->params.vpd.cclk/2) /
1200 adapter->params.vpd.cclk);
1201}
1202
625ba2c2
DM		 1203void t4_set_reg_field(struct adapter *adap, unsigned int addr, u32 mask,
1204 u32 val);
1205
01b69614
HS		 1206int t4_wr_mbox_meat_timeout(struct adapter *adap, int mbox, const void *cmd,
1207 int size, void *rpl, bool sleep_ok, int timeout);
625ba2c2
DM		 1208int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size,
1209 void *rpl, bool sleep_ok);
1210
01b69614
HS		 1211static inline int t4_wr_mbox_timeout(struct adapter *adap, int mbox,
1212 const void *cmd, int size, void *rpl,
1213 int timeout)
1214{
1215 return t4_wr_mbox_meat_timeout(adap, mbox, cmd, size, rpl, true,
1216 timeout);
1217}
1218
625ba2c2
DM		 1219static inline int t4_wr_mbox(struct adapter *adap, int mbox, const void *cmd,
1220 int size, void *rpl)
1221{
1222 return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, true);
1223}
1224
1225static inline int t4_wr_mbox_ns(struct adapter *adap, int mbox, const void *cmd,
1226 int size, void *rpl)
1227{
1228 return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, false);
1229}
1230
13ee15d3
VP		 1231void t4_write_indirect(struct adapter *adap, unsigned int addr_reg,
1232 unsigned int data_reg, const u32 *vals,
1233 unsigned int nregs, unsigned int start_idx);
f2b7e78d
VP		 1234void t4_read_indirect(struct adapter *adap, unsigned int addr_reg,
1235 unsigned int data_reg, u32 *vals, unsigned int nregs,
1236 unsigned int start_idx);
0abfd152 1237void t4_hw_pci_read_cfg4(struct adapter *adapter, int reg, u32 *val);
f2b7e78d
VP		 1238
1239struct fw_filter_wr;
1240
625ba2c2
DM		 1241void t4_intr_enable(struct adapter *adapter);
1242void t4_intr_disable(struct adapter *adapter);
625ba2c2
DM		 1243int t4_slow_intr_handler(struct adapter *adapter);
1244
8203b509 1245int t4_wait_dev_ready(void __iomem *regs);
4036da90 1246int t4_link_l1cfg(struct adapter *adap, unsigned int mbox, unsigned int port,
625ba2c2
DM		 1247 struct link_config *lc);
1248int t4_restart_aneg(struct adapter *adap, unsigned int mbox, unsigned int port);
fc5ab020 1249
b562fc37
HS		 1250u32 t4_read_pcie_cfg4(struct adapter *adap, int reg);
1251u32 t4_get_util_window(struct adapter *adap);
1252void t4_setup_memwin(struct adapter *adap, u32 memwin_base, u32 window);
1253
fc5ab020
HS		 1254#define T4_MEMORY_WRITE 0
1255#define T4_MEMORY_READ 1
1256int t4_memory_rw(struct adapter *adap, int win, int mtype, u32 addr, u32 len,
f01aa633 1257 void *buf, int dir);
fc5ab020
HS		 1258static inline int t4_memory_write(struct adapter *adap, int mtype, u32 addr,
1259 u32 len, __be32 *buf)
1260{
1261 return t4_memory_rw(adap, 0, mtype, addr, len, buf, 0);
1262}
1263
812034f1
HS		 1264unsigned int t4_get_regs_len(struct adapter *adapter);
1265void t4_get_regs(struct adapter *adap, void *buf, size_t buf_size);
1266
625ba2c2 1267int t4_seeprom_wp(struct adapter *adapter, bool enable);
098ef6c2
HS		 1268int t4_get_raw_vpd_params(struct adapter *adapter, struct vpd_params *p);
1269int t4_get_vpd_params(struct adapter *adapter, struct vpd_params *p);
49216c1c
HS		 1270int t4_read_flash(struct adapter *adapter, unsigned int addr,
1271 unsigned int nwords, u32 *data, int byte_oriented);
625ba2c2 1272int t4_load_fw(struct adapter *adapter, const u8 *fw_data, unsigned int size);
01b69614
HS		 1273int t4_load_phy_fw(struct adapter *adap,
1274 int win, spinlock_t *lock,
1275 int (*phy_fw_version)(const u8 *, size_t),
1276 const u8 *phy_fw_data, size_t phy_fw_size);
1277int t4_phy_fw_ver(struct adapter *adap, int *phy_fw_ver);
49216c1c 1278int t4_fwcache(struct adapter *adap, enum fw_params_param_dev_fwcache op);
22c0b963
HS		 1279int t4_fw_upgrade(struct adapter *adap, unsigned int mbox,
1280 const u8 *fw_data, unsigned int size, int force);
acac5962 1281int t4_fl_pkt_align(struct adapter *adap);
636f9d37 1282unsigned int t4_flash_cfg_addr(struct adapter *adapter);
a69265e9 1283int t4_check_fw_version(struct adapter *adap);
16e47624
HS		 1284int t4_get_fw_version(struct adapter *adapter, u32 *vers);
1285int t4_get_tp_version(struct adapter *adapter, u32 *vers);
ba3f8cd5 1286int t4_get_exprom_version(struct adapter *adapter, u32 *vers);
16e47624
HS		 1287int t4_prep_fw(struct adapter *adap, struct fw_info *fw_info,
1288 const u8 *fw_data, unsigned int fw_size,
1289 struct fw_hdr *card_fw, enum dev_state state, int *reset);
625ba2c2 1290int t4_prep_adapter(struct adapter *adapter);
e85c9a7a
HS		 1291
1292enum t4_bar2_qtype { T4_BAR2_QTYPE_EGRESS, T4_BAR2_QTYPE_INGRESS };
b2612722 1293int t4_bar2_sge_qregs(struct adapter *adapter,
e85c9a7a
HS		 1294 unsigned int qid,
1295 enum t4_bar2_qtype qtype,
66cf188e 1296 int user,
e85c9a7a
HS		 1297 u64 *pbar2_qoffset,
1298 unsigned int *pbar2_qid);
1299
dc9daab2
HS		 1300unsigned int qtimer_val(const struct adapter *adap,
1301 const struct sge_rspq *q);
ae469b68
HS		 1302
1303int t4_init_devlog_params(struct adapter *adapter);
e85c9a7a 1304int t4_init_sge_params(struct adapter *adapter);
dcf7b6f5
KS		 1305int t4_init_tp_params(struct adapter *adap);
1306int t4_filter_field_shift(const struct adapter *adap, int filter_sel);
c035e183 1307int t4_init_rss_mode(struct adapter *adap, int mbox);
625ba2c2
DM		 1308int t4_port_init(struct adapter *adap, int mbox, int pf, int vf);
1309void t4_fatal_err(struct adapter *adapter);
625ba2c2
DM		 1310int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid,
1311 int start, int n, const u16 *rspq, unsigned int nrspq);
1312int t4_config_glbl_rss(struct adapter *adapter, int mbox, unsigned int mode,
1313 unsigned int flags);
c035e183
HS		 1314int t4_config_vi_rss(struct adapter *adapter, int mbox, unsigned int viid,
1315 unsigned int flags, unsigned int defq);
688ea5fe
HS		 1316int t4_read_rss(struct adapter *adapter, u16 *entries);
1317void t4_read_rss_key(struct adapter *adapter, u32 *key);
1318void t4_write_rss_key(struct adapter *adap, const u32 *key, int idx);
1319void t4_read_rss_pf_config(struct adapter *adapter, unsigned int index,
1320 u32 *valp);
1321void t4_read_rss_vf_config(struct adapter *adapter, unsigned int index,
1322 u32 *vfl, u32 *vfh);
1323u32 t4_read_rss_pf_map(struct adapter *adapter);
1324u32 t4_read_rss_pf_mask(struct adapter *adapter);
1325
145ef8a5 1326unsigned int t4_get_mps_bg_map(struct adapter *adapter, int idx);
b3bbe36a
HS		 1327void t4_pmtx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]);
1328void t4_pmrx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]);
e5f0e43b
HS		 1329int t4_read_cim_ibq(struct adapter *adap, unsigned int qid, u32 *data,
1330 size_t n);
c778af7d
HS		 1331int t4_read_cim_obq(struct adapter *adap, unsigned int qid, u32 *data,
1332 size_t n);
f1ff24aa
HS		 1333int t4_cim_read(struct adapter *adap, unsigned int addr, unsigned int n,
1334 unsigned int *valp);
1335int t4_cim_write(struct adapter *adap, unsigned int addr, unsigned int n,
1336 const unsigned int *valp);
1337int t4_cim_read_la(struct adapter *adap, u32 *la_buf, unsigned int *wrptr);
19689609
HS		 1338void t4_cim_read_pif_la(struct adapter *adap, u32 *pif_req, u32 *pif_rsp,
1339 unsigned int *pif_req_wrptr,
1340 unsigned int *pif_rsp_wrptr);
26fae93f 1341void t4_cim_read_ma_la(struct adapter *adap, u32 *ma_req, u32 *ma_rsp);
74b3092c 1342void t4_read_cimq_cfg(struct adapter *adap, u16 *base, u16 *size, u16 *thres);
72aca4bf 1343const char *t4_get_port_type_description(enum fw_port_type port_type);
625ba2c2 1344void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p);
a4cfd929
HS		 1345void t4_get_port_stats_offset(struct adapter *adap, int idx,
1346 struct port_stats *stats,
1347 struct port_stats *offset);
65046e84 1348void t4_get_lb_stats(struct adapter *adap, int idx, struct lb_port_stats *p);
625ba2c2 1349void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log);
bad43792 1350void t4_read_cong_tbl(struct adapter *adap, u16 incr[NMTUS][NCCTRL_WIN]);
636f9d37
VP		 1351void t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr,
1352 unsigned int mask, unsigned int val);
2d277b3b 1353void t4_tp_read_la(struct adapter *adap, u64 *la_buf, unsigned int *wrptr);
a4cfd929 1354void t4_tp_get_err_stats(struct adapter *adap, struct tp_err_stats *st);
a6222975 1355void t4_tp_get_cpl_stats(struct adapter *adap, struct tp_cpl_stats *st);
a4cfd929
HS		 1356void t4_tp_get_rdma_stats(struct adapter *adap, struct tp_rdma_stats *st);
1357void t4_get_usm_stats(struct adapter *adap, struct tp_usm_stats *st);
625ba2c2
DM		 1358void t4_tp_get_tcp_stats(struct adapter *adap, struct tp_tcp_stats *v4,
1359 struct tp_tcp_stats *v6);
a6222975
HS		 1360void t4_get_fcoe_stats(struct adapter *adap, unsigned int idx,
1361 struct tp_fcoe_stats *st);
625ba2c2
DM		 1362void t4_load_mtus(struct adapter *adap, const unsigned short *mtus,
1363 const unsigned short *alpha, const unsigned short *beta);
1364
797ff0f5
HS		 1365void t4_ulprx_read_la(struct adapter *adap, u32 *la_buf);
1366
7864026b 1367void t4_get_chan_txrate(struct adapter *adap, u64 *nic_rate, u64 *ofld_rate);
f2b7e78d
VP		 1368void t4_mk_filtdelwr(unsigned int ftid, struct fw_filter_wr *wr, int qid);
1369
625ba2c2
DM		 1370void t4_wol_magic_enable(struct adapter *adap, unsigned int port,
1371 const u8 *addr);
1372int t4_wol_pat_enable(struct adapter *adap, unsigned int port, unsigned int map,
1373 u64 mask0, u64 mask1, unsigned int crc, bool enable);
1374
1375int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox,
1376 enum dev_master master, enum dev_state *state);
1377int t4_fw_bye(struct adapter *adap, unsigned int mbox);
1378int t4_early_init(struct adapter *adap, unsigned int mbox);
1379int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset);
636f9d37
VP		 1380int t4_fixup_host_params(struct adapter *adap, unsigned int page_size,
1381 unsigned int cache_line_size);
1382int t4_fw_initialize(struct adapter *adap, unsigned int mbox);
625ba2c2
DM		 1383int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
1384 unsigned int vf, unsigned int nparams, const u32 *params,
1385 u32 *val);
01b69614
HS		 1386int t4_query_params_rw(struct adapter *adap, unsigned int mbox, unsigned int pf,
1387 unsigned int vf, unsigned int nparams, const u32 *params,
1388 u32 *val, int rw);
1389int t4_set_params_timeout(struct adapter *adap, unsigned int mbox,
1390 unsigned int pf, unsigned int vf,
1391 unsigned int nparams, const u32 *params,
1392 const u32 *val, int timeout);
625ba2c2
DM		 1393int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
1394 unsigned int vf, unsigned int nparams, const u32 *params,
1395 const u32 *val);
1396int t4_cfg_pfvf(struct adapter *adap, unsigned int mbox, unsigned int pf,
1397 unsigned int vf, unsigned int txq, unsigned int txq_eth_ctrl,
1398 unsigned int rxqi, unsigned int rxq, unsigned int tc,
1399 unsigned int vi, unsigned int cmask, unsigned int pmask,
1400 unsigned int nexact, unsigned int rcaps, unsigned int wxcaps);
1401int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port,
1402 unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac,
1403 unsigned int *rss_size);
4f3a0fcf
HS		 1404int t4_free_vi(struct adapter *adap, unsigned int mbox,
1405 unsigned int pf, unsigned int vf,
1406 unsigned int viid);
625ba2c2 1407int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid,
f8f5aafa
DM		 1408 int mtu, int promisc, int all_multi, int bcast, int vlanex,
1409 bool sleep_ok);
625ba2c2
DM		 1410int t4_alloc_mac_filt(struct adapter *adap, unsigned int mbox,
1411 unsigned int viid, bool free, unsigned int naddr,
1412 const u8 **addr, u16 *idx, u64 *hash, bool sleep_ok);
1413int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid,
1414 int idx, const u8 *addr, bool persist, bool add_smt);
1415int t4_set_addr_hash(struct adapter *adap, unsigned int mbox, unsigned int viid,
1416 bool ucast, u64 vec, bool sleep_ok);
688848b1
AB		 1417int t4_enable_vi_params(struct adapter *adap, unsigned int mbox,
1418 unsigned int viid, bool rx_en, bool tx_en, bool dcb_en);
625ba2c2
DM		 1419int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid,
1420 bool rx_en, bool tx_en);
1421int t4_identify_port(struct adapter *adap, unsigned int mbox, unsigned int viid,
1422 unsigned int nblinks);
1423int t4_mdio_rd(struct adapter *adap, unsigned int mbox, unsigned int phy_addr,
1424 unsigned int mmd, unsigned int reg, u16 *valp);
1425int t4_mdio_wr(struct adapter *adap, unsigned int mbox, unsigned int phy_addr,
1426 unsigned int mmd, unsigned int reg, u16 val);
625ba2c2
DM		 1427int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
1428 unsigned int vf, unsigned int iqtype, unsigned int iqid,
1429 unsigned int fl0id, unsigned int fl1id);
1430int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
1431 unsigned int vf, unsigned int eqid);
1432int t4_ctrl_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
1433 unsigned int vf, unsigned int eqid);
1434int t4_ofld_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
1435 unsigned int vf, unsigned int eqid);
5d700ecb 1436int t4_sge_ctxt_flush(struct adapter *adap, unsigned int mbox);
625ba2c2 1437int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl);
881806bc
VP		 1438void t4_db_full(struct adapter *adapter);
1439void t4_db_dropped(struct adapter *adapter);
8e3d04fd
HS		 1440int t4_set_trace_filter(struct adapter *adapter, const struct trace_params *tp,
1441 int filter_index, int enable);
1442void t4_get_trace_filter(struct adapter *adapter, struct trace_params *tp,
1443 int filter_index, int *enabled);
8caa1e84
VP		 1444int t4_fwaddrspace_write(struct adapter *adap, unsigned int mbox,
1445 u32 addr, u32 val);
68bce192 1446void t4_sge_decode_idma_state(struct adapter *adapter, int state);
fd88b31a 1447void t4_free_mem(void *addr);
a3bfb617
HS		 1448void t4_idma_monitor_init(struct adapter *adapter,
1449 struct sge_idma_monitor_state *idma);
1450void t4_idma_monitor(struct adapter *adapter,
1451 struct sge_idma_monitor_state *idma,
1452 int hz, int ticks);
625ba2c2 1453#endif /* __CXGB4_H__ */
Linux kernel - Deliverables
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