projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
cxgb4: Fix some small bugs in t4_sge_init_soft() when our Page Size is 64KB
[deliverable/linux.git] / drivers / net / ethernet / chelsio / cxgb4 / cxgb4.h
CommitLineData
625ba2c2
DM		 1/*
2 * This file is part of the Chelsio T4 Ethernet driver for Linux.
3 *
4 * Copyright (c) 2003-2010 Chelsio Communications, Inc. All rights reserved.
5 *
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
11 *
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
14 * conditions are met:
15 *
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
18 * disclaimer.
19 *
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
24 *
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
32 * SOFTWARE.
33 */
34
35#ifndef __CXGB4_H__
36#define __CXGB4_H__
37
dca4faeb
VP		 38#include "t4_hw.h"
39
625ba2c2
DM		 40#include <linux/bitops.h>
41#include <linux/cache.h>
42#include <linux/interrupt.h>
43#include <linux/list.h>
44#include <linux/netdevice.h>
45#include <linux/pci.h>
46#include <linux/spinlock.h>
47#include <linux/timer.h>
c0b8b992 48#include <linux/vmalloc.h>
625ba2c2
DM		 49#include <asm/io.h>
50#include "cxgb4_uld.h"
625ba2c2 51
16e47624 52#define T4FW_VERSION_MAJOR 0x01
451cd14e
HS		 53#define T4FW_VERSION_MINOR 0x09
54#define T4FW_VERSION_MICRO 0x17
16e47624 55#define T4FW_VERSION_BUILD 0x00
625ba2c2 56
16e47624 57#define T5FW_VERSION_MAJOR 0x01
451cd14e
HS		 58#define T5FW_VERSION_MINOR 0x09
59#define T5FW_VERSION_MICRO 0x17
16e47624 60#define T5FW_VERSION_BUILD 0x00
2422d9a3 61
3069ee9b
VP		 62#define CH_WARN(adap, fmt, ...) dev_warn(adap->pdev_dev, fmt, ## __VA_ARGS__)
63
625ba2c2
DM		 64enum {
65 MAX_NPORTS = 4, /* max # of ports */
47d54d65 66 SERNUM_LEN = 24, /* Serial # length */
625ba2c2
DM		 67 EC_LEN = 16, /* E/C length */
68 ID_LEN = 16, /* ID length */
a94cd705 69 PN_LEN = 16, /* Part Number length */
625ba2c2
DM		 70};
71
72enum {
73 MEM_EDC0,
74 MEM_EDC1,
2422d9a3
SR		 75 MEM_MC,
76 MEM_MC0 = MEM_MC,
77 MEM_MC1
625ba2c2
DM		 78};
79
3069ee9b 80enum {
3eb4afbf
VP		 81 MEMWIN0_APERTURE = 2048,
82 MEMWIN0_BASE = 0x1b800,
3069ee9b
VP		 83 MEMWIN1_APERTURE = 32768,
84 MEMWIN1_BASE = 0x28000,
2422d9a3 85 MEMWIN1_BASE_T5 = 0x52000,
3eb4afbf
VP		 86 MEMWIN2_APERTURE = 65536,
87 MEMWIN2_BASE = 0x30000,
2422d9a3 88 MEMWIN2_BASE_T5 = 0x54000,
3069ee9b
VP		 89};
90
625ba2c2
DM		 91enum dev_master {
92 MASTER_CANT,
93 MASTER_MAY,
94 MASTER_MUST
95};
96
97enum dev_state {
98 DEV_STATE_UNINIT,
99 DEV_STATE_INIT,
100 DEV_STATE_ERR
101};
102
103enum {
104 PAUSE_RX = 1 << 0,
105 PAUSE_TX = 1 << 1,
106 PAUSE_AUTONEG = 1 << 2
107};
108
109struct port_stats {
110 u64 tx_octets; /* total # of octets in good frames */
111 u64 tx_frames; /* all good frames */
112 u64 tx_bcast_frames; /* all broadcast frames */
113 u64 tx_mcast_frames; /* all multicast frames */
114 u64 tx_ucast_frames; /* all unicast frames */
115 u64 tx_error_frames; /* all error frames */
116
117 u64 tx_frames_64; /* # of Tx frames in a particular range */
118 u64 tx_frames_65_127;
119 u64 tx_frames_128_255;
120 u64 tx_frames_256_511;
121 u64 tx_frames_512_1023;
122 u64 tx_frames_1024_1518;
123 u64 tx_frames_1519_max;
124
125 u64 tx_drop; /* # of dropped Tx frames */
126 u64 tx_pause; /* # of transmitted pause frames */
127 u64 tx_ppp0; /* # of transmitted PPP prio 0 frames */
128 u64 tx_ppp1; /* # of transmitted PPP prio 1 frames */
129 u64 tx_ppp2; /* # of transmitted PPP prio 2 frames */
130 u64 tx_ppp3; /* # of transmitted PPP prio 3 frames */
131 u64 tx_ppp4; /* # of transmitted PPP prio 4 frames */
132 u64 tx_ppp5; /* # of transmitted PPP prio 5 frames */
133 u64 tx_ppp6; /* # of transmitted PPP prio 6 frames */
134 u64 tx_ppp7; /* # of transmitted PPP prio 7 frames */
135
136 u64 rx_octets; /* total # of octets in good frames */
137 u64 rx_frames; /* all good frames */
138 u64 rx_bcast_frames; /* all broadcast frames */
139 u64 rx_mcast_frames; /* all multicast frames */
140 u64 rx_ucast_frames; /* all unicast frames */
141 u64 rx_too_long; /* # of frames exceeding MTU */
142 u64 rx_jabber; /* # of jabber frames */
143 u64 rx_fcs_err; /* # of received frames with bad FCS */
144 u64 rx_len_err; /* # of received frames with length error */
145 u64 rx_symbol_err; /* symbol errors */
146 u64 rx_runt; /* # of short frames */
147
148 u64 rx_frames_64; /* # of Rx frames in a particular range */
149 u64 rx_frames_65_127;
150 u64 rx_frames_128_255;
151 u64 rx_frames_256_511;
152 u64 rx_frames_512_1023;
153 u64 rx_frames_1024_1518;
154 u64 rx_frames_1519_max;
155
156 u64 rx_pause; /* # of received pause frames */
157 u64 rx_ppp0; /* # of received PPP prio 0 frames */
158 u64 rx_ppp1; /* # of received PPP prio 1 frames */
159 u64 rx_ppp2; /* # of received PPP prio 2 frames */
160 u64 rx_ppp3; /* # of received PPP prio 3 frames */
161 u64 rx_ppp4; /* # of received PPP prio 4 frames */
162 u64 rx_ppp5; /* # of received PPP prio 5 frames */
163 u64 rx_ppp6; /* # of received PPP prio 6 frames */
164 u64 rx_ppp7; /* # of received PPP prio 7 frames */
165
166 u64 rx_ovflow0; /* drops due to buffer-group 0 overflows */
167 u64 rx_ovflow1; /* drops due to buffer-group 1 overflows */
168 u64 rx_ovflow2; /* drops due to buffer-group 2 overflows */
169 u64 rx_ovflow3; /* drops due to buffer-group 3 overflows */
170 u64 rx_trunc0; /* buffer-group 0 truncated packets */
171 u64 rx_trunc1; /* buffer-group 1 truncated packets */
172 u64 rx_trunc2; /* buffer-group 2 truncated packets */
173 u64 rx_trunc3; /* buffer-group 3 truncated packets */
174};
175
176struct lb_port_stats {
177 u64 octets;
178 u64 frames;
179 u64 bcast_frames;
180 u64 mcast_frames;
181 u64 ucast_frames;
182 u64 error_frames;
183
184 u64 frames_64;
185 u64 frames_65_127;
186 u64 frames_128_255;
187 u64 frames_256_511;
188 u64 frames_512_1023;
189 u64 frames_1024_1518;
190 u64 frames_1519_max;
191
192 u64 drop;
193
194 u64 ovflow0;
195 u64 ovflow1;
196 u64 ovflow2;
197 u64 ovflow3;
198 u64 trunc0;
199 u64 trunc1;
200 u64 trunc2;
201 u64 trunc3;
202};
203
204struct tp_tcp_stats {
205 u32 tcpOutRsts;
206 u64 tcpInSegs;
207 u64 tcpOutSegs;
208 u64 tcpRetransSegs;
209};
210
211struct tp_err_stats {
212 u32 macInErrs[4];
213 u32 hdrInErrs[4];
214 u32 tcpInErrs[4];
215 u32 tnlCongDrops[4];
216 u32 ofldChanDrops[4];
217 u32 tnlTxDrops[4];
218 u32 ofldVlanDrops[4];
219 u32 tcp6InErrs[4];
220 u32 ofldNoNeigh;
221 u32 ofldCongDefer;
222};
223
224struct tp_params {
225 unsigned int ntxchan; /* # of Tx channels */
226 unsigned int tre; /* log2 of core clocks per TP tick */
dca4faeb
VP		 227 unsigned short tx_modq_map; /* TX modulation scheduler queue to */
228 /* channel map */
636f9d37
VP		 229
230 uint32_t dack_re; /* DACK timer resolution */
231 unsigned short tx_modq[NCHAN]; /* channel to modulation queue map */
dcf7b6f5
KS		 232
233 u32 vlan_pri_map; /* cached TP_VLAN_PRI_MAP */
234 u32 ingress_config; /* cached TP_INGRESS_CONFIG */
235
236 /* TP_VLAN_PRI_MAP Compressed Filter Tuple field offsets. This is a
237 * subset of the set of fields which may be present in the Compressed
238 * Filter Tuple portion of filters and TCP TCB connections. The
239 * fields which are present are controlled by the TP_VLAN_PRI_MAP.
240 * Since a variable number of fields may or may not be present, their
241 * shifted field positions within the Compressed Filter Tuple may
242 * vary, or not even be present if the field isn't selected in
243 * TP_VLAN_PRI_MAP. Since some of these fields are needed in various
244 * places we store their offsets here, or a -1 if the field isn't
245 * present.
246 */
247 int vlan_shift;
248 int vnic_shift;
249 int port_shift;
250 int protocol_shift;
625ba2c2
DM		 251};
252
253struct vpd_params {
254 unsigned int cclk;
255 u8 ec[EC_LEN + 1];
256 u8 sn[SERNUM_LEN + 1];
257 u8 id[ID_LEN + 1];
a94cd705 258 u8 pn[PN_LEN + 1];
625ba2c2
DM		 259};
260
261struct pci_params {
262 unsigned char speed;
263 unsigned char width;
264};
265
d14807dd
HS		 266#define CHELSIO_CHIP_CODE(version, revision) (((version) << 4) | (revision))
267#define CHELSIO_CHIP_FPGA 0x100
268#define CHELSIO_CHIP_VERSION(code) (((code) >> 4) & 0xf)
269#define CHELSIO_CHIP_RELEASE(code) ((code) & 0xf)
270
271#define CHELSIO_T4 0x4
272#define CHELSIO_T5 0x5
273
274enum chip_type {
275 T4_A1 = CHELSIO_CHIP_CODE(CHELSIO_T4, 1),
276 T4_A2 = CHELSIO_CHIP_CODE(CHELSIO_T4, 2),
277 T4_FIRST_REV = T4_A1,
278 T4_LAST_REV = T4_A2,
279
280 T5_A0 = CHELSIO_CHIP_CODE(CHELSIO_T5, 0),
281 T5_A1 = CHELSIO_CHIP_CODE(CHELSIO_T5, 1),
282 T5_FIRST_REV = T5_A0,
283 T5_LAST_REV = T5_A1,
284};
285
625ba2c2
DM		 286struct adapter_params {
287 struct tp_params tp;
288 struct vpd_params vpd;
289 struct pci_params pci;
290
900a6596
DM		 291 unsigned int sf_size; /* serial flash size in bytes */
292 unsigned int sf_nsec; /* # of flash sectors */
293 unsigned int sf_fw_start; /* start of FW image in flash */
294
625ba2c2
DM		 295 unsigned int fw_vers;
296 unsigned int tp_vers;
297 u8 api_vers[7];
298
299 unsigned short mtus[NMTUS];
300 unsigned short a_wnd[NCCTRL_WIN];
301 unsigned short b_wnd[NCCTRL_WIN];
302
303 unsigned char nports; /* # of ethernet ports */
304 unsigned char portvec;
d14807dd 305 enum chip_type chip; /* chip code */
625ba2c2
DM		 306 unsigned char offload;
307
9a4da2cd
VP		 308 unsigned char bypass;
309
625ba2c2 310 unsigned int ofldq_wr_cred;
1ac0f095 311 bool ulptx_memwrite_dsgl; /* use of T5 DSGL allowed */
625ba2c2
DM		 312};
313
16e47624
HS		 314#include "t4fw_api.h"
315
316#define FW_VERSION(chip) ( \
317 FW_HDR_FW_VER_MAJOR_GET(chip##FW_VERSION_MAJOR) | \
318 FW_HDR_FW_VER_MINOR_GET(chip##FW_VERSION_MINOR) | \
319 FW_HDR_FW_VER_MICRO_GET(chip##FW_VERSION_MICRO) | \
320 FW_HDR_FW_VER_BUILD_GET(chip##FW_VERSION_BUILD))
321#define FW_INTFVER(chip, intf) (FW_HDR_INTFVER_##intf)
322
323struct fw_info {
324 u8 chip;
325 char *fs_name;
326 char *fw_mod_name;
327 struct fw_hdr fw_hdr;
328};
329
330
625ba2c2
DM		 331struct trace_params {
332 u32 data[TRACE_LEN / 4];
333 u32 mask[TRACE_LEN / 4];
334 unsigned short snap_len;
335 unsigned short min_len;
336 unsigned char skip_ofst;
337 unsigned char skip_len;
338 unsigned char invert;
339 unsigned char port;
340};
341
342struct link_config {
343 unsigned short supported; /* link capabilities */
344 unsigned short advertising; /* advertised capabilities */
345 unsigned short requested_speed; /* speed user has requested */
346 unsigned short speed; /* actual link speed */
347 unsigned char requested_fc; /* flow control user has requested */
348 unsigned char fc; /* actual link flow control */
349 unsigned char autoneg; /* autonegotiating? */
350 unsigned char link_ok; /* link up? */
351};
352
353#define FW_LEN16(fw_struct) FW_CMD_LEN16(sizeof(fw_struct) / 16)
354
355enum {
356 MAX_ETH_QSETS = 32, /* # of Ethernet Tx/Rx queue sets */
357 MAX_OFLD_QSETS = 16, /* # of offload Tx/Rx queue sets */
358 MAX_CTRL_QUEUES = NCHAN, /* # of control Tx queues */
359 MAX_RDMA_QUEUES = NCHAN, /* # of streaming RDMA Rx queues */
360};
361
362enum {
363 MAX_EGRQ = 128, /* max # of egress queues, including FLs */
364 MAX_INGQ = 64 /* max # of interrupt-capable ingress queues */
365};
366
367struct adapter;
625ba2c2
DM		 368struct sge_rspq;
369
370struct port_info {
371 struct adapter *adapter;
625ba2c2
DM		 372 u16 viid;
373 s16 xact_addr_filt; /* index of exact MAC address filter */
374 u16 rss_size; /* size of VI's RSS table slice */
375 s8 mdio_addr;
376 u8 port_type;
377 u8 mod_type;
378 u8 port_id;
379 u8 tx_chan;
380 u8 lport; /* associated offload logical port */
625ba2c2
DM		 381 u8 nqsets; /* # of qsets */
382 u8 first_qset; /* index of first qset */
f796564a 383 u8 rss_mode;
625ba2c2 384 struct link_config link_cfg;
671b0060 385 u16 *rss;
625ba2c2
DM		 386};
387
625ba2c2
DM		 388struct dentry;
389struct work_struct;
390
391enum { /* adapter flags */
392 FULL_INIT_DONE = (1 << 0),
144be3d9
GS		 393 DEV_ENABLED = (1 << 1),
394 USING_MSI = (1 << 2),
395 USING_MSIX = (1 << 3),
625ba2c2 396 FW_OK = (1 << 4),
13ee15d3 397 RSS_TNLALLLOOKUP = (1 << 5),
52367a76
VP		 398 USING_SOFT_PARAMS = (1 << 6),
399 MASTER_PF = (1 << 7),
400 FW_OFLD_CONN = (1 << 9),
625ba2c2
DM		 401};
402
403struct rx_sw_desc;
404
405struct sge_fl { /* SGE free-buffer queue state */
406 unsigned int avail; /* # of available Rx buffers */
407 unsigned int pend_cred; /* new buffers since last FL DB ring */
408 unsigned int cidx; /* consumer index */
409 unsigned int pidx; /* producer index */
410 unsigned long alloc_failed; /* # of times buffer allocation failed */
411 unsigned long large_alloc_failed;
412 unsigned long starving;
413 /* RO fields */
414 unsigned int cntxt_id; /* SGE context id for the free list */
415 unsigned int size; /* capacity of free list */
416 struct rx_sw_desc *sdesc; /* address of SW Rx descriptor ring */
417 __be64 *desc; /* address of HW Rx descriptor ring */
418 dma_addr_t addr; /* bus address of HW ring start */
419};
420
421/* A packet gather list */
422struct pkt_gl {
e91b0f24 423 struct page_frag frags[MAX_SKB_FRAGS];
625ba2c2
DM		 424 void *va; /* virtual address of first byte */
425 unsigned int nfrags; /* # of fragments */
426 unsigned int tot_len; /* total length of fragments */
427};
428
429typedef int (*rspq_handler_t)(struct sge_rspq *q, const __be64 *rsp,
430 const struct pkt_gl *gl);
431
432struct sge_rspq { /* state for an SGE response queue */
433 struct napi_struct napi;
434 const __be64 *cur_desc; /* current descriptor in queue */
435 unsigned int cidx; /* consumer index */
436 u8 gen; /* current generation bit */
437 u8 intr_params; /* interrupt holdoff parameters */
438 u8 next_intr_params; /* holdoff params for next interrupt */
439 u8 pktcnt_idx; /* interrupt packet threshold */
440 u8 uld; /* ULD handling this queue */
441 u8 idx; /* queue index within its group */
442 int offset; /* offset into current Rx buffer */
443 u16 cntxt_id; /* SGE context id for the response q */
444 u16 abs_id; /* absolute SGE id for the response q */
445 __be64 *desc; /* address of HW response ring */
446 dma_addr_t phys_addr; /* physical address of the ring */
447 unsigned int iqe_len; /* entry size */
448 unsigned int size; /* capacity of response queue */
449 struct adapter *adap;
450 struct net_device *netdev; /* associated net device */
451 rspq_handler_t handler;
452};
453
454struct sge_eth_stats { /* Ethernet queue statistics */
455 unsigned long pkts; /* # of ethernet packets */
456 unsigned long lro_pkts; /* # of LRO super packets */
457 unsigned long lro_merged; /* # of wire packets merged by LRO */
458 unsigned long rx_cso; /* # of Rx checksum offloads */
459 unsigned long vlan_ex; /* # of Rx VLAN extractions */
460 unsigned long rx_drops; /* # of packets dropped due to no mem */
461};
462
463struct sge_eth_rxq { /* SW Ethernet Rx queue */
464 struct sge_rspq rspq;
465 struct sge_fl fl;
466 struct sge_eth_stats stats;
467} ____cacheline_aligned_in_smp;
468
469struct sge_ofld_stats { /* offload queue statistics */
470 unsigned long pkts; /* # of packets */
471 unsigned long imm; /* # of immediate-data packets */
472 unsigned long an; /* # of asynchronous notifications */
473 unsigned long nomem; /* # of responses deferred due to no mem */
474};
475
476struct sge_ofld_rxq { /* SW offload Rx queue */
477 struct sge_rspq rspq;
478 struct sge_fl fl;
479 struct sge_ofld_stats stats;
480} ____cacheline_aligned_in_smp;
481
482struct tx_desc {
483 __be64 flit[8];
484};
485
486struct tx_sw_desc;
487
488struct sge_txq {
489 unsigned int in_use; /* # of in-use Tx descriptors */
490 unsigned int size; /* # of descriptors */
491 unsigned int cidx; /* SW consumer index */
492 unsigned int pidx; /* producer index */
493 unsigned long stops; /* # of times q has been stopped */
494 unsigned long restarts; /* # of queue restarts */
495 unsigned int cntxt_id; /* SGE context id for the Tx q */
496 struct tx_desc *desc; /* address of HW Tx descriptor ring */
497 struct tx_sw_desc *sdesc; /* address of SW Tx descriptor ring */
498 struct sge_qstat *stat; /* queue status entry */
499 dma_addr_t phys_addr; /* physical address of the ring */
3069ee9b
VP		 500 spinlock_t db_lock;
501 int db_disabled;
502 unsigned short db_pidx;
22adfe0a 503 u64 udb;
625ba2c2
DM		 504};
505
506struct sge_eth_txq { /* state for an SGE Ethernet Tx queue */
507 struct sge_txq q;
508 struct netdev_queue *txq; /* associated netdev TX queue */
509 unsigned long tso; /* # of TSO requests */
510 unsigned long tx_cso; /* # of Tx checksum offloads */
511 unsigned long vlan_ins; /* # of Tx VLAN insertions */
512 unsigned long mapping_err; /* # of I/O MMU packet mapping errors */
513} ____cacheline_aligned_in_smp;
514
515struct sge_ofld_txq { /* state for an SGE offload Tx queue */
516 struct sge_txq q;
517 struct adapter *adap;
518 struct sk_buff_head sendq; /* list of backpressured packets */
519 struct tasklet_struct qresume_tsk; /* restarts the queue */
520 u8 full; /* the Tx ring is full */
521 unsigned long mapping_err; /* # of I/O MMU packet mapping errors */
522} ____cacheline_aligned_in_smp;
523
524struct sge_ctrl_txq { /* state for an SGE control Tx queue */
525 struct sge_txq q;
526 struct adapter *adap;
527 struct sk_buff_head sendq; /* list of backpressured packets */
528 struct tasklet_struct qresume_tsk; /* restarts the queue */
529 u8 full; /* the Tx ring is full */
530} ____cacheline_aligned_in_smp;
531
532struct sge {
533 struct sge_eth_txq ethtxq[MAX_ETH_QSETS];
534 struct sge_ofld_txq ofldtxq[MAX_OFLD_QSETS];
535 struct sge_ctrl_txq ctrlq[MAX_CTRL_QUEUES];
536
537 struct sge_eth_rxq ethrxq[MAX_ETH_QSETS];
538 struct sge_ofld_rxq ofldrxq[MAX_OFLD_QSETS];
539 struct sge_ofld_rxq rdmarxq[MAX_RDMA_QUEUES];
540 struct sge_rspq fw_evtq ____cacheline_aligned_in_smp;
541
542 struct sge_rspq intrq ____cacheline_aligned_in_smp;
543 spinlock_t intrq_lock;
544
545 u16 max_ethqsets; /* # of available Ethernet queue sets */
546 u16 ethqsets; /* # of active Ethernet queue sets */
547 u16 ethtxq_rover; /* Tx queue to clean up next */
548 u16 ofldqsets; /* # of active offload queue sets */
549 u16 rdmaqs; /* # of available RDMA Rx queues */
550 u16 ofld_rxq[MAX_OFLD_QSETS];
551 u16 rdma_rxq[NCHAN];
552 u16 timer_val[SGE_NTIMERS];
553 u8 counter_val[SGE_NCOUNTERS];
52367a76
VP		 554 u32 fl_pg_order; /* large page allocation size */
555 u32 stat_len; /* length of status page at ring end */
556 u32 pktshift; /* padding between CPL & packet data */
557 u32 fl_align; /* response queue message alignment */
558 u32 fl_starve_thres; /* Free List starvation threshold */
625ba2c2
DM		 559 unsigned int starve_thres;
560 u8 idma_state[2];
e46dab4d
DM		 561 unsigned int egr_start;
562 unsigned int ingr_start;
625ba2c2
DM		 563 void *egr_map[MAX_EGRQ]; /* qid->queue egress queue map */
564 struct sge_rspq *ingr_map[MAX_INGQ]; /* qid->queue ingress queue map */
565 DECLARE_BITMAP(starving_fl, MAX_EGRQ);
566 DECLARE_BITMAP(txq_maperr, MAX_EGRQ);
567 struct timer_list rx_timer; /* refills starving FLs */
568 struct timer_list tx_timer; /* checks Tx queues */
569};
570
571#define for_each_ethrxq(sge, i) for (i = 0; i < (sge)->ethqsets; i++)
572#define for_each_ofldrxq(sge, i) for (i = 0; i < (sge)->ofldqsets; i++)
573#define for_each_rdmarxq(sge, i) for (i = 0; i < (sge)->rdmaqs; i++)
574
575struct l2t_data;
576
2422d9a3
SR		 577#ifdef CONFIG_PCI_IOV
578
7d6727cf
SR		 579/* T4 supports SRIOV on PF0-3 and T5 on PF0-7. However, the Serial
580 * Configuration initialization for T5 only has SR-IOV functionality enabled
581 * on PF0-3 in order to simplify everything.
2422d9a3 582 */
7d6727cf 583#define NUM_OF_PF_WITH_SRIOV 4
2422d9a3
SR		 584
585#endif
586
625ba2c2
DM		 587struct adapter {
588 void __iomem *regs;
22adfe0a 589 void __iomem *bar2;
625ba2c2
DM		 590 struct pci_dev *pdev;
591 struct device *pdev_dev;
3069ee9b 592 unsigned int mbox;
060e0c75
DM		 593 unsigned int fn;
594 unsigned int flags;
2422d9a3 595 enum chip_type chip;
625ba2c2 596
625ba2c2
DM		 597 int msg_enable;
598
599 struct adapter_params params;
600 struct cxgb4_virt_res vres;
601 unsigned int swintr;
602
603 unsigned int wol;
604
605 struct {
606 unsigned short vec;
8cd18ac4 607 char desc[IFNAMSIZ + 10];
625ba2c2
DM		 608 } msix_info[MAX_INGQ + 1];
609
610 struct sge sge;
611
612 struct net_device *port[MAX_NPORTS];
613 u8 chan_map[NCHAN]; /* channel -> port map */
614
793dad94 615 u32 filter_mode;
636f9d37
VP		 616 unsigned int l2t_start;
617 unsigned int l2t_end;
625ba2c2
DM		 618 struct l2t_data *l2t;
619 void *uld_handle[CXGB4_ULD_MAX];
620 struct list_head list_node;
01bcca68 621 struct list_head rcu_node;
625ba2c2
DM		 622
623 struct tid_info tids;
624 void **tid_release_head;
625 spinlock_t tid_release_lock;
626 struct work_struct tid_release_task;
881806bc
VP		 627 struct work_struct db_full_task;
628 struct work_struct db_drop_task;
625ba2c2
DM		 629 bool tid_release_task_busy;
630
631 struct dentry *debugfs_root;
632
633 spinlock_t stats_lock;
634};
635
f2b7e78d
VP		 636/* Defined bit width of user definable filter tuples
637 */
638#define ETHTYPE_BITWIDTH 16
639#define FRAG_BITWIDTH 1
640#define MACIDX_BITWIDTH 9
641#define FCOE_BITWIDTH 1
642#define IPORT_BITWIDTH 3
643#define MATCHTYPE_BITWIDTH 3
644#define PROTO_BITWIDTH 8
645#define TOS_BITWIDTH 8
646#define PF_BITWIDTH 8
647#define VF_BITWIDTH 8
648#define IVLAN_BITWIDTH 16
649#define OVLAN_BITWIDTH 16
650
651/* Filter matching rules. These consist of a set of ingress packet field
652 * (value, mask) tuples. The associated ingress packet field matches the
653 * tuple when ((field & mask) == value). (Thus a wildcard "don't care" field
654 * rule can be constructed by specifying a tuple of (0, 0).) A filter rule
655 * matches an ingress packet when all of the individual individual field
656 * matching rules are true.
657 *
658 * Partial field masks are always valid, however, while it may be easy to
659 * understand their meanings for some fields (e.g. IP address to match a
660 * subnet), for others making sensible partial masks is less intuitive (e.g.
661 * MPS match type) ...
662 *
663 * Most of the following data structures are modeled on T4 capabilities.
664 * Drivers for earlier chips use the subsets which make sense for those chips.
665 * We really need to come up with a hardware-independent mechanism to
666 * represent hardware filter capabilities ...
667 */
668struct ch_filter_tuple {
669 /* Compressed header matching field rules. The TP_VLAN_PRI_MAP
670 * register selects which of these fields will participate in the
671 * filter match rules -- up to a maximum of 36 bits. Because
672 * TP_VLAN_PRI_MAP is a global register, all filters must use the same
673 * set of fields.
674 */
675 uint32_t ethtype:ETHTYPE_BITWIDTH; /* Ethernet type */
676 uint32_t frag:FRAG_BITWIDTH; /* IP fragmentation header */
677 uint32_t ivlan_vld:1; /* inner VLAN valid */
678 uint32_t ovlan_vld:1; /* outer VLAN valid */
679 uint32_t pfvf_vld:1; /* PF/VF valid */
680 uint32_t macidx:MACIDX_BITWIDTH; /* exact match MAC index */
681 uint32_t fcoe:FCOE_BITWIDTH; /* FCoE packet */
682 uint32_t iport:IPORT_BITWIDTH; /* ingress port */
683 uint32_t matchtype:MATCHTYPE_BITWIDTH; /* MPS match type */
684 uint32_t proto:PROTO_BITWIDTH; /* protocol type */
685 uint32_t tos:TOS_BITWIDTH; /* TOS/Traffic Type */
686 uint32_t pf:PF_BITWIDTH; /* PCI-E PF ID */
687 uint32_t vf:VF_BITWIDTH; /* PCI-E VF ID */
688 uint32_t ivlan:IVLAN_BITWIDTH; /* inner VLAN */
689 uint32_t ovlan:OVLAN_BITWIDTH; /* outer VLAN */
690
691 /* Uncompressed header matching field rules. These are always
692 * available for field rules.
693 */
694 uint8_t lip[16]; /* local IP address (IPv4 in [3:0]) */
695 uint8_t fip[16]; /* foreign IP address (IPv4 in [3:0]) */
696 uint16_t lport; /* local port */
697 uint16_t fport; /* foreign port */
698};
699
700/* A filter ioctl command.
701 */
702struct ch_filter_specification {
703 /* Administrative fields for filter.
704 */
705 uint32_t hitcnts:1; /* count filter hits in TCB */
706 uint32_t prio:1; /* filter has priority over active/server */
707
708 /* Fundamental filter typing. This is the one element of filter
709 * matching that doesn't exist as a (value, mask) tuple.
710 */
711 uint32_t type:1; /* 0 => IPv4, 1 => IPv6 */
712
713 /* Packet dispatch information. Ingress packets which match the
714 * filter rules will be dropped, passed to the host or switched back
715 * out as egress packets.
716 */
717 uint32_t action:2; /* drop, pass, switch */
718
719 uint32_t rpttid:1; /* report TID in RSS hash field */
720
721 uint32_t dirsteer:1; /* 0 => RSS, 1 => steer to iq */
722 uint32_t iq:10; /* ingress queue */
723
724 uint32_t maskhash:1; /* dirsteer=0: store RSS hash in TCB */
725 uint32_t dirsteerhash:1;/* dirsteer=1: 0 => TCB contains RSS hash */
726 /* 1 => TCB contains IQ ID */
727
728 /* Switch proxy/rewrite fields. An ingress packet which matches a
729 * filter with "switch" set will be looped back out as an egress
730 * packet -- potentially with some Ethernet header rewriting.
731 */
732 uint32_t eport:2; /* egress port to switch packet out */
733 uint32_t newdmac:1; /* rewrite destination MAC address */
734 uint32_t newsmac:1; /* rewrite source MAC address */
735 uint32_t newvlan:2; /* rewrite VLAN Tag */
736 uint8_t dmac[ETH_ALEN]; /* new destination MAC address */
737 uint8_t smac[ETH_ALEN]; /* new source MAC address */
738 uint16_t vlan; /* VLAN Tag to insert */
739
740 /* Filter rule value/mask pairs.
741 */
742 struct ch_filter_tuple val;
743 struct ch_filter_tuple mask;
744};
745
746enum {
747 FILTER_PASS = 0, /* default */
748 FILTER_DROP,
749 FILTER_SWITCH
750};
751
752enum {
753 VLAN_NOCHANGE = 0, /* default */
754 VLAN_REMOVE,
755 VLAN_INSERT,
756 VLAN_REWRITE
757};
758
2422d9a3
SR		 759static inline int is_t5(enum chip_type chip)
760{
d14807dd 761 return CHELSIO_CHIP_VERSION(chip) == CHELSIO_T5;
2422d9a3
SR		 762}
763
764static inline int is_t4(enum chip_type chip)
765{
d14807dd 766 return CHELSIO_CHIP_VERSION(chip) == CHELSIO_T4;
2422d9a3
SR		 767}
768
625ba2c2
DM		 769static inline u32 t4_read_reg(struct adapter *adap, u32 reg_addr)
770{
771 return readl(adap->regs + reg_addr);
772}
773
774static inline void t4_write_reg(struct adapter *adap, u32 reg_addr, u32 val)
775{
776 writel(val, adap->regs + reg_addr);
777}
778
779#ifndef readq
780static inline u64 readq(const volatile void __iomem *addr)
781{
782 return readl(addr) + ((u64)readl(addr + 4) << 32);
783}
784
785static inline void writeq(u64 val, volatile void __iomem *addr)
786{
787 writel(val, addr);
788 writel(val >> 32, addr + 4);
789}
790#endif
791
792static inline u64 t4_read_reg64(struct adapter *adap, u32 reg_addr)
793{
794 return readq(adap->regs + reg_addr);
795}
796
797static inline void t4_write_reg64(struct adapter *adap, u32 reg_addr, u64 val)
798{
799 writeq(val, adap->regs + reg_addr);
800}
801
802/**
803 * netdev2pinfo - return the port_info structure associated with a net_device
804 * @dev: the netdev
805 *
806 * Return the struct port_info associated with a net_device
807 */
808static inline struct port_info *netdev2pinfo(const struct net_device *dev)
809{
810 return netdev_priv(dev);
811}
812
813/**
814 * adap2pinfo - return the port_info of a port
815 * @adap: the adapter
816 * @idx: the port index
817 *
818 * Return the port_info structure for the port of the given index.
819 */
820static inline struct port_info *adap2pinfo(struct adapter *adap, int idx)
821{
822 return netdev_priv(adap->port[idx]);
823}
824
825/**
826 * netdev2adap - return the adapter structure associated with a net_device
827 * @dev: the netdev
828 *
829 * Return the struct adapter associated with a net_device
830 */
831static inline struct adapter *netdev2adap(const struct net_device *dev)
832{
833 return netdev2pinfo(dev)->adapter;
834}
835
836void t4_os_portmod_changed(const struct adapter *adap, int port_id);
837void t4_os_link_changed(struct adapter *adap, int port_id, int link_stat);
838
839void *t4_alloc_mem(size_t size);
625ba2c2
DM		 840
841void t4_free_sge_resources(struct adapter *adap);
842irq_handler_t t4_intr_handler(struct adapter *adap);
843netdev_tx_t t4_eth_xmit(struct sk_buff *skb, struct net_device *dev);
844int t4_ethrx_handler(struct sge_rspq *q, const __be64 *rsp,
845 const struct pkt_gl *gl);
846int t4_mgmt_tx(struct adapter *adap, struct sk_buff *skb);
847int t4_ofld_send(struct adapter *adap, struct sk_buff *skb);
848int t4_sge_alloc_rxq(struct adapter *adap, struct sge_rspq *iq, bool fwevtq,
849 struct net_device *dev, int intr_idx,
850 struct sge_fl *fl, rspq_handler_t hnd);
851int t4_sge_alloc_eth_txq(struct adapter *adap, struct sge_eth_txq *txq,
852 struct net_device *dev, struct netdev_queue *netdevq,
853 unsigned int iqid);
854int t4_sge_alloc_ctrl_txq(struct adapter *adap, struct sge_ctrl_txq *txq,
855 struct net_device *dev, unsigned int iqid,
856 unsigned int cmplqid);
857int t4_sge_alloc_ofld_txq(struct adapter *adap, struct sge_ofld_txq *txq,
858 struct net_device *dev, unsigned int iqid);
859irqreturn_t t4_sge_intr_msix(int irq, void *cookie);
52367a76 860int t4_sge_init(struct adapter *adap);
625ba2c2
DM		 861void t4_sge_start(struct adapter *adap);
862void t4_sge_stop(struct adapter *adap);
3069ee9b 863extern int dbfifo_int_thresh;
625ba2c2
DM		 864
865#define for_each_port(adapter, iter) \
866 for (iter = 0; iter < (adapter)->params.nports; ++iter)
867
9a4da2cd
VP		 868static inline int is_bypass(struct adapter *adap)
869{
870 return adap->params.bypass;
871}
872
873static inline int is_bypass_device(int device)
874{
875 /* this should be set based upon device capabilities */
876 switch (device) {
877 case 0x440b:
878 case 0x440c:
879 return 1;
880 default:
881 return 0;
882 }
883}
884
625ba2c2
DM		 885static inline unsigned int core_ticks_per_usec(const struct adapter *adap)
886{
887 return adap->params.vpd.cclk / 1000;
888}
889
890static inline unsigned int us_to_core_ticks(const struct adapter *adap,
891 unsigned int us)
892{
893 return (us * adap->params.vpd.cclk) / 1000;
894}
895
52367a76
VP		 896static inline unsigned int core_ticks_to_us(const struct adapter *adapter,
897 unsigned int ticks)
898{
899 /* add Core Clock / 2 to round ticks to nearest uS */
900 return ((ticks * 1000 + adapter->params.vpd.cclk/2) /
901 adapter->params.vpd.cclk);
902}
903
625ba2c2
DM		 904void t4_set_reg_field(struct adapter *adap, unsigned int addr, u32 mask,
905 u32 val);
906
907int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size,
908 void *rpl, bool sleep_ok);
909
910static inline int t4_wr_mbox(struct adapter *adap, int mbox, const void *cmd,
911 int size, void *rpl)
912{
913 return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, true);
914}
915
916static inline int t4_wr_mbox_ns(struct adapter *adap, int mbox, const void *cmd,
917 int size, void *rpl)
918{
919 return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, false);
920}
921
13ee15d3
VP		 922void t4_write_indirect(struct adapter *adap, unsigned int addr_reg,
923 unsigned int data_reg, const u32 *vals,
924 unsigned int nregs, unsigned int start_idx);
f2b7e78d
VP		 925void t4_read_indirect(struct adapter *adap, unsigned int addr_reg,
926 unsigned int data_reg, u32 *vals, unsigned int nregs,
927 unsigned int start_idx);
928
929struct fw_filter_wr;
930
625ba2c2
DM		 931void t4_intr_enable(struct adapter *adapter);
932void t4_intr_disable(struct adapter *adapter);
625ba2c2
DM		 933int t4_slow_intr_handler(struct adapter *adapter);
934
204dc3c0 935int t4_wait_dev_ready(struct adapter *adap);
625ba2c2
DM		 936int t4_link_start(struct adapter *adap, unsigned int mbox, unsigned int port,
937 struct link_config *lc);
938int t4_restart_aneg(struct adapter *adap, unsigned int mbox, unsigned int port);
5afc8b84
VP		 939int t4_memory_write(struct adapter *adap, int mtype, u32 addr, u32 len,
940 __be32 *buf);
625ba2c2 941int t4_seeprom_wp(struct adapter *adapter, bool enable);
636f9d37 942int get_vpd_params(struct adapter *adapter, struct vpd_params *p);
625ba2c2 943int t4_load_fw(struct adapter *adapter, const u8 *fw_data, unsigned int size);
636f9d37 944unsigned int t4_flash_cfg_addr(struct adapter *adapter);
16e47624
HS		 945int t4_get_fw_version(struct adapter *adapter, u32 *vers);
946int t4_get_tp_version(struct adapter *adapter, u32 *vers);
947int t4_prep_fw(struct adapter *adap, struct fw_info *fw_info,
948 const u8 *fw_data, unsigned int fw_size,
949 struct fw_hdr *card_fw, enum dev_state state, int *reset);
625ba2c2 950int t4_prep_adapter(struct adapter *adapter);
dcf7b6f5
KS		 951int t4_init_tp_params(struct adapter *adap);
952int t4_filter_field_shift(const struct adapter *adap, int filter_sel);
625ba2c2
DM		 953int t4_port_init(struct adapter *adap, int mbox, int pf, int vf);
954void t4_fatal_err(struct adapter *adapter);
625ba2c2
DM		 955int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid,
956 int start, int n, const u16 *rspq, unsigned int nrspq);
957int t4_config_glbl_rss(struct adapter *adapter, int mbox, unsigned int mode,
958 unsigned int flags);
19dd37ba
SR		 959int t4_mc_read(struct adapter *adap, int idx, u32 addr, __be32 *data,
960 u64 *parity);
625ba2c2
DM		 961int t4_edc_read(struct adapter *adap, int idx, u32 addr, __be32 *data,
962 u64 *parity);
72aca4bf 963const char *t4_get_port_type_description(enum fw_port_type port_type);
625ba2c2 964void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p);
625ba2c2 965void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log);
636f9d37
VP		 966void t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr,
967 unsigned int mask, unsigned int val);
625ba2c2
DM		 968void t4_tp_get_tcp_stats(struct adapter *adap, struct tp_tcp_stats *v4,
969 struct tp_tcp_stats *v6);
970void t4_load_mtus(struct adapter *adap, const unsigned short *mtus,
971 const unsigned short *alpha, const unsigned short *beta);
972
f2b7e78d
VP		 973void t4_mk_filtdelwr(unsigned int ftid, struct fw_filter_wr *wr, int qid);
974
625ba2c2
DM		 975void t4_wol_magic_enable(struct adapter *adap, unsigned int port,
976 const u8 *addr);
977int t4_wol_pat_enable(struct adapter *adap, unsigned int port, unsigned int map,
978 u64 mask0, u64 mask1, unsigned int crc, bool enable);
979
980int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox,
981 enum dev_master master, enum dev_state *state);
982int t4_fw_bye(struct adapter *adap, unsigned int mbox);
983int t4_early_init(struct adapter *adap, unsigned int mbox);
984int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset);
636f9d37
VP		 985int t4_fixup_host_params(struct adapter *adap, unsigned int page_size,
986 unsigned int cache_line_size);
987int t4_fw_initialize(struct adapter *adap, unsigned int mbox);
625ba2c2
DM		 988int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
989 unsigned int vf, unsigned int nparams, const u32 *params,
990 u32 *val);
991int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
992 unsigned int vf, unsigned int nparams, const u32 *params,
993 const u32 *val);
994int t4_cfg_pfvf(struct adapter *adap, unsigned int mbox, unsigned int pf,
995 unsigned int vf, unsigned int txq, unsigned int txq_eth_ctrl,
996 unsigned int rxqi, unsigned int rxq, unsigned int tc,
997 unsigned int vi, unsigned int cmask, unsigned int pmask,
998 unsigned int nexact, unsigned int rcaps, unsigned int wxcaps);
999int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port,
1000 unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac,
1001 unsigned int *rss_size);
625ba2c2 1002int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid,
f8f5aafa
DM		 1003 int mtu, int promisc, int all_multi, int bcast, int vlanex,
1004 bool sleep_ok);
625ba2c2
DM		 1005int t4_alloc_mac_filt(struct adapter *adap, unsigned int mbox,
1006 unsigned int viid, bool free, unsigned int naddr,
1007 const u8 **addr, u16 *idx, u64 *hash, bool sleep_ok);
1008int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid,
1009 int idx, const u8 *addr, bool persist, bool add_smt);
1010int t4_set_addr_hash(struct adapter *adap, unsigned int mbox, unsigned int viid,
1011 bool ucast, u64 vec, bool sleep_ok);
1012int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid,
1013 bool rx_en, bool tx_en);
1014int t4_identify_port(struct adapter *adap, unsigned int mbox, unsigned int viid,
1015 unsigned int nblinks);
1016int t4_mdio_rd(struct adapter *adap, unsigned int mbox, unsigned int phy_addr,
1017 unsigned int mmd, unsigned int reg, u16 *valp);
1018int t4_mdio_wr(struct adapter *adap, unsigned int mbox, unsigned int phy_addr,
1019 unsigned int mmd, unsigned int reg, u16 val);
625ba2c2
DM		 1020int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
1021 unsigned int vf, unsigned int iqtype, unsigned int iqid,
1022 unsigned int fl0id, unsigned int fl1id);
1023int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
1024 unsigned int vf, unsigned int eqid);
1025int t4_ctrl_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
1026 unsigned int vf, unsigned int eqid);
1027int t4_ofld_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
1028 unsigned int vf, unsigned int eqid);
1029int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl);
881806bc
VP		 1030void t4_db_full(struct adapter *adapter);
1031void t4_db_dropped(struct adapter *adapter);
8caa1e84
VP		 1032int t4_mem_win_read_len(struct adapter *adap, u32 addr, __be32 *data, int len);
1033int t4_fwaddrspace_write(struct adapter *adap, unsigned int mbox,
1034 u32 addr, u32 val);
625ba2c2 1035#endif /* __CXGB4_H__ */
Linux kernel - Deliverables
This page took 0.41309 seconds and 5 git commands to generate.