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cxgb4: Add ethtool support to get adapter stats
[deliverable/linux.git] / drivers / net / ethernet / chelsio / cxgb4 / cxgb4.h
CommitLineData
625ba2c2
DM		 1/*
2 * This file is part of the Chelsio T4 Ethernet driver for Linux.
3 *
ce100b8b 4 * Copyright (c) 2003-2014 Chelsio Communications, Inc. All rights reserved.
625ba2c2
DM		 5 *
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
11 *
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
14 * conditions are met:
15 *
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
18 * disclaimer.
19 *
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
24 *
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
32 * SOFTWARE.
33 */
34
35#ifndef __CXGB4_H__
36#define __CXGB4_H__
37
dca4faeb
VP		 38#include "t4_hw.h"
39
625ba2c2
DM		 40#include <linux/bitops.h>
41#include <linux/cache.h>
42#include <linux/interrupt.h>
43#include <linux/list.h>
44#include <linux/netdevice.h>
45#include <linux/pci.h>
46#include <linux/spinlock.h>
47#include <linux/timer.h>
c0b8b992 48#include <linux/vmalloc.h>
625ba2c2
DM		 49#include <asm/io.h>
50#include "cxgb4_uld.h"
625ba2c2 51
3069ee9b
VP		 52#define CH_WARN(adap, fmt, ...) dev_warn(adap->pdev_dev, fmt, ## __VA_ARGS__)
53
625ba2c2
DM		 54enum {
55 MAX_NPORTS = 4, /* max # of ports */
47d54d65 56 SERNUM_LEN = 24, /* Serial # length */
625ba2c2
DM		 57 EC_LEN = 16, /* E/C length */
58 ID_LEN = 16, /* ID length */
a94cd705 59 PN_LEN = 16, /* Part Number length */
625ba2c2
DM		 60};
61
812034f1
HS		 62enum {
63 T4_REGMAP_SIZE = (160 * 1024),
64 T5_REGMAP_SIZE = (332 * 1024),
65};
66
625ba2c2
DM		 67enum {
68 MEM_EDC0,
69 MEM_EDC1,
2422d9a3
SR		 70 MEM_MC,
71 MEM_MC0 = MEM_MC,
72 MEM_MC1
625ba2c2
DM		 73};
74
3069ee9b 75enum {
3eb4afbf
VP		 76 MEMWIN0_APERTURE = 2048,
77 MEMWIN0_BASE = 0x1b800,
3069ee9b
VP		 78 MEMWIN1_APERTURE = 32768,
79 MEMWIN1_BASE = 0x28000,
2422d9a3 80 MEMWIN1_BASE_T5 = 0x52000,
3eb4afbf
VP		 81 MEMWIN2_APERTURE = 65536,
82 MEMWIN2_BASE = 0x30000,
0abfd152
HS		 83 MEMWIN2_APERTURE_T5 = 131072,
84 MEMWIN2_BASE_T5 = 0x60000,
3069ee9b
VP		 85};
86
625ba2c2
DM		 87enum dev_master {
88 MASTER_CANT,
89 MASTER_MAY,
90 MASTER_MUST
91};
92
93enum dev_state {
94 DEV_STATE_UNINIT,
95 DEV_STATE_INIT,
96 DEV_STATE_ERR
97};
98
99enum {
100 PAUSE_RX = 1 << 0,
101 PAUSE_TX = 1 << 1,
102 PAUSE_AUTONEG = 1 << 2
103};
104
105struct port_stats {
106 u64 tx_octets; /* total # of octets in good frames */
107 u64 tx_frames; /* all good frames */
108 u64 tx_bcast_frames; /* all broadcast frames */
109 u64 tx_mcast_frames; /* all multicast frames */
110 u64 tx_ucast_frames; /* all unicast frames */
111 u64 tx_error_frames; /* all error frames */
112
113 u64 tx_frames_64; /* # of Tx frames in a particular range */
114 u64 tx_frames_65_127;
115 u64 tx_frames_128_255;
116 u64 tx_frames_256_511;
117 u64 tx_frames_512_1023;
118 u64 tx_frames_1024_1518;
119 u64 tx_frames_1519_max;
120
121 u64 tx_drop; /* # of dropped Tx frames */
122 u64 tx_pause; /* # of transmitted pause frames */
123 u64 tx_ppp0; /* # of transmitted PPP prio 0 frames */
124 u64 tx_ppp1; /* # of transmitted PPP prio 1 frames */
125 u64 tx_ppp2; /* # of transmitted PPP prio 2 frames */
126 u64 tx_ppp3; /* # of transmitted PPP prio 3 frames */
127 u64 tx_ppp4; /* # of transmitted PPP prio 4 frames */
128 u64 tx_ppp5; /* # of transmitted PPP prio 5 frames */
129 u64 tx_ppp6; /* # of transmitted PPP prio 6 frames */
130 u64 tx_ppp7; /* # of transmitted PPP prio 7 frames */
131
132 u64 rx_octets; /* total # of octets in good frames */
133 u64 rx_frames; /* all good frames */
134 u64 rx_bcast_frames; /* all broadcast frames */
135 u64 rx_mcast_frames; /* all multicast frames */
136 u64 rx_ucast_frames; /* all unicast frames */
137 u64 rx_too_long; /* # of frames exceeding MTU */
138 u64 rx_jabber; /* # of jabber frames */
139 u64 rx_fcs_err; /* # of received frames with bad FCS */
140 u64 rx_len_err; /* # of received frames with length error */
141 u64 rx_symbol_err; /* symbol errors */
142 u64 rx_runt; /* # of short frames */
143
144 u64 rx_frames_64; /* # of Rx frames in a particular range */
145 u64 rx_frames_65_127;
146 u64 rx_frames_128_255;
147 u64 rx_frames_256_511;
148 u64 rx_frames_512_1023;
149 u64 rx_frames_1024_1518;
150 u64 rx_frames_1519_max;
151
152 u64 rx_pause; /* # of received pause frames */
153 u64 rx_ppp0; /* # of received PPP prio 0 frames */
154 u64 rx_ppp1; /* # of received PPP prio 1 frames */
155 u64 rx_ppp2; /* # of received PPP prio 2 frames */
156 u64 rx_ppp3; /* # of received PPP prio 3 frames */
157 u64 rx_ppp4; /* # of received PPP prio 4 frames */
158 u64 rx_ppp5; /* # of received PPP prio 5 frames */
159 u64 rx_ppp6; /* # of received PPP prio 6 frames */
160 u64 rx_ppp7; /* # of received PPP prio 7 frames */
161
162 u64 rx_ovflow0; /* drops due to buffer-group 0 overflows */
163 u64 rx_ovflow1; /* drops due to buffer-group 1 overflows */
164 u64 rx_ovflow2; /* drops due to buffer-group 2 overflows */
165 u64 rx_ovflow3; /* drops due to buffer-group 3 overflows */
166 u64 rx_trunc0; /* buffer-group 0 truncated packets */
167 u64 rx_trunc1; /* buffer-group 1 truncated packets */
168 u64 rx_trunc2; /* buffer-group 2 truncated packets */
169 u64 rx_trunc3; /* buffer-group 3 truncated packets */
170};
171
172struct lb_port_stats {
173 u64 octets;
174 u64 frames;
175 u64 bcast_frames;
176 u64 mcast_frames;
177 u64 ucast_frames;
178 u64 error_frames;
179
180 u64 frames_64;
181 u64 frames_65_127;
182 u64 frames_128_255;
183 u64 frames_256_511;
184 u64 frames_512_1023;
185 u64 frames_1024_1518;
186 u64 frames_1519_max;
187
188 u64 drop;
189
190 u64 ovflow0;
191 u64 ovflow1;
192 u64 ovflow2;
193 u64 ovflow3;
194 u64 trunc0;
195 u64 trunc1;
196 u64 trunc2;
197 u64 trunc3;
198};
199
200struct tp_tcp_stats {
a4cfd929
HS		 201 u32 tcp_out_rsts;
202 u64 tcp_in_segs;
203 u64 tcp_out_segs;
204 u64 tcp_retrans_segs;
205};
206
207struct tp_usm_stats {
208 u32 frames;
209 u32 drops;
210 u64 octets;
625ba2c2
DM		 211};
212
213struct tp_err_stats {
a4cfd929
HS		 214 u32 mac_in_errs[4];
215 u32 hdr_in_errs[4];
216 u32 tcp_in_errs[4];
217 u32 tnl_cong_drops[4];
218 u32 ofld_chan_drops[4];
219 u32 tnl_tx_drops[4];
220 u32 ofld_vlan_drops[4];
221 u32 tcp6_in_errs[4];
222 u32 ofld_no_neigh;
223 u32 ofld_cong_defer;
224};
225
226struct tp_rdma_stats {
227 u32 rqe_dfr_pkt;
228 u32 rqe_dfr_mod;
625ba2c2
DM		 229};
230
e85c9a7a
HS		 231struct sge_params {
232 u32 hps; /* host page size for our PF/VF */
233 u32 eq_qpp; /* egress queues/page for our PF/VF */
234 u32 iq_qpp; /* egress queues/page for our PF/VF */
235};
236
625ba2c2 237struct tp_params {
625ba2c2 238 unsigned int tre; /* log2 of core clocks per TP tick */
2d277b3b 239 unsigned int la_mask; /* what events are recorded by TP LA */
dca4faeb
VP		 240 unsigned short tx_modq_map; /* TX modulation scheduler queue to */
241 /* channel map */
636f9d37
VP		 242
243 uint32_t dack_re; /* DACK timer resolution */
244 unsigned short tx_modq[NCHAN]; /* channel to modulation queue map */
dcf7b6f5
KS		 245
246 u32 vlan_pri_map; /* cached TP_VLAN_PRI_MAP */
247 u32 ingress_config; /* cached TP_INGRESS_CONFIG */
248
249 /* TP_VLAN_PRI_MAP Compressed Filter Tuple field offsets. This is a
250 * subset of the set of fields which may be present in the Compressed
251 * Filter Tuple portion of filters and TCP TCB connections. The
252 * fields which are present are controlled by the TP_VLAN_PRI_MAP.
253 * Since a variable number of fields may or may not be present, their
254 * shifted field positions within the Compressed Filter Tuple may
255 * vary, or not even be present if the field isn't selected in
256 * TP_VLAN_PRI_MAP. Since some of these fields are needed in various
257 * places we store their offsets here, or a -1 if the field isn't
258 * present.
259 */
260 int vlan_shift;
261 int vnic_shift;
262 int port_shift;
263 int protocol_shift;
625ba2c2
DM		 264};
265
266struct vpd_params {
267 unsigned int cclk;
268 u8 ec[EC_LEN + 1];
269 u8 sn[SERNUM_LEN + 1];
270 u8 id[ID_LEN + 1];
a94cd705 271 u8 pn[PN_LEN + 1];
625ba2c2
DM		 272};
273
274struct pci_params {
275 unsigned char speed;
276 unsigned char width;
277};
278
d14807dd
HS		 279#define CHELSIO_CHIP_CODE(version, revision) (((version) << 4) | (revision))
280#define CHELSIO_CHIP_FPGA 0x100
281#define CHELSIO_CHIP_VERSION(code) (((code) >> 4) & 0xf)
282#define CHELSIO_CHIP_RELEASE(code) ((code) & 0xf)
283
284#define CHELSIO_T4 0x4
285#define CHELSIO_T5 0x5
ab4b583b 286#define CHELSIO_T6 0x6
d14807dd
HS		 287
288enum chip_type {
289 T4_A1 = CHELSIO_CHIP_CODE(CHELSIO_T4, 1),
290 T4_A2 = CHELSIO_CHIP_CODE(CHELSIO_T4, 2),
291 T4_FIRST_REV = T4_A1,
292 T4_LAST_REV = T4_A2,
293
294 T5_A0 = CHELSIO_CHIP_CODE(CHELSIO_T5, 0),
295 T5_A1 = CHELSIO_CHIP_CODE(CHELSIO_T5, 1),
296 T5_FIRST_REV = T5_A0,
297 T5_LAST_REV = T5_A1,
ab4b583b
HS		 298
299 T6_A0 = CHELSIO_CHIP_CODE(CHELSIO_T6, 0),
300 T6_FIRST_REV = T6_A0,
301 T6_LAST_REV = T6_A0,
d14807dd
HS		 302};
303
49aa284f
HS		 304struct devlog_params {
305 u32 memtype; /* which memory (EDC0, EDC1, MC) */
306 u32 start; /* start of log in firmware memory */
307 u32 size; /* size of log */
308};
309
3ccc6cf7
HS		 310/* Stores chip specific parameters */
311struct arch_specific_params {
312 u8 nchan;
313 u16 mps_rplc_size;
314 u16 vfcount;
315 u32 sge_fl_db;
316 u16 mps_tcam_size;
317};
318
625ba2c2 319struct adapter_params {
e85c9a7a 320 struct sge_params sge;
625ba2c2
DM		 321 struct tp_params tp;
322 struct vpd_params vpd;
323 struct pci_params pci;
49aa284f
HS		 324 struct devlog_params devlog;
325 enum pcie_memwin drv_memwin;
625ba2c2 326
f1ff24aa
HS		 327 unsigned int cim_la_size;
328
900a6596
DM		 329 unsigned int sf_size; /* serial flash size in bytes */
330 unsigned int sf_nsec; /* # of flash sectors */
331 unsigned int sf_fw_start; /* start of FW image in flash */
332
625ba2c2
DM		 333 unsigned int fw_vers;
334 unsigned int tp_vers;
335 u8 api_vers[7];
336
337 unsigned short mtus[NMTUS];
338 unsigned short a_wnd[NCCTRL_WIN];
339 unsigned short b_wnd[NCCTRL_WIN];
340
341 unsigned char nports; /* # of ethernet ports */
342 unsigned char portvec;
d14807dd 343 enum chip_type chip; /* chip code */
3ccc6cf7 344 struct arch_specific_params arch; /* chip specific params */
625ba2c2
DM		 345 unsigned char offload;
346
9a4da2cd
VP		 347 unsigned char bypass;
348
625ba2c2 349 unsigned int ofldq_wr_cred;
1ac0f095 350 bool ulptx_memwrite_dsgl; /* use of T5 DSGL allowed */
4c2c5763
HS		 351
352 unsigned int max_ordird_qp; /* Max read depth per RDMA QP */
353 unsigned int max_ird_adapter; /* Max read depth per adapter */
625ba2c2
DM		 354};
355
a3bfb617
HS		 356/* State needed to monitor the forward progress of SGE Ingress DMA activities
357 * and possible hangs.
358 */
359struct sge_idma_monitor_state {
360 unsigned int idma_1s_thresh; /* 1s threshold in Core Clock ticks */
361 unsigned int idma_stalled[2]; /* synthesized stalled timers in HZ */
362 unsigned int idma_state[2]; /* IDMA Hang detect state */
363 unsigned int idma_qid[2]; /* IDMA Hung Ingress Queue ID */
364 unsigned int idma_warn[2]; /* time to warning in HZ */
365};
366
16e47624
HS		 367#include "t4fw_api.h"
368
369#define FW_VERSION(chip) ( \
b2e1a3f0
HS		 370 FW_HDR_FW_VER_MAJOR_G(chip##FW_VERSION_MAJOR) | \
371 FW_HDR_FW_VER_MINOR_G(chip##FW_VERSION_MINOR) | \
372 FW_HDR_FW_VER_MICRO_G(chip##FW_VERSION_MICRO) | \
373 FW_HDR_FW_VER_BUILD_G(chip##FW_VERSION_BUILD))
16e47624
HS		 374#define FW_INTFVER(chip, intf) (FW_HDR_INTFVER_##intf)
375
376struct fw_info {
377 u8 chip;
378 char *fs_name;
379 char *fw_mod_name;
380 struct fw_hdr fw_hdr;
381};
382
383
625ba2c2
DM		 384struct trace_params {
385 u32 data[TRACE_LEN / 4];
386 u32 mask[TRACE_LEN / 4];
387 unsigned short snap_len;
388 unsigned short min_len;
389 unsigned char skip_ofst;
390 unsigned char skip_len;
391 unsigned char invert;
392 unsigned char port;
393};
394
395struct link_config {
396 unsigned short supported; /* link capabilities */
397 unsigned short advertising; /* advertised capabilities */
398 unsigned short requested_speed; /* speed user has requested */
399 unsigned short speed; /* actual link speed */
400 unsigned char requested_fc; /* flow control user has requested */
401 unsigned char fc; /* actual link flow control */
402 unsigned char autoneg; /* autonegotiating? */
403 unsigned char link_ok; /* link up? */
404};
405
e2ac9628 406#define FW_LEN16(fw_struct) FW_CMD_LEN16_V(sizeof(fw_struct) / 16)
625ba2c2
DM		 407
408enum {
409 MAX_ETH_QSETS = 32, /* # of Ethernet Tx/Rx queue sets */
410 MAX_OFLD_QSETS = 16, /* # of offload Tx/Rx queue sets */
411 MAX_CTRL_QUEUES = NCHAN, /* # of control Tx queues */
412 MAX_RDMA_QUEUES = NCHAN, /* # of streaming RDMA Rx queues */
f36e58e5 413 MAX_RDMA_CIQS = 32, /* # of RDMA concentrator IQs */
cf38be6d 414 MAX_ISCSI_QUEUES = NCHAN, /* # of streaming iSCSI Rx queues */
625ba2c2
DM		 415};
416
812034f1
HS		 417enum {
418 MAX_TXQ_ENTRIES = 16384,
419 MAX_CTRL_TXQ_ENTRIES = 1024,
420 MAX_RSPQ_ENTRIES = 16384,
421 MAX_RX_BUFFERS = 16384,
422 MIN_TXQ_ENTRIES = 32,
423 MIN_CTRL_TXQ_ENTRIES = 32,
424 MIN_RSPQ_ENTRIES = 128,
425 MIN_FL_ENTRIES = 16
426};
427
625ba2c2 428enum {
cf38be6d
HS		 429 INGQ_EXTRAS = 2, /* firmware event queue and */
430 /* forwarded interrupts */
cf38be6d
HS		 431 MAX_INGQ = MAX_ETH_QSETS + MAX_OFLD_QSETS + MAX_RDMA_QUEUES
432 + MAX_RDMA_CIQS + MAX_ISCSI_QUEUES + INGQ_EXTRAS,
625ba2c2
DM		 433};
434
435struct adapter;
625ba2c2
DM		 436struct sge_rspq;
437
688848b1
AB		 438#include "cxgb4_dcb.h"
439
76fed8a9
VP		 440#ifdef CONFIG_CHELSIO_T4_FCOE
441#include "cxgb4_fcoe.h"
442#endif /* CONFIG_CHELSIO_T4_FCOE */
443
625ba2c2
DM		 444struct port_info {
445 struct adapter *adapter;
625ba2c2
DM		 446 u16 viid;
447 s16 xact_addr_filt; /* index of exact MAC address filter */
448 u16 rss_size; /* size of VI's RSS table slice */
449 s8 mdio_addr;
40e9de4b 450 enum fw_port_type port_type;
625ba2c2
DM		 451 u8 mod_type;
452 u8 port_id;
453 u8 tx_chan;
454 u8 lport; /* associated offload logical port */
625ba2c2
DM		 455 u8 nqsets; /* # of qsets */
456 u8 first_qset; /* index of first qset */
f796564a 457 u8 rss_mode;
625ba2c2 458 struct link_config link_cfg;
671b0060 459 u16 *rss;
a4cfd929 460 struct port_stats stats_base;
688848b1
AB		 461#ifdef CONFIG_CHELSIO_T4_DCB
462 struct port_dcb_info dcb; /* Data Center Bridging support */
463#endif
76fed8a9
VP		 464#ifdef CONFIG_CHELSIO_T4_FCOE
465 struct cxgb_fcoe fcoe;
466#endif /* CONFIG_CHELSIO_T4_FCOE */
625ba2c2
DM		 467};
468
625ba2c2
DM		 469struct dentry;
470struct work_struct;
471
472enum { /* adapter flags */
473 FULL_INIT_DONE = (1 << 0),
144be3d9
GS		 474 DEV_ENABLED = (1 << 1),
475 USING_MSI = (1 << 2),
476 USING_MSIX = (1 << 3),
625ba2c2 477 FW_OK = (1 << 4),
13ee15d3 478 RSS_TNLALLLOOKUP = (1 << 5),
52367a76
VP		 479 USING_SOFT_PARAMS = (1 << 6),
480 MASTER_PF = (1 << 7),
481 FW_OFLD_CONN = (1 << 9),
625ba2c2
DM		 482};
483
484struct rx_sw_desc;
485
486struct sge_fl { /* SGE free-buffer queue state */
487 unsigned int avail; /* # of available Rx buffers */
488 unsigned int pend_cred; /* new buffers since last FL DB ring */
489 unsigned int cidx; /* consumer index */
490 unsigned int pidx; /* producer index */
491 unsigned long alloc_failed; /* # of times buffer allocation failed */
492 unsigned long large_alloc_failed;
493 unsigned long starving;
494 /* RO fields */
495 unsigned int cntxt_id; /* SGE context id for the free list */
496 unsigned int size; /* capacity of free list */
497 struct rx_sw_desc *sdesc; /* address of SW Rx descriptor ring */
498 __be64 *desc; /* address of HW Rx descriptor ring */
499 dma_addr_t addr; /* bus address of HW ring start */
df64e4d3
HS		 500 void __iomem *bar2_addr; /* address of BAR2 Queue registers */
501 unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */
625ba2c2
DM		 502};
503
504/* A packet gather list */
505struct pkt_gl {
e91b0f24 506 struct page_frag frags[MAX_SKB_FRAGS];
625ba2c2
DM		 507 void *va; /* virtual address of first byte */
508 unsigned int nfrags; /* # of fragments */
509 unsigned int tot_len; /* total length of fragments */
510};
511
512typedef int (*rspq_handler_t)(struct sge_rspq *q, const __be64 *rsp,
513 const struct pkt_gl *gl);
514
515struct sge_rspq { /* state for an SGE response queue */
516 struct napi_struct napi;
517 const __be64 *cur_desc; /* current descriptor in queue */
518 unsigned int cidx; /* consumer index */
519 u8 gen; /* current generation bit */
520 u8 intr_params; /* interrupt holdoff parameters */
521 u8 next_intr_params; /* holdoff params for next interrupt */
e553ec3f 522 u8 adaptive_rx;
625ba2c2
DM		 523 u8 pktcnt_idx; /* interrupt packet threshold */
524 u8 uld; /* ULD handling this queue */
525 u8 idx; /* queue index within its group */
526 int offset; /* offset into current Rx buffer */
527 u16 cntxt_id; /* SGE context id for the response q */
528 u16 abs_id; /* absolute SGE id for the response q */
529 __be64 *desc; /* address of HW response ring */
530 dma_addr_t phys_addr; /* physical address of the ring */
df64e4d3
HS		 531 void __iomem *bar2_addr; /* address of BAR2 Queue registers */
532 unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */
625ba2c2
DM		 533 unsigned int iqe_len; /* entry size */
534 unsigned int size; /* capacity of response queue */
535 struct adapter *adap;
536 struct net_device *netdev; /* associated net device */
537 rspq_handler_t handler;
3a336cb1
HS		 538#ifdef CONFIG_NET_RX_BUSY_POLL
539#define CXGB_POLL_STATE_IDLE 0
540#define CXGB_POLL_STATE_NAPI BIT(0) /* NAPI owns this poll */
541#define CXGB_POLL_STATE_POLL BIT(1) /* poll owns this poll */
542#define CXGB_POLL_STATE_NAPI_YIELD BIT(2) /* NAPI yielded this poll */
543#define CXGB_POLL_STATE_POLL_YIELD BIT(3) /* poll yielded this poll */
544#define CXGB_POLL_YIELD (CXGB_POLL_STATE_NAPI_YIELD | \
545 CXGB_POLL_STATE_POLL_YIELD)
546#define CXGB_POLL_LOCKED (CXGB_POLL_STATE_NAPI | \
547 CXGB_POLL_STATE_POLL)
548#define CXGB_POLL_USER_PEND (CXGB_POLL_STATE_POLL | \
549 CXGB_POLL_STATE_POLL_YIELD)
550 unsigned int bpoll_state;
551 spinlock_t bpoll_lock; /* lock for busy poll */
552#endif /* CONFIG_NET_RX_BUSY_POLL */
553
625ba2c2
DM		 554};
555
556struct sge_eth_stats { /* Ethernet queue statistics */
557 unsigned long pkts; /* # of ethernet packets */
558 unsigned long lro_pkts; /* # of LRO super packets */
559 unsigned long lro_merged; /* # of wire packets merged by LRO */
560 unsigned long rx_cso; /* # of Rx checksum offloads */
561 unsigned long vlan_ex; /* # of Rx VLAN extractions */
562 unsigned long rx_drops; /* # of packets dropped due to no mem */
563};
564
565struct sge_eth_rxq { /* SW Ethernet Rx queue */
566 struct sge_rspq rspq;
567 struct sge_fl fl;
568 struct sge_eth_stats stats;
569} ____cacheline_aligned_in_smp;
570
571struct sge_ofld_stats { /* offload queue statistics */
572 unsigned long pkts; /* # of packets */
573 unsigned long imm; /* # of immediate-data packets */
574 unsigned long an; /* # of asynchronous notifications */
575 unsigned long nomem; /* # of responses deferred due to no mem */
576};
577
578struct sge_ofld_rxq { /* SW offload Rx queue */
579 struct sge_rspq rspq;
580 struct sge_fl fl;
581 struct sge_ofld_stats stats;
582} ____cacheline_aligned_in_smp;
583
584struct tx_desc {
585 __be64 flit[8];
586};
587
588struct tx_sw_desc;
589
590struct sge_txq {
591 unsigned int in_use; /* # of in-use Tx descriptors */
592 unsigned int size; /* # of descriptors */
593 unsigned int cidx; /* SW consumer index */
594 unsigned int pidx; /* producer index */
595 unsigned long stops; /* # of times q has been stopped */
596 unsigned long restarts; /* # of queue restarts */
597 unsigned int cntxt_id; /* SGE context id for the Tx q */
598 struct tx_desc *desc; /* address of HW Tx descriptor ring */
599 struct tx_sw_desc *sdesc; /* address of SW Tx descriptor ring */
600 struct sge_qstat *stat; /* queue status entry */
601 dma_addr_t phys_addr; /* physical address of the ring */
3069ee9b
VP		 602 spinlock_t db_lock;
603 int db_disabled;
604 unsigned short db_pidx;
05eb2389 605 unsigned short db_pidx_inc;
df64e4d3
HS		 606 void __iomem *bar2_addr; /* address of BAR2 Queue registers */
607 unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */
625ba2c2
DM		 608};
609
610struct sge_eth_txq { /* state for an SGE Ethernet Tx queue */
611 struct sge_txq q;
612 struct netdev_queue *txq; /* associated netdev TX queue */
10b00466
AB		 613#ifdef CONFIG_CHELSIO_T4_DCB
614 u8 dcb_prio; /* DCB Priority bound to queue */
615#endif
625ba2c2
DM		 616 unsigned long tso; /* # of TSO requests */
617 unsigned long tx_cso; /* # of Tx checksum offloads */
618 unsigned long vlan_ins; /* # of Tx VLAN insertions */
619 unsigned long mapping_err; /* # of I/O MMU packet mapping errors */
620} ____cacheline_aligned_in_smp;
621
622struct sge_ofld_txq { /* state for an SGE offload Tx queue */
623 struct sge_txq q;
624 struct adapter *adap;
625 struct sk_buff_head sendq; /* list of backpressured packets */
626 struct tasklet_struct qresume_tsk; /* restarts the queue */
627 u8 full; /* the Tx ring is full */
628 unsigned long mapping_err; /* # of I/O MMU packet mapping errors */
629} ____cacheline_aligned_in_smp;
630
631struct sge_ctrl_txq { /* state for an SGE control Tx queue */
632 struct sge_txq q;
633 struct adapter *adap;
634 struct sk_buff_head sendq; /* list of backpressured packets */
635 struct tasklet_struct qresume_tsk; /* restarts the queue */
636 u8 full; /* the Tx ring is full */
637} ____cacheline_aligned_in_smp;
638
639struct sge {
640 struct sge_eth_txq ethtxq[MAX_ETH_QSETS];
641 struct sge_ofld_txq ofldtxq[MAX_OFLD_QSETS];
642 struct sge_ctrl_txq ctrlq[MAX_CTRL_QUEUES];
643
644 struct sge_eth_rxq ethrxq[MAX_ETH_QSETS];
645 struct sge_ofld_rxq ofldrxq[MAX_OFLD_QSETS];
646 struct sge_ofld_rxq rdmarxq[MAX_RDMA_QUEUES];
cf38be6d 647 struct sge_ofld_rxq rdmaciq[MAX_RDMA_CIQS];
625ba2c2
DM		 648 struct sge_rspq fw_evtq ____cacheline_aligned_in_smp;
649
650 struct sge_rspq intrq ____cacheline_aligned_in_smp;
651 spinlock_t intrq_lock;
652
653 u16 max_ethqsets; /* # of available Ethernet queue sets */
654 u16 ethqsets; /* # of active Ethernet queue sets */
655 u16 ethtxq_rover; /* Tx queue to clean up next */
656 u16 ofldqsets; /* # of active offload queue sets */
657 u16 rdmaqs; /* # of available RDMA Rx queues */
cf38be6d 658 u16 rdmaciqs; /* # of available RDMA concentrator IQs */
625ba2c2 659 u16 ofld_rxq[MAX_OFLD_QSETS];
f36e58e5
HS		 660 u16 rdma_rxq[MAX_RDMA_QUEUES];
661 u16 rdma_ciq[MAX_RDMA_CIQS];
625ba2c2
DM		 662 u16 timer_val[SGE_NTIMERS];
663 u8 counter_val[SGE_NCOUNTERS];
52367a76
VP		 664 u32 fl_pg_order; /* large page allocation size */
665 u32 stat_len; /* length of status page at ring end */
666 u32 pktshift; /* padding between CPL & packet data */
667 u32 fl_align; /* response queue message alignment */
668 u32 fl_starve_thres; /* Free List starvation threshold */
0f4d201f 669
a3bfb617 670 struct sge_idma_monitor_state idma_monitor;
e46dab4d 671 unsigned int egr_start;
4b8e27a8 672 unsigned int egr_sz;
e46dab4d 673 unsigned int ingr_start;
4b8e27a8
HS		 674 unsigned int ingr_sz;
675 void **egr_map; /* qid->queue egress queue map */
676 struct sge_rspq **ingr_map; /* qid->queue ingress queue map */
677 unsigned long *starving_fl;
678 unsigned long *txq_maperr;
5b377d11 679 unsigned long *blocked_fl;
625ba2c2
DM		 680 struct timer_list rx_timer; /* refills starving FLs */
681 struct timer_list tx_timer; /* checks Tx queues */
682};
683
684#define for_each_ethrxq(sge, i) for (i = 0; i < (sge)->ethqsets; i++)
685#define for_each_ofldrxq(sge, i) for (i = 0; i < (sge)->ofldqsets; i++)
686#define for_each_rdmarxq(sge, i) for (i = 0; i < (sge)->rdmaqs; i++)
cf38be6d 687#define for_each_rdmaciq(sge, i) for (i = 0; i < (sge)->rdmaciqs; i++)
625ba2c2
DM		 688
689struct l2t_data;
690
2422d9a3
SR		 691#ifdef CONFIG_PCI_IOV
692
7d6727cf
SR		 693/* T4 supports SRIOV on PF0-3 and T5 on PF0-7. However, the Serial
694 * Configuration initialization for T5 only has SR-IOV functionality enabled
695 * on PF0-3 in order to simplify everything.
2422d9a3 696 */
7d6727cf 697#define NUM_OF_PF_WITH_SRIOV 4
2422d9a3
SR		 698
699#endif
700
a4cfd929
HS		 701struct doorbell_stats {
702 u32 db_drop;
703 u32 db_empty;
704 u32 db_full;
705};
706
625ba2c2
DM		 707struct adapter {
708 void __iomem *regs;
22adfe0a 709 void __iomem *bar2;
0abfd152 710 u32 t4_bar0;
625ba2c2
DM		 711 struct pci_dev *pdev;
712 struct device *pdev_dev;
3069ee9b 713 unsigned int mbox;
b2612722 714 unsigned int pf;
060e0c75 715 unsigned int flags;
2422d9a3 716 enum chip_type chip;
625ba2c2 717
625ba2c2
DM		 718 int msg_enable;
719
720 struct adapter_params params;
721 struct cxgb4_virt_res vres;
722 unsigned int swintr;
723
724 unsigned int wol;
725
726 struct {
727 unsigned short vec;
8cd18ac4 728 char desc[IFNAMSIZ + 10];
625ba2c2
DM		 729 } msix_info[MAX_INGQ + 1];
730
a4cfd929 731 struct doorbell_stats db_stats;
625ba2c2
DM		 732 struct sge sge;
733
734 struct net_device *port[MAX_NPORTS];
735 u8 chan_map[NCHAN]; /* channel -> port map */
736
793dad94 737 u32 filter_mode;
636f9d37
VP		 738 unsigned int l2t_start;
739 unsigned int l2t_end;
625ba2c2 740 struct l2t_data *l2t;
b5a02f50
AB		 741 unsigned int clipt_start;
742 unsigned int clipt_end;
743 struct clip_tbl *clipt;
625ba2c2
DM		 744 void *uld_handle[CXGB4_ULD_MAX];
745 struct list_head list_node;
01bcca68 746 struct list_head rcu_node;
625ba2c2
DM		 747
748 struct tid_info tids;
749 void **tid_release_head;
750 spinlock_t tid_release_lock;
29aaee65 751 struct workqueue_struct *workq;
625ba2c2 752 struct work_struct tid_release_task;
881806bc
VP		 753 struct work_struct db_full_task;
754 struct work_struct db_drop_task;
625ba2c2
DM		 755 bool tid_release_task_busy;
756
757 struct dentry *debugfs_root;
758
759 spinlock_t stats_lock;
fc5ab020 760 spinlock_t win0_lock ____cacheline_aligned_in_smp;
625ba2c2
DM		 761};
762
f2b7e78d
VP		 763/* Defined bit width of user definable filter tuples
764 */
765#define ETHTYPE_BITWIDTH 16
766#define FRAG_BITWIDTH 1
767#define MACIDX_BITWIDTH 9
768#define FCOE_BITWIDTH 1
769#define IPORT_BITWIDTH 3
770#define MATCHTYPE_BITWIDTH 3
771#define PROTO_BITWIDTH 8
772#define TOS_BITWIDTH 8
773#define PF_BITWIDTH 8
774#define VF_BITWIDTH 8
775#define IVLAN_BITWIDTH 16
776#define OVLAN_BITWIDTH 16
777
778/* Filter matching rules. These consist of a set of ingress packet field
779 * (value, mask) tuples. The associated ingress packet field matches the
780 * tuple when ((field & mask) == value). (Thus a wildcard "don't care" field
781 * rule can be constructed by specifying a tuple of (0, 0).) A filter rule
782 * matches an ingress packet when all of the individual individual field
783 * matching rules are true.
784 *
785 * Partial field masks are always valid, however, while it may be easy to
786 * understand their meanings for some fields (e.g. IP address to match a
787 * subnet), for others making sensible partial masks is less intuitive (e.g.
788 * MPS match type) ...
789 *
790 * Most of the following data structures are modeled on T4 capabilities.
791 * Drivers for earlier chips use the subsets which make sense for those chips.
792 * We really need to come up with a hardware-independent mechanism to
793 * represent hardware filter capabilities ...
794 */
795struct ch_filter_tuple {
796 /* Compressed header matching field rules. The TP_VLAN_PRI_MAP
797 * register selects which of these fields will participate in the
798 * filter match rules -- up to a maximum of 36 bits. Because
799 * TP_VLAN_PRI_MAP is a global register, all filters must use the same
800 * set of fields.
801 */
802 uint32_t ethtype:ETHTYPE_BITWIDTH; /* Ethernet type */
803 uint32_t frag:FRAG_BITWIDTH; /* IP fragmentation header */
804 uint32_t ivlan_vld:1; /* inner VLAN valid */
805 uint32_t ovlan_vld:1; /* outer VLAN valid */
806 uint32_t pfvf_vld:1; /* PF/VF valid */
807 uint32_t macidx:MACIDX_BITWIDTH; /* exact match MAC index */
808 uint32_t fcoe:FCOE_BITWIDTH; /* FCoE packet */
809 uint32_t iport:IPORT_BITWIDTH; /* ingress port */
810 uint32_t matchtype:MATCHTYPE_BITWIDTH; /* MPS match type */
811 uint32_t proto:PROTO_BITWIDTH; /* protocol type */
812 uint32_t tos:TOS_BITWIDTH; /* TOS/Traffic Type */
813 uint32_t pf:PF_BITWIDTH; /* PCI-E PF ID */
814 uint32_t vf:VF_BITWIDTH; /* PCI-E VF ID */
815 uint32_t ivlan:IVLAN_BITWIDTH; /* inner VLAN */
816 uint32_t ovlan:OVLAN_BITWIDTH; /* outer VLAN */
817
818 /* Uncompressed header matching field rules. These are always
819 * available for field rules.
820 */
821 uint8_t lip[16]; /* local IP address (IPv4 in [3:0]) */
822 uint8_t fip[16]; /* foreign IP address (IPv4 in [3:0]) */
823 uint16_t lport; /* local port */
824 uint16_t fport; /* foreign port */
825};
826
827/* A filter ioctl command.
828 */
829struct ch_filter_specification {
830 /* Administrative fields for filter.
831 */
832 uint32_t hitcnts:1; /* count filter hits in TCB */
833 uint32_t prio:1; /* filter has priority over active/server */
834
835 /* Fundamental filter typing. This is the one element of filter
836 * matching that doesn't exist as a (value, mask) tuple.
837 */
838 uint32_t type:1; /* 0 => IPv4, 1 => IPv6 */
839
840 /* Packet dispatch information. Ingress packets which match the
841 * filter rules will be dropped, passed to the host or switched back
842 * out as egress packets.
843 */
844 uint32_t action:2; /* drop, pass, switch */
845
846 uint32_t rpttid:1; /* report TID in RSS hash field */
847
848 uint32_t dirsteer:1; /* 0 => RSS, 1 => steer to iq */
849 uint32_t iq:10; /* ingress queue */
850
851 uint32_t maskhash:1; /* dirsteer=0: store RSS hash in TCB */
852 uint32_t dirsteerhash:1;/* dirsteer=1: 0 => TCB contains RSS hash */
853 /* 1 => TCB contains IQ ID */
854
855 /* Switch proxy/rewrite fields. An ingress packet which matches a
856 * filter with "switch" set will be looped back out as an egress
857 * packet -- potentially with some Ethernet header rewriting.
858 */
859 uint32_t eport:2; /* egress port to switch packet out */
860 uint32_t newdmac:1; /* rewrite destination MAC address */
861 uint32_t newsmac:1; /* rewrite source MAC address */
862 uint32_t newvlan:2; /* rewrite VLAN Tag */
863 uint8_t dmac[ETH_ALEN]; /* new destination MAC address */
864 uint8_t smac[ETH_ALEN]; /* new source MAC address */
865 uint16_t vlan; /* VLAN Tag to insert */
866
867 /* Filter rule value/mask pairs.
868 */
869 struct ch_filter_tuple val;
870 struct ch_filter_tuple mask;
871};
872
873enum {
874 FILTER_PASS = 0, /* default */
875 FILTER_DROP,
876 FILTER_SWITCH
877};
878
879enum {
880 VLAN_NOCHANGE = 0, /* default */
881 VLAN_REMOVE,
882 VLAN_INSERT,
883 VLAN_REWRITE
884};
885
a4cfd929
HS		 886static inline int is_offload(const struct adapter *adap)
887{
888 return adap->params.offload;
889}
890
ab4b583b
HS		 891static inline int is_t6(enum chip_type chip)
892{
893 return CHELSIO_CHIP_VERSION(chip) == CHELSIO_T6;
894}
895
2422d9a3
SR		 896static inline int is_t5(enum chip_type chip)
897{
d14807dd 898 return CHELSIO_CHIP_VERSION(chip) == CHELSIO_T5;
2422d9a3
SR		 899}
900
901static inline int is_t4(enum chip_type chip)
902{
d14807dd 903 return CHELSIO_CHIP_VERSION(chip) == CHELSIO_T4;
2422d9a3
SR		 904}
905
625ba2c2
DM		 906static inline u32 t4_read_reg(struct adapter *adap, u32 reg_addr)
907{
908 return readl(adap->regs + reg_addr);
909}
910
911static inline void t4_write_reg(struct adapter *adap, u32 reg_addr, u32 val)
912{
913 writel(val, adap->regs + reg_addr);
914}
915
916#ifndef readq
917static inline u64 readq(const volatile void __iomem *addr)
918{
919 return readl(addr) + ((u64)readl(addr + 4) << 32);
920}
921
922static inline void writeq(u64 val, volatile void __iomem *addr)
923{
924 writel(val, addr);
925 writel(val >> 32, addr + 4);
926}
927#endif
928
929static inline u64 t4_read_reg64(struct adapter *adap, u32 reg_addr)
930{
931 return readq(adap->regs + reg_addr);
932}
933
934static inline void t4_write_reg64(struct adapter *adap, u32 reg_addr, u64 val)
935{
936 writeq(val, adap->regs + reg_addr);
937}
938
939/**
940 * netdev2pinfo - return the port_info structure associated with a net_device
941 * @dev: the netdev
942 *
943 * Return the struct port_info associated with a net_device
944 */
945static inline struct port_info *netdev2pinfo(const struct net_device *dev)
946{
947 return netdev_priv(dev);
948}
949
950/**
951 * adap2pinfo - return the port_info of a port
952 * @adap: the adapter
953 * @idx: the port index
954 *
955 * Return the port_info structure for the port of the given index.
956 */
957static inline struct port_info *adap2pinfo(struct adapter *adap, int idx)
958{
959 return netdev_priv(adap->port[idx]);
960}
961
962/**
963 * netdev2adap - return the adapter structure associated with a net_device
964 * @dev: the netdev
965 *
966 * Return the struct adapter associated with a net_device
967 */
968static inline struct adapter *netdev2adap(const struct net_device *dev)
969{
970 return netdev2pinfo(dev)->adapter;
971}
972
3a336cb1
HS		 973#ifdef CONFIG_NET_RX_BUSY_POLL
974static inline void cxgb_busy_poll_init_lock(struct sge_rspq *q)
975{
976 spin_lock_init(&q->bpoll_lock);
977 q->bpoll_state = CXGB_POLL_STATE_IDLE;
978}
979
980static inline bool cxgb_poll_lock_napi(struct sge_rspq *q)
981{
982 bool rc = true;
983
984 spin_lock(&q->bpoll_lock);
985 if (q->bpoll_state & CXGB_POLL_LOCKED) {
986 q->bpoll_state |= CXGB_POLL_STATE_NAPI_YIELD;
987 rc = false;
988 } else {
989 q->bpoll_state = CXGB_POLL_STATE_NAPI;
990 }
991 spin_unlock(&q->bpoll_lock);
992 return rc;
993}
994
995static inline bool cxgb_poll_unlock_napi(struct sge_rspq *q)
996{
997 bool rc = false;
998
999 spin_lock(&q->bpoll_lock);
1000 if (q->bpoll_state & CXGB_POLL_STATE_POLL_YIELD)
1001 rc = true;
1002 q->bpoll_state = CXGB_POLL_STATE_IDLE;
1003 spin_unlock(&q->bpoll_lock);
1004 return rc;
1005}
1006
1007static inline bool cxgb_poll_lock_poll(struct sge_rspq *q)
1008{
1009 bool rc = true;
1010
1011 spin_lock_bh(&q->bpoll_lock);
1012 if (q->bpoll_state & CXGB_POLL_LOCKED) {
1013 q->bpoll_state |= CXGB_POLL_STATE_POLL_YIELD;
1014 rc = false;
1015 } else {
1016 q->bpoll_state |= CXGB_POLL_STATE_POLL;
1017 }
1018 spin_unlock_bh(&q->bpoll_lock);
1019 return rc;
1020}
1021
1022static inline bool cxgb_poll_unlock_poll(struct sge_rspq *q)
1023{
1024 bool rc = false;
1025
1026 spin_lock_bh(&q->bpoll_lock);
1027 if (q->bpoll_state & CXGB_POLL_STATE_POLL_YIELD)
1028 rc = true;
1029 q->bpoll_state = CXGB_POLL_STATE_IDLE;
1030 spin_unlock_bh(&q->bpoll_lock);
1031 return rc;
1032}
1033
1034static inline bool cxgb_poll_busy_polling(struct sge_rspq *q)
1035{
1036 return q->bpoll_state & CXGB_POLL_USER_PEND;
1037}
1038#else
1039static inline void cxgb_busy_poll_init_lock(struct sge_rspq *q)
1040{
1041}
1042
1043static inline bool cxgb_poll_lock_napi(struct sge_rspq *q)
1044{
1045 return true;
1046}
1047
1048static inline bool cxgb_poll_unlock_napi(struct sge_rspq *q)
1049{
1050 return false;
1051}
1052
1053static inline bool cxgb_poll_lock_poll(struct sge_rspq *q)
1054{
1055 return false;
1056}
1057
1058static inline bool cxgb_poll_unlock_poll(struct sge_rspq *q)
1059{
1060 return false;
1061}
1062
1063static inline bool cxgb_poll_busy_polling(struct sge_rspq *q)
1064{
1065 return false;
1066}
1067#endif /* CONFIG_NET_RX_BUSY_POLL */
1068
812034f1
HS		 1069/* Return a version number to identify the type of adapter. The scheme is:
1070 * - bits 0..9: chip version
1071 * - bits 10..15: chip revision
1072 * - bits 16..23: register dump version
1073 */
1074static inline unsigned int mk_adap_vers(struct adapter *ap)
1075{
1076 return CHELSIO_CHIP_VERSION(ap->params.chip) |
1077 (CHELSIO_CHIP_RELEASE(ap->params.chip) << 10) | (1 << 16);
1078}
1079
1080/* Return a queue's interrupt hold-off time in us. 0 means no timer. */
1081static inline unsigned int qtimer_val(const struct adapter *adap,
1082 const struct sge_rspq *q)
1083{
1084 unsigned int idx = q->intr_params >> 1;
1085
1086 return idx < SGE_NTIMERS ? adap->sge.timer_val[idx] : 0;
1087}
1088
1089/* driver version & name used for ethtool_drvinfo */
1090extern char cxgb4_driver_name[];
1091extern const char cxgb4_driver_version[];
1092
625ba2c2
DM		 1093void t4_os_portmod_changed(const struct adapter *adap, int port_id);
1094void t4_os_link_changed(struct adapter *adap, int port_id, int link_stat);
1095
1096void *t4_alloc_mem(size_t size);
625ba2c2
DM		 1097
1098void t4_free_sge_resources(struct adapter *adap);
5fa76694 1099void t4_free_ofld_rxqs(struct adapter *adap, int n, struct sge_ofld_rxq *q);
625ba2c2
DM		 1100irq_handler_t t4_intr_handler(struct adapter *adap);
1101netdev_tx_t t4_eth_xmit(struct sk_buff *skb, struct net_device *dev);
1102int t4_ethrx_handler(struct sge_rspq *q, const __be64 *rsp,
1103 const struct pkt_gl *gl);
1104int t4_mgmt_tx(struct adapter *adap, struct sk_buff *skb);
1105int t4_ofld_send(struct adapter *adap, struct sk_buff *skb);
1106int t4_sge_alloc_rxq(struct adapter *adap, struct sge_rspq *iq, bool fwevtq,
1107 struct net_device *dev, int intr_idx,
145ef8a5 1108 struct sge_fl *fl, rspq_handler_t hnd, int cong);
625ba2c2
DM		 1109int t4_sge_alloc_eth_txq(struct adapter *adap, struct sge_eth_txq *txq,
1110 struct net_device *dev, struct netdev_queue *netdevq,
1111 unsigned int iqid);
1112int t4_sge_alloc_ctrl_txq(struct adapter *adap, struct sge_ctrl_txq *txq,
1113 struct net_device *dev, unsigned int iqid,
1114 unsigned int cmplqid);
1115int t4_sge_alloc_ofld_txq(struct adapter *adap, struct sge_ofld_txq *txq,
1116 struct net_device *dev, unsigned int iqid);
1117irqreturn_t t4_sge_intr_msix(int irq, void *cookie);
52367a76 1118int t4_sge_init(struct adapter *adap);
625ba2c2
DM		 1119void t4_sge_start(struct adapter *adap);
1120void t4_sge_stop(struct adapter *adap);
3a336cb1 1121int cxgb_busy_poll(struct napi_struct *napi);
812034f1
HS		 1122int cxgb4_set_rspq_intr_params(struct sge_rspq *q, unsigned int us,
1123 unsigned int cnt);
1124void cxgb4_set_ethtool_ops(struct net_device *netdev);
1125int cxgb4_write_rss(const struct port_info *pi, const u16 *queues);
3069ee9b 1126extern int dbfifo_int_thresh;
625ba2c2
DM		 1127
1128#define for_each_port(adapter, iter) \
1129 for (iter = 0; iter < (adapter)->params.nports; ++iter)
1130
9a4da2cd
VP		 1131static inline int is_bypass(struct adapter *adap)
1132{
1133 return adap->params.bypass;
1134}
1135
1136static inline int is_bypass_device(int device)
1137{
1138 /* this should be set based upon device capabilities */
1139 switch (device) {
1140 case 0x440b:
1141 case 0x440c:
1142 return 1;
1143 default:
1144 return 0;
1145 }
1146}
1147
01b69614
HS		 1148static inline int is_10gbt_device(int device)
1149{
1150 /* this should be set based upon device capabilities */
1151 switch (device) {
1152 case 0x4409:
1153 case 0x4486:
1154 return 1;
1155
1156 default:
1157 return 0;
1158 }
1159}
1160
625ba2c2
DM		 1161static inline unsigned int core_ticks_per_usec(const struct adapter *adap)
1162{
1163 return adap->params.vpd.cclk / 1000;
1164}
1165
1166static inline unsigned int us_to_core_ticks(const struct adapter *adap,
1167 unsigned int us)
1168{
1169 return (us * adap->params.vpd.cclk) / 1000;
1170}
1171
52367a76
VP		 1172static inline unsigned int core_ticks_to_us(const struct adapter *adapter,
1173 unsigned int ticks)
1174{
1175 /* add Core Clock / 2 to round ticks to nearest uS */
1176 return ((ticks * 1000 + adapter->params.vpd.cclk/2) /
1177 adapter->params.vpd.cclk);
1178}
1179
625ba2c2
DM		 1180void t4_set_reg_field(struct adapter *adap, unsigned int addr, u32 mask,
1181 u32 val);
1182
01b69614
HS		 1183int t4_wr_mbox_meat_timeout(struct adapter *adap, int mbox, const void *cmd,
1184 int size, void *rpl, bool sleep_ok, int timeout);
625ba2c2
DM		 1185int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size,
1186 void *rpl, bool sleep_ok);
1187
01b69614
HS		 1188static inline int t4_wr_mbox_timeout(struct adapter *adap, int mbox,
1189 const void *cmd, int size, void *rpl,
1190 int timeout)
1191{
1192 return t4_wr_mbox_meat_timeout(adap, mbox, cmd, size, rpl, true,
1193 timeout);
1194}
1195
625ba2c2
DM		 1196static inline int t4_wr_mbox(struct adapter *adap, int mbox, const void *cmd,
1197 int size, void *rpl)
1198{
1199 return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, true);
1200}
1201
1202static inline int t4_wr_mbox_ns(struct adapter *adap, int mbox, const void *cmd,
1203 int size, void *rpl)
1204{
1205 return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, false);
1206}
1207
13ee15d3
VP		 1208void t4_write_indirect(struct adapter *adap, unsigned int addr_reg,
1209 unsigned int data_reg, const u32 *vals,
1210 unsigned int nregs, unsigned int start_idx);
f2b7e78d
VP		 1211void t4_read_indirect(struct adapter *adap, unsigned int addr_reg,
1212 unsigned int data_reg, u32 *vals, unsigned int nregs,
1213 unsigned int start_idx);
0abfd152 1214void t4_hw_pci_read_cfg4(struct adapter *adapter, int reg, u32 *val);
f2b7e78d
VP		 1215
1216struct fw_filter_wr;
1217
625ba2c2
DM		 1218void t4_intr_enable(struct adapter *adapter);
1219void t4_intr_disable(struct adapter *adapter);
625ba2c2
DM		 1220int t4_slow_intr_handler(struct adapter *adapter);
1221
8203b509 1222int t4_wait_dev_ready(void __iomem *regs);
625ba2c2
DM		 1223int t4_link_start(struct adapter *adap, unsigned int mbox, unsigned int port,
1224 struct link_config *lc);
1225int t4_restart_aneg(struct adapter *adap, unsigned int mbox, unsigned int port);
fc5ab020 1226
b562fc37
HS		 1227u32 t4_read_pcie_cfg4(struct adapter *adap, int reg);
1228u32 t4_get_util_window(struct adapter *adap);
1229void t4_setup_memwin(struct adapter *adap, u32 memwin_base, u32 window);
1230
fc5ab020
HS		 1231#define T4_MEMORY_WRITE 0
1232#define T4_MEMORY_READ 1
1233int t4_memory_rw(struct adapter *adap, int win, int mtype, u32 addr, u32 len,
f01aa633 1234 void *buf, int dir);
fc5ab020
HS		 1235static inline int t4_memory_write(struct adapter *adap, int mtype, u32 addr,
1236 u32 len, __be32 *buf)
1237{
1238 return t4_memory_rw(adap, 0, mtype, addr, len, buf, 0);
1239}
1240
812034f1
HS		 1241unsigned int t4_get_regs_len(struct adapter *adapter);
1242void t4_get_regs(struct adapter *adap, void *buf, size_t buf_size);
1243
625ba2c2 1244int t4_seeprom_wp(struct adapter *adapter, bool enable);
636f9d37 1245int get_vpd_params(struct adapter *adapter, struct vpd_params *p);
49216c1c
HS		 1246int t4_read_flash(struct adapter *adapter, unsigned int addr,
1247 unsigned int nwords, u32 *data, int byte_oriented);
625ba2c2 1248int t4_load_fw(struct adapter *adapter, const u8 *fw_data, unsigned int size);
01b69614
HS		 1249int t4_load_phy_fw(struct adapter *adap,
1250 int win, spinlock_t *lock,
1251 int (*phy_fw_version)(const u8 *, size_t),
1252 const u8 *phy_fw_data, size_t phy_fw_size);
1253int t4_phy_fw_ver(struct adapter *adap, int *phy_fw_ver);
49216c1c 1254int t4_fwcache(struct adapter *adap, enum fw_params_param_dev_fwcache op);
22c0b963
HS		 1255int t4_fw_upgrade(struct adapter *adap, unsigned int mbox,
1256 const u8 *fw_data, unsigned int size, int force);
636f9d37 1257unsigned int t4_flash_cfg_addr(struct adapter *adapter);
16e47624
HS		 1258int t4_get_fw_version(struct adapter *adapter, u32 *vers);
1259int t4_get_tp_version(struct adapter *adapter, u32 *vers);
ba3f8cd5 1260int t4_get_exprom_version(struct adapter *adapter, u32 *vers);
16e47624
HS		 1261int t4_prep_fw(struct adapter *adap, struct fw_info *fw_info,
1262 const u8 *fw_data, unsigned int fw_size,
1263 struct fw_hdr *card_fw, enum dev_state state, int *reset);
625ba2c2 1264int t4_prep_adapter(struct adapter *adapter);
e85c9a7a
HS		 1265
1266enum t4_bar2_qtype { T4_BAR2_QTYPE_EGRESS, T4_BAR2_QTYPE_INGRESS };
b2612722 1267int t4_bar2_sge_qregs(struct adapter *adapter,
e85c9a7a
HS		 1268 unsigned int qid,
1269 enum t4_bar2_qtype qtype,
1270 u64 *pbar2_qoffset,
1271 unsigned int *pbar2_qid);
1272
dc9daab2
HS		 1273unsigned int qtimer_val(const struct adapter *adap,
1274 const struct sge_rspq *q);
ae469b68
HS		 1275
1276int t4_init_devlog_params(struct adapter *adapter);
e85c9a7a 1277int t4_init_sge_params(struct adapter *adapter);
dcf7b6f5
KS		 1278int t4_init_tp_params(struct adapter *adap);
1279int t4_filter_field_shift(const struct adapter *adap, int filter_sel);
c035e183 1280int t4_init_rss_mode(struct adapter *adap, int mbox);
625ba2c2
DM		 1281int t4_port_init(struct adapter *adap, int mbox, int pf, int vf);
1282void t4_fatal_err(struct adapter *adapter);
625ba2c2
DM		 1283int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid,
1284 int start, int n, const u16 *rspq, unsigned int nrspq);
1285int t4_config_glbl_rss(struct adapter *adapter, int mbox, unsigned int mode,
1286 unsigned int flags);
c035e183
HS		 1287int t4_config_vi_rss(struct adapter *adapter, int mbox, unsigned int viid,
1288 unsigned int flags, unsigned int defq);
688ea5fe
HS		 1289int t4_read_rss(struct adapter *adapter, u16 *entries);
1290void t4_read_rss_key(struct adapter *adapter, u32 *key);
1291void t4_write_rss_key(struct adapter *adap, const u32 *key, int idx);
1292void t4_read_rss_pf_config(struct adapter *adapter, unsigned int index,
1293 u32 *valp);
1294void t4_read_rss_vf_config(struct adapter *adapter, unsigned int index,
1295 u32 *vfl, u32 *vfh);
1296u32 t4_read_rss_pf_map(struct adapter *adapter);
1297u32 t4_read_rss_pf_mask(struct adapter *adapter);
1298
145ef8a5 1299unsigned int t4_get_mps_bg_map(struct adapter *adapter, int idx);
b3bbe36a
HS		 1300void t4_pmtx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]);
1301void t4_pmrx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]);
e5f0e43b
HS		 1302int t4_read_cim_ibq(struct adapter *adap, unsigned int qid, u32 *data,
1303 size_t n);
c778af7d
HS		 1304int t4_read_cim_obq(struct adapter *adap, unsigned int qid, u32 *data,
1305 size_t n);
f1ff24aa
HS		 1306int t4_cim_read(struct adapter *adap, unsigned int addr, unsigned int n,
1307 unsigned int *valp);
1308int t4_cim_write(struct adapter *adap, unsigned int addr, unsigned int n,
1309 const unsigned int *valp);
1310int t4_cim_read_la(struct adapter *adap, u32 *la_buf, unsigned int *wrptr);
74b3092c 1311void t4_read_cimq_cfg(struct adapter *adap, u16 *base, u16 *size, u16 *thres);
72aca4bf 1312const char *t4_get_port_type_description(enum fw_port_type port_type);
625ba2c2 1313void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p);
a4cfd929
HS		 1314void t4_get_port_stats_offset(struct adapter *adap, int idx,
1315 struct port_stats *stats,
1316 struct port_stats *offset);
625ba2c2 1317void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log);
bad43792 1318void t4_read_cong_tbl(struct adapter *adap, u16 incr[NMTUS][NCCTRL_WIN]);
636f9d37
VP		 1319void t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr,
1320 unsigned int mask, unsigned int val);
2d277b3b 1321void t4_tp_read_la(struct adapter *adap, u64 *la_buf, unsigned int *wrptr);
a4cfd929
HS		 1322void t4_tp_get_err_stats(struct adapter *adap, struct tp_err_stats *st);
1323void t4_tp_get_rdma_stats(struct adapter *adap, struct tp_rdma_stats *st);
1324void t4_get_usm_stats(struct adapter *adap, struct tp_usm_stats *st);
625ba2c2
DM		 1325void t4_tp_get_tcp_stats(struct adapter *adap, struct tp_tcp_stats *v4,
1326 struct tp_tcp_stats *v6);
1327void t4_load_mtus(struct adapter *adap, const unsigned short *mtus,
1328 const unsigned short *alpha, const unsigned short *beta);
1329
797ff0f5
HS		 1330void t4_ulprx_read_la(struct adapter *adap, u32 *la_buf);
1331
f2b7e78d
VP		 1332void t4_mk_filtdelwr(unsigned int ftid, struct fw_filter_wr *wr, int qid);
1333
625ba2c2
DM		 1334void t4_wol_magic_enable(struct adapter *adap, unsigned int port,
1335 const u8 *addr);
1336int t4_wol_pat_enable(struct adapter *adap, unsigned int port, unsigned int map,
1337 u64 mask0, u64 mask1, unsigned int crc, bool enable);
1338
1339int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox,
1340 enum dev_master master, enum dev_state *state);
1341int t4_fw_bye(struct adapter *adap, unsigned int mbox);
1342int t4_early_init(struct adapter *adap, unsigned int mbox);
1343int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset);
636f9d37
VP		 1344int t4_fixup_host_params(struct adapter *adap, unsigned int page_size,
1345 unsigned int cache_line_size);
1346int t4_fw_initialize(struct adapter *adap, unsigned int mbox);
625ba2c2
DM		 1347int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
1348 unsigned int vf, unsigned int nparams, const u32 *params,
1349 u32 *val);
01b69614
HS		 1350int t4_query_params_rw(struct adapter *adap, unsigned int mbox, unsigned int pf,
1351 unsigned int vf, unsigned int nparams, const u32 *params,
1352 u32 *val, int rw);
1353int t4_set_params_timeout(struct adapter *adap, unsigned int mbox,
1354 unsigned int pf, unsigned int vf,
1355 unsigned int nparams, const u32 *params,
1356 const u32 *val, int timeout);
625ba2c2
DM		 1357int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
1358 unsigned int vf, unsigned int nparams, const u32 *params,
1359 const u32 *val);
1360int t4_cfg_pfvf(struct adapter *adap, unsigned int mbox, unsigned int pf,
1361 unsigned int vf, unsigned int txq, unsigned int txq_eth_ctrl,
1362 unsigned int rxqi, unsigned int rxq, unsigned int tc,
1363 unsigned int vi, unsigned int cmask, unsigned int pmask,
1364 unsigned int nexact, unsigned int rcaps, unsigned int wxcaps);
1365int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port,
1366 unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac,
1367 unsigned int *rss_size);
625ba2c2 1368int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid,
f8f5aafa
DM		 1369 int mtu, int promisc, int all_multi, int bcast, int vlanex,
1370 bool sleep_ok);
625ba2c2
DM		 1371int t4_alloc_mac_filt(struct adapter *adap, unsigned int mbox,
1372 unsigned int viid, bool free, unsigned int naddr,
1373 const u8 **addr, u16 *idx, u64 *hash, bool sleep_ok);
1374int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid,
1375 int idx, const u8 *addr, bool persist, bool add_smt);
1376int t4_set_addr_hash(struct adapter *adap, unsigned int mbox, unsigned int viid,
1377 bool ucast, u64 vec, bool sleep_ok);
688848b1
AB		 1378int t4_enable_vi_params(struct adapter *adap, unsigned int mbox,
1379 unsigned int viid, bool rx_en, bool tx_en, bool dcb_en);
625ba2c2
DM		 1380int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid,
1381 bool rx_en, bool tx_en);
1382int t4_identify_port(struct adapter *adap, unsigned int mbox, unsigned int viid,
1383 unsigned int nblinks);
1384int t4_mdio_rd(struct adapter *adap, unsigned int mbox, unsigned int phy_addr,
1385 unsigned int mmd, unsigned int reg, u16 *valp);
1386int t4_mdio_wr(struct adapter *adap, unsigned int mbox, unsigned int phy_addr,
1387 unsigned int mmd, unsigned int reg, u16 val);
625ba2c2
DM		 1388int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
1389 unsigned int vf, unsigned int iqtype, unsigned int iqid,
1390 unsigned int fl0id, unsigned int fl1id);
1391int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
1392 unsigned int vf, unsigned int eqid);
1393int t4_ctrl_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
1394 unsigned int vf, unsigned int eqid);
1395int t4_ofld_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
1396 unsigned int vf, unsigned int eqid);
1397int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl);
881806bc
VP		 1398void t4_db_full(struct adapter *adapter);
1399void t4_db_dropped(struct adapter *adapter);
8caa1e84
VP		 1400int t4_fwaddrspace_write(struct adapter *adap, unsigned int mbox,
1401 u32 addr, u32 val);
68bce192 1402void t4_sge_decode_idma_state(struct adapter *adapter, int state);
fd88b31a 1403void t4_free_mem(void *addr);
a3bfb617
HS		 1404void t4_idma_monitor_init(struct adapter *adapter,
1405 struct sge_idma_monitor_state *idma);
1406void t4_idma_monitor(struct adapter *adapter,
1407 struct sge_idma_monitor_state *idma,
1408 int hz, int ticks);
625ba2c2 1409#endif /* __CXGB4_H__ */
Linux kernel - Deliverables
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