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cxgb4: Add is_t6 macro and T6 register ranges
[deliverable/linux.git] / drivers / net / ethernet / chelsio / cxgb4 / cxgb4.h
CommitLineData
625ba2c2
DM		 1/*
2 * This file is part of the Chelsio T4 Ethernet driver for Linux.
3 *
ce100b8b 4 * Copyright (c) 2003-2014 Chelsio Communications, Inc. All rights reserved.
625ba2c2
DM		 5 *
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
11 *
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
14 * conditions are met:
15 *
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
18 * disclaimer.
19 *
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
24 *
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
32 * SOFTWARE.
33 */
34
35#ifndef __CXGB4_H__
36#define __CXGB4_H__
37
dca4faeb
VP		 38#include "t4_hw.h"
39
625ba2c2
DM		 40#include <linux/bitops.h>
41#include <linux/cache.h>
42#include <linux/interrupt.h>
43#include <linux/list.h>
44#include <linux/netdevice.h>
45#include <linux/pci.h>
46#include <linux/spinlock.h>
47#include <linux/timer.h>
c0b8b992 48#include <linux/vmalloc.h>
625ba2c2
DM		 49#include <asm/io.h>
50#include "cxgb4_uld.h"
625ba2c2 51
3069ee9b
VP		 52#define CH_WARN(adap, fmt, ...) dev_warn(adap->pdev_dev, fmt, ## __VA_ARGS__)
53
625ba2c2
DM		 54enum {
55 MAX_NPORTS = 4, /* max # of ports */
47d54d65 56 SERNUM_LEN = 24, /* Serial # length */
625ba2c2
DM		 57 EC_LEN = 16, /* E/C length */
58 ID_LEN = 16, /* ID length */
a94cd705 59 PN_LEN = 16, /* Part Number length */
625ba2c2
DM		 60};
61
812034f1
HS		 62enum {
63 T4_REGMAP_SIZE = (160 * 1024),
64 T5_REGMAP_SIZE = (332 * 1024),
65};
66
625ba2c2
DM		 67enum {
68 MEM_EDC0,
69 MEM_EDC1,
2422d9a3
SR		 70 MEM_MC,
71 MEM_MC0 = MEM_MC,
72 MEM_MC1
625ba2c2
DM		 73};
74
3069ee9b 75enum {
3eb4afbf
VP		 76 MEMWIN0_APERTURE = 2048,
77 MEMWIN0_BASE = 0x1b800,
3069ee9b
VP		 78 MEMWIN1_APERTURE = 32768,
79 MEMWIN1_BASE = 0x28000,
2422d9a3 80 MEMWIN1_BASE_T5 = 0x52000,
3eb4afbf
VP		 81 MEMWIN2_APERTURE = 65536,
82 MEMWIN2_BASE = 0x30000,
0abfd152
HS		 83 MEMWIN2_APERTURE_T5 = 131072,
84 MEMWIN2_BASE_T5 = 0x60000,
3069ee9b
VP		 85};
86
625ba2c2
DM		 87enum dev_master {
88 MASTER_CANT,
89 MASTER_MAY,
90 MASTER_MUST
91};
92
93enum dev_state {
94 DEV_STATE_UNINIT,
95 DEV_STATE_INIT,
96 DEV_STATE_ERR
97};
98
99enum {
100 PAUSE_RX = 1 << 0,
101 PAUSE_TX = 1 << 1,
102 PAUSE_AUTONEG = 1 << 2
103};
104
105struct port_stats {
106 u64 tx_octets; /* total # of octets in good frames */
107 u64 tx_frames; /* all good frames */
108 u64 tx_bcast_frames; /* all broadcast frames */
109 u64 tx_mcast_frames; /* all multicast frames */
110 u64 tx_ucast_frames; /* all unicast frames */
111 u64 tx_error_frames; /* all error frames */
112
113 u64 tx_frames_64; /* # of Tx frames in a particular range */
114 u64 tx_frames_65_127;
115 u64 tx_frames_128_255;
116 u64 tx_frames_256_511;
117 u64 tx_frames_512_1023;
118 u64 tx_frames_1024_1518;
119 u64 tx_frames_1519_max;
120
121 u64 tx_drop; /* # of dropped Tx frames */
122 u64 tx_pause; /* # of transmitted pause frames */
123 u64 tx_ppp0; /* # of transmitted PPP prio 0 frames */
124 u64 tx_ppp1; /* # of transmitted PPP prio 1 frames */
125 u64 tx_ppp2; /* # of transmitted PPP prio 2 frames */
126 u64 tx_ppp3; /* # of transmitted PPP prio 3 frames */
127 u64 tx_ppp4; /* # of transmitted PPP prio 4 frames */
128 u64 tx_ppp5; /* # of transmitted PPP prio 5 frames */
129 u64 tx_ppp6; /* # of transmitted PPP prio 6 frames */
130 u64 tx_ppp7; /* # of transmitted PPP prio 7 frames */
131
132 u64 rx_octets; /* total # of octets in good frames */
133 u64 rx_frames; /* all good frames */
134 u64 rx_bcast_frames; /* all broadcast frames */
135 u64 rx_mcast_frames; /* all multicast frames */
136 u64 rx_ucast_frames; /* all unicast frames */
137 u64 rx_too_long; /* # of frames exceeding MTU */
138 u64 rx_jabber; /* # of jabber frames */
139 u64 rx_fcs_err; /* # of received frames with bad FCS */
140 u64 rx_len_err; /* # of received frames with length error */
141 u64 rx_symbol_err; /* symbol errors */
142 u64 rx_runt; /* # of short frames */
143
144 u64 rx_frames_64; /* # of Rx frames in a particular range */
145 u64 rx_frames_65_127;
146 u64 rx_frames_128_255;
147 u64 rx_frames_256_511;
148 u64 rx_frames_512_1023;
149 u64 rx_frames_1024_1518;
150 u64 rx_frames_1519_max;
151
152 u64 rx_pause; /* # of received pause frames */
153 u64 rx_ppp0; /* # of received PPP prio 0 frames */
154 u64 rx_ppp1; /* # of received PPP prio 1 frames */
155 u64 rx_ppp2; /* # of received PPP prio 2 frames */
156 u64 rx_ppp3; /* # of received PPP prio 3 frames */
157 u64 rx_ppp4; /* # of received PPP prio 4 frames */
158 u64 rx_ppp5; /* # of received PPP prio 5 frames */
159 u64 rx_ppp6; /* # of received PPP prio 6 frames */
160 u64 rx_ppp7; /* # of received PPP prio 7 frames */
161
162 u64 rx_ovflow0; /* drops due to buffer-group 0 overflows */
163 u64 rx_ovflow1; /* drops due to buffer-group 1 overflows */
164 u64 rx_ovflow2; /* drops due to buffer-group 2 overflows */
165 u64 rx_ovflow3; /* drops due to buffer-group 3 overflows */
166 u64 rx_trunc0; /* buffer-group 0 truncated packets */
167 u64 rx_trunc1; /* buffer-group 1 truncated packets */
168 u64 rx_trunc2; /* buffer-group 2 truncated packets */
169 u64 rx_trunc3; /* buffer-group 3 truncated packets */
170};
171
172struct lb_port_stats {
173 u64 octets;
174 u64 frames;
175 u64 bcast_frames;
176 u64 mcast_frames;
177 u64 ucast_frames;
178 u64 error_frames;
179
180 u64 frames_64;
181 u64 frames_65_127;
182 u64 frames_128_255;
183 u64 frames_256_511;
184 u64 frames_512_1023;
185 u64 frames_1024_1518;
186 u64 frames_1519_max;
187
188 u64 drop;
189
190 u64 ovflow0;
191 u64 ovflow1;
192 u64 ovflow2;
193 u64 ovflow3;
194 u64 trunc0;
195 u64 trunc1;
196 u64 trunc2;
197 u64 trunc3;
198};
199
200struct tp_tcp_stats {
201 u32 tcpOutRsts;
202 u64 tcpInSegs;
203 u64 tcpOutSegs;
204 u64 tcpRetransSegs;
205};
206
207struct tp_err_stats {
208 u32 macInErrs[4];
209 u32 hdrInErrs[4];
210 u32 tcpInErrs[4];
211 u32 tnlCongDrops[4];
212 u32 ofldChanDrops[4];
213 u32 tnlTxDrops[4];
214 u32 ofldVlanDrops[4];
215 u32 tcp6InErrs[4];
216 u32 ofldNoNeigh;
217 u32 ofldCongDefer;
218};
219
e85c9a7a
HS		 220struct sge_params {
221 u32 hps; /* host page size for our PF/VF */
222 u32 eq_qpp; /* egress queues/page for our PF/VF */
223 u32 iq_qpp; /* egress queues/page for our PF/VF */
224};
225
625ba2c2
DM		 226struct tp_params {
227 unsigned int ntxchan; /* # of Tx channels */
228 unsigned int tre; /* log2 of core clocks per TP tick */
2d277b3b 229 unsigned int la_mask; /* what events are recorded by TP LA */
dca4faeb
VP		 230 unsigned short tx_modq_map; /* TX modulation scheduler queue to */
231 /* channel map */
636f9d37
VP		 232
233 uint32_t dack_re; /* DACK timer resolution */
234 unsigned short tx_modq[NCHAN]; /* channel to modulation queue map */
dcf7b6f5
KS		 235
236 u32 vlan_pri_map; /* cached TP_VLAN_PRI_MAP */
237 u32 ingress_config; /* cached TP_INGRESS_CONFIG */
238
239 /* TP_VLAN_PRI_MAP Compressed Filter Tuple field offsets. This is a
240 * subset of the set of fields which may be present in the Compressed
241 * Filter Tuple portion of filters and TCP TCB connections. The
242 * fields which are present are controlled by the TP_VLAN_PRI_MAP.
243 * Since a variable number of fields may or may not be present, their
244 * shifted field positions within the Compressed Filter Tuple may
245 * vary, or not even be present if the field isn't selected in
246 * TP_VLAN_PRI_MAP. Since some of these fields are needed in various
247 * places we store their offsets here, or a -1 if the field isn't
248 * present.
249 */
250 int vlan_shift;
251 int vnic_shift;
252 int port_shift;
253 int protocol_shift;
625ba2c2
DM		 254};
255
256struct vpd_params {
257 unsigned int cclk;
258 u8 ec[EC_LEN + 1];
259 u8 sn[SERNUM_LEN + 1];
260 u8 id[ID_LEN + 1];
a94cd705 261 u8 pn[PN_LEN + 1];
625ba2c2
DM		 262};
263
264struct pci_params {
265 unsigned char speed;
266 unsigned char width;
267};
268
d14807dd
HS		 269#define CHELSIO_CHIP_CODE(version, revision) (((version) << 4) | (revision))
270#define CHELSIO_CHIP_FPGA 0x100
271#define CHELSIO_CHIP_VERSION(code) (((code) >> 4) & 0xf)
272#define CHELSIO_CHIP_RELEASE(code) ((code) & 0xf)
273
274#define CHELSIO_T4 0x4
275#define CHELSIO_T5 0x5
ab4b583b 276#define CHELSIO_T6 0x6
d14807dd
HS		 277
278enum chip_type {
279 T4_A1 = CHELSIO_CHIP_CODE(CHELSIO_T4, 1),
280 T4_A2 = CHELSIO_CHIP_CODE(CHELSIO_T4, 2),
281 T4_FIRST_REV = T4_A1,
282 T4_LAST_REV = T4_A2,
283
284 T5_A0 = CHELSIO_CHIP_CODE(CHELSIO_T5, 0),
285 T5_A1 = CHELSIO_CHIP_CODE(CHELSIO_T5, 1),
286 T5_FIRST_REV = T5_A0,
287 T5_LAST_REV = T5_A1,
ab4b583b
HS		 288
289 T6_A0 = CHELSIO_CHIP_CODE(CHELSIO_T6, 0),
290 T6_FIRST_REV = T6_A0,
291 T6_LAST_REV = T6_A0,
d14807dd
HS		 292};
293
49aa284f
HS		 294struct devlog_params {
295 u32 memtype; /* which memory (EDC0, EDC1, MC) */
296 u32 start; /* start of log in firmware memory */
297 u32 size; /* size of log */
298};
299
625ba2c2 300struct adapter_params {
e85c9a7a 301 struct sge_params sge;
625ba2c2
DM		 302 struct tp_params tp;
303 struct vpd_params vpd;
304 struct pci_params pci;
49aa284f
HS		 305 struct devlog_params devlog;
306 enum pcie_memwin drv_memwin;
625ba2c2 307
f1ff24aa
HS		 308 unsigned int cim_la_size;
309
900a6596
DM		 310 unsigned int sf_size; /* serial flash size in bytes */
311 unsigned int sf_nsec; /* # of flash sectors */
312 unsigned int sf_fw_start; /* start of FW image in flash */
313
625ba2c2
DM		 314 unsigned int fw_vers;
315 unsigned int tp_vers;
316 u8 api_vers[7];
317
318 unsigned short mtus[NMTUS];
319 unsigned short a_wnd[NCCTRL_WIN];
320 unsigned short b_wnd[NCCTRL_WIN];
321
322 unsigned char nports; /* # of ethernet ports */
323 unsigned char portvec;
d14807dd 324 enum chip_type chip; /* chip code */
625ba2c2
DM		 325 unsigned char offload;
326
9a4da2cd
VP		 327 unsigned char bypass;
328
625ba2c2 329 unsigned int ofldq_wr_cred;
1ac0f095 330 bool ulptx_memwrite_dsgl; /* use of T5 DSGL allowed */
4c2c5763
HS		 331
332 unsigned int max_ordird_qp; /* Max read depth per RDMA QP */
333 unsigned int max_ird_adapter; /* Max read depth per adapter */
625ba2c2
DM		 334};
335
a3bfb617
HS		 336/* State needed to monitor the forward progress of SGE Ingress DMA activities
337 * and possible hangs.
338 */
339struct sge_idma_monitor_state {
340 unsigned int idma_1s_thresh; /* 1s threshold in Core Clock ticks */
341 unsigned int idma_stalled[2]; /* synthesized stalled timers in HZ */
342 unsigned int idma_state[2]; /* IDMA Hang detect state */
343 unsigned int idma_qid[2]; /* IDMA Hung Ingress Queue ID */
344 unsigned int idma_warn[2]; /* time to warning in HZ */
345};
346
16e47624
HS		 347#include "t4fw_api.h"
348
349#define FW_VERSION(chip) ( \
b2e1a3f0
HS		 350 FW_HDR_FW_VER_MAJOR_G(chip##FW_VERSION_MAJOR) | \
351 FW_HDR_FW_VER_MINOR_G(chip##FW_VERSION_MINOR) | \
352 FW_HDR_FW_VER_MICRO_G(chip##FW_VERSION_MICRO) | \
353 FW_HDR_FW_VER_BUILD_G(chip##FW_VERSION_BUILD))
16e47624
HS		 354#define FW_INTFVER(chip, intf) (FW_HDR_INTFVER_##intf)
355
356struct fw_info {
357 u8 chip;
358 char *fs_name;
359 char *fw_mod_name;
360 struct fw_hdr fw_hdr;
361};
362
363
625ba2c2
DM		 364struct trace_params {
365 u32 data[TRACE_LEN / 4];
366 u32 mask[TRACE_LEN / 4];
367 unsigned short snap_len;
368 unsigned short min_len;
369 unsigned char skip_ofst;
370 unsigned char skip_len;
371 unsigned char invert;
372 unsigned char port;
373};
374
375struct link_config {
376 unsigned short supported; /* link capabilities */
377 unsigned short advertising; /* advertised capabilities */
378 unsigned short requested_speed; /* speed user has requested */
379 unsigned short speed; /* actual link speed */
380 unsigned char requested_fc; /* flow control user has requested */
381 unsigned char fc; /* actual link flow control */
382 unsigned char autoneg; /* autonegotiating? */
383 unsigned char link_ok; /* link up? */
384};
385
e2ac9628 386#define FW_LEN16(fw_struct) FW_CMD_LEN16_V(sizeof(fw_struct) / 16)
625ba2c2
DM		 387
388enum {
389 MAX_ETH_QSETS = 32, /* # of Ethernet Tx/Rx queue sets */
390 MAX_OFLD_QSETS = 16, /* # of offload Tx/Rx queue sets */
391 MAX_CTRL_QUEUES = NCHAN, /* # of control Tx queues */
392 MAX_RDMA_QUEUES = NCHAN, /* # of streaming RDMA Rx queues */
f36e58e5 393 MAX_RDMA_CIQS = 32, /* # of RDMA concentrator IQs */
cf38be6d 394 MAX_ISCSI_QUEUES = NCHAN, /* # of streaming iSCSI Rx queues */
625ba2c2
DM		 395};
396
812034f1
HS		 397enum {
398 MAX_TXQ_ENTRIES = 16384,
399 MAX_CTRL_TXQ_ENTRIES = 1024,
400 MAX_RSPQ_ENTRIES = 16384,
401 MAX_RX_BUFFERS = 16384,
402 MIN_TXQ_ENTRIES = 32,
403 MIN_CTRL_TXQ_ENTRIES = 32,
404 MIN_RSPQ_ENTRIES = 128,
405 MIN_FL_ENTRIES = 16
406};
407
625ba2c2 408enum {
cf38be6d
HS		 409 INGQ_EXTRAS = 2, /* firmware event queue and */
410 /* forwarded interrupts */
cf38be6d
HS		 411 MAX_INGQ = MAX_ETH_QSETS + MAX_OFLD_QSETS + MAX_RDMA_QUEUES
412 + MAX_RDMA_CIQS + MAX_ISCSI_QUEUES + INGQ_EXTRAS,
625ba2c2
DM		 413};
414
415struct adapter;
625ba2c2
DM		 416struct sge_rspq;
417
688848b1
AB		 418#include "cxgb4_dcb.h"
419
76fed8a9
VP		 420#ifdef CONFIG_CHELSIO_T4_FCOE
421#include "cxgb4_fcoe.h"
422#endif /* CONFIG_CHELSIO_T4_FCOE */
423
625ba2c2
DM		 424struct port_info {
425 struct adapter *adapter;
625ba2c2
DM		 426 u16 viid;
427 s16 xact_addr_filt; /* index of exact MAC address filter */
428 u16 rss_size; /* size of VI's RSS table slice */
429 s8 mdio_addr;
40e9de4b 430 enum fw_port_type port_type;
625ba2c2
DM		 431 u8 mod_type;
432 u8 port_id;
433 u8 tx_chan;
434 u8 lport; /* associated offload logical port */
625ba2c2
DM		 435 u8 nqsets; /* # of qsets */
436 u8 first_qset; /* index of first qset */
f796564a 437 u8 rss_mode;
625ba2c2 438 struct link_config link_cfg;
671b0060 439 u16 *rss;
688848b1
AB		 440#ifdef CONFIG_CHELSIO_T4_DCB
441 struct port_dcb_info dcb; /* Data Center Bridging support */
442#endif
76fed8a9
VP		 443#ifdef CONFIG_CHELSIO_T4_FCOE
444 struct cxgb_fcoe fcoe;
445#endif /* CONFIG_CHELSIO_T4_FCOE */
625ba2c2
DM		 446};
447
625ba2c2
DM		 448struct dentry;
449struct work_struct;
450
451enum { /* adapter flags */
452 FULL_INIT_DONE = (1 << 0),
144be3d9
GS		 453 DEV_ENABLED = (1 << 1),
454 USING_MSI = (1 << 2),
455 USING_MSIX = (1 << 3),
625ba2c2 456 FW_OK = (1 << 4),
13ee15d3 457 RSS_TNLALLLOOKUP = (1 << 5),
52367a76
VP		 458 USING_SOFT_PARAMS = (1 << 6),
459 MASTER_PF = (1 << 7),
460 FW_OFLD_CONN = (1 << 9),
625ba2c2
DM		 461};
462
463struct rx_sw_desc;
464
465struct sge_fl { /* SGE free-buffer queue state */
466 unsigned int avail; /* # of available Rx buffers */
467 unsigned int pend_cred; /* new buffers since last FL DB ring */
468 unsigned int cidx; /* consumer index */
469 unsigned int pidx; /* producer index */
470 unsigned long alloc_failed; /* # of times buffer allocation failed */
471 unsigned long large_alloc_failed;
472 unsigned long starving;
473 /* RO fields */
474 unsigned int cntxt_id; /* SGE context id for the free list */
475 unsigned int size; /* capacity of free list */
476 struct rx_sw_desc *sdesc; /* address of SW Rx descriptor ring */
477 __be64 *desc; /* address of HW Rx descriptor ring */
478 dma_addr_t addr; /* bus address of HW ring start */
df64e4d3
HS		 479 void __iomem *bar2_addr; /* address of BAR2 Queue registers */
480 unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */
625ba2c2
DM		 481};
482
483/* A packet gather list */
484struct pkt_gl {
e91b0f24 485 struct page_frag frags[MAX_SKB_FRAGS];
625ba2c2
DM		 486 void *va; /* virtual address of first byte */
487 unsigned int nfrags; /* # of fragments */
488 unsigned int tot_len; /* total length of fragments */
489};
490
491typedef int (*rspq_handler_t)(struct sge_rspq *q, const __be64 *rsp,
492 const struct pkt_gl *gl);
493
494struct sge_rspq { /* state for an SGE response queue */
495 struct napi_struct napi;
496 const __be64 *cur_desc; /* current descriptor in queue */
497 unsigned int cidx; /* consumer index */
498 u8 gen; /* current generation bit */
499 u8 intr_params; /* interrupt holdoff parameters */
500 u8 next_intr_params; /* holdoff params for next interrupt */
e553ec3f 501 u8 adaptive_rx;
625ba2c2
DM		 502 u8 pktcnt_idx; /* interrupt packet threshold */
503 u8 uld; /* ULD handling this queue */
504 u8 idx; /* queue index within its group */
505 int offset; /* offset into current Rx buffer */
506 u16 cntxt_id; /* SGE context id for the response q */
507 u16 abs_id; /* absolute SGE id for the response q */
508 __be64 *desc; /* address of HW response ring */
509 dma_addr_t phys_addr; /* physical address of the ring */
df64e4d3
HS		 510 void __iomem *bar2_addr; /* address of BAR2 Queue registers */
511 unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */
625ba2c2
DM		 512 unsigned int iqe_len; /* entry size */
513 unsigned int size; /* capacity of response queue */
514 struct adapter *adap;
515 struct net_device *netdev; /* associated net device */
516 rspq_handler_t handler;
3a336cb1
HS		 517#ifdef CONFIG_NET_RX_BUSY_POLL
518#define CXGB_POLL_STATE_IDLE 0
519#define CXGB_POLL_STATE_NAPI BIT(0) /* NAPI owns this poll */
520#define CXGB_POLL_STATE_POLL BIT(1) /* poll owns this poll */
521#define CXGB_POLL_STATE_NAPI_YIELD BIT(2) /* NAPI yielded this poll */
522#define CXGB_POLL_STATE_POLL_YIELD BIT(3) /* poll yielded this poll */
523#define CXGB_POLL_YIELD (CXGB_POLL_STATE_NAPI_YIELD | \
524 CXGB_POLL_STATE_POLL_YIELD)
525#define CXGB_POLL_LOCKED (CXGB_POLL_STATE_NAPI | \
526 CXGB_POLL_STATE_POLL)
527#define CXGB_POLL_USER_PEND (CXGB_POLL_STATE_POLL | \
528 CXGB_POLL_STATE_POLL_YIELD)
529 unsigned int bpoll_state;
530 spinlock_t bpoll_lock; /* lock for busy poll */
531#endif /* CONFIG_NET_RX_BUSY_POLL */
532
625ba2c2
DM		 533};
534
535struct sge_eth_stats { /* Ethernet queue statistics */
536 unsigned long pkts; /* # of ethernet packets */
537 unsigned long lro_pkts; /* # of LRO super packets */
538 unsigned long lro_merged; /* # of wire packets merged by LRO */
539 unsigned long rx_cso; /* # of Rx checksum offloads */
540 unsigned long vlan_ex; /* # of Rx VLAN extractions */
541 unsigned long rx_drops; /* # of packets dropped due to no mem */
542};
543
544struct sge_eth_rxq { /* SW Ethernet Rx queue */
545 struct sge_rspq rspq;
546 struct sge_fl fl;
547 struct sge_eth_stats stats;
548} ____cacheline_aligned_in_smp;
549
550struct sge_ofld_stats { /* offload queue statistics */
551 unsigned long pkts; /* # of packets */
552 unsigned long imm; /* # of immediate-data packets */
553 unsigned long an; /* # of asynchronous notifications */
554 unsigned long nomem; /* # of responses deferred due to no mem */
555};
556
557struct sge_ofld_rxq { /* SW offload Rx queue */
558 struct sge_rspq rspq;
559 struct sge_fl fl;
560 struct sge_ofld_stats stats;
561} ____cacheline_aligned_in_smp;
562
563struct tx_desc {
564 __be64 flit[8];
565};
566
567struct tx_sw_desc;
568
569struct sge_txq {
570 unsigned int in_use; /* # of in-use Tx descriptors */
571 unsigned int size; /* # of descriptors */
572 unsigned int cidx; /* SW consumer index */
573 unsigned int pidx; /* producer index */
574 unsigned long stops; /* # of times q has been stopped */
575 unsigned long restarts; /* # of queue restarts */
576 unsigned int cntxt_id; /* SGE context id for the Tx q */
577 struct tx_desc *desc; /* address of HW Tx descriptor ring */
578 struct tx_sw_desc *sdesc; /* address of SW Tx descriptor ring */
579 struct sge_qstat *stat; /* queue status entry */
580 dma_addr_t phys_addr; /* physical address of the ring */
3069ee9b
VP		 581 spinlock_t db_lock;
582 int db_disabled;
583 unsigned short db_pidx;
05eb2389 584 unsigned short db_pidx_inc;
df64e4d3
HS		 585 void __iomem *bar2_addr; /* address of BAR2 Queue registers */
586 unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */
625ba2c2
DM		 587};
588
589struct sge_eth_txq { /* state for an SGE Ethernet Tx queue */
590 struct sge_txq q;
591 struct netdev_queue *txq; /* associated netdev TX queue */
10b00466
AB		 592#ifdef CONFIG_CHELSIO_T4_DCB
593 u8 dcb_prio; /* DCB Priority bound to queue */
594#endif
625ba2c2
DM		 595 unsigned long tso; /* # of TSO requests */
596 unsigned long tx_cso; /* # of Tx checksum offloads */
597 unsigned long vlan_ins; /* # of Tx VLAN insertions */
598 unsigned long mapping_err; /* # of I/O MMU packet mapping errors */
599} ____cacheline_aligned_in_smp;
600
601struct sge_ofld_txq { /* state for an SGE offload Tx queue */
602 struct sge_txq q;
603 struct adapter *adap;
604 struct sk_buff_head sendq; /* list of backpressured packets */
605 struct tasklet_struct qresume_tsk; /* restarts the queue */
606 u8 full; /* the Tx ring is full */
607 unsigned long mapping_err; /* # of I/O MMU packet mapping errors */
608} ____cacheline_aligned_in_smp;
609
610struct sge_ctrl_txq { /* state for an SGE control Tx queue */
611 struct sge_txq q;
612 struct adapter *adap;
613 struct sk_buff_head sendq; /* list of backpressured packets */
614 struct tasklet_struct qresume_tsk; /* restarts the queue */
615 u8 full; /* the Tx ring is full */
616} ____cacheline_aligned_in_smp;
617
618struct sge {
619 struct sge_eth_txq ethtxq[MAX_ETH_QSETS];
620 struct sge_ofld_txq ofldtxq[MAX_OFLD_QSETS];
621 struct sge_ctrl_txq ctrlq[MAX_CTRL_QUEUES];
622
623 struct sge_eth_rxq ethrxq[MAX_ETH_QSETS];
624 struct sge_ofld_rxq ofldrxq[MAX_OFLD_QSETS];
625 struct sge_ofld_rxq rdmarxq[MAX_RDMA_QUEUES];
cf38be6d 626 struct sge_ofld_rxq rdmaciq[MAX_RDMA_CIQS];
625ba2c2
DM		 627 struct sge_rspq fw_evtq ____cacheline_aligned_in_smp;
628
629 struct sge_rspq intrq ____cacheline_aligned_in_smp;
630 spinlock_t intrq_lock;
631
632 u16 max_ethqsets; /* # of available Ethernet queue sets */
633 u16 ethqsets; /* # of active Ethernet queue sets */
634 u16 ethtxq_rover; /* Tx queue to clean up next */
635 u16 ofldqsets; /* # of active offload queue sets */
636 u16 rdmaqs; /* # of available RDMA Rx queues */
cf38be6d 637 u16 rdmaciqs; /* # of available RDMA concentrator IQs */
625ba2c2 638 u16 ofld_rxq[MAX_OFLD_QSETS];
f36e58e5
HS		 639 u16 rdma_rxq[MAX_RDMA_QUEUES];
640 u16 rdma_ciq[MAX_RDMA_CIQS];
625ba2c2
DM		 641 u16 timer_val[SGE_NTIMERS];
642 u8 counter_val[SGE_NCOUNTERS];
52367a76
VP		 643 u32 fl_pg_order; /* large page allocation size */
644 u32 stat_len; /* length of status page at ring end */
645 u32 pktshift; /* padding between CPL & packet data */
646 u32 fl_align; /* response queue message alignment */
647 u32 fl_starve_thres; /* Free List starvation threshold */
0f4d201f 648
a3bfb617 649 struct sge_idma_monitor_state idma_monitor;
e46dab4d 650 unsigned int egr_start;
4b8e27a8 651 unsigned int egr_sz;
e46dab4d 652 unsigned int ingr_start;
4b8e27a8
HS		 653 unsigned int ingr_sz;
654 void **egr_map; /* qid->queue egress queue map */
655 struct sge_rspq **ingr_map; /* qid->queue ingress queue map */
656 unsigned long *starving_fl;
657 unsigned long *txq_maperr;
5b377d11 658 unsigned long *blocked_fl;
625ba2c2
DM		 659 struct timer_list rx_timer; /* refills starving FLs */
660 struct timer_list tx_timer; /* checks Tx queues */
661};
662
663#define for_each_ethrxq(sge, i) for (i = 0; i < (sge)->ethqsets; i++)
664#define for_each_ofldrxq(sge, i) for (i = 0; i < (sge)->ofldqsets; i++)
665#define for_each_rdmarxq(sge, i) for (i = 0; i < (sge)->rdmaqs; i++)
cf38be6d 666#define for_each_rdmaciq(sge, i) for (i = 0; i < (sge)->rdmaciqs; i++)
625ba2c2
DM		 667
668struct l2t_data;
669
2422d9a3
SR		 670#ifdef CONFIG_PCI_IOV
671
7d6727cf
SR		 672/* T4 supports SRIOV on PF0-3 and T5 on PF0-7. However, the Serial
673 * Configuration initialization for T5 only has SR-IOV functionality enabled
674 * on PF0-3 in order to simplify everything.
2422d9a3 675 */
7d6727cf 676#define NUM_OF_PF_WITH_SRIOV 4
2422d9a3
SR		 677
678#endif
679
625ba2c2
DM		 680struct adapter {
681 void __iomem *regs;
22adfe0a 682 void __iomem *bar2;
0abfd152 683 u32 t4_bar0;
625ba2c2
DM		 684 struct pci_dev *pdev;
685 struct device *pdev_dev;
3069ee9b 686 unsigned int mbox;
b2612722 687 unsigned int pf;
060e0c75 688 unsigned int flags;
2422d9a3 689 enum chip_type chip;
625ba2c2 690
625ba2c2
DM		 691 int msg_enable;
692
693 struct adapter_params params;
694 struct cxgb4_virt_res vres;
695 unsigned int swintr;
696
697 unsigned int wol;
698
699 struct {
700 unsigned short vec;
8cd18ac4 701 char desc[IFNAMSIZ + 10];
625ba2c2
DM		 702 } msix_info[MAX_INGQ + 1];
703
704 struct sge sge;
705
706 struct net_device *port[MAX_NPORTS];
707 u8 chan_map[NCHAN]; /* channel -> port map */
708
793dad94 709 u32 filter_mode;
636f9d37
VP		 710 unsigned int l2t_start;
711 unsigned int l2t_end;
625ba2c2 712 struct l2t_data *l2t;
b5a02f50
AB		 713 unsigned int clipt_start;
714 unsigned int clipt_end;
715 struct clip_tbl *clipt;
625ba2c2
DM		 716 void *uld_handle[CXGB4_ULD_MAX];
717 struct list_head list_node;
01bcca68 718 struct list_head rcu_node;
625ba2c2
DM		 719
720 struct tid_info tids;
721 void **tid_release_head;
722 spinlock_t tid_release_lock;
29aaee65 723 struct workqueue_struct *workq;
625ba2c2 724 struct work_struct tid_release_task;
881806bc
VP		 725 struct work_struct db_full_task;
726 struct work_struct db_drop_task;
625ba2c2
DM		 727 bool tid_release_task_busy;
728
729 struct dentry *debugfs_root;
730
731 spinlock_t stats_lock;
fc5ab020 732 spinlock_t win0_lock ____cacheline_aligned_in_smp;
625ba2c2
DM		 733};
734
f2b7e78d
VP		 735/* Defined bit width of user definable filter tuples
736 */
737#define ETHTYPE_BITWIDTH 16
738#define FRAG_BITWIDTH 1
739#define MACIDX_BITWIDTH 9
740#define FCOE_BITWIDTH 1
741#define IPORT_BITWIDTH 3
742#define MATCHTYPE_BITWIDTH 3
743#define PROTO_BITWIDTH 8
744#define TOS_BITWIDTH 8
745#define PF_BITWIDTH 8
746#define VF_BITWIDTH 8
747#define IVLAN_BITWIDTH 16
748#define OVLAN_BITWIDTH 16
749
750/* Filter matching rules. These consist of a set of ingress packet field
751 * (value, mask) tuples. The associated ingress packet field matches the
752 * tuple when ((field & mask) == value). (Thus a wildcard "don't care" field
753 * rule can be constructed by specifying a tuple of (0, 0).) A filter rule
754 * matches an ingress packet when all of the individual individual field
755 * matching rules are true.
756 *
757 * Partial field masks are always valid, however, while it may be easy to
758 * understand their meanings for some fields (e.g. IP address to match a
759 * subnet), for others making sensible partial masks is less intuitive (e.g.
760 * MPS match type) ...
761 *
762 * Most of the following data structures are modeled on T4 capabilities.
763 * Drivers for earlier chips use the subsets which make sense for those chips.
764 * We really need to come up with a hardware-independent mechanism to
765 * represent hardware filter capabilities ...
766 */
767struct ch_filter_tuple {
768 /* Compressed header matching field rules. The TP_VLAN_PRI_MAP
769 * register selects which of these fields will participate in the
770 * filter match rules -- up to a maximum of 36 bits. Because
771 * TP_VLAN_PRI_MAP is a global register, all filters must use the same
772 * set of fields.
773 */
774 uint32_t ethtype:ETHTYPE_BITWIDTH; /* Ethernet type */
775 uint32_t frag:FRAG_BITWIDTH; /* IP fragmentation header */
776 uint32_t ivlan_vld:1; /* inner VLAN valid */
777 uint32_t ovlan_vld:1; /* outer VLAN valid */
778 uint32_t pfvf_vld:1; /* PF/VF valid */
779 uint32_t macidx:MACIDX_BITWIDTH; /* exact match MAC index */
780 uint32_t fcoe:FCOE_BITWIDTH; /* FCoE packet */
781 uint32_t iport:IPORT_BITWIDTH; /* ingress port */
782 uint32_t matchtype:MATCHTYPE_BITWIDTH; /* MPS match type */
783 uint32_t proto:PROTO_BITWIDTH; /* protocol type */
784 uint32_t tos:TOS_BITWIDTH; /* TOS/Traffic Type */
785 uint32_t pf:PF_BITWIDTH; /* PCI-E PF ID */
786 uint32_t vf:VF_BITWIDTH; /* PCI-E VF ID */
787 uint32_t ivlan:IVLAN_BITWIDTH; /* inner VLAN */
788 uint32_t ovlan:OVLAN_BITWIDTH; /* outer VLAN */
789
790 /* Uncompressed header matching field rules. These are always
791 * available for field rules.
792 */
793 uint8_t lip[16]; /* local IP address (IPv4 in [3:0]) */
794 uint8_t fip[16]; /* foreign IP address (IPv4 in [3:0]) */
795 uint16_t lport; /* local port */
796 uint16_t fport; /* foreign port */
797};
798
799/* A filter ioctl command.
800 */
801struct ch_filter_specification {
802 /* Administrative fields for filter.
803 */
804 uint32_t hitcnts:1; /* count filter hits in TCB */
805 uint32_t prio:1; /* filter has priority over active/server */
806
807 /* Fundamental filter typing. This is the one element of filter
808 * matching that doesn't exist as a (value, mask) tuple.
809 */
810 uint32_t type:1; /* 0 => IPv4, 1 => IPv6 */
811
812 /* Packet dispatch information. Ingress packets which match the
813 * filter rules will be dropped, passed to the host or switched back
814 * out as egress packets.
815 */
816 uint32_t action:2; /* drop, pass, switch */
817
818 uint32_t rpttid:1; /* report TID in RSS hash field */
819
820 uint32_t dirsteer:1; /* 0 => RSS, 1 => steer to iq */
821 uint32_t iq:10; /* ingress queue */
822
823 uint32_t maskhash:1; /* dirsteer=0: store RSS hash in TCB */
824 uint32_t dirsteerhash:1;/* dirsteer=1: 0 => TCB contains RSS hash */
825 /* 1 => TCB contains IQ ID */
826
827 /* Switch proxy/rewrite fields. An ingress packet which matches a
828 * filter with "switch" set will be looped back out as an egress
829 * packet -- potentially with some Ethernet header rewriting.
830 */
831 uint32_t eport:2; /* egress port to switch packet out */
832 uint32_t newdmac:1; /* rewrite destination MAC address */
833 uint32_t newsmac:1; /* rewrite source MAC address */
834 uint32_t newvlan:2; /* rewrite VLAN Tag */
835 uint8_t dmac[ETH_ALEN]; /* new destination MAC address */
836 uint8_t smac[ETH_ALEN]; /* new source MAC address */
837 uint16_t vlan; /* VLAN Tag to insert */
838
839 /* Filter rule value/mask pairs.
840 */
841 struct ch_filter_tuple val;
842 struct ch_filter_tuple mask;
843};
844
845enum {
846 FILTER_PASS = 0, /* default */
847 FILTER_DROP,
848 FILTER_SWITCH
849};
850
851enum {
852 VLAN_NOCHANGE = 0, /* default */
853 VLAN_REMOVE,
854 VLAN_INSERT,
855 VLAN_REWRITE
856};
857
ab4b583b
HS		 858static inline int is_t6(enum chip_type chip)
859{
860 return CHELSIO_CHIP_VERSION(chip) == CHELSIO_T6;
861}
862
2422d9a3
SR		 863static inline int is_t5(enum chip_type chip)
864{
d14807dd 865 return CHELSIO_CHIP_VERSION(chip) == CHELSIO_T5;
2422d9a3
SR		 866}
867
868static inline int is_t4(enum chip_type chip)
869{
d14807dd 870 return CHELSIO_CHIP_VERSION(chip) == CHELSIO_T4;
2422d9a3
SR		 871}
872
625ba2c2
DM		 873static inline u32 t4_read_reg(struct adapter *adap, u32 reg_addr)
874{
875 return readl(adap->regs + reg_addr);
876}
877
878static inline void t4_write_reg(struct adapter *adap, u32 reg_addr, u32 val)
879{
880 writel(val, adap->regs + reg_addr);
881}
882
883#ifndef readq
884static inline u64 readq(const volatile void __iomem *addr)
885{
886 return readl(addr) + ((u64)readl(addr + 4) << 32);
887}
888
889static inline void writeq(u64 val, volatile void __iomem *addr)
890{
891 writel(val, addr);
892 writel(val >> 32, addr + 4);
893}
894#endif
895
896static inline u64 t4_read_reg64(struct adapter *adap, u32 reg_addr)
897{
898 return readq(adap->regs + reg_addr);
899}
900
901static inline void t4_write_reg64(struct adapter *adap, u32 reg_addr, u64 val)
902{
903 writeq(val, adap->regs + reg_addr);
904}
905
906/**
907 * netdev2pinfo - return the port_info structure associated with a net_device
908 * @dev: the netdev
909 *
910 * Return the struct port_info associated with a net_device
911 */
912static inline struct port_info *netdev2pinfo(const struct net_device *dev)
913{
914 return netdev_priv(dev);
915}
916
917/**
918 * adap2pinfo - return the port_info of a port
919 * @adap: the adapter
920 * @idx: the port index
921 *
922 * Return the port_info structure for the port of the given index.
923 */
924static inline struct port_info *adap2pinfo(struct adapter *adap, int idx)
925{
926 return netdev_priv(adap->port[idx]);
927}
928
929/**
930 * netdev2adap - return the adapter structure associated with a net_device
931 * @dev: the netdev
932 *
933 * Return the struct adapter associated with a net_device
934 */
935static inline struct adapter *netdev2adap(const struct net_device *dev)
936{
937 return netdev2pinfo(dev)->adapter;
938}
939
3a336cb1
HS		 940#ifdef CONFIG_NET_RX_BUSY_POLL
941static inline void cxgb_busy_poll_init_lock(struct sge_rspq *q)
942{
943 spin_lock_init(&q->bpoll_lock);
944 q->bpoll_state = CXGB_POLL_STATE_IDLE;
945}
946
947static inline bool cxgb_poll_lock_napi(struct sge_rspq *q)
948{
949 bool rc = true;
950
951 spin_lock(&q->bpoll_lock);
952 if (q->bpoll_state & CXGB_POLL_LOCKED) {
953 q->bpoll_state |= CXGB_POLL_STATE_NAPI_YIELD;
954 rc = false;
955 } else {
956 q->bpoll_state = CXGB_POLL_STATE_NAPI;
957 }
958 spin_unlock(&q->bpoll_lock);
959 return rc;
960}
961
962static inline bool cxgb_poll_unlock_napi(struct sge_rspq *q)
963{
964 bool rc = false;
965
966 spin_lock(&q->bpoll_lock);
967 if (q->bpoll_state & CXGB_POLL_STATE_POLL_YIELD)
968 rc = true;
969 q->bpoll_state = CXGB_POLL_STATE_IDLE;
970 spin_unlock(&q->bpoll_lock);
971 return rc;
972}
973
974static inline bool cxgb_poll_lock_poll(struct sge_rspq *q)
975{
976 bool rc = true;
977
978 spin_lock_bh(&q->bpoll_lock);
979 if (q->bpoll_state & CXGB_POLL_LOCKED) {
980 q->bpoll_state |= CXGB_POLL_STATE_POLL_YIELD;
981 rc = false;
982 } else {
983 q->bpoll_state |= CXGB_POLL_STATE_POLL;
984 }
985 spin_unlock_bh(&q->bpoll_lock);
986 return rc;
987}
988
989static inline bool cxgb_poll_unlock_poll(struct sge_rspq *q)
990{
991 bool rc = false;
992
993 spin_lock_bh(&q->bpoll_lock);
994 if (q->bpoll_state & CXGB_POLL_STATE_POLL_YIELD)
995 rc = true;
996 q->bpoll_state = CXGB_POLL_STATE_IDLE;
997 spin_unlock_bh(&q->bpoll_lock);
998 return rc;
999}
1000
1001static inline bool cxgb_poll_busy_polling(struct sge_rspq *q)
1002{
1003 return q->bpoll_state & CXGB_POLL_USER_PEND;
1004}
1005#else
1006static inline void cxgb_busy_poll_init_lock(struct sge_rspq *q)
1007{
1008}
1009
1010static inline bool cxgb_poll_lock_napi(struct sge_rspq *q)
1011{
1012 return true;
1013}
1014
1015static inline bool cxgb_poll_unlock_napi(struct sge_rspq *q)
1016{
1017 return false;
1018}
1019
1020static inline bool cxgb_poll_lock_poll(struct sge_rspq *q)
1021{
1022 return false;
1023}
1024
1025static inline bool cxgb_poll_unlock_poll(struct sge_rspq *q)
1026{
1027 return false;
1028}
1029
1030static inline bool cxgb_poll_busy_polling(struct sge_rspq *q)
1031{
1032 return false;
1033}
1034#endif /* CONFIG_NET_RX_BUSY_POLL */
1035
812034f1
HS		 1036/* Return a version number to identify the type of adapter. The scheme is:
1037 * - bits 0..9: chip version
1038 * - bits 10..15: chip revision
1039 * - bits 16..23: register dump version
1040 */
1041static inline unsigned int mk_adap_vers(struct adapter *ap)
1042{
1043 return CHELSIO_CHIP_VERSION(ap->params.chip) |
1044 (CHELSIO_CHIP_RELEASE(ap->params.chip) << 10) | (1 << 16);
1045}
1046
1047/* Return a queue's interrupt hold-off time in us. 0 means no timer. */
1048static inline unsigned int qtimer_val(const struct adapter *adap,
1049 const struct sge_rspq *q)
1050{
1051 unsigned int idx = q->intr_params >> 1;
1052
1053 return idx < SGE_NTIMERS ? adap->sge.timer_val[idx] : 0;
1054}
1055
1056/* driver version & name used for ethtool_drvinfo */
1057extern char cxgb4_driver_name[];
1058extern const char cxgb4_driver_version[];
1059
625ba2c2
DM		 1060void t4_os_portmod_changed(const struct adapter *adap, int port_id);
1061void t4_os_link_changed(struct adapter *adap, int port_id, int link_stat);
1062
1063void *t4_alloc_mem(size_t size);
625ba2c2
DM		 1064
1065void t4_free_sge_resources(struct adapter *adap);
5fa76694 1066void t4_free_ofld_rxqs(struct adapter *adap, int n, struct sge_ofld_rxq *q);
625ba2c2
DM		 1067irq_handler_t t4_intr_handler(struct adapter *adap);
1068netdev_tx_t t4_eth_xmit(struct sk_buff *skb, struct net_device *dev);
1069int t4_ethrx_handler(struct sge_rspq *q, const __be64 *rsp,
1070 const struct pkt_gl *gl);
1071int t4_mgmt_tx(struct adapter *adap, struct sk_buff *skb);
1072int t4_ofld_send(struct adapter *adap, struct sk_buff *skb);
1073int t4_sge_alloc_rxq(struct adapter *adap, struct sge_rspq *iq, bool fwevtq,
1074 struct net_device *dev, int intr_idx,
145ef8a5 1075 struct sge_fl *fl, rspq_handler_t hnd, int cong);
625ba2c2
DM		 1076int t4_sge_alloc_eth_txq(struct adapter *adap, struct sge_eth_txq *txq,
1077 struct net_device *dev, struct netdev_queue *netdevq,
1078 unsigned int iqid);
1079int t4_sge_alloc_ctrl_txq(struct adapter *adap, struct sge_ctrl_txq *txq,
1080 struct net_device *dev, unsigned int iqid,
1081 unsigned int cmplqid);
1082int t4_sge_alloc_ofld_txq(struct adapter *adap, struct sge_ofld_txq *txq,
1083 struct net_device *dev, unsigned int iqid);
1084irqreturn_t t4_sge_intr_msix(int irq, void *cookie);
52367a76 1085int t4_sge_init(struct adapter *adap);
625ba2c2
DM		 1086void t4_sge_start(struct adapter *adap);
1087void t4_sge_stop(struct adapter *adap);
3a336cb1 1088int cxgb_busy_poll(struct napi_struct *napi);
812034f1
HS		 1089int cxgb4_set_rspq_intr_params(struct sge_rspq *q, unsigned int us,
1090 unsigned int cnt);
1091void cxgb4_set_ethtool_ops(struct net_device *netdev);
1092int cxgb4_write_rss(const struct port_info *pi, const u16 *queues);
3069ee9b 1093extern int dbfifo_int_thresh;
625ba2c2
DM		 1094
1095#define for_each_port(adapter, iter) \
1096 for (iter = 0; iter < (adapter)->params.nports; ++iter)
1097
9a4da2cd
VP		 1098static inline int is_bypass(struct adapter *adap)
1099{
1100 return adap->params.bypass;
1101}
1102
1103static inline int is_bypass_device(int device)
1104{
1105 /* this should be set based upon device capabilities */
1106 switch (device) {
1107 case 0x440b:
1108 case 0x440c:
1109 return 1;
1110 default:
1111 return 0;
1112 }
1113}
1114
01b69614
HS		 1115static inline int is_10gbt_device(int device)
1116{
1117 /* this should be set based upon device capabilities */
1118 switch (device) {
1119 case 0x4409:
1120 case 0x4486:
1121 return 1;
1122
1123 default:
1124 return 0;
1125 }
1126}
1127
625ba2c2
DM		 1128static inline unsigned int core_ticks_per_usec(const struct adapter *adap)
1129{
1130 return adap->params.vpd.cclk / 1000;
1131}
1132
1133static inline unsigned int us_to_core_ticks(const struct adapter *adap,
1134 unsigned int us)
1135{
1136 return (us * adap->params.vpd.cclk) / 1000;
1137}
1138
52367a76
VP		 1139static inline unsigned int core_ticks_to_us(const struct adapter *adapter,
1140 unsigned int ticks)
1141{
1142 /* add Core Clock / 2 to round ticks to nearest uS */
1143 return ((ticks * 1000 + adapter->params.vpd.cclk/2) /
1144 adapter->params.vpd.cclk);
1145}
1146
625ba2c2
DM		 1147void t4_set_reg_field(struct adapter *adap, unsigned int addr, u32 mask,
1148 u32 val);
1149
01b69614
HS		 1150int t4_wr_mbox_meat_timeout(struct adapter *adap, int mbox, const void *cmd,
1151 int size, void *rpl, bool sleep_ok, int timeout);
625ba2c2
DM		 1152int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size,
1153 void *rpl, bool sleep_ok);
1154
01b69614
HS		 1155static inline int t4_wr_mbox_timeout(struct adapter *adap, int mbox,
1156 const void *cmd, int size, void *rpl,
1157 int timeout)
1158{
1159 return t4_wr_mbox_meat_timeout(adap, mbox, cmd, size, rpl, true,
1160 timeout);
1161}
1162
625ba2c2
DM		 1163static inline int t4_wr_mbox(struct adapter *adap, int mbox, const void *cmd,
1164 int size, void *rpl)
1165{
1166 return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, true);
1167}
1168
1169static inline int t4_wr_mbox_ns(struct adapter *adap, int mbox, const void *cmd,
1170 int size, void *rpl)
1171{
1172 return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, false);
1173}
1174
13ee15d3
VP		 1175void t4_write_indirect(struct adapter *adap, unsigned int addr_reg,
1176 unsigned int data_reg, const u32 *vals,
1177 unsigned int nregs, unsigned int start_idx);
f2b7e78d
VP		 1178void t4_read_indirect(struct adapter *adap, unsigned int addr_reg,
1179 unsigned int data_reg, u32 *vals, unsigned int nregs,
1180 unsigned int start_idx);
0abfd152 1181void t4_hw_pci_read_cfg4(struct adapter *adapter, int reg, u32 *val);
f2b7e78d
VP		 1182
1183struct fw_filter_wr;
1184
625ba2c2
DM		 1185void t4_intr_enable(struct adapter *adapter);
1186void t4_intr_disable(struct adapter *adapter);
625ba2c2
DM		 1187int t4_slow_intr_handler(struct adapter *adapter);
1188
8203b509 1189int t4_wait_dev_ready(void __iomem *regs);
625ba2c2
DM		 1190int t4_link_start(struct adapter *adap, unsigned int mbox, unsigned int port,
1191 struct link_config *lc);
1192int t4_restart_aneg(struct adapter *adap, unsigned int mbox, unsigned int port);
fc5ab020 1193
b562fc37
HS		 1194u32 t4_read_pcie_cfg4(struct adapter *adap, int reg);
1195u32 t4_get_util_window(struct adapter *adap);
1196void t4_setup_memwin(struct adapter *adap, u32 memwin_base, u32 window);
1197
fc5ab020
HS		 1198#define T4_MEMORY_WRITE 0
1199#define T4_MEMORY_READ 1
1200int t4_memory_rw(struct adapter *adap, int win, int mtype, u32 addr, u32 len,
f01aa633 1201 void *buf, int dir);
fc5ab020
HS		 1202static inline int t4_memory_write(struct adapter *adap, int mtype, u32 addr,
1203 u32 len, __be32 *buf)
1204{
1205 return t4_memory_rw(adap, 0, mtype, addr, len, buf, 0);
1206}
1207
812034f1
HS		 1208unsigned int t4_get_regs_len(struct adapter *adapter);
1209void t4_get_regs(struct adapter *adap, void *buf, size_t buf_size);
1210
625ba2c2 1211int t4_seeprom_wp(struct adapter *adapter, bool enable);
636f9d37 1212int get_vpd_params(struct adapter *adapter, struct vpd_params *p);
49216c1c
HS		 1213int t4_read_flash(struct adapter *adapter, unsigned int addr,
1214 unsigned int nwords, u32 *data, int byte_oriented);
625ba2c2 1215int t4_load_fw(struct adapter *adapter, const u8 *fw_data, unsigned int size);
01b69614
HS		 1216int t4_load_phy_fw(struct adapter *adap,
1217 int win, spinlock_t *lock,
1218 int (*phy_fw_version)(const u8 *, size_t),
1219 const u8 *phy_fw_data, size_t phy_fw_size);
1220int t4_phy_fw_ver(struct adapter *adap, int *phy_fw_ver);
49216c1c 1221int t4_fwcache(struct adapter *adap, enum fw_params_param_dev_fwcache op);
22c0b963
HS		 1222int t4_fw_upgrade(struct adapter *adap, unsigned int mbox,
1223 const u8 *fw_data, unsigned int size, int force);
636f9d37 1224unsigned int t4_flash_cfg_addr(struct adapter *adapter);
16e47624
HS		 1225int t4_get_fw_version(struct adapter *adapter, u32 *vers);
1226int t4_get_tp_version(struct adapter *adapter, u32 *vers);
ba3f8cd5 1227int t4_get_exprom_version(struct adapter *adapter, u32 *vers);
16e47624
HS		 1228int t4_prep_fw(struct adapter *adap, struct fw_info *fw_info,
1229 const u8 *fw_data, unsigned int fw_size,
1230 struct fw_hdr *card_fw, enum dev_state state, int *reset);
625ba2c2 1231int t4_prep_adapter(struct adapter *adapter);
e85c9a7a
HS		 1232
1233enum t4_bar2_qtype { T4_BAR2_QTYPE_EGRESS, T4_BAR2_QTYPE_INGRESS };
b2612722 1234int t4_bar2_sge_qregs(struct adapter *adapter,
e85c9a7a
HS		 1235 unsigned int qid,
1236 enum t4_bar2_qtype qtype,
1237 u64 *pbar2_qoffset,
1238 unsigned int *pbar2_qid);
1239
dc9daab2
HS		 1240unsigned int qtimer_val(const struct adapter *adap,
1241 const struct sge_rspq *q);
ae469b68
HS		 1242
1243int t4_init_devlog_params(struct adapter *adapter);
e85c9a7a 1244int t4_init_sge_params(struct adapter *adapter);
dcf7b6f5
KS		 1245int t4_init_tp_params(struct adapter *adap);
1246int t4_filter_field_shift(const struct adapter *adap, int filter_sel);
c035e183 1247int t4_init_rss_mode(struct adapter *adap, int mbox);
625ba2c2
DM		 1248int t4_port_init(struct adapter *adap, int mbox, int pf, int vf);
1249void t4_fatal_err(struct adapter *adapter);
625ba2c2
DM		 1250int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid,
1251 int start, int n, const u16 *rspq, unsigned int nrspq);
1252int t4_config_glbl_rss(struct adapter *adapter, int mbox, unsigned int mode,
1253 unsigned int flags);
c035e183
HS		 1254int t4_config_vi_rss(struct adapter *adapter, int mbox, unsigned int viid,
1255 unsigned int flags, unsigned int defq);
688ea5fe
HS		 1256int t4_read_rss(struct adapter *adapter, u16 *entries);
1257void t4_read_rss_key(struct adapter *adapter, u32 *key);
1258void t4_write_rss_key(struct adapter *adap, const u32 *key, int idx);
1259void t4_read_rss_pf_config(struct adapter *adapter, unsigned int index,
1260 u32 *valp);
1261void t4_read_rss_vf_config(struct adapter *adapter, unsigned int index,
1262 u32 *vfl, u32 *vfh);
1263u32 t4_read_rss_pf_map(struct adapter *adapter);
1264u32 t4_read_rss_pf_mask(struct adapter *adapter);
1265
145ef8a5 1266unsigned int t4_get_mps_bg_map(struct adapter *adapter, int idx);
b3bbe36a
HS		 1267void t4_pmtx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]);
1268void t4_pmrx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]);
e5f0e43b
HS		 1269int t4_read_cim_ibq(struct adapter *adap, unsigned int qid, u32 *data,
1270 size_t n);
c778af7d
HS		 1271int t4_read_cim_obq(struct adapter *adap, unsigned int qid, u32 *data,
1272 size_t n);
f1ff24aa
HS		 1273int t4_cim_read(struct adapter *adap, unsigned int addr, unsigned int n,
1274 unsigned int *valp);
1275int t4_cim_write(struct adapter *adap, unsigned int addr, unsigned int n,
1276 const unsigned int *valp);
1277int t4_cim_read_la(struct adapter *adap, u32 *la_buf, unsigned int *wrptr);
74b3092c 1278void t4_read_cimq_cfg(struct adapter *adap, u16 *base, u16 *size, u16 *thres);
72aca4bf 1279const char *t4_get_port_type_description(enum fw_port_type port_type);
625ba2c2 1280void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p);
625ba2c2 1281void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log);
bad43792 1282void t4_read_cong_tbl(struct adapter *adap, u16 incr[NMTUS][NCCTRL_WIN]);
636f9d37
VP		 1283void t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr,
1284 unsigned int mask, unsigned int val);
2d277b3b 1285void t4_tp_read_la(struct adapter *adap, u64 *la_buf, unsigned int *wrptr);
625ba2c2
DM		 1286void t4_tp_get_tcp_stats(struct adapter *adap, struct tp_tcp_stats *v4,
1287 struct tp_tcp_stats *v6);
1288void t4_load_mtus(struct adapter *adap, const unsigned short *mtus,
1289 const unsigned short *alpha, const unsigned short *beta);
1290
797ff0f5
HS		 1291void t4_ulprx_read_la(struct adapter *adap, u32 *la_buf);
1292
f2b7e78d
VP		 1293void t4_mk_filtdelwr(unsigned int ftid, struct fw_filter_wr *wr, int qid);
1294
625ba2c2
DM		 1295void t4_wol_magic_enable(struct adapter *adap, unsigned int port,
1296 const u8 *addr);
1297int t4_wol_pat_enable(struct adapter *adap, unsigned int port, unsigned int map,
1298 u64 mask0, u64 mask1, unsigned int crc, bool enable);
1299
1300int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox,
1301 enum dev_master master, enum dev_state *state);
1302int t4_fw_bye(struct adapter *adap, unsigned int mbox);
1303int t4_early_init(struct adapter *adap, unsigned int mbox);
1304int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset);
636f9d37
VP		 1305int t4_fixup_host_params(struct adapter *adap, unsigned int page_size,
1306 unsigned int cache_line_size);
1307int t4_fw_initialize(struct adapter *adap, unsigned int mbox);
625ba2c2
DM		 1308int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
1309 unsigned int vf, unsigned int nparams, const u32 *params,
1310 u32 *val);
01b69614
HS		 1311int t4_query_params_rw(struct adapter *adap, unsigned int mbox, unsigned int pf,
1312 unsigned int vf, unsigned int nparams, const u32 *params,
1313 u32 *val, int rw);
1314int t4_set_params_timeout(struct adapter *adap, unsigned int mbox,
1315 unsigned int pf, unsigned int vf,
1316 unsigned int nparams, const u32 *params,
1317 const u32 *val, int timeout);
625ba2c2
DM		 1318int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
1319 unsigned int vf, unsigned int nparams, const u32 *params,
1320 const u32 *val);
1321int t4_cfg_pfvf(struct adapter *adap, unsigned int mbox, unsigned int pf,
1322 unsigned int vf, unsigned int txq, unsigned int txq_eth_ctrl,
1323 unsigned int rxqi, unsigned int rxq, unsigned int tc,
1324 unsigned int vi, unsigned int cmask, unsigned int pmask,
1325 unsigned int nexact, unsigned int rcaps, unsigned int wxcaps);
1326int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port,
1327 unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac,
1328 unsigned int *rss_size);
625ba2c2 1329int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid,
f8f5aafa
DM		 1330 int mtu, int promisc, int all_multi, int bcast, int vlanex,
1331 bool sleep_ok);
625ba2c2
DM		 1332int t4_alloc_mac_filt(struct adapter *adap, unsigned int mbox,
1333 unsigned int viid, bool free, unsigned int naddr,
1334 const u8 **addr, u16 *idx, u64 *hash, bool sleep_ok);
1335int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid,
1336 int idx, const u8 *addr, bool persist, bool add_smt);
1337int t4_set_addr_hash(struct adapter *adap, unsigned int mbox, unsigned int viid,
1338 bool ucast, u64 vec, bool sleep_ok);
688848b1
AB		 1339int t4_enable_vi_params(struct adapter *adap, unsigned int mbox,
1340 unsigned int viid, bool rx_en, bool tx_en, bool dcb_en);
625ba2c2
DM		 1341int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid,
1342 bool rx_en, bool tx_en);
1343int t4_identify_port(struct adapter *adap, unsigned int mbox, unsigned int viid,
1344 unsigned int nblinks);
1345int t4_mdio_rd(struct adapter *adap, unsigned int mbox, unsigned int phy_addr,
1346 unsigned int mmd, unsigned int reg, u16 *valp);
1347int t4_mdio_wr(struct adapter *adap, unsigned int mbox, unsigned int phy_addr,
1348 unsigned int mmd, unsigned int reg, u16 val);
625ba2c2
DM		 1349int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
1350 unsigned int vf, unsigned int iqtype, unsigned int iqid,
1351 unsigned int fl0id, unsigned int fl1id);
1352int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
1353 unsigned int vf, unsigned int eqid);
1354int t4_ctrl_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
1355 unsigned int vf, unsigned int eqid);
1356int t4_ofld_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
1357 unsigned int vf, unsigned int eqid);
1358int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl);
881806bc
VP		 1359void t4_db_full(struct adapter *adapter);
1360void t4_db_dropped(struct adapter *adapter);
8caa1e84
VP		 1361int t4_fwaddrspace_write(struct adapter *adap, unsigned int mbox,
1362 u32 addr, u32 val);
68bce192 1363void t4_sge_decode_idma_state(struct adapter *adapter, int state);
fd88b31a 1364void t4_free_mem(void *addr);
a3bfb617
HS		 1365void t4_idma_monitor_init(struct adapter *adapter,
1366 struct sge_idma_monitor_state *idma);
1367void t4_idma_monitor(struct adapter *adapter,
1368 struct sge_idma_monitor_state *idma,
1369 int hz, int ticks);
625ba2c2 1370#endif /* __CXGB4_H__ */
Linux kernel - Deliverables
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