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625ba2c2 DM |
1 | /* |
2 | * This file is part of the Chelsio T4 Ethernet driver for Linux. | |
3 | * | |
ce100b8b | 4 | * Copyright (c) 2003-2014 Chelsio Communications, Inc. All rights reserved. |
625ba2c2 DM |
5 | * |
6 | * This software is available to you under a choice of one of two | |
7 | * licenses. You may choose to be licensed under the terms of the GNU | |
8 | * General Public License (GPL) Version 2, available from the file | |
9 | * COPYING in the main directory of this source tree, or the | |
10 | * OpenIB.org BSD license below: | |
11 | * | |
12 | * Redistribution and use in source and binary forms, with or | |
13 | * without modification, are permitted provided that the following | |
14 | * conditions are met: | |
15 | * | |
16 | * - Redistributions of source code must retain the above | |
17 | * copyright notice, this list of conditions and the following | |
18 | * disclaimer. | |
19 | * | |
20 | * - Redistributions in binary form must reproduce the above | |
21 | * copyright notice, this list of conditions and the following | |
22 | * disclaimer in the documentation and/or other materials | |
23 | * provided with the distribution. | |
24 | * | |
25 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
26 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
27 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
28 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
29 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
30 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
31 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
32 | * SOFTWARE. | |
33 | */ | |
34 | ||
35 | #ifndef __CXGB4_H__ | |
36 | #define __CXGB4_H__ | |
37 | ||
dca4faeb VP |
38 | #include "t4_hw.h" |
39 | ||
625ba2c2 DM |
40 | #include <linux/bitops.h> |
41 | #include <linux/cache.h> | |
42 | #include <linux/interrupt.h> | |
43 | #include <linux/list.h> | |
44 | #include <linux/netdevice.h> | |
45 | #include <linux/pci.h> | |
46 | #include <linux/spinlock.h> | |
47 | #include <linux/timer.h> | |
c0b8b992 | 48 | #include <linux/vmalloc.h> |
625ba2c2 DM |
49 | #include <asm/io.h> |
50 | #include "cxgb4_uld.h" | |
625ba2c2 | 51 | |
16e47624 | 52 | #define T4FW_VERSION_MAJOR 0x01 |
c5ac9704 HS |
53 | #define T4FW_VERSION_MINOR 0x0C |
54 | #define T4FW_VERSION_MICRO 0x19 | |
16e47624 | 55 | #define T4FW_VERSION_BUILD 0x00 |
625ba2c2 | 56 | |
16e47624 | 57 | #define T5FW_VERSION_MAJOR 0x01 |
c5ac9704 HS |
58 | #define T5FW_VERSION_MINOR 0x0C |
59 | #define T5FW_VERSION_MICRO 0x19 | |
16e47624 | 60 | #define T5FW_VERSION_BUILD 0x00 |
2422d9a3 | 61 | |
3069ee9b VP |
62 | #define CH_WARN(adap, fmt, ...) dev_warn(adap->pdev_dev, fmt, ## __VA_ARGS__) |
63 | ||
625ba2c2 DM |
64 | enum { |
65 | MAX_NPORTS = 4, /* max # of ports */ | |
47d54d65 | 66 | SERNUM_LEN = 24, /* Serial # length */ |
625ba2c2 DM |
67 | EC_LEN = 16, /* E/C length */ |
68 | ID_LEN = 16, /* ID length */ | |
a94cd705 | 69 | PN_LEN = 16, /* Part Number length */ |
625ba2c2 DM |
70 | }; |
71 | ||
72 | enum { | |
73 | MEM_EDC0, | |
74 | MEM_EDC1, | |
2422d9a3 SR |
75 | MEM_MC, |
76 | MEM_MC0 = MEM_MC, | |
77 | MEM_MC1 | |
625ba2c2 DM |
78 | }; |
79 | ||
3069ee9b | 80 | enum { |
3eb4afbf VP |
81 | MEMWIN0_APERTURE = 2048, |
82 | MEMWIN0_BASE = 0x1b800, | |
3069ee9b VP |
83 | MEMWIN1_APERTURE = 32768, |
84 | MEMWIN1_BASE = 0x28000, | |
2422d9a3 | 85 | MEMWIN1_BASE_T5 = 0x52000, |
3eb4afbf VP |
86 | MEMWIN2_APERTURE = 65536, |
87 | MEMWIN2_BASE = 0x30000, | |
0abfd152 HS |
88 | MEMWIN2_APERTURE_T5 = 131072, |
89 | MEMWIN2_BASE_T5 = 0x60000, | |
3069ee9b VP |
90 | }; |
91 | ||
625ba2c2 DM |
92 | enum dev_master { |
93 | MASTER_CANT, | |
94 | MASTER_MAY, | |
95 | MASTER_MUST | |
96 | }; | |
97 | ||
98 | enum dev_state { | |
99 | DEV_STATE_UNINIT, | |
100 | DEV_STATE_INIT, | |
101 | DEV_STATE_ERR | |
102 | }; | |
103 | ||
104 | enum { | |
105 | PAUSE_RX = 1 << 0, | |
106 | PAUSE_TX = 1 << 1, | |
107 | PAUSE_AUTONEG = 1 << 2 | |
108 | }; | |
109 | ||
110 | struct port_stats { | |
111 | u64 tx_octets; /* total # of octets in good frames */ | |
112 | u64 tx_frames; /* all good frames */ | |
113 | u64 tx_bcast_frames; /* all broadcast frames */ | |
114 | u64 tx_mcast_frames; /* all multicast frames */ | |
115 | u64 tx_ucast_frames; /* all unicast frames */ | |
116 | u64 tx_error_frames; /* all error frames */ | |
117 | ||
118 | u64 tx_frames_64; /* # of Tx frames in a particular range */ | |
119 | u64 tx_frames_65_127; | |
120 | u64 tx_frames_128_255; | |
121 | u64 tx_frames_256_511; | |
122 | u64 tx_frames_512_1023; | |
123 | u64 tx_frames_1024_1518; | |
124 | u64 tx_frames_1519_max; | |
125 | ||
126 | u64 tx_drop; /* # of dropped Tx frames */ | |
127 | u64 tx_pause; /* # of transmitted pause frames */ | |
128 | u64 tx_ppp0; /* # of transmitted PPP prio 0 frames */ | |
129 | u64 tx_ppp1; /* # of transmitted PPP prio 1 frames */ | |
130 | u64 tx_ppp2; /* # of transmitted PPP prio 2 frames */ | |
131 | u64 tx_ppp3; /* # of transmitted PPP prio 3 frames */ | |
132 | u64 tx_ppp4; /* # of transmitted PPP prio 4 frames */ | |
133 | u64 tx_ppp5; /* # of transmitted PPP prio 5 frames */ | |
134 | u64 tx_ppp6; /* # of transmitted PPP prio 6 frames */ | |
135 | u64 tx_ppp7; /* # of transmitted PPP prio 7 frames */ | |
136 | ||
137 | u64 rx_octets; /* total # of octets in good frames */ | |
138 | u64 rx_frames; /* all good frames */ | |
139 | u64 rx_bcast_frames; /* all broadcast frames */ | |
140 | u64 rx_mcast_frames; /* all multicast frames */ | |
141 | u64 rx_ucast_frames; /* all unicast frames */ | |
142 | u64 rx_too_long; /* # of frames exceeding MTU */ | |
143 | u64 rx_jabber; /* # of jabber frames */ | |
144 | u64 rx_fcs_err; /* # of received frames with bad FCS */ | |
145 | u64 rx_len_err; /* # of received frames with length error */ | |
146 | u64 rx_symbol_err; /* symbol errors */ | |
147 | u64 rx_runt; /* # of short frames */ | |
148 | ||
149 | u64 rx_frames_64; /* # of Rx frames in a particular range */ | |
150 | u64 rx_frames_65_127; | |
151 | u64 rx_frames_128_255; | |
152 | u64 rx_frames_256_511; | |
153 | u64 rx_frames_512_1023; | |
154 | u64 rx_frames_1024_1518; | |
155 | u64 rx_frames_1519_max; | |
156 | ||
157 | u64 rx_pause; /* # of received pause frames */ | |
158 | u64 rx_ppp0; /* # of received PPP prio 0 frames */ | |
159 | u64 rx_ppp1; /* # of received PPP prio 1 frames */ | |
160 | u64 rx_ppp2; /* # of received PPP prio 2 frames */ | |
161 | u64 rx_ppp3; /* # of received PPP prio 3 frames */ | |
162 | u64 rx_ppp4; /* # of received PPP prio 4 frames */ | |
163 | u64 rx_ppp5; /* # of received PPP prio 5 frames */ | |
164 | u64 rx_ppp6; /* # of received PPP prio 6 frames */ | |
165 | u64 rx_ppp7; /* # of received PPP prio 7 frames */ | |
166 | ||
167 | u64 rx_ovflow0; /* drops due to buffer-group 0 overflows */ | |
168 | u64 rx_ovflow1; /* drops due to buffer-group 1 overflows */ | |
169 | u64 rx_ovflow2; /* drops due to buffer-group 2 overflows */ | |
170 | u64 rx_ovflow3; /* drops due to buffer-group 3 overflows */ | |
171 | u64 rx_trunc0; /* buffer-group 0 truncated packets */ | |
172 | u64 rx_trunc1; /* buffer-group 1 truncated packets */ | |
173 | u64 rx_trunc2; /* buffer-group 2 truncated packets */ | |
174 | u64 rx_trunc3; /* buffer-group 3 truncated packets */ | |
175 | }; | |
176 | ||
177 | struct lb_port_stats { | |
178 | u64 octets; | |
179 | u64 frames; | |
180 | u64 bcast_frames; | |
181 | u64 mcast_frames; | |
182 | u64 ucast_frames; | |
183 | u64 error_frames; | |
184 | ||
185 | u64 frames_64; | |
186 | u64 frames_65_127; | |
187 | u64 frames_128_255; | |
188 | u64 frames_256_511; | |
189 | u64 frames_512_1023; | |
190 | u64 frames_1024_1518; | |
191 | u64 frames_1519_max; | |
192 | ||
193 | u64 drop; | |
194 | ||
195 | u64 ovflow0; | |
196 | u64 ovflow1; | |
197 | u64 ovflow2; | |
198 | u64 ovflow3; | |
199 | u64 trunc0; | |
200 | u64 trunc1; | |
201 | u64 trunc2; | |
202 | u64 trunc3; | |
203 | }; | |
204 | ||
205 | struct tp_tcp_stats { | |
206 | u32 tcpOutRsts; | |
207 | u64 tcpInSegs; | |
208 | u64 tcpOutSegs; | |
209 | u64 tcpRetransSegs; | |
210 | }; | |
211 | ||
212 | struct tp_err_stats { | |
213 | u32 macInErrs[4]; | |
214 | u32 hdrInErrs[4]; | |
215 | u32 tcpInErrs[4]; | |
216 | u32 tnlCongDrops[4]; | |
217 | u32 ofldChanDrops[4]; | |
218 | u32 tnlTxDrops[4]; | |
219 | u32 ofldVlanDrops[4]; | |
220 | u32 tcp6InErrs[4]; | |
221 | u32 ofldNoNeigh; | |
222 | u32 ofldCongDefer; | |
223 | }; | |
224 | ||
e85c9a7a HS |
225 | struct sge_params { |
226 | u32 hps; /* host page size for our PF/VF */ | |
227 | u32 eq_qpp; /* egress queues/page for our PF/VF */ | |
228 | u32 iq_qpp; /* egress queues/page for our PF/VF */ | |
229 | }; | |
230 | ||
625ba2c2 DM |
231 | struct tp_params { |
232 | unsigned int ntxchan; /* # of Tx channels */ | |
233 | unsigned int tre; /* log2 of core clocks per TP tick */ | |
dca4faeb VP |
234 | unsigned short tx_modq_map; /* TX modulation scheduler queue to */ |
235 | /* channel map */ | |
636f9d37 VP |
236 | |
237 | uint32_t dack_re; /* DACK timer resolution */ | |
238 | unsigned short tx_modq[NCHAN]; /* channel to modulation queue map */ | |
dcf7b6f5 KS |
239 | |
240 | u32 vlan_pri_map; /* cached TP_VLAN_PRI_MAP */ | |
241 | u32 ingress_config; /* cached TP_INGRESS_CONFIG */ | |
242 | ||
243 | /* TP_VLAN_PRI_MAP Compressed Filter Tuple field offsets. This is a | |
244 | * subset of the set of fields which may be present in the Compressed | |
245 | * Filter Tuple portion of filters and TCP TCB connections. The | |
246 | * fields which are present are controlled by the TP_VLAN_PRI_MAP. | |
247 | * Since a variable number of fields may or may not be present, their | |
248 | * shifted field positions within the Compressed Filter Tuple may | |
249 | * vary, or not even be present if the field isn't selected in | |
250 | * TP_VLAN_PRI_MAP. Since some of these fields are needed in various | |
251 | * places we store their offsets here, or a -1 if the field isn't | |
252 | * present. | |
253 | */ | |
254 | int vlan_shift; | |
255 | int vnic_shift; | |
256 | int port_shift; | |
257 | int protocol_shift; | |
625ba2c2 DM |
258 | }; |
259 | ||
260 | struct vpd_params { | |
261 | unsigned int cclk; | |
262 | u8 ec[EC_LEN + 1]; | |
263 | u8 sn[SERNUM_LEN + 1]; | |
264 | u8 id[ID_LEN + 1]; | |
a94cd705 | 265 | u8 pn[PN_LEN + 1]; |
625ba2c2 DM |
266 | }; |
267 | ||
268 | struct pci_params { | |
269 | unsigned char speed; | |
270 | unsigned char width; | |
271 | }; | |
272 | ||
d14807dd HS |
273 | #define CHELSIO_CHIP_CODE(version, revision) (((version) << 4) | (revision)) |
274 | #define CHELSIO_CHIP_FPGA 0x100 | |
275 | #define CHELSIO_CHIP_VERSION(code) (((code) >> 4) & 0xf) | |
276 | #define CHELSIO_CHIP_RELEASE(code) ((code) & 0xf) | |
277 | ||
278 | #define CHELSIO_T4 0x4 | |
279 | #define CHELSIO_T5 0x5 | |
280 | ||
281 | enum chip_type { | |
282 | T4_A1 = CHELSIO_CHIP_CODE(CHELSIO_T4, 1), | |
283 | T4_A2 = CHELSIO_CHIP_CODE(CHELSIO_T4, 2), | |
284 | T4_FIRST_REV = T4_A1, | |
285 | T4_LAST_REV = T4_A2, | |
286 | ||
287 | T5_A0 = CHELSIO_CHIP_CODE(CHELSIO_T5, 0), | |
288 | T5_A1 = CHELSIO_CHIP_CODE(CHELSIO_T5, 1), | |
289 | T5_FIRST_REV = T5_A0, | |
290 | T5_LAST_REV = T5_A1, | |
291 | }; | |
292 | ||
49aa284f HS |
293 | struct devlog_params { |
294 | u32 memtype; /* which memory (EDC0, EDC1, MC) */ | |
295 | u32 start; /* start of log in firmware memory */ | |
296 | u32 size; /* size of log */ | |
297 | }; | |
298 | ||
625ba2c2 | 299 | struct adapter_params { |
e85c9a7a | 300 | struct sge_params sge; |
625ba2c2 DM |
301 | struct tp_params tp; |
302 | struct vpd_params vpd; | |
303 | struct pci_params pci; | |
49aa284f HS |
304 | struct devlog_params devlog; |
305 | enum pcie_memwin drv_memwin; | |
625ba2c2 | 306 | |
f1ff24aa HS |
307 | unsigned int cim_la_size; |
308 | ||
900a6596 DM |
309 | unsigned int sf_size; /* serial flash size in bytes */ |
310 | unsigned int sf_nsec; /* # of flash sectors */ | |
311 | unsigned int sf_fw_start; /* start of FW image in flash */ | |
312 | ||
625ba2c2 DM |
313 | unsigned int fw_vers; |
314 | unsigned int tp_vers; | |
315 | u8 api_vers[7]; | |
316 | ||
317 | unsigned short mtus[NMTUS]; | |
318 | unsigned short a_wnd[NCCTRL_WIN]; | |
319 | unsigned short b_wnd[NCCTRL_WIN]; | |
320 | ||
321 | unsigned char nports; /* # of ethernet ports */ | |
322 | unsigned char portvec; | |
d14807dd | 323 | enum chip_type chip; /* chip code */ |
625ba2c2 DM |
324 | unsigned char offload; |
325 | ||
9a4da2cd VP |
326 | unsigned char bypass; |
327 | ||
625ba2c2 | 328 | unsigned int ofldq_wr_cred; |
1ac0f095 | 329 | bool ulptx_memwrite_dsgl; /* use of T5 DSGL allowed */ |
4c2c5763 HS |
330 | |
331 | unsigned int max_ordird_qp; /* Max read depth per RDMA QP */ | |
332 | unsigned int max_ird_adapter; /* Max read depth per adapter */ | |
625ba2c2 DM |
333 | }; |
334 | ||
16e47624 HS |
335 | #include "t4fw_api.h" |
336 | ||
337 | #define FW_VERSION(chip) ( \ | |
b2e1a3f0 HS |
338 | FW_HDR_FW_VER_MAJOR_G(chip##FW_VERSION_MAJOR) | \ |
339 | FW_HDR_FW_VER_MINOR_G(chip##FW_VERSION_MINOR) | \ | |
340 | FW_HDR_FW_VER_MICRO_G(chip##FW_VERSION_MICRO) | \ | |
341 | FW_HDR_FW_VER_BUILD_G(chip##FW_VERSION_BUILD)) | |
16e47624 HS |
342 | #define FW_INTFVER(chip, intf) (FW_HDR_INTFVER_##intf) |
343 | ||
344 | struct fw_info { | |
345 | u8 chip; | |
346 | char *fs_name; | |
347 | char *fw_mod_name; | |
348 | struct fw_hdr fw_hdr; | |
349 | }; | |
350 | ||
351 | ||
625ba2c2 DM |
352 | struct trace_params { |
353 | u32 data[TRACE_LEN / 4]; | |
354 | u32 mask[TRACE_LEN / 4]; | |
355 | unsigned short snap_len; | |
356 | unsigned short min_len; | |
357 | unsigned char skip_ofst; | |
358 | unsigned char skip_len; | |
359 | unsigned char invert; | |
360 | unsigned char port; | |
361 | }; | |
362 | ||
363 | struct link_config { | |
364 | unsigned short supported; /* link capabilities */ | |
365 | unsigned short advertising; /* advertised capabilities */ | |
366 | unsigned short requested_speed; /* speed user has requested */ | |
367 | unsigned short speed; /* actual link speed */ | |
368 | unsigned char requested_fc; /* flow control user has requested */ | |
369 | unsigned char fc; /* actual link flow control */ | |
370 | unsigned char autoneg; /* autonegotiating? */ | |
371 | unsigned char link_ok; /* link up? */ | |
372 | }; | |
373 | ||
e2ac9628 | 374 | #define FW_LEN16(fw_struct) FW_CMD_LEN16_V(sizeof(fw_struct) / 16) |
625ba2c2 DM |
375 | |
376 | enum { | |
377 | MAX_ETH_QSETS = 32, /* # of Ethernet Tx/Rx queue sets */ | |
378 | MAX_OFLD_QSETS = 16, /* # of offload Tx/Rx queue sets */ | |
379 | MAX_CTRL_QUEUES = NCHAN, /* # of control Tx queues */ | |
380 | MAX_RDMA_QUEUES = NCHAN, /* # of streaming RDMA Rx queues */ | |
cf38be6d HS |
381 | MAX_RDMA_CIQS = NCHAN, /* # of RDMA concentrator IQs */ |
382 | MAX_ISCSI_QUEUES = NCHAN, /* # of streaming iSCSI Rx queues */ | |
625ba2c2 DM |
383 | }; |
384 | ||
385 | enum { | |
cf38be6d HS |
386 | INGQ_EXTRAS = 2, /* firmware event queue and */ |
387 | /* forwarded interrupts */ | |
388 | MAX_EGRQ = MAX_ETH_QSETS*2 + MAX_OFLD_QSETS*2 | |
389 | + MAX_CTRL_QUEUES + MAX_RDMA_QUEUES + MAX_ISCSI_QUEUES, | |
390 | MAX_INGQ = MAX_ETH_QSETS + MAX_OFLD_QSETS + MAX_RDMA_QUEUES | |
391 | + MAX_RDMA_CIQS + MAX_ISCSI_QUEUES + INGQ_EXTRAS, | |
625ba2c2 DM |
392 | }; |
393 | ||
394 | struct adapter; | |
625ba2c2 DM |
395 | struct sge_rspq; |
396 | ||
688848b1 AB |
397 | #include "cxgb4_dcb.h" |
398 | ||
625ba2c2 DM |
399 | struct port_info { |
400 | struct adapter *adapter; | |
625ba2c2 DM |
401 | u16 viid; |
402 | s16 xact_addr_filt; /* index of exact MAC address filter */ | |
403 | u16 rss_size; /* size of VI's RSS table slice */ | |
404 | s8 mdio_addr; | |
40e9de4b | 405 | enum fw_port_type port_type; |
625ba2c2 DM |
406 | u8 mod_type; |
407 | u8 port_id; | |
408 | u8 tx_chan; | |
409 | u8 lport; /* associated offload logical port */ | |
625ba2c2 DM |
410 | u8 nqsets; /* # of qsets */ |
411 | u8 first_qset; /* index of first qset */ | |
f796564a | 412 | u8 rss_mode; |
625ba2c2 | 413 | struct link_config link_cfg; |
671b0060 | 414 | u16 *rss; |
688848b1 AB |
415 | #ifdef CONFIG_CHELSIO_T4_DCB |
416 | struct port_dcb_info dcb; /* Data Center Bridging support */ | |
417 | #endif | |
625ba2c2 DM |
418 | }; |
419 | ||
625ba2c2 DM |
420 | struct dentry; |
421 | struct work_struct; | |
422 | ||
423 | enum { /* adapter flags */ | |
424 | FULL_INIT_DONE = (1 << 0), | |
144be3d9 GS |
425 | DEV_ENABLED = (1 << 1), |
426 | USING_MSI = (1 << 2), | |
427 | USING_MSIX = (1 << 3), | |
625ba2c2 | 428 | FW_OK = (1 << 4), |
13ee15d3 | 429 | RSS_TNLALLLOOKUP = (1 << 5), |
52367a76 VP |
430 | USING_SOFT_PARAMS = (1 << 6), |
431 | MASTER_PF = (1 << 7), | |
432 | FW_OFLD_CONN = (1 << 9), | |
625ba2c2 DM |
433 | }; |
434 | ||
435 | struct rx_sw_desc; | |
436 | ||
437 | struct sge_fl { /* SGE free-buffer queue state */ | |
438 | unsigned int avail; /* # of available Rx buffers */ | |
439 | unsigned int pend_cred; /* new buffers since last FL DB ring */ | |
440 | unsigned int cidx; /* consumer index */ | |
441 | unsigned int pidx; /* producer index */ | |
442 | unsigned long alloc_failed; /* # of times buffer allocation failed */ | |
443 | unsigned long large_alloc_failed; | |
444 | unsigned long starving; | |
445 | /* RO fields */ | |
446 | unsigned int cntxt_id; /* SGE context id for the free list */ | |
447 | unsigned int size; /* capacity of free list */ | |
448 | struct rx_sw_desc *sdesc; /* address of SW Rx descriptor ring */ | |
449 | __be64 *desc; /* address of HW Rx descriptor ring */ | |
450 | dma_addr_t addr; /* bus address of HW ring start */ | |
df64e4d3 HS |
451 | void __iomem *bar2_addr; /* address of BAR2 Queue registers */ |
452 | unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */ | |
625ba2c2 DM |
453 | }; |
454 | ||
455 | /* A packet gather list */ | |
456 | struct pkt_gl { | |
e91b0f24 | 457 | struct page_frag frags[MAX_SKB_FRAGS]; |
625ba2c2 DM |
458 | void *va; /* virtual address of first byte */ |
459 | unsigned int nfrags; /* # of fragments */ | |
460 | unsigned int tot_len; /* total length of fragments */ | |
461 | }; | |
462 | ||
463 | typedef int (*rspq_handler_t)(struct sge_rspq *q, const __be64 *rsp, | |
464 | const struct pkt_gl *gl); | |
465 | ||
466 | struct sge_rspq { /* state for an SGE response queue */ | |
467 | struct napi_struct napi; | |
468 | const __be64 *cur_desc; /* current descriptor in queue */ | |
469 | unsigned int cidx; /* consumer index */ | |
470 | u8 gen; /* current generation bit */ | |
471 | u8 intr_params; /* interrupt holdoff parameters */ | |
472 | u8 next_intr_params; /* holdoff params for next interrupt */ | |
e553ec3f | 473 | u8 adaptive_rx; |
625ba2c2 DM |
474 | u8 pktcnt_idx; /* interrupt packet threshold */ |
475 | u8 uld; /* ULD handling this queue */ | |
476 | u8 idx; /* queue index within its group */ | |
477 | int offset; /* offset into current Rx buffer */ | |
478 | u16 cntxt_id; /* SGE context id for the response q */ | |
479 | u16 abs_id; /* absolute SGE id for the response q */ | |
480 | __be64 *desc; /* address of HW response ring */ | |
481 | dma_addr_t phys_addr; /* physical address of the ring */ | |
df64e4d3 HS |
482 | void __iomem *bar2_addr; /* address of BAR2 Queue registers */ |
483 | unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */ | |
625ba2c2 DM |
484 | unsigned int iqe_len; /* entry size */ |
485 | unsigned int size; /* capacity of response queue */ | |
486 | struct adapter *adap; | |
487 | struct net_device *netdev; /* associated net device */ | |
488 | rspq_handler_t handler; | |
489 | }; | |
490 | ||
491 | struct sge_eth_stats { /* Ethernet queue statistics */ | |
492 | unsigned long pkts; /* # of ethernet packets */ | |
493 | unsigned long lro_pkts; /* # of LRO super packets */ | |
494 | unsigned long lro_merged; /* # of wire packets merged by LRO */ | |
495 | unsigned long rx_cso; /* # of Rx checksum offloads */ | |
496 | unsigned long vlan_ex; /* # of Rx VLAN extractions */ | |
497 | unsigned long rx_drops; /* # of packets dropped due to no mem */ | |
498 | }; | |
499 | ||
500 | struct sge_eth_rxq { /* SW Ethernet Rx queue */ | |
501 | struct sge_rspq rspq; | |
502 | struct sge_fl fl; | |
503 | struct sge_eth_stats stats; | |
504 | } ____cacheline_aligned_in_smp; | |
505 | ||
506 | struct sge_ofld_stats { /* offload queue statistics */ | |
507 | unsigned long pkts; /* # of packets */ | |
508 | unsigned long imm; /* # of immediate-data packets */ | |
509 | unsigned long an; /* # of asynchronous notifications */ | |
510 | unsigned long nomem; /* # of responses deferred due to no mem */ | |
511 | }; | |
512 | ||
513 | struct sge_ofld_rxq { /* SW offload Rx queue */ | |
514 | struct sge_rspq rspq; | |
515 | struct sge_fl fl; | |
516 | struct sge_ofld_stats stats; | |
517 | } ____cacheline_aligned_in_smp; | |
518 | ||
519 | struct tx_desc { | |
520 | __be64 flit[8]; | |
521 | }; | |
522 | ||
523 | struct tx_sw_desc; | |
524 | ||
525 | struct sge_txq { | |
526 | unsigned int in_use; /* # of in-use Tx descriptors */ | |
527 | unsigned int size; /* # of descriptors */ | |
528 | unsigned int cidx; /* SW consumer index */ | |
529 | unsigned int pidx; /* producer index */ | |
530 | unsigned long stops; /* # of times q has been stopped */ | |
531 | unsigned long restarts; /* # of queue restarts */ | |
532 | unsigned int cntxt_id; /* SGE context id for the Tx q */ | |
533 | struct tx_desc *desc; /* address of HW Tx descriptor ring */ | |
534 | struct tx_sw_desc *sdesc; /* address of SW Tx descriptor ring */ | |
535 | struct sge_qstat *stat; /* queue status entry */ | |
536 | dma_addr_t phys_addr; /* physical address of the ring */ | |
3069ee9b VP |
537 | spinlock_t db_lock; |
538 | int db_disabled; | |
539 | unsigned short db_pidx; | |
05eb2389 | 540 | unsigned short db_pidx_inc; |
df64e4d3 HS |
541 | void __iomem *bar2_addr; /* address of BAR2 Queue registers */ |
542 | unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */ | |
625ba2c2 DM |
543 | }; |
544 | ||
545 | struct sge_eth_txq { /* state for an SGE Ethernet Tx queue */ | |
546 | struct sge_txq q; | |
547 | struct netdev_queue *txq; /* associated netdev TX queue */ | |
10b00466 AB |
548 | #ifdef CONFIG_CHELSIO_T4_DCB |
549 | u8 dcb_prio; /* DCB Priority bound to queue */ | |
550 | #endif | |
625ba2c2 DM |
551 | unsigned long tso; /* # of TSO requests */ |
552 | unsigned long tx_cso; /* # of Tx checksum offloads */ | |
553 | unsigned long vlan_ins; /* # of Tx VLAN insertions */ | |
554 | unsigned long mapping_err; /* # of I/O MMU packet mapping errors */ | |
555 | } ____cacheline_aligned_in_smp; | |
556 | ||
557 | struct sge_ofld_txq { /* state for an SGE offload Tx queue */ | |
558 | struct sge_txq q; | |
559 | struct adapter *adap; | |
560 | struct sk_buff_head sendq; /* list of backpressured packets */ | |
561 | struct tasklet_struct qresume_tsk; /* restarts the queue */ | |
562 | u8 full; /* the Tx ring is full */ | |
563 | unsigned long mapping_err; /* # of I/O MMU packet mapping errors */ | |
564 | } ____cacheline_aligned_in_smp; | |
565 | ||
566 | struct sge_ctrl_txq { /* state for an SGE control Tx queue */ | |
567 | struct sge_txq q; | |
568 | struct adapter *adap; | |
569 | struct sk_buff_head sendq; /* list of backpressured packets */ | |
570 | struct tasklet_struct qresume_tsk; /* restarts the queue */ | |
571 | u8 full; /* the Tx ring is full */ | |
572 | } ____cacheline_aligned_in_smp; | |
573 | ||
574 | struct sge { | |
575 | struct sge_eth_txq ethtxq[MAX_ETH_QSETS]; | |
576 | struct sge_ofld_txq ofldtxq[MAX_OFLD_QSETS]; | |
577 | struct sge_ctrl_txq ctrlq[MAX_CTRL_QUEUES]; | |
578 | ||
579 | struct sge_eth_rxq ethrxq[MAX_ETH_QSETS]; | |
580 | struct sge_ofld_rxq ofldrxq[MAX_OFLD_QSETS]; | |
581 | struct sge_ofld_rxq rdmarxq[MAX_RDMA_QUEUES]; | |
cf38be6d | 582 | struct sge_ofld_rxq rdmaciq[MAX_RDMA_CIQS]; |
625ba2c2 DM |
583 | struct sge_rspq fw_evtq ____cacheline_aligned_in_smp; |
584 | ||
585 | struct sge_rspq intrq ____cacheline_aligned_in_smp; | |
586 | spinlock_t intrq_lock; | |
587 | ||
588 | u16 max_ethqsets; /* # of available Ethernet queue sets */ | |
589 | u16 ethqsets; /* # of active Ethernet queue sets */ | |
590 | u16 ethtxq_rover; /* Tx queue to clean up next */ | |
591 | u16 ofldqsets; /* # of active offload queue sets */ | |
592 | u16 rdmaqs; /* # of available RDMA Rx queues */ | |
cf38be6d | 593 | u16 rdmaciqs; /* # of available RDMA concentrator IQs */ |
625ba2c2 DM |
594 | u16 ofld_rxq[MAX_OFLD_QSETS]; |
595 | u16 rdma_rxq[NCHAN]; | |
cf38be6d | 596 | u16 rdma_ciq[NCHAN]; |
625ba2c2 DM |
597 | u16 timer_val[SGE_NTIMERS]; |
598 | u8 counter_val[SGE_NCOUNTERS]; | |
52367a76 VP |
599 | u32 fl_pg_order; /* large page allocation size */ |
600 | u32 stat_len; /* length of status page at ring end */ | |
601 | u32 pktshift; /* padding between CPL & packet data */ | |
602 | u32 fl_align; /* response queue message alignment */ | |
603 | u32 fl_starve_thres; /* Free List starvation threshold */ | |
0f4d201f KS |
604 | |
605 | /* State variables for detecting an SGE Ingress DMA hang */ | |
606 | unsigned int idma_1s_thresh;/* SGE same State Counter 1s threshold */ | |
607 | unsigned int idma_stalled[2];/* SGE synthesized stalled timers in HZ */ | |
608 | unsigned int idma_state[2]; /* SGE IDMA Hang detect state */ | |
609 | unsigned int idma_qid[2]; /* SGE IDMA Hung Ingress Queue ID */ | |
610 | ||
e46dab4d DM |
611 | unsigned int egr_start; |
612 | unsigned int ingr_start; | |
625ba2c2 DM |
613 | void *egr_map[MAX_EGRQ]; /* qid->queue egress queue map */ |
614 | struct sge_rspq *ingr_map[MAX_INGQ]; /* qid->queue ingress queue map */ | |
615 | DECLARE_BITMAP(starving_fl, MAX_EGRQ); | |
616 | DECLARE_BITMAP(txq_maperr, MAX_EGRQ); | |
617 | struct timer_list rx_timer; /* refills starving FLs */ | |
618 | struct timer_list tx_timer; /* checks Tx queues */ | |
619 | }; | |
620 | ||
621 | #define for_each_ethrxq(sge, i) for (i = 0; i < (sge)->ethqsets; i++) | |
622 | #define for_each_ofldrxq(sge, i) for (i = 0; i < (sge)->ofldqsets; i++) | |
623 | #define for_each_rdmarxq(sge, i) for (i = 0; i < (sge)->rdmaqs; i++) | |
cf38be6d | 624 | #define for_each_rdmaciq(sge, i) for (i = 0; i < (sge)->rdmaciqs; i++) |
625ba2c2 DM |
625 | |
626 | struct l2t_data; | |
627 | ||
2422d9a3 SR |
628 | #ifdef CONFIG_PCI_IOV |
629 | ||
7d6727cf SR |
630 | /* T4 supports SRIOV on PF0-3 and T5 on PF0-7. However, the Serial |
631 | * Configuration initialization for T5 only has SR-IOV functionality enabled | |
632 | * on PF0-3 in order to simplify everything. | |
2422d9a3 | 633 | */ |
7d6727cf | 634 | #define NUM_OF_PF_WITH_SRIOV 4 |
2422d9a3 SR |
635 | |
636 | #endif | |
637 | ||
625ba2c2 DM |
638 | struct adapter { |
639 | void __iomem *regs; | |
22adfe0a | 640 | void __iomem *bar2; |
0abfd152 | 641 | u32 t4_bar0; |
625ba2c2 DM |
642 | struct pci_dev *pdev; |
643 | struct device *pdev_dev; | |
3069ee9b | 644 | unsigned int mbox; |
060e0c75 DM |
645 | unsigned int fn; |
646 | unsigned int flags; | |
2422d9a3 | 647 | enum chip_type chip; |
625ba2c2 | 648 | |
625ba2c2 DM |
649 | int msg_enable; |
650 | ||
651 | struct adapter_params params; | |
652 | struct cxgb4_virt_res vres; | |
653 | unsigned int swintr; | |
654 | ||
655 | unsigned int wol; | |
656 | ||
657 | struct { | |
658 | unsigned short vec; | |
8cd18ac4 | 659 | char desc[IFNAMSIZ + 10]; |
625ba2c2 DM |
660 | } msix_info[MAX_INGQ + 1]; |
661 | ||
662 | struct sge sge; | |
663 | ||
664 | struct net_device *port[MAX_NPORTS]; | |
665 | u8 chan_map[NCHAN]; /* channel -> port map */ | |
666 | ||
793dad94 | 667 | u32 filter_mode; |
636f9d37 VP |
668 | unsigned int l2t_start; |
669 | unsigned int l2t_end; | |
625ba2c2 | 670 | struct l2t_data *l2t; |
b5a02f50 AB |
671 | unsigned int clipt_start; |
672 | unsigned int clipt_end; | |
673 | struct clip_tbl *clipt; | |
625ba2c2 DM |
674 | void *uld_handle[CXGB4_ULD_MAX]; |
675 | struct list_head list_node; | |
01bcca68 | 676 | struct list_head rcu_node; |
625ba2c2 DM |
677 | |
678 | struct tid_info tids; | |
679 | void **tid_release_head; | |
680 | spinlock_t tid_release_lock; | |
29aaee65 | 681 | struct workqueue_struct *workq; |
625ba2c2 | 682 | struct work_struct tid_release_task; |
881806bc VP |
683 | struct work_struct db_full_task; |
684 | struct work_struct db_drop_task; | |
625ba2c2 DM |
685 | bool tid_release_task_busy; |
686 | ||
687 | struct dentry *debugfs_root; | |
688 | ||
689 | spinlock_t stats_lock; | |
fc5ab020 | 690 | spinlock_t win0_lock ____cacheline_aligned_in_smp; |
625ba2c2 DM |
691 | }; |
692 | ||
f2b7e78d VP |
693 | /* Defined bit width of user definable filter tuples |
694 | */ | |
695 | #define ETHTYPE_BITWIDTH 16 | |
696 | #define FRAG_BITWIDTH 1 | |
697 | #define MACIDX_BITWIDTH 9 | |
698 | #define FCOE_BITWIDTH 1 | |
699 | #define IPORT_BITWIDTH 3 | |
700 | #define MATCHTYPE_BITWIDTH 3 | |
701 | #define PROTO_BITWIDTH 8 | |
702 | #define TOS_BITWIDTH 8 | |
703 | #define PF_BITWIDTH 8 | |
704 | #define VF_BITWIDTH 8 | |
705 | #define IVLAN_BITWIDTH 16 | |
706 | #define OVLAN_BITWIDTH 16 | |
707 | ||
708 | /* Filter matching rules. These consist of a set of ingress packet field | |
709 | * (value, mask) tuples. The associated ingress packet field matches the | |
710 | * tuple when ((field & mask) == value). (Thus a wildcard "don't care" field | |
711 | * rule can be constructed by specifying a tuple of (0, 0).) A filter rule | |
712 | * matches an ingress packet when all of the individual individual field | |
713 | * matching rules are true. | |
714 | * | |
715 | * Partial field masks are always valid, however, while it may be easy to | |
716 | * understand their meanings for some fields (e.g. IP address to match a | |
717 | * subnet), for others making sensible partial masks is less intuitive (e.g. | |
718 | * MPS match type) ... | |
719 | * | |
720 | * Most of the following data structures are modeled on T4 capabilities. | |
721 | * Drivers for earlier chips use the subsets which make sense for those chips. | |
722 | * We really need to come up with a hardware-independent mechanism to | |
723 | * represent hardware filter capabilities ... | |
724 | */ | |
725 | struct ch_filter_tuple { | |
726 | /* Compressed header matching field rules. The TP_VLAN_PRI_MAP | |
727 | * register selects which of these fields will participate in the | |
728 | * filter match rules -- up to a maximum of 36 bits. Because | |
729 | * TP_VLAN_PRI_MAP is a global register, all filters must use the same | |
730 | * set of fields. | |
731 | */ | |
732 | uint32_t ethtype:ETHTYPE_BITWIDTH; /* Ethernet type */ | |
733 | uint32_t frag:FRAG_BITWIDTH; /* IP fragmentation header */ | |
734 | uint32_t ivlan_vld:1; /* inner VLAN valid */ | |
735 | uint32_t ovlan_vld:1; /* outer VLAN valid */ | |
736 | uint32_t pfvf_vld:1; /* PF/VF valid */ | |
737 | uint32_t macidx:MACIDX_BITWIDTH; /* exact match MAC index */ | |
738 | uint32_t fcoe:FCOE_BITWIDTH; /* FCoE packet */ | |
739 | uint32_t iport:IPORT_BITWIDTH; /* ingress port */ | |
740 | uint32_t matchtype:MATCHTYPE_BITWIDTH; /* MPS match type */ | |
741 | uint32_t proto:PROTO_BITWIDTH; /* protocol type */ | |
742 | uint32_t tos:TOS_BITWIDTH; /* TOS/Traffic Type */ | |
743 | uint32_t pf:PF_BITWIDTH; /* PCI-E PF ID */ | |
744 | uint32_t vf:VF_BITWIDTH; /* PCI-E VF ID */ | |
745 | uint32_t ivlan:IVLAN_BITWIDTH; /* inner VLAN */ | |
746 | uint32_t ovlan:OVLAN_BITWIDTH; /* outer VLAN */ | |
747 | ||
748 | /* Uncompressed header matching field rules. These are always | |
749 | * available for field rules. | |
750 | */ | |
751 | uint8_t lip[16]; /* local IP address (IPv4 in [3:0]) */ | |
752 | uint8_t fip[16]; /* foreign IP address (IPv4 in [3:0]) */ | |
753 | uint16_t lport; /* local port */ | |
754 | uint16_t fport; /* foreign port */ | |
755 | }; | |
756 | ||
757 | /* A filter ioctl command. | |
758 | */ | |
759 | struct ch_filter_specification { | |
760 | /* Administrative fields for filter. | |
761 | */ | |
762 | uint32_t hitcnts:1; /* count filter hits in TCB */ | |
763 | uint32_t prio:1; /* filter has priority over active/server */ | |
764 | ||
765 | /* Fundamental filter typing. This is the one element of filter | |
766 | * matching that doesn't exist as a (value, mask) tuple. | |
767 | */ | |
768 | uint32_t type:1; /* 0 => IPv4, 1 => IPv6 */ | |
769 | ||
770 | /* Packet dispatch information. Ingress packets which match the | |
771 | * filter rules will be dropped, passed to the host or switched back | |
772 | * out as egress packets. | |
773 | */ | |
774 | uint32_t action:2; /* drop, pass, switch */ | |
775 | ||
776 | uint32_t rpttid:1; /* report TID in RSS hash field */ | |
777 | ||
778 | uint32_t dirsteer:1; /* 0 => RSS, 1 => steer to iq */ | |
779 | uint32_t iq:10; /* ingress queue */ | |
780 | ||
781 | uint32_t maskhash:1; /* dirsteer=0: store RSS hash in TCB */ | |
782 | uint32_t dirsteerhash:1;/* dirsteer=1: 0 => TCB contains RSS hash */ | |
783 | /* 1 => TCB contains IQ ID */ | |
784 | ||
785 | /* Switch proxy/rewrite fields. An ingress packet which matches a | |
786 | * filter with "switch" set will be looped back out as an egress | |
787 | * packet -- potentially with some Ethernet header rewriting. | |
788 | */ | |
789 | uint32_t eport:2; /* egress port to switch packet out */ | |
790 | uint32_t newdmac:1; /* rewrite destination MAC address */ | |
791 | uint32_t newsmac:1; /* rewrite source MAC address */ | |
792 | uint32_t newvlan:2; /* rewrite VLAN Tag */ | |
793 | uint8_t dmac[ETH_ALEN]; /* new destination MAC address */ | |
794 | uint8_t smac[ETH_ALEN]; /* new source MAC address */ | |
795 | uint16_t vlan; /* VLAN Tag to insert */ | |
796 | ||
797 | /* Filter rule value/mask pairs. | |
798 | */ | |
799 | struct ch_filter_tuple val; | |
800 | struct ch_filter_tuple mask; | |
801 | }; | |
802 | ||
803 | enum { | |
804 | FILTER_PASS = 0, /* default */ | |
805 | FILTER_DROP, | |
806 | FILTER_SWITCH | |
807 | }; | |
808 | ||
809 | enum { | |
810 | VLAN_NOCHANGE = 0, /* default */ | |
811 | VLAN_REMOVE, | |
812 | VLAN_INSERT, | |
813 | VLAN_REWRITE | |
814 | }; | |
815 | ||
2422d9a3 SR |
816 | static inline int is_t5(enum chip_type chip) |
817 | { | |
d14807dd | 818 | return CHELSIO_CHIP_VERSION(chip) == CHELSIO_T5; |
2422d9a3 SR |
819 | } |
820 | ||
821 | static inline int is_t4(enum chip_type chip) | |
822 | { | |
d14807dd | 823 | return CHELSIO_CHIP_VERSION(chip) == CHELSIO_T4; |
2422d9a3 SR |
824 | } |
825 | ||
625ba2c2 DM |
826 | static inline u32 t4_read_reg(struct adapter *adap, u32 reg_addr) |
827 | { | |
828 | return readl(adap->regs + reg_addr); | |
829 | } | |
830 | ||
831 | static inline void t4_write_reg(struct adapter *adap, u32 reg_addr, u32 val) | |
832 | { | |
833 | writel(val, adap->regs + reg_addr); | |
834 | } | |
835 | ||
836 | #ifndef readq | |
837 | static inline u64 readq(const volatile void __iomem *addr) | |
838 | { | |
839 | return readl(addr) + ((u64)readl(addr + 4) << 32); | |
840 | } | |
841 | ||
842 | static inline void writeq(u64 val, volatile void __iomem *addr) | |
843 | { | |
844 | writel(val, addr); | |
845 | writel(val >> 32, addr + 4); | |
846 | } | |
847 | #endif | |
848 | ||
849 | static inline u64 t4_read_reg64(struct adapter *adap, u32 reg_addr) | |
850 | { | |
851 | return readq(adap->regs + reg_addr); | |
852 | } | |
853 | ||
854 | static inline void t4_write_reg64(struct adapter *adap, u32 reg_addr, u64 val) | |
855 | { | |
856 | writeq(val, adap->regs + reg_addr); | |
857 | } | |
858 | ||
859 | /** | |
860 | * netdev2pinfo - return the port_info structure associated with a net_device | |
861 | * @dev: the netdev | |
862 | * | |
863 | * Return the struct port_info associated with a net_device | |
864 | */ | |
865 | static inline struct port_info *netdev2pinfo(const struct net_device *dev) | |
866 | { | |
867 | return netdev_priv(dev); | |
868 | } | |
869 | ||
870 | /** | |
871 | * adap2pinfo - return the port_info of a port | |
872 | * @adap: the adapter | |
873 | * @idx: the port index | |
874 | * | |
875 | * Return the port_info structure for the port of the given index. | |
876 | */ | |
877 | static inline struct port_info *adap2pinfo(struct adapter *adap, int idx) | |
878 | { | |
879 | return netdev_priv(adap->port[idx]); | |
880 | } | |
881 | ||
882 | /** | |
883 | * netdev2adap - return the adapter structure associated with a net_device | |
884 | * @dev: the netdev | |
885 | * | |
886 | * Return the struct adapter associated with a net_device | |
887 | */ | |
888 | static inline struct adapter *netdev2adap(const struct net_device *dev) | |
889 | { | |
890 | return netdev2pinfo(dev)->adapter; | |
891 | } | |
892 | ||
893 | void t4_os_portmod_changed(const struct adapter *adap, int port_id); | |
894 | void t4_os_link_changed(struct adapter *adap, int port_id, int link_stat); | |
895 | ||
896 | void *t4_alloc_mem(size_t size); | |
625ba2c2 DM |
897 | |
898 | void t4_free_sge_resources(struct adapter *adap); | |
5fa76694 | 899 | void t4_free_ofld_rxqs(struct adapter *adap, int n, struct sge_ofld_rxq *q); |
625ba2c2 DM |
900 | irq_handler_t t4_intr_handler(struct adapter *adap); |
901 | netdev_tx_t t4_eth_xmit(struct sk_buff *skb, struct net_device *dev); | |
902 | int t4_ethrx_handler(struct sge_rspq *q, const __be64 *rsp, | |
903 | const struct pkt_gl *gl); | |
904 | int t4_mgmt_tx(struct adapter *adap, struct sk_buff *skb); | |
905 | int t4_ofld_send(struct adapter *adap, struct sk_buff *skb); | |
906 | int t4_sge_alloc_rxq(struct adapter *adap, struct sge_rspq *iq, bool fwevtq, | |
907 | struct net_device *dev, int intr_idx, | |
908 | struct sge_fl *fl, rspq_handler_t hnd); | |
909 | int t4_sge_alloc_eth_txq(struct adapter *adap, struct sge_eth_txq *txq, | |
910 | struct net_device *dev, struct netdev_queue *netdevq, | |
911 | unsigned int iqid); | |
912 | int t4_sge_alloc_ctrl_txq(struct adapter *adap, struct sge_ctrl_txq *txq, | |
913 | struct net_device *dev, unsigned int iqid, | |
914 | unsigned int cmplqid); | |
915 | int t4_sge_alloc_ofld_txq(struct adapter *adap, struct sge_ofld_txq *txq, | |
916 | struct net_device *dev, unsigned int iqid); | |
917 | irqreturn_t t4_sge_intr_msix(int irq, void *cookie); | |
52367a76 | 918 | int t4_sge_init(struct adapter *adap); |
625ba2c2 DM |
919 | void t4_sge_start(struct adapter *adap); |
920 | void t4_sge_stop(struct adapter *adap); | |
3069ee9b | 921 | extern int dbfifo_int_thresh; |
625ba2c2 DM |
922 | |
923 | #define for_each_port(adapter, iter) \ | |
924 | for (iter = 0; iter < (adapter)->params.nports; ++iter) | |
925 | ||
9a4da2cd VP |
926 | static inline int is_bypass(struct adapter *adap) |
927 | { | |
928 | return adap->params.bypass; | |
929 | } | |
930 | ||
931 | static inline int is_bypass_device(int device) | |
932 | { | |
933 | /* this should be set based upon device capabilities */ | |
934 | switch (device) { | |
935 | case 0x440b: | |
936 | case 0x440c: | |
937 | return 1; | |
938 | default: | |
939 | return 0; | |
940 | } | |
941 | } | |
942 | ||
625ba2c2 DM |
943 | static inline unsigned int core_ticks_per_usec(const struct adapter *adap) |
944 | { | |
945 | return adap->params.vpd.cclk / 1000; | |
946 | } | |
947 | ||
948 | static inline unsigned int us_to_core_ticks(const struct adapter *adap, | |
949 | unsigned int us) | |
950 | { | |
951 | return (us * adap->params.vpd.cclk) / 1000; | |
952 | } | |
953 | ||
52367a76 VP |
954 | static inline unsigned int core_ticks_to_us(const struct adapter *adapter, |
955 | unsigned int ticks) | |
956 | { | |
957 | /* add Core Clock / 2 to round ticks to nearest uS */ | |
958 | return ((ticks * 1000 + adapter->params.vpd.cclk/2) / | |
959 | adapter->params.vpd.cclk); | |
960 | } | |
961 | ||
625ba2c2 DM |
962 | void t4_set_reg_field(struct adapter *adap, unsigned int addr, u32 mask, |
963 | u32 val); | |
964 | ||
965 | int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size, | |
966 | void *rpl, bool sleep_ok); | |
967 | ||
968 | static inline int t4_wr_mbox(struct adapter *adap, int mbox, const void *cmd, | |
969 | int size, void *rpl) | |
970 | { | |
971 | return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, true); | |
972 | } | |
973 | ||
974 | static inline int t4_wr_mbox_ns(struct adapter *adap, int mbox, const void *cmd, | |
975 | int size, void *rpl) | |
976 | { | |
977 | return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, false); | |
978 | } | |
979 | ||
13ee15d3 VP |
980 | void t4_write_indirect(struct adapter *adap, unsigned int addr_reg, |
981 | unsigned int data_reg, const u32 *vals, | |
982 | unsigned int nregs, unsigned int start_idx); | |
f2b7e78d VP |
983 | void t4_read_indirect(struct adapter *adap, unsigned int addr_reg, |
984 | unsigned int data_reg, u32 *vals, unsigned int nregs, | |
985 | unsigned int start_idx); | |
0abfd152 | 986 | void t4_hw_pci_read_cfg4(struct adapter *adapter, int reg, u32 *val); |
f2b7e78d VP |
987 | |
988 | struct fw_filter_wr; | |
989 | ||
625ba2c2 DM |
990 | void t4_intr_enable(struct adapter *adapter); |
991 | void t4_intr_disable(struct adapter *adapter); | |
625ba2c2 DM |
992 | int t4_slow_intr_handler(struct adapter *adapter); |
993 | ||
8203b509 | 994 | int t4_wait_dev_ready(void __iomem *regs); |
625ba2c2 DM |
995 | int t4_link_start(struct adapter *adap, unsigned int mbox, unsigned int port, |
996 | struct link_config *lc); | |
997 | int t4_restart_aneg(struct adapter *adap, unsigned int mbox, unsigned int port); | |
fc5ab020 HS |
998 | |
999 | #define T4_MEMORY_WRITE 0 | |
1000 | #define T4_MEMORY_READ 1 | |
1001 | int t4_memory_rw(struct adapter *adap, int win, int mtype, u32 addr, u32 len, | |
1002 | __be32 *buf, int dir); | |
1003 | static inline int t4_memory_write(struct adapter *adap, int mtype, u32 addr, | |
1004 | u32 len, __be32 *buf) | |
1005 | { | |
1006 | return t4_memory_rw(adap, 0, mtype, addr, len, buf, 0); | |
1007 | } | |
1008 | ||
625ba2c2 | 1009 | int t4_seeprom_wp(struct adapter *adapter, bool enable); |
636f9d37 | 1010 | int get_vpd_params(struct adapter *adapter, struct vpd_params *p); |
49216c1c HS |
1011 | int t4_read_flash(struct adapter *adapter, unsigned int addr, |
1012 | unsigned int nwords, u32 *data, int byte_oriented); | |
625ba2c2 | 1013 | int t4_load_fw(struct adapter *adapter, const u8 *fw_data, unsigned int size); |
49216c1c | 1014 | int t4_fwcache(struct adapter *adap, enum fw_params_param_dev_fwcache op); |
22c0b963 HS |
1015 | int t4_fw_upgrade(struct adapter *adap, unsigned int mbox, |
1016 | const u8 *fw_data, unsigned int size, int force); | |
636f9d37 | 1017 | unsigned int t4_flash_cfg_addr(struct adapter *adapter); |
16e47624 HS |
1018 | int t4_get_fw_version(struct adapter *adapter, u32 *vers); |
1019 | int t4_get_tp_version(struct adapter *adapter, u32 *vers); | |
1020 | int t4_prep_fw(struct adapter *adap, struct fw_info *fw_info, | |
1021 | const u8 *fw_data, unsigned int fw_size, | |
1022 | struct fw_hdr *card_fw, enum dev_state state, int *reset); | |
625ba2c2 | 1023 | int t4_prep_adapter(struct adapter *adapter); |
e85c9a7a HS |
1024 | |
1025 | enum t4_bar2_qtype { T4_BAR2_QTYPE_EGRESS, T4_BAR2_QTYPE_INGRESS }; | |
dd0bcc0b | 1026 | int cxgb4_t4_bar2_sge_qregs(struct adapter *adapter, |
e85c9a7a HS |
1027 | unsigned int qid, |
1028 | enum t4_bar2_qtype qtype, | |
1029 | u64 *pbar2_qoffset, | |
1030 | unsigned int *pbar2_qid); | |
1031 | ||
dc9daab2 HS |
1032 | unsigned int qtimer_val(const struct adapter *adap, |
1033 | const struct sge_rspq *q); | |
e85c9a7a | 1034 | int t4_init_sge_params(struct adapter *adapter); |
dcf7b6f5 KS |
1035 | int t4_init_tp_params(struct adapter *adap); |
1036 | int t4_filter_field_shift(const struct adapter *adap, int filter_sel); | |
625ba2c2 DM |
1037 | int t4_port_init(struct adapter *adap, int mbox, int pf, int vf); |
1038 | void t4_fatal_err(struct adapter *adapter); | |
625ba2c2 DM |
1039 | int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid, |
1040 | int start, int n, const u16 *rspq, unsigned int nrspq); | |
1041 | int t4_config_glbl_rss(struct adapter *adapter, int mbox, unsigned int mode, | |
1042 | unsigned int flags); | |
688ea5fe HS |
1043 | int t4_read_rss(struct adapter *adapter, u16 *entries); |
1044 | void t4_read_rss_key(struct adapter *adapter, u32 *key); | |
1045 | void t4_write_rss_key(struct adapter *adap, const u32 *key, int idx); | |
1046 | void t4_read_rss_pf_config(struct adapter *adapter, unsigned int index, | |
1047 | u32 *valp); | |
1048 | void t4_read_rss_vf_config(struct adapter *adapter, unsigned int index, | |
1049 | u32 *vfl, u32 *vfh); | |
1050 | u32 t4_read_rss_pf_map(struct adapter *adapter); | |
1051 | u32 t4_read_rss_pf_mask(struct adapter *adapter); | |
1052 | ||
19dd37ba SR |
1053 | int t4_mc_read(struct adapter *adap, int idx, u32 addr, __be32 *data, |
1054 | u64 *parity); | |
625ba2c2 DM |
1055 | int t4_edc_read(struct adapter *adap, int idx, u32 addr, __be32 *data, |
1056 | u64 *parity); | |
e5f0e43b HS |
1057 | int t4_read_cim_ibq(struct adapter *adap, unsigned int qid, u32 *data, |
1058 | size_t n); | |
c778af7d HS |
1059 | int t4_read_cim_obq(struct adapter *adap, unsigned int qid, u32 *data, |
1060 | size_t n); | |
f1ff24aa HS |
1061 | int t4_cim_read(struct adapter *adap, unsigned int addr, unsigned int n, |
1062 | unsigned int *valp); | |
1063 | int t4_cim_write(struct adapter *adap, unsigned int addr, unsigned int n, | |
1064 | const unsigned int *valp); | |
1065 | int t4_cim_read_la(struct adapter *adap, u32 *la_buf, unsigned int *wrptr); | |
74b3092c | 1066 | void t4_read_cimq_cfg(struct adapter *adap, u16 *base, u16 *size, u16 *thres); |
72aca4bf | 1067 | const char *t4_get_port_type_description(enum fw_port_type port_type); |
625ba2c2 | 1068 | void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p); |
625ba2c2 | 1069 | void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log); |
636f9d37 VP |
1070 | void t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr, |
1071 | unsigned int mask, unsigned int val); | |
625ba2c2 DM |
1072 | void t4_tp_get_tcp_stats(struct adapter *adap, struct tp_tcp_stats *v4, |
1073 | struct tp_tcp_stats *v6); | |
1074 | void t4_load_mtus(struct adapter *adap, const unsigned short *mtus, | |
1075 | const unsigned short *alpha, const unsigned short *beta); | |
1076 | ||
f2b7e78d VP |
1077 | void t4_mk_filtdelwr(unsigned int ftid, struct fw_filter_wr *wr, int qid); |
1078 | ||
625ba2c2 DM |
1079 | void t4_wol_magic_enable(struct adapter *adap, unsigned int port, |
1080 | const u8 *addr); | |
1081 | int t4_wol_pat_enable(struct adapter *adap, unsigned int port, unsigned int map, | |
1082 | u64 mask0, u64 mask1, unsigned int crc, bool enable); | |
1083 | ||
1084 | int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox, | |
1085 | enum dev_master master, enum dev_state *state); | |
1086 | int t4_fw_bye(struct adapter *adap, unsigned int mbox); | |
1087 | int t4_early_init(struct adapter *adap, unsigned int mbox); | |
1088 | int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset); | |
636f9d37 VP |
1089 | int t4_fixup_host_params(struct adapter *adap, unsigned int page_size, |
1090 | unsigned int cache_line_size); | |
1091 | int t4_fw_initialize(struct adapter *adap, unsigned int mbox); | |
625ba2c2 DM |
1092 | int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf, |
1093 | unsigned int vf, unsigned int nparams, const u32 *params, | |
1094 | u32 *val); | |
1095 | int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf, | |
1096 | unsigned int vf, unsigned int nparams, const u32 *params, | |
1097 | const u32 *val); | |
688848b1 AB |
1098 | int t4_set_params_nosleep(struct adapter *adap, unsigned int mbox, |
1099 | unsigned int pf, unsigned int vf, | |
1100 | unsigned int nparams, const u32 *params, | |
1101 | const u32 *val); | |
625ba2c2 DM |
1102 | int t4_cfg_pfvf(struct adapter *adap, unsigned int mbox, unsigned int pf, |
1103 | unsigned int vf, unsigned int txq, unsigned int txq_eth_ctrl, | |
1104 | unsigned int rxqi, unsigned int rxq, unsigned int tc, | |
1105 | unsigned int vi, unsigned int cmask, unsigned int pmask, | |
1106 | unsigned int nexact, unsigned int rcaps, unsigned int wxcaps); | |
1107 | int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port, | |
1108 | unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac, | |
1109 | unsigned int *rss_size); | |
625ba2c2 | 1110 | int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid, |
f8f5aafa DM |
1111 | int mtu, int promisc, int all_multi, int bcast, int vlanex, |
1112 | bool sleep_ok); | |
625ba2c2 DM |
1113 | int t4_alloc_mac_filt(struct adapter *adap, unsigned int mbox, |
1114 | unsigned int viid, bool free, unsigned int naddr, | |
1115 | const u8 **addr, u16 *idx, u64 *hash, bool sleep_ok); | |
1116 | int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid, | |
1117 | int idx, const u8 *addr, bool persist, bool add_smt); | |
1118 | int t4_set_addr_hash(struct adapter *adap, unsigned int mbox, unsigned int viid, | |
1119 | bool ucast, u64 vec, bool sleep_ok); | |
688848b1 AB |
1120 | int t4_enable_vi_params(struct adapter *adap, unsigned int mbox, |
1121 | unsigned int viid, bool rx_en, bool tx_en, bool dcb_en); | |
625ba2c2 DM |
1122 | int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid, |
1123 | bool rx_en, bool tx_en); | |
1124 | int t4_identify_port(struct adapter *adap, unsigned int mbox, unsigned int viid, | |
1125 | unsigned int nblinks); | |
1126 | int t4_mdio_rd(struct adapter *adap, unsigned int mbox, unsigned int phy_addr, | |
1127 | unsigned int mmd, unsigned int reg, u16 *valp); | |
1128 | int t4_mdio_wr(struct adapter *adap, unsigned int mbox, unsigned int phy_addr, | |
1129 | unsigned int mmd, unsigned int reg, u16 val); | |
625ba2c2 DM |
1130 | int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, |
1131 | unsigned int vf, unsigned int iqtype, unsigned int iqid, | |
1132 | unsigned int fl0id, unsigned int fl1id); | |
1133 | int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, | |
1134 | unsigned int vf, unsigned int eqid); | |
1135 | int t4_ctrl_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, | |
1136 | unsigned int vf, unsigned int eqid); | |
1137 | int t4_ofld_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, | |
1138 | unsigned int vf, unsigned int eqid); | |
1139 | int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl); | |
881806bc VP |
1140 | void t4_db_full(struct adapter *adapter); |
1141 | void t4_db_dropped(struct adapter *adapter); | |
8caa1e84 VP |
1142 | int t4_fwaddrspace_write(struct adapter *adap, unsigned int mbox, |
1143 | u32 addr, u32 val); | |
68bce192 | 1144 | void t4_sge_decode_idma_state(struct adapter *adapter, int state); |
fd88b31a | 1145 | void t4_free_mem(void *addr); |
625ba2c2 | 1146 | #endif /* __CXGB4_H__ */ |