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Merge tag 'batman-adv-for-davem' of git://git.open-mesh.org/linux-merge
[deliverable/linux.git] / drivers / net / ethernet / chelsio / cxgb4 / cxgb4.h
CommitLineData
625ba2c2
DM		 1/*
2 * This file is part of the Chelsio T4 Ethernet driver for Linux.
3 *
ce100b8b 4 * Copyright (c) 2003-2014 Chelsio Communications, Inc. All rights reserved.
625ba2c2
DM		 5 *
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
11 *
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
14 * conditions are met:
15 *
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
18 * disclaimer.
19 *
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
24 *
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
32 * SOFTWARE.
33 */
34
35#ifndef __CXGB4_H__
36#define __CXGB4_H__
37
dca4faeb
VP		 38#include "t4_hw.h"
39
625ba2c2
DM		 40#include <linux/bitops.h>
41#include <linux/cache.h>
42#include <linux/interrupt.h>
43#include <linux/list.h>
44#include <linux/netdevice.h>
45#include <linux/pci.h>
46#include <linux/spinlock.h>
47#include <linux/timer.h>
c0b8b992 48#include <linux/vmalloc.h>
625ba2c2
DM		 49#include <asm/io.h>
50#include "cxgb4_uld.h"
625ba2c2 51
3069ee9b
VP		 52#define CH_WARN(adap, fmt, ...) dev_warn(adap->pdev_dev, fmt, ## __VA_ARGS__)
53
625ba2c2
DM		 54enum {
55 MAX_NPORTS = 4, /* max # of ports */
47d54d65 56 SERNUM_LEN = 24, /* Serial # length */
625ba2c2
DM		 57 EC_LEN = 16, /* E/C length */
58 ID_LEN = 16, /* ID length */
a94cd705 59 PN_LEN = 16, /* Part Number length */
625ba2c2
DM		 60};
61
812034f1
HS		 62enum {
63 T4_REGMAP_SIZE = (160 * 1024),
64 T5_REGMAP_SIZE = (332 * 1024),
65};
66
625ba2c2
DM		 67enum {
68 MEM_EDC0,
69 MEM_EDC1,
2422d9a3
SR		 70 MEM_MC,
71 MEM_MC0 = MEM_MC,
72 MEM_MC1
625ba2c2
DM		 73};
74
3069ee9b 75enum {
3eb4afbf
VP		 76 MEMWIN0_APERTURE = 2048,
77 MEMWIN0_BASE = 0x1b800,
3069ee9b
VP		 78 MEMWIN1_APERTURE = 32768,
79 MEMWIN1_BASE = 0x28000,
2422d9a3 80 MEMWIN1_BASE_T5 = 0x52000,
3eb4afbf
VP		 81 MEMWIN2_APERTURE = 65536,
82 MEMWIN2_BASE = 0x30000,
0abfd152
HS		 83 MEMWIN2_APERTURE_T5 = 131072,
84 MEMWIN2_BASE_T5 = 0x60000,
3069ee9b
VP		 85};
86
625ba2c2
DM		 87enum dev_master {
88 MASTER_CANT,
89 MASTER_MAY,
90 MASTER_MUST
91};
92
93enum dev_state {
94 DEV_STATE_UNINIT,
95 DEV_STATE_INIT,
96 DEV_STATE_ERR
97};
98
99enum {
100 PAUSE_RX = 1 << 0,
101 PAUSE_TX = 1 << 1,
102 PAUSE_AUTONEG = 1 << 2
103};
104
105struct port_stats {
106 u64 tx_octets; /* total # of octets in good frames */
107 u64 tx_frames; /* all good frames */
108 u64 tx_bcast_frames; /* all broadcast frames */
109 u64 tx_mcast_frames; /* all multicast frames */
110 u64 tx_ucast_frames; /* all unicast frames */
111 u64 tx_error_frames; /* all error frames */
112
113 u64 tx_frames_64; /* # of Tx frames in a particular range */
114 u64 tx_frames_65_127;
115 u64 tx_frames_128_255;
116 u64 tx_frames_256_511;
117 u64 tx_frames_512_1023;
118 u64 tx_frames_1024_1518;
119 u64 tx_frames_1519_max;
120
121 u64 tx_drop; /* # of dropped Tx frames */
122 u64 tx_pause; /* # of transmitted pause frames */
123 u64 tx_ppp0; /* # of transmitted PPP prio 0 frames */
124 u64 tx_ppp1; /* # of transmitted PPP prio 1 frames */
125 u64 tx_ppp2; /* # of transmitted PPP prio 2 frames */
126 u64 tx_ppp3; /* # of transmitted PPP prio 3 frames */
127 u64 tx_ppp4; /* # of transmitted PPP prio 4 frames */
128 u64 tx_ppp5; /* # of transmitted PPP prio 5 frames */
129 u64 tx_ppp6; /* # of transmitted PPP prio 6 frames */
130 u64 tx_ppp7; /* # of transmitted PPP prio 7 frames */
131
132 u64 rx_octets; /* total # of octets in good frames */
133 u64 rx_frames; /* all good frames */
134 u64 rx_bcast_frames; /* all broadcast frames */
135 u64 rx_mcast_frames; /* all multicast frames */
136 u64 rx_ucast_frames; /* all unicast frames */
137 u64 rx_too_long; /* # of frames exceeding MTU */
138 u64 rx_jabber; /* # of jabber frames */
139 u64 rx_fcs_err; /* # of received frames with bad FCS */
140 u64 rx_len_err; /* # of received frames with length error */
141 u64 rx_symbol_err; /* symbol errors */
142 u64 rx_runt; /* # of short frames */
143
144 u64 rx_frames_64; /* # of Rx frames in a particular range */
145 u64 rx_frames_65_127;
146 u64 rx_frames_128_255;
147 u64 rx_frames_256_511;
148 u64 rx_frames_512_1023;
149 u64 rx_frames_1024_1518;
150 u64 rx_frames_1519_max;
151
152 u64 rx_pause; /* # of received pause frames */
153 u64 rx_ppp0; /* # of received PPP prio 0 frames */
154 u64 rx_ppp1; /* # of received PPP prio 1 frames */
155 u64 rx_ppp2; /* # of received PPP prio 2 frames */
156 u64 rx_ppp3; /* # of received PPP prio 3 frames */
157 u64 rx_ppp4; /* # of received PPP prio 4 frames */
158 u64 rx_ppp5; /* # of received PPP prio 5 frames */
159 u64 rx_ppp6; /* # of received PPP prio 6 frames */
160 u64 rx_ppp7; /* # of received PPP prio 7 frames */
161
162 u64 rx_ovflow0; /* drops due to buffer-group 0 overflows */
163 u64 rx_ovflow1; /* drops due to buffer-group 1 overflows */
164 u64 rx_ovflow2; /* drops due to buffer-group 2 overflows */
165 u64 rx_ovflow3; /* drops due to buffer-group 3 overflows */
166 u64 rx_trunc0; /* buffer-group 0 truncated packets */
167 u64 rx_trunc1; /* buffer-group 1 truncated packets */
168 u64 rx_trunc2; /* buffer-group 2 truncated packets */
169 u64 rx_trunc3; /* buffer-group 3 truncated packets */
170};
171
172struct lb_port_stats {
173 u64 octets;
174 u64 frames;
175 u64 bcast_frames;
176 u64 mcast_frames;
177 u64 ucast_frames;
178 u64 error_frames;
179
180 u64 frames_64;
181 u64 frames_65_127;
182 u64 frames_128_255;
183 u64 frames_256_511;
184 u64 frames_512_1023;
185 u64 frames_1024_1518;
186 u64 frames_1519_max;
187
188 u64 drop;
189
190 u64 ovflow0;
191 u64 ovflow1;
192 u64 ovflow2;
193 u64 ovflow3;
194 u64 trunc0;
195 u64 trunc1;
196 u64 trunc2;
197 u64 trunc3;
198};
199
200struct tp_tcp_stats {
201 u32 tcpOutRsts;
202 u64 tcpInSegs;
203 u64 tcpOutSegs;
204 u64 tcpRetransSegs;
205};
206
207struct tp_err_stats {
208 u32 macInErrs[4];
209 u32 hdrInErrs[4];
210 u32 tcpInErrs[4];
211 u32 tnlCongDrops[4];
212 u32 ofldChanDrops[4];
213 u32 tnlTxDrops[4];
214 u32 ofldVlanDrops[4];
215 u32 tcp6InErrs[4];
216 u32 ofldNoNeigh;
217 u32 ofldCongDefer;
218};
219
e85c9a7a
HS		 220struct sge_params {
221 u32 hps; /* host page size for our PF/VF */
222 u32 eq_qpp; /* egress queues/page for our PF/VF */
223 u32 iq_qpp; /* egress queues/page for our PF/VF */
224};
225
625ba2c2 226struct tp_params {
625ba2c2 227 unsigned int tre; /* log2 of core clocks per TP tick */
2d277b3b 228 unsigned int la_mask; /* what events are recorded by TP LA */
dca4faeb
VP		 229 unsigned short tx_modq_map; /* TX modulation scheduler queue to */
230 /* channel map */
636f9d37
VP		 231
232 uint32_t dack_re; /* DACK timer resolution */
233 unsigned short tx_modq[NCHAN]; /* channel to modulation queue map */
dcf7b6f5
KS		 234
235 u32 vlan_pri_map; /* cached TP_VLAN_PRI_MAP */
236 u32 ingress_config; /* cached TP_INGRESS_CONFIG */
237
238 /* TP_VLAN_PRI_MAP Compressed Filter Tuple field offsets. This is a
239 * subset of the set of fields which may be present in the Compressed
240 * Filter Tuple portion of filters and TCP TCB connections. The
241 * fields which are present are controlled by the TP_VLAN_PRI_MAP.
242 * Since a variable number of fields may or may not be present, their
243 * shifted field positions within the Compressed Filter Tuple may
244 * vary, or not even be present if the field isn't selected in
245 * TP_VLAN_PRI_MAP. Since some of these fields are needed in various
246 * places we store their offsets here, or a -1 if the field isn't
247 * present.
248 */
249 int vlan_shift;
250 int vnic_shift;
251 int port_shift;
252 int protocol_shift;
625ba2c2
DM		 253};
254
255struct vpd_params {
256 unsigned int cclk;
257 u8 ec[EC_LEN + 1];
258 u8 sn[SERNUM_LEN + 1];
259 u8 id[ID_LEN + 1];
a94cd705 260 u8 pn[PN_LEN + 1];
625ba2c2
DM		 261};
262
263struct pci_params {
264 unsigned char speed;
265 unsigned char width;
266};
267
d14807dd
HS		 268#define CHELSIO_CHIP_CODE(version, revision) (((version) << 4) | (revision))
269#define CHELSIO_CHIP_FPGA 0x100
270#define CHELSIO_CHIP_VERSION(code) (((code) >> 4) & 0xf)
271#define CHELSIO_CHIP_RELEASE(code) ((code) & 0xf)
272
273#define CHELSIO_T4 0x4
274#define CHELSIO_T5 0x5
ab4b583b 275#define CHELSIO_T6 0x6
d14807dd
HS		 276
277enum chip_type {
278 T4_A1 = CHELSIO_CHIP_CODE(CHELSIO_T4, 1),
279 T4_A2 = CHELSIO_CHIP_CODE(CHELSIO_T4, 2),
280 T4_FIRST_REV = T4_A1,
281 T4_LAST_REV = T4_A2,
282
283 T5_A0 = CHELSIO_CHIP_CODE(CHELSIO_T5, 0),
284 T5_A1 = CHELSIO_CHIP_CODE(CHELSIO_T5, 1),
285 T5_FIRST_REV = T5_A0,
286 T5_LAST_REV = T5_A1,
ab4b583b
HS		 287
288 T6_A0 = CHELSIO_CHIP_CODE(CHELSIO_T6, 0),
289 T6_FIRST_REV = T6_A0,
290 T6_LAST_REV = T6_A0,
d14807dd
HS		 291};
292
49aa284f
HS		 293struct devlog_params {
294 u32 memtype; /* which memory (EDC0, EDC1, MC) */
295 u32 start; /* start of log in firmware memory */
296 u32 size; /* size of log */
297};
298
3ccc6cf7
HS		 299/* Stores chip specific parameters */
300struct arch_specific_params {
301 u8 nchan;
302 u16 mps_rplc_size;
303 u16 vfcount;
304 u32 sge_fl_db;
305 u16 mps_tcam_size;
306};
307
625ba2c2 308struct adapter_params {
e85c9a7a 309 struct sge_params sge;
625ba2c2
DM		 310 struct tp_params tp;
311 struct vpd_params vpd;
312 struct pci_params pci;
49aa284f
HS		 313 struct devlog_params devlog;
314 enum pcie_memwin drv_memwin;
625ba2c2 315
f1ff24aa
HS		 316 unsigned int cim_la_size;
317
900a6596
DM		 318 unsigned int sf_size; /* serial flash size in bytes */
319 unsigned int sf_nsec; /* # of flash sectors */
320 unsigned int sf_fw_start; /* start of FW image in flash */
321
625ba2c2
DM		 322 unsigned int fw_vers;
323 unsigned int tp_vers;
324 u8 api_vers[7];
325
326 unsigned short mtus[NMTUS];
327 unsigned short a_wnd[NCCTRL_WIN];
328 unsigned short b_wnd[NCCTRL_WIN];
329
330 unsigned char nports; /* # of ethernet ports */
331 unsigned char portvec;
d14807dd 332 enum chip_type chip; /* chip code */
3ccc6cf7 333 struct arch_specific_params arch; /* chip specific params */
625ba2c2
DM		 334 unsigned char offload;
335
9a4da2cd
VP		 336 unsigned char bypass;
337
625ba2c2 338 unsigned int ofldq_wr_cred;
1ac0f095 339 bool ulptx_memwrite_dsgl; /* use of T5 DSGL allowed */
4c2c5763
HS		 340
341 unsigned int max_ordird_qp; /* Max read depth per RDMA QP */
342 unsigned int max_ird_adapter; /* Max read depth per adapter */
625ba2c2
DM		 343};
344
a3bfb617
HS		 345/* State needed to monitor the forward progress of SGE Ingress DMA activities
346 * and possible hangs.
347 */
348struct sge_idma_monitor_state {
349 unsigned int idma_1s_thresh; /* 1s threshold in Core Clock ticks */
350 unsigned int idma_stalled[2]; /* synthesized stalled timers in HZ */
351 unsigned int idma_state[2]; /* IDMA Hang detect state */
352 unsigned int idma_qid[2]; /* IDMA Hung Ingress Queue ID */
353 unsigned int idma_warn[2]; /* time to warning in HZ */
354};
355
16e47624
HS		 356#include "t4fw_api.h"
357
358#define FW_VERSION(chip) ( \
b2e1a3f0
HS		 359 FW_HDR_FW_VER_MAJOR_G(chip##FW_VERSION_MAJOR) | \
360 FW_HDR_FW_VER_MINOR_G(chip##FW_VERSION_MINOR) | \
361 FW_HDR_FW_VER_MICRO_G(chip##FW_VERSION_MICRO) | \
362 FW_HDR_FW_VER_BUILD_G(chip##FW_VERSION_BUILD))
16e47624
HS		 363#define FW_INTFVER(chip, intf) (FW_HDR_INTFVER_##intf)
364
365struct fw_info {
366 u8 chip;
367 char *fs_name;
368 char *fw_mod_name;
369 struct fw_hdr fw_hdr;
370};
371
372
625ba2c2
DM		 373struct trace_params {
374 u32 data[TRACE_LEN / 4];
375 u32 mask[TRACE_LEN / 4];
376 unsigned short snap_len;
377 unsigned short min_len;
378 unsigned char skip_ofst;
379 unsigned char skip_len;
380 unsigned char invert;
381 unsigned char port;
382};
383
384struct link_config {
385 unsigned short supported; /* link capabilities */
386 unsigned short advertising; /* advertised capabilities */
387 unsigned short requested_speed; /* speed user has requested */
388 unsigned short speed; /* actual link speed */
389 unsigned char requested_fc; /* flow control user has requested */
390 unsigned char fc; /* actual link flow control */
391 unsigned char autoneg; /* autonegotiating? */
392 unsigned char link_ok; /* link up? */
393};
394
e2ac9628 395#define FW_LEN16(fw_struct) FW_CMD_LEN16_V(sizeof(fw_struct) / 16)
625ba2c2
DM		 396
397enum {
398 MAX_ETH_QSETS = 32, /* # of Ethernet Tx/Rx queue sets */
399 MAX_OFLD_QSETS = 16, /* # of offload Tx/Rx queue sets */
400 MAX_CTRL_QUEUES = NCHAN, /* # of control Tx queues */
401 MAX_RDMA_QUEUES = NCHAN, /* # of streaming RDMA Rx queues */
f36e58e5 402 MAX_RDMA_CIQS = 32, /* # of RDMA concentrator IQs */
cf38be6d 403 MAX_ISCSI_QUEUES = NCHAN, /* # of streaming iSCSI Rx queues */
625ba2c2
DM		 404};
405
812034f1
HS		 406enum {
407 MAX_TXQ_ENTRIES = 16384,
408 MAX_CTRL_TXQ_ENTRIES = 1024,
409 MAX_RSPQ_ENTRIES = 16384,
410 MAX_RX_BUFFERS = 16384,
411 MIN_TXQ_ENTRIES = 32,
412 MIN_CTRL_TXQ_ENTRIES = 32,
413 MIN_RSPQ_ENTRIES = 128,
414 MIN_FL_ENTRIES = 16
415};
416
625ba2c2 417enum {
cf38be6d
HS		 418 INGQ_EXTRAS = 2, /* firmware event queue and */
419 /* forwarded interrupts */
cf38be6d
HS		 420 MAX_INGQ = MAX_ETH_QSETS + MAX_OFLD_QSETS + MAX_RDMA_QUEUES
421 + MAX_RDMA_CIQS + MAX_ISCSI_QUEUES + INGQ_EXTRAS,
625ba2c2
DM		 422};
423
424struct adapter;
625ba2c2
DM		 425struct sge_rspq;
426
688848b1
AB		 427#include "cxgb4_dcb.h"
428
76fed8a9
VP		 429#ifdef CONFIG_CHELSIO_T4_FCOE
430#include "cxgb4_fcoe.h"
431#endif /* CONFIG_CHELSIO_T4_FCOE */
432
625ba2c2
DM		 433struct port_info {
434 struct adapter *adapter;
625ba2c2
DM		 435 u16 viid;
436 s16 xact_addr_filt; /* index of exact MAC address filter */
437 u16 rss_size; /* size of VI's RSS table slice */
438 s8 mdio_addr;
40e9de4b 439 enum fw_port_type port_type;
625ba2c2
DM		 440 u8 mod_type;
441 u8 port_id;
442 u8 tx_chan;
443 u8 lport; /* associated offload logical port */
625ba2c2
DM		 444 u8 nqsets; /* # of qsets */
445 u8 first_qset; /* index of first qset */
f796564a 446 u8 rss_mode;
625ba2c2 447 struct link_config link_cfg;
671b0060 448 u16 *rss;
688848b1
AB		 449#ifdef CONFIG_CHELSIO_T4_DCB
450 struct port_dcb_info dcb; /* Data Center Bridging support */
451#endif
76fed8a9
VP		 452#ifdef CONFIG_CHELSIO_T4_FCOE
453 struct cxgb_fcoe fcoe;
454#endif /* CONFIG_CHELSIO_T4_FCOE */
625ba2c2
DM		 455};
456
625ba2c2
DM		 457struct dentry;
458struct work_struct;
459
460enum { /* adapter flags */
461 FULL_INIT_DONE = (1 << 0),
144be3d9
GS		 462 DEV_ENABLED = (1 << 1),
463 USING_MSI = (1 << 2),
464 USING_MSIX = (1 << 3),
625ba2c2 465 FW_OK = (1 << 4),
13ee15d3 466 RSS_TNLALLLOOKUP = (1 << 5),
52367a76
VP		 467 USING_SOFT_PARAMS = (1 << 6),
468 MASTER_PF = (1 << 7),
469 FW_OFLD_CONN = (1 << 9),
625ba2c2
DM		 470};
471
472struct rx_sw_desc;
473
474struct sge_fl { /* SGE free-buffer queue state */
475 unsigned int avail; /* # of available Rx buffers */
476 unsigned int pend_cred; /* new buffers since last FL DB ring */
477 unsigned int cidx; /* consumer index */
478 unsigned int pidx; /* producer index */
479 unsigned long alloc_failed; /* # of times buffer allocation failed */
480 unsigned long large_alloc_failed;
481 unsigned long starving;
482 /* RO fields */
483 unsigned int cntxt_id; /* SGE context id for the free list */
484 unsigned int size; /* capacity of free list */
485 struct rx_sw_desc *sdesc; /* address of SW Rx descriptor ring */
486 __be64 *desc; /* address of HW Rx descriptor ring */
487 dma_addr_t addr; /* bus address of HW ring start */
df64e4d3
HS		 488 void __iomem *bar2_addr; /* address of BAR2 Queue registers */
489 unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */
625ba2c2
DM		 490};
491
492/* A packet gather list */
493struct pkt_gl {
e91b0f24 494 struct page_frag frags[MAX_SKB_FRAGS];
625ba2c2
DM		 495 void *va; /* virtual address of first byte */
496 unsigned int nfrags; /* # of fragments */
497 unsigned int tot_len; /* total length of fragments */
498};
499
500typedef int (*rspq_handler_t)(struct sge_rspq *q, const __be64 *rsp,
501 const struct pkt_gl *gl);
502
503struct sge_rspq { /* state for an SGE response queue */
504 struct napi_struct napi;
505 const __be64 *cur_desc; /* current descriptor in queue */
506 unsigned int cidx; /* consumer index */
507 u8 gen; /* current generation bit */
508 u8 intr_params; /* interrupt holdoff parameters */
509 u8 next_intr_params; /* holdoff params for next interrupt */
e553ec3f 510 u8 adaptive_rx;
625ba2c2
DM		 511 u8 pktcnt_idx; /* interrupt packet threshold */
512 u8 uld; /* ULD handling this queue */
513 u8 idx; /* queue index within its group */
514 int offset; /* offset into current Rx buffer */
515 u16 cntxt_id; /* SGE context id for the response q */
516 u16 abs_id; /* absolute SGE id for the response q */
517 __be64 *desc; /* address of HW response ring */
518 dma_addr_t phys_addr; /* physical address of the ring */
df64e4d3
HS		 519 void __iomem *bar2_addr; /* address of BAR2 Queue registers */
520 unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */
625ba2c2
DM		 521 unsigned int iqe_len; /* entry size */
522 unsigned int size; /* capacity of response queue */
523 struct adapter *adap;
524 struct net_device *netdev; /* associated net device */
525 rspq_handler_t handler;
3a336cb1
HS		 526#ifdef CONFIG_NET_RX_BUSY_POLL
527#define CXGB_POLL_STATE_IDLE 0
528#define CXGB_POLL_STATE_NAPI BIT(0) /* NAPI owns this poll */
529#define CXGB_POLL_STATE_POLL BIT(1) /* poll owns this poll */
530#define CXGB_POLL_STATE_NAPI_YIELD BIT(2) /* NAPI yielded this poll */
531#define CXGB_POLL_STATE_POLL_YIELD BIT(3) /* poll yielded this poll */
532#define CXGB_POLL_YIELD (CXGB_POLL_STATE_NAPI_YIELD | \
533 CXGB_POLL_STATE_POLL_YIELD)
534#define CXGB_POLL_LOCKED (CXGB_POLL_STATE_NAPI | \
535 CXGB_POLL_STATE_POLL)
536#define CXGB_POLL_USER_PEND (CXGB_POLL_STATE_POLL | \
537 CXGB_POLL_STATE_POLL_YIELD)
538 unsigned int bpoll_state;
539 spinlock_t bpoll_lock; /* lock for busy poll */
540#endif /* CONFIG_NET_RX_BUSY_POLL */
541
625ba2c2
DM		 542};
543
544struct sge_eth_stats { /* Ethernet queue statistics */
545 unsigned long pkts; /* # of ethernet packets */
546 unsigned long lro_pkts; /* # of LRO super packets */
547 unsigned long lro_merged; /* # of wire packets merged by LRO */
548 unsigned long rx_cso; /* # of Rx checksum offloads */
549 unsigned long vlan_ex; /* # of Rx VLAN extractions */
550 unsigned long rx_drops; /* # of packets dropped due to no mem */
551};
552
553struct sge_eth_rxq { /* SW Ethernet Rx queue */
554 struct sge_rspq rspq;
555 struct sge_fl fl;
556 struct sge_eth_stats stats;
557} ____cacheline_aligned_in_smp;
558
559struct sge_ofld_stats { /* offload queue statistics */
560 unsigned long pkts; /* # of packets */
561 unsigned long imm; /* # of immediate-data packets */
562 unsigned long an; /* # of asynchronous notifications */
563 unsigned long nomem; /* # of responses deferred due to no mem */
564};
565
566struct sge_ofld_rxq { /* SW offload Rx queue */
567 struct sge_rspq rspq;
568 struct sge_fl fl;
569 struct sge_ofld_stats stats;
570} ____cacheline_aligned_in_smp;
571
572struct tx_desc {
573 __be64 flit[8];
574};
575
576struct tx_sw_desc;
577
578struct sge_txq {
579 unsigned int in_use; /* # of in-use Tx descriptors */
580 unsigned int size; /* # of descriptors */
581 unsigned int cidx; /* SW consumer index */
582 unsigned int pidx; /* producer index */
583 unsigned long stops; /* # of times q has been stopped */
584 unsigned long restarts; /* # of queue restarts */
585 unsigned int cntxt_id; /* SGE context id for the Tx q */
586 struct tx_desc *desc; /* address of HW Tx descriptor ring */
587 struct tx_sw_desc *sdesc; /* address of SW Tx descriptor ring */
588 struct sge_qstat *stat; /* queue status entry */
589 dma_addr_t phys_addr; /* physical address of the ring */
3069ee9b
VP		 590 spinlock_t db_lock;
591 int db_disabled;
592 unsigned short db_pidx;
05eb2389 593 unsigned short db_pidx_inc;
df64e4d3
HS		 594 void __iomem *bar2_addr; /* address of BAR2 Queue registers */
595 unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */
625ba2c2
DM		 596};
597
598struct sge_eth_txq { /* state for an SGE Ethernet Tx queue */
599 struct sge_txq q;
600 struct netdev_queue *txq; /* associated netdev TX queue */
10b00466
AB		 601#ifdef CONFIG_CHELSIO_T4_DCB
602 u8 dcb_prio; /* DCB Priority bound to queue */
603#endif
625ba2c2
DM		 604 unsigned long tso; /* # of TSO requests */
605 unsigned long tx_cso; /* # of Tx checksum offloads */
606 unsigned long vlan_ins; /* # of Tx VLAN insertions */
607 unsigned long mapping_err; /* # of I/O MMU packet mapping errors */
608} ____cacheline_aligned_in_smp;
609
610struct sge_ofld_txq { /* state for an SGE offload Tx queue */
611 struct sge_txq q;
612 struct adapter *adap;
613 struct sk_buff_head sendq; /* list of backpressured packets */
614 struct tasklet_struct qresume_tsk; /* restarts the queue */
615 u8 full; /* the Tx ring is full */
616 unsigned long mapping_err; /* # of I/O MMU packet mapping errors */
617} ____cacheline_aligned_in_smp;
618
619struct sge_ctrl_txq { /* state for an SGE control Tx queue */
620 struct sge_txq q;
621 struct adapter *adap;
622 struct sk_buff_head sendq; /* list of backpressured packets */
623 struct tasklet_struct qresume_tsk; /* restarts the queue */
624 u8 full; /* the Tx ring is full */
625} ____cacheline_aligned_in_smp;
626
627struct sge {
628 struct sge_eth_txq ethtxq[MAX_ETH_QSETS];
629 struct sge_ofld_txq ofldtxq[MAX_OFLD_QSETS];
630 struct sge_ctrl_txq ctrlq[MAX_CTRL_QUEUES];
631
632 struct sge_eth_rxq ethrxq[MAX_ETH_QSETS];
633 struct sge_ofld_rxq ofldrxq[MAX_OFLD_QSETS];
634 struct sge_ofld_rxq rdmarxq[MAX_RDMA_QUEUES];
cf38be6d 635 struct sge_ofld_rxq rdmaciq[MAX_RDMA_CIQS];
625ba2c2
DM		 636 struct sge_rspq fw_evtq ____cacheline_aligned_in_smp;
637
638 struct sge_rspq intrq ____cacheline_aligned_in_smp;
639 spinlock_t intrq_lock;
640
641 u16 max_ethqsets; /* # of available Ethernet queue sets */
642 u16 ethqsets; /* # of active Ethernet queue sets */
643 u16 ethtxq_rover; /* Tx queue to clean up next */
644 u16 ofldqsets; /* # of active offload queue sets */
645 u16 rdmaqs; /* # of available RDMA Rx queues */
cf38be6d 646 u16 rdmaciqs; /* # of available RDMA concentrator IQs */
625ba2c2 647 u16 ofld_rxq[MAX_OFLD_QSETS];
f36e58e5
HS		 648 u16 rdma_rxq[MAX_RDMA_QUEUES];
649 u16 rdma_ciq[MAX_RDMA_CIQS];
625ba2c2
DM		 650 u16 timer_val[SGE_NTIMERS];
651 u8 counter_val[SGE_NCOUNTERS];
52367a76
VP		 652 u32 fl_pg_order; /* large page allocation size */
653 u32 stat_len; /* length of status page at ring end */
654 u32 pktshift; /* padding between CPL & packet data */
655 u32 fl_align; /* response queue message alignment */
656 u32 fl_starve_thres; /* Free List starvation threshold */
0f4d201f 657
a3bfb617 658 struct sge_idma_monitor_state idma_monitor;
e46dab4d 659 unsigned int egr_start;
4b8e27a8 660 unsigned int egr_sz;
e46dab4d 661 unsigned int ingr_start;
4b8e27a8
HS		 662 unsigned int ingr_sz;
663 void **egr_map; /* qid->queue egress queue map */
664 struct sge_rspq **ingr_map; /* qid->queue ingress queue map */
665 unsigned long *starving_fl;
666 unsigned long *txq_maperr;
5b377d11 667 unsigned long *blocked_fl;
625ba2c2
DM		 668 struct timer_list rx_timer; /* refills starving FLs */
669 struct timer_list tx_timer; /* checks Tx queues */
670};
671
672#define for_each_ethrxq(sge, i) for (i = 0; i < (sge)->ethqsets; i++)
673#define for_each_ofldrxq(sge, i) for (i = 0; i < (sge)->ofldqsets; i++)
674#define for_each_rdmarxq(sge, i) for (i = 0; i < (sge)->rdmaqs; i++)
cf38be6d 675#define for_each_rdmaciq(sge, i) for (i = 0; i < (sge)->rdmaciqs; i++)
625ba2c2
DM		 676
677struct l2t_data;
678
2422d9a3
SR		 679#ifdef CONFIG_PCI_IOV
680
7d6727cf
SR		 681/* T4 supports SRIOV on PF0-3 and T5 on PF0-7. However, the Serial
682 * Configuration initialization for T5 only has SR-IOV functionality enabled
683 * on PF0-3 in order to simplify everything.
2422d9a3 684 */
7d6727cf 685#define NUM_OF_PF_WITH_SRIOV 4
2422d9a3
SR		 686
687#endif
688
625ba2c2
DM		 689struct adapter {
690 void __iomem *regs;
22adfe0a 691 void __iomem *bar2;
0abfd152 692 u32 t4_bar0;
625ba2c2
DM		 693 struct pci_dev *pdev;
694 struct device *pdev_dev;
3069ee9b 695 unsigned int mbox;
b2612722 696 unsigned int pf;
060e0c75 697 unsigned int flags;
2422d9a3 698 enum chip_type chip;
625ba2c2 699
625ba2c2
DM		 700 int msg_enable;
701
702 struct adapter_params params;
703 struct cxgb4_virt_res vres;
704 unsigned int swintr;
705
706 unsigned int wol;
707
708 struct {
709 unsigned short vec;
8cd18ac4 710 char desc[IFNAMSIZ + 10];
625ba2c2
DM		 711 } msix_info[MAX_INGQ + 1];
712
713 struct sge sge;
714
715 struct net_device *port[MAX_NPORTS];
716 u8 chan_map[NCHAN]; /* channel -> port map */
717
793dad94 718 u32 filter_mode;
636f9d37
VP		 719 unsigned int l2t_start;
720 unsigned int l2t_end;
625ba2c2 721 struct l2t_data *l2t;
b5a02f50
AB		 722 unsigned int clipt_start;
723 unsigned int clipt_end;
724 struct clip_tbl *clipt;
625ba2c2
DM		 725 void *uld_handle[CXGB4_ULD_MAX];
726 struct list_head list_node;
01bcca68 727 struct list_head rcu_node;
625ba2c2
DM		 728
729 struct tid_info tids;
730 void **tid_release_head;
731 spinlock_t tid_release_lock;
29aaee65 732 struct workqueue_struct *workq;
625ba2c2 733 struct work_struct tid_release_task;
881806bc
VP		 734 struct work_struct db_full_task;
735 struct work_struct db_drop_task;
625ba2c2
DM		 736 bool tid_release_task_busy;
737
738 struct dentry *debugfs_root;
739
740 spinlock_t stats_lock;
fc5ab020 741 spinlock_t win0_lock ____cacheline_aligned_in_smp;
625ba2c2
DM		 742};
743
f2b7e78d
VP		 744/* Defined bit width of user definable filter tuples
745 */
746#define ETHTYPE_BITWIDTH 16
747#define FRAG_BITWIDTH 1
748#define MACIDX_BITWIDTH 9
749#define FCOE_BITWIDTH 1
750#define IPORT_BITWIDTH 3
751#define MATCHTYPE_BITWIDTH 3
752#define PROTO_BITWIDTH 8
753#define TOS_BITWIDTH 8
754#define PF_BITWIDTH 8
755#define VF_BITWIDTH 8
756#define IVLAN_BITWIDTH 16
757#define OVLAN_BITWIDTH 16
758
759/* Filter matching rules. These consist of a set of ingress packet field
760 * (value, mask) tuples. The associated ingress packet field matches the
761 * tuple when ((field & mask) == value). (Thus a wildcard "don't care" field
762 * rule can be constructed by specifying a tuple of (0, 0).) A filter rule
763 * matches an ingress packet when all of the individual individual field
764 * matching rules are true.
765 *
766 * Partial field masks are always valid, however, while it may be easy to
767 * understand their meanings for some fields (e.g. IP address to match a
768 * subnet), for others making sensible partial masks is less intuitive (e.g.
769 * MPS match type) ...
770 *
771 * Most of the following data structures are modeled on T4 capabilities.
772 * Drivers for earlier chips use the subsets which make sense for those chips.
773 * We really need to come up with a hardware-independent mechanism to
774 * represent hardware filter capabilities ...
775 */
776struct ch_filter_tuple {
777 /* Compressed header matching field rules. The TP_VLAN_PRI_MAP
778 * register selects which of these fields will participate in the
779 * filter match rules -- up to a maximum of 36 bits. Because
780 * TP_VLAN_PRI_MAP is a global register, all filters must use the same
781 * set of fields.
782 */
783 uint32_t ethtype:ETHTYPE_BITWIDTH; /* Ethernet type */
784 uint32_t frag:FRAG_BITWIDTH; /* IP fragmentation header */
785 uint32_t ivlan_vld:1; /* inner VLAN valid */
786 uint32_t ovlan_vld:1; /* outer VLAN valid */
787 uint32_t pfvf_vld:1; /* PF/VF valid */
788 uint32_t macidx:MACIDX_BITWIDTH; /* exact match MAC index */
789 uint32_t fcoe:FCOE_BITWIDTH; /* FCoE packet */
790 uint32_t iport:IPORT_BITWIDTH; /* ingress port */
791 uint32_t matchtype:MATCHTYPE_BITWIDTH; /* MPS match type */
792 uint32_t proto:PROTO_BITWIDTH; /* protocol type */
793 uint32_t tos:TOS_BITWIDTH; /* TOS/Traffic Type */
794 uint32_t pf:PF_BITWIDTH; /* PCI-E PF ID */
795 uint32_t vf:VF_BITWIDTH; /* PCI-E VF ID */
796 uint32_t ivlan:IVLAN_BITWIDTH; /* inner VLAN */
797 uint32_t ovlan:OVLAN_BITWIDTH; /* outer VLAN */
798
799 /* Uncompressed header matching field rules. These are always
800 * available for field rules.
801 */
802 uint8_t lip[16]; /* local IP address (IPv4 in [3:0]) */
803 uint8_t fip[16]; /* foreign IP address (IPv4 in [3:0]) */
804 uint16_t lport; /* local port */
805 uint16_t fport; /* foreign port */
806};
807
808/* A filter ioctl command.
809 */
810struct ch_filter_specification {
811 /* Administrative fields for filter.
812 */
813 uint32_t hitcnts:1; /* count filter hits in TCB */
814 uint32_t prio:1; /* filter has priority over active/server */
815
816 /* Fundamental filter typing. This is the one element of filter
817 * matching that doesn't exist as a (value, mask) tuple.
818 */
819 uint32_t type:1; /* 0 => IPv4, 1 => IPv6 */
820
821 /* Packet dispatch information. Ingress packets which match the
822 * filter rules will be dropped, passed to the host or switched back
823 * out as egress packets.
824 */
825 uint32_t action:2; /* drop, pass, switch */
826
827 uint32_t rpttid:1; /* report TID in RSS hash field */
828
829 uint32_t dirsteer:1; /* 0 => RSS, 1 => steer to iq */
830 uint32_t iq:10; /* ingress queue */
831
832 uint32_t maskhash:1; /* dirsteer=0: store RSS hash in TCB */
833 uint32_t dirsteerhash:1;/* dirsteer=1: 0 => TCB contains RSS hash */
834 /* 1 => TCB contains IQ ID */
835
836 /* Switch proxy/rewrite fields. An ingress packet which matches a
837 * filter with "switch" set will be looped back out as an egress
838 * packet -- potentially with some Ethernet header rewriting.
839 */
840 uint32_t eport:2; /* egress port to switch packet out */
841 uint32_t newdmac:1; /* rewrite destination MAC address */
842 uint32_t newsmac:1; /* rewrite source MAC address */
843 uint32_t newvlan:2; /* rewrite VLAN Tag */
844 uint8_t dmac[ETH_ALEN]; /* new destination MAC address */
845 uint8_t smac[ETH_ALEN]; /* new source MAC address */
846 uint16_t vlan; /* VLAN Tag to insert */
847
848 /* Filter rule value/mask pairs.
849 */
850 struct ch_filter_tuple val;
851 struct ch_filter_tuple mask;
852};
853
854enum {
855 FILTER_PASS = 0, /* default */
856 FILTER_DROP,
857 FILTER_SWITCH
858};
859
860enum {
861 VLAN_NOCHANGE = 0, /* default */
862 VLAN_REMOVE,
863 VLAN_INSERT,
864 VLAN_REWRITE
865};
866
ab4b583b
HS		 867static inline int is_t6(enum chip_type chip)
868{
869 return CHELSIO_CHIP_VERSION(chip) == CHELSIO_T6;
870}
871
2422d9a3
SR		 872static inline int is_t5(enum chip_type chip)
873{
d14807dd 874 return CHELSIO_CHIP_VERSION(chip) == CHELSIO_T5;
2422d9a3
SR		 875}
876
877static inline int is_t4(enum chip_type chip)
878{
d14807dd 879 return CHELSIO_CHIP_VERSION(chip) == CHELSIO_T4;
2422d9a3
SR		 880}
881
625ba2c2
DM		 882static inline u32 t4_read_reg(struct adapter *adap, u32 reg_addr)
883{
884 return readl(adap->regs + reg_addr);
885}
886
887static inline void t4_write_reg(struct adapter *adap, u32 reg_addr, u32 val)
888{
889 writel(val, adap->regs + reg_addr);
890}
891
892#ifndef readq
893static inline u64 readq(const volatile void __iomem *addr)
894{
895 return readl(addr) + ((u64)readl(addr + 4) << 32);
896}
897
898static inline void writeq(u64 val, volatile void __iomem *addr)
899{
900 writel(val, addr);
901 writel(val >> 32, addr + 4);
902}
903#endif
904
905static inline u64 t4_read_reg64(struct adapter *adap, u32 reg_addr)
906{
907 return readq(adap->regs + reg_addr);
908}
909
910static inline void t4_write_reg64(struct adapter *adap, u32 reg_addr, u64 val)
911{
912 writeq(val, adap->regs + reg_addr);
913}
914
915/**
916 * netdev2pinfo - return the port_info structure associated with a net_device
917 * @dev: the netdev
918 *
919 * Return the struct port_info associated with a net_device
920 */
921static inline struct port_info *netdev2pinfo(const struct net_device *dev)
922{
923 return netdev_priv(dev);
924}
925
926/**
927 * adap2pinfo - return the port_info of a port
928 * @adap: the adapter
929 * @idx: the port index
930 *
931 * Return the port_info structure for the port of the given index.
932 */
933static inline struct port_info *adap2pinfo(struct adapter *adap, int idx)
934{
935 return netdev_priv(adap->port[idx]);
936}
937
938/**
939 * netdev2adap - return the adapter structure associated with a net_device
940 * @dev: the netdev
941 *
942 * Return the struct adapter associated with a net_device
943 */
944static inline struct adapter *netdev2adap(const struct net_device *dev)
945{
946 return netdev2pinfo(dev)->adapter;
947}
948
3a336cb1
HS		 949#ifdef CONFIG_NET_RX_BUSY_POLL
950static inline void cxgb_busy_poll_init_lock(struct sge_rspq *q)
951{
952 spin_lock_init(&q->bpoll_lock);
953 q->bpoll_state = CXGB_POLL_STATE_IDLE;
954}
955
956static inline bool cxgb_poll_lock_napi(struct sge_rspq *q)
957{
958 bool rc = true;
959
960 spin_lock(&q->bpoll_lock);
961 if (q->bpoll_state & CXGB_POLL_LOCKED) {
962 q->bpoll_state |= CXGB_POLL_STATE_NAPI_YIELD;
963 rc = false;
964 } else {
965 q->bpoll_state = CXGB_POLL_STATE_NAPI;
966 }
967 spin_unlock(&q->bpoll_lock);
968 return rc;
969}
970
971static inline bool cxgb_poll_unlock_napi(struct sge_rspq *q)
972{
973 bool rc = false;
974
975 spin_lock(&q->bpoll_lock);
976 if (q->bpoll_state & CXGB_POLL_STATE_POLL_YIELD)
977 rc = true;
978 q->bpoll_state = CXGB_POLL_STATE_IDLE;
979 spin_unlock(&q->bpoll_lock);
980 return rc;
981}
982
983static inline bool cxgb_poll_lock_poll(struct sge_rspq *q)
984{
985 bool rc = true;
986
987 spin_lock_bh(&q->bpoll_lock);
988 if (q->bpoll_state & CXGB_POLL_LOCKED) {
989 q->bpoll_state |= CXGB_POLL_STATE_POLL_YIELD;
990 rc = false;
991 } else {
992 q->bpoll_state |= CXGB_POLL_STATE_POLL;
993 }
994 spin_unlock_bh(&q->bpoll_lock);
995 return rc;
996}
997
998static inline bool cxgb_poll_unlock_poll(struct sge_rspq *q)
999{
1000 bool rc = false;
1001
1002 spin_lock_bh(&q->bpoll_lock);
1003 if (q->bpoll_state & CXGB_POLL_STATE_POLL_YIELD)
1004 rc = true;
1005 q->bpoll_state = CXGB_POLL_STATE_IDLE;
1006 spin_unlock_bh(&q->bpoll_lock);
1007 return rc;
1008}
1009
1010static inline bool cxgb_poll_busy_polling(struct sge_rspq *q)
1011{
1012 return q->bpoll_state & CXGB_POLL_USER_PEND;
1013}
1014#else
1015static inline void cxgb_busy_poll_init_lock(struct sge_rspq *q)
1016{
1017}
1018
1019static inline bool cxgb_poll_lock_napi(struct sge_rspq *q)
1020{
1021 return true;
1022}
1023
1024static inline bool cxgb_poll_unlock_napi(struct sge_rspq *q)
1025{
1026 return false;
1027}
1028
1029static inline bool cxgb_poll_lock_poll(struct sge_rspq *q)
1030{
1031 return false;
1032}
1033
1034static inline bool cxgb_poll_unlock_poll(struct sge_rspq *q)
1035{
1036 return false;
1037}
1038
1039static inline bool cxgb_poll_busy_polling(struct sge_rspq *q)
1040{
1041 return false;
1042}
1043#endif /* CONFIG_NET_RX_BUSY_POLL */
1044
812034f1
HS		 1045/* Return a version number to identify the type of adapter. The scheme is:
1046 * - bits 0..9: chip version
1047 * - bits 10..15: chip revision
1048 * - bits 16..23: register dump version
1049 */
1050static inline unsigned int mk_adap_vers(struct adapter *ap)
1051{
1052 return CHELSIO_CHIP_VERSION(ap->params.chip) |
1053 (CHELSIO_CHIP_RELEASE(ap->params.chip) << 10) | (1 << 16);
1054}
1055
1056/* Return a queue's interrupt hold-off time in us. 0 means no timer. */
1057static inline unsigned int qtimer_val(const struct adapter *adap,
1058 const struct sge_rspq *q)
1059{
1060 unsigned int idx = q->intr_params >> 1;
1061
1062 return idx < SGE_NTIMERS ? adap->sge.timer_val[idx] : 0;
1063}
1064
1065/* driver version & name used for ethtool_drvinfo */
1066extern char cxgb4_driver_name[];
1067extern const char cxgb4_driver_version[];
1068
625ba2c2
DM		 1069void t4_os_portmod_changed(const struct adapter *adap, int port_id);
1070void t4_os_link_changed(struct adapter *adap, int port_id, int link_stat);
1071
1072void *t4_alloc_mem(size_t size);
625ba2c2
DM		 1073
1074void t4_free_sge_resources(struct adapter *adap);
5fa76694 1075void t4_free_ofld_rxqs(struct adapter *adap, int n, struct sge_ofld_rxq *q);
625ba2c2
DM		 1076irq_handler_t t4_intr_handler(struct adapter *adap);
1077netdev_tx_t t4_eth_xmit(struct sk_buff *skb, struct net_device *dev);
1078int t4_ethrx_handler(struct sge_rspq *q, const __be64 *rsp,
1079 const struct pkt_gl *gl);
1080int t4_mgmt_tx(struct adapter *adap, struct sk_buff *skb);
1081int t4_ofld_send(struct adapter *adap, struct sk_buff *skb);
1082int t4_sge_alloc_rxq(struct adapter *adap, struct sge_rspq *iq, bool fwevtq,
1083 struct net_device *dev, int intr_idx,
145ef8a5 1084 struct sge_fl *fl, rspq_handler_t hnd, int cong);
625ba2c2
DM		 1085int t4_sge_alloc_eth_txq(struct adapter *adap, struct sge_eth_txq *txq,
1086 struct net_device *dev, struct netdev_queue *netdevq,
1087 unsigned int iqid);
1088int t4_sge_alloc_ctrl_txq(struct adapter *adap, struct sge_ctrl_txq *txq,
1089 struct net_device *dev, unsigned int iqid,
1090 unsigned int cmplqid);
1091int t4_sge_alloc_ofld_txq(struct adapter *adap, struct sge_ofld_txq *txq,
1092 struct net_device *dev, unsigned int iqid);
1093irqreturn_t t4_sge_intr_msix(int irq, void *cookie);
52367a76 1094int t4_sge_init(struct adapter *adap);
625ba2c2
DM		 1095void t4_sge_start(struct adapter *adap);
1096void t4_sge_stop(struct adapter *adap);
3a336cb1 1097int cxgb_busy_poll(struct napi_struct *napi);
812034f1
HS		 1098int cxgb4_set_rspq_intr_params(struct sge_rspq *q, unsigned int us,
1099 unsigned int cnt);
1100void cxgb4_set_ethtool_ops(struct net_device *netdev);
1101int cxgb4_write_rss(const struct port_info *pi, const u16 *queues);
3069ee9b 1102extern int dbfifo_int_thresh;
625ba2c2
DM		 1103
1104#define for_each_port(adapter, iter) \
1105 for (iter = 0; iter < (adapter)->params.nports; ++iter)
1106
9a4da2cd
VP		 1107static inline int is_bypass(struct adapter *adap)
1108{
1109 return adap->params.bypass;
1110}
1111
1112static inline int is_bypass_device(int device)
1113{
1114 /* this should be set based upon device capabilities */
1115 switch (device) {
1116 case 0x440b:
1117 case 0x440c:
1118 return 1;
1119 default:
1120 return 0;
1121 }
1122}
1123
01b69614
HS		 1124static inline int is_10gbt_device(int device)
1125{
1126 /* this should be set based upon device capabilities */
1127 switch (device) {
1128 case 0x4409:
1129 case 0x4486:
1130 return 1;
1131
1132 default:
1133 return 0;
1134 }
1135}
1136
625ba2c2
DM		 1137static inline unsigned int core_ticks_per_usec(const struct adapter *adap)
1138{
1139 return adap->params.vpd.cclk / 1000;
1140}
1141
1142static inline unsigned int us_to_core_ticks(const struct adapter *adap,
1143 unsigned int us)
1144{
1145 return (us * adap->params.vpd.cclk) / 1000;
1146}
1147
52367a76
VP		 1148static inline unsigned int core_ticks_to_us(const struct adapter *adapter,
1149 unsigned int ticks)
1150{
1151 /* add Core Clock / 2 to round ticks to nearest uS */
1152 return ((ticks * 1000 + adapter->params.vpd.cclk/2) /
1153 adapter->params.vpd.cclk);
1154}
1155
625ba2c2
DM		 1156void t4_set_reg_field(struct adapter *adap, unsigned int addr, u32 mask,
1157 u32 val);
1158
01b69614
HS		 1159int t4_wr_mbox_meat_timeout(struct adapter *adap, int mbox, const void *cmd,
1160 int size, void *rpl, bool sleep_ok, int timeout);
625ba2c2
DM		 1161int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size,
1162 void *rpl, bool sleep_ok);
1163
01b69614
HS		 1164static inline int t4_wr_mbox_timeout(struct adapter *adap, int mbox,
1165 const void *cmd, int size, void *rpl,
1166 int timeout)
1167{
1168 return t4_wr_mbox_meat_timeout(adap, mbox, cmd, size, rpl, true,
1169 timeout);
1170}
1171
625ba2c2
DM		 1172static inline int t4_wr_mbox(struct adapter *adap, int mbox, const void *cmd,
1173 int size, void *rpl)
1174{
1175 return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, true);
1176}
1177
1178static inline int t4_wr_mbox_ns(struct adapter *adap, int mbox, const void *cmd,
1179 int size, void *rpl)
1180{
1181 return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, false);
1182}
1183
13ee15d3
VP		 1184void t4_write_indirect(struct adapter *adap, unsigned int addr_reg,
1185 unsigned int data_reg, const u32 *vals,
1186 unsigned int nregs, unsigned int start_idx);
f2b7e78d
VP		 1187void t4_read_indirect(struct adapter *adap, unsigned int addr_reg,
1188 unsigned int data_reg, u32 *vals, unsigned int nregs,
1189 unsigned int start_idx);
0abfd152 1190void t4_hw_pci_read_cfg4(struct adapter *adapter, int reg, u32 *val);
f2b7e78d
VP		 1191
1192struct fw_filter_wr;
1193
625ba2c2
DM		 1194void t4_intr_enable(struct adapter *adapter);
1195void t4_intr_disable(struct adapter *adapter);
625ba2c2
DM		 1196int t4_slow_intr_handler(struct adapter *adapter);
1197
8203b509 1198int t4_wait_dev_ready(void __iomem *regs);
625ba2c2
DM		 1199int t4_link_start(struct adapter *adap, unsigned int mbox, unsigned int port,
1200 struct link_config *lc);
1201int t4_restart_aneg(struct adapter *adap, unsigned int mbox, unsigned int port);
fc5ab020 1202
b562fc37
HS		 1203u32 t4_read_pcie_cfg4(struct adapter *adap, int reg);
1204u32 t4_get_util_window(struct adapter *adap);
1205void t4_setup_memwin(struct adapter *adap, u32 memwin_base, u32 window);
1206
fc5ab020
HS		 1207#define T4_MEMORY_WRITE 0
1208#define T4_MEMORY_READ 1
1209int t4_memory_rw(struct adapter *adap, int win, int mtype, u32 addr, u32 len,
f01aa633 1210 void *buf, int dir);
fc5ab020
HS		 1211static inline int t4_memory_write(struct adapter *adap, int mtype, u32 addr,
1212 u32 len, __be32 *buf)
1213{
1214 return t4_memory_rw(adap, 0, mtype, addr, len, buf, 0);
1215}
1216
812034f1
HS		 1217unsigned int t4_get_regs_len(struct adapter *adapter);
1218void t4_get_regs(struct adapter *adap, void *buf, size_t buf_size);
1219
625ba2c2 1220int t4_seeprom_wp(struct adapter *adapter, bool enable);
636f9d37 1221int get_vpd_params(struct adapter *adapter, struct vpd_params *p);
49216c1c
HS		 1222int t4_read_flash(struct adapter *adapter, unsigned int addr,
1223 unsigned int nwords, u32 *data, int byte_oriented);
625ba2c2 1224int t4_load_fw(struct adapter *adapter, const u8 *fw_data, unsigned int size);
01b69614
HS		 1225int t4_load_phy_fw(struct adapter *adap,
1226 int win, spinlock_t *lock,
1227 int (*phy_fw_version)(const u8 *, size_t),
1228 const u8 *phy_fw_data, size_t phy_fw_size);
1229int t4_phy_fw_ver(struct adapter *adap, int *phy_fw_ver);
49216c1c 1230int t4_fwcache(struct adapter *adap, enum fw_params_param_dev_fwcache op);
22c0b963
HS		 1231int t4_fw_upgrade(struct adapter *adap, unsigned int mbox,
1232 const u8 *fw_data, unsigned int size, int force);
636f9d37 1233unsigned int t4_flash_cfg_addr(struct adapter *adapter);
16e47624
HS		 1234int t4_get_fw_version(struct adapter *adapter, u32 *vers);
1235int t4_get_tp_version(struct adapter *adapter, u32 *vers);
ba3f8cd5 1236int t4_get_exprom_version(struct adapter *adapter, u32 *vers);
16e47624
HS		 1237int t4_prep_fw(struct adapter *adap, struct fw_info *fw_info,
1238 const u8 *fw_data, unsigned int fw_size,
1239 struct fw_hdr *card_fw, enum dev_state state, int *reset);
625ba2c2 1240int t4_prep_adapter(struct adapter *adapter);
e85c9a7a
HS		 1241
1242enum t4_bar2_qtype { T4_BAR2_QTYPE_EGRESS, T4_BAR2_QTYPE_INGRESS };
b2612722 1243int t4_bar2_sge_qregs(struct adapter *adapter,
e85c9a7a
HS		 1244 unsigned int qid,
1245 enum t4_bar2_qtype qtype,
1246 u64 *pbar2_qoffset,
1247 unsigned int *pbar2_qid);
1248
dc9daab2
HS		 1249unsigned int qtimer_val(const struct adapter *adap,
1250 const struct sge_rspq *q);
ae469b68
HS		 1251
1252int t4_init_devlog_params(struct adapter *adapter);
e85c9a7a 1253int t4_init_sge_params(struct adapter *adapter);
dcf7b6f5
KS		 1254int t4_init_tp_params(struct adapter *adap);
1255int t4_filter_field_shift(const struct adapter *adap, int filter_sel);
c035e183 1256int t4_init_rss_mode(struct adapter *adap, int mbox);
625ba2c2
DM		 1257int t4_port_init(struct adapter *adap, int mbox, int pf, int vf);
1258void t4_fatal_err(struct adapter *adapter);
625ba2c2
DM		 1259int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid,
1260 int start, int n, const u16 *rspq, unsigned int nrspq);
1261int t4_config_glbl_rss(struct adapter *adapter, int mbox, unsigned int mode,
1262 unsigned int flags);
c035e183
HS		 1263int t4_config_vi_rss(struct adapter *adapter, int mbox, unsigned int viid,
1264 unsigned int flags, unsigned int defq);
688ea5fe
HS		 1265int t4_read_rss(struct adapter *adapter, u16 *entries);
1266void t4_read_rss_key(struct adapter *adapter, u32 *key);
1267void t4_write_rss_key(struct adapter *adap, const u32 *key, int idx);
1268void t4_read_rss_pf_config(struct adapter *adapter, unsigned int index,
1269 u32 *valp);
1270void t4_read_rss_vf_config(struct adapter *adapter, unsigned int index,
1271 u32 *vfl, u32 *vfh);
1272u32 t4_read_rss_pf_map(struct adapter *adapter);
1273u32 t4_read_rss_pf_mask(struct adapter *adapter);
1274
145ef8a5 1275unsigned int t4_get_mps_bg_map(struct adapter *adapter, int idx);
b3bbe36a
HS		 1276void t4_pmtx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]);
1277void t4_pmrx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]);
e5f0e43b
HS		 1278int t4_read_cim_ibq(struct adapter *adap, unsigned int qid, u32 *data,
1279 size_t n);
c778af7d
HS		 1280int t4_read_cim_obq(struct adapter *adap, unsigned int qid, u32 *data,
1281 size_t n);
f1ff24aa
HS		 1282int t4_cim_read(struct adapter *adap, unsigned int addr, unsigned int n,
1283 unsigned int *valp);
1284int t4_cim_write(struct adapter *adap, unsigned int addr, unsigned int n,
1285 const unsigned int *valp);
1286int t4_cim_read_la(struct adapter *adap, u32 *la_buf, unsigned int *wrptr);
74b3092c 1287void t4_read_cimq_cfg(struct adapter *adap, u16 *base, u16 *size, u16 *thres);
72aca4bf 1288const char *t4_get_port_type_description(enum fw_port_type port_type);
625ba2c2 1289void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p);
625ba2c2 1290void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log);
bad43792 1291void t4_read_cong_tbl(struct adapter *adap, u16 incr[NMTUS][NCCTRL_WIN]);
636f9d37
VP		 1292void t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr,
1293 unsigned int mask, unsigned int val);
2d277b3b 1294void t4_tp_read_la(struct adapter *adap, u64 *la_buf, unsigned int *wrptr);
625ba2c2
DM		 1295void t4_tp_get_tcp_stats(struct adapter *adap, struct tp_tcp_stats *v4,
1296 struct tp_tcp_stats *v6);
1297void t4_load_mtus(struct adapter *adap, const unsigned short *mtus,
1298 const unsigned short *alpha, const unsigned short *beta);
1299
797ff0f5
HS		 1300void t4_ulprx_read_la(struct adapter *adap, u32 *la_buf);
1301
f2b7e78d
VP		 1302void t4_mk_filtdelwr(unsigned int ftid, struct fw_filter_wr *wr, int qid);
1303
625ba2c2
DM		 1304void t4_wol_magic_enable(struct adapter *adap, unsigned int port,
1305 const u8 *addr);
1306int t4_wol_pat_enable(struct adapter *adap, unsigned int port, unsigned int map,
1307 u64 mask0, u64 mask1, unsigned int crc, bool enable);
1308
1309int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox,
1310 enum dev_master master, enum dev_state *state);
1311int t4_fw_bye(struct adapter *adap, unsigned int mbox);
1312int t4_early_init(struct adapter *adap, unsigned int mbox);
1313int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset);
636f9d37
VP		 1314int t4_fixup_host_params(struct adapter *adap, unsigned int page_size,
1315 unsigned int cache_line_size);
1316int t4_fw_initialize(struct adapter *adap, unsigned int mbox);
625ba2c2
DM		 1317int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
1318 unsigned int vf, unsigned int nparams, const u32 *params,
1319 u32 *val);
01b69614
HS		 1320int t4_query_params_rw(struct adapter *adap, unsigned int mbox, unsigned int pf,
1321 unsigned int vf, unsigned int nparams, const u32 *params,
1322 u32 *val, int rw);
1323int t4_set_params_timeout(struct adapter *adap, unsigned int mbox,
1324 unsigned int pf, unsigned int vf,
1325 unsigned int nparams, const u32 *params,
1326 const u32 *val, int timeout);
625ba2c2
DM		 1327int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
1328 unsigned int vf, unsigned int nparams, const u32 *params,
1329 const u32 *val);
1330int t4_cfg_pfvf(struct adapter *adap, unsigned int mbox, unsigned int pf,
1331 unsigned int vf, unsigned int txq, unsigned int txq_eth_ctrl,
1332 unsigned int rxqi, unsigned int rxq, unsigned int tc,
1333 unsigned int vi, unsigned int cmask, unsigned int pmask,
1334 unsigned int nexact, unsigned int rcaps, unsigned int wxcaps);
1335int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port,
1336 unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac,
1337 unsigned int *rss_size);
625ba2c2 1338int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid,
f8f5aafa
DM		 1339 int mtu, int promisc, int all_multi, int bcast, int vlanex,
1340 bool sleep_ok);
625ba2c2
DM		 1341int t4_alloc_mac_filt(struct adapter *adap, unsigned int mbox,
1342 unsigned int viid, bool free, unsigned int naddr,
1343 const u8 **addr, u16 *idx, u64 *hash, bool sleep_ok);
1344int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid,
1345 int idx, const u8 *addr, bool persist, bool add_smt);
1346int t4_set_addr_hash(struct adapter *adap, unsigned int mbox, unsigned int viid,
1347 bool ucast, u64 vec, bool sleep_ok);
688848b1
AB		 1348int t4_enable_vi_params(struct adapter *adap, unsigned int mbox,
1349 unsigned int viid, bool rx_en, bool tx_en, bool dcb_en);
625ba2c2
DM		 1350int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid,
1351 bool rx_en, bool tx_en);
1352int t4_identify_port(struct adapter *adap, unsigned int mbox, unsigned int viid,
1353 unsigned int nblinks);
1354int t4_mdio_rd(struct adapter *adap, unsigned int mbox, unsigned int phy_addr,
1355 unsigned int mmd, unsigned int reg, u16 *valp);
1356int t4_mdio_wr(struct adapter *adap, unsigned int mbox, unsigned int phy_addr,
1357 unsigned int mmd, unsigned int reg, u16 val);
625ba2c2
DM		 1358int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
1359 unsigned int vf, unsigned int iqtype, unsigned int iqid,
1360 unsigned int fl0id, unsigned int fl1id);
1361int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
1362 unsigned int vf, unsigned int eqid);
1363int t4_ctrl_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
1364 unsigned int vf, unsigned int eqid);
1365int t4_ofld_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
1366 unsigned int vf, unsigned int eqid);
1367int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl);
881806bc
VP		 1368void t4_db_full(struct adapter *adapter);
1369void t4_db_dropped(struct adapter *adapter);
8caa1e84
VP		 1370int t4_fwaddrspace_write(struct adapter *adap, unsigned int mbox,
1371 u32 addr, u32 val);
68bce192 1372void t4_sge_decode_idma_state(struct adapter *adapter, int state);
fd88b31a 1373void t4_free_mem(void *addr);
a3bfb617
HS		 1374void t4_idma_monitor_init(struct adapter *adapter,
1375 struct sge_idma_monitor_state *idma);
1376void t4_idma_monitor(struct adapter *adapter,
1377 struct sge_idma_monitor_state *idma,
1378 int hz, int ticks);
625ba2c2 1379#endif /* __CXGB4_H__ */
Linux kernel - Deliverables
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