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cxgb4 : Fix missing initialization of win0_lock
[deliverable/linux.git] / drivers / net / ethernet / chelsio / cxgb4 / cxgb4_main.c
CommitLineData
b8ff05a9
DM		 1/*
2 * This file is part of the Chelsio T4 Ethernet driver for Linux.
3 *
ce100b8b 4 * Copyright (c) 2003-2014 Chelsio Communications, Inc. All rights reserved.
b8ff05a9
DM		 5 *
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
11 *
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
14 * conditions are met:
15 *
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
18 * disclaimer.
19 *
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
24 *
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
32 * SOFTWARE.
33 */
34
35#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
36
37#include <linux/bitmap.h>
38#include <linux/crc32.h>
39#include <linux/ctype.h>
40#include <linux/debugfs.h>
41#include <linux/err.h>
42#include <linux/etherdevice.h>
43#include <linux/firmware.h>
01789349 44#include <linux/if.h>
b8ff05a9
DM		 45#include <linux/if_vlan.h>
46#include <linux/init.h>
47#include <linux/log2.h>
48#include <linux/mdio.h>
49#include <linux/module.h>
50#include <linux/moduleparam.h>
51#include <linux/mutex.h>
52#include <linux/netdevice.h>
53#include <linux/pci.h>
54#include <linux/aer.h>
55#include <linux/rtnetlink.h>
56#include <linux/sched.h>
57#include <linux/seq_file.h>
58#include <linux/sockios.h>
59#include <linux/vmalloc.h>
60#include <linux/workqueue.h>
61#include <net/neighbour.h>
62#include <net/netevent.h>
01bcca68 63#include <net/addrconf.h>
b8ff05a9
DM		 64#include <asm/uaccess.h>
65
66#include "cxgb4.h"
67#include "t4_regs.h"
68#include "t4_msg.h"
69#include "t4fw_api.h"
688848b1 70#include "cxgb4_dcb.h"
b8ff05a9
DM		 71#include "l2t.h"
72
01bcca68
VP		 73#include <../drivers/net/bonding/bonding.h>
74
75#ifdef DRV_VERSION
76#undef DRV_VERSION
77#endif
3a7f8554
SR		 78#define DRV_VERSION "2.0.0-ko"
79#define DRV_DESC "Chelsio T4/T5 Network Driver"
b8ff05a9
DM		 80
81/*
82 * Max interrupt hold-off timer value in us. Queues fall back to this value
83 * under extreme memory pressure so it's largish to give the system time to
84 * recover.
85 */
86#define MAX_SGE_TIMERVAL 200U
87
7ee9ff94 88enum {
13ee15d3
VP		 89 /*
90 * Physical Function provisioning constants.
91 */
92 PFRES_NVI = 4, /* # of Virtual Interfaces */
93 PFRES_NETHCTRL = 128, /* # of EQs used for ETH or CTRL Qs */
94 PFRES_NIQFLINT = 128, /* # of ingress Qs/w Free List(s)/intr
95 */
96 PFRES_NEQ = 256, /* # of egress queues */
97 PFRES_NIQ = 0, /* # of ingress queues */
98 PFRES_TC = 0, /* PCI-E traffic class */
99 PFRES_NEXACTF = 128, /* # of exact MPS filters */
100
101 PFRES_R_CAPS = FW_CMD_CAP_PF,
102 PFRES_WX_CAPS = FW_CMD_CAP_PF,
103
104#ifdef CONFIG_PCI_IOV
105 /*
106 * Virtual Function provisioning constants. We need two extra Ingress
107 * Queues with Interrupt capability to serve as the VF's Firmware
108 * Event Queue and Forwarded Interrupt Queue (when using MSI mode) --
109 * neither will have Free Lists associated with them). For each
110 * Ethernet/Control Egress Queue and for each Free List, we need an
111 * Egress Context.
112 */
7ee9ff94
CL		 113 VFRES_NPORTS = 1, /* # of "ports" per VF */
114 VFRES_NQSETS = 2, /* # of "Queue Sets" per VF */
115
116 VFRES_NVI = VFRES_NPORTS, /* # of Virtual Interfaces */
117 VFRES_NETHCTRL = VFRES_NQSETS, /* # of EQs used for ETH or CTRL Qs */
118 VFRES_NIQFLINT = VFRES_NQSETS+2,/* # of ingress Qs/w Free List(s)/intr */
7ee9ff94 119 VFRES_NEQ = VFRES_NQSETS*2, /* # of egress queues */
13ee15d3 120 VFRES_NIQ = 0, /* # of non-fl/int ingress queues */
7ee9ff94
CL		 121 VFRES_TC = 0, /* PCI-E traffic class */
122 VFRES_NEXACTF = 16, /* # of exact MPS filters */
123
124 VFRES_R_CAPS = FW_CMD_CAP_DMAQ|FW_CMD_CAP_VF|FW_CMD_CAP_PORT,
125 VFRES_WX_CAPS = FW_CMD_CAP_DMAQ|FW_CMD_CAP_VF,
13ee15d3 126#endif
7ee9ff94
CL		 127};
128
129/*
130 * Provide a Port Access Rights Mask for the specified PF/VF. This is very
131 * static and likely not to be useful in the long run. We really need to
132 * implement some form of persistent configuration which the firmware
133 * controls.
134 */
135static unsigned int pfvfres_pmask(struct adapter *adapter,
136 unsigned int pf, unsigned int vf)
137{
138 unsigned int portn, portvec;
139
140 /*
141 * Give PF's access to all of the ports.
142 */
143 if (vf == 0)
144 return FW_PFVF_CMD_PMASK_MASK;
145
146 /*
147 * For VFs, we'll assign them access to the ports based purely on the
148 * PF. We assign active ports in order, wrapping around if there are
149 * fewer active ports than PFs: e.g. active port[pf % nports].
150 * Unfortunately the adapter's port_info structs haven't been
151 * initialized yet so we have to compute this.
152 */
153 if (adapter->params.nports == 0)
154 return 0;
155
156 portn = pf % adapter->params.nports;
157 portvec = adapter->params.portvec;
158 for (;;) {
159 /*
160 * Isolate the lowest set bit in the port vector. If we're at
161 * the port number that we want, return that as the pmask.
162 * otherwise mask that bit out of the port vector and
163 * decrement our port number ...
164 */
165 unsigned int pmask = portvec ^ (portvec & (portvec-1));
166 if (portn == 0)
167 return pmask;
168 portn--;
169 portvec &= ~pmask;
170 }
171 /*NOTREACHED*/
172}
7ee9ff94 173
b8ff05a9
DM		 174enum {
175 MAX_TXQ_ENTRIES = 16384,
176 MAX_CTRL_TXQ_ENTRIES = 1024,
177 MAX_RSPQ_ENTRIES = 16384,
178 MAX_RX_BUFFERS = 16384,
179 MIN_TXQ_ENTRIES = 32,
180 MIN_CTRL_TXQ_ENTRIES = 32,
181 MIN_RSPQ_ENTRIES = 128,
182 MIN_FL_ENTRIES = 16
183};
184
f2b7e78d
VP		 185/* Host shadow copy of ingress filter entry. This is in host native format
186 * and doesn't match the ordering or bit order, etc. of the hardware of the
187 * firmware command. The use of bit-field structure elements is purely to
188 * remind ourselves of the field size limitations and save memory in the case
189 * where the filter table is large.
190 */
191struct filter_entry {
192 /* Administrative fields for filter.
193 */
194 u32 valid:1; /* filter allocated and valid */
195 u32 locked:1; /* filter is administratively locked */
196
197 u32 pending:1; /* filter action is pending firmware reply */
198 u32 smtidx:8; /* Source MAC Table index for smac */
199 struct l2t_entry *l2t; /* Layer Two Table entry for dmac */
200
201 /* The filter itself. Most of this is a straight copy of information
202 * provided by the extended ioctl(). Some fields are translated to
203 * internal forms -- for instance the Ingress Queue ID passed in from
204 * the ioctl() is translated into the Absolute Ingress Queue ID.
205 */
206 struct ch_filter_specification fs;
207};
208
b8ff05a9
DM		 209#define DFLT_MSG_ENABLE (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK | \
210 NETIF_MSG_TIMER | NETIF_MSG_IFDOWN | NETIF_MSG_IFUP |\
211 NETIF_MSG_RX_ERR | NETIF_MSG_TX_ERR)
212
060e0c75 213#define CH_DEVICE(devid, data) { PCI_VDEVICE(CHELSIO, devid), (data) }
b8ff05a9 214
9baa3c34 215static const struct pci_device_id cxgb4_pci_tbl[] = {
060e0c75 216 CH_DEVICE(0xa000, 0), /* PE10K */
ccea790e
DM		 217 CH_DEVICE(0x4001, -1),
218 CH_DEVICE(0x4002, -1),
219 CH_DEVICE(0x4003, -1),
220 CH_DEVICE(0x4004, -1),
221 CH_DEVICE(0x4005, -1),
222 CH_DEVICE(0x4006, -1),
223 CH_DEVICE(0x4007, -1),
224 CH_DEVICE(0x4008, -1),
225 CH_DEVICE(0x4009, -1),
226 CH_DEVICE(0x400a, -1),
fb1e933d
HS		 227 CH_DEVICE(0x400d, -1),
228 CH_DEVICE(0x400e, -1),
229 CH_DEVICE(0x4080, -1),
230 CH_DEVICE(0x4081, -1),
231 CH_DEVICE(0x4082, -1),
232 CH_DEVICE(0x4083, -1),
233 CH_DEVICE(0x4084, -1),
234 CH_DEVICE(0x4085, -1),
235 CH_DEVICE(0x4086, -1),
236 CH_DEVICE(0x4087, -1),
237 CH_DEVICE(0x4088, -1),
ccea790e
DM		 238 CH_DEVICE(0x4401, 4),
239 CH_DEVICE(0x4402, 4),
240 CH_DEVICE(0x4403, 4),
241 CH_DEVICE(0x4404, 4),
242 CH_DEVICE(0x4405, 4),
243 CH_DEVICE(0x4406, 4),
244 CH_DEVICE(0x4407, 4),
245 CH_DEVICE(0x4408, 4),
246 CH_DEVICE(0x4409, 4),
247 CH_DEVICE(0x440a, 4),
f637d577
VP		 248 CH_DEVICE(0x440d, 4),
249 CH_DEVICE(0x440e, 4),
fb1e933d
HS		 250 CH_DEVICE(0x4480, 4),
251 CH_DEVICE(0x4481, 4),
252 CH_DEVICE(0x4482, 4),
253 CH_DEVICE(0x4483, 4),
254 CH_DEVICE(0x4484, 4),
255 CH_DEVICE(0x4485, 4),
256 CH_DEVICE(0x4486, 4),
257 CH_DEVICE(0x4487, 4),
258 CH_DEVICE(0x4488, 4),
9ef603a0
VP		 259 CH_DEVICE(0x5001, 4),
260 CH_DEVICE(0x5002, 4),
261 CH_DEVICE(0x5003, 4),
262 CH_DEVICE(0x5004, 4),
263 CH_DEVICE(0x5005, 4),
264 CH_DEVICE(0x5006, 4),
265 CH_DEVICE(0x5007, 4),
266 CH_DEVICE(0x5008, 4),
267 CH_DEVICE(0x5009, 4),
268 CH_DEVICE(0x500A, 4),
269 CH_DEVICE(0x500B, 4),
270 CH_DEVICE(0x500C, 4),
271 CH_DEVICE(0x500D, 4),
272 CH_DEVICE(0x500E, 4),
273 CH_DEVICE(0x500F, 4),
274 CH_DEVICE(0x5010, 4),
275 CH_DEVICE(0x5011, 4),
276 CH_DEVICE(0x5012, 4),
277 CH_DEVICE(0x5013, 4),
f0a8e6de
HS		 278 CH_DEVICE(0x5014, 4),
279 CH_DEVICE(0x5015, 4),
0183aa62
HS		 280 CH_DEVICE(0x5080, 4),
281 CH_DEVICE(0x5081, 4),
282 CH_DEVICE(0x5082, 4),
283 CH_DEVICE(0x5083, 4),
284 CH_DEVICE(0x5084, 4),
285 CH_DEVICE(0x5085, 4),
56e03e51 286 CH_DEVICE(0x5086, 4),
91c04a9e
HS		 287 CH_DEVICE(0x5087, 4),
288 CH_DEVICE(0x5088, 4),
9ef603a0
VP		 289 CH_DEVICE(0x5401, 4),
290 CH_DEVICE(0x5402, 4),
291 CH_DEVICE(0x5403, 4),
292 CH_DEVICE(0x5404, 4),
293 CH_DEVICE(0x5405, 4),
294 CH_DEVICE(0x5406, 4),
295 CH_DEVICE(0x5407, 4),
296 CH_DEVICE(0x5408, 4),
297 CH_DEVICE(0x5409, 4),
298 CH_DEVICE(0x540A, 4),
299 CH_DEVICE(0x540B, 4),
300 CH_DEVICE(0x540C, 4),
301 CH_DEVICE(0x540D, 4),
302 CH_DEVICE(0x540E, 4),
303 CH_DEVICE(0x540F, 4),
304 CH_DEVICE(0x5410, 4),
305 CH_DEVICE(0x5411, 4),
306 CH_DEVICE(0x5412, 4),
307 CH_DEVICE(0x5413, 4),
f0a8e6de
HS		 308 CH_DEVICE(0x5414, 4),
309 CH_DEVICE(0x5415, 4),
0183aa62
HS		 310 CH_DEVICE(0x5480, 4),
311 CH_DEVICE(0x5481, 4),
312 CH_DEVICE(0x5482, 4),
313 CH_DEVICE(0x5483, 4),
314 CH_DEVICE(0x5484, 4),
315 CH_DEVICE(0x5485, 4),
56e03e51 316 CH_DEVICE(0x5486, 4),
91c04a9e
HS		 317 CH_DEVICE(0x5487, 4),
318 CH_DEVICE(0x5488, 4),
b8ff05a9
DM		 319 { 0, }
320};
321
16e47624 322#define FW4_FNAME "cxgb4/t4fw.bin"
0a57a536 323#define FW5_FNAME "cxgb4/t5fw.bin"
16e47624 324#define FW4_CFNAME "cxgb4/t4-config.txt"
0a57a536 325#define FW5_CFNAME "cxgb4/t5-config.txt"
b8ff05a9
DM		 326
327MODULE_DESCRIPTION(DRV_DESC);
328MODULE_AUTHOR("Chelsio Communications");
329MODULE_LICENSE("Dual BSD/GPL");
330MODULE_VERSION(DRV_VERSION);
331MODULE_DEVICE_TABLE(pci, cxgb4_pci_tbl);
16e47624 332MODULE_FIRMWARE(FW4_FNAME);
0a57a536 333MODULE_FIRMWARE(FW5_FNAME);
b8ff05a9 334
636f9d37
VP		 335/*
336 * Normally we're willing to become the firmware's Master PF but will be happy
337 * if another PF has already become the Master and initialized the adapter.
338 * Setting "force_init" will cause this driver to forcibly establish itself as
339 * the Master PF and initialize the adapter.
340 */
341static uint force_init;
342
343module_param(force_init, uint, 0644);
344MODULE_PARM_DESC(force_init, "Forcibly become Master PF and initialize adapter");
345
13ee15d3
VP		 346/*
347 * Normally if the firmware we connect to has Configuration File support, we
348 * use that and only fall back to the old Driver-based initialization if the
349 * Configuration File fails for some reason. If force_old_init is set, then
350 * we'll always use the old Driver-based initialization sequence.
351 */
352static uint force_old_init;
353
354module_param(force_old_init, uint, 0644);
355MODULE_PARM_DESC(force_old_init, "Force old initialization sequence");
356
b8ff05a9
DM		 357static int dflt_msg_enable = DFLT_MSG_ENABLE;
358
359module_param(dflt_msg_enable, int, 0644);
360MODULE_PARM_DESC(dflt_msg_enable, "Chelsio T4 default message enable bitmap");
361
362/*
363 * The driver uses the best interrupt scheme available on a platform in the
364 * order MSI-X, MSI, legacy INTx interrupts. This parameter determines which
365 * of these schemes the driver may consider as follows:
366 *
367 * msi = 2: choose from among all three options
368 * msi = 1: only consider MSI and INTx interrupts
369 * msi = 0: force INTx interrupts
370 */
371static int msi = 2;
372
373module_param(msi, int, 0644);
374MODULE_PARM_DESC(msi, "whether to use INTx (0), MSI (1) or MSI-X (2)");
375
376/*
377 * Queue interrupt hold-off timer values. Queues default to the first of these
378 * upon creation.
379 */
380static unsigned int intr_holdoff[SGE_NTIMERS - 1] = { 5, 10, 20, 50, 100 };
381
382module_param_array(intr_holdoff, uint, NULL, 0644);
383MODULE_PARM_DESC(intr_holdoff, "values for queue interrupt hold-off timers "
384 "0..4 in microseconds");
385
386static unsigned int intr_cnt[SGE_NCOUNTERS - 1] = { 4, 8, 16 };
387
388module_param_array(intr_cnt, uint, NULL, 0644);
389MODULE_PARM_DESC(intr_cnt,
390 "thresholds 1..3 for queue interrupt packet counters");
391
636f9d37
VP		 392/*
393 * Normally we tell the chip to deliver Ingress Packets into our DMA buffers
394 * offset by 2 bytes in order to have the IP headers line up on 4-byte
395 * boundaries. This is a requirement for many architectures which will throw
396 * a machine check fault if an attempt is made to access one of the 4-byte IP
397 * header fields on a non-4-byte boundary. And it's a major performance issue
398 * even on some architectures which allow it like some implementations of the
399 * x86 ISA. However, some architectures don't mind this and for some very
400 * edge-case performance sensitive applications (like forwarding large volumes
401 * of small packets), setting this DMA offset to 0 will decrease the number of
402 * PCI-E Bus transfers enough to measurably affect performance.
403 */
404static int rx_dma_offset = 2;
405
eb939922 406static bool vf_acls;
b8ff05a9
DM		 407
408#ifdef CONFIG_PCI_IOV
409module_param(vf_acls, bool, 0644);
410MODULE_PARM_DESC(vf_acls, "if set enable virtualization L2 ACL enforcement");
411
7d6727cf
SR		 412/* Configure the number of PCI-E Virtual Function which are to be instantiated
413 * on SR-IOV Capable Physical Functions.
0a57a536 414 */
7d6727cf 415static unsigned int num_vf[NUM_OF_PF_WITH_SRIOV];
b8ff05a9
DM		 416
417module_param_array(num_vf, uint, NULL, 0644);
7d6727cf 418MODULE_PARM_DESC(num_vf, "number of VFs for each of PFs 0-3");
b8ff05a9
DM		 419#endif
420
688848b1
AB		 421/* TX Queue select used to determine what algorithm to use for selecting TX
422 * queue. Select between the kernel provided function (select_queue=0) or user
423 * cxgb_select_queue function (select_queue=1)
424 *
425 * Default: select_queue=0
426 */
427static int select_queue;
428module_param(select_queue, int, 0644);
429MODULE_PARM_DESC(select_queue,
430 "Select between kernel provided method of selecting or driver method of selecting TX queue. Default is kernel method.");
431
13ee15d3
VP		 432/*
433 * The filter TCAM has a fixed portion and a variable portion. The fixed
434 * portion can match on source/destination IP IPv4/IPv6 addresses and TCP/UDP
435 * ports. The variable portion is 36 bits which can include things like Exact
436 * Match MAC Index (9 bits), Ether Type (16 bits), IP Protocol (8 bits),
437 * [Inner] VLAN Tag (17 bits), etc. which, if all were somehow selected, would
438 * far exceed the 36-bit budget for this "compressed" header portion of the
439 * filter. Thus, we have a scarce resource which must be carefully managed.
440 *
441 * By default we set this up to mostly match the set of filter matching
442 * capabilities of T3 but with accommodations for some of T4's more
443 * interesting features:
444 *
445 * { IP Fragment (1), MPS Match Type (3), IP Protocol (8),
446 * [Inner] VLAN (17), Port (3), FCoE (1) }
447 */
448enum {
449 TP_VLAN_PRI_MAP_DEFAULT = HW_TPL_FR_MT_PR_IV_P_FC,
450 TP_VLAN_PRI_MAP_FIRST = FCOE_SHIFT,
451 TP_VLAN_PRI_MAP_LAST = FRAGMENTATION_SHIFT,
452};
453
454static unsigned int tp_vlan_pri_map = TP_VLAN_PRI_MAP_DEFAULT;
455
f2b7e78d
VP		 456module_param(tp_vlan_pri_map, uint, 0644);
457MODULE_PARM_DESC(tp_vlan_pri_map, "global compressed filter configuration");
458
b8ff05a9
DM		 459static struct dentry *cxgb4_debugfs_root;
460
461static LIST_HEAD(adapter_list);
462static DEFINE_MUTEX(uld_mutex);
01bcca68
VP		 463/* Adapter list to be accessed from atomic context */
464static LIST_HEAD(adap_rcu_list);
465static DEFINE_SPINLOCK(adap_rcu_lock);
b8ff05a9
DM		 466static struct cxgb4_uld_info ulds[CXGB4_ULD_MAX];
467static const char *uld_str[] = { "RDMA", "iSCSI" };
468
469static void link_report(struct net_device *dev)
470{
471 if (!netif_carrier_ok(dev))
472 netdev_info(dev, "link down\n");
473 else {
474 static const char *fc[] = { "no", "Rx", "Tx", "Tx/Rx" };
475
476 const char *s = "10Mbps";
477 const struct port_info *p = netdev_priv(dev);
478
479 switch (p->link_cfg.speed) {
e8b39015 480 case 10000:
b8ff05a9
DM		 481 s = "10Gbps";
482 break;
e8b39015 483 case 1000:
b8ff05a9
DM		 484 s = "1000Mbps";
485 break;
e8b39015 486 case 100:
b8ff05a9
DM		 487 s = "100Mbps";
488 break;
e8b39015 489 case 40000:
72aca4bf
KS		 490 s = "40Gbps";
491 break;
b8ff05a9
DM		 492 }
493
494 netdev_info(dev, "link up, %s, full-duplex, %s PAUSE\n", s,
495 fc[p->link_cfg.fc]);
496 }
497}
498
688848b1
AB		 499#ifdef CONFIG_CHELSIO_T4_DCB
500/* Set up/tear down Data Center Bridging Priority mapping for a net device. */
501static void dcb_tx_queue_prio_enable(struct net_device *dev, int enable)
502{
503 struct port_info *pi = netdev_priv(dev);
504 struct adapter *adap = pi->adapter;
505 struct sge_eth_txq *txq = &adap->sge.ethtxq[pi->first_qset];
506 int i;
507
508 /* We use a simple mapping of Port TX Queue Index to DCB
509 * Priority when we're enabling DCB.
510 */
511 for (i = 0; i < pi->nqsets; i++, txq++) {
512 u32 name, value;
513 int err;
514
515 name = (FW_PARAMS_MNEM(FW_PARAMS_MNEM_DMAQ) |
516 FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DMAQ_EQ_DCBPRIO_ETH) |
517 FW_PARAMS_PARAM_YZ(txq->q.cntxt_id));
518 value = enable ? i : 0xffffffff;
519
520 /* Since we can be called while atomic (from "interrupt
521 * level") we need to issue the Set Parameters Commannd
522 * without sleeping (timeout < 0).
523 */
524 err = t4_set_params_nosleep(adap, adap->mbox, adap->fn, 0, 1,
525 &name, &value);
526
527 if (err)
528 dev_err(adap->pdev_dev,
529 "Can't %s DCB Priority on port %d, TX Queue %d: err=%d\n",
530 enable ? "set" : "unset", pi->port_id, i, -err);
10b00466
AB		 531 else
532 txq->dcb_prio = value;
688848b1
AB		 533 }
534}
535#endif /* CONFIG_CHELSIO_T4_DCB */
536
b8ff05a9
DM		 537void t4_os_link_changed(struct adapter *adapter, int port_id, int link_stat)
538{
539 struct net_device *dev = adapter->port[port_id];
540
541 /* Skip changes from disabled ports. */
542 if (netif_running(dev) && link_stat != netif_carrier_ok(dev)) {
543 if (link_stat)
544 netif_carrier_on(dev);
688848b1
AB		 545 else {
546#ifdef CONFIG_CHELSIO_T4_DCB
547 cxgb4_dcb_state_init(dev);
548 dcb_tx_queue_prio_enable(dev, false);
549#endif /* CONFIG_CHELSIO_T4_DCB */
b8ff05a9 550 netif_carrier_off(dev);
688848b1 551 }
b8ff05a9
DM		 552
553 link_report(dev);
554 }
555}
556
557void t4_os_portmod_changed(const struct adapter *adap, int port_id)
558{
559 static const char *mod_str[] = {
a0881cab 560 NULL, "LR", "SR", "ER", "passive DA", "active DA", "LRM"
b8ff05a9
DM		 561 };
562
563 const struct net_device *dev = adap->port[port_id];
564 const struct port_info *pi = netdev_priv(dev);
565
566 if (pi->mod_type == FW_PORT_MOD_TYPE_NONE)
567 netdev_info(dev, "port module unplugged\n");
a0881cab 568 else if (pi->mod_type < ARRAY_SIZE(mod_str))
b8ff05a9
DM		 569 netdev_info(dev, "%s module inserted\n", mod_str[pi->mod_type]);
570}
571
572/*
573 * Configure the exact and hash address filters to handle a port's multicast
574 * and secondary unicast MAC addresses.
575 */
576static int set_addr_filters(const struct net_device *dev, bool sleep)
577{
578 u64 mhash = 0;
579 u64 uhash = 0;
580 bool free = true;
581 u16 filt_idx[7];
582 const u8 *addr[7];
583 int ret, naddr = 0;
b8ff05a9
DM		 584 const struct netdev_hw_addr *ha;
585 int uc_cnt = netdev_uc_count(dev);
4a35ecf8 586 int mc_cnt = netdev_mc_count(dev);
b8ff05a9 587 const struct port_info *pi = netdev_priv(dev);
060e0c75 588 unsigned int mb = pi->adapter->fn;
b8ff05a9
DM		 589
590 /* first do the secondary unicast addresses */
591 netdev_for_each_uc_addr(ha, dev) {
592 addr[naddr++] = ha->addr;
593 if (--uc_cnt == 0 || naddr >= ARRAY_SIZE(addr)) {
060e0c75 594 ret = t4_alloc_mac_filt(pi->adapter, mb, pi->viid, free,
b8ff05a9
DM		 595 naddr, addr, filt_idx, &uhash, sleep);
596 if (ret < 0)
597 return ret;
598
599 free = false;
600 naddr = 0;
601 }
602 }
603
604 /* next set up the multicast addresses */
4a35ecf8
DM		 605 netdev_for_each_mc_addr(ha, dev) {
606 addr[naddr++] = ha->addr;
607 if (--mc_cnt == 0 || naddr >= ARRAY_SIZE(addr)) {
060e0c75 608 ret = t4_alloc_mac_filt(pi->adapter, mb, pi->viid, free,
b8ff05a9
DM		 609 naddr, addr, filt_idx, &mhash, sleep);
610 if (ret < 0)
611 return ret;
612
613 free = false;
614 naddr = 0;
615 }
616 }
617
060e0c75 618 return t4_set_addr_hash(pi->adapter, mb, pi->viid, uhash != 0,
b8ff05a9
DM		 619 uhash | mhash, sleep);
620}
621
3069ee9b
VP		 622int dbfifo_int_thresh = 10; /* 10 == 640 entry threshold */
623module_param(dbfifo_int_thresh, int, 0644);
624MODULE_PARM_DESC(dbfifo_int_thresh, "doorbell fifo interrupt threshold");
625
404d9e3f
VP		 626/*
627 * usecs to sleep while draining the dbfifo
628 */
629static int dbfifo_drain_delay = 1000;
3069ee9b
VP		 630module_param(dbfifo_drain_delay, int, 0644);
631MODULE_PARM_DESC(dbfifo_drain_delay,
632 "usecs to sleep while draining the dbfifo");
633
b8ff05a9
DM		 634/*
635 * Set Rx properties of a port, such as promiscruity, address filters, and MTU.
636 * If @mtu is -1 it is left unchanged.
637 */
638static int set_rxmode(struct net_device *dev, int mtu, bool sleep_ok)
639{
640 int ret;
641 struct port_info *pi = netdev_priv(dev);
642
643 ret = set_addr_filters(dev, sleep_ok);
644 if (ret == 0)
060e0c75 645 ret = t4_set_rxmode(pi->adapter, pi->adapter->fn, pi->viid, mtu,
b8ff05a9 646 (dev->flags & IFF_PROMISC) ? 1 : 0,
f8f5aafa 647 (dev->flags & IFF_ALLMULTI) ? 1 : 0, 1, -1,
b8ff05a9
DM		 648 sleep_ok);
649 return ret;
650}
651
652/**
653 * link_start - enable a port
654 * @dev: the port to enable
655 *
656 * Performs the MAC and PHY actions needed to enable a port.
657 */
658static int link_start(struct net_device *dev)
659{
660 int ret;
661 struct port_info *pi = netdev_priv(dev);
060e0c75 662 unsigned int mb = pi->adapter->fn;
b8ff05a9
DM		 663
664 /*
665 * We do not set address filters and promiscuity here, the stack does
666 * that step explicitly.
667 */
060e0c75 668 ret = t4_set_rxmode(pi->adapter, mb, pi->viid, dev->mtu, -1, -1, -1,
f646968f 669 !!(dev->features & NETIF_F_HW_VLAN_CTAG_RX), true);
b8ff05a9 670 if (ret == 0) {
060e0c75 671 ret = t4_change_mac(pi->adapter, mb, pi->viid,
b8ff05a9 672 pi->xact_addr_filt, dev->dev_addr, true,
b6bd29e7 673 true);
b8ff05a9
DM		 674 if (ret >= 0) {
675 pi->xact_addr_filt = ret;
676 ret = 0;
677 }
678 }
679 if (ret == 0)
060e0c75
DM		 680 ret = t4_link_start(pi->adapter, mb, pi->tx_chan,
681 &pi->link_cfg);
30f00847
AB		 682 if (ret == 0) {
683 local_bh_disable();
688848b1
AB		 684 ret = t4_enable_vi_params(pi->adapter, mb, pi->viid, true,
685 true, CXGB4_DCB_ENABLED);
30f00847
AB		 686 local_bh_enable();
687 }
688848b1 688
b8ff05a9
DM		 689 return ret;
690}
691
688848b1
AB		 692int cxgb4_dcb_enabled(const struct net_device *dev)
693{
694#ifdef CONFIG_CHELSIO_T4_DCB
695 struct port_info *pi = netdev_priv(dev);
696
3bb06261
AB		 697 if (!pi->dcb.enabled)
698 return 0;
699
700 return ((pi->dcb.state == CXGB4_DCB_STATE_FW_ALLSYNCED) ||
701 (pi->dcb.state == CXGB4_DCB_STATE_HOST));
688848b1
AB		 702#else
703 return 0;
704#endif
705}
706EXPORT_SYMBOL(cxgb4_dcb_enabled);
707
708#ifdef CONFIG_CHELSIO_T4_DCB
709/* Handle a Data Center Bridging update message from the firmware. */
710static void dcb_rpl(struct adapter *adap, const struct fw_port_cmd *pcmd)
711{
712 int port = FW_PORT_CMD_PORTID_GET(ntohl(pcmd->op_to_portid));
713 struct net_device *dev = adap->port[port];
714 int old_dcb_enabled = cxgb4_dcb_enabled(dev);
715 int new_dcb_enabled;
716
717 cxgb4_dcb_handle_fw_update(adap, pcmd);
718 new_dcb_enabled = cxgb4_dcb_enabled(dev);
719
720 /* If the DCB has become enabled or disabled on the port then we're
721 * going to need to set up/tear down DCB Priority parameters for the
722 * TX Queues associated with the port.
723 */
724 if (new_dcb_enabled != old_dcb_enabled)
725 dcb_tx_queue_prio_enable(dev, new_dcb_enabled);
726}
727#endif /* CONFIG_CHELSIO_T4_DCB */
728
f2b7e78d
VP		 729/* Clear a filter and release any of its resources that we own. This also
730 * clears the filter's "pending" status.
731 */
732static void clear_filter(struct adapter *adap, struct filter_entry *f)
733{
734 /* If the new or old filter have loopback rewriteing rules then we'll
735 * need to free any existing Layer Two Table (L2T) entries of the old
736 * filter rule. The firmware will handle freeing up any Source MAC
737 * Table (SMT) entries used for rewriting Source MAC Addresses in
738 * loopback rules.
739 */
740 if (f->l2t)
741 cxgb4_l2t_release(f->l2t);
742
743 /* The zeroing of the filter rule below clears the filter valid,
744 * pending, locked flags, l2t pointer, etc. so it's all we need for
745 * this operation.
746 */
747 memset(f, 0, sizeof(*f));
748}
749
750/* Handle a filter write/deletion reply.
751 */
752static void filter_rpl(struct adapter *adap, const struct cpl_set_tcb_rpl *rpl)
753{
754 unsigned int idx = GET_TID(rpl);
755 unsigned int nidx = idx - adap->tids.ftid_base;
756 unsigned int ret;
757 struct filter_entry *f;
758
759 if (idx >= adap->tids.ftid_base && nidx <
760 (adap->tids.nftids + adap->tids.nsftids)) {
761 idx = nidx;
762 ret = GET_TCB_COOKIE(rpl->cookie);
763 f = &adap->tids.ftid_tab[idx];
764
765 if (ret == FW_FILTER_WR_FLT_DELETED) {
766 /* Clear the filter when we get confirmation from the
767 * hardware that the filter has been deleted.
768 */
769 clear_filter(adap, f);
770 } else if (ret == FW_FILTER_WR_SMT_TBL_FULL) {
771 dev_err(adap->pdev_dev, "filter %u setup failed due to full SMT\n",
772 idx);
773 clear_filter(adap, f);
774 } else if (ret == FW_FILTER_WR_FLT_ADDED) {
775 f->smtidx = (be64_to_cpu(rpl->oldval) >> 24) & 0xff;
776 f->pending = 0; /* asynchronous setup completed */
777 f->valid = 1;
778 } else {
779 /* Something went wrong. Issue a warning about the
780 * problem and clear everything out.
781 */
782 dev_err(adap->pdev_dev, "filter %u setup failed with error %u\n",
783 idx, ret);
784 clear_filter(adap, f);
785 }
786 }
787}
788
789/* Response queue handler for the FW event queue.
b8ff05a9
DM		 790 */
791static int fwevtq_handler(struct sge_rspq *q, const __be64 *rsp,
792 const struct pkt_gl *gl)
793{
794 u8 opcode = ((const struct rss_header *)rsp)->opcode;
795
796 rsp++; /* skip RSS header */
b407a4a9
VP		 797
798 /* FW can send EGR_UPDATEs encapsulated in a CPL_FW4_MSG.
799 */
800 if (unlikely(opcode == CPL_FW4_MSG &&
801 ((const struct cpl_fw4_msg *)rsp)->type == FW_TYPE_RSSCPL)) {
802 rsp++;
803 opcode = ((const struct rss_header *)rsp)->opcode;
804 rsp++;
805 if (opcode != CPL_SGE_EGR_UPDATE) {
806 dev_err(q->adap->pdev_dev, "unexpected FW4/CPL %#x on FW event queue\n"
807 , opcode);
808 goto out;
809 }
810 }
811
b8ff05a9
DM		 812 if (likely(opcode == CPL_SGE_EGR_UPDATE)) {
813 const struct cpl_sge_egr_update *p = (void *)rsp;
814 unsigned int qid = EGR_QID(ntohl(p->opcode_qid));
e46dab4d 815 struct sge_txq *txq;
b8ff05a9 816
e46dab4d 817 txq = q->adap->sge.egr_map[qid - q->adap->sge.egr_start];
b8ff05a9 818 txq->restarts++;
e46dab4d 819 if ((u8 *)txq < (u8 *)q->adap->sge.ofldtxq) {
b8ff05a9
DM		 820 struct sge_eth_txq *eq;
821
822 eq = container_of(txq, struct sge_eth_txq, q);
823 netif_tx_wake_queue(eq->txq);
824 } else {
825 struct sge_ofld_txq *oq;
826
827 oq = container_of(txq, struct sge_ofld_txq, q);
828 tasklet_schedule(&oq->qresume_tsk);
829 }
830 } else if (opcode == CPL_FW6_MSG || opcode == CPL_FW4_MSG) {
831 const struct cpl_fw6_msg *p = (void *)rsp;
832
688848b1
AB		 833#ifdef CONFIG_CHELSIO_T4_DCB
834 const struct fw_port_cmd *pcmd = (const void *)p->data;
835 unsigned int cmd = FW_CMD_OP_GET(ntohl(pcmd->op_to_portid));
836 unsigned int action =
837 FW_PORT_CMD_ACTION_GET(ntohl(pcmd->action_to_len16));
838
839 if (cmd == FW_PORT_CMD &&
840 action == FW_PORT_ACTION_GET_PORT_INFO) {
841 int port = FW_PORT_CMD_PORTID_GET(
842 be32_to_cpu(pcmd->op_to_portid));
843 struct net_device *dev = q->adap->port[port];
844 int state_input = ((pcmd->u.info.dcbxdis_pkd &
845 FW_PORT_CMD_DCBXDIS)
846 ? CXGB4_DCB_INPUT_FW_DISABLED
847 : CXGB4_DCB_INPUT_FW_ENABLED);
848
849 cxgb4_dcb_state_fsm(dev, state_input);
850 }
851
852 if (cmd == FW_PORT_CMD &&
853 action == FW_PORT_ACTION_L2_DCB_CFG)
854 dcb_rpl(q->adap, pcmd);
855 else
856#endif
857 if (p->type == 0)
858 t4_handle_fw_rpl(q->adap, p->data);
b8ff05a9
DM		 859 } else if (opcode == CPL_L2T_WRITE_RPL) {
860 const struct cpl_l2t_write_rpl *p = (void *)rsp;
861
862 do_l2t_write_rpl(q->adap, p);
f2b7e78d
VP		 863 } else if (opcode == CPL_SET_TCB_RPL) {
864 const struct cpl_set_tcb_rpl *p = (void *)rsp;
865
866 filter_rpl(q->adap, p);
b8ff05a9
DM		 867 } else
868 dev_err(q->adap->pdev_dev,
869 "unexpected CPL %#x on FW event queue\n", opcode);
b407a4a9 870out:
b8ff05a9
DM		 871 return 0;
872}
873
874/**
875 * uldrx_handler - response queue handler for ULD queues
876 * @q: the response queue that received the packet
877 * @rsp: the response queue descriptor holding the offload message
878 * @gl: the gather list of packet fragments
879 *
880 * Deliver an ingress offload packet to a ULD. All processing is done by
881 * the ULD, we just maintain statistics.
882 */
883static int uldrx_handler(struct sge_rspq *q, const __be64 *rsp,
884 const struct pkt_gl *gl)
885{
886 struct sge_ofld_rxq *rxq = container_of(q, struct sge_ofld_rxq, rspq);
887
b407a4a9
VP		 888 /* FW can send CPLs encapsulated in a CPL_FW4_MSG.
889 */
890 if (((const struct rss_header *)rsp)->opcode == CPL_FW4_MSG &&
891 ((const struct cpl_fw4_msg *)(rsp + 1))->type == FW_TYPE_RSSCPL)
892 rsp += 2;
893
b8ff05a9
DM		 894 if (ulds[q->uld].rx_handler(q->adap->uld_handle[q->uld], rsp, gl)) {
895 rxq->stats.nomem++;
896 return -1;
897 }
898 if (gl == NULL)
899 rxq->stats.imm++;
900 else if (gl == CXGB4_MSG_AN)
901 rxq->stats.an++;
902 else
903 rxq->stats.pkts++;
904 return 0;
905}
906
907static void disable_msi(struct adapter *adapter)
908{
909 if (adapter->flags & USING_MSIX) {
910 pci_disable_msix(adapter->pdev);
911 adapter->flags &= ~USING_MSIX;
912 } else if (adapter->flags & USING_MSI) {
913 pci_disable_msi(adapter->pdev);
914 adapter->flags &= ~USING_MSI;
915 }
916}
917
918/*
919 * Interrupt handler for non-data events used with MSI-X.
920 */
921static irqreturn_t t4_nondata_intr(int irq, void *cookie)
922{
923 struct adapter *adap = cookie;
924
925 u32 v = t4_read_reg(adap, MYPF_REG(PL_PF_INT_CAUSE));
926 if (v & PFSW) {
927 adap->swintr = 1;
928 t4_write_reg(adap, MYPF_REG(PL_PF_INT_CAUSE), v);
929 }
930 t4_slow_intr_handler(adap);
931 return IRQ_HANDLED;
932}
933
934/*
935 * Name the MSI-X interrupts.
936 */
937static void name_msix_vecs(struct adapter *adap)
938{
ba27816c 939 int i, j, msi_idx = 2, n = sizeof(adap->msix_info[0].desc);
b8ff05a9
DM		 940
941 /* non-data interrupts */
b1a3c2b6 942 snprintf(adap->msix_info[0].desc, n, "%s", adap->port[0]->name);
b8ff05a9
DM		 943
944 /* FW events */
b1a3c2b6
DM		 945 snprintf(adap->msix_info[1].desc, n, "%s-FWeventq",
946 adap->port[0]->name);
b8ff05a9
DM		 947
948 /* Ethernet queues */
949 for_each_port(adap, j) {
950 struct net_device *d = adap->port[j];
951 const struct port_info *pi = netdev_priv(d);
952
ba27816c 953 for (i = 0; i < pi->nqsets; i++, msi_idx++)
b8ff05a9
DM		 954 snprintf(adap->msix_info[msi_idx].desc, n, "%s-Rx%d",
955 d->name, i);
b8ff05a9
DM		 956 }
957
958 /* offload queues */
ba27816c
DM		 959 for_each_ofldrxq(&adap->sge, i)
960 snprintf(adap->msix_info[msi_idx++].desc, n, "%s-ofld%d",
b1a3c2b6 961 adap->port[0]->name, i);
ba27816c
DM		 962
963 for_each_rdmarxq(&adap->sge, i)
964 snprintf(adap->msix_info[msi_idx++].desc, n, "%s-rdma%d",
b1a3c2b6 965 adap->port[0]->name, i);
cf38be6d
HS		 966
967 for_each_rdmaciq(&adap->sge, i)
968 snprintf(adap->msix_info[msi_idx++].desc, n, "%s-rdma-ciq%d",
969 adap->port[0]->name, i);
b8ff05a9
DM		 970}
971
972static int request_msix_queue_irqs(struct adapter *adap)
973{
974 struct sge *s = &adap->sge;
cf38be6d
HS		 975 int err, ethqidx, ofldqidx = 0, rdmaqidx = 0, rdmaciqqidx = 0;
976 int msi_index = 2;
b8ff05a9
DM		 977
978 err = request_irq(adap->msix_info[1].vec, t4_sge_intr_msix, 0,
979 adap->msix_info[1].desc, &s->fw_evtq);
980 if (err)
981 return err;
982
983 for_each_ethrxq(s, ethqidx) {
404d9e3f
VP		 984 err = request_irq(adap->msix_info[msi_index].vec,
985 t4_sge_intr_msix, 0,
986 adap->msix_info[msi_index].desc,
b8ff05a9
DM		 987 &s->ethrxq[ethqidx].rspq);
988 if (err)
989 goto unwind;
404d9e3f 990 msi_index++;
b8ff05a9
DM		 991 }
992 for_each_ofldrxq(s, ofldqidx) {
404d9e3f
VP		 993 err = request_irq(adap->msix_info[msi_index].vec,
994 t4_sge_intr_msix, 0,
995 adap->msix_info[msi_index].desc,
b8ff05a9
DM		 996 &s->ofldrxq[ofldqidx].rspq);
997 if (err)
998 goto unwind;
404d9e3f 999 msi_index++;
b8ff05a9
DM		 1000 }
1001 for_each_rdmarxq(s, rdmaqidx) {
404d9e3f
VP		 1002 err = request_irq(adap->msix_info[msi_index].vec,
1003 t4_sge_intr_msix, 0,
1004 adap->msix_info[msi_index].desc,
b8ff05a9
DM		 1005 &s->rdmarxq[rdmaqidx].rspq);
1006 if (err)
1007 goto unwind;
404d9e3f 1008 msi_index++;
b8ff05a9 1009 }
cf38be6d
HS		 1010 for_each_rdmaciq(s, rdmaciqqidx) {
1011 err = request_irq(adap->msix_info[msi_index].vec,
1012 t4_sge_intr_msix, 0,
1013 adap->msix_info[msi_index].desc,
1014 &s->rdmaciq[rdmaciqqidx].rspq);
1015 if (err)
1016 goto unwind;
1017 msi_index++;
1018 }
b8ff05a9
DM		 1019 return 0;
1020
1021unwind:
cf38be6d
HS		 1022 while (--rdmaciqqidx >= 0)
1023 free_irq(adap->msix_info[--msi_index].vec,
1024 &s->rdmaciq[rdmaciqqidx].rspq);
b8ff05a9 1025 while (--rdmaqidx >= 0)
404d9e3f 1026 free_irq(adap->msix_info[--msi_index].vec,
b8ff05a9
DM		 1027 &s->rdmarxq[rdmaqidx].rspq);
1028 while (--ofldqidx >= 0)
404d9e3f 1029 free_irq(adap->msix_info[--msi_index].vec,
b8ff05a9
DM		 1030 &s->ofldrxq[ofldqidx].rspq);
1031 while (--ethqidx >= 0)
404d9e3f
VP		 1032 free_irq(adap->msix_info[--msi_index].vec,
1033 &s->ethrxq[ethqidx].rspq);
b8ff05a9
DM		 1034 free_irq(adap->msix_info[1].vec, &s->fw_evtq);
1035 return err;
1036}
1037
1038static void free_msix_queue_irqs(struct adapter *adap)
1039{
404d9e3f 1040 int i, msi_index = 2;
b8ff05a9
DM		 1041 struct sge *s = &adap->sge;
1042
1043 free_irq(adap->msix_info[1].vec, &s->fw_evtq);
1044 for_each_ethrxq(s, i)
404d9e3f 1045 free_irq(adap->msix_info[msi_index++].vec, &s->ethrxq[i].rspq);
b8ff05a9 1046 for_each_ofldrxq(s, i)
404d9e3f 1047 free_irq(adap->msix_info[msi_index++].vec, &s->ofldrxq[i].rspq);
b8ff05a9 1048 for_each_rdmarxq(s, i)
404d9e3f 1049 free_irq(adap->msix_info[msi_index++].vec, &s->rdmarxq[i].rspq);
cf38be6d
HS		 1050 for_each_rdmaciq(s, i)
1051 free_irq(adap->msix_info[msi_index++].vec, &s->rdmaciq[i].rspq);
b8ff05a9
DM		 1052}
1053
671b0060
DM		 1054/**
1055 * write_rss - write the RSS table for a given port
1056 * @pi: the port
1057 * @queues: array of queue indices for RSS
1058 *
1059 * Sets up the portion of the HW RSS table for the port's VI to distribute
1060 * packets to the Rx queues in @queues.
1061 */
1062static int write_rss(const struct port_info *pi, const u16 *queues)
1063{
1064 u16 *rss;
1065 int i, err;
1066 const struct sge_eth_rxq *q = &pi->adapter->sge.ethrxq[pi->first_qset];
1067
1068 rss = kmalloc(pi->rss_size * sizeof(u16), GFP_KERNEL);
1069 if (!rss)
1070 return -ENOMEM;
1071
1072 /* map the queue indices to queue ids */
1073 for (i = 0; i < pi->rss_size; i++, queues++)
1074 rss[i] = q[*queues].rspq.abs_id;
1075
060e0c75
DM		 1076 err = t4_config_rss_range(pi->adapter, pi->adapter->fn, pi->viid, 0,
1077 pi->rss_size, rss, pi->rss_size);
671b0060
DM		 1078 kfree(rss);
1079 return err;
1080}
1081
b8ff05a9
DM		 1082/**
1083 * setup_rss - configure RSS
1084 * @adap: the adapter
1085 *
671b0060 1086 * Sets up RSS for each port.
b8ff05a9
DM		 1087 */
1088static int setup_rss(struct adapter *adap)
1089{
671b0060 1090 int i, err;
b8ff05a9
DM		 1091
1092 for_each_port(adap, i) {
1093 const struct port_info *pi = adap2pinfo(adap, i);
b8ff05a9 1094
671b0060 1095 err = write_rss(pi, pi->rss);
b8ff05a9
DM		 1096 if (err)
1097 return err;
1098 }
1099 return 0;
1100}
1101
e46dab4d
DM		 1102/*
1103 * Return the channel of the ingress queue with the given qid.
1104 */
1105static unsigned int rxq_to_chan(const struct sge *p, unsigned int qid)
1106{
1107 qid -= p->ingr_start;
1108 return netdev2pinfo(p->ingr_map[qid]->netdev)->tx_chan;
1109}
1110
b8ff05a9
DM		 1111/*
1112 * Wait until all NAPI handlers are descheduled.
1113 */
1114static void quiesce_rx(struct adapter *adap)
1115{
1116 int i;
1117
1118 for (i = 0; i < ARRAY_SIZE(adap->sge.ingr_map); i++) {
1119 struct sge_rspq *q = adap->sge.ingr_map[i];
1120
1121 if (q && q->handler)
1122 napi_disable(&q->napi);
1123 }
1124}
1125
1126/*
1127 * Enable NAPI scheduling and interrupt generation for all Rx queues.
1128 */
1129static void enable_rx(struct adapter *adap)
1130{
1131 int i;
1132
1133 for (i = 0; i < ARRAY_SIZE(adap->sge.ingr_map); i++) {
1134 struct sge_rspq *q = adap->sge.ingr_map[i];
1135
1136 if (!q)
1137 continue;
1138 if (q->handler)
1139 napi_enable(&q->napi);
1140 /* 0-increment GTS to start the timer and enable interrupts */
1141 t4_write_reg(adap, MYPF_REG(SGE_PF_GTS),
1142 SEINTARM(q->intr_params) |
1143 INGRESSQID(q->cntxt_id));
1144 }
1145}
1146
1147/**
1148 * setup_sge_queues - configure SGE Tx/Rx/response queues
1149 * @adap: the adapter
1150 *
1151 * Determines how many sets of SGE queues to use and initializes them.
1152 * We support multiple queue sets per port if we have MSI-X, otherwise
1153 * just one queue set per port.
1154 */
1155static int setup_sge_queues(struct adapter *adap)
1156{
1157 int err, msi_idx, i, j;
1158 struct sge *s = &adap->sge;
1159
1160 bitmap_zero(s->starving_fl, MAX_EGRQ);
1161 bitmap_zero(s->txq_maperr, MAX_EGRQ);
1162
1163 if (adap->flags & USING_MSIX)
1164 msi_idx = 1; /* vector 0 is for non-queue interrupts */
1165 else {
1166 err = t4_sge_alloc_rxq(adap, &s->intrq, false, adap->port[0], 0,
1167 NULL, NULL);
1168 if (err)
1169 return err;
1170 msi_idx = -((int)s->intrq.abs_id + 1);
1171 }
1172
1173 err = t4_sge_alloc_rxq(adap, &s->fw_evtq, true, adap->port[0],
1174 msi_idx, NULL, fwevtq_handler);
1175 if (err) {
1176freeout: t4_free_sge_resources(adap);
1177 return err;
1178 }
1179
1180 for_each_port(adap, i) {
1181 struct net_device *dev = adap->port[i];
1182 struct port_info *pi = netdev_priv(dev);
1183 struct sge_eth_rxq *q = &s->ethrxq[pi->first_qset];
1184 struct sge_eth_txq *t = &s->ethtxq[pi->first_qset];
1185
1186 for (j = 0; j < pi->nqsets; j++, q++) {
1187 if (msi_idx > 0)
1188 msi_idx++;
1189 err = t4_sge_alloc_rxq(adap, &q->rspq, false, dev,
1190 msi_idx, &q->fl,
1191 t4_ethrx_handler);
1192 if (err)
1193 goto freeout;
1194 q->rspq.idx = j;
1195 memset(&q->stats, 0, sizeof(q->stats));
1196 }
1197 for (j = 0; j < pi->nqsets; j++, t++) {
1198 err = t4_sge_alloc_eth_txq(adap, t, dev,
1199 netdev_get_tx_queue(dev, j),
1200 s->fw_evtq.cntxt_id);
1201 if (err)
1202 goto freeout;
1203 }
1204 }
1205
1206 j = s->ofldqsets / adap->params.nports; /* ofld queues per channel */
1207 for_each_ofldrxq(s, i) {
1208 struct sge_ofld_rxq *q = &s->ofldrxq[i];
1209 struct net_device *dev = adap->port[i / j];
1210
1211 if (msi_idx > 0)
1212 msi_idx++;
1213 err = t4_sge_alloc_rxq(adap, &q->rspq, false, dev, msi_idx,
cf38be6d
HS		 1214 q->fl.size ? &q->fl : NULL,
1215 uldrx_handler);
b8ff05a9
DM		 1216 if (err)
1217 goto freeout;
1218 memset(&q->stats, 0, sizeof(q->stats));
1219 s->ofld_rxq[i] = q->rspq.abs_id;
1220 err = t4_sge_alloc_ofld_txq(adap, &s->ofldtxq[i], dev,
1221 s->fw_evtq.cntxt_id);
1222 if (err)
1223 goto freeout;
1224 }
1225
1226 for_each_rdmarxq(s, i) {
1227 struct sge_ofld_rxq *q = &s->rdmarxq[i];
1228
1229 if (msi_idx > 0)
1230 msi_idx++;
1231 err = t4_sge_alloc_rxq(adap, &q->rspq, false, adap->port[i],
cf38be6d
HS		 1232 msi_idx, q->fl.size ? &q->fl : NULL,
1233 uldrx_handler);
b8ff05a9
DM		 1234 if (err)
1235 goto freeout;
1236 memset(&q->stats, 0, sizeof(q->stats));
1237 s->rdma_rxq[i] = q->rspq.abs_id;
1238 }
1239
cf38be6d
HS		 1240 for_each_rdmaciq(s, i) {
1241 struct sge_ofld_rxq *q = &s->rdmaciq[i];
1242
1243 if (msi_idx > 0)
1244 msi_idx++;
1245 err = t4_sge_alloc_rxq(adap, &q->rspq, false, adap->port[i],
1246 msi_idx, q->fl.size ? &q->fl : NULL,
1247 uldrx_handler);
1248 if (err)
1249 goto freeout;
1250 memset(&q->stats, 0, sizeof(q->stats));
1251 s->rdma_ciq[i] = q->rspq.abs_id;
1252 }
1253
b8ff05a9
DM		 1254 for_each_port(adap, i) {
1255 /*
1256 * Note that ->rdmarxq[i].rspq.cntxt_id below is 0 if we don't
1257 * have RDMA queues, and that's the right value.
1258 */
1259 err = t4_sge_alloc_ctrl_txq(adap, &s->ctrlq[i], adap->port[i],
1260 s->fw_evtq.cntxt_id,
1261 s->rdmarxq[i].rspq.cntxt_id);
1262 if (err)
1263 goto freeout;
1264 }
1265
9bb59b96
HS		 1266 t4_write_reg(adap, is_t4(adap->params.chip) ?
1267 MPS_TRC_RSS_CONTROL :
1268 MPS_T5_TRC_RSS_CONTROL,
b8ff05a9
DM		 1269 RSSCONTROL(netdev2pinfo(adap->port[0])->tx_chan) |
1270 QUEUENUMBER(s->ethrxq[0].rspq.abs_id));
1271 return 0;
1272}
1273
b8ff05a9
DM		 1274/*
1275 * Allocate a chunk of memory using kmalloc or, if that fails, vmalloc.
1276 * The allocated memory is cleared.
1277 */
1278void *t4_alloc_mem(size_t size)
1279{
8be04b93 1280 void *p = kzalloc(size, GFP_KERNEL | __GFP_NOWARN);
b8ff05a9
DM		 1281
1282 if (!p)
89bf67f1 1283 p = vzalloc(size);
b8ff05a9
DM		 1284 return p;
1285}
1286
1287/*
1288 * Free memory allocated through alloc_mem().
1289 */
31b9c19b 1290static void t4_free_mem(void *addr)
b8ff05a9
DM		 1291{
1292 if (is_vmalloc_addr(addr))
1293 vfree(addr);
1294 else
1295 kfree(addr);
1296}
1297
f2b7e78d
VP		 1298/* Send a Work Request to write the filter at a specified index. We construct
1299 * a Firmware Filter Work Request to have the work done and put the indicated
1300 * filter into "pending" mode which will prevent any further actions against
1301 * it till we get a reply from the firmware on the completion status of the
1302 * request.
1303 */
1304static int set_filter_wr(struct adapter *adapter, int fidx)
1305{
1306 struct filter_entry *f = &adapter->tids.ftid_tab[fidx];
1307 struct sk_buff *skb;
1308 struct fw_filter_wr *fwr;
1309 unsigned int ftid;
1310
1311 /* If the new filter requires loopback Destination MAC and/or VLAN
1312 * rewriting then we need to allocate a Layer 2 Table (L2T) entry for
1313 * the filter.
1314 */
1315 if (f->fs.newdmac || f->fs.newvlan) {
1316 /* allocate L2T entry for new filter */
1317 f->l2t = t4_l2t_alloc_switching(adapter->l2t);
1318 if (f->l2t == NULL)
1319 return -EAGAIN;
1320 if (t4_l2t_set_switching(adapter, f->l2t, f->fs.vlan,
1321 f->fs.eport, f->fs.dmac)) {
1322 cxgb4_l2t_release(f->l2t);
1323 f->l2t = NULL;
1324 return -ENOMEM;
1325 }
1326 }
1327
1328 ftid = adapter->tids.ftid_base + fidx;
1329
1330 skb = alloc_skb(sizeof(*fwr), GFP_KERNEL | __GFP_NOFAIL);
1331 fwr = (struct fw_filter_wr *)__skb_put(skb, sizeof(*fwr));
1332 memset(fwr, 0, sizeof(*fwr));
1333
1334 /* It would be nice to put most of the following in t4_hw.c but most
1335 * of the work is translating the cxgbtool ch_filter_specification
1336 * into the Work Request and the definition of that structure is
1337 * currently in cxgbtool.h which isn't appropriate to pull into the
1338 * common code. We may eventually try to come up with a more neutral
1339 * filter specification structure but for now it's easiest to simply
1340 * put this fairly direct code in line ...
1341 */
1342 fwr->op_pkd = htonl(FW_WR_OP(FW_FILTER_WR));
1343 fwr->len16_pkd = htonl(FW_WR_LEN16(sizeof(*fwr)/16));
1344 fwr->tid_to_iq =
1345 htonl(V_FW_FILTER_WR_TID(ftid) |
1346 V_FW_FILTER_WR_RQTYPE(f->fs.type) |
1347 V_FW_FILTER_WR_NOREPLY(0) |
1348 V_FW_FILTER_WR_IQ(f->fs.iq));
1349 fwr->del_filter_to_l2tix =
1350 htonl(V_FW_FILTER_WR_RPTTID(f->fs.rpttid) |
1351 V_FW_FILTER_WR_DROP(f->fs.action == FILTER_DROP) |
1352 V_FW_FILTER_WR_DIRSTEER(f->fs.dirsteer) |
1353 V_FW_FILTER_WR_MASKHASH(f->fs.maskhash) |
1354 V_FW_FILTER_WR_DIRSTEERHASH(f->fs.dirsteerhash) |
1355 V_FW_FILTER_WR_LPBK(f->fs.action == FILTER_SWITCH) |
1356 V_FW_FILTER_WR_DMAC(f->fs.newdmac) |
1357 V_FW_FILTER_WR_SMAC(f->fs.newsmac) |
1358 V_FW_FILTER_WR_INSVLAN(f->fs.newvlan == VLAN_INSERT ||
1359 f->fs.newvlan == VLAN_REWRITE) |
1360 V_FW_FILTER_WR_RMVLAN(f->fs.newvlan == VLAN_REMOVE ||
1361 f->fs.newvlan == VLAN_REWRITE) |
1362 V_FW_FILTER_WR_HITCNTS(f->fs.hitcnts) |
1363 V_FW_FILTER_WR_TXCHAN(f->fs.eport) |
1364 V_FW_FILTER_WR_PRIO(f->fs.prio) |
1365 V_FW_FILTER_WR_L2TIX(f->l2t ? f->l2t->idx : 0));
1366 fwr->ethtype = htons(f->fs.val.ethtype);
1367 fwr->ethtypem = htons(f->fs.mask.ethtype);
1368 fwr->frag_to_ovlan_vldm =
1369 (V_FW_FILTER_WR_FRAG(f->fs.val.frag) |
1370 V_FW_FILTER_WR_FRAGM(f->fs.mask.frag) |
1371 V_FW_FILTER_WR_IVLAN_VLD(f->fs.val.ivlan_vld) |
1372 V_FW_FILTER_WR_OVLAN_VLD(f->fs.val.ovlan_vld) |
1373 V_FW_FILTER_WR_IVLAN_VLDM(f->fs.mask.ivlan_vld) |
1374 V_FW_FILTER_WR_OVLAN_VLDM(f->fs.mask.ovlan_vld));
1375 fwr->smac_sel = 0;
1376 fwr->rx_chan_rx_rpl_iq =
1377 htons(V_FW_FILTER_WR_RX_CHAN(0) |
1378 V_FW_FILTER_WR_RX_RPL_IQ(adapter->sge.fw_evtq.abs_id));
1379 fwr->maci_to_matchtypem =
1380 htonl(V_FW_FILTER_WR_MACI(f->fs.val.macidx) |
1381 V_FW_FILTER_WR_MACIM(f->fs.mask.macidx) |
1382 V_FW_FILTER_WR_FCOE(f->fs.val.fcoe) |
1383 V_FW_FILTER_WR_FCOEM(f->fs.mask.fcoe) |
1384 V_FW_FILTER_WR_PORT(f->fs.val.iport) |
1385 V_FW_FILTER_WR_PORTM(f->fs.mask.iport) |
1386 V_FW_FILTER_WR_MATCHTYPE(f->fs.val.matchtype) |
1387 V_FW_FILTER_WR_MATCHTYPEM(f->fs.mask.matchtype));
1388 fwr->ptcl = f->fs.val.proto;
1389 fwr->ptclm = f->fs.mask.proto;
1390 fwr->ttyp = f->fs.val.tos;
1391 fwr->ttypm = f->fs.mask.tos;
1392 fwr->ivlan = htons(f->fs.val.ivlan);
1393 fwr->ivlanm = htons(f->fs.mask.ivlan);
1394 fwr->ovlan = htons(f->fs.val.ovlan);
1395 fwr->ovlanm = htons(f->fs.mask.ovlan);
1396 memcpy(fwr->lip, f->fs.val.lip, sizeof(fwr->lip));
1397 memcpy(fwr->lipm, f->fs.mask.lip, sizeof(fwr->lipm));
1398 memcpy(fwr->fip, f->fs.val.fip, sizeof(fwr->fip));
1399 memcpy(fwr->fipm, f->fs.mask.fip, sizeof(fwr->fipm));
1400 fwr->lp = htons(f->fs.val.lport);
1401 fwr->lpm = htons(f->fs.mask.lport);
1402 fwr->fp = htons(f->fs.val.fport);
1403 fwr->fpm = htons(f->fs.mask.fport);
1404 if (f->fs.newsmac)
1405 memcpy(fwr->sma, f->fs.smac, sizeof(fwr->sma));
1406
1407 /* Mark the filter as "pending" and ship off the Filter Work Request.
1408 * When we get the Work Request Reply we'll clear the pending status.
1409 */
1410 f->pending = 1;
1411 set_wr_txq(skb, CPL_PRIORITY_CONTROL, f->fs.val.iport & 0x3);
1412 t4_ofld_send(adapter, skb);
1413 return 0;
1414}
1415
1416/* Delete the filter at a specified index.
1417 */
1418static int del_filter_wr(struct adapter *adapter, int fidx)
1419{
1420 struct filter_entry *f = &adapter->tids.ftid_tab[fidx];
1421 struct sk_buff *skb;
1422 struct fw_filter_wr *fwr;
1423 unsigned int len, ftid;
1424
1425 len = sizeof(*fwr);
1426 ftid = adapter->tids.ftid_base + fidx;
1427
1428 skb = alloc_skb(len, GFP_KERNEL | __GFP_NOFAIL);
1429 fwr = (struct fw_filter_wr *)__skb_put(skb, len);
1430 t4_mk_filtdelwr(ftid, fwr, adapter->sge.fw_evtq.abs_id);
1431
1432 /* Mark the filter as "pending" and ship off the Filter Work Request.
1433 * When we get the Work Request Reply we'll clear the pending status.
1434 */
1435 f->pending = 1;
1436 t4_mgmt_tx(adapter, skb);
1437 return 0;
1438}
1439
688848b1
AB		 1440static u16 cxgb_select_queue(struct net_device *dev, struct sk_buff *skb,
1441 void *accel_priv, select_queue_fallback_t fallback)
1442{
1443 int txq;
1444
1445#ifdef CONFIG_CHELSIO_T4_DCB
1446 /* If a Data Center Bridging has been successfully negotiated on this
1447 * link then we'll use the skb's priority to map it to a TX Queue.
1448 * The skb's priority is determined via the VLAN Tag Priority Code
1449 * Point field.
1450 */
1451 if (cxgb4_dcb_enabled(dev)) {
1452 u16 vlan_tci;
1453 int err;
1454
1455 err = vlan_get_tag(skb, &vlan_tci);
1456 if (unlikely(err)) {
1457 if (net_ratelimit())
1458 netdev_warn(dev,
1459 "TX Packet without VLAN Tag on DCB Link\n");
1460 txq = 0;
1461 } else {
1462 txq = (vlan_tci & VLAN_PRIO_MASK) >> VLAN_PRIO_SHIFT;
1463 }
1464 return txq;
1465 }
1466#endif /* CONFIG_CHELSIO_T4_DCB */
1467
1468 if (select_queue) {
1469 txq = (skb_rx_queue_recorded(skb)
1470 ? skb_get_rx_queue(skb)
1471 : smp_processor_id());
1472
1473 while (unlikely(txq >= dev->real_num_tx_queues))
1474 txq -= dev->real_num_tx_queues;
1475
1476 return txq;
1477 }
1478
1479 return fallback(dev, skb) % dev->real_num_tx_queues;
1480}
1481
b8ff05a9
DM		 1482static inline int is_offload(const struct adapter *adap)
1483{
1484 return adap->params.offload;
1485}
1486
1487/*
1488 * Implementation of ethtool operations.
1489 */
1490
1491static u32 get_msglevel(struct net_device *dev)
1492{
1493 return netdev2adap(dev)->msg_enable;
1494}
1495
1496static void set_msglevel(struct net_device *dev, u32 val)
1497{
1498 netdev2adap(dev)->msg_enable = val;
1499}
1500
1501static char stats_strings[][ETH_GSTRING_LEN] = {
1502 "TxOctetsOK ",
1503 "TxFramesOK ",
1504 "TxBroadcastFrames ",
1505 "TxMulticastFrames ",
1506 "TxUnicastFrames ",
1507 "TxErrorFrames ",
1508
1509 "TxFrames64 ",
1510 "TxFrames65To127 ",
1511 "TxFrames128To255 ",
1512 "TxFrames256To511 ",
1513 "TxFrames512To1023 ",
1514 "TxFrames1024To1518 ",
1515 "TxFrames1519ToMax ",
1516
1517 "TxFramesDropped ",
1518 "TxPauseFrames ",
1519 "TxPPP0Frames ",
1520 "TxPPP1Frames ",
1521 "TxPPP2Frames ",
1522 "TxPPP3Frames ",
1523 "TxPPP4Frames ",
1524 "TxPPP5Frames ",
1525 "TxPPP6Frames ",
1526 "TxPPP7Frames ",
1527
1528 "RxOctetsOK ",
1529 "RxFramesOK ",
1530 "RxBroadcastFrames ",
1531 "RxMulticastFrames ",
1532 "RxUnicastFrames ",
1533
1534 "RxFramesTooLong ",
1535 "RxJabberErrors ",
1536 "RxFCSErrors ",
1537 "RxLengthErrors ",
1538 "RxSymbolErrors ",
1539 "RxRuntFrames ",
1540
1541 "RxFrames64 ",
1542 "RxFrames65To127 ",
1543 "RxFrames128To255 ",
1544 "RxFrames256To511 ",
1545 "RxFrames512To1023 ",
1546 "RxFrames1024To1518 ",
1547 "RxFrames1519ToMax ",
1548
1549 "RxPauseFrames ",
1550 "RxPPP0Frames ",
1551 "RxPPP1Frames ",
1552 "RxPPP2Frames ",
1553 "RxPPP3Frames ",
1554 "RxPPP4Frames ",
1555 "RxPPP5Frames ",
1556 "RxPPP6Frames ",
1557 "RxPPP7Frames ",
1558
1559 "RxBG0FramesDropped ",
1560 "RxBG1FramesDropped ",
1561 "RxBG2FramesDropped ",
1562 "RxBG3FramesDropped ",
1563 "RxBG0FramesTrunc ",
1564 "RxBG1FramesTrunc ",
1565 "RxBG2FramesTrunc ",
1566 "RxBG3FramesTrunc ",
1567
1568 "TSO ",
1569 "TxCsumOffload ",
1570 "RxCsumGood ",
1571 "VLANextractions ",
1572 "VLANinsertions ",
4a6346d4
DM		 1573 "GROpackets ",
1574 "GROmerged ",
22adfe0a
SR		 1575 "WriteCoalSuccess ",
1576 "WriteCoalFail ",
b8ff05a9
DM		 1577};
1578
1579static int get_sset_count(struct net_device *dev, int sset)
1580{
1581 switch (sset) {
1582 case ETH_SS_STATS:
1583 return ARRAY_SIZE(stats_strings);
1584 default:
1585 return -EOPNOTSUPP;
1586 }
1587}
1588
1589#define T4_REGMAP_SIZE (160 * 1024)
251f9e88 1590#define T5_REGMAP_SIZE (332 * 1024)
b8ff05a9
DM		 1591
1592static int get_regs_len(struct net_device *dev)
1593{
251f9e88 1594 struct adapter *adap = netdev2adap(dev);
d14807dd 1595 if (is_t4(adap->params.chip))
251f9e88
SR		 1596 return T4_REGMAP_SIZE;
1597 else
1598 return T5_REGMAP_SIZE;
b8ff05a9
DM		 1599}
1600
1601static int get_eeprom_len(struct net_device *dev)
1602{
1603 return EEPROMSIZE;
1604}
1605
1606static void get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
1607{
1608 struct adapter *adapter = netdev2adap(dev);
1609
23020ab3
RJ		 1610 strlcpy(info->driver, KBUILD_MODNAME, sizeof(info->driver));
1611 strlcpy(info->version, DRV_VERSION, sizeof(info->version));
1612 strlcpy(info->bus_info, pci_name(adapter->pdev),
1613 sizeof(info->bus_info));
b8ff05a9 1614
84b40501 1615 if (adapter->params.fw_vers)
b8ff05a9
DM		 1616 snprintf(info->fw_version, sizeof(info->fw_version),
1617 "%u.%u.%u.%u, TP %u.%u.%u.%u",
1618 FW_HDR_FW_VER_MAJOR_GET(adapter->params.fw_vers),
1619 FW_HDR_FW_VER_MINOR_GET(adapter->params.fw_vers),
1620 FW_HDR_FW_VER_MICRO_GET(adapter->params.fw_vers),
1621 FW_HDR_FW_VER_BUILD_GET(adapter->params.fw_vers),
1622 FW_HDR_FW_VER_MAJOR_GET(adapter->params.tp_vers),
1623 FW_HDR_FW_VER_MINOR_GET(adapter->params.tp_vers),
1624 FW_HDR_FW_VER_MICRO_GET(adapter->params.tp_vers),
1625 FW_HDR_FW_VER_BUILD_GET(adapter->params.tp_vers));
1626}
1627
1628static void get_strings(struct net_device *dev, u32 stringset, u8 *data)
1629{
1630 if (stringset == ETH_SS_STATS)
1631 memcpy(data, stats_strings, sizeof(stats_strings));
1632}
1633
1634/*
1635 * port stats maintained per queue of the port. They should be in the same
1636 * order as in stats_strings above.
1637 */
1638struct queue_port_stats {
1639 u64 tso;
1640 u64 tx_csum;
1641 u64 rx_csum;
1642 u64 vlan_ex;
1643 u64 vlan_ins;
4a6346d4
DM		 1644 u64 gro_pkts;
1645 u64 gro_merged;
b8ff05a9
DM		 1646};
1647
1648static void collect_sge_port_stats(const struct adapter *adap,
1649 const struct port_info *p, struct queue_port_stats *s)
1650{
1651 int i;
1652 const struct sge_eth_txq *tx = &adap->sge.ethtxq[p->first_qset];
1653 const struct sge_eth_rxq *rx = &adap->sge.ethrxq[p->first_qset];
1654
1655 memset(s, 0, sizeof(*s));
1656 for (i = 0; i < p->nqsets; i++, rx++, tx++) {
1657 s->tso += tx->tso;
1658 s->tx_csum += tx->tx_cso;
1659 s->rx_csum += rx->stats.rx_cso;
1660 s->vlan_ex += rx->stats.vlan_ex;
1661 s->vlan_ins += tx->vlan_ins;
4a6346d4
DM		 1662 s->gro_pkts += rx->stats.lro_pkts;
1663 s->gro_merged += rx->stats.lro_merged;
b8ff05a9
DM		 1664 }
1665}
1666
1667static void get_stats(struct net_device *dev, struct ethtool_stats *stats,
1668 u64 *data)
1669{
1670 struct port_info *pi = netdev_priv(dev);
1671 struct adapter *adapter = pi->adapter;
22adfe0a 1672 u32 val1, val2;
b8ff05a9
DM		 1673
1674 t4_get_port_stats(adapter, pi->tx_chan, (struct port_stats *)data);
1675
1676 data += sizeof(struct port_stats) / sizeof(u64);
1677 collect_sge_port_stats(adapter, pi, (struct queue_port_stats *)data);
22adfe0a 1678 data += sizeof(struct queue_port_stats) / sizeof(u64);
d14807dd 1679 if (!is_t4(adapter->params.chip)) {
22adfe0a
SR		 1680 t4_write_reg(adapter, SGE_STAT_CFG, STATSOURCE_T5(7));
1681 val1 = t4_read_reg(adapter, SGE_STAT_TOTAL);
1682 val2 = t4_read_reg(adapter, SGE_STAT_MATCH);
1683 *data = val1 - val2;
1684 data++;
1685 *data = val2;
1686 data++;
1687 } else {
1688 memset(data, 0, 2 * sizeof(u64));
1689 *data += 2;
1690 }
b8ff05a9
DM		 1691}
1692
1693/*
1694 * Return a version number to identify the type of adapter. The scheme is:
1695 * - bits 0..9: chip version
1696 * - bits 10..15: chip revision
835bb606 1697 * - bits 16..23: register dump version
b8ff05a9
DM		 1698 */
1699static inline unsigned int mk_adap_vers(const struct adapter *ap)
1700{
d14807dd
HS		 1701 return CHELSIO_CHIP_VERSION(ap->params.chip) |
1702 (CHELSIO_CHIP_RELEASE(ap->params.chip) << 10) | (1 << 16);
b8ff05a9
DM		 1703}
1704
1705static void reg_block_dump(struct adapter *ap, void *buf, unsigned int start,
1706 unsigned int end)
1707{
1708 u32 *p = buf + start;
1709
1710 for ( ; start <= end; start += sizeof(u32))
1711 *p++ = t4_read_reg(ap, start);
1712}
1713
1714static void get_regs(struct net_device *dev, struct ethtool_regs *regs,
1715 void *buf)
1716{
251f9e88 1717 static const unsigned int t4_reg_ranges[] = {
b8ff05a9
DM		 1718 0x1008, 0x1108,
1719 0x1180, 0x11b4,
1720 0x11fc, 0x123c,
1721 0x1300, 0x173c,
1722 0x1800, 0x18fc,
1723 0x3000, 0x30d8,
1724 0x30e0, 0x5924,
1725 0x5960, 0x59d4,
1726 0x5a00, 0x5af8,
1727 0x6000, 0x6098,
1728 0x6100, 0x6150,
1729 0x6200, 0x6208,
1730 0x6240, 0x6248,
1731 0x6280, 0x6338,
1732 0x6370, 0x638c,
1733 0x6400, 0x643c,
1734 0x6500, 0x6524,
1735 0x6a00, 0x6a38,
1736 0x6a60, 0x6a78,
1737 0x6b00, 0x6b84,
1738 0x6bf0, 0x6c84,
1739 0x6cf0, 0x6d84,
1740 0x6df0, 0x6e84,
1741 0x6ef0, 0x6f84,
1742 0x6ff0, 0x7084,
1743 0x70f0, 0x7184,
1744 0x71f0, 0x7284,
1745 0x72f0, 0x7384,
1746 0x73f0, 0x7450,
1747 0x7500, 0x7530,
1748 0x7600, 0x761c,
1749 0x7680, 0x76cc,
1750 0x7700, 0x7798,
1751 0x77c0, 0x77fc,
1752 0x7900, 0x79fc,
1753 0x7b00, 0x7c38,
1754 0x7d00, 0x7efc,
1755 0x8dc0, 0x8e1c,
1756 0x8e30, 0x8e78,
1757 0x8ea0, 0x8f6c,
1758 0x8fc0, 0x9074,
1759 0x90fc, 0x90fc,
1760 0x9400, 0x9458,
1761 0x9600, 0x96bc,
1762 0x9800, 0x9808,
1763 0x9820, 0x983c,
1764 0x9850, 0x9864,
1765 0x9c00, 0x9c6c,
1766 0x9c80, 0x9cec,
1767 0x9d00, 0x9d6c,
1768 0x9d80, 0x9dec,
1769 0x9e00, 0x9e6c,
1770 0x9e80, 0x9eec,
1771 0x9f00, 0x9f6c,
1772 0x9f80, 0x9fec,
1773 0xd004, 0xd03c,
1774 0xdfc0, 0xdfe0,
1775 0xe000, 0xea7c,
3d9103f8
HS		 1776 0xf000, 0x11110,
1777 0x11118, 0x11190,
835bb606
DM		 1778 0x19040, 0x1906c,
1779 0x19078, 0x19080,
1780 0x1908c, 0x19124,
b8ff05a9
DM		 1781 0x19150, 0x191b0,
1782 0x191d0, 0x191e8,
1783 0x19238, 0x1924c,
1784 0x193f8, 0x19474,
1785 0x19490, 0x194f8,
1786 0x19800, 0x19f30,
1787 0x1a000, 0x1a06c,
1788 0x1a0b0, 0x1a120,
1789 0x1a128, 0x1a138,
1790 0x1a190, 0x1a1c4,
1791 0x1a1fc, 0x1a1fc,
1792 0x1e040, 0x1e04c,
835bb606 1793 0x1e284, 0x1e28c,
b8ff05a9
DM		 1794 0x1e2c0, 0x1e2c0,
1795 0x1e2e0, 0x1e2e0,
1796 0x1e300, 0x1e384,
1797 0x1e3c0, 0x1e3c8,
1798 0x1e440, 0x1e44c,
835bb606 1799 0x1e684, 0x1e68c,
b8ff05a9
DM		 1800 0x1e6c0, 0x1e6c0,
1801 0x1e6e0, 0x1e6e0,
1802 0x1e700, 0x1e784,
1803 0x1e7c0, 0x1e7c8,
1804 0x1e840, 0x1e84c,
835bb606 1805 0x1ea84, 0x1ea8c,
b8ff05a9
DM		 1806 0x1eac0, 0x1eac0,
1807 0x1eae0, 0x1eae0,
1808 0x1eb00, 0x1eb84,
1809 0x1ebc0, 0x1ebc8,
1810 0x1ec40, 0x1ec4c,
835bb606 1811 0x1ee84, 0x1ee8c,
b8ff05a9
DM		 1812 0x1eec0, 0x1eec0,
1813 0x1eee0, 0x1eee0,
1814 0x1ef00, 0x1ef84,
1815 0x1efc0, 0x1efc8,
1816 0x1f040, 0x1f04c,
835bb606 1817 0x1f284, 0x1f28c,
b8ff05a9
DM		 1818 0x1f2c0, 0x1f2c0,
1819 0x1f2e0, 0x1f2e0,
1820 0x1f300, 0x1f384,
1821 0x1f3c0, 0x1f3c8,
1822 0x1f440, 0x1f44c,
835bb606 1823 0x1f684, 0x1f68c,
b8ff05a9
DM		 1824 0x1f6c0, 0x1f6c0,
1825 0x1f6e0, 0x1f6e0,
1826 0x1f700, 0x1f784,
1827 0x1f7c0, 0x1f7c8,
1828 0x1f840, 0x1f84c,
835bb606 1829 0x1fa84, 0x1fa8c,
b8ff05a9
DM		 1830 0x1fac0, 0x1fac0,
1831 0x1fae0, 0x1fae0,
1832 0x1fb00, 0x1fb84,
1833 0x1fbc0, 0x1fbc8,
1834 0x1fc40, 0x1fc4c,
835bb606 1835 0x1fe84, 0x1fe8c,
b8ff05a9
DM		 1836 0x1fec0, 0x1fec0,
1837 0x1fee0, 0x1fee0,
1838 0x1ff00, 0x1ff84,
1839 0x1ffc0, 0x1ffc8,
1840 0x20000, 0x2002c,
1841 0x20100, 0x2013c,
1842 0x20190, 0x201c8,
1843 0x20200, 0x20318,
1844 0x20400, 0x20528,
1845 0x20540, 0x20614,
1846 0x21000, 0x21040,
1847 0x2104c, 0x21060,
1848 0x210c0, 0x210ec,
1849 0x21200, 0x21268,
1850 0x21270, 0x21284,
1851 0x212fc, 0x21388,
1852 0x21400, 0x21404,
1853 0x21500, 0x21518,
1854 0x2152c, 0x2153c,
1855 0x21550, 0x21554,
1856 0x21600, 0x21600,
1857 0x21608, 0x21628,
1858 0x21630, 0x2163c,
1859 0x21700, 0x2171c,
1860 0x21780, 0x2178c,
1861 0x21800, 0x21c38,
1862 0x21c80, 0x21d7c,
1863 0x21e00, 0x21e04,
1864 0x22000, 0x2202c,
1865 0x22100, 0x2213c,
1866 0x22190, 0x221c8,
1867 0x22200, 0x22318,
1868 0x22400, 0x22528,
1869 0x22540, 0x22614,
1870 0x23000, 0x23040,
1871 0x2304c, 0x23060,
1872 0x230c0, 0x230ec,
1873 0x23200, 0x23268,
1874 0x23270, 0x23284,
1875 0x232fc, 0x23388,
1876 0x23400, 0x23404,
1877 0x23500, 0x23518,
1878 0x2352c, 0x2353c,
1879 0x23550, 0x23554,
1880 0x23600, 0x23600,
1881 0x23608, 0x23628,
1882 0x23630, 0x2363c,
1883 0x23700, 0x2371c,
1884 0x23780, 0x2378c,
1885 0x23800, 0x23c38,
1886 0x23c80, 0x23d7c,
1887 0x23e00, 0x23e04,
1888 0x24000, 0x2402c,
1889 0x24100, 0x2413c,
1890 0x24190, 0x241c8,
1891 0x24200, 0x24318,
1892 0x24400, 0x24528,
1893 0x24540, 0x24614,
1894 0x25000, 0x25040,
1895 0x2504c, 0x25060,
1896 0x250c0, 0x250ec,
1897 0x25200, 0x25268,
1898 0x25270, 0x25284,
1899 0x252fc, 0x25388,
1900 0x25400, 0x25404,
1901 0x25500, 0x25518,
1902 0x2552c, 0x2553c,
1903 0x25550, 0x25554,
1904 0x25600, 0x25600,
1905 0x25608, 0x25628,
1906 0x25630, 0x2563c,
1907 0x25700, 0x2571c,
1908 0x25780, 0x2578c,
1909 0x25800, 0x25c38,
1910 0x25c80, 0x25d7c,
1911 0x25e00, 0x25e04,
1912 0x26000, 0x2602c,
1913 0x26100, 0x2613c,
1914 0x26190, 0x261c8,
1915 0x26200, 0x26318,
1916 0x26400, 0x26528,
1917 0x26540, 0x26614,
1918 0x27000, 0x27040,
1919 0x2704c, 0x27060,
1920 0x270c0, 0x270ec,
1921 0x27200, 0x27268,
1922 0x27270, 0x27284,
1923 0x272fc, 0x27388,
1924 0x27400, 0x27404,
1925 0x27500, 0x27518,
1926 0x2752c, 0x2753c,
1927 0x27550, 0x27554,
1928 0x27600, 0x27600,
1929 0x27608, 0x27628,
1930 0x27630, 0x2763c,
1931 0x27700, 0x2771c,
1932 0x27780, 0x2778c,
1933 0x27800, 0x27c38,
1934 0x27c80, 0x27d7c,
1935 0x27e00, 0x27e04
1936 };
1937
251f9e88
SR		 1938 static const unsigned int t5_reg_ranges[] = {
1939 0x1008, 0x1148,
1940 0x1180, 0x11b4,
1941 0x11fc, 0x123c,
1942 0x1280, 0x173c,
1943 0x1800, 0x18fc,
1944 0x3000, 0x3028,
1945 0x3060, 0x30d8,
1946 0x30e0, 0x30fc,
1947 0x3140, 0x357c,
1948 0x35a8, 0x35cc,
1949 0x35ec, 0x35ec,
1950 0x3600, 0x5624,
1951 0x56cc, 0x575c,
1952 0x580c, 0x5814,
1953 0x5890, 0x58bc,
1954 0x5940, 0x59dc,
1955 0x59fc, 0x5a18,
1956 0x5a60, 0x5a9c,
1957 0x5b9c, 0x5bfc,
1958 0x6000, 0x6040,
1959 0x6058, 0x614c,
1960 0x7700, 0x7798,
1961 0x77c0, 0x78fc,
1962 0x7b00, 0x7c54,
1963 0x7d00, 0x7efc,
1964 0x8dc0, 0x8de0,
1965 0x8df8, 0x8e84,
1966 0x8ea0, 0x8f84,
1967 0x8fc0, 0x90f8,
1968 0x9400, 0x9470,
1969 0x9600, 0x96f4,
1970 0x9800, 0x9808,
1971 0x9820, 0x983c,
1972 0x9850, 0x9864,
1973 0x9c00, 0x9c6c,
1974 0x9c80, 0x9cec,
1975 0x9d00, 0x9d6c,
1976 0x9d80, 0x9dec,
1977 0x9e00, 0x9e6c,
1978 0x9e80, 0x9eec,
1979 0x9f00, 0x9f6c,
1980 0x9f80, 0xa020,
1981 0xd004, 0xd03c,
1982 0xdfc0, 0xdfe0,
1983 0xe000, 0x11088,
3d9103f8
HS		 1984 0x1109c, 0x11110,
1985 0x11118, 0x1117c,
251f9e88
SR		 1986 0x11190, 0x11204,
1987 0x19040, 0x1906c,
1988 0x19078, 0x19080,
1989 0x1908c, 0x19124,
1990 0x19150, 0x191b0,
1991 0x191d0, 0x191e8,
1992 0x19238, 0x19290,
1993 0x193f8, 0x19474,
1994 0x19490, 0x194cc,
1995 0x194f0, 0x194f8,
1996 0x19c00, 0x19c60,
1997 0x19c94, 0x19e10,
1998 0x19e50, 0x19f34,
1999 0x19f40, 0x19f50,
2000 0x19f90, 0x19fe4,
2001 0x1a000, 0x1a06c,
2002 0x1a0b0, 0x1a120,
2003 0x1a128, 0x1a138,
2004 0x1a190, 0x1a1c4,
2005 0x1a1fc, 0x1a1fc,
2006 0x1e008, 0x1e00c,
2007 0x1e040, 0x1e04c,
2008 0x1e284, 0x1e290,
2009 0x1e2c0, 0x1e2c0,
2010 0x1e2e0, 0x1e2e0,
2011 0x1e300, 0x1e384,
2012 0x1e3c0, 0x1e3c8,
2013 0x1e408, 0x1e40c,
2014 0x1e440, 0x1e44c,
2015 0x1e684, 0x1e690,
2016 0x1e6c0, 0x1e6c0,
2017 0x1e6e0, 0x1e6e0,
2018 0x1e700, 0x1e784,
2019 0x1e7c0, 0x1e7c8,
2020 0x1e808, 0x1e80c,
2021 0x1e840, 0x1e84c,
2022 0x1ea84, 0x1ea90,
2023 0x1eac0, 0x1eac0,
2024 0x1eae0, 0x1eae0,
2025 0x1eb00, 0x1eb84,
2026 0x1ebc0, 0x1ebc8,
2027 0x1ec08, 0x1ec0c,
2028 0x1ec40, 0x1ec4c,
2029 0x1ee84, 0x1ee90,
2030 0x1eec0, 0x1eec0,
2031 0x1eee0, 0x1eee0,
2032 0x1ef00, 0x1ef84,
2033 0x1efc0, 0x1efc8,
2034 0x1f008, 0x1f00c,
2035 0x1f040, 0x1f04c,
2036 0x1f284, 0x1f290,
2037 0x1f2c0, 0x1f2c0,
2038 0x1f2e0, 0x1f2e0,
2039 0x1f300, 0x1f384,
2040 0x1f3c0, 0x1f3c8,
2041 0x1f408, 0x1f40c,
2042 0x1f440, 0x1f44c,
2043 0x1f684, 0x1f690,
2044 0x1f6c0, 0x1f6c0,
2045 0x1f6e0, 0x1f6e0,
2046 0x1f700, 0x1f784,
2047 0x1f7c0, 0x1f7c8,
2048 0x1f808, 0x1f80c,
2049 0x1f840, 0x1f84c,
2050 0x1fa84, 0x1fa90,
2051 0x1fac0, 0x1fac0,
2052 0x1fae0, 0x1fae0,
2053 0x1fb00, 0x1fb84,
2054 0x1fbc0, 0x1fbc8,
2055 0x1fc08, 0x1fc0c,
2056 0x1fc40, 0x1fc4c,
2057 0x1fe84, 0x1fe90,
2058 0x1fec0, 0x1fec0,
2059 0x1fee0, 0x1fee0,
2060 0x1ff00, 0x1ff84,
2061 0x1ffc0, 0x1ffc8,
2062 0x30000, 0x30030,
2063 0x30100, 0x30144,
2064 0x30190, 0x301d0,
2065 0x30200, 0x30318,
2066 0x30400, 0x3052c,
2067 0x30540, 0x3061c,
2068 0x30800, 0x30834,
2069 0x308c0, 0x30908,
2070 0x30910, 0x309ac,
2071 0x30a00, 0x30a04,
2072 0x30a0c, 0x30a2c,
2073 0x30a44, 0x30a50,
2074 0x30a74, 0x30c24,
2075 0x30d08, 0x30d14,
2076 0x30d1c, 0x30d20,
2077 0x30d3c, 0x30d50,
2078 0x31200, 0x3120c,
2079 0x31220, 0x31220,
2080 0x31240, 0x31240,
2081 0x31600, 0x31600,
2082 0x31608, 0x3160c,
2083 0x31a00, 0x31a1c,
2084 0x31e04, 0x31e20,
2085 0x31e38, 0x31e3c,
2086 0x31e80, 0x31e80,
2087 0x31e88, 0x31ea8,
2088 0x31eb0, 0x31eb4,
2089 0x31ec8, 0x31ed4,
2090 0x31fb8, 0x32004,
2091 0x32208, 0x3223c,
2092 0x32600, 0x32630,
2093 0x32a00, 0x32abc,
2094 0x32b00, 0x32b70,
2095 0x33000, 0x33048,
2096 0x33060, 0x3309c,
2097 0x330f0, 0x33148,
2098 0x33160, 0x3319c,
2099 0x331f0, 0x332e4,
2100 0x332f8, 0x333e4,
2101 0x333f8, 0x33448,
2102 0x33460, 0x3349c,
2103 0x334f0, 0x33548,
2104 0x33560, 0x3359c,
2105 0x335f0, 0x336e4,
2106 0x336f8, 0x337e4,
2107 0x337f8, 0x337fc,
2108 0x33814, 0x33814,
2109 0x3382c, 0x3382c,
2110 0x33880, 0x3388c,
2111 0x338e8, 0x338ec,
2112 0x33900, 0x33948,
2113 0x33960, 0x3399c,
2114 0x339f0, 0x33ae4,
2115 0x33af8, 0x33b10,
2116 0x33b28, 0x33b28,
2117 0x33b3c, 0x33b50,
2118 0x33bf0, 0x33c10,
2119 0x33c28, 0x33c28,
2120 0x33c3c, 0x33c50,
2121 0x33cf0, 0x33cfc,
2122 0x34000, 0x34030,
2123 0x34100, 0x34144,
2124 0x34190, 0x341d0,
2125 0x34200, 0x34318,
2126 0x34400, 0x3452c,
2127 0x34540, 0x3461c,
2128 0x34800, 0x34834,
2129 0x348c0, 0x34908,
2130 0x34910, 0x349ac,
2131 0x34a00, 0x34a04,
2132 0x34a0c, 0x34a2c,
2133 0x34a44, 0x34a50,
2134 0x34a74, 0x34c24,
2135 0x34d08, 0x34d14,
2136 0x34d1c, 0x34d20,
2137 0x34d3c, 0x34d50,
2138 0x35200, 0x3520c,
2139 0x35220, 0x35220,
2140 0x35240, 0x35240,
2141 0x35600, 0x35600,
2142 0x35608, 0x3560c,
2143 0x35a00, 0x35a1c,
2144 0x35e04, 0x35e20,
2145 0x35e38, 0x35e3c,
2146 0x35e80, 0x35e80,
2147 0x35e88, 0x35ea8,
2148 0x35eb0, 0x35eb4,
2149 0x35ec8, 0x35ed4,
2150 0x35fb8, 0x36004,
2151 0x36208, 0x3623c,
2152 0x36600, 0x36630,
2153 0x36a00, 0x36abc,
2154 0x36b00, 0x36b70,
2155 0x37000, 0x37048,
2156 0x37060, 0x3709c,
2157 0x370f0, 0x37148,
2158 0x37160, 0x3719c,
2159 0x371f0, 0x372e4,
2160 0x372f8, 0x373e4,
2161 0x373f8, 0x37448,
2162 0x37460, 0x3749c,
2163 0x374f0, 0x37548,
2164 0x37560, 0x3759c,
2165 0x375f0, 0x376e4,
2166 0x376f8, 0x377e4,
2167 0x377f8, 0x377fc,
2168 0x37814, 0x37814,
2169 0x3782c, 0x3782c,
2170 0x37880, 0x3788c,
2171 0x378e8, 0x378ec,
2172 0x37900, 0x37948,
2173 0x37960, 0x3799c,
2174 0x379f0, 0x37ae4,
2175 0x37af8, 0x37b10,
2176 0x37b28, 0x37b28,
2177 0x37b3c, 0x37b50,
2178 0x37bf0, 0x37c10,
2179 0x37c28, 0x37c28,
2180 0x37c3c, 0x37c50,
2181 0x37cf0, 0x37cfc,
2182 0x38000, 0x38030,
2183 0x38100, 0x38144,
2184 0x38190, 0x381d0,
2185 0x38200, 0x38318,
2186 0x38400, 0x3852c,
2187 0x38540, 0x3861c,
2188 0x38800, 0x38834,
2189 0x388c0, 0x38908,
2190 0x38910, 0x389ac,
2191 0x38a00, 0x38a04,
2192 0x38a0c, 0x38a2c,
2193 0x38a44, 0x38a50,
2194 0x38a74, 0x38c24,
2195 0x38d08, 0x38d14,
2196 0x38d1c, 0x38d20,
2197 0x38d3c, 0x38d50,
2198 0x39200, 0x3920c,
2199 0x39220, 0x39220,
2200 0x39240, 0x39240,
2201 0x39600, 0x39600,
2202 0x39608, 0x3960c,
2203 0x39a00, 0x39a1c,
2204 0x39e04, 0x39e20,
2205 0x39e38, 0x39e3c,
2206 0x39e80, 0x39e80,
2207 0x39e88, 0x39ea8,
2208 0x39eb0, 0x39eb4,
2209 0x39ec8, 0x39ed4,
2210 0x39fb8, 0x3a004,
2211 0x3a208, 0x3a23c,
2212 0x3a600, 0x3a630,
2213 0x3aa00, 0x3aabc,
2214 0x3ab00, 0x3ab70,
2215 0x3b000, 0x3b048,
2216 0x3b060, 0x3b09c,
2217 0x3b0f0, 0x3b148,
2218 0x3b160, 0x3b19c,
2219 0x3b1f0, 0x3b2e4,
2220 0x3b2f8, 0x3b3e4,
2221 0x3b3f8, 0x3b448,
2222 0x3b460, 0x3b49c,
2223 0x3b4f0, 0x3b548,
2224 0x3b560, 0x3b59c,
2225 0x3b5f0, 0x3b6e4,
2226 0x3b6f8, 0x3b7e4,
2227 0x3b7f8, 0x3b7fc,
2228 0x3b814, 0x3b814,
2229 0x3b82c, 0x3b82c,
2230 0x3b880, 0x3b88c,
2231 0x3b8e8, 0x3b8ec,
2232 0x3b900, 0x3b948,
2233 0x3b960, 0x3b99c,
2234 0x3b9f0, 0x3bae4,
2235 0x3baf8, 0x3bb10,
2236 0x3bb28, 0x3bb28,
2237 0x3bb3c, 0x3bb50,
2238 0x3bbf0, 0x3bc10,
2239 0x3bc28, 0x3bc28,
2240 0x3bc3c, 0x3bc50,
2241 0x3bcf0, 0x3bcfc,
2242 0x3c000, 0x3c030,
2243 0x3c100, 0x3c144,
2244 0x3c190, 0x3c1d0,
2245 0x3c200, 0x3c318,
2246 0x3c400, 0x3c52c,
2247 0x3c540, 0x3c61c,
2248 0x3c800, 0x3c834,
2249 0x3c8c0, 0x3c908,
2250 0x3c910, 0x3c9ac,
2251 0x3ca00, 0x3ca04,
2252 0x3ca0c, 0x3ca2c,
2253 0x3ca44, 0x3ca50,
2254 0x3ca74, 0x3cc24,
2255 0x3cd08, 0x3cd14,
2256 0x3cd1c, 0x3cd20,
2257 0x3cd3c, 0x3cd50,
2258 0x3d200, 0x3d20c,
2259 0x3d220, 0x3d220,
2260 0x3d240, 0x3d240,
2261 0x3d600, 0x3d600,
2262 0x3d608, 0x3d60c,
2263 0x3da00, 0x3da1c,
2264 0x3de04, 0x3de20,
2265 0x3de38, 0x3de3c,
2266 0x3de80, 0x3de80,
2267 0x3de88, 0x3dea8,
2268 0x3deb0, 0x3deb4,
2269 0x3dec8, 0x3ded4,
2270 0x3dfb8, 0x3e004,
2271 0x3e208, 0x3e23c,
2272 0x3e600, 0x3e630,
2273 0x3ea00, 0x3eabc,
2274 0x3eb00, 0x3eb70,
2275 0x3f000, 0x3f048,
2276 0x3f060, 0x3f09c,
2277 0x3f0f0, 0x3f148,
2278 0x3f160, 0x3f19c,
2279 0x3f1f0, 0x3f2e4,
2280 0x3f2f8, 0x3f3e4,
2281 0x3f3f8, 0x3f448,
2282 0x3f460, 0x3f49c,
2283 0x3f4f0, 0x3f548,
2284 0x3f560, 0x3f59c,
2285 0x3f5f0, 0x3f6e4,
2286 0x3f6f8, 0x3f7e4,
2287 0x3f7f8, 0x3f7fc,
2288 0x3f814, 0x3f814,
2289 0x3f82c, 0x3f82c,
2290 0x3f880, 0x3f88c,
2291 0x3f8e8, 0x3f8ec,
2292 0x3f900, 0x3f948,
2293 0x3f960, 0x3f99c,
2294 0x3f9f0, 0x3fae4,
2295 0x3faf8, 0x3fb10,
2296 0x3fb28, 0x3fb28,
2297 0x3fb3c, 0x3fb50,
2298 0x3fbf0, 0x3fc10,
2299 0x3fc28, 0x3fc28,
2300 0x3fc3c, 0x3fc50,
2301 0x3fcf0, 0x3fcfc,
2302 0x40000, 0x4000c,
2303 0x40040, 0x40068,
2304 0x40080, 0x40144,
2305 0x40180, 0x4018c,
2306 0x40200, 0x40298,
2307 0x402ac, 0x4033c,
2308 0x403f8, 0x403fc,
c1f49e3e 2309 0x41304, 0x413c4,
251f9e88
SR		 2310 0x41400, 0x4141c,
2311 0x41480, 0x414d0,
2312 0x44000, 0x44078,
2313 0x440c0, 0x44278,
2314 0x442c0, 0x44478,
2315 0x444c0, 0x44678,
2316 0x446c0, 0x44878,
2317 0x448c0, 0x449fc,
2318 0x45000, 0x45068,
2319 0x45080, 0x45084,
2320 0x450a0, 0x450b0,
2321 0x45200, 0x45268,
2322 0x45280, 0x45284,
2323 0x452a0, 0x452b0,
2324 0x460c0, 0x460e4,
2325 0x47000, 0x4708c,
2326 0x47200, 0x47250,
2327 0x47400, 0x47420,
2328 0x47600, 0x47618,
2329 0x47800, 0x47814,
2330 0x48000, 0x4800c,
2331 0x48040, 0x48068,
2332 0x48080, 0x48144,
2333 0x48180, 0x4818c,
2334 0x48200, 0x48298,
2335 0x482ac, 0x4833c,
2336 0x483f8, 0x483fc,
c1f49e3e 2337 0x49304, 0x493c4,
251f9e88
SR		 2338 0x49400, 0x4941c,
2339 0x49480, 0x494d0,
2340 0x4c000, 0x4c078,
2341 0x4c0c0, 0x4c278,
2342 0x4c2c0, 0x4c478,
2343 0x4c4c0, 0x4c678,
2344 0x4c6c0, 0x4c878,
2345 0x4c8c0, 0x4c9fc,
2346 0x4d000, 0x4d068,
2347 0x4d080, 0x4d084,
2348 0x4d0a0, 0x4d0b0,
2349 0x4d200, 0x4d268,
2350 0x4d280, 0x4d284,
2351 0x4d2a0, 0x4d2b0,
2352 0x4e0c0, 0x4e0e4,
2353 0x4f000, 0x4f08c,
2354 0x4f200, 0x4f250,
2355 0x4f400, 0x4f420,
2356 0x4f600, 0x4f618,
2357 0x4f800, 0x4f814,
2358 0x50000, 0x500cc,
2359 0x50400, 0x50400,
2360 0x50800, 0x508cc,
2361 0x50c00, 0x50c00,
2362 0x51000, 0x5101c,
2363 0x51300, 0x51308,
2364 };
2365
b8ff05a9
DM		 2366 int i;
2367 struct adapter *ap = netdev2adap(dev);
251f9e88
SR		 2368 static const unsigned int *reg_ranges;
2369 int arr_size = 0, buf_size = 0;
2370
d14807dd 2371 if (is_t4(ap->params.chip)) {
251f9e88
SR		 2372 reg_ranges = &t4_reg_ranges[0];
2373 arr_size = ARRAY_SIZE(t4_reg_ranges);
2374 buf_size = T4_REGMAP_SIZE;
2375 } else {
2376 reg_ranges = &t5_reg_ranges[0];
2377 arr_size = ARRAY_SIZE(t5_reg_ranges);
2378 buf_size = T5_REGMAP_SIZE;
2379 }
b8ff05a9
DM		 2380
2381 regs->version = mk_adap_vers(ap);
2382
251f9e88
SR		 2383 memset(buf, 0, buf_size);
2384 for (i = 0; i < arr_size; i += 2)
b8ff05a9
DM		 2385 reg_block_dump(ap, buf, reg_ranges[i], reg_ranges[i + 1]);
2386}
2387
2388static int restart_autoneg(struct net_device *dev)
2389{
2390 struct port_info *p = netdev_priv(dev);
2391
2392 if (!netif_running(dev))
2393 return -EAGAIN;
2394 if (p->link_cfg.autoneg != AUTONEG_ENABLE)
2395 return -EINVAL;
060e0c75 2396 t4_restart_aneg(p->adapter, p->adapter->fn, p->tx_chan);
b8ff05a9
DM		 2397 return 0;
2398}
2399
c5e06360
DM		 2400static int identify_port(struct net_device *dev,
2401 enum ethtool_phys_id_state state)
b8ff05a9 2402{
c5e06360 2403 unsigned int val;
060e0c75
DM		 2404 struct adapter *adap = netdev2adap(dev);
2405
c5e06360
DM		 2406 if (state == ETHTOOL_ID_ACTIVE)
2407 val = 0xffff;
2408 else if (state == ETHTOOL_ID_INACTIVE)
2409 val = 0;
2410 else
2411 return -EINVAL;
b8ff05a9 2412
c5e06360 2413 return t4_identify_port(adap, adap->fn, netdev2pinfo(dev)->viid, val);
b8ff05a9
DM		 2414}
2415
2416static unsigned int from_fw_linkcaps(unsigned int type, unsigned int caps)
2417{
2418 unsigned int v = 0;
2419
a0881cab
DM		 2420 if (type == FW_PORT_TYPE_BT_SGMII || type == FW_PORT_TYPE_BT_XFI ||
2421 type == FW_PORT_TYPE_BT_XAUI) {
b8ff05a9
DM		 2422 v |= SUPPORTED_TP;
2423 if (caps & FW_PORT_CAP_SPEED_100M)
2424 v |= SUPPORTED_100baseT_Full;
2425 if (caps & FW_PORT_CAP_SPEED_1G)
2426 v |= SUPPORTED_1000baseT_Full;
2427 if (caps & FW_PORT_CAP_SPEED_10G)
2428 v |= SUPPORTED_10000baseT_Full;
2429 } else if (type == FW_PORT_TYPE_KX4 || type == FW_PORT_TYPE_KX) {
2430 v |= SUPPORTED_Backplane;
2431 if (caps & FW_PORT_CAP_SPEED_1G)
2432 v |= SUPPORTED_1000baseKX_Full;
2433 if (caps & FW_PORT_CAP_SPEED_10G)
2434 v |= SUPPORTED_10000baseKX4_Full;
2435 } else if (type == FW_PORT_TYPE_KR)
2436 v |= SUPPORTED_Backplane | SUPPORTED_10000baseKR_Full;
a0881cab 2437 else if (type == FW_PORT_TYPE_BP_AP)
7d5e77aa
DM		 2438 v |= SUPPORTED_Backplane | SUPPORTED_10000baseR_FEC |
2439 SUPPORTED_10000baseKR_Full | SUPPORTED_1000baseKX_Full;
2440 else if (type == FW_PORT_TYPE_BP4_AP)
2441 v |= SUPPORTED_Backplane | SUPPORTED_10000baseR_FEC |
2442 SUPPORTED_10000baseKR_Full | SUPPORTED_1000baseKX_Full |
2443 SUPPORTED_10000baseKX4_Full;
a0881cab
DM		 2444 else if (type == FW_PORT_TYPE_FIBER_XFI ||
2445 type == FW_PORT_TYPE_FIBER_XAUI || type == FW_PORT_TYPE_SFP)
b8ff05a9 2446 v |= SUPPORTED_FIBRE;
72aca4bf
KS		 2447 else if (type == FW_PORT_TYPE_BP40_BA)
2448 v |= SUPPORTED_40000baseSR4_Full;
b8ff05a9
DM		 2449
2450 if (caps & FW_PORT_CAP_ANEG)
2451 v |= SUPPORTED_Autoneg;
2452 return v;
2453}
2454
2455static unsigned int to_fw_linkcaps(unsigned int caps)
2456{
2457 unsigned int v = 0;
2458
2459 if (caps & ADVERTISED_100baseT_Full)
2460 v |= FW_PORT_CAP_SPEED_100M;
2461 if (caps & ADVERTISED_1000baseT_Full)
2462 v |= FW_PORT_CAP_SPEED_1G;
2463 if (caps & ADVERTISED_10000baseT_Full)
2464 v |= FW_PORT_CAP_SPEED_10G;
72aca4bf
KS		 2465 if (caps & ADVERTISED_40000baseSR4_Full)
2466 v |= FW_PORT_CAP_SPEED_40G;
b8ff05a9
DM		 2467 return v;
2468}
2469
2470static int get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2471{
2472 const struct port_info *p = netdev_priv(dev);
2473
2474 if (p->port_type == FW_PORT_TYPE_BT_SGMII ||
a0881cab 2475 p->port_type == FW_PORT_TYPE_BT_XFI ||
b8ff05a9
DM		 2476 p->port_type == FW_PORT_TYPE_BT_XAUI)
2477 cmd->port = PORT_TP;
a0881cab
DM		 2478 else if (p->port_type == FW_PORT_TYPE_FIBER_XFI ||
2479 p->port_type == FW_PORT_TYPE_FIBER_XAUI)
b8ff05a9 2480 cmd->port = PORT_FIBRE;
3e00a509
HS		 2481 else if (p->port_type == FW_PORT_TYPE_SFP ||
2482 p->port_type == FW_PORT_TYPE_QSFP_10G ||
2483 p->port_type == FW_PORT_TYPE_QSFP) {
2484 if (p->mod_type == FW_PORT_MOD_TYPE_LR ||
2485 p->mod_type == FW_PORT_MOD_TYPE_SR ||
2486 p->mod_type == FW_PORT_MOD_TYPE_ER ||
2487 p->mod_type == FW_PORT_MOD_TYPE_LRM)
2488 cmd->port = PORT_FIBRE;
2489 else if (p->mod_type == FW_PORT_MOD_TYPE_TWINAX_PASSIVE ||
2490 p->mod_type == FW_PORT_MOD_TYPE_TWINAX_ACTIVE)
a0881cab
DM		 2491 cmd->port = PORT_DA;
2492 else
3e00a509 2493 cmd->port = PORT_OTHER;
a0881cab 2494 } else
b8ff05a9
DM		 2495 cmd->port = PORT_OTHER;
2496
2497 if (p->mdio_addr >= 0) {
2498 cmd->phy_address = p->mdio_addr;
2499 cmd->transceiver = XCVR_EXTERNAL;
2500 cmd->mdio_support = p->port_type == FW_PORT_TYPE_BT_SGMII ?
2501 MDIO_SUPPORTS_C22 : MDIO_SUPPORTS_C45;
2502 } else {
2503 cmd->phy_address = 0; /* not really, but no better option */
2504 cmd->transceiver = XCVR_INTERNAL;
2505 cmd->mdio_support = 0;
2506 }
2507
2508 cmd->supported = from_fw_linkcaps(p->port_type, p->link_cfg.supported);
2509 cmd->advertising = from_fw_linkcaps(p->port_type,
2510 p->link_cfg.advertising);
70739497
DD		 2511 ethtool_cmd_speed_set(cmd,
2512 netif_carrier_ok(dev) ? p->link_cfg.speed : 0);
b8ff05a9
DM		 2513 cmd->duplex = DUPLEX_FULL;
2514 cmd->autoneg = p->link_cfg.autoneg;
2515 cmd->maxtxpkt = 0;
2516 cmd->maxrxpkt = 0;
2517 return 0;
2518}
2519
2520static unsigned int speed_to_caps(int speed)
2521{
e8b39015 2522 if (speed == 100)
b8ff05a9 2523 return FW_PORT_CAP_SPEED_100M;
e8b39015 2524 if (speed == 1000)
b8ff05a9 2525 return FW_PORT_CAP_SPEED_1G;
e8b39015 2526 if (speed == 10000)
b8ff05a9 2527 return FW_PORT_CAP_SPEED_10G;
e8b39015 2528 if (speed == 40000)
72aca4bf 2529 return FW_PORT_CAP_SPEED_40G;
b8ff05a9
DM		 2530 return 0;
2531}
2532
2533static int set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2534{
2535 unsigned int cap;
2536 struct port_info *p = netdev_priv(dev);
2537 struct link_config *lc = &p->link_cfg;
25db0338 2538 u32 speed = ethtool_cmd_speed(cmd);
b8ff05a9
DM		 2539
2540 if (cmd->duplex != DUPLEX_FULL) /* only full-duplex supported */
2541 return -EINVAL;
2542
2543 if (!(lc->supported & FW_PORT_CAP_ANEG)) {
2544 /*
2545 * PHY offers a single speed. See if that's what's
2546 * being requested.
2547 */
2548 if (cmd->autoneg == AUTONEG_DISABLE &&
25db0338
DD		 2549 (lc->supported & speed_to_caps(speed)))
2550 return 0;
b8ff05a9
DM		 2551 return -EINVAL;
2552 }
2553
2554 if (cmd->autoneg == AUTONEG_DISABLE) {
25db0338 2555 cap = speed_to_caps(speed);
b8ff05a9 2556
72aca4bf 2557 if (!(lc->supported & cap) ||
e8b39015
BH		 2558 (speed == 1000) ||
2559 (speed == 10000) ||
72aca4bf 2560 (speed == 40000))
b8ff05a9
DM		 2561 return -EINVAL;
2562 lc->requested_speed = cap;
2563 lc->advertising = 0;
2564 } else {
2565 cap = to_fw_linkcaps(cmd->advertising);
2566 if (!(lc->supported & cap))
2567 return -EINVAL;
2568 lc->requested_speed = 0;
2569 lc->advertising = cap | FW_PORT_CAP_ANEG;
2570 }
2571 lc->autoneg = cmd->autoneg;
2572
2573 if (netif_running(dev))
060e0c75
DM		 2574 return t4_link_start(p->adapter, p->adapter->fn, p->tx_chan,
2575 lc);
b8ff05a9
DM		 2576 return 0;
2577}
2578
2579static void get_pauseparam(struct net_device *dev,
2580 struct ethtool_pauseparam *epause)
2581{
2582 struct port_info *p = netdev_priv(dev);
2583
2584 epause->autoneg = (p->link_cfg.requested_fc & PAUSE_AUTONEG) != 0;
2585 epause->rx_pause = (p->link_cfg.fc & PAUSE_RX) != 0;
2586 epause->tx_pause = (p->link_cfg.fc & PAUSE_TX) != 0;
2587}
2588
2589static int set_pauseparam(struct net_device *dev,
2590 struct ethtool_pauseparam *epause)
2591{
2592 struct port_info *p = netdev_priv(dev);
2593 struct link_config *lc = &p->link_cfg;
2594
2595 if (epause->autoneg == AUTONEG_DISABLE)
2596 lc->requested_fc = 0;
2597 else if (lc->supported & FW_PORT_CAP_ANEG)
2598 lc->requested_fc = PAUSE_AUTONEG;
2599 else
2600 return -EINVAL;
2601
2602 if (epause->rx_pause)
2603 lc->requested_fc |= PAUSE_RX;
2604 if (epause->tx_pause)
2605 lc->requested_fc |= PAUSE_TX;
2606 if (netif_running(dev))
060e0c75
DM		 2607 return t4_link_start(p->adapter, p->adapter->fn, p->tx_chan,
2608 lc);
b8ff05a9
DM		 2609 return 0;
2610}
2611
b8ff05a9
DM		 2612static void get_sge_param(struct net_device *dev, struct ethtool_ringparam *e)
2613{
2614 const struct port_info *pi = netdev_priv(dev);
2615 const struct sge *s = &pi->adapter->sge;
2616
2617 e->rx_max_pending = MAX_RX_BUFFERS;
2618 e->rx_mini_max_pending = MAX_RSPQ_ENTRIES;
2619 e->rx_jumbo_max_pending = 0;
2620 e->tx_max_pending = MAX_TXQ_ENTRIES;
2621
2622 e->rx_pending = s->ethrxq[pi->first_qset].fl.size - 8;
2623 e->rx_mini_pending = s->ethrxq[pi->first_qset].rspq.size;
2624 e->rx_jumbo_pending = 0;
2625 e->tx_pending = s->ethtxq[pi->first_qset].q.size;
2626}
2627
2628static int set_sge_param(struct net_device *dev, struct ethtool_ringparam *e)
2629{
2630 int i;
2631 const struct port_info *pi = netdev_priv(dev);
2632 struct adapter *adapter = pi->adapter;
2633 struct sge *s = &adapter->sge;
2634
2635 if (e->rx_pending > MAX_RX_BUFFERS || e->rx_jumbo_pending ||
2636 e->tx_pending > MAX_TXQ_ENTRIES ||
2637 e->rx_mini_pending > MAX_RSPQ_ENTRIES ||
2638 e->rx_mini_pending < MIN_RSPQ_ENTRIES ||
2639 e->rx_pending < MIN_FL_ENTRIES || e->tx_pending < MIN_TXQ_ENTRIES)
2640 return -EINVAL;
2641
2642 if (adapter->flags & FULL_INIT_DONE)
2643 return -EBUSY;
2644
2645 for (i = 0; i < pi->nqsets; ++i) {
2646 s->ethtxq[pi->first_qset + i].q.size = e->tx_pending;
2647 s->ethrxq[pi->first_qset + i].fl.size = e->rx_pending + 8;
2648 s->ethrxq[pi->first_qset + i].rspq.size = e->rx_mini_pending;
2649 }
2650 return 0;
2651}
2652
2653static int closest_timer(const struct sge *s, int time)
2654{
2655 int i, delta, match = 0, min_delta = INT_MAX;
2656
2657 for (i = 0; i < ARRAY_SIZE(s->timer_val); i++) {
2658 delta = time - s->timer_val[i];
2659 if (delta < 0)
2660 delta = -delta;
2661 if (delta < min_delta) {
2662 min_delta = delta;
2663 match = i;
2664 }
2665 }
2666 return match;
2667}
2668
2669static int closest_thres(const struct sge *s, int thres)
2670{
2671 int i, delta, match = 0, min_delta = INT_MAX;
2672
2673 for (i = 0; i < ARRAY_SIZE(s->counter_val); i++) {
2674 delta = thres - s->counter_val[i];
2675 if (delta < 0)
2676 delta = -delta;
2677 if (delta < min_delta) {
2678 min_delta = delta;
2679 match = i;
2680 }
2681 }
2682 return match;
2683}
2684
2685/*
2686 * Return a queue's interrupt hold-off time in us. 0 means no timer.
2687 */
2688static unsigned int qtimer_val(const struct adapter *adap,
2689 const struct sge_rspq *q)
2690{
2691 unsigned int idx = q->intr_params >> 1;
2692
2693 return idx < SGE_NTIMERS ? adap->sge.timer_val[idx] : 0;
2694}
2695
2696/**
c887ad0e 2697 * set_rspq_intr_params - set a queue's interrupt holdoff parameters
b8ff05a9
DM		 2698 * @q: the Rx queue
2699 * @us: the hold-off time in us, or 0 to disable timer
2700 * @cnt: the hold-off packet count, or 0 to disable counter
2701 *
2702 * Sets an Rx queue's interrupt hold-off time and packet count. At least
2703 * one of the two needs to be enabled for the queue to generate interrupts.
2704 */
c887ad0e
HS		 2705static int set_rspq_intr_params(struct sge_rspq *q,
2706 unsigned int us, unsigned int cnt)
b8ff05a9 2707{
c887ad0e
HS		 2708 struct adapter *adap = q->adap;
2709
b8ff05a9
DM		 2710 if ((us | cnt) == 0)
2711 cnt = 1;
2712
2713 if (cnt) {
2714 int err;
2715 u32 v, new_idx;
2716
2717 new_idx = closest_thres(&adap->sge, cnt);
2718 if (q->desc && q->pktcnt_idx != new_idx) {
2719 /* the queue has already been created, update it */
2720 v = FW_PARAMS_MNEM(FW_PARAMS_MNEM_DMAQ) |
2721 FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DMAQ_IQ_INTCNTTHRESH) |
2722 FW_PARAMS_PARAM_YZ(q->cntxt_id);
060e0c75
DM		 2723 err = t4_set_params(adap, adap->fn, adap->fn, 0, 1, &v,
2724 &new_idx);
b8ff05a9
DM		 2725 if (err)
2726 return err;
2727 }
2728 q->pktcnt_idx = new_idx;
2729 }
2730
2731 us = us == 0 ? 6 : closest_timer(&adap->sge, us);
2732 q->intr_params = QINTR_TIMER_IDX(us) | (cnt > 0 ? QINTR_CNT_EN : 0);
2733 return 0;
2734}
2735
c887ad0e
HS		 2736/**
2737 * set_rx_intr_params - set a net devices's RX interrupt holdoff paramete!
2738 * @dev: the network device
2739 * @us: the hold-off time in us, or 0 to disable timer
2740 * @cnt: the hold-off packet count, or 0 to disable counter
2741 *
2742 * Set the RX interrupt hold-off parameters for a network device.
2743 */
2744static int set_rx_intr_params(struct net_device *dev,
2745 unsigned int us, unsigned int cnt)
b8ff05a9 2746{
c887ad0e
HS		 2747 int i, err;
2748 struct port_info *pi = netdev_priv(dev);
b8ff05a9 2749 struct adapter *adap = pi->adapter;
c887ad0e
HS		 2750 struct sge_eth_rxq *q = &adap->sge.ethrxq[pi->first_qset];
2751
2752 for (i = 0; i < pi->nqsets; i++, q++) {
2753 err = set_rspq_intr_params(&q->rspq, us, cnt);
2754 if (err)
2755 return err;
d4fc9dc2 2756 }
c887ad0e
HS		 2757 return 0;
2758}
2759
e553ec3f
HS		 2760static int set_adaptive_rx_setting(struct net_device *dev, int adaptive_rx)
2761{
2762 int i;
2763 struct port_info *pi = netdev_priv(dev);
2764 struct adapter *adap = pi->adapter;
2765 struct sge_eth_rxq *q = &adap->sge.ethrxq[pi->first_qset];
2766
2767 for (i = 0; i < pi->nqsets; i++, q++)
2768 q->rspq.adaptive_rx = adaptive_rx;
2769
2770 return 0;
2771}
2772
2773static int get_adaptive_rx_setting(struct net_device *dev)
2774{
2775 struct port_info *pi = netdev_priv(dev);
2776 struct adapter *adap = pi->adapter;
2777 struct sge_eth_rxq *q = &adap->sge.ethrxq[pi->first_qset];
2778
2779 return q->rspq.adaptive_rx;
2780}
2781
c887ad0e
HS		 2782static int set_coalesce(struct net_device *dev, struct ethtool_coalesce *c)
2783{
e553ec3f 2784 set_adaptive_rx_setting(dev, c->use_adaptive_rx_coalesce);
c887ad0e
HS		 2785 return set_rx_intr_params(dev, c->rx_coalesce_usecs,
2786 c->rx_max_coalesced_frames);
b8ff05a9
DM		 2787}
2788
2789static int get_coalesce(struct net_device *dev, struct ethtool_coalesce *c)
2790{
2791 const struct port_info *pi = netdev_priv(dev);
2792 const struct adapter *adap = pi->adapter;
2793 const struct sge_rspq *rq = &adap->sge.ethrxq[pi->first_qset].rspq;
2794
2795 c->rx_coalesce_usecs = qtimer_val(adap, rq);
2796 c->rx_max_coalesced_frames = (rq->intr_params & QINTR_CNT_EN) ?
2797 adap->sge.counter_val[rq->pktcnt_idx] : 0;
e553ec3f 2798 c->use_adaptive_rx_coalesce = get_adaptive_rx_setting(dev);
b8ff05a9
DM		 2799 return 0;
2800}
2801
1478b3ee
DM		 2802/**
2803 * eeprom_ptov - translate a physical EEPROM address to virtual
2804 * @phys_addr: the physical EEPROM address
2805 * @fn: the PCI function number
2806 * @sz: size of function-specific area
2807 *
2808 * Translate a physical EEPROM address to virtual. The first 1K is
2809 * accessed through virtual addresses starting at 31K, the rest is
2810 * accessed through virtual addresses starting at 0.
2811 *
2812 * The mapping is as follows:
2813 * [0..1K) -> [31K..32K)
2814 * [1K..1K+A) -> [31K-A..31K)
2815 * [1K+A..ES) -> [0..ES-A-1K)
2816 *
2817 * where A = @fn * @sz, and ES = EEPROM size.
b8ff05a9 2818 */
1478b3ee 2819static int eeprom_ptov(unsigned int phys_addr, unsigned int fn, unsigned int sz)
b8ff05a9 2820{
1478b3ee 2821 fn *= sz;
b8ff05a9
DM		 2822 if (phys_addr < 1024)
2823 return phys_addr + (31 << 10);
1478b3ee
DM		 2824 if (phys_addr < 1024 + fn)
2825 return 31744 - fn + phys_addr - 1024;
b8ff05a9 2826 if (phys_addr < EEPROMSIZE)
1478b3ee 2827 return phys_addr - 1024 - fn;
b8ff05a9
DM		 2828 return -EINVAL;
2829}
2830
2831/*
2832 * The next two routines implement eeprom read/write from physical addresses.
b8ff05a9
DM		 2833 */
2834static int eeprom_rd_phys(struct adapter *adap, unsigned int phys_addr, u32 *v)
2835{
1478b3ee 2836 int vaddr = eeprom_ptov(phys_addr, adap->fn, EEPROMPFSIZE);
b8ff05a9
DM		 2837
2838 if (vaddr >= 0)
2839 vaddr = pci_read_vpd(adap->pdev, vaddr, sizeof(u32), v);
2840 return vaddr < 0 ? vaddr : 0;
2841}
2842
2843static int eeprom_wr_phys(struct adapter *adap, unsigned int phys_addr, u32 v)
2844{
1478b3ee 2845 int vaddr = eeprom_ptov(phys_addr, adap->fn, EEPROMPFSIZE);
b8ff05a9
DM		 2846
2847 if (vaddr >= 0)
2848 vaddr = pci_write_vpd(adap->pdev, vaddr, sizeof(u32), &v);
2849 return vaddr < 0 ? vaddr : 0;
2850}
2851
2852#define EEPROM_MAGIC 0x38E2F10C
2853
2854static int get_eeprom(struct net_device *dev, struct ethtool_eeprom *e,
2855 u8 *data)
2856{
2857 int i, err = 0;
2858 struct adapter *adapter = netdev2adap(dev);
2859
2860 u8 *buf = kmalloc(EEPROMSIZE, GFP_KERNEL);
2861 if (!buf)
2862 return -ENOMEM;
2863
2864 e->magic = EEPROM_MAGIC;
2865 for (i = e->offset & ~3; !err && i < e->offset + e->len; i += 4)
2866 err = eeprom_rd_phys(adapter, i, (u32 *)&buf[i]);
2867
2868 if (!err)
2869 memcpy(data, buf + e->offset, e->len);
2870 kfree(buf);
2871 return err;
2872}
2873
2874static int set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
2875 u8 *data)
2876{
2877 u8 *buf;
2878 int err = 0;
2879 u32 aligned_offset, aligned_len, *p;
2880 struct adapter *adapter = netdev2adap(dev);
2881
2882 if (eeprom->magic != EEPROM_MAGIC)
2883 return -EINVAL;
2884
2885 aligned_offset = eeprom->offset & ~3;
2886 aligned_len = (eeprom->len + (eeprom->offset & 3) + 3) & ~3;
2887
1478b3ee
DM		 2888 if (adapter->fn > 0) {
2889 u32 start = 1024 + adapter->fn * EEPROMPFSIZE;
2890
2891 if (aligned_offset < start ||
2892 aligned_offset + aligned_len > start + EEPROMPFSIZE)
2893 return -EPERM;
2894 }
2895
b8ff05a9
DM		 2896 if (aligned_offset != eeprom->offset || aligned_len != eeprom->len) {
2897 /*
2898 * RMW possibly needed for first or last words.
2899 */
2900 buf = kmalloc(aligned_len, GFP_KERNEL);
2901 if (!buf)
2902 return -ENOMEM;
2903 err = eeprom_rd_phys(adapter, aligned_offset, (u32 *)buf);
2904 if (!err && aligned_len > 4)
2905 err = eeprom_rd_phys(adapter,
2906 aligned_offset + aligned_len - 4,
2907 (u32 *)&buf[aligned_len - 4]);
2908 if (err)
2909 goto out;
2910 memcpy(buf + (eeprom->offset & 3), data, eeprom->len);
2911 } else
2912 buf = data;
2913
2914 err = t4_seeprom_wp(adapter, false);
2915 if (err)
2916 goto out;
2917
2918 for (p = (u32 *)buf; !err && aligned_len; aligned_len -= 4, p++) {
2919 err = eeprom_wr_phys(adapter, aligned_offset, *p);
2920 aligned_offset += 4;
2921 }
2922
2923 if (!err)
2924 err = t4_seeprom_wp(adapter, true);
2925out:
2926 if (buf != data)
2927 kfree(buf);
2928 return err;
2929}
2930
2931static int set_flash(struct net_device *netdev, struct ethtool_flash *ef)
2932{
2933 int ret;
2934 const struct firmware *fw;
2935 struct adapter *adap = netdev2adap(netdev);
22c0b963 2936 unsigned int mbox = FW_PCIE_FW_MASTER_MASK + 1;
b8ff05a9
DM		 2937
2938 ef->data[sizeof(ef->data) - 1] = '\0';
2939 ret = request_firmware(&fw, ef->data, adap->pdev_dev);
2940 if (ret < 0)
2941 return ret;
2942
22c0b963
HS		 2943 /* If the adapter has been fully initialized then we'll go ahead and
2944 * try to get the firmware's cooperation in upgrading to the new
2945 * firmware image otherwise we'll try to do the entire job from the
2946 * host ... and we always "force" the operation in this path.
2947 */
2948 if (adap->flags & FULL_INIT_DONE)
2949 mbox = adap->mbox;
2950
2951 ret = t4_fw_upgrade(adap, mbox, fw->data, fw->size, 1);
b8ff05a9
DM		 2952 release_firmware(fw);
2953 if (!ret)
22c0b963
HS		 2954 dev_info(adap->pdev_dev, "loaded firmware %s,"
2955 " reload cxgb4 driver\n", ef->data);
b8ff05a9
DM		 2956 return ret;
2957}
2958
2959#define WOL_SUPPORTED (WAKE_BCAST | WAKE_MAGIC)
2960#define BCAST_CRC 0xa0ccc1a6
2961
2962static void get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2963{
2964 wol->supported = WAKE_BCAST | WAKE_MAGIC;
2965 wol->wolopts = netdev2adap(dev)->wol;
2966 memset(&wol->sopass, 0, sizeof(wol->sopass));
2967}
2968
2969static int set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2970{
2971 int err = 0;
2972 struct port_info *pi = netdev_priv(dev);
2973
2974 if (wol->wolopts & ~WOL_SUPPORTED)
2975 return -EINVAL;
2976 t4_wol_magic_enable(pi->adapter, pi->tx_chan,
2977 (wol->wolopts & WAKE_MAGIC) ? dev->dev_addr : NULL);
2978 if (wol->wolopts & WAKE_BCAST) {
2979 err = t4_wol_pat_enable(pi->adapter, pi->tx_chan, 0xfe, ~0ULL,
2980 ~0ULL, 0, false);
2981 if (!err)
2982 err = t4_wol_pat_enable(pi->adapter, pi->tx_chan, 1,
2983 ~6ULL, ~0ULL, BCAST_CRC, true);
2984 } else
2985 t4_wol_pat_enable(pi->adapter, pi->tx_chan, 0, 0, 0, 0, false);
2986 return err;
2987}
2988
c8f44aff 2989static int cxgb_set_features(struct net_device *dev, netdev_features_t features)
87b6cf51 2990{
2ed28baa 2991 const struct port_info *pi = netdev_priv(dev);
c8f44aff 2992 netdev_features_t changed = dev->features ^ features;
19ecae2c 2993 int err;
19ecae2c 2994
f646968f 2995 if (!(changed & NETIF_F_HW_VLAN_CTAG_RX))
2ed28baa 2996 return 0;
19ecae2c 2997
2ed28baa
MM		 2998 err = t4_set_rxmode(pi->adapter, pi->adapter->fn, pi->viid, -1,
2999 -1, -1, -1,
f646968f 3000 !!(features & NETIF_F_HW_VLAN_CTAG_RX), true);
2ed28baa 3001 if (unlikely(err))
f646968f 3002 dev->features = features ^ NETIF_F_HW_VLAN_CTAG_RX;
19ecae2c 3003 return err;
87b6cf51
DM		 3004}
3005
7850f63f 3006static u32 get_rss_table_size(struct net_device *dev)
671b0060
DM		 3007{
3008 const struct port_info *pi = netdev_priv(dev);
671b0060 3009
7850f63f
BH		 3010 return pi->rss_size;
3011}
3012
fe62d001 3013static int get_rss_table(struct net_device *dev, u32 *p, u8 *key)
7850f63f
BH		 3014{
3015 const struct port_info *pi = netdev_priv(dev);
3016 unsigned int n = pi->rss_size;
3017
671b0060 3018 while (n--)
7850f63f 3019 p[n] = pi->rss[n];
671b0060
DM		 3020 return 0;
3021}
3022
fe62d001 3023static int set_rss_table(struct net_device *dev, const u32 *p, const u8 *key)
671b0060
DM		 3024{
3025 unsigned int i;
3026 struct port_info *pi = netdev_priv(dev);
3027
7850f63f
BH		 3028 for (i = 0; i < pi->rss_size; i++)
3029 pi->rss[i] = p[i];
671b0060
DM		 3030 if (pi->adapter->flags & FULL_INIT_DONE)
3031 return write_rss(pi, pi->rss);
3032 return 0;
3033}
3034
3035static int get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *info,
815c7db5 3036 u32 *rules)
671b0060 3037{
f796564a
DM		 3038 const struct port_info *pi = netdev_priv(dev);
3039
671b0060 3040 switch (info->cmd) {
f796564a
DM		 3041 case ETHTOOL_GRXFH: {
3042 unsigned int v = pi->rss_mode;
3043
3044 info->data = 0;
3045 switch (info->flow_type) {
3046 case TCP_V4_FLOW:
3047 if (v & FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN)
3048 info->data = RXH_IP_SRC | RXH_IP_DST |
3049 RXH_L4_B_0_1 | RXH_L4_B_2_3;
3050 else if (v & FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN)
3051 info->data = RXH_IP_SRC | RXH_IP_DST;
3052 break;
3053 case UDP_V4_FLOW:
3054 if ((v & FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN) &&
3055 (v & FW_RSS_VI_CONFIG_CMD_UDPEN))
3056 info->data = RXH_IP_SRC | RXH_IP_DST |
3057 RXH_L4_B_0_1 | RXH_L4_B_2_3;
3058 else if (v & FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN)
3059 info->data = RXH_IP_SRC | RXH_IP_DST;
3060 break;
3061 case SCTP_V4_FLOW:
3062 case AH_ESP_V4_FLOW:
3063 case IPV4_FLOW:
3064 if (v & FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN)
3065 info->data = RXH_IP_SRC | RXH_IP_DST;
3066 break;
3067 case TCP_V6_FLOW:
3068 if (v & FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN)
3069 info->data = RXH_IP_SRC | RXH_IP_DST |
3070 RXH_L4_B_0_1 | RXH_L4_B_2_3;
3071 else if (v & FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN)
3072 info->data = RXH_IP_SRC | RXH_IP_DST;
3073 break;
3074 case UDP_V6_FLOW:
3075 if ((v & FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN) &&
3076 (v & FW_RSS_VI_CONFIG_CMD_UDPEN))
3077 info->data = RXH_IP_SRC | RXH_IP_DST |
3078 RXH_L4_B_0_1 | RXH_L4_B_2_3;
3079 else if (v & FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN)
3080 info->data = RXH_IP_SRC | RXH_IP_DST;
3081 break;
3082 case SCTP_V6_FLOW:
3083 case AH_ESP_V6_FLOW:
3084 case IPV6_FLOW:
3085 if (v & FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN)
3086 info->data = RXH_IP_SRC | RXH_IP_DST;
3087 break;
3088 }
3089 return 0;
3090 }
671b0060 3091 case ETHTOOL_GRXRINGS:
f796564a 3092 info->data = pi->nqsets;
671b0060
DM		 3093 return 0;
3094 }
3095 return -EOPNOTSUPP;
3096}
3097
9b07be4b 3098static const struct ethtool_ops cxgb_ethtool_ops = {
b8ff05a9
DM		 3099 .get_settings = get_settings,
3100 .set_settings = set_settings,
3101 .get_drvinfo = get_drvinfo,
3102 .get_msglevel = get_msglevel,
3103 .set_msglevel = set_msglevel,
3104 .get_ringparam = get_sge_param,
3105 .set_ringparam = set_sge_param,
3106 .get_coalesce = get_coalesce,
3107 .set_coalesce = set_coalesce,
3108 .get_eeprom_len = get_eeprom_len,
3109 .get_eeprom = get_eeprom,
3110 .set_eeprom = set_eeprom,
3111 .get_pauseparam = get_pauseparam,
3112 .set_pauseparam = set_pauseparam,
b8ff05a9
DM		 3113 .get_link = ethtool_op_get_link,
3114 .get_strings = get_strings,
c5e06360 3115 .set_phys_id = identify_port,
b8ff05a9
DM		 3116 .nway_reset = restart_autoneg,
3117 .get_sset_count = get_sset_count,
3118 .get_ethtool_stats = get_stats,
3119 .get_regs_len = get_regs_len,
3120 .get_regs = get_regs,
3121 .get_wol = get_wol,
3122 .set_wol = set_wol,
671b0060 3123 .get_rxnfc = get_rxnfc,
7850f63f 3124 .get_rxfh_indir_size = get_rss_table_size,
fe62d001
BH		 3125 .get_rxfh = get_rss_table,
3126 .set_rxfh = set_rss_table,
b8ff05a9
DM		 3127 .flash_device = set_flash,
3128};
3129
3130/*
3131 * debugfs support
3132 */
b8ff05a9
DM		 3133static ssize_t mem_read(struct file *file, char __user *buf, size_t count,
3134 loff_t *ppos)
3135{
3136 loff_t pos = *ppos;
496ad9aa 3137 loff_t avail = file_inode(file)->i_size;
b8ff05a9
DM		 3138 unsigned int mem = (uintptr_t)file->private_data & 3;
3139 struct adapter *adap = file->private_data - mem;
fc5ab020
HS		 3140 __be32 *data;
3141 int ret;
b8ff05a9
DM		 3142
3143 if (pos < 0)
3144 return -EINVAL;
3145 if (pos >= avail)
3146 return 0;
3147 if (count > avail - pos)
3148 count = avail - pos;
3149
fc5ab020
HS		 3150 data = t4_alloc_mem(count);
3151 if (!data)
3152 return -ENOMEM;
b8ff05a9 3153
fc5ab020
HS		 3154 spin_lock(&adap->win0_lock);
3155 ret = t4_memory_rw(adap, 0, mem, pos, count, data, T4_MEMORY_READ);
3156 spin_unlock(&adap->win0_lock);
3157 if (ret) {
3158 t4_free_mem(data);
3159 return ret;
3160 }
3161 ret = copy_to_user(buf, data, count);
b8ff05a9 3162
fc5ab020
HS		 3163 t4_free_mem(data);
3164 if (ret)
3165 return -EFAULT;
b8ff05a9 3166
fc5ab020 3167 *ppos = pos + count;
b8ff05a9
DM		 3168 return count;
3169}
3170
3171static const struct file_operations mem_debugfs_fops = {
3172 .owner = THIS_MODULE,
234e3405 3173 .open = simple_open,
b8ff05a9 3174 .read = mem_read,
6038f373 3175 .llseek = default_llseek,
b8ff05a9
DM		 3176};
3177
91744948 3178static void add_debugfs_mem(struct adapter *adap, const char *name,
1dd06ae8 3179 unsigned int idx, unsigned int size_mb)
b8ff05a9
DM		 3180{
3181 struct dentry *de;
3182
3183 de = debugfs_create_file(name, S_IRUSR, adap->debugfs_root,
3184 (void *)adap + idx, &mem_debugfs_fops);
3185 if (de && de->d_inode)
3186 de->d_inode->i_size = size_mb << 20;
3187}
3188
91744948 3189static int setup_debugfs(struct adapter *adap)
b8ff05a9
DM		 3190{
3191 int i;
19dd37ba 3192 u32 size;
b8ff05a9
DM		 3193
3194 if (IS_ERR_OR_NULL(adap->debugfs_root))
3195 return -1;
3196
3197 i = t4_read_reg(adap, MA_TARGET_MEM_ENABLE);
19dd37ba
SR		 3198 if (i & EDRAM0_ENABLE) {
3199 size = t4_read_reg(adap, MA_EDRAM0_BAR);
3200 add_debugfs_mem(adap, "edc0", MEM_EDC0, EDRAM_SIZE_GET(size));
3201 }
3202 if (i & EDRAM1_ENABLE) {
3203 size = t4_read_reg(adap, MA_EDRAM1_BAR);
3204 add_debugfs_mem(adap, "edc1", MEM_EDC1, EDRAM_SIZE_GET(size));
3205 }
d14807dd 3206 if (is_t4(adap->params.chip)) {
19dd37ba
SR		 3207 size = t4_read_reg(adap, MA_EXT_MEMORY_BAR);
3208 if (i & EXT_MEM_ENABLE)
3209 add_debugfs_mem(adap, "mc", MEM_MC,
3210 EXT_MEM_SIZE_GET(size));
3211 } else {
3212 if (i & EXT_MEM_ENABLE) {
3213 size = t4_read_reg(adap, MA_EXT_MEMORY_BAR);
3214 add_debugfs_mem(adap, "mc0", MEM_MC0,
3215 EXT_MEM_SIZE_GET(size));
3216 }
3217 if (i & EXT_MEM1_ENABLE) {
3218 size = t4_read_reg(adap, MA_EXT_MEMORY1_BAR);
3219 add_debugfs_mem(adap, "mc1", MEM_MC1,
3220 EXT_MEM_SIZE_GET(size));
3221 }
3222 }
b8ff05a9
DM		 3223 if (adap->l2t)
3224 debugfs_create_file("l2t", S_IRUSR, adap->debugfs_root, adap,
3225 &t4_l2t_fops);
3226 return 0;
3227}
3228
3229/*
3230 * upper-layer driver support
3231 */
3232
3233/*
3234 * Allocate an active-open TID and set it to the supplied value.
3235 */
3236int cxgb4_alloc_atid(struct tid_info *t, void *data)
3237{
3238 int atid = -1;
3239
3240 spin_lock_bh(&t->atid_lock);
3241 if (t->afree) {
3242 union aopen_entry *p = t->afree;
3243
f2b7e78d 3244 atid = (p - t->atid_tab) + t->atid_base;
b8ff05a9
DM		 3245 t->afree = p->next;
3246 p->data = data;
3247 t->atids_in_use++;
3248 }
3249 spin_unlock_bh(&t->atid_lock);
3250 return atid;
3251}
3252EXPORT_SYMBOL(cxgb4_alloc_atid);
3253
3254/*
3255 * Release an active-open TID.
3256 */
3257void cxgb4_free_atid(struct tid_info *t, unsigned int atid)
3258{
f2b7e78d 3259 union aopen_entry *p = &t->atid_tab[atid - t->atid_base];
b8ff05a9
DM		 3260
3261 spin_lock_bh(&t->atid_lock);
3262 p->next = t->afree;
3263 t->afree = p;
3264 t->atids_in_use--;
3265 spin_unlock_bh(&t->atid_lock);
3266}
3267EXPORT_SYMBOL(cxgb4_free_atid);
3268
3269/*
3270 * Allocate a server TID and set it to the supplied value.
3271 */
3272int cxgb4_alloc_stid(struct tid_info *t, int family, void *data)
3273{
3274 int stid;
3275
3276 spin_lock_bh(&t->stid_lock);
3277 if (family == PF_INET) {
3278 stid = find_first_zero_bit(t->stid_bmap, t->nstids);
3279 if (stid < t->nstids)
3280 __set_bit(stid, t->stid_bmap);
3281 else
3282 stid = -1;
3283 } else {
3284 stid = bitmap_find_free_region(t->stid_bmap, t->nstids, 2);
3285 if (stid < 0)
3286 stid = -1;
3287 }
3288 if (stid >= 0) {
3289 t->stid_tab[stid].data = data;
3290 stid += t->stid_base;
15f63b74
KS		 3291 /* IPv6 requires max of 520 bits or 16 cells in TCAM
3292 * This is equivalent to 4 TIDs. With CLIP enabled it
3293 * needs 2 TIDs.
3294 */
3295 if (family == PF_INET)
3296 t->stids_in_use++;
3297 else
3298 t->stids_in_use += 4;
b8ff05a9
DM		 3299 }
3300 spin_unlock_bh(&t->stid_lock);
3301 return stid;
3302}
3303EXPORT_SYMBOL(cxgb4_alloc_stid);
3304
dca4faeb
VP		 3305/* Allocate a server filter TID and set it to the supplied value.
3306 */
3307int cxgb4_alloc_sftid(struct tid_info *t, int family, void *data)
3308{
3309 int stid;
3310
3311 spin_lock_bh(&t->stid_lock);
3312 if (family == PF_INET) {
3313 stid = find_next_zero_bit(t->stid_bmap,
3314 t->nstids + t->nsftids, t->nstids);
3315 if (stid < (t->nstids + t->nsftids))
3316 __set_bit(stid, t->stid_bmap);
3317 else
3318 stid = -1;
3319 } else {
3320 stid = -1;
3321 }
3322 if (stid >= 0) {
3323 t->stid_tab[stid].data = data;
470c60c4
KS		 3324 stid -= t->nstids;
3325 stid += t->sftid_base;
dca4faeb
VP		 3326 t->stids_in_use++;
3327 }
3328 spin_unlock_bh(&t->stid_lock);
3329 return stid;
3330}
3331EXPORT_SYMBOL(cxgb4_alloc_sftid);
3332
3333/* Release a server TID.
b8ff05a9
DM		 3334 */
3335void cxgb4_free_stid(struct tid_info *t, unsigned int stid, int family)
3336{
470c60c4
KS		 3337 /* Is it a server filter TID? */
3338 if (t->nsftids && (stid >= t->sftid_base)) {
3339 stid -= t->sftid_base;
3340 stid += t->nstids;
3341 } else {
3342 stid -= t->stid_base;
3343 }
3344
b8ff05a9
DM		 3345 spin_lock_bh(&t->stid_lock);
3346 if (family == PF_INET)
3347 __clear_bit(stid, t->stid_bmap);
3348 else
3349 bitmap_release_region(t->stid_bmap, stid, 2);
3350 t->stid_tab[stid].data = NULL;
15f63b74
KS		 3351 if (family == PF_INET)
3352 t->stids_in_use--;
3353 else
3354 t->stids_in_use -= 4;
b8ff05a9
DM		 3355 spin_unlock_bh(&t->stid_lock);
3356}
3357EXPORT_SYMBOL(cxgb4_free_stid);
3358
3359/*
3360 * Populate a TID_RELEASE WR. Caller must properly size the skb.
3361 */
3362static void mk_tid_release(struct sk_buff *skb, unsigned int chan,
3363 unsigned int tid)
3364{
3365 struct cpl_tid_release *req;
3366
3367 set_wr_txq(skb, CPL_PRIORITY_SETUP, chan);
3368 req = (struct cpl_tid_release *)__skb_put(skb, sizeof(*req));
3369 INIT_TP_WR(req, tid);
3370 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_TID_RELEASE, tid));
3371}
3372
3373/*
3374 * Queue a TID release request and if necessary schedule a work queue to
3375 * process it.
3376 */
31b9c19b 3377static void cxgb4_queue_tid_release(struct tid_info *t, unsigned int chan,
3378 unsigned int tid)
b8ff05a9
DM		 3379{
3380 void **p = &t->tid_tab[tid];
3381 struct adapter *adap = container_of(t, struct adapter, tids);
3382
3383 spin_lock_bh(&adap->tid_release_lock);
3384 *p = adap->tid_release_head;
3385 /* Low 2 bits encode the Tx channel number */
3386 adap->tid_release_head = (void **)((uintptr_t)p | chan);
3387 if (!adap->tid_release_task_busy) {
3388 adap->tid_release_task_busy = true;
29aaee65 3389 queue_work(adap->workq, &adap->tid_release_task);
b8ff05a9
DM		 3390 }
3391 spin_unlock_bh(&adap->tid_release_lock);
3392}
b8ff05a9
DM		 3393
3394/*
3395 * Process the list of pending TID release requests.
3396 */
3397static void process_tid_release_list(struct work_struct *work)
3398{
3399 struct sk_buff *skb;
3400 struct adapter *adap;
3401
3402 adap = container_of(work, struct adapter, tid_release_task);
3403
3404 spin_lock_bh(&adap->tid_release_lock);
3405 while (adap->tid_release_head) {
3406 void **p = adap->tid_release_head;
3407 unsigned int chan = (uintptr_t)p & 3;
3408 p = (void *)p - chan;
3409
3410 adap->tid_release_head = *p;
3411 *p = NULL;
3412 spin_unlock_bh(&adap->tid_release_lock);
3413
3414 while (!(skb = alloc_skb(sizeof(struct cpl_tid_release),
3415 GFP_KERNEL)))
3416 schedule_timeout_uninterruptible(1);
3417
3418 mk_tid_release(skb, chan, p - adap->tids.tid_tab);
3419 t4_ofld_send(adap, skb);
3420 spin_lock_bh(&adap->tid_release_lock);
3421 }
3422 adap->tid_release_task_busy = false;
3423 spin_unlock_bh(&adap->tid_release_lock);
3424}
3425
3426/*
3427 * Release a TID and inform HW. If we are unable to allocate the release
3428 * message we defer to a work queue.
3429 */
3430void cxgb4_remove_tid(struct tid_info *t, unsigned int chan, unsigned int tid)
3431{
3432 void *old;
3433 struct sk_buff *skb;
3434 struct adapter *adap = container_of(t, struct adapter, tids);
3435
3436 old = t->tid_tab[tid];
3437 skb = alloc_skb(sizeof(struct cpl_tid_release), GFP_ATOMIC);
3438 if (likely(skb)) {
3439 t->tid_tab[tid] = NULL;
3440 mk_tid_release(skb, chan, tid);
3441 t4_ofld_send(adap, skb);
3442 } else
3443 cxgb4_queue_tid_release(t, chan, tid);
3444 if (old)
3445 atomic_dec(&t->tids_in_use);
3446}
3447EXPORT_SYMBOL(cxgb4_remove_tid);
3448
3449/*
3450 * Allocate and initialize the TID tables. Returns 0 on success.
3451 */
3452static int tid_init(struct tid_info *t)
3453{
3454 size_t size;
f2b7e78d 3455 unsigned int stid_bmap_size;
b8ff05a9 3456 unsigned int natids = t->natids;
b6f8eaec 3457 struct adapter *adap = container_of(t, struct adapter, tids);
b8ff05a9 3458
dca4faeb 3459 stid_bmap_size = BITS_TO_LONGS(t->nstids + t->nsftids);
f2b7e78d
VP		 3460 size = t->ntids * sizeof(*t->tid_tab) +
3461 natids * sizeof(*t->atid_tab) +
b8ff05a9 3462 t->nstids * sizeof(*t->stid_tab) +
dca4faeb 3463 t->nsftids * sizeof(*t->stid_tab) +
f2b7e78d 3464 stid_bmap_size * sizeof(long) +
dca4faeb
VP		 3465 t->nftids * sizeof(*t->ftid_tab) +
3466 t->nsftids * sizeof(*t->ftid_tab);
f2b7e78d 3467
b8ff05a9
DM		 3468 t->tid_tab = t4_alloc_mem(size);
3469 if (!t->tid_tab)
3470 return -ENOMEM;
3471
3472 t->atid_tab = (union aopen_entry *)&t->tid_tab[t->ntids];
3473 t->stid_tab = (struct serv_entry *)&t->atid_tab[natids];
dca4faeb 3474 t->stid_bmap = (unsigned long *)&t->stid_tab[t->nstids + t->nsftids];
f2b7e78d 3475 t->ftid_tab = (struct filter_entry *)&t->stid_bmap[stid_bmap_size];
b8ff05a9
DM		 3476 spin_lock_init(&t->stid_lock);
3477 spin_lock_init(&t->atid_lock);
3478
3479 t->stids_in_use = 0;
3480 t->afree = NULL;
3481 t->atids_in_use = 0;
3482 atomic_set(&t->tids_in_use, 0);
3483
3484 /* Setup the free list for atid_tab and clear the stid bitmap. */
3485 if (natids) {
3486 while (--natids)
3487 t->atid_tab[natids - 1].next = &t->atid_tab[natids];
3488 t->afree = t->atid_tab;
3489 }
dca4faeb 3490 bitmap_zero(t->stid_bmap, t->nstids + t->nsftids);
b6f8eaec
KS		 3491 /* Reserve stid 0 for T4/T5 adapters */
3492 if (!t->stid_base &&
3493 (is_t4(adap->params.chip) || is_t5(adap->params.chip)))
3494 __set_bit(0, t->stid_bmap);
3495
b8ff05a9
DM		 3496 return 0;
3497}
3498
a3e3b285
AB		 3499int cxgb4_clip_get(const struct net_device *dev,
3500 const struct in6_addr *lip)
01bcca68
VP		 3501{
3502 struct adapter *adap;
3503 struct fw_clip_cmd c;
3504
3505 adap = netdev2adap(dev);
3506 memset(&c, 0, sizeof(c));
3507 c.op_to_write = htonl(FW_CMD_OP(FW_CLIP_CMD) |
3508 FW_CMD_REQUEST | FW_CMD_WRITE);
3509 c.alloc_to_len16 = htonl(F_FW_CLIP_CMD_ALLOC | FW_LEN16(c));
12f2a479
JP		 3510 c.ip_hi = *(__be64 *)(lip->s6_addr);
3511 c.ip_lo = *(__be64 *)(lip->s6_addr + 8);
01bcca68
VP		 3512 return t4_wr_mbox_meat(adap, adap->mbox, &c, sizeof(c), &c, false);
3513}
a3e3b285 3514EXPORT_SYMBOL(cxgb4_clip_get);
01bcca68 3515
a3e3b285
AB		 3516int cxgb4_clip_release(const struct net_device *dev,
3517 const struct in6_addr *lip)
01bcca68
VP		 3518{
3519 struct adapter *adap;
3520 struct fw_clip_cmd c;
3521
3522 adap = netdev2adap(dev);
3523 memset(&c, 0, sizeof(c));
3524 c.op_to_write = htonl(FW_CMD_OP(FW_CLIP_CMD) |
3525 FW_CMD_REQUEST | FW_CMD_READ);
3526 c.alloc_to_len16 = htonl(F_FW_CLIP_CMD_FREE | FW_LEN16(c));
12f2a479
JP		 3527 c.ip_hi = *(__be64 *)(lip->s6_addr);
3528 c.ip_lo = *(__be64 *)(lip->s6_addr + 8);
01bcca68
VP		 3529 return t4_wr_mbox_meat(adap, adap->mbox, &c, sizeof(c), &c, false);
3530}
a3e3b285 3531EXPORT_SYMBOL(cxgb4_clip_release);
01bcca68 3532
b8ff05a9
DM		 3533/**
3534 * cxgb4_create_server - create an IP server
3535 * @dev: the device
3536 * @stid: the server TID
3537 * @sip: local IP address to bind server to
3538 * @sport: the server's TCP port
3539 * @queue: queue to direct messages from this server to
3540 *
3541 * Create an IP server for the given port and address.
3542 * Returns <0 on error and one of the %NET_XMIT_* values on success.
3543 */
3544int cxgb4_create_server(const struct net_device *dev, unsigned int stid,
793dad94
VP		 3545 __be32 sip, __be16 sport, __be16 vlan,
3546 unsigned int queue)
b8ff05a9
DM		 3547{
3548 unsigned int chan;
3549 struct sk_buff *skb;
3550 struct adapter *adap;
3551 struct cpl_pass_open_req *req;
80f40c1f 3552 int ret;
b8ff05a9
DM		 3553
3554 skb = alloc_skb(sizeof(*req), GFP_KERNEL);
3555 if (!skb)
3556 return -ENOMEM;
3557
3558 adap = netdev2adap(dev);
3559 req = (struct cpl_pass_open_req *)__skb_put(skb, sizeof(*req));
3560 INIT_TP_WR(req, 0);
3561 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_PASS_OPEN_REQ, stid));
3562 req->local_port = sport;
3563 req->peer_port = htons(0);
3564 req->local_ip = sip;
3565 req->peer_ip = htonl(0);
e46dab4d 3566 chan = rxq_to_chan(&adap->sge, queue);
b8ff05a9
DM		 3567 req->opt0 = cpu_to_be64(TX_CHAN(chan));
3568 req->opt1 = cpu_to_be64(CONN_POLICY_ASK |
3569 SYN_RSS_ENABLE | SYN_RSS_QUEUE(queue));
80f40c1f
VP		 3570 ret = t4_mgmt_tx(adap, skb);
3571 return net_xmit_eval(ret);
b8ff05a9
DM		 3572}
3573EXPORT_SYMBOL(cxgb4_create_server);
3574
80f40c1f
VP		 3575/* cxgb4_create_server6 - create an IPv6 server
3576 * @dev: the device
3577 * @stid: the server TID
3578 * @sip: local IPv6 address to bind server to
3579 * @sport: the server's TCP port
3580 * @queue: queue to direct messages from this server to
3581 *
3582 * Create an IPv6 server for the given port and address.
3583 * Returns <0 on error and one of the %NET_XMIT_* values on success.
3584 */
3585int cxgb4_create_server6(const struct net_device *dev, unsigned int stid,
3586 const struct in6_addr *sip, __be16 sport,
3587 unsigned int queue)
3588{
3589 unsigned int chan;
3590 struct sk_buff *skb;
3591 struct adapter *adap;
3592 struct cpl_pass_open_req6 *req;
3593 int ret;
3594
3595 skb = alloc_skb(sizeof(*req), GFP_KERNEL);
3596 if (!skb)
3597 return -ENOMEM;
3598
3599 adap = netdev2adap(dev);
3600 req = (struct cpl_pass_open_req6 *)__skb_put(skb, sizeof(*req));
3601 INIT_TP_WR(req, 0);
3602 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_PASS_OPEN_REQ6, stid));
3603 req->local_port = sport;
3604 req->peer_port = htons(0);
3605 req->local_ip_hi = *(__be64 *)(sip->s6_addr);
3606 req->local_ip_lo = *(__be64 *)(sip->s6_addr + 8);
3607 req->peer_ip_hi = cpu_to_be64(0);
3608 req->peer_ip_lo = cpu_to_be64(0);
3609 chan = rxq_to_chan(&adap->sge, queue);
3610 req->opt0 = cpu_to_be64(TX_CHAN(chan));
3611 req->opt1 = cpu_to_be64(CONN_POLICY_ASK |
3612 SYN_RSS_ENABLE | SYN_RSS_QUEUE(queue));
3613 ret = t4_mgmt_tx(adap, skb);
3614 return net_xmit_eval(ret);
3615}
3616EXPORT_SYMBOL(cxgb4_create_server6);
3617
3618int cxgb4_remove_server(const struct net_device *dev, unsigned int stid,
3619 unsigned int queue, bool ipv6)
3620{
3621 struct sk_buff *skb;
3622 struct adapter *adap;
3623 struct cpl_close_listsvr_req *req;
3624 int ret;
3625
3626 adap = netdev2adap(dev);
3627
3628 skb = alloc_skb(sizeof(*req), GFP_KERNEL);
3629 if (!skb)
3630 return -ENOMEM;
3631
3632 req = (struct cpl_close_listsvr_req *)__skb_put(skb, sizeof(*req));
3633 INIT_TP_WR(req, 0);
3634 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_CLOSE_LISTSRV_REQ, stid));
3635 req->reply_ctrl = htons(NO_REPLY(0) | (ipv6 ? LISTSVR_IPV6(1) :
3636 LISTSVR_IPV6(0)) | QUEUENO(queue));
3637 ret = t4_mgmt_tx(adap, skb);
3638 return net_xmit_eval(ret);
3639}
3640EXPORT_SYMBOL(cxgb4_remove_server);
3641
b8ff05a9
DM		 3642/**
3643 * cxgb4_best_mtu - find the entry in the MTU table closest to an MTU
3644 * @mtus: the HW MTU table
3645 * @mtu: the target MTU
3646 * @idx: index of selected entry in the MTU table
3647 *
3648 * Returns the index and the value in the HW MTU table that is closest to
3649 * but does not exceed @mtu, unless @mtu is smaller than any value in the
3650 * table, in which case that smallest available value is selected.
3651 */
3652unsigned int cxgb4_best_mtu(const unsigned short *mtus, unsigned short mtu,
3653 unsigned int *idx)
3654{
3655 unsigned int i = 0;
3656
3657 while (i < NMTUS - 1 && mtus[i + 1] <= mtu)
3658 ++i;
3659 if (idx)
3660 *idx = i;
3661 return mtus[i];
3662}
3663EXPORT_SYMBOL(cxgb4_best_mtu);
3664
92e7ae71
HS		 3665/**
3666 * cxgb4_best_aligned_mtu - find best MTU, [hopefully] data size aligned
3667 * @mtus: the HW MTU table
3668 * @header_size: Header Size
3669 * @data_size_max: maximum Data Segment Size
3670 * @data_size_align: desired Data Segment Size Alignment (2^N)
3671 * @mtu_idxp: HW MTU Table Index return value pointer (possibly NULL)
3672 *
3673 * Similar to cxgb4_best_mtu() but instead of searching the Hardware
3674 * MTU Table based solely on a Maximum MTU parameter, we break that
3675 * parameter up into a Header Size and Maximum Data Segment Size, and
3676 * provide a desired Data Segment Size Alignment. If we find an MTU in
3677 * the Hardware MTU Table which will result in a Data Segment Size with
3678 * the requested alignment _and_ that MTU isn't "too far" from the
3679 * closest MTU, then we'll return that rather than the closest MTU.
3680 */
3681unsigned int cxgb4_best_aligned_mtu(const unsigned short *mtus,
3682 unsigned short header_size,
3683 unsigned short data_size_max,
3684 unsigned short data_size_align,
3685 unsigned int *mtu_idxp)
3686{
3687 unsigned short max_mtu = header_size + data_size_max;
3688 unsigned short data_size_align_mask = data_size_align - 1;
3689 int mtu_idx, aligned_mtu_idx;
3690
3691 /* Scan the MTU Table till we find an MTU which is larger than our
3692 * Maximum MTU or we reach the end of the table. Along the way,
3693 * record the last MTU found, if any, which will result in a Data
3694 * Segment Length matching the requested alignment.
3695 */
3696 for (mtu_idx = 0, aligned_mtu_idx = -1; mtu_idx < NMTUS; mtu_idx++) {
3697 unsigned short data_size = mtus[mtu_idx] - header_size;
3698
3699 /* If this MTU minus the Header Size would result in a
3700 * Data Segment Size of the desired alignment, remember it.
3701 */
3702 if ((data_size & data_size_align_mask) == 0)
3703 aligned_mtu_idx = mtu_idx;
3704
3705 /* If we're not at the end of the Hardware MTU Table and the
3706 * next element is larger than our Maximum MTU, drop out of
3707 * the loop.
3708 */
3709 if (mtu_idx+1 < NMTUS && mtus[mtu_idx+1] > max_mtu)
3710 break;
3711 }
3712
3713 /* If we fell out of the loop because we ran to the end of the table,
3714 * then we just have to use the last [largest] entry.
3715 */
3716 if (mtu_idx == NMTUS)
3717 mtu_idx--;
3718
3719 /* If we found an MTU which resulted in the requested Data Segment
3720 * Length alignment and that's "not far" from the largest MTU which is
3721 * less than or equal to the maximum MTU, then use that.
3722 */
3723 if (aligned_mtu_idx >= 0 &&
3724 mtu_idx - aligned_mtu_idx <= 1)
3725 mtu_idx = aligned_mtu_idx;
3726
3727 /* If the caller has passed in an MTU Index pointer, pass the
3728 * MTU Index back. Return the MTU value.
3729 */
3730 if (mtu_idxp)
3731 *mtu_idxp = mtu_idx;
3732 return mtus[mtu_idx];
3733}
3734EXPORT_SYMBOL(cxgb4_best_aligned_mtu);
3735
b8ff05a9
DM		 3736/**
3737 * cxgb4_port_chan - get the HW channel of a port
3738 * @dev: the net device for the port
3739 *
3740 * Return the HW Tx channel of the given port.
3741 */
3742unsigned int cxgb4_port_chan(const struct net_device *dev)
3743{
3744 return netdev2pinfo(dev)->tx_chan;
3745}
3746EXPORT_SYMBOL(cxgb4_port_chan);
3747
881806bc
VP		 3748unsigned int cxgb4_dbfifo_count(const struct net_device *dev, int lpfifo)
3749{
3750 struct adapter *adap = netdev2adap(dev);
2cc301d2 3751 u32 v1, v2, lp_count, hp_count;
881806bc 3752
2cc301d2
SR		 3753 v1 = t4_read_reg(adap, A_SGE_DBFIFO_STATUS);
3754 v2 = t4_read_reg(adap, SGE_DBFIFO_STATUS2);
d14807dd 3755 if (is_t4(adap->params.chip)) {
2cc301d2
SR		 3756 lp_count = G_LP_COUNT(v1);
3757 hp_count = G_HP_COUNT(v1);
3758 } else {
3759 lp_count = G_LP_COUNT_T5(v1);
3760 hp_count = G_HP_COUNT_T5(v2);
3761 }
3762 return lpfifo ? lp_count : hp_count;
881806bc
VP		 3763}
3764EXPORT_SYMBOL(cxgb4_dbfifo_count);
3765
b8ff05a9
DM		 3766/**
3767 * cxgb4_port_viid - get the VI id of a port
3768 * @dev: the net device for the port
3769 *
3770 * Return the VI id of the given port.
3771 */
3772unsigned int cxgb4_port_viid(const struct net_device *dev)
3773{
3774 return netdev2pinfo(dev)->viid;
3775}
3776EXPORT_SYMBOL(cxgb4_port_viid);
3777
3778/**
3779 * cxgb4_port_idx - get the index of a port
3780 * @dev: the net device for the port
3781 *
3782 * Return the index of the given port.
3783 */
3784unsigned int cxgb4_port_idx(const struct net_device *dev)
3785{
3786 return netdev2pinfo(dev)->port_id;
3787}
3788EXPORT_SYMBOL(cxgb4_port_idx);
3789
b8ff05a9
DM		 3790void cxgb4_get_tcp_stats(struct pci_dev *pdev, struct tp_tcp_stats *v4,
3791 struct tp_tcp_stats *v6)
3792{
3793 struct adapter *adap = pci_get_drvdata(pdev);
3794
3795 spin_lock(&adap->stats_lock);
3796 t4_tp_get_tcp_stats(adap, v4, v6);
3797 spin_unlock(&adap->stats_lock);
3798}
3799EXPORT_SYMBOL(cxgb4_get_tcp_stats);
3800
3801void cxgb4_iscsi_init(struct net_device *dev, unsigned int tag_mask,
3802 const unsigned int *pgsz_order)
3803{
3804 struct adapter *adap = netdev2adap(dev);
3805
3806 t4_write_reg(adap, ULP_RX_ISCSI_TAGMASK, tag_mask);
3807 t4_write_reg(adap, ULP_RX_ISCSI_PSZ, HPZ0(pgsz_order[0]) |
3808 HPZ1(pgsz_order[1]) | HPZ2(pgsz_order[2]) |
3809 HPZ3(pgsz_order[3]));
3810}
3811EXPORT_SYMBOL(cxgb4_iscsi_init);
3812
3069ee9b
VP		 3813int cxgb4_flush_eq_cache(struct net_device *dev)
3814{
3815 struct adapter *adap = netdev2adap(dev);
3816 int ret;
3817
3818 ret = t4_fwaddrspace_write(adap, adap->mbox,
3819 0xe1000000 + A_SGE_CTXT_CMD, 0x20000000);
3820 return ret;
3821}
3822EXPORT_SYMBOL(cxgb4_flush_eq_cache);
3823
3824static int read_eq_indices(struct adapter *adap, u16 qid, u16 *pidx, u16 *cidx)
3825{
3826 u32 addr = t4_read_reg(adap, A_SGE_DBQ_CTXT_BADDR) + 24 * qid + 8;
3827 __be64 indices;
3828 int ret;
3829
fc5ab020
HS		 3830 spin_lock(&adap->win0_lock);
3831 ret = t4_memory_rw(adap, 0, MEM_EDC0, addr,
3832 sizeof(indices), (__be32 *)&indices,
3833 T4_MEMORY_READ);
3834 spin_unlock(&adap->win0_lock);
3069ee9b 3835 if (!ret) {
404d9e3f
VP		 3836 *cidx = (be64_to_cpu(indices) >> 25) & 0xffff;
3837 *pidx = (be64_to_cpu(indices) >> 9) & 0xffff;
3069ee9b
VP		 3838 }
3839 return ret;
3840}
3841
3842int cxgb4_sync_txq_pidx(struct net_device *dev, u16 qid, u16 pidx,
3843 u16 size)
3844{
3845 struct adapter *adap = netdev2adap(dev);
3846 u16 hw_pidx, hw_cidx;
3847 int ret;
3848
3849 ret = read_eq_indices(adap, qid, &hw_pidx, &hw_cidx);
3850 if (ret)
3851 goto out;
3852
3853 if (pidx != hw_pidx) {
3854 u16 delta;
3855
3856 if (pidx >= hw_pidx)
3857 delta = pidx - hw_pidx;
3858 else
3859 delta = size - hw_pidx + pidx;
3860 wmb();
840f3000
VP		 3861 t4_write_reg(adap, MYPF_REG(SGE_PF_KDOORBELL),
3862 QID(qid) | PIDX(delta));
3069ee9b
VP		 3863 }
3864out:
3865 return ret;
3866}
3867EXPORT_SYMBOL(cxgb4_sync_txq_pidx);
3868
3cbdb928
VP		 3869void cxgb4_disable_db_coalescing(struct net_device *dev)
3870{
3871 struct adapter *adap;
3872
3873 adap = netdev2adap(dev);
3874 t4_set_reg_field(adap, A_SGE_DOORBELL_CONTROL, F_NOCOALESCE,
3875 F_NOCOALESCE);
3876}
3877EXPORT_SYMBOL(cxgb4_disable_db_coalescing);
3878
3879void cxgb4_enable_db_coalescing(struct net_device *dev)
3880{
3881 struct adapter *adap;
3882
3883 adap = netdev2adap(dev);
3884 t4_set_reg_field(adap, A_SGE_DOORBELL_CONTROL, F_NOCOALESCE, 0);
3885}
3886EXPORT_SYMBOL(cxgb4_enable_db_coalescing);
3887
031cf476
HS		 3888int cxgb4_read_tpte(struct net_device *dev, u32 stag, __be32 *tpte)
3889{
3890 struct adapter *adap;
3891 u32 offset, memtype, memaddr;
3892 u32 edc0_size, edc1_size, mc0_size, mc1_size;
3893 u32 edc0_end, edc1_end, mc0_end, mc1_end;
3894 int ret;
3895
3896 adap = netdev2adap(dev);
3897
3898 offset = ((stag >> 8) * 32) + adap->vres.stag.start;
3899
3900 /* Figure out where the offset lands in the Memory Type/Address scheme.
3901 * This code assumes that the memory is laid out starting at offset 0
3902 * with no breaks as: EDC0, EDC1, MC0, MC1. All cards have both EDC0
3903 * and EDC1. Some cards will have neither MC0 nor MC1, most cards have
3904 * MC0, and some have both MC0 and MC1.
3905 */
3906 edc0_size = EDRAM_SIZE_GET(t4_read_reg(adap, MA_EDRAM0_BAR)) << 20;
3907 edc1_size = EDRAM_SIZE_GET(t4_read_reg(adap, MA_EDRAM1_BAR)) << 20;
3908 mc0_size = EXT_MEM_SIZE_GET(t4_read_reg(adap, MA_EXT_MEMORY_BAR)) << 20;
3909
3910 edc0_end = edc0_size;
3911 edc1_end = edc0_end + edc1_size;
3912 mc0_end = edc1_end + mc0_size;
3913
3914 if (offset < edc0_end) {
3915 memtype = MEM_EDC0;
3916 memaddr = offset;
3917 } else if (offset < edc1_end) {
3918 memtype = MEM_EDC1;
3919 memaddr = offset - edc0_end;
3920 } else {
3921 if (offset < mc0_end) {
3922 memtype = MEM_MC0;
3923 memaddr = offset - edc1_end;
3924 } else if (is_t4(adap->params.chip)) {
3925 /* T4 only has a single memory channel */
3926 goto err;
3927 } else {
3928 mc1_size = EXT_MEM_SIZE_GET(
3929 t4_read_reg(adap,
3930 MA_EXT_MEMORY1_BAR)) << 20;
3931 mc1_end = mc0_end + mc1_size;
3932 if (offset < mc1_end) {
3933 memtype = MEM_MC1;
3934 memaddr = offset - mc0_end;
3935 } else {
3936 /* offset beyond the end of any memory */
3937 goto err;
3938 }
3939 }
3940 }
3941
3942 spin_lock(&adap->win0_lock);
3943 ret = t4_memory_rw(adap, 0, memtype, memaddr, 32, tpte, T4_MEMORY_READ);
3944 spin_unlock(&adap->win0_lock);
3945 return ret;
3946
3947err:
3948 dev_err(adap->pdev_dev, "stag %#x, offset %#x out of range\n",
3949 stag, offset);
3950 return -EINVAL;
3951}
3952EXPORT_SYMBOL(cxgb4_read_tpte);
3953
7730b4c7
HS		 3954u64 cxgb4_read_sge_timestamp(struct net_device *dev)
3955{
3956 u32 hi, lo;
3957 struct adapter *adap;
3958
3959 adap = netdev2adap(dev);
3960 lo = t4_read_reg(adap, SGE_TIMESTAMP_LO);
3961 hi = GET_TSVAL(t4_read_reg(adap, SGE_TIMESTAMP_HI));
3962
3963 return ((u64)hi << 32) | (u64)lo;
3964}
3965EXPORT_SYMBOL(cxgb4_read_sge_timestamp);
3966
b8ff05a9
DM		 3967static struct pci_driver cxgb4_driver;
3968
3969static void check_neigh_update(struct neighbour *neigh)
3970{
3971 const struct device *parent;
3972 const struct net_device *netdev = neigh->dev;
3973
3974 if (netdev->priv_flags & IFF_802_1Q_VLAN)
3975 netdev = vlan_dev_real_dev(netdev);
3976 parent = netdev->dev.parent;
3977 if (parent && parent->driver == &cxgb4_driver.driver)
3978 t4_l2t_update(dev_get_drvdata(parent), neigh);
3979}
3980
3981static int netevent_cb(struct notifier_block *nb, unsigned long event,
3982 void *data)
3983{
3984 switch (event) {
3985 case NETEVENT_NEIGH_UPDATE:
3986 check_neigh_update(data);
3987 break;
b8ff05a9
DM		 3988 case NETEVENT_REDIRECT:
3989 default:
3990 break;
3991 }
3992 return 0;
3993}
3994
3995static bool netevent_registered;
3996static struct notifier_block cxgb4_netevent_nb = {
3997 .notifier_call = netevent_cb
3998};
3999
3069ee9b
VP		 4000static void drain_db_fifo(struct adapter *adap, int usecs)
4001{
2cc301d2 4002 u32 v1, v2, lp_count, hp_count;
3069ee9b
VP		 4003
4004 do {
2cc301d2
SR		 4005 v1 = t4_read_reg(adap, A_SGE_DBFIFO_STATUS);
4006 v2 = t4_read_reg(adap, SGE_DBFIFO_STATUS2);
d14807dd 4007 if (is_t4(adap->params.chip)) {
2cc301d2
SR		 4008 lp_count = G_LP_COUNT(v1);
4009 hp_count = G_HP_COUNT(v1);
4010 } else {
4011 lp_count = G_LP_COUNT_T5(v1);
4012 hp_count = G_HP_COUNT_T5(v2);
4013 }
4014
4015 if (lp_count == 0 && hp_count == 0)
4016 break;
3069ee9b
VP		 4017 set_current_state(TASK_UNINTERRUPTIBLE);
4018 schedule_timeout(usecs_to_jiffies(usecs));
3069ee9b
VP		 4019 } while (1);
4020}
4021
4022static void disable_txq_db(struct sge_txq *q)
4023{
05eb2389
SW		 4024 unsigned long flags;
4025
4026 spin_lock_irqsave(&q->db_lock, flags);
3069ee9b 4027 q->db_disabled = 1;
05eb2389 4028 spin_unlock_irqrestore(&q->db_lock, flags);
3069ee9b
VP		 4029}
4030
05eb2389 4031static void enable_txq_db(struct adapter *adap, struct sge_txq *q)
3069ee9b
VP		 4032{
4033 spin_lock_irq(&q->db_lock);
05eb2389
SW		 4034 if (q->db_pidx_inc) {
4035 /* Make sure that all writes to the TX descriptors
4036 * are committed before we tell HW about them.
4037 */
4038 wmb();
4039 t4_write_reg(adap, MYPF_REG(SGE_PF_KDOORBELL),
4040 QID(q->cntxt_id) | PIDX(q->db_pidx_inc));
4041 q->db_pidx_inc = 0;
4042 }
3069ee9b
VP		 4043 q->db_disabled = 0;
4044 spin_unlock_irq(&q->db_lock);
4045}
4046
4047static void disable_dbs(struct adapter *adap)
4048{
4049 int i;
4050
4051 for_each_ethrxq(&adap->sge, i)
4052 disable_txq_db(&adap->sge.ethtxq[i].q);
4053 for_each_ofldrxq(&adap->sge, i)
4054 disable_txq_db(&adap->sge.ofldtxq[i].q);
4055 for_each_port(adap, i)
4056 disable_txq_db(&adap->sge.ctrlq[i].q);
4057}
4058
4059static void enable_dbs(struct adapter *adap)
4060{
4061 int i;
4062
4063 for_each_ethrxq(&adap->sge, i)
05eb2389 4064 enable_txq_db(adap, &adap->sge.ethtxq[i].q);
3069ee9b 4065 for_each_ofldrxq(&adap->sge, i)
05eb2389 4066 enable_txq_db(adap, &adap->sge.ofldtxq[i].q);
3069ee9b 4067 for_each_port(adap, i)
05eb2389
SW		 4068 enable_txq_db(adap, &adap->sge.ctrlq[i].q);
4069}
4070
4071static void notify_rdma_uld(struct adapter *adap, enum cxgb4_control cmd)
4072{
4073 if (adap->uld_handle[CXGB4_ULD_RDMA])
4074 ulds[CXGB4_ULD_RDMA].control(adap->uld_handle[CXGB4_ULD_RDMA],
4075 cmd);
4076}
4077
4078static void process_db_full(struct work_struct *work)
4079{
4080 struct adapter *adap;
4081
4082 adap = container_of(work, struct adapter, db_full_task);
4083
4084 drain_db_fifo(adap, dbfifo_drain_delay);
4085 enable_dbs(adap);
4086 notify_rdma_uld(adap, CXGB4_CONTROL_DB_EMPTY);
4087 t4_set_reg_field(adap, SGE_INT_ENABLE3,
4088 DBFIFO_HP_INT | DBFIFO_LP_INT,
4089 DBFIFO_HP_INT | DBFIFO_LP_INT);
3069ee9b
VP		 4090}
4091
4092static void sync_txq_pidx(struct adapter *adap, struct sge_txq *q)
4093{
4094 u16 hw_pidx, hw_cidx;
4095 int ret;
4096
05eb2389 4097 spin_lock_irq(&q->db_lock);
3069ee9b
VP		 4098 ret = read_eq_indices(adap, (u16)q->cntxt_id, &hw_pidx, &hw_cidx);
4099 if (ret)
4100 goto out;
4101 if (q->db_pidx != hw_pidx) {
4102 u16 delta;
4103
4104 if (q->db_pidx >= hw_pidx)
4105 delta = q->db_pidx - hw_pidx;
4106 else
4107 delta = q->size - hw_pidx + q->db_pidx;
4108 wmb();
840f3000
VP		 4109 t4_write_reg(adap, MYPF_REG(SGE_PF_KDOORBELL),
4110 QID(q->cntxt_id) | PIDX(delta));
3069ee9b
VP		 4111 }
4112out:
4113 q->db_disabled = 0;
05eb2389
SW		 4114 q->db_pidx_inc = 0;
4115 spin_unlock_irq(&q->db_lock);
3069ee9b
VP		 4116 if (ret)
4117 CH_WARN(adap, "DB drop recovery failed.\n");
4118}
4119static void recover_all_queues(struct adapter *adap)
4120{
4121 int i;
4122
4123 for_each_ethrxq(&adap->sge, i)
4124 sync_txq_pidx(adap, &adap->sge.ethtxq[i].q);
4125 for_each_ofldrxq(&adap->sge, i)
4126 sync_txq_pidx(adap, &adap->sge.ofldtxq[i].q);
4127 for_each_port(adap, i)
4128 sync_txq_pidx(adap, &adap->sge.ctrlq[i].q);
4129}
4130
881806bc
VP		 4131static void process_db_drop(struct work_struct *work)
4132{
4133 struct adapter *adap;
881806bc 4134
3069ee9b 4135 adap = container_of(work, struct adapter, db_drop_task);
881806bc 4136
d14807dd 4137 if (is_t4(adap->params.chip)) {
05eb2389 4138 drain_db_fifo(adap, dbfifo_drain_delay);
2cc301d2 4139 notify_rdma_uld(adap, CXGB4_CONTROL_DB_DROP);
05eb2389 4140 drain_db_fifo(adap, dbfifo_drain_delay);
2cc301d2 4141 recover_all_queues(adap);
05eb2389 4142 drain_db_fifo(adap, dbfifo_drain_delay);
2cc301d2 4143 enable_dbs(adap);
05eb2389 4144 notify_rdma_uld(adap, CXGB4_CONTROL_DB_EMPTY);
2cc301d2
SR		 4145 } else {
4146 u32 dropped_db = t4_read_reg(adap, 0x010ac);
4147 u16 qid = (dropped_db >> 15) & 0x1ffff;
4148 u16 pidx_inc = dropped_db & 0x1fff;
4149 unsigned int s_qpp;
4150 unsigned short udb_density;
4151 unsigned long qpshift;
4152 int page;
4153 u32 udb;
4154
4155 dev_warn(adap->pdev_dev,
4156 "Dropped DB 0x%x qid %d bar2 %d coalesce %d pidx %d\n",
4157 dropped_db, qid,
4158 (dropped_db >> 14) & 1,
4159 (dropped_db >> 13) & 1,
4160 pidx_inc);
4161
4162 drain_db_fifo(adap, 1);
4163
4164 s_qpp = QUEUESPERPAGEPF1 * adap->fn;
4165 udb_density = 1 << QUEUESPERPAGEPF0_GET(t4_read_reg(adap,
4166 SGE_EGRESS_QUEUES_PER_PAGE_PF) >> s_qpp);
4167 qpshift = PAGE_SHIFT - ilog2(udb_density);
4168 udb = qid << qpshift;
4169 udb &= PAGE_MASK;
4170 page = udb / PAGE_SIZE;
4171 udb += (qid - (page * udb_density)) * 128;
4172
4173 writel(PIDX(pidx_inc), adap->bar2 + udb + 8);
4174
4175 /* Re-enable BAR2 WC */
4176 t4_set_reg_field(adap, 0x10b0, 1<<15, 1<<15);
4177 }
4178
3069ee9b 4179 t4_set_reg_field(adap, A_SGE_DOORBELL_CONTROL, F_DROPPED_DB, 0);
881806bc
VP		 4180}
4181
4182void t4_db_full(struct adapter *adap)
4183{
d14807dd 4184 if (is_t4(adap->params.chip)) {
05eb2389
SW		 4185 disable_dbs(adap);
4186 notify_rdma_uld(adap, CXGB4_CONTROL_DB_FULL);
2cc301d2
SR		 4187 t4_set_reg_field(adap, SGE_INT_ENABLE3,
4188 DBFIFO_HP_INT | DBFIFO_LP_INT, 0);
29aaee65 4189 queue_work(adap->workq, &adap->db_full_task);
2cc301d2 4190 }
881806bc
VP		 4191}
4192
4193void t4_db_dropped(struct adapter *adap)
4194{
05eb2389
SW		 4195 if (is_t4(adap->params.chip)) {
4196 disable_dbs(adap);
4197 notify_rdma_uld(adap, CXGB4_CONTROL_DB_FULL);
4198 }
29aaee65 4199 queue_work(adap->workq, &adap->db_drop_task);
881806bc
VP		 4200}
4201
b8ff05a9
DM		 4202static void uld_attach(struct adapter *adap, unsigned int uld)
4203{
4204 void *handle;
4205 struct cxgb4_lld_info lli;
dca4faeb 4206 unsigned short i;
b8ff05a9
DM		 4207
4208 lli.pdev = adap->pdev;
35b1de55 4209 lli.pf = adap->fn;
b8ff05a9
DM		 4210 lli.l2t = adap->l2t;
4211 lli.tids = &adap->tids;
4212 lli.ports = adap->port;
4213 lli.vr = &adap->vres;
4214 lli.mtus = adap->params.mtus;
4215 if (uld == CXGB4_ULD_RDMA) {
4216 lli.rxq_ids = adap->sge.rdma_rxq;
cf38be6d 4217 lli.ciq_ids = adap->sge.rdma_ciq;
b8ff05a9 4218 lli.nrxq = adap->sge.rdmaqs;
cf38be6d 4219 lli.nciq = adap->sge.rdmaciqs;
b8ff05a9
DM		 4220 } else if (uld == CXGB4_ULD_ISCSI) {
4221 lli.rxq_ids = adap->sge.ofld_rxq;
4222 lli.nrxq = adap->sge.ofldqsets;
4223 }
4224 lli.ntxq = adap->sge.ofldqsets;
4225 lli.nchan = adap->params.nports;
4226 lli.nports = adap->params.nports;
4227 lli.wr_cred = adap->params.ofldq_wr_cred;
d14807dd 4228 lli.adapter_type = adap->params.chip;
b8ff05a9 4229 lli.iscsi_iolen = MAXRXDATA_GET(t4_read_reg(adap, TP_PARA_REG2));
7730b4c7 4230 lli.cclk_ps = 1000000000 / adap->params.vpd.cclk;
b8ff05a9 4231 lli.udb_density = 1 << QUEUESPERPAGEPF0_GET(
060e0c75
DM		 4232 t4_read_reg(adap, SGE_EGRESS_QUEUES_PER_PAGE_PF) >>
4233 (adap->fn * 4));
b8ff05a9 4234 lli.ucq_density = 1 << QUEUESPERPAGEPF0_GET(
060e0c75
DM		 4235 t4_read_reg(adap, SGE_INGRESS_QUEUES_PER_PAGE_PF) >>
4236 (adap->fn * 4));
dcf7b6f5 4237 lli.filt_mode = adap->params.tp.vlan_pri_map;
dca4faeb
VP		 4238 /* MODQ_REQ_MAP sets queues 0-3 to chan 0-3 */
4239 for (i = 0; i < NCHAN; i++)
4240 lli.tx_modq[i] = i;
b8ff05a9
DM		 4241 lli.gts_reg = adap->regs + MYPF_REG(SGE_PF_GTS);
4242 lli.db_reg = adap->regs + MYPF_REG(SGE_PF_KDOORBELL);
4243 lli.fw_vers = adap->params.fw_vers;
3069ee9b 4244 lli.dbfifo_int_thresh = dbfifo_int_thresh;
04e10e21
HS		 4245 lli.sge_ingpadboundary = adap->sge.fl_align;
4246 lli.sge_egrstatuspagesize = adap->sge.stat_len;
dca4faeb
VP		 4247 lli.sge_pktshift = adap->sge.pktshift;
4248 lli.enable_fw_ofld_conn = adap->flags & FW_OFLD_CONN;
4c2c5763
HS		 4249 lli.max_ordird_qp = adap->params.max_ordird_qp;
4250 lli.max_ird_adapter = adap->params.max_ird_adapter;
1ac0f095 4251 lli.ulptx_memwrite_dsgl = adap->params.ulptx_memwrite_dsgl;
b8ff05a9
DM		 4252
4253 handle = ulds[uld].add(&lli);
4254 if (IS_ERR(handle)) {
4255 dev_warn(adap->pdev_dev,
4256 "could not attach to the %s driver, error %ld\n",
4257 uld_str[uld], PTR_ERR(handle));
4258 return;
4259 }
4260
4261 adap->uld_handle[uld] = handle;
4262
4263 if (!netevent_registered) {
4264 register_netevent_notifier(&cxgb4_netevent_nb);
4265 netevent_registered = true;
4266 }
e29f5dbc
DM		 4267
4268 if (adap->flags & FULL_INIT_DONE)
4269 ulds[uld].state_change(handle, CXGB4_STATE_UP);
b8ff05a9
DM		 4270}
4271
4272static void attach_ulds(struct adapter *adap)
4273{
4274 unsigned int i;
4275
01bcca68
VP		 4276 spin_lock(&adap_rcu_lock);
4277 list_add_tail_rcu(&adap->rcu_node, &adap_rcu_list);
4278 spin_unlock(&adap_rcu_lock);
4279
b8ff05a9
DM		 4280 mutex_lock(&uld_mutex);
4281 list_add_tail(&adap->list_node, &adapter_list);
4282 for (i = 0; i < CXGB4_ULD_MAX; i++)
4283 if (ulds[i].add)
4284 uld_attach(adap, i);
4285 mutex_unlock(&uld_mutex);
4286}
4287
4288static void detach_ulds(struct adapter *adap)
4289{
4290 unsigned int i;
4291
4292 mutex_lock(&uld_mutex);
4293 list_del(&adap->list_node);
4294 for (i = 0; i < CXGB4_ULD_MAX; i++)
4295 if (adap->uld_handle[i]) {
4296 ulds[i].state_change(adap->uld_handle[i],
4297 CXGB4_STATE_DETACH);
4298 adap->uld_handle[i] = NULL;
4299 }
4300 if (netevent_registered && list_empty(&adapter_list)) {
4301 unregister_netevent_notifier(&cxgb4_netevent_nb);
4302 netevent_registered = false;
4303 }
4304 mutex_unlock(&uld_mutex);
01bcca68
VP		 4305
4306 spin_lock(&adap_rcu_lock);
4307 list_del_rcu(&adap->rcu_node);
4308 spin_unlock(&adap_rcu_lock);
b8ff05a9
DM		 4309}
4310
4311static void notify_ulds(struct adapter *adap, enum cxgb4_state new_state)
4312{
4313 unsigned int i;
4314
4315 mutex_lock(&uld_mutex);
4316 for (i = 0; i < CXGB4_ULD_MAX; i++)
4317 if (adap->uld_handle[i])
4318 ulds[i].state_change(adap->uld_handle[i], new_state);
4319 mutex_unlock(&uld_mutex);
4320}
4321
4322/**
4323 * cxgb4_register_uld - register an upper-layer driver
4324 * @type: the ULD type
4325 * @p: the ULD methods
4326 *
4327 * Registers an upper-layer driver with this driver and notifies the ULD
4328 * about any presently available devices that support its type. Returns
4329 * %-EBUSY if a ULD of the same type is already registered.
4330 */
4331int cxgb4_register_uld(enum cxgb4_uld type, const struct cxgb4_uld_info *p)
4332{
4333 int ret = 0;
4334 struct adapter *adap;
4335
4336 if (type >= CXGB4_ULD_MAX)
4337 return -EINVAL;
4338 mutex_lock(&uld_mutex);
4339 if (ulds[type].add) {
4340 ret = -EBUSY;
4341 goto out;
4342 }
4343 ulds[type] = *p;
4344 list_for_each_entry(adap, &adapter_list, list_node)
4345 uld_attach(adap, type);
4346out: mutex_unlock(&uld_mutex);
4347 return ret;
4348}
4349EXPORT_SYMBOL(cxgb4_register_uld);
4350
4351/**
4352 * cxgb4_unregister_uld - unregister an upper-layer driver
4353 * @type: the ULD type
4354 *
4355 * Unregisters an existing upper-layer driver.
4356 */
4357int cxgb4_unregister_uld(enum cxgb4_uld type)
4358{
4359 struct adapter *adap;
4360
4361 if (type >= CXGB4_ULD_MAX)
4362 return -EINVAL;
4363 mutex_lock(&uld_mutex);
4364 list_for_each_entry(adap, &adapter_list, list_node)
4365 adap->uld_handle[type] = NULL;
4366 ulds[type].add = NULL;
4367 mutex_unlock(&uld_mutex);
4368 return 0;
4369}
4370EXPORT_SYMBOL(cxgb4_unregister_uld);
4371
01bcca68 4372/* Check if netdev on which event is occured belongs to us or not. Return
ee9a33b2
LR		 4373 * success (true) if it belongs otherwise failure (false).
4374 * Called with rcu_read_lock() held.
01bcca68 4375 */
1bb60376 4376#if IS_ENABLED(CONFIG_IPV6)
ee9a33b2 4377static bool cxgb4_netdev(const struct net_device *netdev)
01bcca68
VP		 4378{
4379 struct adapter *adap;
4380 int i;
4381
01bcca68
VP		 4382 list_for_each_entry_rcu(adap, &adap_rcu_list, rcu_node)
4383 for (i = 0; i < MAX_NPORTS; i++)
ee9a33b2
LR		 4384 if (adap->port[i] == netdev)
4385 return true;
4386 return false;
01bcca68
VP		 4387}
4388
4389static int clip_add(struct net_device *event_dev, struct inet6_ifaddr *ifa,
4390 unsigned long event)
4391{
4392 int ret = NOTIFY_DONE;
4393
4394 rcu_read_lock();
4395 if (cxgb4_netdev(event_dev)) {
4396 switch (event) {
4397 case NETDEV_UP:
4398 ret = cxgb4_clip_get(event_dev,
4399 (const struct in6_addr *)ifa->addr.s6_addr);
4400 if (ret < 0) {
4401 rcu_read_unlock();
4402 return ret;
4403 }
4404 ret = NOTIFY_OK;
4405 break;
4406 case NETDEV_DOWN:
4407 cxgb4_clip_release(event_dev,
4408 (const struct in6_addr *)ifa->addr.s6_addr);
4409 ret = NOTIFY_OK;
4410 break;
4411 default:
4412 break;
4413 }
4414 }
4415 rcu_read_unlock();
4416 return ret;
4417}
4418
4419static int cxgb4_inet6addr_handler(struct notifier_block *this,
4420 unsigned long event, void *data)
4421{
4422 struct inet6_ifaddr *ifa = data;
4423 struct net_device *event_dev;
4424 int ret = NOTIFY_DONE;
01bcca68 4425 struct bonding *bond = netdev_priv(ifa->idev->dev);
9caff1e7 4426 struct list_head *iter;
01bcca68
VP		 4427 struct slave *slave;
4428 struct pci_dev *first_pdev = NULL;
4429
4430 if (ifa->idev->dev->priv_flags & IFF_802_1Q_VLAN) {
4431 event_dev = vlan_dev_real_dev(ifa->idev->dev);
4432 ret = clip_add(event_dev, ifa, event);
4433 } else if (ifa->idev->dev->flags & IFF_MASTER) {
4434 /* It is possible that two different adapters are bonded in one
4435 * bond. We need to find such different adapters and add clip
4436 * in all of them only once.
4437 */
9caff1e7 4438 bond_for_each_slave(bond, slave, iter) {
01bcca68
VP		 4439 if (!first_pdev) {
4440 ret = clip_add(slave->dev, ifa, event);
4441 /* If clip_add is success then only initialize
4442 * first_pdev since it means it is our device
4443 */
4444 if (ret == NOTIFY_OK)
4445 first_pdev = to_pci_dev(
4446 slave->dev->dev.parent);
4447 } else if (first_pdev !=
4448 to_pci_dev(slave->dev->dev.parent))
4449 ret = clip_add(slave->dev, ifa, event);
4450 }
01bcca68
VP		 4451 } else
4452 ret = clip_add(ifa->idev->dev, ifa, event);
4453
4454 return ret;
4455}
4456
4457static struct notifier_block cxgb4_inet6addr_notifier = {
4458 .notifier_call = cxgb4_inet6addr_handler
4459};
4460
4461/* Retrieves IPv6 addresses from a root device (bond, vlan) associated with
4462 * a physical device.
4463 * The physical device reference is needed to send the actul CLIP command.
4464 */
4465static int update_dev_clip(struct net_device *root_dev, struct net_device *dev)
4466{
4467 struct inet6_dev *idev = NULL;
4468 struct inet6_ifaddr *ifa;
4469 int ret = 0;
4470
4471 idev = __in6_dev_get(root_dev);
4472 if (!idev)
4473 return ret;
4474
4475 read_lock_bh(&idev->lock);
4476 list_for_each_entry(ifa, &idev->addr_list, if_list) {
4477 ret = cxgb4_clip_get(dev,
4478 (const struct in6_addr *)ifa->addr.s6_addr);
4479 if (ret < 0)
4480 break;
4481 }
4482 read_unlock_bh(&idev->lock);
4483
4484 return ret;
4485}
4486
4487static int update_root_dev_clip(struct net_device *dev)
4488{
4489 struct net_device *root_dev = NULL;
4490 int i, ret = 0;
4491
4492 /* First populate the real net device's IPv6 addresses */
4493 ret = update_dev_clip(dev, dev);
4494 if (ret)
4495 return ret;
4496
4497 /* Parse all bond and vlan devices layered on top of the physical dev */
587ddfe2
AB		 4498 root_dev = netdev_master_upper_dev_get_rcu(dev);
4499 if (root_dev) {
4500 ret = update_dev_clip(root_dev, dev);
4501 if (ret)
4502 return ret;
4503 }
4504
01bcca68 4505 for (i = 0; i < VLAN_N_VID; i++) {
f06c7f9f 4506 root_dev = __vlan_find_dev_deep_rcu(dev, htons(ETH_P_8021Q), i);
01bcca68
VP		 4507 if (!root_dev)
4508 continue;
4509
4510 ret = update_dev_clip(root_dev, dev);
4511 if (ret)
4512 break;
4513 }
4514 return ret;
4515}
4516
4517static void update_clip(const struct adapter *adap)
4518{
4519 int i;
4520 struct net_device *dev;
4521 int ret;
4522
4523 rcu_read_lock();
4524
4525 for (i = 0; i < MAX_NPORTS; i++) {
4526 dev = adap->port[i];
4527 ret = 0;
4528
4529 if (dev)
4530 ret = update_root_dev_clip(dev);
4531
4532 if (ret < 0)
4533 break;
4534 }
4535 rcu_read_unlock();
4536}
1bb60376 4537#endif /* IS_ENABLED(CONFIG_IPV6) */
01bcca68 4538
b8ff05a9
DM		 4539/**
4540 * cxgb_up - enable the adapter
4541 * @adap: adapter being enabled
4542 *
4543 * Called when the first port is enabled, this function performs the
4544 * actions necessary to make an adapter operational, such as completing
4545 * the initialization of HW modules, and enabling interrupts.
4546 *
4547 * Must be called with the rtnl lock held.
4548 */
4549static int cxgb_up(struct adapter *adap)
4550{
aaefae9b 4551 int err;
b8ff05a9 4552
aaefae9b
DM		 4553 err = setup_sge_queues(adap);
4554 if (err)
4555 goto out;
4556 err = setup_rss(adap);
4557 if (err)
4558 goto freeq;
b8ff05a9
DM		 4559
4560 if (adap->flags & USING_MSIX) {
aaefae9b 4561 name_msix_vecs(adap);
b8ff05a9
DM		 4562 err = request_irq(adap->msix_info[0].vec, t4_nondata_intr, 0,
4563 adap->msix_info[0].desc, adap);
4564 if (err)
4565 goto irq_err;
4566
4567 err = request_msix_queue_irqs(adap);
4568 if (err) {
4569 free_irq(adap->msix_info[0].vec, adap);
4570 goto irq_err;
4571 }
4572 } else {
4573 err = request_irq(adap->pdev->irq, t4_intr_handler(adap),
4574 (adap->flags & USING_MSI) ? 0 : IRQF_SHARED,
b1a3c2b6 4575 adap->port[0]->name, adap);
b8ff05a9
DM		 4576 if (err)
4577 goto irq_err;
4578 }
4579 enable_rx(adap);
4580 t4_sge_start(adap);
4581 t4_intr_enable(adap);
aaefae9b 4582 adap->flags |= FULL_INIT_DONE;
b8ff05a9 4583 notify_ulds(adap, CXGB4_STATE_UP);
1bb60376 4584#if IS_ENABLED(CONFIG_IPV6)
01bcca68 4585 update_clip(adap);
1bb60376 4586#endif
b8ff05a9
DM		 4587 out:
4588 return err;
4589 irq_err:
4590 dev_err(adap->pdev_dev, "request_irq failed, err %d\n", err);
aaefae9b
DM		 4591 freeq:
4592 t4_free_sge_resources(adap);
b8ff05a9
DM		 4593 goto out;
4594}
4595
4596static void cxgb_down(struct adapter *adapter)
4597{
4598 t4_intr_disable(adapter);
4599 cancel_work_sync(&adapter->tid_release_task);
881806bc
VP		 4600 cancel_work_sync(&adapter->db_full_task);
4601 cancel_work_sync(&adapter->db_drop_task);
b8ff05a9 4602 adapter->tid_release_task_busy = false;
204dc3c0 4603 adapter->tid_release_head = NULL;
b8ff05a9
DM		 4604
4605 if (adapter->flags & USING_MSIX) {
4606 free_msix_queue_irqs(adapter);
4607 free_irq(adapter->msix_info[0].vec, adapter);
4608 } else
4609 free_irq(adapter->pdev->irq, adapter);
4610 quiesce_rx(adapter);
aaefae9b
DM		 4611 t4_sge_stop(adapter);
4612 t4_free_sge_resources(adapter);
4613 adapter->flags &= ~FULL_INIT_DONE;
b8ff05a9
DM		 4614}
4615
4616/*
4617 * net_device operations
4618 */
4619static int cxgb_open(struct net_device *dev)
4620{
4621 int err;
4622 struct port_info *pi = netdev_priv(dev);
4623 struct adapter *adapter = pi->adapter;
4624
6a3c869a
DM		 4625 netif_carrier_off(dev);
4626
aaefae9b
DM		 4627 if (!(adapter->flags & FULL_INIT_DONE)) {
4628 err = cxgb_up(adapter);
4629 if (err < 0)
4630 return err;
4631 }
b8ff05a9 4632
f68707b8
DM		 4633 err = link_start(dev);
4634 if (!err)
4635 netif_tx_start_all_queues(dev);
4636 return err;
b8ff05a9
DM		 4637}
4638
4639static int cxgb_close(struct net_device *dev)
4640{
b8ff05a9
DM		 4641 struct port_info *pi = netdev_priv(dev);
4642 struct adapter *adapter = pi->adapter;
4643
4644 netif_tx_stop_all_queues(dev);
4645 netif_carrier_off(dev);
060e0c75 4646 return t4_enable_vi(adapter, adapter->fn, pi->viid, false, false);
b8ff05a9
DM		 4647}
4648
f2b7e78d
VP		 4649/* Return an error number if the indicated filter isn't writable ...
4650 */
4651static int writable_filter(struct filter_entry *f)
4652{
4653 if (f->locked)
4654 return -EPERM;
4655 if (f->pending)
4656 return -EBUSY;
4657
4658 return 0;
4659}
4660
4661/* Delete the filter at the specified index (if valid). The checks for all
4662 * the common problems with doing this like the filter being locked, currently
4663 * pending in another operation, etc.
4664 */
4665static int delete_filter(struct adapter *adapter, unsigned int fidx)
4666{
4667 struct filter_entry *f;
4668 int ret;
4669
dca4faeb 4670 if (fidx >= adapter->tids.nftids + adapter->tids.nsftids)
f2b7e78d
VP		 4671 return -EINVAL;
4672
4673 f = &adapter->tids.ftid_tab[fidx];
4674 ret = writable_filter(f);
4675 if (ret)
4676 return ret;
4677 if (f->valid)
4678 return del_filter_wr(adapter, fidx);
4679
4680 return 0;
4681}
4682
dca4faeb 4683int cxgb4_create_server_filter(const struct net_device *dev, unsigned int stid,
793dad94
VP		 4684 __be32 sip, __be16 sport, __be16 vlan,
4685 unsigned int queue, unsigned char port, unsigned char mask)
dca4faeb
VP		 4686{
4687 int ret;
4688 struct filter_entry *f;
4689 struct adapter *adap;
4690 int i;
4691 u8 *val;
4692
4693 adap = netdev2adap(dev);
4694
1cab775c 4695 /* Adjust stid to correct filter index */
470c60c4 4696 stid -= adap->tids.sftid_base;
1cab775c
VP		 4697 stid += adap->tids.nftids;
4698
dca4faeb
VP		 4699 /* Check to make sure the filter requested is writable ...
4700 */
4701 f = &adap->tids.ftid_tab[stid];
4702 ret = writable_filter(f);
4703 if (ret)
4704 return ret;
4705
4706 /* Clear out any old resources being used by the filter before
4707 * we start constructing the new filter.
4708 */
4709 if (f->valid)
4710 clear_filter(adap, f);
4711
4712 /* Clear out filter specifications */
4713 memset(&f->fs, 0, sizeof(struct ch_filter_specification));
4714 f->fs.val.lport = cpu_to_be16(sport);
4715 f->fs.mask.lport = ~0;
4716 val = (u8 *)&sip;
793dad94 4717 if ((val[0] | val[1] | val[2] | val[3]) != 0) {
dca4faeb
VP		 4718 for (i = 0; i < 4; i++) {
4719 f->fs.val.lip[i] = val[i];
4720 f->fs.mask.lip[i] = ~0;
4721 }
dcf7b6f5 4722 if (adap->params.tp.vlan_pri_map & F_PORT) {
793dad94
VP		 4723 f->fs.val.iport = port;
4724 f->fs.mask.iport = mask;
4725 }
4726 }
dca4faeb 4727
dcf7b6f5 4728 if (adap->params.tp.vlan_pri_map & F_PROTOCOL) {
7c89e555
KS		 4729 f->fs.val.proto = IPPROTO_TCP;
4730 f->fs.mask.proto = ~0;
4731 }
4732
dca4faeb
VP		 4733 f->fs.dirsteer = 1;
4734 f->fs.iq = queue;
4735 /* Mark filter as locked */
4736 f->locked = 1;
4737 f->fs.rpttid = 1;
4738
4739 ret = set_filter_wr(adap, stid);
4740 if (ret) {
4741 clear_filter(adap, f);
4742 return ret;
4743 }
4744
4745 return 0;
4746}
4747EXPORT_SYMBOL(cxgb4_create_server_filter);
4748
4749int cxgb4_remove_server_filter(const struct net_device *dev, unsigned int stid,
4750 unsigned int queue, bool ipv6)
4751{
4752 int ret;
4753 struct filter_entry *f;
4754 struct adapter *adap;
4755
4756 adap = netdev2adap(dev);
1cab775c
VP		 4757
4758 /* Adjust stid to correct filter index */
470c60c4 4759 stid -= adap->tids.sftid_base;
1cab775c
VP		 4760 stid += adap->tids.nftids;
4761
dca4faeb
VP		 4762 f = &adap->tids.ftid_tab[stid];
4763 /* Unlock the filter */
4764 f->locked = 0;
4765
4766 ret = delete_filter(adap, stid);
4767 if (ret)
4768 return ret;
4769
4770 return 0;
4771}
4772EXPORT_SYMBOL(cxgb4_remove_server_filter);
4773
f5152c90
DM		 4774static struct rtnl_link_stats64 *cxgb_get_stats(struct net_device *dev,
4775 struct rtnl_link_stats64 *ns)
b8ff05a9
DM		 4776{
4777 struct port_stats stats;
4778 struct port_info *p = netdev_priv(dev);
4779 struct adapter *adapter = p->adapter;
b8ff05a9 4780
9fe6cb58
GS		 4781 /* Block retrieving statistics during EEH error
4782 * recovery. Otherwise, the recovery might fail
4783 * and the PCI device will be removed permanently
4784 */
b8ff05a9 4785 spin_lock(&adapter->stats_lock);
9fe6cb58
GS		 4786 if (!netif_device_present(dev)) {
4787 spin_unlock(&adapter->stats_lock);
4788 return ns;
4789 }
b8ff05a9
DM		 4790 t4_get_port_stats(adapter, p->tx_chan, &stats);
4791 spin_unlock(&adapter->stats_lock);
4792
4793 ns->tx_bytes = stats.tx_octets;
4794 ns->tx_packets = stats.tx_frames;
4795 ns->rx_bytes = stats.rx_octets;
4796 ns->rx_packets = stats.rx_frames;
4797 ns->multicast = stats.rx_mcast_frames;
4798
4799 /* detailed rx_errors */
4800 ns->rx_length_errors = stats.rx_jabber + stats.rx_too_long +
4801 stats.rx_runt;
4802 ns->rx_over_errors = 0;
4803 ns->rx_crc_errors = stats.rx_fcs_err;
4804 ns->rx_frame_errors = stats.rx_symbol_err;
4805 ns->rx_fifo_errors = stats.rx_ovflow0 + stats.rx_ovflow1 +
4806 stats.rx_ovflow2 + stats.rx_ovflow3 +
4807 stats.rx_trunc0 + stats.rx_trunc1 +
4808 stats.rx_trunc2 + stats.rx_trunc3;
4809 ns->rx_missed_errors = 0;
4810
4811 /* detailed tx_errors */
4812 ns->tx_aborted_errors = 0;
4813 ns->tx_carrier_errors = 0;
4814 ns->tx_fifo_errors = 0;
4815 ns->tx_heartbeat_errors = 0;
4816 ns->tx_window_errors = 0;
4817
4818 ns->tx_errors = stats.tx_error_frames;
4819 ns->rx_errors = stats.rx_symbol_err + stats.rx_fcs_err +
4820 ns->rx_length_errors + stats.rx_len_err + ns->rx_fifo_errors;
4821 return ns;
4822}
4823
4824static int cxgb_ioctl(struct net_device *dev, struct ifreq *req, int cmd)
4825{
060e0c75 4826 unsigned int mbox;
b8ff05a9
DM		 4827 int ret = 0, prtad, devad;
4828 struct port_info *pi = netdev_priv(dev);
4829 struct mii_ioctl_data *data = (struct mii_ioctl_data *)&req->ifr_data;
4830
4831 switch (cmd) {
4832 case SIOCGMIIPHY:
4833 if (pi->mdio_addr < 0)
4834 return -EOPNOTSUPP;
4835 data->phy_id = pi->mdio_addr;
4836 break;
4837 case SIOCGMIIREG:
4838 case SIOCSMIIREG:
4839 if (mdio_phy_id_is_c45(data->phy_id)) {
4840 prtad = mdio_phy_id_prtad(data->phy_id);
4841 devad = mdio_phy_id_devad(data->phy_id);
4842 } else if (data->phy_id < 32) {
4843 prtad = data->phy_id;
4844 devad = 0;
4845 data->reg_num &= 0x1f;
4846 } else
4847 return -EINVAL;
4848
060e0c75 4849 mbox = pi->adapter->fn;
b8ff05a9 4850 if (cmd == SIOCGMIIREG)
060e0c75 4851 ret = t4_mdio_rd(pi->adapter, mbox, prtad, devad,
b8ff05a9
DM		 4852 data->reg_num, &data->val_out);
4853 else
060e0c75 4854 ret = t4_mdio_wr(pi->adapter, mbox, prtad, devad,
b8ff05a9
DM		 4855 data->reg_num, data->val_in);
4856 break;
4857 default:
4858 return -EOPNOTSUPP;
4859 }
4860 return ret;
4861}
4862
4863static void cxgb_set_rxmode(struct net_device *dev)
4864{
4865 /* unfortunately we can't return errors to the stack */
4866 set_rxmode(dev, -1, false);
4867}
4868
4869static int cxgb_change_mtu(struct net_device *dev, int new_mtu)
4870{
4871 int ret;
4872 struct port_info *pi = netdev_priv(dev);
4873
4874 if (new_mtu < 81 || new_mtu > MAX_MTU) /* accommodate SACK */
4875 return -EINVAL;
060e0c75
DM		 4876 ret = t4_set_rxmode(pi->adapter, pi->adapter->fn, pi->viid, new_mtu, -1,
4877 -1, -1, -1, true);
b8ff05a9
DM		 4878 if (!ret)
4879 dev->mtu = new_mtu;
4880 return ret;
4881}
4882
4883static int cxgb_set_mac_addr(struct net_device *dev, void *p)
4884{
4885 int ret;
4886 struct sockaddr *addr = p;
4887 struct port_info *pi = netdev_priv(dev);
4888
4889 if (!is_valid_ether_addr(addr->sa_data))
504f9b5a 4890 return -EADDRNOTAVAIL;
b8ff05a9 4891
060e0c75
DM		 4892 ret = t4_change_mac(pi->adapter, pi->adapter->fn, pi->viid,
4893 pi->xact_addr_filt, addr->sa_data, true, true);
b8ff05a9
DM		 4894 if (ret < 0)
4895 return ret;
4896
4897 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
4898 pi->xact_addr_filt = ret;
4899 return 0;
4900}
4901
b8ff05a9
DM		 4902#ifdef CONFIG_NET_POLL_CONTROLLER
4903static void cxgb_netpoll(struct net_device *dev)
4904{
4905 struct port_info *pi = netdev_priv(dev);
4906 struct adapter *adap = pi->adapter;
4907
4908 if (adap->flags & USING_MSIX) {
4909 int i;
4910 struct sge_eth_rxq *rx = &adap->sge.ethrxq[pi->first_qset];
4911
4912 for (i = pi->nqsets; i; i--, rx++)
4913 t4_sge_intr_msix(0, &rx->rspq);
4914 } else
4915 t4_intr_handler(adap)(0, adap);
4916}
4917#endif
4918
4919static const struct net_device_ops cxgb4_netdev_ops = {
4920 .ndo_open = cxgb_open,
4921 .ndo_stop = cxgb_close,
4922 .ndo_start_xmit = t4_eth_xmit,
688848b1 4923 .ndo_select_queue = cxgb_select_queue,
9be793bf 4924 .ndo_get_stats64 = cxgb_get_stats,
b8ff05a9
DM		 4925 .ndo_set_rx_mode = cxgb_set_rxmode,
4926 .ndo_set_mac_address = cxgb_set_mac_addr,
2ed28baa 4927 .ndo_set_features = cxgb_set_features,
b8ff05a9
DM		 4928 .ndo_validate_addr = eth_validate_addr,
4929 .ndo_do_ioctl = cxgb_ioctl,
4930 .ndo_change_mtu = cxgb_change_mtu,
b8ff05a9
DM		 4931#ifdef CONFIG_NET_POLL_CONTROLLER
4932 .ndo_poll_controller = cxgb_netpoll,
4933#endif
4934};
4935
4936void t4_fatal_err(struct adapter *adap)
4937{
4938 t4_set_reg_field(adap, SGE_CONTROL, GLOBALENABLE, 0);
4939 t4_intr_disable(adap);
4940 dev_alert(adap->pdev_dev, "encountered fatal error, adapter stopped\n");
4941}
4942
0abfd152
HS		 4943/* Return the specified PCI-E Configuration Space register from our Physical
4944 * Function. We try first via a Firmware LDST Command since we prefer to let
4945 * the firmware own all of these registers, but if that fails we go for it
4946 * directly ourselves.
4947 */
4948static u32 t4_read_pcie_cfg4(struct adapter *adap, int reg)
4949{
4950 struct fw_ldst_cmd ldst_cmd;
4951 u32 val;
4952 int ret;
4953
4954 /* Construct and send the Firmware LDST Command to retrieve the
4955 * specified PCI-E Configuration Space register.
4956 */
4957 memset(&ldst_cmd, 0, sizeof(ldst_cmd));
4958 ldst_cmd.op_to_addrspace =
4959 htonl(FW_CMD_OP(FW_LDST_CMD) |
4960 FW_CMD_REQUEST |
4961 FW_CMD_READ |
4962 FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_FUNC_PCIE));
4963 ldst_cmd.cycles_to_len16 = htonl(FW_LEN16(ldst_cmd));
4964 ldst_cmd.u.pcie.select_naccess = FW_LDST_CMD_NACCESS(1);
4965 ldst_cmd.u.pcie.ctrl_to_fn =
4966 (FW_LDST_CMD_LC | FW_LDST_CMD_FN(adap->fn));
4967 ldst_cmd.u.pcie.r = reg;
4968 ret = t4_wr_mbox(adap, adap->mbox, &ldst_cmd, sizeof(ldst_cmd),
4969 &ldst_cmd);
4970
4971 /* If the LDST Command suucceeded, exctract the returned register
4972 * value. Otherwise read it directly ourself.
4973 */
4974 if (ret == 0)
4975 val = ntohl(ldst_cmd.u.pcie.data[0]);
4976 else
4977 t4_hw_pci_read_cfg4(adap, reg, &val);
4978
4979 return val;
4980}
4981
b8ff05a9
DM		 4982static void setup_memwin(struct adapter *adap)
4983{
0abfd152 4984 u32 mem_win0_base, mem_win1_base, mem_win2_base, mem_win2_aperture;
b8ff05a9 4985
d14807dd 4986 if (is_t4(adap->params.chip)) {
0abfd152
HS		 4987 u32 bar0;
4988
4989 /* Truncation intentional: we only read the bottom 32-bits of
4990 * the 64-bit BAR0/BAR1 ... We use the hardware backdoor
4991 * mechanism to read BAR0 instead of using
4992 * pci_resource_start() because we could be operating from
4993 * within a Virtual Machine which is trapping our accesses to
4994 * our Configuration Space and we need to set up the PCI-E
4995 * Memory Window decoders with the actual addresses which will
4996 * be coming across the PCI-E link.
4997 */
4998 bar0 = t4_read_pcie_cfg4(adap, PCI_BASE_ADDRESS_0);
4999 bar0 &= PCI_BASE_ADDRESS_MEM_MASK;
5000 adap->t4_bar0 = bar0;
5001
19dd37ba
SR		 5002 mem_win0_base = bar0 + MEMWIN0_BASE;
5003 mem_win1_base = bar0 + MEMWIN1_BASE;
5004 mem_win2_base = bar0 + MEMWIN2_BASE;
0abfd152 5005 mem_win2_aperture = MEMWIN2_APERTURE;
19dd37ba
SR		 5006 } else {
5007 /* For T5, only relative offset inside the PCIe BAR is passed */
5008 mem_win0_base = MEMWIN0_BASE;
0abfd152 5009 mem_win1_base = MEMWIN1_BASE;
19dd37ba 5010 mem_win2_base = MEMWIN2_BASE_T5;
0abfd152 5011 mem_win2_aperture = MEMWIN2_APERTURE_T5;
19dd37ba 5012 }
b8ff05a9 5013 t4_write_reg(adap, PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN, 0),
19dd37ba 5014 mem_win0_base | BIR(0) |
b8ff05a9
DM		 5015 WINDOW(ilog2(MEMWIN0_APERTURE) - 10));
5016 t4_write_reg(adap, PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN, 1),
19dd37ba 5017 mem_win1_base | BIR(0) |
b8ff05a9
DM		 5018 WINDOW(ilog2(MEMWIN1_APERTURE) - 10));
5019 t4_write_reg(adap, PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN, 2),
19dd37ba 5020 mem_win2_base | BIR(0) |
0abfd152
HS		 5021 WINDOW(ilog2(mem_win2_aperture) - 10));
5022 t4_read_reg(adap, PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN, 2));
636f9d37
VP		 5023}
5024
5025static void setup_memwin_rdma(struct adapter *adap)
5026{
1ae970e0 5027 if (adap->vres.ocq.size) {
0abfd152
HS		 5028 u32 start;
5029 unsigned int sz_kb;
1ae970e0 5030
0abfd152
HS		 5031 start = t4_read_pcie_cfg4(adap, PCI_BASE_ADDRESS_2);
5032 start &= PCI_BASE_ADDRESS_MEM_MASK;
5033 start += OCQ_WIN_OFFSET(adap->pdev, &adap->vres);
1ae970e0
DM		 5034 sz_kb = roundup_pow_of_two(adap->vres.ocq.size) >> 10;
5035 t4_write_reg(adap,
5036 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN, 3),
5037 start | BIR(1) | WINDOW(ilog2(sz_kb)));
5038 t4_write_reg(adap,
5039 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET, 3),
5040 adap->vres.ocq.start);
5041 t4_read_reg(adap,
5042 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET, 3));
5043 }
b8ff05a9
DM		 5044}
5045
02b5fb8e
DM		 5046static int adap_init1(struct adapter *adap, struct fw_caps_config_cmd *c)
5047{
5048 u32 v;
5049 int ret;
5050
5051 /* get device capabilities */
5052 memset(c, 0, sizeof(*c));
5053 c->op_to_write = htonl(FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
5054 FW_CMD_REQUEST | FW_CMD_READ);
ce91a923 5055 c->cfvalid_to_len16 = htonl(FW_LEN16(*c));
060e0c75 5056 ret = t4_wr_mbox(adap, adap->fn, c, sizeof(*c), c);
02b5fb8e
DM		 5057 if (ret < 0)
5058 return ret;
5059
5060 /* select capabilities we'll be using */
5061 if (c->niccaps & htons(FW_CAPS_CONFIG_NIC_VM)) {
5062 if (!vf_acls)
5063 c->niccaps ^= htons(FW_CAPS_CONFIG_NIC_VM);
5064 else
5065 c->niccaps = htons(FW_CAPS_CONFIG_NIC_VM);
5066 } else if (vf_acls) {
5067 dev_err(adap->pdev_dev, "virtualization ACLs not supported");
5068 return ret;
5069 }
5070 c->op_to_write = htonl(FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
5071 FW_CMD_REQUEST | FW_CMD_WRITE);
060e0c75 5072 ret = t4_wr_mbox(adap, adap->fn, c, sizeof(*c), NULL);
02b5fb8e
DM		 5073 if (ret < 0)
5074 return ret;
5075
060e0c75 5076 ret = t4_config_glbl_rss(adap, adap->fn,
02b5fb8e
DM		 5077 FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL,
5078 FW_RSS_GLB_CONFIG_CMD_TNLMAPEN |
5079 FW_RSS_GLB_CONFIG_CMD_TNLALLLKP);
5080 if (ret < 0)
5081 return ret;
5082
060e0c75
DM		 5083 ret = t4_cfg_pfvf(adap, adap->fn, adap->fn, 0, MAX_EGRQ, 64, MAX_INGQ,
5084 0, 0, 4, 0xf, 0xf, 16, FW_CMD_CAP_PF, FW_CMD_CAP_PF);
02b5fb8e
DM		 5085 if (ret < 0)
5086 return ret;
5087
5088 t4_sge_init(adap);
5089
02b5fb8e
DM		 5090 /* tweak some settings */
5091 t4_write_reg(adap, TP_SHIFT_CNT, 0x64f8849);
5092 t4_write_reg(adap, ULP_RX_TDDP_PSZ, HPZ0(PAGE_SHIFT - 12));
5093 t4_write_reg(adap, TP_PIO_ADDR, TP_INGRESS_CONFIG);
5094 v = t4_read_reg(adap, TP_PIO_DATA);
5095 t4_write_reg(adap, TP_PIO_DATA, v & ~CSUM_HAS_PSEUDO_HDR);
060e0c75 5096
dca4faeb
VP		 5097 /* first 4 Tx modulation queues point to consecutive Tx channels */
5098 adap->params.tp.tx_modq_map = 0xE4;
5099 t4_write_reg(adap, A_TP_TX_MOD_QUEUE_REQ_MAP,
5100 V_TX_MOD_QUEUE_REQ_MAP(adap->params.tp.tx_modq_map));
5101
5102 /* associate each Tx modulation queue with consecutive Tx channels */
5103 v = 0x84218421;
5104 t4_write_indirect(adap, TP_PIO_ADDR, TP_PIO_DATA,
5105 &v, 1, A_TP_TX_SCHED_HDR);
5106 t4_write_indirect(adap, TP_PIO_ADDR, TP_PIO_DATA,
5107 &v, 1, A_TP_TX_SCHED_FIFO);
5108 t4_write_indirect(adap, TP_PIO_ADDR, TP_PIO_DATA,
5109 &v, 1, A_TP_TX_SCHED_PCMD);
5110
5111#define T4_TX_MODQ_10G_WEIGHT_DEFAULT 16 /* in KB units */
5112 if (is_offload(adap)) {
5113 t4_write_reg(adap, A_TP_TX_MOD_QUEUE_WEIGHT0,
5114 V_TX_MODQ_WEIGHT0(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
5115 V_TX_MODQ_WEIGHT1(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
5116 V_TX_MODQ_WEIGHT2(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
5117 V_TX_MODQ_WEIGHT3(T4_TX_MODQ_10G_WEIGHT_DEFAULT));
5118 t4_write_reg(adap, A_TP_TX_MOD_CHANNEL_WEIGHT,
5119 V_TX_MODQ_WEIGHT0(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
5120 V_TX_MODQ_WEIGHT1(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
5121 V_TX_MODQ_WEIGHT2(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
5122 V_TX_MODQ_WEIGHT3(T4_TX_MODQ_10G_WEIGHT_DEFAULT));
5123 }
5124
060e0c75
DM		 5125 /* get basic stuff going */
5126 return t4_early_init(adap, adap->fn);
02b5fb8e
DM		 5127}
5128
b8ff05a9
DM		 5129/*
5130 * Max # of ATIDs. The absolute HW max is 16K but we keep it lower.
5131 */
5132#define MAX_ATIDS 8192U
5133
636f9d37
VP		 5134/*
5135 * Phase 0 of initialization: contact FW, obtain config, perform basic init.
5136 *
5137 * If the firmware we're dealing with has Configuration File support, then
5138 * we use that to perform all configuration
5139 */
5140
5141/*
5142 * Tweak configuration based on module parameters, etc. Most of these have
5143 * defaults assigned to them by Firmware Configuration Files (if we're using
5144 * them) but need to be explicitly set if we're using hard-coded
5145 * initialization. But even in the case of using Firmware Configuration
5146 * Files, we'd like to expose the ability to change these via module
5147 * parameters so these are essentially common tweaks/settings for
5148 * Configuration Files and hard-coded initialization ...
5149 */
5150static int adap_init0_tweaks(struct adapter *adapter)
5151{
5152 /*
5153 * Fix up various Host-Dependent Parameters like Page Size, Cache
5154 * Line Size, etc. The firmware default is for a 4KB Page Size and
5155 * 64B Cache Line Size ...
5156 */
5157 t4_fixup_host_params(adapter, PAGE_SIZE, L1_CACHE_BYTES);
5158
5159 /*
5160 * Process module parameters which affect early initialization.
5161 */
5162 if (rx_dma_offset != 2 && rx_dma_offset != 0) {
5163 dev_err(&adapter->pdev->dev,
5164 "Ignoring illegal rx_dma_offset=%d, using 2\n",
5165 rx_dma_offset);
5166 rx_dma_offset = 2;
5167 }
5168 t4_set_reg_field(adapter, SGE_CONTROL,
5169 PKTSHIFT_MASK,
5170 PKTSHIFT(rx_dma_offset));
5171
5172 /*
5173 * Don't include the "IP Pseudo Header" in CPL_RX_PKT checksums: Linux
5174 * adds the pseudo header itself.
5175 */
5176 t4_tp_wr_bits_indirect(adapter, TP_INGRESS_CONFIG,
5177 CSUM_HAS_PSEUDO_HDR, 0);
5178
5179 return 0;
5180}
5181
5182/*
5183 * Attempt to initialize the adapter via a Firmware Configuration File.
5184 */
5185static int adap_init0_config(struct adapter *adapter, int reset)
5186{
5187 struct fw_caps_config_cmd caps_cmd;
5188 const struct firmware *cf;
5189 unsigned long mtype = 0, maddr = 0;
5190 u32 finiver, finicsum, cfcsum;
16e47624
HS		 5191 int ret;
5192 int config_issued = 0;
0a57a536 5193 char *fw_config_file, fw_config_file_path[256];
16e47624 5194 char *config_name = NULL;
636f9d37
VP		 5195
5196 /*
5197 * Reset device if necessary.
5198 */
5199 if (reset) {
5200 ret = t4_fw_reset(adapter, adapter->mbox,
5201 PIORSTMODE | PIORST);
5202 if (ret < 0)
5203 goto bye;
5204 }
5205
5206 /*
5207 * If we have a T4 configuration file under /lib/firmware/cxgb4/,
5208 * then use that. Otherwise, use the configuration file stored
5209 * in the adapter flash ...
5210 */
d14807dd 5211 switch (CHELSIO_CHIP_VERSION(adapter->params.chip)) {
0a57a536 5212 case CHELSIO_T4:
16e47624 5213 fw_config_file = FW4_CFNAME;
0a57a536
SR		 5214 break;
5215 case CHELSIO_T5:
5216 fw_config_file = FW5_CFNAME;
5217 break;
5218 default:
5219 dev_err(adapter->pdev_dev, "Device %d is not supported\n",
5220 adapter->pdev->device);
5221 ret = -EINVAL;
5222 goto bye;
5223 }
5224
5225 ret = request_firmware(&cf, fw_config_file, adapter->pdev_dev);
636f9d37 5226 if (ret < 0) {
16e47624 5227 config_name = "On FLASH";
636f9d37
VP		 5228 mtype = FW_MEMTYPE_CF_FLASH;
5229 maddr = t4_flash_cfg_addr(adapter);
5230 } else {
5231 u32 params[7], val[7];
5232
16e47624
HS		 5233 sprintf(fw_config_file_path,
5234 "/lib/firmware/%s", fw_config_file);
5235 config_name = fw_config_file_path;
5236
636f9d37
VP		 5237 if (cf->size >= FLASH_CFG_MAX_SIZE)
5238 ret = -ENOMEM;
5239 else {
5240 params[0] = (FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
5241 FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_CF));
5242 ret = t4_query_params(adapter, adapter->mbox,
5243 adapter->fn, 0, 1, params, val);
5244 if (ret == 0) {
5245 /*
fc5ab020 5246 * For t4_memory_rw() below addresses and
636f9d37
VP		 5247 * sizes have to be in terms of multiples of 4
5248 * bytes. So, if the Configuration File isn't
5249 * a multiple of 4 bytes in length we'll have
5250 * to write that out separately since we can't
5251 * guarantee that the bytes following the
5252 * residual byte in the buffer returned by
5253 * request_firmware() are zeroed out ...
5254 */
5255 size_t resid = cf->size & 0x3;
5256 size_t size = cf->size & ~0x3;
5257 __be32 *data = (__be32 *)cf->data;
5258
5259 mtype = FW_PARAMS_PARAM_Y_GET(val[0]);
5260 maddr = FW_PARAMS_PARAM_Z_GET(val[0]) << 16;
5261
fc5ab020
HS		 5262 spin_lock(&adapter->win0_lock);
5263 ret = t4_memory_rw(adapter, 0, mtype, maddr,
5264 size, data, T4_MEMORY_WRITE);
636f9d37
VP		 5265 if (ret == 0 && resid != 0) {
5266 union {
5267 __be32 word;
5268 char buf[4];
5269 } last;
5270 int i;
5271
5272 last.word = data[size >> 2];
5273 for (i = resid; i < 4; i++)
5274 last.buf[i] = 0;
fc5ab020
HS		 5275 ret = t4_memory_rw(adapter, 0, mtype,
5276 maddr + size,
5277 4, &last.word,
5278 T4_MEMORY_WRITE);
636f9d37 5279 }
fc5ab020 5280 spin_unlock(&adapter->win0_lock);
636f9d37
VP		 5281 }
5282 }
5283
5284 release_firmware(cf);
5285 if (ret)
5286 goto bye;
5287 }
5288
5289 /*
5290 * Issue a Capability Configuration command to the firmware to get it
5291 * to parse the Configuration File. We don't use t4_fw_config_file()
5292 * because we want the ability to modify various features after we've
5293 * processed the configuration file ...
5294 */
5295 memset(&caps_cmd, 0, sizeof(caps_cmd));
5296 caps_cmd.op_to_write =
5297 htonl(FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
5298 FW_CMD_REQUEST |
5299 FW_CMD_READ);
ce91a923 5300 caps_cmd.cfvalid_to_len16 =
636f9d37
VP		 5301 htonl(FW_CAPS_CONFIG_CMD_CFVALID |
5302 FW_CAPS_CONFIG_CMD_MEMTYPE_CF(mtype) |
5303 FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(maddr >> 16) |
5304 FW_LEN16(caps_cmd));
5305 ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd, sizeof(caps_cmd),
5306 &caps_cmd);
16e47624
HS		 5307
5308 /* If the CAPS_CONFIG failed with an ENOENT (for a Firmware
5309 * Configuration File in FLASH), our last gasp effort is to use the
5310 * Firmware Configuration File which is embedded in the firmware. A
5311 * very few early versions of the firmware didn't have one embedded
5312 * but we can ignore those.
5313 */
5314 if (ret == -ENOENT) {
5315 memset(&caps_cmd, 0, sizeof(caps_cmd));
5316 caps_cmd.op_to_write =
5317 htonl(FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
5318 FW_CMD_REQUEST |
5319 FW_CMD_READ);
5320 caps_cmd.cfvalid_to_len16 = htonl(FW_LEN16(caps_cmd));
5321 ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd,
5322 sizeof(caps_cmd), &caps_cmd);
5323 config_name = "Firmware Default";
5324 }
5325
5326 config_issued = 1;
636f9d37
VP		 5327 if (ret < 0)
5328 goto bye;
5329
5330 finiver = ntohl(caps_cmd.finiver);
5331 finicsum = ntohl(caps_cmd.finicsum);
5332 cfcsum = ntohl(caps_cmd.cfcsum);
5333 if (finicsum != cfcsum)
5334 dev_warn(adapter->pdev_dev, "Configuration File checksum "\
5335 "mismatch: [fini] csum=%#x, computed csum=%#x\n",
5336 finicsum, cfcsum);
5337
636f9d37
VP		 5338 /*
5339 * And now tell the firmware to use the configuration we just loaded.
5340 */
5341 caps_cmd.op_to_write =
5342 htonl(FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
5343 FW_CMD_REQUEST |
5344 FW_CMD_WRITE);
ce91a923 5345 caps_cmd.cfvalid_to_len16 = htonl(FW_LEN16(caps_cmd));
636f9d37
VP		 5346 ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd, sizeof(caps_cmd),
5347 NULL);
5348 if (ret < 0)
5349 goto bye;
5350
5351 /*
5352 * Tweak configuration based on system architecture, module
5353 * parameters, etc.
5354 */
5355 ret = adap_init0_tweaks(adapter);
5356 if (ret < 0)
5357 goto bye;
5358
5359 /*
5360 * And finally tell the firmware to initialize itself using the
5361 * parameters from the Configuration File.
5362 */
5363 ret = t4_fw_initialize(adapter, adapter->mbox);
5364 if (ret < 0)
5365 goto bye;
5366
5367 /*
5368 * Return successfully and note that we're operating with parameters
5369 * not supplied by the driver, rather than from hard-wired
5370 * initialization constants burried in the driver.
5371 */
5372 adapter->flags |= USING_SOFT_PARAMS;
5373 dev_info(adapter->pdev_dev, "Successfully configured using Firmware "\
16e47624
HS		 5374 "Configuration File \"%s\", version %#x, computed checksum %#x\n",
5375 config_name, finiver, cfcsum);
636f9d37
VP		 5376 return 0;
5377
5378 /*
5379 * Something bad happened. Return the error ... (If the "error"
5380 * is that there's no Configuration File on the adapter we don't
5381 * want to issue a warning since this is fairly common.)
5382 */
5383bye:
16e47624
HS		 5384 if (config_issued && ret != -ENOENT)
5385 dev_warn(adapter->pdev_dev, "\"%s\" configuration file error %d\n",
5386 config_name, -ret);
636f9d37
VP		 5387 return ret;
5388}
5389
13ee15d3
VP		 5390/*
5391 * Attempt to initialize the adapter via hard-coded, driver supplied
5392 * parameters ...
5393 */
5394static int adap_init0_no_config(struct adapter *adapter, int reset)
5395{
5396 struct sge *s = &adapter->sge;
5397 struct fw_caps_config_cmd caps_cmd;
5398 u32 v;
5399 int i, ret;
5400
5401 /*
5402 * Reset device if necessary
5403 */
5404 if (reset) {
5405 ret = t4_fw_reset(adapter, adapter->mbox,
5406 PIORSTMODE | PIORST);
5407 if (ret < 0)
5408 goto bye;
5409 }
5410
5411 /*
5412 * Get device capabilities and select which we'll be using.
5413 */
5414 memset(&caps_cmd, 0, sizeof(caps_cmd));
5415 caps_cmd.op_to_write = htonl(FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
5416 FW_CMD_REQUEST | FW_CMD_READ);
ce91a923 5417 caps_cmd.cfvalid_to_len16 = htonl(FW_LEN16(caps_cmd));
13ee15d3
VP		 5418 ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd, sizeof(caps_cmd),
5419 &caps_cmd);
5420 if (ret < 0)
5421 goto bye;
5422
13ee15d3
VP		 5423 if (caps_cmd.niccaps & htons(FW_CAPS_CONFIG_NIC_VM)) {
5424 if (!vf_acls)
5425 caps_cmd.niccaps ^= htons(FW_CAPS_CONFIG_NIC_VM);
5426 else
5427 caps_cmd.niccaps = htons(FW_CAPS_CONFIG_NIC_VM);
5428 } else if (vf_acls) {
5429 dev_err(adapter->pdev_dev, "virtualization ACLs not supported");
5430 goto bye;
5431 }
5432 caps_cmd.op_to_write = htonl(FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
5433 FW_CMD_REQUEST | FW_CMD_WRITE);
5434 ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd, sizeof(caps_cmd),
5435 NULL);
5436 if (ret < 0)
5437 goto bye;
5438
5439 /*
5440 * Tweak configuration based on system architecture, module
5441 * parameters, etc.
5442 */
5443 ret = adap_init0_tweaks(adapter);
5444 if (ret < 0)
5445 goto bye;
5446
5447 /*
5448 * Select RSS Global Mode we want to use. We use "Basic Virtual"
5449 * mode which maps each Virtual Interface to its own section of
5450 * the RSS Table and we turn on all map and hash enables ...
5451 */
5452 adapter->flags |= RSS_TNLALLLOOKUP;
5453 ret = t4_config_glbl_rss(adapter, adapter->mbox,
5454 FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL,
5455 FW_RSS_GLB_CONFIG_CMD_TNLMAPEN |
5456 FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ |
5457 ((adapter->flags & RSS_TNLALLLOOKUP) ?
5458 FW_RSS_GLB_CONFIG_CMD_TNLALLLKP : 0));
5459 if (ret < 0)
5460 goto bye;
5461
5462 /*
5463 * Set up our own fundamental resource provisioning ...
5464 */
5465 ret = t4_cfg_pfvf(adapter, adapter->mbox, adapter->fn, 0,
5466 PFRES_NEQ, PFRES_NETHCTRL,
5467 PFRES_NIQFLINT, PFRES_NIQ,
5468 PFRES_TC, PFRES_NVI,
5469 FW_PFVF_CMD_CMASK_MASK,
5470 pfvfres_pmask(adapter, adapter->fn, 0),
5471 PFRES_NEXACTF,
5472 PFRES_R_CAPS, PFRES_WX_CAPS);
5473 if (ret < 0)
5474 goto bye;
5475
5476 /*
5477 * Perform low level SGE initialization. We need to do this before we
5478 * send the firmware the INITIALIZE command because that will cause
5479 * any other PF Drivers which are waiting for the Master
5480 * Initialization to proceed forward.
5481 */
5482 for (i = 0; i < SGE_NTIMERS - 1; i++)
5483 s->timer_val[i] = min(intr_holdoff[i], MAX_SGE_TIMERVAL);
5484 s->timer_val[SGE_NTIMERS - 1] = MAX_SGE_TIMERVAL;
5485 s->counter_val[0] = 1;
5486 for (i = 1; i < SGE_NCOUNTERS; i++)
5487 s->counter_val[i] = min(intr_cnt[i - 1],
5488 THRESHOLD_0_GET(THRESHOLD_0_MASK));
5489 t4_sge_init(adapter);
5490
5491#ifdef CONFIG_PCI_IOV
5492 /*
5493 * Provision resource limits for Virtual Functions. We currently
5494 * grant them all the same static resource limits except for the Port
5495 * Access Rights Mask which we're assigning based on the PF. All of
5496 * the static provisioning stuff for both the PF and VF really needs
5497 * to be managed in a persistent manner for each device which the
5498 * firmware controls.
5499 */
5500 {
5501 int pf, vf;
5502
7d6727cf 5503 for (pf = 0; pf < ARRAY_SIZE(num_vf); pf++) {
13ee15d3
VP		 5504 if (num_vf[pf] <= 0)
5505 continue;
5506
5507 /* VF numbering starts at 1! */
5508 for (vf = 1; vf <= num_vf[pf]; vf++) {
5509 ret = t4_cfg_pfvf(adapter, adapter->mbox,
5510 pf, vf,
5511 VFRES_NEQ, VFRES_NETHCTRL,
5512 VFRES_NIQFLINT, VFRES_NIQ,
5513 VFRES_TC, VFRES_NVI,
1f1e4958 5514 FW_PFVF_CMD_CMASK_MASK,
13ee15d3
VP		 5515 pfvfres_pmask(
5516 adapter, pf, vf),
5517 VFRES_NEXACTF,
5518 VFRES_R_CAPS, VFRES_WX_CAPS);
5519 if (ret < 0)
5520 dev_warn(adapter->pdev_dev,
5521 "failed to "\
5522 "provision pf/vf=%d/%d; "
5523 "err=%d\n", pf, vf, ret);
5524 }
5525 }
5526 }
5527#endif
5528
5529 /*
5530 * Set up the default filter mode. Later we'll want to implement this
5531 * via a firmware command, etc. ... This needs to be done before the
5532 * firmare initialization command ... If the selected set of fields
5533 * isn't equal to the default value, we'll need to make sure that the
5534 * field selections will fit in the 36-bit budget.
5535 */
5536 if (tp_vlan_pri_map != TP_VLAN_PRI_MAP_DEFAULT) {
404d9e3f 5537 int j, bits = 0;
13ee15d3 5538
404d9e3f
VP		 5539 for (j = TP_VLAN_PRI_MAP_FIRST; j <= TP_VLAN_PRI_MAP_LAST; j++)
5540 switch (tp_vlan_pri_map & (1 << j)) {
13ee15d3
VP		 5541 case 0:
5542 /* compressed filter field not enabled */
5543 break;
5544 case FCOE_MASK:
5545 bits += 1;
5546 break;
5547 case PORT_MASK:
5548 bits += 3;
5549 break;
5550 case VNIC_ID_MASK:
5551 bits += 17;
5552 break;
5553 case VLAN_MASK:
5554 bits += 17;
5555 break;
5556 case TOS_MASK:
5557 bits += 8;
5558 break;
5559 case PROTOCOL_MASK:
5560 bits += 8;
5561 break;
5562 case ETHERTYPE_MASK:
5563 bits += 16;
5564 break;
5565 case MACMATCH_MASK:
5566 bits += 9;
5567 break;
5568 case MPSHITTYPE_MASK:
5569 bits += 3;
5570 break;
5571 case FRAGMENTATION_MASK:
5572 bits += 1;
5573 break;
5574 }
5575
5576 if (bits > 36) {
5577 dev_err(adapter->pdev_dev,
5578 "tp_vlan_pri_map=%#x needs %d bits > 36;"\
5579 " using %#x\n", tp_vlan_pri_map, bits,
5580 TP_VLAN_PRI_MAP_DEFAULT);
5581 tp_vlan_pri_map = TP_VLAN_PRI_MAP_DEFAULT;
5582 }
5583 }
5584 v = tp_vlan_pri_map;
5585 t4_write_indirect(adapter, TP_PIO_ADDR, TP_PIO_DATA,
5586 &v, 1, TP_VLAN_PRI_MAP);
5587
5588 /*
5589 * We need Five Tuple Lookup mode to be set in TP_GLOBAL_CONFIG order
5590 * to support any of the compressed filter fields above. Newer
5591 * versions of the firmware do this automatically but it doesn't hurt
5592 * to set it here. Meanwhile, we do _not_ need to set Lookup Every
5593 * Packet in TP_INGRESS_CONFIG to support matching non-TCP packets
5594 * since the firmware automatically turns this on and off when we have
5595 * a non-zero number of filters active (since it does have a
5596 * performance impact).
5597 */
5598 if (tp_vlan_pri_map)
5599 t4_set_reg_field(adapter, TP_GLOBAL_CONFIG,
5600 FIVETUPLELOOKUP_MASK,
5601 FIVETUPLELOOKUP_MASK);
5602
5603 /*
5604 * Tweak some settings.
5605 */
5606 t4_write_reg(adapter, TP_SHIFT_CNT, SYNSHIFTMAX(6) |
5607 RXTSHIFTMAXR1(4) | RXTSHIFTMAXR2(15) |
5608 PERSHIFTBACKOFFMAX(8) | PERSHIFTMAX(8) |
5609 KEEPALIVEMAXR1(4) | KEEPALIVEMAXR2(9));
5610
5611 /*
5612 * Get basic stuff going by issuing the Firmware Initialize command.
5613 * Note that this _must_ be after all PFVF commands ...
5614 */
5615 ret = t4_fw_initialize(adapter, adapter->mbox);
5616 if (ret < 0)
5617 goto bye;
5618
5619 /*
5620 * Return successfully!
5621 */
5622 dev_info(adapter->pdev_dev, "Successfully configured using built-in "\
5623 "driver parameters\n");
5624 return 0;
5625
5626 /*
5627 * Something bad happened. Return the error ...
5628 */
5629bye:
5630 return ret;
5631}
5632
16e47624
HS		 5633static struct fw_info fw_info_array[] = {
5634 {
5635 .chip = CHELSIO_T4,
5636 .fs_name = FW4_CFNAME,
5637 .fw_mod_name = FW4_FNAME,
5638 .fw_hdr = {
5639 .chip = FW_HDR_CHIP_T4,
5640 .fw_ver = __cpu_to_be32(FW_VERSION(T4)),
5641 .intfver_nic = FW_INTFVER(T4, NIC),
5642 .intfver_vnic = FW_INTFVER(T4, VNIC),
5643 .intfver_ri = FW_INTFVER(T4, RI),
5644 .intfver_iscsi = FW_INTFVER(T4, ISCSI),
5645 .intfver_fcoe = FW_INTFVER(T4, FCOE),
5646 },
5647 }, {
5648 .chip = CHELSIO_T5,
5649 .fs_name = FW5_CFNAME,
5650 .fw_mod_name = FW5_FNAME,
5651 .fw_hdr = {
5652 .chip = FW_HDR_CHIP_T5,
5653 .fw_ver = __cpu_to_be32(FW_VERSION(T5)),
5654 .intfver_nic = FW_INTFVER(T5, NIC),
5655 .intfver_vnic = FW_INTFVER(T5, VNIC),
5656 .intfver_ri = FW_INTFVER(T5, RI),
5657 .intfver_iscsi = FW_INTFVER(T5, ISCSI),
5658 .intfver_fcoe = FW_INTFVER(T5, FCOE),
5659 },
5660 }
5661};
5662
5663static struct fw_info *find_fw_info(int chip)
5664{
5665 int i;
5666
5667 for (i = 0; i < ARRAY_SIZE(fw_info_array); i++) {
5668 if (fw_info_array[i].chip == chip)
5669 return &fw_info_array[i];
5670 }
5671 return NULL;
5672}
5673
b8ff05a9
DM		 5674/*
5675 * Phase 0 of initialization: contact FW, obtain config, perform basic init.
5676 */
5677static int adap_init0(struct adapter *adap)
5678{
5679 int ret;
5680 u32 v, port_vec;
5681 enum dev_state state;
5682 u32 params[7], val[7];
9a4da2cd 5683 struct fw_caps_config_cmd caps_cmd;
dcf7b6f5 5684 int reset = 1;
b8ff05a9 5685
636f9d37
VP		 5686 /*
5687 * Contact FW, advertising Master capability (and potentially forcing
5688 * ourselves as the Master PF if our module parameter force_init is
5689 * set).
5690 */
5691 ret = t4_fw_hello(adap, adap->mbox, adap->fn,
5692 force_init ? MASTER_MUST : MASTER_MAY,
5693 &state);
b8ff05a9
DM		 5694 if (ret < 0) {
5695 dev_err(adap->pdev_dev, "could not connect to FW, error %d\n",
5696 ret);
5697 return ret;
5698 }
636f9d37
VP		 5699 if (ret == adap->mbox)
5700 adap->flags |= MASTER_PF;
5701 if (force_init && state == DEV_STATE_INIT)
5702 state = DEV_STATE_UNINIT;
b8ff05a9 5703
636f9d37
VP		 5704 /*
5705 * If we're the Master PF Driver and the device is uninitialized,
5706 * then let's consider upgrading the firmware ... (We always want
5707 * to check the firmware version number in order to A. get it for
5708 * later reporting and B. to warn if the currently loaded firmware
5709 * is excessively mismatched relative to the driver.)
5710 */
16e47624
HS		 5711 t4_get_fw_version(adap, &adap->params.fw_vers);
5712 t4_get_tp_version(adap, &adap->params.tp_vers);
636f9d37 5713 if ((adap->flags & MASTER_PF) && state != DEV_STATE_INIT) {
16e47624
HS		 5714 struct fw_info *fw_info;
5715 struct fw_hdr *card_fw;
5716 const struct firmware *fw;
5717 const u8 *fw_data = NULL;
5718 unsigned int fw_size = 0;
5719
5720 /* This is the firmware whose headers the driver was compiled
5721 * against
5722 */
5723 fw_info = find_fw_info(CHELSIO_CHIP_VERSION(adap->params.chip));
5724 if (fw_info == NULL) {
5725 dev_err(adap->pdev_dev,
5726 "unable to get firmware info for chip %d.\n",
5727 CHELSIO_CHIP_VERSION(adap->params.chip));
5728 return -EINVAL;
636f9d37 5729 }
16e47624
HS		 5730
5731 /* allocate memory to read the header of the firmware on the
5732 * card
5733 */
5734 card_fw = t4_alloc_mem(sizeof(*card_fw));
5735
5736 /* Get FW from from /lib/firmware/ */
5737 ret = request_firmware(&fw, fw_info->fw_mod_name,
5738 adap->pdev_dev);
5739 if (ret < 0) {
5740 dev_err(adap->pdev_dev,
5741 "unable to load firmware image %s, error %d\n",
5742 fw_info->fw_mod_name, ret);
5743 } else {
5744 fw_data = fw->data;
5745 fw_size = fw->size;
5746 }
5747
5748 /* upgrade FW logic */
5749 ret = t4_prep_fw(adap, fw_info, fw_data, fw_size, card_fw,
5750 state, &reset);
5751
5752 /* Cleaning up */
5753 if (fw != NULL)
5754 release_firmware(fw);
5755 t4_free_mem(card_fw);
5756
636f9d37 5757 if (ret < 0)
16e47624 5758 goto bye;
636f9d37 5759 }
b8ff05a9 5760
636f9d37
VP		 5761 /*
5762 * Grab VPD parameters. This should be done after we establish a
5763 * connection to the firmware since some of the VPD parameters
5764 * (notably the Core Clock frequency) are retrieved via requests to
5765 * the firmware. On the other hand, we need these fairly early on
5766 * so we do this right after getting ahold of the firmware.
5767 */
5768 ret = get_vpd_params(adap, &adap->params.vpd);
a0881cab
DM		 5769 if (ret < 0)
5770 goto bye;
a0881cab 5771
636f9d37 5772 /*
13ee15d3
VP		 5773 * Find out what ports are available to us. Note that we need to do
5774 * this before calling adap_init0_no_config() since it needs nports
5775 * and portvec ...
636f9d37
VP		 5776 */
5777 v =
5778 FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
5779 FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_PORTVEC);
5780 ret = t4_query_params(adap, adap->mbox, adap->fn, 0, 1, &v, &port_vec);
a0881cab
DM		 5781 if (ret < 0)
5782 goto bye;
5783
636f9d37
VP		 5784 adap->params.nports = hweight32(port_vec);
5785 adap->params.portvec = port_vec;
5786
5787 /*
5788 * If the firmware is initialized already (and we're not forcing a
5789 * master initialization), note that we're living with existing
5790 * adapter parameters. Otherwise, it's time to try initializing the
5791 * adapter ...
5792 */
5793 if (state == DEV_STATE_INIT) {
5794 dev_info(adap->pdev_dev, "Coming up as %s: "\
5795 "Adapter already initialized\n",
5796 adap->flags & MASTER_PF ? "MASTER" : "SLAVE");
5797 adap->flags |= USING_SOFT_PARAMS;
5798 } else {
5799 dev_info(adap->pdev_dev, "Coming up as MASTER: "\
5800 "Initializing adapter\n");
636f9d37
VP		 5801
5802 /*
5803 * If the firmware doesn't support Configuration
5804 * Files warn user and exit,
5805 */
5806 if (ret < 0)
13ee15d3 5807 dev_warn(adap->pdev_dev, "Firmware doesn't support "
636f9d37 5808 "configuration file.\n");
13ee15d3
VP		 5809 if (force_old_init)
5810 ret = adap_init0_no_config(adap, reset);
636f9d37
VP		 5811 else {
5812 /*
13ee15d3
VP		 5813 * Find out whether we're dealing with a version of
5814 * the firmware which has configuration file support.
636f9d37 5815 */
13ee15d3
VP		 5816 params[0] = (FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
5817 FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_CF));
5818 ret = t4_query_params(adap, adap->mbox, adap->fn, 0, 1,
5819 params, val);
636f9d37 5820
13ee15d3
VP		 5821 /*
5822 * If the firmware doesn't support Configuration
5823 * Files, use the old Driver-based, hard-wired
5824 * initialization. Otherwise, try using the
5825 * Configuration File support and fall back to the
5826 * Driver-based initialization if there's no
5827 * Configuration File found.
5828 */
5829 if (ret < 0)
5830 ret = adap_init0_no_config(adap, reset);
5831 else {
5832 /*
5833 * The firmware provides us with a memory
5834 * buffer where we can load a Configuration
5835 * File from the host if we want to override
5836 * the Configuration File in flash.
5837 */
5838
5839 ret = adap_init0_config(adap, reset);
5840 if (ret == -ENOENT) {
5841 dev_info(adap->pdev_dev,
5842 "No Configuration File present "
16e47624 5843 "on adapter. Using hard-wired "
13ee15d3
VP		 5844 "configuration parameters.\n");
5845 ret = adap_init0_no_config(adap, reset);
5846 }
636f9d37
VP		 5847 }
5848 }
5849 if (ret < 0) {
5850 dev_err(adap->pdev_dev,
5851 "could not initialize adapter, error %d\n",
5852 -ret);
5853 goto bye;
5854 }
5855 }
5856
5857 /*
5858 * If we're living with non-hard-coded parameters (either from a
5859 * Firmware Configuration File or values programmed by a different PF
5860 * Driver), give the SGE code a chance to pull in anything that it
5861 * needs ... Note that this must be called after we retrieve our VPD
5862 * parameters in order to know how to convert core ticks to seconds.
5863 */
5864 if (adap->flags & USING_SOFT_PARAMS) {
5865 ret = t4_sge_init(adap);
5866 if (ret < 0)
5867 goto bye;
5868 }
5869
9a4da2cd
VP		 5870 if (is_bypass_device(adap->pdev->device))
5871 adap->params.bypass = 1;
5872
636f9d37
VP		 5873 /*
5874 * Grab some of our basic fundamental operating parameters.
5875 */
5876#define FW_PARAM_DEV(param) \
5877 (FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | \
5878 FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_##param))
5879
b8ff05a9 5880#define FW_PARAM_PFVF(param) \
636f9d37
VP		 5881 FW_PARAMS_MNEM(FW_PARAMS_MNEM_PFVF) | \
5882 FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_PFVF_##param)| \
5883 FW_PARAMS_PARAM_Y(0) | \
5884 FW_PARAMS_PARAM_Z(0)
b8ff05a9 5885
636f9d37 5886 params[0] = FW_PARAM_PFVF(EQ_START);
b8ff05a9
DM		 5887 params[1] = FW_PARAM_PFVF(L2T_START);
5888 params[2] = FW_PARAM_PFVF(L2T_END);
5889 params[3] = FW_PARAM_PFVF(FILTER_START);
5890 params[4] = FW_PARAM_PFVF(FILTER_END);
e46dab4d 5891 params[5] = FW_PARAM_PFVF(IQFLINT_START);
636f9d37 5892 ret = t4_query_params(adap, adap->mbox, adap->fn, 0, 6, params, val);
b8ff05a9
DM		 5893 if (ret < 0)
5894 goto bye;
636f9d37
VP		 5895 adap->sge.egr_start = val[0];
5896 adap->l2t_start = val[1];
5897 adap->l2t_end = val[2];
b8ff05a9
DM		 5898 adap->tids.ftid_base = val[3];
5899 adap->tids.nftids = val[4] - val[3] + 1;
e46dab4d 5900 adap->sge.ingr_start = val[5];
b8ff05a9 5901
636f9d37
VP		 5902 /* query params related to active filter region */
5903 params[0] = FW_PARAM_PFVF(ACTIVE_FILTER_START);
5904 params[1] = FW_PARAM_PFVF(ACTIVE_FILTER_END);
5905 ret = t4_query_params(adap, adap->mbox, adap->fn, 0, 2, params, val);
5906 /* If Active filter size is set we enable establishing
5907 * offload connection through firmware work request
5908 */
5909 if ((val[0] != val[1]) && (ret >= 0)) {
5910 adap->flags |= FW_OFLD_CONN;
5911 adap->tids.aftid_base = val[0];
5912 adap->tids.aftid_end = val[1];
5913 }
5914
b407a4a9
VP		 5915 /* If we're running on newer firmware, let it know that we're
5916 * prepared to deal with encapsulated CPL messages. Older
5917 * firmware won't understand this and we'll just get
5918 * unencapsulated messages ...
5919 */
5920 params[0] = FW_PARAM_PFVF(CPLFW4MSG_ENCAP);
5921 val[0] = 1;
5922 (void) t4_set_params(adap, adap->mbox, adap->fn, 0, 1, params, val);
5923
1ac0f095
KS		 5924 /*
5925 * Find out whether we're allowed to use the T5+ ULPTX MEMWRITE DSGL
5926 * capability. Earlier versions of the firmware didn't have the
5927 * ULPTX_MEMWRITE_DSGL so we'll interpret a query failure as no
5928 * permission to use ULPTX MEMWRITE DSGL.
5929 */
5930 if (is_t4(adap->params.chip)) {
5931 adap->params.ulptx_memwrite_dsgl = false;
5932 } else {
5933 params[0] = FW_PARAM_DEV(ULPTX_MEMWRITE_DSGL);
5934 ret = t4_query_params(adap, adap->mbox, adap->fn, 0,
5935 1, params, val);
5936 adap->params.ulptx_memwrite_dsgl = (ret == 0 && val[0] != 0);
5937 }
5938
636f9d37
VP		 5939 /*
5940 * Get device capabilities so we can determine what resources we need
5941 * to manage.
5942 */
5943 memset(&caps_cmd, 0, sizeof(caps_cmd));
9a4da2cd 5944 caps_cmd.op_to_write = htonl(FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
13ee15d3 5945 FW_CMD_REQUEST | FW_CMD_READ);
ce91a923 5946 caps_cmd.cfvalid_to_len16 = htonl(FW_LEN16(caps_cmd));
636f9d37
VP		 5947 ret = t4_wr_mbox(adap, adap->mbox, &caps_cmd, sizeof(caps_cmd),
5948 &caps_cmd);
5949 if (ret < 0)
5950 goto bye;
5951
13ee15d3 5952 if (caps_cmd.ofldcaps) {
b8ff05a9
DM		 5953 /* query offload-related parameters */
5954 params[0] = FW_PARAM_DEV(NTID);
5955 params[1] = FW_PARAM_PFVF(SERVER_START);
5956 params[2] = FW_PARAM_PFVF(SERVER_END);
5957 params[3] = FW_PARAM_PFVF(TDDP_START);
5958 params[4] = FW_PARAM_PFVF(TDDP_END);
5959 params[5] = FW_PARAM_DEV(FLOWC_BUFFIFO_SZ);
636f9d37
VP		 5960 ret = t4_query_params(adap, adap->mbox, adap->fn, 0, 6,
5961 params, val);
b8ff05a9
DM		 5962 if (ret < 0)
5963 goto bye;
5964 adap->tids.ntids = val[0];
5965 adap->tids.natids = min(adap->tids.ntids / 2, MAX_ATIDS);
5966 adap->tids.stid_base = val[1];
5967 adap->tids.nstids = val[2] - val[1] + 1;
636f9d37
VP		 5968 /*
5969 * Setup server filter region. Divide the availble filter
5970 * region into two parts. Regular filters get 1/3rd and server
5971 * filters get 2/3rd part. This is only enabled if workarond
5972 * path is enabled.
5973 * 1. For regular filters.
5974 * 2. Server filter: This are special filters which are used
5975 * to redirect SYN packets to offload queue.
5976 */
5977 if (adap->flags & FW_OFLD_CONN && !is_bypass(adap)) {
5978 adap->tids.sftid_base = adap->tids.ftid_base +
5979 DIV_ROUND_UP(adap->tids.nftids, 3);
5980 adap->tids.nsftids = adap->tids.nftids -
5981 DIV_ROUND_UP(adap->tids.nftids, 3);
5982 adap->tids.nftids = adap->tids.sftid_base -
5983 adap->tids.ftid_base;
5984 }
b8ff05a9
DM		 5985 adap->vres.ddp.start = val[3];
5986 adap->vres.ddp.size = val[4] - val[3] + 1;
5987 adap->params.ofldq_wr_cred = val[5];
636f9d37 5988
b8ff05a9
DM		 5989 adap->params.offload = 1;
5990 }
636f9d37 5991 if (caps_cmd.rdmacaps) {
b8ff05a9
DM		 5992 params[0] = FW_PARAM_PFVF(STAG_START);
5993 params[1] = FW_PARAM_PFVF(STAG_END);
5994 params[2] = FW_PARAM_PFVF(RQ_START);
5995 params[3] = FW_PARAM_PFVF(RQ_END);
5996 params[4] = FW_PARAM_PFVF(PBL_START);
5997 params[5] = FW_PARAM_PFVF(PBL_END);
636f9d37
VP		 5998 ret = t4_query_params(adap, adap->mbox, adap->fn, 0, 6,
5999 params, val);
b8ff05a9
DM		 6000 if (ret < 0)
6001 goto bye;
6002 adap->vres.stag.start = val[0];
6003 adap->vres.stag.size = val[1] - val[0] + 1;
6004 adap->vres.rq.start = val[2];
6005 adap->vres.rq.size = val[3] - val[2] + 1;
6006 adap->vres.pbl.start = val[4];
6007 adap->vres.pbl.size = val[5] - val[4] + 1;
a0881cab
DM		 6008
6009 params[0] = FW_PARAM_PFVF(SQRQ_START);
6010 params[1] = FW_PARAM_PFVF(SQRQ_END);
6011 params[2] = FW_PARAM_PFVF(CQ_START);
6012 params[3] = FW_PARAM_PFVF(CQ_END);
1ae970e0
DM		 6013 params[4] = FW_PARAM_PFVF(OCQ_START);
6014 params[5] = FW_PARAM_PFVF(OCQ_END);
5c937dd3
HS		 6015 ret = t4_query_params(adap, adap->mbox, adap->fn, 0, 6, params,
6016 val);
a0881cab
DM		 6017 if (ret < 0)
6018 goto bye;
6019 adap->vres.qp.start = val[0];
6020 adap->vres.qp.size = val[1] - val[0] + 1;
6021 adap->vres.cq.start = val[2];
6022 adap->vres.cq.size = val[3] - val[2] + 1;
1ae970e0
DM		 6023 adap->vres.ocq.start = val[4];
6024 adap->vres.ocq.size = val[5] - val[4] + 1;
4c2c5763
HS		 6025
6026 params[0] = FW_PARAM_DEV(MAXORDIRD_QP);
6027 params[1] = FW_PARAM_DEV(MAXIRD_ADAPTER);
5c937dd3
HS		 6028 ret = t4_query_params(adap, adap->mbox, adap->fn, 0, 2, params,
6029 val);
4c2c5763
HS		 6030 if (ret < 0) {
6031 adap->params.max_ordird_qp = 8;
6032 adap->params.max_ird_adapter = 32 * adap->tids.ntids;
6033 ret = 0;
6034 } else {
6035 adap->params.max_ordird_qp = val[0];
6036 adap->params.max_ird_adapter = val[1];
6037 }
6038 dev_info(adap->pdev_dev,
6039 "max_ordird_qp %d max_ird_adapter %d\n",
6040 adap->params.max_ordird_qp,
6041 adap->params.max_ird_adapter);
b8ff05a9 6042 }
636f9d37 6043 if (caps_cmd.iscsicaps) {
b8ff05a9
DM		 6044 params[0] = FW_PARAM_PFVF(ISCSI_START);
6045 params[1] = FW_PARAM_PFVF(ISCSI_END);
636f9d37
VP		 6046 ret = t4_query_params(adap, adap->mbox, adap->fn, 0, 2,
6047 params, val);
b8ff05a9
DM		 6048 if (ret < 0)
6049 goto bye;
6050 adap->vres.iscsi.start = val[0];
6051 adap->vres.iscsi.size = val[1] - val[0] + 1;
6052 }
6053#undef FW_PARAM_PFVF
6054#undef FW_PARAM_DEV
6055
92e7ae71
HS		 6056 /* The MTU/MSS Table is initialized by now, so load their values. If
6057 * we're initializing the adapter, then we'll make any modifications
6058 * we want to the MTU/MSS Table and also initialize the congestion
6059 * parameters.
636f9d37 6060 */
b8ff05a9 6061 t4_read_mtu_tbl(adap, adap->params.mtus, NULL);
92e7ae71
HS		 6062 if (state != DEV_STATE_INIT) {
6063 int i;
6064
6065 /* The default MTU Table contains values 1492 and 1500.
6066 * However, for TCP, it's better to have two values which are
6067 * a multiple of 8 +/- 4 bytes apart near this popular MTU.
6068 * This allows us to have a TCP Data Payload which is a
6069 * multiple of 8 regardless of what combination of TCP Options
6070 * are in use (always a multiple of 4 bytes) which is
6071 * important for performance reasons. For instance, if no
6072 * options are in use, then we have a 20-byte IP header and a
6073 * 20-byte TCP header. In this case, a 1500-byte MSS would
6074 * result in a TCP Data Payload of 1500 - 40 == 1460 bytes
6075 * which is not a multiple of 8. So using an MSS of 1488 in
6076 * this case results in a TCP Data Payload of 1448 bytes which
6077 * is a multiple of 8. On the other hand, if 12-byte TCP Time
6078 * Stamps have been negotiated, then an MTU of 1500 bytes
6079 * results in a TCP Data Payload of 1448 bytes which, as
6080 * above, is a multiple of 8 bytes ...
6081 */
6082 for (i = 0; i < NMTUS; i++)
6083 if (adap->params.mtus[i] == 1492) {
6084 adap->params.mtus[i] = 1488;
6085 break;
6086 }
7ee9ff94 6087
92e7ae71
HS		 6088 t4_load_mtus(adap, adap->params.mtus, adap->params.a_wnd,
6089 adap->params.b_wnd);
6090 }
dcf7b6f5 6091 t4_init_tp_params(adap);
636f9d37 6092 adap->flags |= FW_OK;
b8ff05a9
DM		 6093 return 0;
6094
6095 /*
636f9d37
VP		 6096 * Something bad happened. If a command timed out or failed with EIO
6097 * FW does not operate within its spec or something catastrophic
6098 * happened to HW/FW, stop issuing commands.
b8ff05a9 6099 */
636f9d37
VP		 6100bye:
6101 if (ret != -ETIMEDOUT && ret != -EIO)
6102 t4_fw_bye(adap, adap->mbox);
b8ff05a9
DM		 6103 return ret;
6104}
6105
204dc3c0
DM		 6106/* EEH callbacks */
6107
6108static pci_ers_result_t eeh_err_detected(struct pci_dev *pdev,
6109 pci_channel_state_t state)
6110{
6111 int i;
6112 struct adapter *adap = pci_get_drvdata(pdev);
6113
6114 if (!adap)
6115 goto out;
6116
6117 rtnl_lock();
6118 adap->flags &= ~FW_OK;
6119 notify_ulds(adap, CXGB4_STATE_START_RECOVERY);
9fe6cb58 6120 spin_lock(&adap->stats_lock);
204dc3c0
DM		 6121 for_each_port(adap, i) {
6122 struct net_device *dev = adap->port[i];
6123
6124 netif_device_detach(dev);
6125 netif_carrier_off(dev);
6126 }
9fe6cb58 6127 spin_unlock(&adap->stats_lock);
204dc3c0
DM		 6128 if (adap->flags & FULL_INIT_DONE)
6129 cxgb_down(adap);
6130 rtnl_unlock();
144be3d9
GS		 6131 if ((adap->flags & DEV_ENABLED)) {
6132 pci_disable_device(pdev);
6133 adap->flags &= ~DEV_ENABLED;
6134 }
204dc3c0
DM		 6135out: return state == pci_channel_io_perm_failure ?
6136 PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_NEED_RESET;
6137}
6138
6139static pci_ers_result_t eeh_slot_reset(struct pci_dev *pdev)
6140{
6141 int i, ret;
6142 struct fw_caps_config_cmd c;
6143 struct adapter *adap = pci_get_drvdata(pdev);
6144
6145 if (!adap) {
6146 pci_restore_state(pdev);
6147 pci_save_state(pdev);
6148 return PCI_ERS_RESULT_RECOVERED;
6149 }
6150
144be3d9
GS		 6151 if (!(adap->flags & DEV_ENABLED)) {
6152 if (pci_enable_device(pdev)) {
6153 dev_err(&pdev->dev, "Cannot reenable PCI "
6154 "device after reset\n");
6155 return PCI_ERS_RESULT_DISCONNECT;
6156 }
6157 adap->flags |= DEV_ENABLED;
204dc3c0
DM		 6158 }
6159
6160 pci_set_master(pdev);
6161 pci_restore_state(pdev);
6162 pci_save_state(pdev);
6163 pci_cleanup_aer_uncorrect_error_status(pdev);
6164
8203b509 6165 if (t4_wait_dev_ready(adap->regs) < 0)
204dc3c0 6166 return PCI_ERS_RESULT_DISCONNECT;
777c2300 6167 if (t4_fw_hello(adap, adap->fn, adap->fn, MASTER_MUST, NULL) < 0)
204dc3c0
DM		 6168 return PCI_ERS_RESULT_DISCONNECT;
6169 adap->flags |= FW_OK;
6170 if (adap_init1(adap, &c))
6171 return PCI_ERS_RESULT_DISCONNECT;
6172
6173 for_each_port(adap, i) {
6174 struct port_info *p = adap2pinfo(adap, i);
6175
060e0c75
DM		 6176 ret = t4_alloc_vi(adap, adap->fn, p->tx_chan, adap->fn, 0, 1,
6177 NULL, NULL);
204dc3c0
DM		 6178 if (ret < 0)
6179 return PCI_ERS_RESULT_DISCONNECT;
6180 p->viid = ret;
6181 p->xact_addr_filt = -1;
6182 }
6183
6184 t4_load_mtus(adap, adap->params.mtus, adap->params.a_wnd,
6185 adap->params.b_wnd);
1ae970e0 6186 setup_memwin(adap);
204dc3c0
DM		 6187 if (cxgb_up(adap))
6188 return PCI_ERS_RESULT_DISCONNECT;
6189 return PCI_ERS_RESULT_RECOVERED;
6190}
6191
6192static void eeh_resume(struct pci_dev *pdev)
6193{
6194 int i;
6195 struct adapter *adap = pci_get_drvdata(pdev);
6196
6197 if (!adap)
6198 return;
6199
6200 rtnl_lock();
6201 for_each_port(adap, i) {
6202 struct net_device *dev = adap->port[i];
6203
6204 if (netif_running(dev)) {
6205 link_start(dev);
6206 cxgb_set_rxmode(dev);
6207 }
6208 netif_device_attach(dev);
6209 }
6210 rtnl_unlock();
6211}
6212
3646f0e5 6213static const struct pci_error_handlers cxgb4_eeh = {
204dc3c0
DM		 6214 .error_detected = eeh_err_detected,
6215 .slot_reset = eeh_slot_reset,
6216 .resume = eeh_resume,
6217};
6218
57d8b764 6219static inline bool is_x_10g_port(const struct link_config *lc)
b8ff05a9 6220{
57d8b764
KS		 6221 return (lc->supported & FW_PORT_CAP_SPEED_10G) != 0 ||
6222 (lc->supported & FW_PORT_CAP_SPEED_40G) != 0;
b8ff05a9
DM		 6223}
6224
c887ad0e
HS		 6225static inline void init_rspq(struct adapter *adap, struct sge_rspq *q,
6226 unsigned int us, unsigned int cnt,
b8ff05a9
DM		 6227 unsigned int size, unsigned int iqe_size)
6228{
c887ad0e
HS		 6229 q->adap = adap;
6230 set_rspq_intr_params(q, us, cnt);
b8ff05a9
DM		 6231 q->iqe_len = iqe_size;
6232 q->size = size;
6233}
6234
6235/*
6236 * Perform default configuration of DMA queues depending on the number and type
6237 * of ports we found and the number of available CPUs. Most settings can be
6238 * modified by the admin prior to actual use.
6239 */
91744948 6240static void cfg_queues(struct adapter *adap)
b8ff05a9
DM		 6241{
6242 struct sge *s = &adap->sge;
688848b1
AB		 6243 int i, n10g = 0, qidx = 0;
6244#ifndef CONFIG_CHELSIO_T4_DCB
6245 int q10g = 0;
6246#endif
cf38be6d 6247 int ciq_size;
b8ff05a9
DM		 6248
6249 for_each_port(adap, i)
57d8b764 6250 n10g += is_x_10g_port(&adap2pinfo(adap, i)->link_cfg);
688848b1
AB		 6251#ifdef CONFIG_CHELSIO_T4_DCB
6252 /* For Data Center Bridging support we need to be able to support up
6253 * to 8 Traffic Priorities; each of which will be assigned to its
6254 * own TX Queue in order to prevent Head-Of-Line Blocking.
6255 */
6256 if (adap->params.nports * 8 > MAX_ETH_QSETS) {
6257 dev_err(adap->pdev_dev, "MAX_ETH_QSETS=%d < %d!\n",
6258 MAX_ETH_QSETS, adap->params.nports * 8);
6259 BUG_ON(1);
6260 }
b8ff05a9 6261
688848b1
AB		 6262 for_each_port(adap, i) {
6263 struct port_info *pi = adap2pinfo(adap, i);
6264
6265 pi->first_qset = qidx;
6266 pi->nqsets = 8;
6267 qidx += pi->nqsets;
6268 }
6269#else /* !CONFIG_CHELSIO_T4_DCB */
b8ff05a9
DM		 6270 /*
6271 * We default to 1 queue per non-10G port and up to # of cores queues
6272 * per 10G port.
6273 */
6274 if (n10g)
6275 q10g = (MAX_ETH_QSETS - (adap->params.nports - n10g)) / n10g;
5952dde7
YM		 6276 if (q10g > netif_get_num_default_rss_queues())
6277 q10g = netif_get_num_default_rss_queues();
b8ff05a9
DM		 6278
6279 for_each_port(adap, i) {
6280 struct port_info *pi = adap2pinfo(adap, i);
6281
6282 pi->first_qset = qidx;
57d8b764 6283 pi->nqsets = is_x_10g_port(&pi->link_cfg) ? q10g : 1;
b8ff05a9
DM		 6284 qidx += pi->nqsets;
6285 }
688848b1 6286#endif /* !CONFIG_CHELSIO_T4_DCB */
b8ff05a9
DM		 6287
6288 s->ethqsets = qidx;
6289 s->max_ethqsets = qidx; /* MSI-X may lower it later */
6290
6291 if (is_offload(adap)) {
6292 /*
6293 * For offload we use 1 queue/channel if all ports are up to 1G,
6294 * otherwise we divide all available queues amongst the channels
6295 * capped by the number of available cores.
6296 */
6297 if (n10g) {
6298 i = min_t(int, ARRAY_SIZE(s->ofldrxq),
6299 num_online_cpus());
6300 s->ofldqsets = roundup(i, adap->params.nports);
6301 } else
6302 s->ofldqsets = adap->params.nports;
6303 /* For RDMA one Rx queue per channel suffices */
6304 s->rdmaqs = adap->params.nports;
cf38be6d 6305 s->rdmaciqs = adap->params.nports;
b8ff05a9
DM		 6306 }
6307
6308 for (i = 0; i < ARRAY_SIZE(s->ethrxq); i++) {
6309 struct sge_eth_rxq *r = &s->ethrxq[i];
6310
c887ad0e 6311 init_rspq(adap, &r->rspq, 5, 10, 1024, 64);
b8ff05a9
DM		 6312 r->fl.size = 72;
6313 }
6314
6315 for (i = 0; i < ARRAY_SIZE(s->ethtxq); i++)
6316 s->ethtxq[i].q.size = 1024;
6317
6318 for (i = 0; i < ARRAY_SIZE(s->ctrlq); i++)
6319 s->ctrlq[i].q.size = 512;
6320
6321 for (i = 0; i < ARRAY_SIZE(s->ofldtxq); i++)
6322 s->ofldtxq[i].q.size = 1024;
6323
6324 for (i = 0; i < ARRAY_SIZE(s->ofldrxq); i++) {
6325 struct sge_ofld_rxq *r = &s->ofldrxq[i];
6326
c887ad0e 6327 init_rspq(adap, &r->rspq, 5, 1, 1024, 64);
b8ff05a9
DM		 6328 r->rspq.uld = CXGB4_ULD_ISCSI;
6329 r->fl.size = 72;
6330 }
6331
6332 for (i = 0; i < ARRAY_SIZE(s->rdmarxq); i++) {
6333 struct sge_ofld_rxq *r = &s->rdmarxq[i];
6334
c887ad0e 6335 init_rspq(adap, &r->rspq, 5, 1, 511, 64);
b8ff05a9
DM		 6336 r->rspq.uld = CXGB4_ULD_RDMA;
6337 r->fl.size = 72;
6338 }
6339
cf38be6d
HS		 6340 ciq_size = 64 + adap->vres.cq.size + adap->tids.nftids;
6341 if (ciq_size > SGE_MAX_IQ_SIZE) {
6342 CH_WARN(adap, "CIQ size too small for available IQs\n");
6343 ciq_size = SGE_MAX_IQ_SIZE;
6344 }
6345
6346 for (i = 0; i < ARRAY_SIZE(s->rdmaciq); i++) {
6347 struct sge_ofld_rxq *r = &s->rdmaciq[i];
6348
c887ad0e 6349 init_rspq(adap, &r->rspq, 5, 1, ciq_size, 64);
cf38be6d
HS		 6350 r->rspq.uld = CXGB4_ULD_RDMA;
6351 }
6352
c887ad0e
HS		 6353 init_rspq(adap, &s->fw_evtq, 0, 1, 1024, 64);
6354 init_rspq(adap, &s->intrq, 0, 1, 2 * MAX_INGQ, 64);
b8ff05a9
DM		 6355}
6356
6357/*
6358 * Reduce the number of Ethernet queues across all ports to at most n.
6359 * n provides at least one queue per port.
6360 */
91744948 6361static void reduce_ethqs(struct adapter *adap, int n)
b8ff05a9
DM		 6362{
6363 int i;
6364 struct port_info *pi;
6365
6366 while (n < adap->sge.ethqsets)
6367 for_each_port(adap, i) {
6368 pi = adap2pinfo(adap, i);
6369 if (pi->nqsets > 1) {
6370 pi->nqsets--;
6371 adap->sge.ethqsets--;
6372 if (adap->sge.ethqsets <= n)
6373 break;
6374 }
6375 }
6376
6377 n = 0;
6378 for_each_port(adap, i) {
6379 pi = adap2pinfo(adap, i);
6380 pi->first_qset = n;
6381 n += pi->nqsets;
6382 }
6383}
6384
6385/* 2 MSI-X vectors needed for the FW queue and non-data interrupts */
6386#define EXTRA_VECS 2
6387
91744948 6388static int enable_msix(struct adapter *adap)
b8ff05a9
DM		 6389{
6390 int ofld_need = 0;
c32ad224 6391 int i, want, need;
b8ff05a9
DM		 6392 struct sge *s = &adap->sge;
6393 unsigned int nchan = adap->params.nports;
6394 struct msix_entry entries[MAX_INGQ + 1];
6395
6396 for (i = 0; i < ARRAY_SIZE(entries); ++i)
6397 entries[i].entry = i;
6398
6399 want = s->max_ethqsets + EXTRA_VECS;
6400 if (is_offload(adap)) {
cf38be6d 6401 want += s->rdmaqs + s->rdmaciqs + s->ofldqsets;
b8ff05a9 6402 /* need nchan for each possible ULD */
cf38be6d 6403 ofld_need = 3 * nchan;
b8ff05a9 6404 }
688848b1
AB		 6405#ifdef CONFIG_CHELSIO_T4_DCB
6406 /* For Data Center Bridging we need 8 Ethernet TX Priority Queues for
6407 * each port.
6408 */
6409 need = 8 * adap->params.nports + EXTRA_VECS + ofld_need;
6410#else
b8ff05a9 6411 need = adap->params.nports + EXTRA_VECS + ofld_need;
688848b1 6412#endif
c32ad224
AG		 6413 want = pci_enable_msix_range(adap->pdev, entries, need, want);
6414 if (want < 0)
6415 return want;
b8ff05a9 6416
c32ad224
AG		 6417 /*
6418 * Distribute available vectors to the various queue groups.
6419 * Every group gets its minimum requirement and NIC gets top
6420 * priority for leftovers.
6421 */
6422 i = want - EXTRA_VECS - ofld_need;
6423 if (i < s->max_ethqsets) {
6424 s->max_ethqsets = i;
6425 if (i < s->ethqsets)
6426 reduce_ethqs(adap, i);
6427 }
6428 if (is_offload(adap)) {
6429 i = want - EXTRA_VECS - s->max_ethqsets;
6430 i -= ofld_need - nchan;
6431 s->ofldqsets = (i / nchan) * nchan; /* round down */
6432 }
6433 for (i = 0; i < want; ++i)
6434 adap->msix_info[i].vec = entries[i].vector;
6435
6436 return 0;
b8ff05a9
DM		 6437}
6438
6439#undef EXTRA_VECS
6440
91744948 6441static int init_rss(struct adapter *adap)
671b0060
DM		 6442{
6443 unsigned int i, j;
6444
6445 for_each_port(adap, i) {
6446 struct port_info *pi = adap2pinfo(adap, i);
6447
6448 pi->rss = kcalloc(pi->rss_size, sizeof(u16), GFP_KERNEL);
6449 if (!pi->rss)
6450 return -ENOMEM;
6451 for (j = 0; j < pi->rss_size; j++)
278bc429 6452 pi->rss[j] = ethtool_rxfh_indir_default(j, pi->nqsets);
671b0060
DM		 6453 }
6454 return 0;
6455}
6456
91744948 6457static void print_port_info(const struct net_device *dev)
b8ff05a9 6458{
b8ff05a9 6459 char buf[80];
118969ed 6460 char *bufp = buf;
f1a051b9 6461 const char *spd = "";
118969ed
DM		 6462 const struct port_info *pi = netdev_priv(dev);
6463 const struct adapter *adap = pi->adapter;
f1a051b9
DM		 6464
6465 if (adap->params.pci.speed == PCI_EXP_LNKSTA_CLS_2_5GB)
6466 spd = " 2.5 GT/s";
6467 else if (adap->params.pci.speed == PCI_EXP_LNKSTA_CLS_5_0GB)
6468 spd = " 5 GT/s";
d2e752db
RD		 6469 else if (adap->params.pci.speed == PCI_EXP_LNKSTA_CLS_8_0GB)
6470 spd = " 8 GT/s";
b8ff05a9 6471
118969ed
DM		 6472 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_100M)
6473 bufp += sprintf(bufp, "100/");
6474 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_1G)
6475 bufp += sprintf(bufp, "1000/");
6476 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_10G)
6477 bufp += sprintf(bufp, "10G/");
72aca4bf
KS		 6478 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_40G)
6479 bufp += sprintf(bufp, "40G/");
118969ed
DM		 6480 if (bufp != buf)
6481 --bufp;
72aca4bf 6482 sprintf(bufp, "BASE-%s", t4_get_port_type_description(pi->port_type));
118969ed
DM		 6483
6484 netdev_info(dev, "Chelsio %s rev %d %s %sNIC PCIe x%d%s%s\n",
0a57a536 6485 adap->params.vpd.id,
d14807dd 6486 CHELSIO_CHIP_RELEASE(adap->params.chip), buf,
118969ed
DM		 6487 is_offload(adap) ? "R" : "", adap->params.pci.width, spd,
6488 (adap->flags & USING_MSIX) ? " MSI-X" :
6489 (adap->flags & USING_MSI) ? " MSI" : "");
a94cd705
KS		 6490 netdev_info(dev, "S/N: %s, P/N: %s\n",
6491 adap->params.vpd.sn, adap->params.vpd.pn);
b8ff05a9
DM		 6492}
6493
91744948 6494static void enable_pcie_relaxed_ordering(struct pci_dev *dev)
ef306b50 6495{
e5c8ae5f 6496 pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_RELAX_EN);
ef306b50
DM		 6497}
6498
06546391
DM		 6499/*
6500 * Free the following resources:
6501 * - memory used for tables
6502 * - MSI/MSI-X
6503 * - net devices
6504 * - resources FW is holding for us
6505 */
6506static void free_some_resources(struct adapter *adapter)
6507{
6508 unsigned int i;
6509
6510 t4_free_mem(adapter->l2t);
6511 t4_free_mem(adapter->tids.tid_tab);
6512 disable_msi(adapter);
6513
6514 for_each_port(adapter, i)
671b0060
DM		 6515 if (adapter->port[i]) {
6516 kfree(adap2pinfo(adapter, i)->rss);
06546391 6517 free_netdev(adapter->port[i]);
671b0060 6518 }
06546391 6519 if (adapter->flags & FW_OK)
060e0c75 6520 t4_fw_bye(adapter, adapter->fn);
06546391
DM		 6521}
6522
2ed28baa 6523#define TSO_FLAGS (NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_TSO_ECN)
35d35682 6524#define VLAN_FEAT (NETIF_F_SG | NETIF_F_IP_CSUM | TSO_FLAGS | \
b8ff05a9 6525 NETIF_F_IPV6_CSUM | NETIF_F_HIGHDMA)
22adfe0a 6526#define SEGMENT_SIZE 128
b8ff05a9 6527
1dd06ae8 6528static int init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
b8ff05a9 6529{
22adfe0a 6530 int func, i, err, s_qpp, qpp, num_seg;
b8ff05a9 6531 struct port_info *pi;
c8f44aff 6532 bool highdma = false;
b8ff05a9 6533 struct adapter *adapter = NULL;
d6ce2628 6534 void __iomem *regs;
b8ff05a9
DM		 6535
6536 printk_once(KERN_INFO "%s - version %s\n", DRV_DESC, DRV_VERSION);
6537
6538 err = pci_request_regions(pdev, KBUILD_MODNAME);
6539 if (err) {
6540 /* Just info, some other driver may have claimed the device. */
6541 dev_info(&pdev->dev, "cannot obtain PCI resources\n");
6542 return err;
6543 }
6544
b8ff05a9
DM		 6545 err = pci_enable_device(pdev);
6546 if (err) {
6547 dev_err(&pdev->dev, "cannot enable PCI device\n");
6548 goto out_release_regions;
6549 }
6550
d6ce2628
HS		 6551 regs = pci_ioremap_bar(pdev, 0);
6552 if (!regs) {
6553 dev_err(&pdev->dev, "cannot map device registers\n");
6554 err = -ENOMEM;
6555 goto out_disable_device;
6556 }
6557
8203b509
HS		 6558 err = t4_wait_dev_ready(regs);
6559 if (err < 0)
6560 goto out_unmap_bar0;
6561
d6ce2628
HS		 6562 /* We control everything through one PF */
6563 func = SOURCEPF_GET(readl(regs + PL_WHOAMI));
6564 if (func != ent->driver_data) {
6565 iounmap(regs);
6566 pci_disable_device(pdev);
6567 pci_save_state(pdev); /* to restore SR-IOV later */
6568 goto sriov;
6569 }
6570
b8ff05a9 6571 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
c8f44aff 6572 highdma = true;
b8ff05a9
DM		 6573 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
6574 if (err) {
6575 dev_err(&pdev->dev, "unable to obtain 64-bit DMA for "
6576 "coherent allocations\n");
d6ce2628 6577 goto out_unmap_bar0;
b8ff05a9
DM		 6578 }
6579 } else {
6580 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
6581 if (err) {
6582 dev_err(&pdev->dev, "no usable DMA configuration\n");
d6ce2628 6583 goto out_unmap_bar0;
b8ff05a9
DM		 6584 }
6585 }
6586
6587 pci_enable_pcie_error_reporting(pdev);
ef306b50 6588 enable_pcie_relaxed_ordering(pdev);
b8ff05a9
DM		 6589 pci_set_master(pdev);
6590 pci_save_state(pdev);
6591
6592 adapter = kzalloc(sizeof(*adapter), GFP_KERNEL);
6593 if (!adapter) {
6594 err = -ENOMEM;
d6ce2628 6595 goto out_unmap_bar0;
b8ff05a9
DM		 6596 }
6597
29aaee65
AB		 6598 adapter->workq = create_singlethread_workqueue("cxgb4");
6599 if (!adapter->workq) {
6600 err = -ENOMEM;
6601 goto out_free_adapter;
6602 }
6603
144be3d9
GS		 6604 /* PCI device has been enabled */
6605 adapter->flags |= DEV_ENABLED;
6606
d6ce2628 6607 adapter->regs = regs;
b8ff05a9
DM		 6608 adapter->pdev = pdev;
6609 adapter->pdev_dev = &pdev->dev;
3069ee9b 6610 adapter->mbox = func;
060e0c75 6611 adapter->fn = func;
b8ff05a9
DM		 6612 adapter->msg_enable = dflt_msg_enable;
6613 memset(adapter->chan_map, 0xff, sizeof(adapter->chan_map));
6614
6615 spin_lock_init(&adapter->stats_lock);
6616 spin_lock_init(&adapter->tid_release_lock);
e327c225 6617 spin_lock_init(&adapter->win0_lock);
b8ff05a9
DM		 6618
6619 INIT_WORK(&adapter->tid_release_task, process_tid_release_list);
881806bc
VP		 6620 INIT_WORK(&adapter->db_full_task, process_db_full);
6621 INIT_WORK(&adapter->db_drop_task, process_db_drop);
b8ff05a9
DM		 6622
6623 err = t4_prep_adapter(adapter);
6624 if (err)
d6ce2628
HS		 6625 goto out_free_adapter;
6626
22adfe0a 6627
d14807dd 6628 if (!is_t4(adapter->params.chip)) {
22adfe0a
SR		 6629 s_qpp = QUEUESPERPAGEPF1 * adapter->fn;
6630 qpp = 1 << QUEUESPERPAGEPF0_GET(t4_read_reg(adapter,
6631 SGE_EGRESS_QUEUES_PER_PAGE_PF) >> s_qpp);
6632 num_seg = PAGE_SIZE / SEGMENT_SIZE;
6633
6634 /* Each segment size is 128B. Write coalescing is enabled only
6635 * when SGE_EGRESS_QUEUES_PER_PAGE_PF reg value for the
6636 * queue is less no of segments that can be accommodated in
6637 * a page size.
6638 */
6639 if (qpp > num_seg) {
6640 dev_err(&pdev->dev,
6641 "Incorrect number of egress queues per page\n");
6642 err = -EINVAL;
d6ce2628 6643 goto out_free_adapter;
22adfe0a
SR		 6644 }
6645 adapter->bar2 = ioremap_wc(pci_resource_start(pdev, 2),
6646 pci_resource_len(pdev, 2));
6647 if (!adapter->bar2) {
6648 dev_err(&pdev->dev, "cannot map device bar2 region\n");
6649 err = -ENOMEM;
d6ce2628 6650 goto out_free_adapter;
22adfe0a
SR		 6651 }
6652 }
6653
636f9d37 6654 setup_memwin(adapter);
b8ff05a9 6655 err = adap_init0(adapter);
636f9d37 6656 setup_memwin_rdma(adapter);
b8ff05a9
DM		 6657 if (err)
6658 goto out_unmap_bar;
6659
6660 for_each_port(adapter, i) {
6661 struct net_device *netdev;
6662
6663 netdev = alloc_etherdev_mq(sizeof(struct port_info),
6664 MAX_ETH_QSETS);
6665 if (!netdev) {
6666 err = -ENOMEM;
6667 goto out_free_dev;
6668 }
6669
6670 SET_NETDEV_DEV(netdev, &pdev->dev);
6671
6672 adapter->port[i] = netdev;
6673 pi = netdev_priv(netdev);
6674 pi->adapter = adapter;
6675 pi->xact_addr_filt = -1;
b8ff05a9 6676 pi->port_id = i;
b8ff05a9
DM		 6677 netdev->irq = pdev->irq;
6678
2ed28baa
MM		 6679 netdev->hw_features = NETIF_F_SG | TSO_FLAGS |
6680 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
6681 NETIF_F_RXCSUM | NETIF_F_RXHASH |
f646968f 6682 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
c8f44aff
MM		 6683 if (highdma)
6684 netdev->hw_features |= NETIF_F_HIGHDMA;
6685 netdev->features |= netdev->hw_features;
b8ff05a9
DM		 6686 netdev->vlan_features = netdev->features & VLAN_FEAT;
6687
01789349
JP		 6688 netdev->priv_flags |= IFF_UNICAST_FLT;
6689
b8ff05a9 6690 netdev->netdev_ops = &cxgb4_netdev_ops;
688848b1
AB		 6691#ifdef CONFIG_CHELSIO_T4_DCB
6692 netdev->dcbnl_ops = &cxgb4_dcb_ops;
6693 cxgb4_dcb_state_init(netdev);
6694#endif
7ad24ea4 6695 netdev->ethtool_ops = &cxgb_ethtool_ops;
b8ff05a9
DM		 6696 }
6697
6698 pci_set_drvdata(pdev, adapter);
6699
6700 if (adapter->flags & FW_OK) {
060e0c75 6701 err = t4_port_init(adapter, func, func, 0);
b8ff05a9
DM		 6702 if (err)
6703 goto out_free_dev;
6704 }
6705
6706 /*
6707 * Configure queues and allocate tables now, they can be needed as
6708 * soon as the first register_netdev completes.
6709 */
6710 cfg_queues(adapter);
6711
6712 adapter->l2t = t4_init_l2t();
6713 if (!adapter->l2t) {
6714 /* We tolerate a lack of L2T, giving up some functionality */
6715 dev_warn(&pdev->dev, "could not allocate L2T, continuing\n");
6716 adapter->params.offload = 0;
6717 }
6718
6719 if (is_offload(adapter) && tid_init(&adapter->tids) < 0) {
6720 dev_warn(&pdev->dev, "could not allocate TID table, "
6721 "continuing\n");
6722 adapter->params.offload = 0;
6723 }
6724
f7cabcdd
DM		 6725 /* See what interrupts we'll be using */
6726 if (msi > 1 && enable_msix(adapter) == 0)
6727 adapter->flags |= USING_MSIX;
6728 else if (msi > 0 && pci_enable_msi(pdev) == 0)
6729 adapter->flags |= USING_MSI;
6730
671b0060
DM		 6731 err = init_rss(adapter);
6732 if (err)
6733 goto out_free_dev;
6734
b8ff05a9
DM		 6735 /*
6736 * The card is now ready to go. If any errors occur during device
6737 * registration we do not fail the whole card but rather proceed only
6738 * with the ports we manage to register successfully. However we must
6739 * register at least one net device.
6740 */
6741 for_each_port(adapter, i) {
a57cabe0
DM		 6742 pi = adap2pinfo(adapter, i);
6743 netif_set_real_num_tx_queues(adapter->port[i], pi->nqsets);
6744 netif_set_real_num_rx_queues(adapter->port[i], pi->nqsets);
6745
b8ff05a9
DM		 6746 err = register_netdev(adapter->port[i]);
6747 if (err)
b1a3c2b6 6748 break;
b1a3c2b6
DM		 6749 adapter->chan_map[pi->tx_chan] = i;
6750 print_port_info(adapter->port[i]);
b8ff05a9 6751 }
b1a3c2b6 6752 if (i == 0) {
b8ff05a9
DM		 6753 dev_err(&pdev->dev, "could not register any net devices\n");
6754 goto out_free_dev;
6755 }
b1a3c2b6
DM		 6756 if (err) {
6757 dev_warn(&pdev->dev, "only %d net devices registered\n", i);
6758 err = 0;
6403eab1 6759 }
b8ff05a9
DM		 6760
6761 if (cxgb4_debugfs_root) {
6762 adapter->debugfs_root = debugfs_create_dir(pci_name(pdev),
6763 cxgb4_debugfs_root);
6764 setup_debugfs(adapter);
6765 }
6766
6482aa7c
DLR		 6767 /* PCIe EEH recovery on powerpc platforms needs fundamental reset */
6768 pdev->needs_freset = 1;
6769
b8ff05a9
DM		 6770 if (is_offload(adapter))
6771 attach_ulds(adapter);
6772
8e1e6059 6773sriov:
b8ff05a9 6774#ifdef CONFIG_PCI_IOV
7d6727cf 6775 if (func < ARRAY_SIZE(num_vf) && num_vf[func] > 0)
b8ff05a9
DM		 6776 if (pci_enable_sriov(pdev, num_vf[func]) == 0)
6777 dev_info(&pdev->dev,
6778 "instantiated %u virtual functions\n",
6779 num_vf[func]);
6780#endif
6781 return 0;
6782
6783 out_free_dev:
06546391 6784 free_some_resources(adapter);
b8ff05a9 6785 out_unmap_bar:
d14807dd 6786 if (!is_t4(adapter->params.chip))
22adfe0a 6787 iounmap(adapter->bar2);
b8ff05a9 6788 out_free_adapter:
29aaee65
AB		 6789 if (adapter->workq)
6790 destroy_workqueue(adapter->workq);
6791
b8ff05a9 6792 kfree(adapter);
d6ce2628
HS		 6793 out_unmap_bar0:
6794 iounmap(regs);
b8ff05a9
DM		 6795 out_disable_device:
6796 pci_disable_pcie_error_reporting(pdev);
6797 pci_disable_device(pdev);
6798 out_release_regions:
6799 pci_release_regions(pdev);
b8ff05a9
DM		 6800 return err;
6801}
6802
91744948 6803static void remove_one(struct pci_dev *pdev)
b8ff05a9
DM		 6804{
6805 struct adapter *adapter = pci_get_drvdata(pdev);
6806
636f9d37 6807#ifdef CONFIG_PCI_IOV
b8ff05a9
DM		 6808 pci_disable_sriov(pdev);
6809
636f9d37
VP		 6810#endif
6811
b8ff05a9
DM		 6812 if (adapter) {
6813 int i;
6814
29aaee65
AB		 6815 /* Tear down per-adapter Work Queue first since it can contain
6816 * references to our adapter data structure.
6817 */
6818 destroy_workqueue(adapter->workq);
6819
b8ff05a9
DM		 6820 if (is_offload(adapter))
6821 detach_ulds(adapter);
6822
6823 for_each_port(adapter, i)
8f3a7676 6824 if (adapter->port[i]->reg_state == NETREG_REGISTERED)
b8ff05a9
DM		 6825 unregister_netdev(adapter->port[i]);
6826
9f16dc2e 6827 debugfs_remove_recursive(adapter->debugfs_root);
b8ff05a9 6828
f2b7e78d
VP		 6829 /* If we allocated filters, free up state associated with any
6830 * valid filters ...
6831 */
6832 if (adapter->tids.ftid_tab) {
6833 struct filter_entry *f = &adapter->tids.ftid_tab[0];
dca4faeb
VP		 6834 for (i = 0; i < (adapter->tids.nftids +
6835 adapter->tids.nsftids); i++, f++)
f2b7e78d
VP		 6836 if (f->valid)
6837 clear_filter(adapter, f);
6838 }
6839
aaefae9b
DM		 6840 if (adapter->flags & FULL_INIT_DONE)
6841 cxgb_down(adapter);
b8ff05a9 6842
06546391 6843 free_some_resources(adapter);
b8ff05a9 6844 iounmap(adapter->regs);
d14807dd 6845 if (!is_t4(adapter->params.chip))
22adfe0a 6846 iounmap(adapter->bar2);
b8ff05a9 6847 pci_disable_pcie_error_reporting(pdev);
144be3d9
GS		 6848 if ((adapter->flags & DEV_ENABLED)) {
6849 pci_disable_device(pdev);
6850 adapter->flags &= ~DEV_ENABLED;
6851 }
b8ff05a9 6852 pci_release_regions(pdev);
ee9a33b2 6853 synchronize_rcu();
8b662fe7 6854 kfree(adapter);
a069ec91 6855 } else
b8ff05a9
DM		 6856 pci_release_regions(pdev);
6857}
6858
6859static struct pci_driver cxgb4_driver = {
6860 .name = KBUILD_MODNAME,
6861 .id_table = cxgb4_pci_tbl,
6862 .probe = init_one,
91744948 6863 .remove = remove_one,
687d705c 6864 .shutdown = remove_one,
204dc3c0 6865 .err_handler = &cxgb4_eeh,
b8ff05a9
DM		 6866};
6867
6868static int __init cxgb4_init_module(void)
6869{
6870 int ret;
6871
6872 /* Debugfs support is optional, just warn if this fails */
6873 cxgb4_debugfs_root = debugfs_create_dir(KBUILD_MODNAME, NULL);
6874 if (!cxgb4_debugfs_root)
428ac43f 6875 pr_warn("could not create debugfs entry, continuing\n");
b8ff05a9
DM		 6876
6877 ret = pci_register_driver(&cxgb4_driver);
29aaee65 6878 if (ret < 0)
b8ff05a9 6879 debugfs_remove(cxgb4_debugfs_root);
01bcca68 6880
1bb60376 6881#if IS_ENABLED(CONFIG_IPV6)
01bcca68 6882 register_inet6addr_notifier(&cxgb4_inet6addr_notifier);
1bb60376 6883#endif
01bcca68 6884
b8ff05a9
DM		 6885 return ret;
6886}
6887
6888static void __exit cxgb4_cleanup_module(void)
6889{
1bb60376 6890#if IS_ENABLED(CONFIG_IPV6)
01bcca68 6891 unregister_inet6addr_notifier(&cxgb4_inet6addr_notifier);
1bb60376 6892#endif
b8ff05a9
DM		 6893 pci_unregister_driver(&cxgb4_driver);
6894 debugfs_remove(cxgb4_debugfs_root); /* NULL ok */
6895}
6896
6897module_init(cxgb4_init_module);
6898module_exit(cxgb4_cleanup_module);
Linux kernel - Deliverables
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