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cxgb4: Replaced the backdoor mechanism to access the HW memory with PCIe Window method
[deliverable/linux.git] / drivers / net / ethernet / chelsio / cxgb4 / cxgb4_main.c
CommitLineData
b8ff05a9
DM		 1/*
2 * This file is part of the Chelsio T4 Ethernet driver for Linux.
3 *
ce100b8b 4 * Copyright (c) 2003-2014 Chelsio Communications, Inc. All rights reserved.
b8ff05a9
DM		 5 *
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
11 *
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
14 * conditions are met:
15 *
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
18 * disclaimer.
19 *
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
24 *
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
32 * SOFTWARE.
33 */
34
35#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
36
37#include <linux/bitmap.h>
38#include <linux/crc32.h>
39#include <linux/ctype.h>
40#include <linux/debugfs.h>
41#include <linux/err.h>
42#include <linux/etherdevice.h>
43#include <linux/firmware.h>
01789349 44#include <linux/if.h>
b8ff05a9
DM		 45#include <linux/if_vlan.h>
46#include <linux/init.h>
47#include <linux/log2.h>
48#include <linux/mdio.h>
49#include <linux/module.h>
50#include <linux/moduleparam.h>
51#include <linux/mutex.h>
52#include <linux/netdevice.h>
53#include <linux/pci.h>
54#include <linux/aer.h>
55#include <linux/rtnetlink.h>
56#include <linux/sched.h>
57#include <linux/seq_file.h>
58#include <linux/sockios.h>
59#include <linux/vmalloc.h>
60#include <linux/workqueue.h>
61#include <net/neighbour.h>
62#include <net/netevent.h>
01bcca68 63#include <net/addrconf.h>
b8ff05a9
DM		 64#include <asm/uaccess.h>
65
66#include "cxgb4.h"
67#include "t4_regs.h"
68#include "t4_msg.h"
69#include "t4fw_api.h"
688848b1 70#include "cxgb4_dcb.h"
b8ff05a9
DM		 71#include "l2t.h"
72
01bcca68
VP		 73#include <../drivers/net/bonding/bonding.h>
74
75#ifdef DRV_VERSION
76#undef DRV_VERSION
77#endif
3a7f8554
SR		 78#define DRV_VERSION "2.0.0-ko"
79#define DRV_DESC "Chelsio T4/T5 Network Driver"
b8ff05a9
DM		 80
81/*
82 * Max interrupt hold-off timer value in us. Queues fall back to this value
83 * under extreme memory pressure so it's largish to give the system time to
84 * recover.
85 */
86#define MAX_SGE_TIMERVAL 200U
87
7ee9ff94 88enum {
13ee15d3
VP		 89 /*
90 * Physical Function provisioning constants.
91 */
92 PFRES_NVI = 4, /* # of Virtual Interfaces */
93 PFRES_NETHCTRL = 128, /* # of EQs used for ETH or CTRL Qs */
94 PFRES_NIQFLINT = 128, /* # of ingress Qs/w Free List(s)/intr
95 */
96 PFRES_NEQ = 256, /* # of egress queues */
97 PFRES_NIQ = 0, /* # of ingress queues */
98 PFRES_TC = 0, /* PCI-E traffic class */
99 PFRES_NEXACTF = 128, /* # of exact MPS filters */
100
101 PFRES_R_CAPS = FW_CMD_CAP_PF,
102 PFRES_WX_CAPS = FW_CMD_CAP_PF,
103
104#ifdef CONFIG_PCI_IOV
105 /*
106 * Virtual Function provisioning constants. We need two extra Ingress
107 * Queues with Interrupt capability to serve as the VF's Firmware
108 * Event Queue and Forwarded Interrupt Queue (when using MSI mode) --
109 * neither will have Free Lists associated with them). For each
110 * Ethernet/Control Egress Queue and for each Free List, we need an
111 * Egress Context.
112 */
7ee9ff94
CL		 113 VFRES_NPORTS = 1, /* # of "ports" per VF */
114 VFRES_NQSETS = 2, /* # of "Queue Sets" per VF */
115
116 VFRES_NVI = VFRES_NPORTS, /* # of Virtual Interfaces */
117 VFRES_NETHCTRL = VFRES_NQSETS, /* # of EQs used for ETH or CTRL Qs */
118 VFRES_NIQFLINT = VFRES_NQSETS+2,/* # of ingress Qs/w Free List(s)/intr */
7ee9ff94 119 VFRES_NEQ = VFRES_NQSETS*2, /* # of egress queues */
13ee15d3 120 VFRES_NIQ = 0, /* # of non-fl/int ingress queues */
7ee9ff94
CL		 121 VFRES_TC = 0, /* PCI-E traffic class */
122 VFRES_NEXACTF = 16, /* # of exact MPS filters */
123
124 VFRES_R_CAPS = FW_CMD_CAP_DMAQ|FW_CMD_CAP_VF|FW_CMD_CAP_PORT,
125 VFRES_WX_CAPS = FW_CMD_CAP_DMAQ|FW_CMD_CAP_VF,
13ee15d3 126#endif
7ee9ff94
CL		 127};
128
129/*
130 * Provide a Port Access Rights Mask for the specified PF/VF. This is very
131 * static and likely not to be useful in the long run. We really need to
132 * implement some form of persistent configuration which the firmware
133 * controls.
134 */
135static unsigned int pfvfres_pmask(struct adapter *adapter,
136 unsigned int pf, unsigned int vf)
137{
138 unsigned int portn, portvec;
139
140 /*
141 * Give PF's access to all of the ports.
142 */
143 if (vf == 0)
144 return FW_PFVF_CMD_PMASK_MASK;
145
146 /*
147 * For VFs, we'll assign them access to the ports based purely on the
148 * PF. We assign active ports in order, wrapping around if there are
149 * fewer active ports than PFs: e.g. active port[pf % nports].
150 * Unfortunately the adapter's port_info structs haven't been
151 * initialized yet so we have to compute this.
152 */
153 if (adapter->params.nports == 0)
154 return 0;
155
156 portn = pf % adapter->params.nports;
157 portvec = adapter->params.portvec;
158 for (;;) {
159 /*
160 * Isolate the lowest set bit in the port vector. If we're at
161 * the port number that we want, return that as the pmask.
162 * otherwise mask that bit out of the port vector and
163 * decrement our port number ...
164 */
165 unsigned int pmask = portvec ^ (portvec & (portvec-1));
166 if (portn == 0)
167 return pmask;
168 portn--;
169 portvec &= ~pmask;
170 }
171 /*NOTREACHED*/
172}
7ee9ff94 173
b8ff05a9
DM		 174enum {
175 MAX_TXQ_ENTRIES = 16384,
176 MAX_CTRL_TXQ_ENTRIES = 1024,
177 MAX_RSPQ_ENTRIES = 16384,
178 MAX_RX_BUFFERS = 16384,
179 MIN_TXQ_ENTRIES = 32,
180 MIN_CTRL_TXQ_ENTRIES = 32,
181 MIN_RSPQ_ENTRIES = 128,
182 MIN_FL_ENTRIES = 16
183};
184
f2b7e78d
VP		 185/* Host shadow copy of ingress filter entry. This is in host native format
186 * and doesn't match the ordering or bit order, etc. of the hardware of the
187 * firmware command. The use of bit-field structure elements is purely to
188 * remind ourselves of the field size limitations and save memory in the case
189 * where the filter table is large.
190 */
191struct filter_entry {
192 /* Administrative fields for filter.
193 */
194 u32 valid:1; /* filter allocated and valid */
195 u32 locked:1; /* filter is administratively locked */
196
197 u32 pending:1; /* filter action is pending firmware reply */
198 u32 smtidx:8; /* Source MAC Table index for smac */
199 struct l2t_entry *l2t; /* Layer Two Table entry for dmac */
200
201 /* The filter itself. Most of this is a straight copy of information
202 * provided by the extended ioctl(). Some fields are translated to
203 * internal forms -- for instance the Ingress Queue ID passed in from
204 * the ioctl() is translated into the Absolute Ingress Queue ID.
205 */
206 struct ch_filter_specification fs;
207};
208
b8ff05a9
DM		 209#define DFLT_MSG_ENABLE (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK | \
210 NETIF_MSG_TIMER | NETIF_MSG_IFDOWN | NETIF_MSG_IFUP |\
211 NETIF_MSG_RX_ERR | NETIF_MSG_TX_ERR)
212
060e0c75 213#define CH_DEVICE(devid, data) { PCI_VDEVICE(CHELSIO, devid), (data) }
b8ff05a9
DM		 214
215static DEFINE_PCI_DEVICE_TABLE(cxgb4_pci_tbl) = {
060e0c75 216 CH_DEVICE(0xa000, 0), /* PE10K */
ccea790e
DM		 217 CH_DEVICE(0x4001, -1),
218 CH_DEVICE(0x4002, -1),
219 CH_DEVICE(0x4003, -1),
220 CH_DEVICE(0x4004, -1),
221 CH_DEVICE(0x4005, -1),
222 CH_DEVICE(0x4006, -1),
223 CH_DEVICE(0x4007, -1),
224 CH_DEVICE(0x4008, -1),
225 CH_DEVICE(0x4009, -1),
226 CH_DEVICE(0x400a, -1),
227 CH_DEVICE(0x4401, 4),
228 CH_DEVICE(0x4402, 4),
229 CH_DEVICE(0x4403, 4),
230 CH_DEVICE(0x4404, 4),
231 CH_DEVICE(0x4405, 4),
232 CH_DEVICE(0x4406, 4),
233 CH_DEVICE(0x4407, 4),
234 CH_DEVICE(0x4408, 4),
235 CH_DEVICE(0x4409, 4),
236 CH_DEVICE(0x440a, 4),
f637d577
VP		 237 CH_DEVICE(0x440d, 4),
238 CH_DEVICE(0x440e, 4),
9ef603a0
VP		 239 CH_DEVICE(0x5001, 4),
240 CH_DEVICE(0x5002, 4),
241 CH_DEVICE(0x5003, 4),
242 CH_DEVICE(0x5004, 4),
243 CH_DEVICE(0x5005, 4),
244 CH_DEVICE(0x5006, 4),
245 CH_DEVICE(0x5007, 4),
246 CH_DEVICE(0x5008, 4),
247 CH_DEVICE(0x5009, 4),
248 CH_DEVICE(0x500A, 4),
249 CH_DEVICE(0x500B, 4),
250 CH_DEVICE(0x500C, 4),
251 CH_DEVICE(0x500D, 4),
252 CH_DEVICE(0x500E, 4),
253 CH_DEVICE(0x500F, 4),
254 CH_DEVICE(0x5010, 4),
255 CH_DEVICE(0x5011, 4),
256 CH_DEVICE(0x5012, 4),
257 CH_DEVICE(0x5013, 4),
f0a8e6de
HS		 258 CH_DEVICE(0x5014, 4),
259 CH_DEVICE(0x5015, 4),
0183aa62
HS		 260 CH_DEVICE(0x5080, 4),
261 CH_DEVICE(0x5081, 4),
262 CH_DEVICE(0x5082, 4),
263 CH_DEVICE(0x5083, 4),
264 CH_DEVICE(0x5084, 4),
265 CH_DEVICE(0x5085, 4),
9ef603a0
VP		 266 CH_DEVICE(0x5401, 4),
267 CH_DEVICE(0x5402, 4),
268 CH_DEVICE(0x5403, 4),
269 CH_DEVICE(0x5404, 4),
270 CH_DEVICE(0x5405, 4),
271 CH_DEVICE(0x5406, 4),
272 CH_DEVICE(0x5407, 4),
273 CH_DEVICE(0x5408, 4),
274 CH_DEVICE(0x5409, 4),
275 CH_DEVICE(0x540A, 4),
276 CH_DEVICE(0x540B, 4),
277 CH_DEVICE(0x540C, 4),
278 CH_DEVICE(0x540D, 4),
279 CH_DEVICE(0x540E, 4),
280 CH_DEVICE(0x540F, 4),
281 CH_DEVICE(0x5410, 4),
282 CH_DEVICE(0x5411, 4),
283 CH_DEVICE(0x5412, 4),
284 CH_DEVICE(0x5413, 4),
f0a8e6de
HS		 285 CH_DEVICE(0x5414, 4),
286 CH_DEVICE(0x5415, 4),
0183aa62
HS		 287 CH_DEVICE(0x5480, 4),
288 CH_DEVICE(0x5481, 4),
289 CH_DEVICE(0x5482, 4),
290 CH_DEVICE(0x5483, 4),
291 CH_DEVICE(0x5484, 4),
292 CH_DEVICE(0x5485, 4),
b8ff05a9
DM		 293 { 0, }
294};
295
16e47624 296#define FW4_FNAME "cxgb4/t4fw.bin"
0a57a536 297#define FW5_FNAME "cxgb4/t5fw.bin"
16e47624 298#define FW4_CFNAME "cxgb4/t4-config.txt"
0a57a536 299#define FW5_CFNAME "cxgb4/t5-config.txt"
b8ff05a9
DM		 300
301MODULE_DESCRIPTION(DRV_DESC);
302MODULE_AUTHOR("Chelsio Communications");
303MODULE_LICENSE("Dual BSD/GPL");
304MODULE_VERSION(DRV_VERSION);
305MODULE_DEVICE_TABLE(pci, cxgb4_pci_tbl);
16e47624 306MODULE_FIRMWARE(FW4_FNAME);
0a57a536 307MODULE_FIRMWARE(FW5_FNAME);
b8ff05a9 308
636f9d37
VP		 309/*
310 * Normally we're willing to become the firmware's Master PF but will be happy
311 * if another PF has already become the Master and initialized the adapter.
312 * Setting "force_init" will cause this driver to forcibly establish itself as
313 * the Master PF and initialize the adapter.
314 */
315static uint force_init;
316
317module_param(force_init, uint, 0644);
318MODULE_PARM_DESC(force_init, "Forcibly become Master PF and initialize adapter");
319
13ee15d3
VP		 320/*
321 * Normally if the firmware we connect to has Configuration File support, we
322 * use that and only fall back to the old Driver-based initialization if the
323 * Configuration File fails for some reason. If force_old_init is set, then
324 * we'll always use the old Driver-based initialization sequence.
325 */
326static uint force_old_init;
327
328module_param(force_old_init, uint, 0644);
329MODULE_PARM_DESC(force_old_init, "Force old initialization sequence");
330
b8ff05a9
DM		 331static int dflt_msg_enable = DFLT_MSG_ENABLE;
332
333module_param(dflt_msg_enable, int, 0644);
334MODULE_PARM_DESC(dflt_msg_enable, "Chelsio T4 default message enable bitmap");
335
336/*
337 * The driver uses the best interrupt scheme available on a platform in the
338 * order MSI-X, MSI, legacy INTx interrupts. This parameter determines which
339 * of these schemes the driver may consider as follows:
340 *
341 * msi = 2: choose from among all three options
342 * msi = 1: only consider MSI and INTx interrupts
343 * msi = 0: force INTx interrupts
344 */
345static int msi = 2;
346
347module_param(msi, int, 0644);
348MODULE_PARM_DESC(msi, "whether to use INTx (0), MSI (1) or MSI-X (2)");
349
350/*
351 * Queue interrupt hold-off timer values. Queues default to the first of these
352 * upon creation.
353 */
354static unsigned int intr_holdoff[SGE_NTIMERS - 1] = { 5, 10, 20, 50, 100 };
355
356module_param_array(intr_holdoff, uint, NULL, 0644);
357MODULE_PARM_DESC(intr_holdoff, "values for queue interrupt hold-off timers "
358 "0..4 in microseconds");
359
360static unsigned int intr_cnt[SGE_NCOUNTERS - 1] = { 4, 8, 16 };
361
362module_param_array(intr_cnt, uint, NULL, 0644);
363MODULE_PARM_DESC(intr_cnt,
364 "thresholds 1..3 for queue interrupt packet counters");
365
636f9d37
VP		 366/*
367 * Normally we tell the chip to deliver Ingress Packets into our DMA buffers
368 * offset by 2 bytes in order to have the IP headers line up on 4-byte
369 * boundaries. This is a requirement for many architectures which will throw
370 * a machine check fault if an attempt is made to access one of the 4-byte IP
371 * header fields on a non-4-byte boundary. And it's a major performance issue
372 * even on some architectures which allow it like some implementations of the
373 * x86 ISA. However, some architectures don't mind this and for some very
374 * edge-case performance sensitive applications (like forwarding large volumes
375 * of small packets), setting this DMA offset to 0 will decrease the number of
376 * PCI-E Bus transfers enough to measurably affect performance.
377 */
378static int rx_dma_offset = 2;
379
eb939922 380static bool vf_acls;
b8ff05a9
DM		 381
382#ifdef CONFIG_PCI_IOV
383module_param(vf_acls, bool, 0644);
384MODULE_PARM_DESC(vf_acls, "if set enable virtualization L2 ACL enforcement");
385
7d6727cf
SR		 386/* Configure the number of PCI-E Virtual Function which are to be instantiated
387 * on SR-IOV Capable Physical Functions.
0a57a536 388 */
7d6727cf 389static unsigned int num_vf[NUM_OF_PF_WITH_SRIOV];
b8ff05a9
DM		 390
391module_param_array(num_vf, uint, NULL, 0644);
7d6727cf 392MODULE_PARM_DESC(num_vf, "number of VFs for each of PFs 0-3");
b8ff05a9
DM		 393#endif
394
688848b1
AB		 395/* TX Queue select used to determine what algorithm to use for selecting TX
396 * queue. Select between the kernel provided function (select_queue=0) or user
397 * cxgb_select_queue function (select_queue=1)
398 *
399 * Default: select_queue=0
400 */
401static int select_queue;
402module_param(select_queue, int, 0644);
403MODULE_PARM_DESC(select_queue,
404 "Select between kernel provided method of selecting or driver method of selecting TX queue. Default is kernel method.");
405
13ee15d3
VP		 406/*
407 * The filter TCAM has a fixed portion and a variable portion. The fixed
408 * portion can match on source/destination IP IPv4/IPv6 addresses and TCP/UDP
409 * ports. The variable portion is 36 bits which can include things like Exact
410 * Match MAC Index (9 bits), Ether Type (16 bits), IP Protocol (8 bits),
411 * [Inner] VLAN Tag (17 bits), etc. which, if all were somehow selected, would
412 * far exceed the 36-bit budget for this "compressed" header portion of the
413 * filter. Thus, we have a scarce resource which must be carefully managed.
414 *
415 * By default we set this up to mostly match the set of filter matching
416 * capabilities of T3 but with accommodations for some of T4's more
417 * interesting features:
418 *
419 * { IP Fragment (1), MPS Match Type (3), IP Protocol (8),
420 * [Inner] VLAN (17), Port (3), FCoE (1) }
421 */
422enum {
423 TP_VLAN_PRI_MAP_DEFAULT = HW_TPL_FR_MT_PR_IV_P_FC,
424 TP_VLAN_PRI_MAP_FIRST = FCOE_SHIFT,
425 TP_VLAN_PRI_MAP_LAST = FRAGMENTATION_SHIFT,
426};
427
428static unsigned int tp_vlan_pri_map = TP_VLAN_PRI_MAP_DEFAULT;
429
f2b7e78d
VP		 430module_param(tp_vlan_pri_map, uint, 0644);
431MODULE_PARM_DESC(tp_vlan_pri_map, "global compressed filter configuration");
432
b8ff05a9
DM		 433static struct dentry *cxgb4_debugfs_root;
434
435static LIST_HEAD(adapter_list);
436static DEFINE_MUTEX(uld_mutex);
01bcca68
VP		 437/* Adapter list to be accessed from atomic context */
438static LIST_HEAD(adap_rcu_list);
439static DEFINE_SPINLOCK(adap_rcu_lock);
b8ff05a9
DM		 440static struct cxgb4_uld_info ulds[CXGB4_ULD_MAX];
441static const char *uld_str[] = { "RDMA", "iSCSI" };
442
443static void link_report(struct net_device *dev)
444{
445 if (!netif_carrier_ok(dev))
446 netdev_info(dev, "link down\n");
447 else {
448 static const char *fc[] = { "no", "Rx", "Tx", "Tx/Rx" };
449
450 const char *s = "10Mbps";
451 const struct port_info *p = netdev_priv(dev);
452
453 switch (p->link_cfg.speed) {
e8b39015 454 case 10000:
b8ff05a9
DM		 455 s = "10Gbps";
456 break;
e8b39015 457 case 1000:
b8ff05a9
DM		 458 s = "1000Mbps";
459 break;
e8b39015 460 case 100:
b8ff05a9
DM		 461 s = "100Mbps";
462 break;
e8b39015 463 case 40000:
72aca4bf
KS		 464 s = "40Gbps";
465 break;
b8ff05a9
DM		 466 }
467
468 netdev_info(dev, "link up, %s, full-duplex, %s PAUSE\n", s,
469 fc[p->link_cfg.fc]);
470 }
471}
472
688848b1
AB		 473#ifdef CONFIG_CHELSIO_T4_DCB
474/* Set up/tear down Data Center Bridging Priority mapping for a net device. */
475static void dcb_tx_queue_prio_enable(struct net_device *dev, int enable)
476{
477 struct port_info *pi = netdev_priv(dev);
478 struct adapter *adap = pi->adapter;
479 struct sge_eth_txq *txq = &adap->sge.ethtxq[pi->first_qset];
480 int i;
481
482 /* We use a simple mapping of Port TX Queue Index to DCB
483 * Priority when we're enabling DCB.
484 */
485 for (i = 0; i < pi->nqsets; i++, txq++) {
486 u32 name, value;
487 int err;
488
489 name = (FW_PARAMS_MNEM(FW_PARAMS_MNEM_DMAQ) |
490 FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DMAQ_EQ_DCBPRIO_ETH) |
491 FW_PARAMS_PARAM_YZ(txq->q.cntxt_id));
492 value = enable ? i : 0xffffffff;
493
494 /* Since we can be called while atomic (from "interrupt
495 * level") we need to issue the Set Parameters Commannd
496 * without sleeping (timeout < 0).
497 */
498 err = t4_set_params_nosleep(adap, adap->mbox, adap->fn, 0, 1,
499 &name, &value);
500
501 if (err)
502 dev_err(adap->pdev_dev,
503 "Can't %s DCB Priority on port %d, TX Queue %d: err=%d\n",
504 enable ? "set" : "unset", pi->port_id, i, -err);
505 }
506}
507#endif /* CONFIG_CHELSIO_T4_DCB */
508
b8ff05a9
DM		 509void t4_os_link_changed(struct adapter *adapter, int port_id, int link_stat)
510{
511 struct net_device *dev = adapter->port[port_id];
512
513 /* Skip changes from disabled ports. */
514 if (netif_running(dev) && link_stat != netif_carrier_ok(dev)) {
515 if (link_stat)
516 netif_carrier_on(dev);
688848b1
AB		 517 else {
518#ifdef CONFIG_CHELSIO_T4_DCB
519 cxgb4_dcb_state_init(dev);
520 dcb_tx_queue_prio_enable(dev, false);
521#endif /* CONFIG_CHELSIO_T4_DCB */
b8ff05a9 522 netif_carrier_off(dev);
688848b1 523 }
b8ff05a9
DM		 524
525 link_report(dev);
526 }
527}
528
529void t4_os_portmod_changed(const struct adapter *adap, int port_id)
530{
531 static const char *mod_str[] = {
a0881cab 532 NULL, "LR", "SR", "ER", "passive DA", "active DA", "LRM"
b8ff05a9
DM		 533 };
534
535 const struct net_device *dev = adap->port[port_id];
536 const struct port_info *pi = netdev_priv(dev);
537
538 if (pi->mod_type == FW_PORT_MOD_TYPE_NONE)
539 netdev_info(dev, "port module unplugged\n");
a0881cab 540 else if (pi->mod_type < ARRAY_SIZE(mod_str))
b8ff05a9
DM		 541 netdev_info(dev, "%s module inserted\n", mod_str[pi->mod_type]);
542}
543
544/*
545 * Configure the exact and hash address filters to handle a port's multicast
546 * and secondary unicast MAC addresses.
547 */
548static int set_addr_filters(const struct net_device *dev, bool sleep)
549{
550 u64 mhash = 0;
551 u64 uhash = 0;
552 bool free = true;
553 u16 filt_idx[7];
554 const u8 *addr[7];
555 int ret, naddr = 0;
b8ff05a9
DM		 556 const struct netdev_hw_addr *ha;
557 int uc_cnt = netdev_uc_count(dev);
4a35ecf8 558 int mc_cnt = netdev_mc_count(dev);
b8ff05a9 559 const struct port_info *pi = netdev_priv(dev);
060e0c75 560 unsigned int mb = pi->adapter->fn;
b8ff05a9
DM		 561
562 /* first do the secondary unicast addresses */
563 netdev_for_each_uc_addr(ha, dev) {
564 addr[naddr++] = ha->addr;
565 if (--uc_cnt == 0 || naddr >= ARRAY_SIZE(addr)) {
060e0c75 566 ret = t4_alloc_mac_filt(pi->adapter, mb, pi->viid, free,
b8ff05a9
DM		 567 naddr, addr, filt_idx, &uhash, sleep);
568 if (ret < 0)
569 return ret;
570
571 free = false;
572 naddr = 0;
573 }
574 }
575
576 /* next set up the multicast addresses */
4a35ecf8
DM		 577 netdev_for_each_mc_addr(ha, dev) {
578 addr[naddr++] = ha->addr;
579 if (--mc_cnt == 0 || naddr >= ARRAY_SIZE(addr)) {
060e0c75 580 ret = t4_alloc_mac_filt(pi->adapter, mb, pi->viid, free,
b8ff05a9
DM		 581 naddr, addr, filt_idx, &mhash, sleep);
582 if (ret < 0)
583 return ret;
584
585 free = false;
586 naddr = 0;
587 }
588 }
589
060e0c75 590 return t4_set_addr_hash(pi->adapter, mb, pi->viid, uhash != 0,
b8ff05a9
DM		 591 uhash | mhash, sleep);
592}
593
3069ee9b
VP		 594int dbfifo_int_thresh = 10; /* 10 == 640 entry threshold */
595module_param(dbfifo_int_thresh, int, 0644);
596MODULE_PARM_DESC(dbfifo_int_thresh, "doorbell fifo interrupt threshold");
597
404d9e3f
VP		 598/*
599 * usecs to sleep while draining the dbfifo
600 */
601static int dbfifo_drain_delay = 1000;
3069ee9b
VP		 602module_param(dbfifo_drain_delay, int, 0644);
603MODULE_PARM_DESC(dbfifo_drain_delay,
604 "usecs to sleep while draining the dbfifo");
605
b8ff05a9
DM		 606/*
607 * Set Rx properties of a port, such as promiscruity, address filters, and MTU.
608 * If @mtu is -1 it is left unchanged.
609 */
610static int set_rxmode(struct net_device *dev, int mtu, bool sleep_ok)
611{
612 int ret;
613 struct port_info *pi = netdev_priv(dev);
614
615 ret = set_addr_filters(dev, sleep_ok);
616 if (ret == 0)
060e0c75 617 ret = t4_set_rxmode(pi->adapter, pi->adapter->fn, pi->viid, mtu,
b8ff05a9 618 (dev->flags & IFF_PROMISC) ? 1 : 0,
f8f5aafa 619 (dev->flags & IFF_ALLMULTI) ? 1 : 0, 1, -1,
b8ff05a9
DM		 620 sleep_ok);
621 return ret;
622}
623
3069ee9b
VP		 624static struct workqueue_struct *workq;
625
b8ff05a9
DM		 626/**
627 * link_start - enable a port
628 * @dev: the port to enable
629 *
630 * Performs the MAC and PHY actions needed to enable a port.
631 */
632static int link_start(struct net_device *dev)
633{
634 int ret;
635 struct port_info *pi = netdev_priv(dev);
060e0c75 636 unsigned int mb = pi->adapter->fn;
b8ff05a9
DM		 637
638 /*
639 * We do not set address filters and promiscuity here, the stack does
640 * that step explicitly.
641 */
060e0c75 642 ret = t4_set_rxmode(pi->adapter, mb, pi->viid, dev->mtu, -1, -1, -1,
f646968f 643 !!(dev->features & NETIF_F_HW_VLAN_CTAG_RX), true);
b8ff05a9 644 if (ret == 0) {
060e0c75 645 ret = t4_change_mac(pi->adapter, mb, pi->viid,
b8ff05a9 646 pi->xact_addr_filt, dev->dev_addr, true,
b6bd29e7 647 true);
b8ff05a9
DM		 648 if (ret >= 0) {
649 pi->xact_addr_filt = ret;
650 ret = 0;
651 }
652 }
653 if (ret == 0)
060e0c75
DM		 654 ret = t4_link_start(pi->adapter, mb, pi->tx_chan,
655 &pi->link_cfg);
b8ff05a9 656 if (ret == 0)
688848b1
AB		 657 ret = t4_enable_vi_params(pi->adapter, mb, pi->viid, true,
658 true, CXGB4_DCB_ENABLED);
659
b8ff05a9
DM		 660 return ret;
661}
662
688848b1
AB		 663int cxgb4_dcb_enabled(const struct net_device *dev)
664{
665#ifdef CONFIG_CHELSIO_T4_DCB
666 struct port_info *pi = netdev_priv(dev);
667
668 return pi->dcb.state == CXGB4_DCB_STATE_FW_ALLSYNCED;
669#else
670 return 0;
671#endif
672}
673EXPORT_SYMBOL(cxgb4_dcb_enabled);
674
675#ifdef CONFIG_CHELSIO_T4_DCB
676/* Handle a Data Center Bridging update message from the firmware. */
677static void dcb_rpl(struct adapter *adap, const struct fw_port_cmd *pcmd)
678{
679 int port = FW_PORT_CMD_PORTID_GET(ntohl(pcmd->op_to_portid));
680 struct net_device *dev = adap->port[port];
681 int old_dcb_enabled = cxgb4_dcb_enabled(dev);
682 int new_dcb_enabled;
683
684 cxgb4_dcb_handle_fw_update(adap, pcmd);
685 new_dcb_enabled = cxgb4_dcb_enabled(dev);
686
687 /* If the DCB has become enabled or disabled on the port then we're
688 * going to need to set up/tear down DCB Priority parameters for the
689 * TX Queues associated with the port.
690 */
691 if (new_dcb_enabled != old_dcb_enabled)
692 dcb_tx_queue_prio_enable(dev, new_dcb_enabled);
693}
694#endif /* CONFIG_CHELSIO_T4_DCB */
695
f2b7e78d
VP		 696/* Clear a filter and release any of its resources that we own. This also
697 * clears the filter's "pending" status.
698 */
699static void clear_filter(struct adapter *adap, struct filter_entry *f)
700{
701 /* If the new or old filter have loopback rewriteing rules then we'll
702 * need to free any existing Layer Two Table (L2T) entries of the old
703 * filter rule. The firmware will handle freeing up any Source MAC
704 * Table (SMT) entries used for rewriting Source MAC Addresses in
705 * loopback rules.
706 */
707 if (f->l2t)
708 cxgb4_l2t_release(f->l2t);
709
710 /* The zeroing of the filter rule below clears the filter valid,
711 * pending, locked flags, l2t pointer, etc. so it's all we need for
712 * this operation.
713 */
714 memset(f, 0, sizeof(*f));
715}
716
717/* Handle a filter write/deletion reply.
718 */
719static void filter_rpl(struct adapter *adap, const struct cpl_set_tcb_rpl *rpl)
720{
721 unsigned int idx = GET_TID(rpl);
722 unsigned int nidx = idx - adap->tids.ftid_base;
723 unsigned int ret;
724 struct filter_entry *f;
725
726 if (idx >= adap->tids.ftid_base && nidx <
727 (adap->tids.nftids + adap->tids.nsftids)) {
728 idx = nidx;
729 ret = GET_TCB_COOKIE(rpl->cookie);
730 f = &adap->tids.ftid_tab[idx];
731
732 if (ret == FW_FILTER_WR_FLT_DELETED) {
733 /* Clear the filter when we get confirmation from the
734 * hardware that the filter has been deleted.
735 */
736 clear_filter(adap, f);
737 } else if (ret == FW_FILTER_WR_SMT_TBL_FULL) {
738 dev_err(adap->pdev_dev, "filter %u setup failed due to full SMT\n",
739 idx);
740 clear_filter(adap, f);
741 } else if (ret == FW_FILTER_WR_FLT_ADDED) {
742 f->smtidx = (be64_to_cpu(rpl->oldval) >> 24) & 0xff;
743 f->pending = 0; /* asynchronous setup completed */
744 f->valid = 1;
745 } else {
746 /* Something went wrong. Issue a warning about the
747 * problem and clear everything out.
748 */
749 dev_err(adap->pdev_dev, "filter %u setup failed with error %u\n",
750 idx, ret);
751 clear_filter(adap, f);
752 }
753 }
754}
755
756/* Response queue handler for the FW event queue.
b8ff05a9
DM		 757 */
758static int fwevtq_handler(struct sge_rspq *q, const __be64 *rsp,
759 const struct pkt_gl *gl)
760{
761 u8 opcode = ((const struct rss_header *)rsp)->opcode;
762
763 rsp++; /* skip RSS header */
b407a4a9
VP		 764
765 /* FW can send EGR_UPDATEs encapsulated in a CPL_FW4_MSG.
766 */
767 if (unlikely(opcode == CPL_FW4_MSG &&
768 ((const struct cpl_fw4_msg *)rsp)->type == FW_TYPE_RSSCPL)) {
769 rsp++;
770 opcode = ((const struct rss_header *)rsp)->opcode;
771 rsp++;
772 if (opcode != CPL_SGE_EGR_UPDATE) {
773 dev_err(q->adap->pdev_dev, "unexpected FW4/CPL %#x on FW event queue\n"
774 , opcode);
775 goto out;
776 }
777 }
778
b8ff05a9
DM		 779 if (likely(opcode == CPL_SGE_EGR_UPDATE)) {
780 const struct cpl_sge_egr_update *p = (void *)rsp;
781 unsigned int qid = EGR_QID(ntohl(p->opcode_qid));
e46dab4d 782 struct sge_txq *txq;
b8ff05a9 783
e46dab4d 784 txq = q->adap->sge.egr_map[qid - q->adap->sge.egr_start];
b8ff05a9 785 txq->restarts++;
e46dab4d 786 if ((u8 *)txq < (u8 *)q->adap->sge.ofldtxq) {
b8ff05a9
DM		 787 struct sge_eth_txq *eq;
788
789 eq = container_of(txq, struct sge_eth_txq, q);
790 netif_tx_wake_queue(eq->txq);
791 } else {
792 struct sge_ofld_txq *oq;
793
794 oq = container_of(txq, struct sge_ofld_txq, q);
795 tasklet_schedule(&oq->qresume_tsk);
796 }
797 } else if (opcode == CPL_FW6_MSG || opcode == CPL_FW4_MSG) {
798 const struct cpl_fw6_msg *p = (void *)rsp;
799
688848b1
AB		 800#ifdef CONFIG_CHELSIO_T4_DCB
801 const struct fw_port_cmd *pcmd = (const void *)p->data;
802 unsigned int cmd = FW_CMD_OP_GET(ntohl(pcmd->op_to_portid));
803 unsigned int action =
804 FW_PORT_CMD_ACTION_GET(ntohl(pcmd->action_to_len16));
805
806 if (cmd == FW_PORT_CMD &&
807 action == FW_PORT_ACTION_GET_PORT_INFO) {
808 int port = FW_PORT_CMD_PORTID_GET(
809 be32_to_cpu(pcmd->op_to_portid));
810 struct net_device *dev = q->adap->port[port];
811 int state_input = ((pcmd->u.info.dcbxdis_pkd &
812 FW_PORT_CMD_DCBXDIS)
813 ? CXGB4_DCB_INPUT_FW_DISABLED
814 : CXGB4_DCB_INPUT_FW_ENABLED);
815
816 cxgb4_dcb_state_fsm(dev, state_input);
817 }
818
819 if (cmd == FW_PORT_CMD &&
820 action == FW_PORT_ACTION_L2_DCB_CFG)
821 dcb_rpl(q->adap, pcmd);
822 else
823#endif
824 if (p->type == 0)
825 t4_handle_fw_rpl(q->adap, p->data);
b8ff05a9
DM		 826 } else if (opcode == CPL_L2T_WRITE_RPL) {
827 const struct cpl_l2t_write_rpl *p = (void *)rsp;
828
829 do_l2t_write_rpl(q->adap, p);
f2b7e78d
VP		 830 } else if (opcode == CPL_SET_TCB_RPL) {
831 const struct cpl_set_tcb_rpl *p = (void *)rsp;
832
833 filter_rpl(q->adap, p);
b8ff05a9
DM		 834 } else
835 dev_err(q->adap->pdev_dev,
836 "unexpected CPL %#x on FW event queue\n", opcode);
b407a4a9 837out:
b8ff05a9
DM		 838 return 0;
839}
840
841/**
842 * uldrx_handler - response queue handler for ULD queues
843 * @q: the response queue that received the packet
844 * @rsp: the response queue descriptor holding the offload message
845 * @gl: the gather list of packet fragments
846 *
847 * Deliver an ingress offload packet to a ULD. All processing is done by
848 * the ULD, we just maintain statistics.
849 */
850static int uldrx_handler(struct sge_rspq *q, const __be64 *rsp,
851 const struct pkt_gl *gl)
852{
853 struct sge_ofld_rxq *rxq = container_of(q, struct sge_ofld_rxq, rspq);
854
b407a4a9
VP		 855 /* FW can send CPLs encapsulated in a CPL_FW4_MSG.
856 */
857 if (((const struct rss_header *)rsp)->opcode == CPL_FW4_MSG &&
858 ((const struct cpl_fw4_msg *)(rsp + 1))->type == FW_TYPE_RSSCPL)
859 rsp += 2;
860
b8ff05a9
DM		 861 if (ulds[q->uld].rx_handler(q->adap->uld_handle[q->uld], rsp, gl)) {
862 rxq->stats.nomem++;
863 return -1;
864 }
865 if (gl == NULL)
866 rxq->stats.imm++;
867 else if (gl == CXGB4_MSG_AN)
868 rxq->stats.an++;
869 else
870 rxq->stats.pkts++;
871 return 0;
872}
873
874static void disable_msi(struct adapter *adapter)
875{
876 if (adapter->flags & USING_MSIX) {
877 pci_disable_msix(adapter->pdev);
878 adapter->flags &= ~USING_MSIX;
879 } else if (adapter->flags & USING_MSI) {
880 pci_disable_msi(adapter->pdev);
881 adapter->flags &= ~USING_MSI;
882 }
883}
884
885/*
886 * Interrupt handler for non-data events used with MSI-X.
887 */
888static irqreturn_t t4_nondata_intr(int irq, void *cookie)
889{
890 struct adapter *adap = cookie;
891
892 u32 v = t4_read_reg(adap, MYPF_REG(PL_PF_INT_CAUSE));
893 if (v & PFSW) {
894 adap->swintr = 1;
895 t4_write_reg(adap, MYPF_REG(PL_PF_INT_CAUSE), v);
896 }
897 t4_slow_intr_handler(adap);
898 return IRQ_HANDLED;
899}
900
901/*
902 * Name the MSI-X interrupts.
903 */
904static void name_msix_vecs(struct adapter *adap)
905{
ba27816c 906 int i, j, msi_idx = 2, n = sizeof(adap->msix_info[0].desc);
b8ff05a9
DM		 907
908 /* non-data interrupts */
b1a3c2b6 909 snprintf(adap->msix_info[0].desc, n, "%s", adap->port[0]->name);
b8ff05a9
DM		 910
911 /* FW events */
b1a3c2b6
DM		 912 snprintf(adap->msix_info[1].desc, n, "%s-FWeventq",
913 adap->port[0]->name);
b8ff05a9
DM		 914
915 /* Ethernet queues */
916 for_each_port(adap, j) {
917 struct net_device *d = adap->port[j];
918 const struct port_info *pi = netdev_priv(d);
919
ba27816c 920 for (i = 0; i < pi->nqsets; i++, msi_idx++)
b8ff05a9
DM		 921 snprintf(adap->msix_info[msi_idx].desc, n, "%s-Rx%d",
922 d->name, i);
b8ff05a9
DM		 923 }
924
925 /* offload queues */
ba27816c
DM		 926 for_each_ofldrxq(&adap->sge, i)
927 snprintf(adap->msix_info[msi_idx++].desc, n, "%s-ofld%d",
b1a3c2b6 928 adap->port[0]->name, i);
ba27816c
DM		 929
930 for_each_rdmarxq(&adap->sge, i)
931 snprintf(adap->msix_info[msi_idx++].desc, n, "%s-rdma%d",
b1a3c2b6 932 adap->port[0]->name, i);
cf38be6d
HS		 933
934 for_each_rdmaciq(&adap->sge, i)
935 snprintf(adap->msix_info[msi_idx++].desc, n, "%s-rdma-ciq%d",
936 adap->port[0]->name, i);
b8ff05a9
DM		 937}
938
939static int request_msix_queue_irqs(struct adapter *adap)
940{
941 struct sge *s = &adap->sge;
cf38be6d
HS		 942 int err, ethqidx, ofldqidx = 0, rdmaqidx = 0, rdmaciqqidx = 0;
943 int msi_index = 2;
b8ff05a9
DM		 944
945 err = request_irq(adap->msix_info[1].vec, t4_sge_intr_msix, 0,
946 adap->msix_info[1].desc, &s->fw_evtq);
947 if (err)
948 return err;
949
950 for_each_ethrxq(s, ethqidx) {
404d9e3f
VP		 951 err = request_irq(adap->msix_info[msi_index].vec,
952 t4_sge_intr_msix, 0,
953 adap->msix_info[msi_index].desc,
b8ff05a9
DM		 954 &s->ethrxq[ethqidx].rspq);
955 if (err)
956 goto unwind;
404d9e3f 957 msi_index++;
b8ff05a9
DM		 958 }
959 for_each_ofldrxq(s, ofldqidx) {
404d9e3f
VP		 960 err = request_irq(adap->msix_info[msi_index].vec,
961 t4_sge_intr_msix, 0,
962 adap->msix_info[msi_index].desc,
b8ff05a9
DM		 963 &s->ofldrxq[ofldqidx].rspq);
964 if (err)
965 goto unwind;
404d9e3f 966 msi_index++;
b8ff05a9
DM		 967 }
968 for_each_rdmarxq(s, rdmaqidx) {
404d9e3f
VP		 969 err = request_irq(adap->msix_info[msi_index].vec,
970 t4_sge_intr_msix, 0,
971 adap->msix_info[msi_index].desc,
b8ff05a9
DM		 972 &s->rdmarxq[rdmaqidx].rspq);
973 if (err)
974 goto unwind;
404d9e3f 975 msi_index++;
b8ff05a9 976 }
cf38be6d
HS		 977 for_each_rdmaciq(s, rdmaciqqidx) {
978 err = request_irq(adap->msix_info[msi_index].vec,
979 t4_sge_intr_msix, 0,
980 adap->msix_info[msi_index].desc,
981 &s->rdmaciq[rdmaciqqidx].rspq);
982 if (err)
983 goto unwind;
984 msi_index++;
985 }
b8ff05a9
DM		 986 return 0;
987
988unwind:
cf38be6d
HS		 989 while (--rdmaciqqidx >= 0)
990 free_irq(adap->msix_info[--msi_index].vec,
991 &s->rdmaciq[rdmaciqqidx].rspq);
b8ff05a9 992 while (--rdmaqidx >= 0)
404d9e3f 993 free_irq(adap->msix_info[--msi_index].vec,
b8ff05a9
DM		 994 &s->rdmarxq[rdmaqidx].rspq);
995 while (--ofldqidx >= 0)
404d9e3f 996 free_irq(adap->msix_info[--msi_index].vec,
b8ff05a9
DM		 997 &s->ofldrxq[ofldqidx].rspq);
998 while (--ethqidx >= 0)
404d9e3f
VP		 999 free_irq(adap->msix_info[--msi_index].vec,
1000 &s->ethrxq[ethqidx].rspq);
b8ff05a9
DM		 1001 free_irq(adap->msix_info[1].vec, &s->fw_evtq);
1002 return err;
1003}
1004
1005static void free_msix_queue_irqs(struct adapter *adap)
1006{
404d9e3f 1007 int i, msi_index = 2;
b8ff05a9
DM		 1008 struct sge *s = &adap->sge;
1009
1010 free_irq(adap->msix_info[1].vec, &s->fw_evtq);
1011 for_each_ethrxq(s, i)
404d9e3f 1012 free_irq(adap->msix_info[msi_index++].vec, &s->ethrxq[i].rspq);
b8ff05a9 1013 for_each_ofldrxq(s, i)
404d9e3f 1014 free_irq(adap->msix_info[msi_index++].vec, &s->ofldrxq[i].rspq);
b8ff05a9 1015 for_each_rdmarxq(s, i)
404d9e3f 1016 free_irq(adap->msix_info[msi_index++].vec, &s->rdmarxq[i].rspq);
cf38be6d
HS		 1017 for_each_rdmaciq(s, i)
1018 free_irq(adap->msix_info[msi_index++].vec, &s->rdmaciq[i].rspq);
b8ff05a9
DM		 1019}
1020
671b0060
DM		 1021/**
1022 * write_rss - write the RSS table for a given port
1023 * @pi: the port
1024 * @queues: array of queue indices for RSS
1025 *
1026 * Sets up the portion of the HW RSS table for the port's VI to distribute
1027 * packets to the Rx queues in @queues.
1028 */
1029static int write_rss(const struct port_info *pi, const u16 *queues)
1030{
1031 u16 *rss;
1032 int i, err;
1033 const struct sge_eth_rxq *q = &pi->adapter->sge.ethrxq[pi->first_qset];
1034
1035 rss = kmalloc(pi->rss_size * sizeof(u16), GFP_KERNEL);
1036 if (!rss)
1037 return -ENOMEM;
1038
1039 /* map the queue indices to queue ids */
1040 for (i = 0; i < pi->rss_size; i++, queues++)
1041 rss[i] = q[*queues].rspq.abs_id;
1042
060e0c75
DM		 1043 err = t4_config_rss_range(pi->adapter, pi->adapter->fn, pi->viid, 0,
1044 pi->rss_size, rss, pi->rss_size);
671b0060
DM		 1045 kfree(rss);
1046 return err;
1047}
1048
b8ff05a9
DM		 1049/**
1050 * setup_rss - configure RSS
1051 * @adap: the adapter
1052 *
671b0060 1053 * Sets up RSS for each port.
b8ff05a9
DM		 1054 */
1055static int setup_rss(struct adapter *adap)
1056{
671b0060 1057 int i, err;
b8ff05a9
DM		 1058
1059 for_each_port(adap, i) {
1060 const struct port_info *pi = adap2pinfo(adap, i);
b8ff05a9 1061
671b0060 1062 err = write_rss(pi, pi->rss);
b8ff05a9
DM		 1063 if (err)
1064 return err;
1065 }
1066 return 0;
1067}
1068
e46dab4d
DM		 1069/*
1070 * Return the channel of the ingress queue with the given qid.
1071 */
1072static unsigned int rxq_to_chan(const struct sge *p, unsigned int qid)
1073{
1074 qid -= p->ingr_start;
1075 return netdev2pinfo(p->ingr_map[qid]->netdev)->tx_chan;
1076}
1077
b8ff05a9
DM		 1078/*
1079 * Wait until all NAPI handlers are descheduled.
1080 */
1081static void quiesce_rx(struct adapter *adap)
1082{
1083 int i;
1084
1085 for (i = 0; i < ARRAY_SIZE(adap->sge.ingr_map); i++) {
1086 struct sge_rspq *q = adap->sge.ingr_map[i];
1087
1088 if (q && q->handler)
1089 napi_disable(&q->napi);
1090 }
1091}
1092
1093/*
1094 * Enable NAPI scheduling and interrupt generation for all Rx queues.
1095 */
1096static void enable_rx(struct adapter *adap)
1097{
1098 int i;
1099
1100 for (i = 0; i < ARRAY_SIZE(adap->sge.ingr_map); i++) {
1101 struct sge_rspq *q = adap->sge.ingr_map[i];
1102
1103 if (!q)
1104 continue;
1105 if (q->handler)
1106 napi_enable(&q->napi);
1107 /* 0-increment GTS to start the timer and enable interrupts */
1108 t4_write_reg(adap, MYPF_REG(SGE_PF_GTS),
1109 SEINTARM(q->intr_params) |
1110 INGRESSQID(q->cntxt_id));
1111 }
1112}
1113
1114/**
1115 * setup_sge_queues - configure SGE Tx/Rx/response queues
1116 * @adap: the adapter
1117 *
1118 * Determines how many sets of SGE queues to use and initializes them.
1119 * We support multiple queue sets per port if we have MSI-X, otherwise
1120 * just one queue set per port.
1121 */
1122static int setup_sge_queues(struct adapter *adap)
1123{
1124 int err, msi_idx, i, j;
1125 struct sge *s = &adap->sge;
1126
1127 bitmap_zero(s->starving_fl, MAX_EGRQ);
1128 bitmap_zero(s->txq_maperr, MAX_EGRQ);
1129
1130 if (adap->flags & USING_MSIX)
1131 msi_idx = 1; /* vector 0 is for non-queue interrupts */
1132 else {
1133 err = t4_sge_alloc_rxq(adap, &s->intrq, false, adap->port[0], 0,
1134 NULL, NULL);
1135 if (err)
1136 return err;
1137 msi_idx = -((int)s->intrq.abs_id + 1);
1138 }
1139
1140 err = t4_sge_alloc_rxq(adap, &s->fw_evtq, true, adap->port[0],
1141 msi_idx, NULL, fwevtq_handler);
1142 if (err) {
1143freeout: t4_free_sge_resources(adap);
1144 return err;
1145 }
1146
1147 for_each_port(adap, i) {
1148 struct net_device *dev = adap->port[i];
1149 struct port_info *pi = netdev_priv(dev);
1150 struct sge_eth_rxq *q = &s->ethrxq[pi->first_qset];
1151 struct sge_eth_txq *t = &s->ethtxq[pi->first_qset];
1152
1153 for (j = 0; j < pi->nqsets; j++, q++) {
1154 if (msi_idx > 0)
1155 msi_idx++;
1156 err = t4_sge_alloc_rxq(adap, &q->rspq, false, dev,
1157 msi_idx, &q->fl,
1158 t4_ethrx_handler);
1159 if (err)
1160 goto freeout;
1161 q->rspq.idx = j;
1162 memset(&q->stats, 0, sizeof(q->stats));
1163 }
1164 for (j = 0; j < pi->nqsets; j++, t++) {
1165 err = t4_sge_alloc_eth_txq(adap, t, dev,
1166 netdev_get_tx_queue(dev, j),
1167 s->fw_evtq.cntxt_id);
1168 if (err)
1169 goto freeout;
1170 }
1171 }
1172
1173 j = s->ofldqsets / adap->params.nports; /* ofld queues per channel */
1174 for_each_ofldrxq(s, i) {
1175 struct sge_ofld_rxq *q = &s->ofldrxq[i];
1176 struct net_device *dev = adap->port[i / j];
1177
1178 if (msi_idx > 0)
1179 msi_idx++;
1180 err = t4_sge_alloc_rxq(adap, &q->rspq, false, dev, msi_idx,
cf38be6d
HS		 1181 q->fl.size ? &q->fl : NULL,
1182 uldrx_handler);
b8ff05a9
DM		 1183 if (err)
1184 goto freeout;
1185 memset(&q->stats, 0, sizeof(q->stats));
1186 s->ofld_rxq[i] = q->rspq.abs_id;
1187 err = t4_sge_alloc_ofld_txq(adap, &s->ofldtxq[i], dev,
1188 s->fw_evtq.cntxt_id);
1189 if (err)
1190 goto freeout;
1191 }
1192
1193 for_each_rdmarxq(s, i) {
1194 struct sge_ofld_rxq *q = &s->rdmarxq[i];
1195
1196 if (msi_idx > 0)
1197 msi_idx++;
1198 err = t4_sge_alloc_rxq(adap, &q->rspq, false, adap->port[i],
cf38be6d
HS		 1199 msi_idx, q->fl.size ? &q->fl : NULL,
1200 uldrx_handler);
b8ff05a9
DM		 1201 if (err)
1202 goto freeout;
1203 memset(&q->stats, 0, sizeof(q->stats));
1204 s->rdma_rxq[i] = q->rspq.abs_id;
1205 }
1206
cf38be6d
HS		 1207 for_each_rdmaciq(s, i) {
1208 struct sge_ofld_rxq *q = &s->rdmaciq[i];
1209
1210 if (msi_idx > 0)
1211 msi_idx++;
1212 err = t4_sge_alloc_rxq(adap, &q->rspq, false, adap->port[i],
1213 msi_idx, q->fl.size ? &q->fl : NULL,
1214 uldrx_handler);
1215 if (err)
1216 goto freeout;
1217 memset(&q->stats, 0, sizeof(q->stats));
1218 s->rdma_ciq[i] = q->rspq.abs_id;
1219 }
1220
b8ff05a9
DM		 1221 for_each_port(adap, i) {
1222 /*
1223 * Note that ->rdmarxq[i].rspq.cntxt_id below is 0 if we don't
1224 * have RDMA queues, and that's the right value.
1225 */
1226 err = t4_sge_alloc_ctrl_txq(adap, &s->ctrlq[i], adap->port[i],
1227 s->fw_evtq.cntxt_id,
1228 s->rdmarxq[i].rspq.cntxt_id);
1229 if (err)
1230 goto freeout;
1231 }
1232
1233 t4_write_reg(adap, MPS_TRC_RSS_CONTROL,
1234 RSSCONTROL(netdev2pinfo(adap->port[0])->tx_chan) |
1235 QUEUENUMBER(s->ethrxq[0].rspq.abs_id));
1236 return 0;
1237}
1238
b8ff05a9
DM		 1239/*
1240 * Allocate a chunk of memory using kmalloc or, if that fails, vmalloc.
1241 * The allocated memory is cleared.
1242 */
1243void *t4_alloc_mem(size_t size)
1244{
8be04b93 1245 void *p = kzalloc(size, GFP_KERNEL | __GFP_NOWARN);
b8ff05a9
DM		 1246
1247 if (!p)
89bf67f1 1248 p = vzalloc(size);
b8ff05a9
DM		 1249 return p;
1250}
1251
1252/*
1253 * Free memory allocated through alloc_mem().
1254 */
31b9c19b 1255static void t4_free_mem(void *addr)
b8ff05a9
DM		 1256{
1257 if (is_vmalloc_addr(addr))
1258 vfree(addr);
1259 else
1260 kfree(addr);
1261}
1262
f2b7e78d
VP		 1263/* Send a Work Request to write the filter at a specified index. We construct
1264 * a Firmware Filter Work Request to have the work done and put the indicated
1265 * filter into "pending" mode which will prevent any further actions against
1266 * it till we get a reply from the firmware on the completion status of the
1267 * request.
1268 */
1269static int set_filter_wr(struct adapter *adapter, int fidx)
1270{
1271 struct filter_entry *f = &adapter->tids.ftid_tab[fidx];
1272 struct sk_buff *skb;
1273 struct fw_filter_wr *fwr;
1274 unsigned int ftid;
1275
1276 /* If the new filter requires loopback Destination MAC and/or VLAN
1277 * rewriting then we need to allocate a Layer 2 Table (L2T) entry for
1278 * the filter.
1279 */
1280 if (f->fs.newdmac || f->fs.newvlan) {
1281 /* allocate L2T entry for new filter */
1282 f->l2t = t4_l2t_alloc_switching(adapter->l2t);
1283 if (f->l2t == NULL)
1284 return -EAGAIN;
1285 if (t4_l2t_set_switching(adapter, f->l2t, f->fs.vlan,
1286 f->fs.eport, f->fs.dmac)) {
1287 cxgb4_l2t_release(f->l2t);
1288 f->l2t = NULL;
1289 return -ENOMEM;
1290 }
1291 }
1292
1293 ftid = adapter->tids.ftid_base + fidx;
1294
1295 skb = alloc_skb(sizeof(*fwr), GFP_KERNEL | __GFP_NOFAIL);
1296 fwr = (struct fw_filter_wr *)__skb_put(skb, sizeof(*fwr));
1297 memset(fwr, 0, sizeof(*fwr));
1298
1299 /* It would be nice to put most of the following in t4_hw.c but most
1300 * of the work is translating the cxgbtool ch_filter_specification
1301 * into the Work Request and the definition of that structure is
1302 * currently in cxgbtool.h which isn't appropriate to pull into the
1303 * common code. We may eventually try to come up with a more neutral
1304 * filter specification structure but for now it's easiest to simply
1305 * put this fairly direct code in line ...
1306 */
1307 fwr->op_pkd = htonl(FW_WR_OP(FW_FILTER_WR));
1308 fwr->len16_pkd = htonl(FW_WR_LEN16(sizeof(*fwr)/16));
1309 fwr->tid_to_iq =
1310 htonl(V_FW_FILTER_WR_TID(ftid) |
1311 V_FW_FILTER_WR_RQTYPE(f->fs.type) |
1312 V_FW_FILTER_WR_NOREPLY(0) |
1313 V_FW_FILTER_WR_IQ(f->fs.iq));
1314 fwr->del_filter_to_l2tix =
1315 htonl(V_FW_FILTER_WR_RPTTID(f->fs.rpttid) |
1316 V_FW_FILTER_WR_DROP(f->fs.action == FILTER_DROP) |
1317 V_FW_FILTER_WR_DIRSTEER(f->fs.dirsteer) |
1318 V_FW_FILTER_WR_MASKHASH(f->fs.maskhash) |
1319 V_FW_FILTER_WR_DIRSTEERHASH(f->fs.dirsteerhash) |
1320 V_FW_FILTER_WR_LPBK(f->fs.action == FILTER_SWITCH) |
1321 V_FW_FILTER_WR_DMAC(f->fs.newdmac) |
1322 V_FW_FILTER_WR_SMAC(f->fs.newsmac) |
1323 V_FW_FILTER_WR_INSVLAN(f->fs.newvlan == VLAN_INSERT ||
1324 f->fs.newvlan == VLAN_REWRITE) |
1325 V_FW_FILTER_WR_RMVLAN(f->fs.newvlan == VLAN_REMOVE ||
1326 f->fs.newvlan == VLAN_REWRITE) |
1327 V_FW_FILTER_WR_HITCNTS(f->fs.hitcnts) |
1328 V_FW_FILTER_WR_TXCHAN(f->fs.eport) |
1329 V_FW_FILTER_WR_PRIO(f->fs.prio) |
1330 V_FW_FILTER_WR_L2TIX(f->l2t ? f->l2t->idx : 0));
1331 fwr->ethtype = htons(f->fs.val.ethtype);
1332 fwr->ethtypem = htons(f->fs.mask.ethtype);
1333 fwr->frag_to_ovlan_vldm =
1334 (V_FW_FILTER_WR_FRAG(f->fs.val.frag) |
1335 V_FW_FILTER_WR_FRAGM(f->fs.mask.frag) |
1336 V_FW_FILTER_WR_IVLAN_VLD(f->fs.val.ivlan_vld) |
1337 V_FW_FILTER_WR_OVLAN_VLD(f->fs.val.ovlan_vld) |
1338 V_FW_FILTER_WR_IVLAN_VLDM(f->fs.mask.ivlan_vld) |
1339 V_FW_FILTER_WR_OVLAN_VLDM(f->fs.mask.ovlan_vld));
1340 fwr->smac_sel = 0;
1341 fwr->rx_chan_rx_rpl_iq =
1342 htons(V_FW_FILTER_WR_RX_CHAN(0) |
1343 V_FW_FILTER_WR_RX_RPL_IQ(adapter->sge.fw_evtq.abs_id));
1344 fwr->maci_to_matchtypem =
1345 htonl(V_FW_FILTER_WR_MACI(f->fs.val.macidx) |
1346 V_FW_FILTER_WR_MACIM(f->fs.mask.macidx) |
1347 V_FW_FILTER_WR_FCOE(f->fs.val.fcoe) |
1348 V_FW_FILTER_WR_FCOEM(f->fs.mask.fcoe) |
1349 V_FW_FILTER_WR_PORT(f->fs.val.iport) |
1350 V_FW_FILTER_WR_PORTM(f->fs.mask.iport) |
1351 V_FW_FILTER_WR_MATCHTYPE(f->fs.val.matchtype) |
1352 V_FW_FILTER_WR_MATCHTYPEM(f->fs.mask.matchtype));
1353 fwr->ptcl = f->fs.val.proto;
1354 fwr->ptclm = f->fs.mask.proto;
1355 fwr->ttyp = f->fs.val.tos;
1356 fwr->ttypm = f->fs.mask.tos;
1357 fwr->ivlan = htons(f->fs.val.ivlan);
1358 fwr->ivlanm = htons(f->fs.mask.ivlan);
1359 fwr->ovlan = htons(f->fs.val.ovlan);
1360 fwr->ovlanm = htons(f->fs.mask.ovlan);
1361 memcpy(fwr->lip, f->fs.val.lip, sizeof(fwr->lip));
1362 memcpy(fwr->lipm, f->fs.mask.lip, sizeof(fwr->lipm));
1363 memcpy(fwr->fip, f->fs.val.fip, sizeof(fwr->fip));
1364 memcpy(fwr->fipm, f->fs.mask.fip, sizeof(fwr->fipm));
1365 fwr->lp = htons(f->fs.val.lport);
1366 fwr->lpm = htons(f->fs.mask.lport);
1367 fwr->fp = htons(f->fs.val.fport);
1368 fwr->fpm = htons(f->fs.mask.fport);
1369 if (f->fs.newsmac)
1370 memcpy(fwr->sma, f->fs.smac, sizeof(fwr->sma));
1371
1372 /* Mark the filter as "pending" and ship off the Filter Work Request.
1373 * When we get the Work Request Reply we'll clear the pending status.
1374 */
1375 f->pending = 1;
1376 set_wr_txq(skb, CPL_PRIORITY_CONTROL, f->fs.val.iport & 0x3);
1377 t4_ofld_send(adapter, skb);
1378 return 0;
1379}
1380
1381/* Delete the filter at a specified index.
1382 */
1383static int del_filter_wr(struct adapter *adapter, int fidx)
1384{
1385 struct filter_entry *f = &adapter->tids.ftid_tab[fidx];
1386 struct sk_buff *skb;
1387 struct fw_filter_wr *fwr;
1388 unsigned int len, ftid;
1389
1390 len = sizeof(*fwr);
1391 ftid = adapter->tids.ftid_base + fidx;
1392
1393 skb = alloc_skb(len, GFP_KERNEL | __GFP_NOFAIL);
1394 fwr = (struct fw_filter_wr *)__skb_put(skb, len);
1395 t4_mk_filtdelwr(ftid, fwr, adapter->sge.fw_evtq.abs_id);
1396
1397 /* Mark the filter as "pending" and ship off the Filter Work Request.
1398 * When we get the Work Request Reply we'll clear the pending status.
1399 */
1400 f->pending = 1;
1401 t4_mgmt_tx(adapter, skb);
1402 return 0;
1403}
1404
688848b1
AB		 1405static u16 cxgb_select_queue(struct net_device *dev, struct sk_buff *skb,
1406 void *accel_priv, select_queue_fallback_t fallback)
1407{
1408 int txq;
1409
1410#ifdef CONFIG_CHELSIO_T4_DCB
1411 /* If a Data Center Bridging has been successfully negotiated on this
1412 * link then we'll use the skb's priority to map it to a TX Queue.
1413 * The skb's priority is determined via the VLAN Tag Priority Code
1414 * Point field.
1415 */
1416 if (cxgb4_dcb_enabled(dev)) {
1417 u16 vlan_tci;
1418 int err;
1419
1420 err = vlan_get_tag(skb, &vlan_tci);
1421 if (unlikely(err)) {
1422 if (net_ratelimit())
1423 netdev_warn(dev,
1424 "TX Packet without VLAN Tag on DCB Link\n");
1425 txq = 0;
1426 } else {
1427 txq = (vlan_tci & VLAN_PRIO_MASK) >> VLAN_PRIO_SHIFT;
1428 }
1429 return txq;
1430 }
1431#endif /* CONFIG_CHELSIO_T4_DCB */
1432
1433 if (select_queue) {
1434 txq = (skb_rx_queue_recorded(skb)
1435 ? skb_get_rx_queue(skb)
1436 : smp_processor_id());
1437
1438 while (unlikely(txq >= dev->real_num_tx_queues))
1439 txq -= dev->real_num_tx_queues;
1440
1441 return txq;
1442 }
1443
1444 return fallback(dev, skb) % dev->real_num_tx_queues;
1445}
1446
b8ff05a9
DM		 1447static inline int is_offload(const struct adapter *adap)
1448{
1449 return adap->params.offload;
1450}
1451
1452/*
1453 * Implementation of ethtool operations.
1454 */
1455
1456static u32 get_msglevel(struct net_device *dev)
1457{
1458 return netdev2adap(dev)->msg_enable;
1459}
1460
1461static void set_msglevel(struct net_device *dev, u32 val)
1462{
1463 netdev2adap(dev)->msg_enable = val;
1464}
1465
1466static char stats_strings[][ETH_GSTRING_LEN] = {
1467 "TxOctetsOK ",
1468 "TxFramesOK ",
1469 "TxBroadcastFrames ",
1470 "TxMulticastFrames ",
1471 "TxUnicastFrames ",
1472 "TxErrorFrames ",
1473
1474 "TxFrames64 ",
1475 "TxFrames65To127 ",
1476 "TxFrames128To255 ",
1477 "TxFrames256To511 ",
1478 "TxFrames512To1023 ",
1479 "TxFrames1024To1518 ",
1480 "TxFrames1519ToMax ",
1481
1482 "TxFramesDropped ",
1483 "TxPauseFrames ",
1484 "TxPPP0Frames ",
1485 "TxPPP1Frames ",
1486 "TxPPP2Frames ",
1487 "TxPPP3Frames ",
1488 "TxPPP4Frames ",
1489 "TxPPP5Frames ",
1490 "TxPPP6Frames ",
1491 "TxPPP7Frames ",
1492
1493 "RxOctetsOK ",
1494 "RxFramesOK ",
1495 "RxBroadcastFrames ",
1496 "RxMulticastFrames ",
1497 "RxUnicastFrames ",
1498
1499 "RxFramesTooLong ",
1500 "RxJabberErrors ",
1501 "RxFCSErrors ",
1502 "RxLengthErrors ",
1503 "RxSymbolErrors ",
1504 "RxRuntFrames ",
1505
1506 "RxFrames64 ",
1507 "RxFrames65To127 ",
1508 "RxFrames128To255 ",
1509 "RxFrames256To511 ",
1510 "RxFrames512To1023 ",
1511 "RxFrames1024To1518 ",
1512 "RxFrames1519ToMax ",
1513
1514 "RxPauseFrames ",
1515 "RxPPP0Frames ",
1516 "RxPPP1Frames ",
1517 "RxPPP2Frames ",
1518 "RxPPP3Frames ",
1519 "RxPPP4Frames ",
1520 "RxPPP5Frames ",
1521 "RxPPP6Frames ",
1522 "RxPPP7Frames ",
1523
1524 "RxBG0FramesDropped ",
1525 "RxBG1FramesDropped ",
1526 "RxBG2FramesDropped ",
1527 "RxBG3FramesDropped ",
1528 "RxBG0FramesTrunc ",
1529 "RxBG1FramesTrunc ",
1530 "RxBG2FramesTrunc ",
1531 "RxBG3FramesTrunc ",
1532
1533 "TSO ",
1534 "TxCsumOffload ",
1535 "RxCsumGood ",
1536 "VLANextractions ",
1537 "VLANinsertions ",
4a6346d4
DM		 1538 "GROpackets ",
1539 "GROmerged ",
22adfe0a
SR		 1540 "WriteCoalSuccess ",
1541 "WriteCoalFail ",
b8ff05a9
DM		 1542};
1543
1544static int get_sset_count(struct net_device *dev, int sset)
1545{
1546 switch (sset) {
1547 case ETH_SS_STATS:
1548 return ARRAY_SIZE(stats_strings);
1549 default:
1550 return -EOPNOTSUPP;
1551 }
1552}
1553
1554#define T4_REGMAP_SIZE (160 * 1024)
251f9e88 1555#define T5_REGMAP_SIZE (332 * 1024)
b8ff05a9
DM		 1556
1557static int get_regs_len(struct net_device *dev)
1558{
251f9e88 1559 struct adapter *adap = netdev2adap(dev);
d14807dd 1560 if (is_t4(adap->params.chip))
251f9e88
SR		 1561 return T4_REGMAP_SIZE;
1562 else
1563 return T5_REGMAP_SIZE;
b8ff05a9
DM		 1564}
1565
1566static int get_eeprom_len(struct net_device *dev)
1567{
1568 return EEPROMSIZE;
1569}
1570
1571static void get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
1572{
1573 struct adapter *adapter = netdev2adap(dev);
1574
23020ab3
RJ		 1575 strlcpy(info->driver, KBUILD_MODNAME, sizeof(info->driver));
1576 strlcpy(info->version, DRV_VERSION, sizeof(info->version));
1577 strlcpy(info->bus_info, pci_name(adapter->pdev),
1578 sizeof(info->bus_info));
b8ff05a9 1579
84b40501 1580 if (adapter->params.fw_vers)
b8ff05a9
DM		 1581 snprintf(info->fw_version, sizeof(info->fw_version),
1582 "%u.%u.%u.%u, TP %u.%u.%u.%u",
1583 FW_HDR_FW_VER_MAJOR_GET(adapter->params.fw_vers),
1584 FW_HDR_FW_VER_MINOR_GET(adapter->params.fw_vers),
1585 FW_HDR_FW_VER_MICRO_GET(adapter->params.fw_vers),
1586 FW_HDR_FW_VER_BUILD_GET(adapter->params.fw_vers),
1587 FW_HDR_FW_VER_MAJOR_GET(adapter->params.tp_vers),
1588 FW_HDR_FW_VER_MINOR_GET(adapter->params.tp_vers),
1589 FW_HDR_FW_VER_MICRO_GET(adapter->params.tp_vers),
1590 FW_HDR_FW_VER_BUILD_GET(adapter->params.tp_vers));
1591}
1592
1593static void get_strings(struct net_device *dev, u32 stringset, u8 *data)
1594{
1595 if (stringset == ETH_SS_STATS)
1596 memcpy(data, stats_strings, sizeof(stats_strings));
1597}
1598
1599/*
1600 * port stats maintained per queue of the port. They should be in the same
1601 * order as in stats_strings above.
1602 */
1603struct queue_port_stats {
1604 u64 tso;
1605 u64 tx_csum;
1606 u64 rx_csum;
1607 u64 vlan_ex;
1608 u64 vlan_ins;
4a6346d4
DM		 1609 u64 gro_pkts;
1610 u64 gro_merged;
b8ff05a9
DM		 1611};
1612
1613static void collect_sge_port_stats(const struct adapter *adap,
1614 const struct port_info *p, struct queue_port_stats *s)
1615{
1616 int i;
1617 const struct sge_eth_txq *tx = &adap->sge.ethtxq[p->first_qset];
1618 const struct sge_eth_rxq *rx = &adap->sge.ethrxq[p->first_qset];
1619
1620 memset(s, 0, sizeof(*s));
1621 for (i = 0; i < p->nqsets; i++, rx++, tx++) {
1622 s->tso += tx->tso;
1623 s->tx_csum += tx->tx_cso;
1624 s->rx_csum += rx->stats.rx_cso;
1625 s->vlan_ex += rx->stats.vlan_ex;
1626 s->vlan_ins += tx->vlan_ins;
4a6346d4
DM		 1627 s->gro_pkts += rx->stats.lro_pkts;
1628 s->gro_merged += rx->stats.lro_merged;
b8ff05a9
DM		 1629 }
1630}
1631
1632static void get_stats(struct net_device *dev, struct ethtool_stats *stats,
1633 u64 *data)
1634{
1635 struct port_info *pi = netdev_priv(dev);
1636 struct adapter *adapter = pi->adapter;
22adfe0a 1637 u32 val1, val2;
b8ff05a9
DM		 1638
1639 t4_get_port_stats(adapter, pi->tx_chan, (struct port_stats *)data);
1640
1641 data += sizeof(struct port_stats) / sizeof(u64);
1642 collect_sge_port_stats(adapter, pi, (struct queue_port_stats *)data);
22adfe0a 1643 data += sizeof(struct queue_port_stats) / sizeof(u64);
d14807dd 1644 if (!is_t4(adapter->params.chip)) {
22adfe0a
SR		 1645 t4_write_reg(adapter, SGE_STAT_CFG, STATSOURCE_T5(7));
1646 val1 = t4_read_reg(adapter, SGE_STAT_TOTAL);
1647 val2 = t4_read_reg(adapter, SGE_STAT_MATCH);
1648 *data = val1 - val2;
1649 data++;
1650 *data = val2;
1651 data++;
1652 } else {
1653 memset(data, 0, 2 * sizeof(u64));
1654 *data += 2;
1655 }
b8ff05a9
DM		 1656}
1657
1658/*
1659 * Return a version number to identify the type of adapter. The scheme is:
1660 * - bits 0..9: chip version
1661 * - bits 10..15: chip revision
835bb606 1662 * - bits 16..23: register dump version
b8ff05a9
DM		 1663 */
1664static inline unsigned int mk_adap_vers(const struct adapter *ap)
1665{
d14807dd
HS		 1666 return CHELSIO_CHIP_VERSION(ap->params.chip) |
1667 (CHELSIO_CHIP_RELEASE(ap->params.chip) << 10) | (1 << 16);
b8ff05a9
DM		 1668}
1669
1670static void reg_block_dump(struct adapter *ap, void *buf, unsigned int start,
1671 unsigned int end)
1672{
1673 u32 *p = buf + start;
1674
1675 for ( ; start <= end; start += sizeof(u32))
1676 *p++ = t4_read_reg(ap, start);
1677}
1678
1679static void get_regs(struct net_device *dev, struct ethtool_regs *regs,
1680 void *buf)
1681{
251f9e88 1682 static const unsigned int t4_reg_ranges[] = {
b8ff05a9
DM		 1683 0x1008, 0x1108,
1684 0x1180, 0x11b4,
1685 0x11fc, 0x123c,
1686 0x1300, 0x173c,
1687 0x1800, 0x18fc,
1688 0x3000, 0x30d8,
1689 0x30e0, 0x5924,
1690 0x5960, 0x59d4,
1691 0x5a00, 0x5af8,
1692 0x6000, 0x6098,
1693 0x6100, 0x6150,
1694 0x6200, 0x6208,
1695 0x6240, 0x6248,
1696 0x6280, 0x6338,
1697 0x6370, 0x638c,
1698 0x6400, 0x643c,
1699 0x6500, 0x6524,
1700 0x6a00, 0x6a38,
1701 0x6a60, 0x6a78,
1702 0x6b00, 0x6b84,
1703 0x6bf0, 0x6c84,
1704 0x6cf0, 0x6d84,
1705 0x6df0, 0x6e84,
1706 0x6ef0, 0x6f84,
1707 0x6ff0, 0x7084,
1708 0x70f0, 0x7184,
1709 0x71f0, 0x7284,
1710 0x72f0, 0x7384,
1711 0x73f0, 0x7450,
1712 0x7500, 0x7530,
1713 0x7600, 0x761c,
1714 0x7680, 0x76cc,
1715 0x7700, 0x7798,
1716 0x77c0, 0x77fc,
1717 0x7900, 0x79fc,
1718 0x7b00, 0x7c38,
1719 0x7d00, 0x7efc,
1720 0x8dc0, 0x8e1c,
1721 0x8e30, 0x8e78,
1722 0x8ea0, 0x8f6c,
1723 0x8fc0, 0x9074,
1724 0x90fc, 0x90fc,
1725 0x9400, 0x9458,
1726 0x9600, 0x96bc,
1727 0x9800, 0x9808,
1728 0x9820, 0x983c,
1729 0x9850, 0x9864,
1730 0x9c00, 0x9c6c,
1731 0x9c80, 0x9cec,
1732 0x9d00, 0x9d6c,
1733 0x9d80, 0x9dec,
1734 0x9e00, 0x9e6c,
1735 0x9e80, 0x9eec,
1736 0x9f00, 0x9f6c,
1737 0x9f80, 0x9fec,
1738 0xd004, 0xd03c,
1739 0xdfc0, 0xdfe0,
1740 0xe000, 0xea7c,
1741 0xf000, 0x11190,
835bb606
DM		 1742 0x19040, 0x1906c,
1743 0x19078, 0x19080,
1744 0x1908c, 0x19124,
b8ff05a9
DM		 1745 0x19150, 0x191b0,
1746 0x191d0, 0x191e8,
1747 0x19238, 0x1924c,
1748 0x193f8, 0x19474,
1749 0x19490, 0x194f8,
1750 0x19800, 0x19f30,
1751 0x1a000, 0x1a06c,
1752 0x1a0b0, 0x1a120,
1753 0x1a128, 0x1a138,
1754 0x1a190, 0x1a1c4,
1755 0x1a1fc, 0x1a1fc,
1756 0x1e040, 0x1e04c,
835bb606 1757 0x1e284, 0x1e28c,
b8ff05a9
DM		 1758 0x1e2c0, 0x1e2c0,
1759 0x1e2e0, 0x1e2e0,
1760 0x1e300, 0x1e384,
1761 0x1e3c0, 0x1e3c8,
1762 0x1e440, 0x1e44c,
835bb606 1763 0x1e684, 0x1e68c,
b8ff05a9
DM		 1764 0x1e6c0, 0x1e6c0,
1765 0x1e6e0, 0x1e6e0,
1766 0x1e700, 0x1e784,
1767 0x1e7c0, 0x1e7c8,
1768 0x1e840, 0x1e84c,
835bb606 1769 0x1ea84, 0x1ea8c,
b8ff05a9
DM		 1770 0x1eac0, 0x1eac0,
1771 0x1eae0, 0x1eae0,
1772 0x1eb00, 0x1eb84,
1773 0x1ebc0, 0x1ebc8,
1774 0x1ec40, 0x1ec4c,
835bb606 1775 0x1ee84, 0x1ee8c,
b8ff05a9
DM		 1776 0x1eec0, 0x1eec0,
1777 0x1eee0, 0x1eee0,
1778 0x1ef00, 0x1ef84,
1779 0x1efc0, 0x1efc8,
1780 0x1f040, 0x1f04c,
835bb606 1781 0x1f284, 0x1f28c,
b8ff05a9
DM		 1782 0x1f2c0, 0x1f2c0,
1783 0x1f2e0, 0x1f2e0,
1784 0x1f300, 0x1f384,
1785 0x1f3c0, 0x1f3c8,
1786 0x1f440, 0x1f44c,
835bb606 1787 0x1f684, 0x1f68c,
b8ff05a9
DM		 1788 0x1f6c0, 0x1f6c0,
1789 0x1f6e0, 0x1f6e0,
1790 0x1f700, 0x1f784,
1791 0x1f7c0, 0x1f7c8,
1792 0x1f840, 0x1f84c,
835bb606 1793 0x1fa84, 0x1fa8c,
b8ff05a9
DM		 1794 0x1fac0, 0x1fac0,
1795 0x1fae0, 0x1fae0,
1796 0x1fb00, 0x1fb84,
1797 0x1fbc0, 0x1fbc8,
1798 0x1fc40, 0x1fc4c,
835bb606 1799 0x1fe84, 0x1fe8c,
b8ff05a9
DM		 1800 0x1fec0, 0x1fec0,
1801 0x1fee0, 0x1fee0,
1802 0x1ff00, 0x1ff84,
1803 0x1ffc0, 0x1ffc8,
1804 0x20000, 0x2002c,
1805 0x20100, 0x2013c,
1806 0x20190, 0x201c8,
1807 0x20200, 0x20318,
1808 0x20400, 0x20528,
1809 0x20540, 0x20614,
1810 0x21000, 0x21040,
1811 0x2104c, 0x21060,
1812 0x210c0, 0x210ec,
1813 0x21200, 0x21268,
1814 0x21270, 0x21284,
1815 0x212fc, 0x21388,
1816 0x21400, 0x21404,
1817 0x21500, 0x21518,
1818 0x2152c, 0x2153c,
1819 0x21550, 0x21554,
1820 0x21600, 0x21600,
1821 0x21608, 0x21628,
1822 0x21630, 0x2163c,
1823 0x21700, 0x2171c,
1824 0x21780, 0x2178c,
1825 0x21800, 0x21c38,
1826 0x21c80, 0x21d7c,
1827 0x21e00, 0x21e04,
1828 0x22000, 0x2202c,
1829 0x22100, 0x2213c,
1830 0x22190, 0x221c8,
1831 0x22200, 0x22318,
1832 0x22400, 0x22528,
1833 0x22540, 0x22614,
1834 0x23000, 0x23040,
1835 0x2304c, 0x23060,
1836 0x230c0, 0x230ec,
1837 0x23200, 0x23268,
1838 0x23270, 0x23284,
1839 0x232fc, 0x23388,
1840 0x23400, 0x23404,
1841 0x23500, 0x23518,
1842 0x2352c, 0x2353c,
1843 0x23550, 0x23554,
1844 0x23600, 0x23600,
1845 0x23608, 0x23628,
1846 0x23630, 0x2363c,
1847 0x23700, 0x2371c,
1848 0x23780, 0x2378c,
1849 0x23800, 0x23c38,
1850 0x23c80, 0x23d7c,
1851 0x23e00, 0x23e04,
1852 0x24000, 0x2402c,
1853 0x24100, 0x2413c,
1854 0x24190, 0x241c8,
1855 0x24200, 0x24318,
1856 0x24400, 0x24528,
1857 0x24540, 0x24614,
1858 0x25000, 0x25040,
1859 0x2504c, 0x25060,
1860 0x250c0, 0x250ec,
1861 0x25200, 0x25268,
1862 0x25270, 0x25284,
1863 0x252fc, 0x25388,
1864 0x25400, 0x25404,
1865 0x25500, 0x25518,
1866 0x2552c, 0x2553c,
1867 0x25550, 0x25554,
1868 0x25600, 0x25600,
1869 0x25608, 0x25628,
1870 0x25630, 0x2563c,
1871 0x25700, 0x2571c,
1872 0x25780, 0x2578c,
1873 0x25800, 0x25c38,
1874 0x25c80, 0x25d7c,
1875 0x25e00, 0x25e04,
1876 0x26000, 0x2602c,
1877 0x26100, 0x2613c,
1878 0x26190, 0x261c8,
1879 0x26200, 0x26318,
1880 0x26400, 0x26528,
1881 0x26540, 0x26614,
1882 0x27000, 0x27040,
1883 0x2704c, 0x27060,
1884 0x270c0, 0x270ec,
1885 0x27200, 0x27268,
1886 0x27270, 0x27284,
1887 0x272fc, 0x27388,
1888 0x27400, 0x27404,
1889 0x27500, 0x27518,
1890 0x2752c, 0x2753c,
1891 0x27550, 0x27554,
1892 0x27600, 0x27600,
1893 0x27608, 0x27628,
1894 0x27630, 0x2763c,
1895 0x27700, 0x2771c,
1896 0x27780, 0x2778c,
1897 0x27800, 0x27c38,
1898 0x27c80, 0x27d7c,
1899 0x27e00, 0x27e04
1900 };
1901
251f9e88
SR		 1902 static const unsigned int t5_reg_ranges[] = {
1903 0x1008, 0x1148,
1904 0x1180, 0x11b4,
1905 0x11fc, 0x123c,
1906 0x1280, 0x173c,
1907 0x1800, 0x18fc,
1908 0x3000, 0x3028,
1909 0x3060, 0x30d8,
1910 0x30e0, 0x30fc,
1911 0x3140, 0x357c,
1912 0x35a8, 0x35cc,
1913 0x35ec, 0x35ec,
1914 0x3600, 0x5624,
1915 0x56cc, 0x575c,
1916 0x580c, 0x5814,
1917 0x5890, 0x58bc,
1918 0x5940, 0x59dc,
1919 0x59fc, 0x5a18,
1920 0x5a60, 0x5a9c,
1921 0x5b9c, 0x5bfc,
1922 0x6000, 0x6040,
1923 0x6058, 0x614c,
1924 0x7700, 0x7798,
1925 0x77c0, 0x78fc,
1926 0x7b00, 0x7c54,
1927 0x7d00, 0x7efc,
1928 0x8dc0, 0x8de0,
1929 0x8df8, 0x8e84,
1930 0x8ea0, 0x8f84,
1931 0x8fc0, 0x90f8,
1932 0x9400, 0x9470,
1933 0x9600, 0x96f4,
1934 0x9800, 0x9808,
1935 0x9820, 0x983c,
1936 0x9850, 0x9864,
1937 0x9c00, 0x9c6c,
1938 0x9c80, 0x9cec,
1939 0x9d00, 0x9d6c,
1940 0x9d80, 0x9dec,
1941 0x9e00, 0x9e6c,
1942 0x9e80, 0x9eec,
1943 0x9f00, 0x9f6c,
1944 0x9f80, 0xa020,
1945 0xd004, 0xd03c,
1946 0xdfc0, 0xdfe0,
1947 0xe000, 0x11088,
1948 0x1109c, 0x1117c,
1949 0x11190, 0x11204,
1950 0x19040, 0x1906c,
1951 0x19078, 0x19080,
1952 0x1908c, 0x19124,
1953 0x19150, 0x191b0,
1954 0x191d0, 0x191e8,
1955 0x19238, 0x19290,
1956 0x193f8, 0x19474,
1957 0x19490, 0x194cc,
1958 0x194f0, 0x194f8,
1959 0x19c00, 0x19c60,
1960 0x19c94, 0x19e10,
1961 0x19e50, 0x19f34,
1962 0x19f40, 0x19f50,
1963 0x19f90, 0x19fe4,
1964 0x1a000, 0x1a06c,
1965 0x1a0b0, 0x1a120,
1966 0x1a128, 0x1a138,
1967 0x1a190, 0x1a1c4,
1968 0x1a1fc, 0x1a1fc,
1969 0x1e008, 0x1e00c,
1970 0x1e040, 0x1e04c,
1971 0x1e284, 0x1e290,
1972 0x1e2c0, 0x1e2c0,
1973 0x1e2e0, 0x1e2e0,
1974 0x1e300, 0x1e384,
1975 0x1e3c0, 0x1e3c8,
1976 0x1e408, 0x1e40c,
1977 0x1e440, 0x1e44c,
1978 0x1e684, 0x1e690,
1979 0x1e6c0, 0x1e6c0,
1980 0x1e6e0, 0x1e6e0,
1981 0x1e700, 0x1e784,
1982 0x1e7c0, 0x1e7c8,
1983 0x1e808, 0x1e80c,
1984 0x1e840, 0x1e84c,
1985 0x1ea84, 0x1ea90,
1986 0x1eac0, 0x1eac0,
1987 0x1eae0, 0x1eae0,
1988 0x1eb00, 0x1eb84,
1989 0x1ebc0, 0x1ebc8,
1990 0x1ec08, 0x1ec0c,
1991 0x1ec40, 0x1ec4c,
1992 0x1ee84, 0x1ee90,
1993 0x1eec0, 0x1eec0,
1994 0x1eee0, 0x1eee0,
1995 0x1ef00, 0x1ef84,
1996 0x1efc0, 0x1efc8,
1997 0x1f008, 0x1f00c,
1998 0x1f040, 0x1f04c,
1999 0x1f284, 0x1f290,
2000 0x1f2c0, 0x1f2c0,
2001 0x1f2e0, 0x1f2e0,
2002 0x1f300, 0x1f384,
2003 0x1f3c0, 0x1f3c8,
2004 0x1f408, 0x1f40c,
2005 0x1f440, 0x1f44c,
2006 0x1f684, 0x1f690,
2007 0x1f6c0, 0x1f6c0,
2008 0x1f6e0, 0x1f6e0,
2009 0x1f700, 0x1f784,
2010 0x1f7c0, 0x1f7c8,
2011 0x1f808, 0x1f80c,
2012 0x1f840, 0x1f84c,
2013 0x1fa84, 0x1fa90,
2014 0x1fac0, 0x1fac0,
2015 0x1fae0, 0x1fae0,
2016 0x1fb00, 0x1fb84,
2017 0x1fbc0, 0x1fbc8,
2018 0x1fc08, 0x1fc0c,
2019 0x1fc40, 0x1fc4c,
2020 0x1fe84, 0x1fe90,
2021 0x1fec0, 0x1fec0,
2022 0x1fee0, 0x1fee0,
2023 0x1ff00, 0x1ff84,
2024 0x1ffc0, 0x1ffc8,
2025 0x30000, 0x30030,
2026 0x30100, 0x30144,
2027 0x30190, 0x301d0,
2028 0x30200, 0x30318,
2029 0x30400, 0x3052c,
2030 0x30540, 0x3061c,
2031 0x30800, 0x30834,
2032 0x308c0, 0x30908,
2033 0x30910, 0x309ac,
2034 0x30a00, 0x30a04,
2035 0x30a0c, 0x30a2c,
2036 0x30a44, 0x30a50,
2037 0x30a74, 0x30c24,
2038 0x30d08, 0x30d14,
2039 0x30d1c, 0x30d20,
2040 0x30d3c, 0x30d50,
2041 0x31200, 0x3120c,
2042 0x31220, 0x31220,
2043 0x31240, 0x31240,
2044 0x31600, 0x31600,
2045 0x31608, 0x3160c,
2046 0x31a00, 0x31a1c,
2047 0x31e04, 0x31e20,
2048 0x31e38, 0x31e3c,
2049 0x31e80, 0x31e80,
2050 0x31e88, 0x31ea8,
2051 0x31eb0, 0x31eb4,
2052 0x31ec8, 0x31ed4,
2053 0x31fb8, 0x32004,
2054 0x32208, 0x3223c,
2055 0x32600, 0x32630,
2056 0x32a00, 0x32abc,
2057 0x32b00, 0x32b70,
2058 0x33000, 0x33048,
2059 0x33060, 0x3309c,
2060 0x330f0, 0x33148,
2061 0x33160, 0x3319c,
2062 0x331f0, 0x332e4,
2063 0x332f8, 0x333e4,
2064 0x333f8, 0x33448,
2065 0x33460, 0x3349c,
2066 0x334f0, 0x33548,
2067 0x33560, 0x3359c,
2068 0x335f0, 0x336e4,
2069 0x336f8, 0x337e4,
2070 0x337f8, 0x337fc,
2071 0x33814, 0x33814,
2072 0x3382c, 0x3382c,
2073 0x33880, 0x3388c,
2074 0x338e8, 0x338ec,
2075 0x33900, 0x33948,
2076 0x33960, 0x3399c,
2077 0x339f0, 0x33ae4,
2078 0x33af8, 0x33b10,
2079 0x33b28, 0x33b28,
2080 0x33b3c, 0x33b50,
2081 0x33bf0, 0x33c10,
2082 0x33c28, 0x33c28,
2083 0x33c3c, 0x33c50,
2084 0x33cf0, 0x33cfc,
2085 0x34000, 0x34030,
2086 0x34100, 0x34144,
2087 0x34190, 0x341d0,
2088 0x34200, 0x34318,
2089 0x34400, 0x3452c,
2090 0x34540, 0x3461c,
2091 0x34800, 0x34834,
2092 0x348c0, 0x34908,
2093 0x34910, 0x349ac,
2094 0x34a00, 0x34a04,
2095 0x34a0c, 0x34a2c,
2096 0x34a44, 0x34a50,
2097 0x34a74, 0x34c24,
2098 0x34d08, 0x34d14,
2099 0x34d1c, 0x34d20,
2100 0x34d3c, 0x34d50,
2101 0x35200, 0x3520c,
2102 0x35220, 0x35220,
2103 0x35240, 0x35240,
2104 0x35600, 0x35600,
2105 0x35608, 0x3560c,
2106 0x35a00, 0x35a1c,
2107 0x35e04, 0x35e20,
2108 0x35e38, 0x35e3c,
2109 0x35e80, 0x35e80,
2110 0x35e88, 0x35ea8,
2111 0x35eb0, 0x35eb4,
2112 0x35ec8, 0x35ed4,
2113 0x35fb8, 0x36004,
2114 0x36208, 0x3623c,
2115 0x36600, 0x36630,
2116 0x36a00, 0x36abc,
2117 0x36b00, 0x36b70,
2118 0x37000, 0x37048,
2119 0x37060, 0x3709c,
2120 0x370f0, 0x37148,
2121 0x37160, 0x3719c,
2122 0x371f0, 0x372e4,
2123 0x372f8, 0x373e4,
2124 0x373f8, 0x37448,
2125 0x37460, 0x3749c,
2126 0x374f0, 0x37548,
2127 0x37560, 0x3759c,
2128 0x375f0, 0x376e4,
2129 0x376f8, 0x377e4,
2130 0x377f8, 0x377fc,
2131 0x37814, 0x37814,
2132 0x3782c, 0x3782c,
2133 0x37880, 0x3788c,
2134 0x378e8, 0x378ec,
2135 0x37900, 0x37948,
2136 0x37960, 0x3799c,
2137 0x379f0, 0x37ae4,
2138 0x37af8, 0x37b10,
2139 0x37b28, 0x37b28,
2140 0x37b3c, 0x37b50,
2141 0x37bf0, 0x37c10,
2142 0x37c28, 0x37c28,
2143 0x37c3c, 0x37c50,
2144 0x37cf0, 0x37cfc,
2145 0x38000, 0x38030,
2146 0x38100, 0x38144,
2147 0x38190, 0x381d0,
2148 0x38200, 0x38318,
2149 0x38400, 0x3852c,
2150 0x38540, 0x3861c,
2151 0x38800, 0x38834,
2152 0x388c0, 0x38908,
2153 0x38910, 0x389ac,
2154 0x38a00, 0x38a04,
2155 0x38a0c, 0x38a2c,
2156 0x38a44, 0x38a50,
2157 0x38a74, 0x38c24,
2158 0x38d08, 0x38d14,
2159 0x38d1c, 0x38d20,
2160 0x38d3c, 0x38d50,
2161 0x39200, 0x3920c,
2162 0x39220, 0x39220,
2163 0x39240, 0x39240,
2164 0x39600, 0x39600,
2165 0x39608, 0x3960c,
2166 0x39a00, 0x39a1c,
2167 0x39e04, 0x39e20,
2168 0x39e38, 0x39e3c,
2169 0x39e80, 0x39e80,
2170 0x39e88, 0x39ea8,
2171 0x39eb0, 0x39eb4,
2172 0x39ec8, 0x39ed4,
2173 0x39fb8, 0x3a004,
2174 0x3a208, 0x3a23c,
2175 0x3a600, 0x3a630,
2176 0x3aa00, 0x3aabc,
2177 0x3ab00, 0x3ab70,
2178 0x3b000, 0x3b048,
2179 0x3b060, 0x3b09c,
2180 0x3b0f0, 0x3b148,
2181 0x3b160, 0x3b19c,
2182 0x3b1f0, 0x3b2e4,
2183 0x3b2f8, 0x3b3e4,
2184 0x3b3f8, 0x3b448,
2185 0x3b460, 0x3b49c,
2186 0x3b4f0, 0x3b548,
2187 0x3b560, 0x3b59c,
2188 0x3b5f0, 0x3b6e4,
2189 0x3b6f8, 0x3b7e4,
2190 0x3b7f8, 0x3b7fc,
2191 0x3b814, 0x3b814,
2192 0x3b82c, 0x3b82c,
2193 0x3b880, 0x3b88c,
2194 0x3b8e8, 0x3b8ec,
2195 0x3b900, 0x3b948,
2196 0x3b960, 0x3b99c,
2197 0x3b9f0, 0x3bae4,
2198 0x3baf8, 0x3bb10,
2199 0x3bb28, 0x3bb28,
2200 0x3bb3c, 0x3bb50,
2201 0x3bbf0, 0x3bc10,
2202 0x3bc28, 0x3bc28,
2203 0x3bc3c, 0x3bc50,
2204 0x3bcf0, 0x3bcfc,
2205 0x3c000, 0x3c030,
2206 0x3c100, 0x3c144,
2207 0x3c190, 0x3c1d0,
2208 0x3c200, 0x3c318,
2209 0x3c400, 0x3c52c,
2210 0x3c540, 0x3c61c,
2211 0x3c800, 0x3c834,
2212 0x3c8c0, 0x3c908,
2213 0x3c910, 0x3c9ac,
2214 0x3ca00, 0x3ca04,
2215 0x3ca0c, 0x3ca2c,
2216 0x3ca44, 0x3ca50,
2217 0x3ca74, 0x3cc24,
2218 0x3cd08, 0x3cd14,
2219 0x3cd1c, 0x3cd20,
2220 0x3cd3c, 0x3cd50,
2221 0x3d200, 0x3d20c,
2222 0x3d220, 0x3d220,
2223 0x3d240, 0x3d240,
2224 0x3d600, 0x3d600,
2225 0x3d608, 0x3d60c,
2226 0x3da00, 0x3da1c,
2227 0x3de04, 0x3de20,
2228 0x3de38, 0x3de3c,
2229 0x3de80, 0x3de80,
2230 0x3de88, 0x3dea8,
2231 0x3deb0, 0x3deb4,
2232 0x3dec8, 0x3ded4,
2233 0x3dfb8, 0x3e004,
2234 0x3e208, 0x3e23c,
2235 0x3e600, 0x3e630,
2236 0x3ea00, 0x3eabc,
2237 0x3eb00, 0x3eb70,
2238 0x3f000, 0x3f048,
2239 0x3f060, 0x3f09c,
2240 0x3f0f0, 0x3f148,
2241 0x3f160, 0x3f19c,
2242 0x3f1f0, 0x3f2e4,
2243 0x3f2f8, 0x3f3e4,
2244 0x3f3f8, 0x3f448,
2245 0x3f460, 0x3f49c,
2246 0x3f4f0, 0x3f548,
2247 0x3f560, 0x3f59c,
2248 0x3f5f0, 0x3f6e4,
2249 0x3f6f8, 0x3f7e4,
2250 0x3f7f8, 0x3f7fc,
2251 0x3f814, 0x3f814,
2252 0x3f82c, 0x3f82c,
2253 0x3f880, 0x3f88c,
2254 0x3f8e8, 0x3f8ec,
2255 0x3f900, 0x3f948,
2256 0x3f960, 0x3f99c,
2257 0x3f9f0, 0x3fae4,
2258 0x3faf8, 0x3fb10,
2259 0x3fb28, 0x3fb28,
2260 0x3fb3c, 0x3fb50,
2261 0x3fbf0, 0x3fc10,
2262 0x3fc28, 0x3fc28,
2263 0x3fc3c, 0x3fc50,
2264 0x3fcf0, 0x3fcfc,
2265 0x40000, 0x4000c,
2266 0x40040, 0x40068,
2267 0x40080, 0x40144,
2268 0x40180, 0x4018c,
2269 0x40200, 0x40298,
2270 0x402ac, 0x4033c,
2271 0x403f8, 0x403fc,
c1f49e3e 2272 0x41304, 0x413c4,
251f9e88
SR		 2273 0x41400, 0x4141c,
2274 0x41480, 0x414d0,
2275 0x44000, 0x44078,
2276 0x440c0, 0x44278,
2277 0x442c0, 0x44478,
2278 0x444c0, 0x44678,
2279 0x446c0, 0x44878,
2280 0x448c0, 0x449fc,
2281 0x45000, 0x45068,
2282 0x45080, 0x45084,
2283 0x450a0, 0x450b0,
2284 0x45200, 0x45268,
2285 0x45280, 0x45284,
2286 0x452a0, 0x452b0,
2287 0x460c0, 0x460e4,
2288 0x47000, 0x4708c,
2289 0x47200, 0x47250,
2290 0x47400, 0x47420,
2291 0x47600, 0x47618,
2292 0x47800, 0x47814,
2293 0x48000, 0x4800c,
2294 0x48040, 0x48068,
2295 0x48080, 0x48144,
2296 0x48180, 0x4818c,
2297 0x48200, 0x48298,
2298 0x482ac, 0x4833c,
2299 0x483f8, 0x483fc,
c1f49e3e 2300 0x49304, 0x493c4,
251f9e88
SR		 2301 0x49400, 0x4941c,
2302 0x49480, 0x494d0,
2303 0x4c000, 0x4c078,
2304 0x4c0c0, 0x4c278,
2305 0x4c2c0, 0x4c478,
2306 0x4c4c0, 0x4c678,
2307 0x4c6c0, 0x4c878,
2308 0x4c8c0, 0x4c9fc,
2309 0x4d000, 0x4d068,
2310 0x4d080, 0x4d084,
2311 0x4d0a0, 0x4d0b0,
2312 0x4d200, 0x4d268,
2313 0x4d280, 0x4d284,
2314 0x4d2a0, 0x4d2b0,
2315 0x4e0c0, 0x4e0e4,
2316 0x4f000, 0x4f08c,
2317 0x4f200, 0x4f250,
2318 0x4f400, 0x4f420,
2319 0x4f600, 0x4f618,
2320 0x4f800, 0x4f814,
2321 0x50000, 0x500cc,
2322 0x50400, 0x50400,
2323 0x50800, 0x508cc,
2324 0x50c00, 0x50c00,
2325 0x51000, 0x5101c,
2326 0x51300, 0x51308,
2327 };
2328
b8ff05a9
DM		 2329 int i;
2330 struct adapter *ap = netdev2adap(dev);
251f9e88
SR		 2331 static const unsigned int *reg_ranges;
2332 int arr_size = 0, buf_size = 0;
2333
d14807dd 2334 if (is_t4(ap->params.chip)) {
251f9e88
SR		 2335 reg_ranges = &t4_reg_ranges[0];
2336 arr_size = ARRAY_SIZE(t4_reg_ranges);
2337 buf_size = T4_REGMAP_SIZE;
2338 } else {
2339 reg_ranges = &t5_reg_ranges[0];
2340 arr_size = ARRAY_SIZE(t5_reg_ranges);
2341 buf_size = T5_REGMAP_SIZE;
2342 }
b8ff05a9
DM		 2343
2344 regs->version = mk_adap_vers(ap);
2345
251f9e88
SR		 2346 memset(buf, 0, buf_size);
2347 for (i = 0; i < arr_size; i += 2)
b8ff05a9
DM		 2348 reg_block_dump(ap, buf, reg_ranges[i], reg_ranges[i + 1]);
2349}
2350
2351static int restart_autoneg(struct net_device *dev)
2352{
2353 struct port_info *p = netdev_priv(dev);
2354
2355 if (!netif_running(dev))
2356 return -EAGAIN;
2357 if (p->link_cfg.autoneg != AUTONEG_ENABLE)
2358 return -EINVAL;
060e0c75 2359 t4_restart_aneg(p->adapter, p->adapter->fn, p->tx_chan);
b8ff05a9
DM		 2360 return 0;
2361}
2362
c5e06360
DM		 2363static int identify_port(struct net_device *dev,
2364 enum ethtool_phys_id_state state)
b8ff05a9 2365{
c5e06360 2366 unsigned int val;
060e0c75
DM		 2367 struct adapter *adap = netdev2adap(dev);
2368
c5e06360
DM		 2369 if (state == ETHTOOL_ID_ACTIVE)
2370 val = 0xffff;
2371 else if (state == ETHTOOL_ID_INACTIVE)
2372 val = 0;
2373 else
2374 return -EINVAL;
b8ff05a9 2375
c5e06360 2376 return t4_identify_port(adap, adap->fn, netdev2pinfo(dev)->viid, val);
b8ff05a9
DM		 2377}
2378
2379static unsigned int from_fw_linkcaps(unsigned int type, unsigned int caps)
2380{
2381 unsigned int v = 0;
2382
a0881cab
DM		 2383 if (type == FW_PORT_TYPE_BT_SGMII || type == FW_PORT_TYPE_BT_XFI ||
2384 type == FW_PORT_TYPE_BT_XAUI) {
b8ff05a9
DM		 2385 v |= SUPPORTED_TP;
2386 if (caps & FW_PORT_CAP_SPEED_100M)
2387 v |= SUPPORTED_100baseT_Full;
2388 if (caps & FW_PORT_CAP_SPEED_1G)
2389 v |= SUPPORTED_1000baseT_Full;
2390 if (caps & FW_PORT_CAP_SPEED_10G)
2391 v |= SUPPORTED_10000baseT_Full;
2392 } else if (type == FW_PORT_TYPE_KX4 || type == FW_PORT_TYPE_KX) {
2393 v |= SUPPORTED_Backplane;
2394 if (caps & FW_PORT_CAP_SPEED_1G)
2395 v |= SUPPORTED_1000baseKX_Full;
2396 if (caps & FW_PORT_CAP_SPEED_10G)
2397 v |= SUPPORTED_10000baseKX4_Full;
2398 } else if (type == FW_PORT_TYPE_KR)
2399 v |= SUPPORTED_Backplane | SUPPORTED_10000baseKR_Full;
a0881cab 2400 else if (type == FW_PORT_TYPE_BP_AP)
7d5e77aa
DM		 2401 v |= SUPPORTED_Backplane | SUPPORTED_10000baseR_FEC |
2402 SUPPORTED_10000baseKR_Full | SUPPORTED_1000baseKX_Full;
2403 else if (type == FW_PORT_TYPE_BP4_AP)
2404 v |= SUPPORTED_Backplane | SUPPORTED_10000baseR_FEC |
2405 SUPPORTED_10000baseKR_Full | SUPPORTED_1000baseKX_Full |
2406 SUPPORTED_10000baseKX4_Full;
a0881cab
DM		 2407 else if (type == FW_PORT_TYPE_FIBER_XFI ||
2408 type == FW_PORT_TYPE_FIBER_XAUI || type == FW_PORT_TYPE_SFP)
b8ff05a9 2409 v |= SUPPORTED_FIBRE;
72aca4bf
KS		 2410 else if (type == FW_PORT_TYPE_BP40_BA)
2411 v |= SUPPORTED_40000baseSR4_Full;
b8ff05a9
DM		 2412
2413 if (caps & FW_PORT_CAP_ANEG)
2414 v |= SUPPORTED_Autoneg;
2415 return v;
2416}
2417
2418static unsigned int to_fw_linkcaps(unsigned int caps)
2419{
2420 unsigned int v = 0;
2421
2422 if (caps & ADVERTISED_100baseT_Full)
2423 v |= FW_PORT_CAP_SPEED_100M;
2424 if (caps & ADVERTISED_1000baseT_Full)
2425 v |= FW_PORT_CAP_SPEED_1G;
2426 if (caps & ADVERTISED_10000baseT_Full)
2427 v |= FW_PORT_CAP_SPEED_10G;
72aca4bf
KS		 2428 if (caps & ADVERTISED_40000baseSR4_Full)
2429 v |= FW_PORT_CAP_SPEED_40G;
b8ff05a9
DM		 2430 return v;
2431}
2432
2433static int get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2434{
2435 const struct port_info *p = netdev_priv(dev);
2436
2437 if (p->port_type == FW_PORT_TYPE_BT_SGMII ||
a0881cab 2438 p->port_type == FW_PORT_TYPE_BT_XFI ||
b8ff05a9
DM		 2439 p->port_type == FW_PORT_TYPE_BT_XAUI)
2440 cmd->port = PORT_TP;
a0881cab
DM		 2441 else if (p->port_type == FW_PORT_TYPE_FIBER_XFI ||
2442 p->port_type == FW_PORT_TYPE_FIBER_XAUI)
b8ff05a9 2443 cmd->port = PORT_FIBRE;
3e00a509
HS		 2444 else if (p->port_type == FW_PORT_TYPE_SFP ||
2445 p->port_type == FW_PORT_TYPE_QSFP_10G ||
2446 p->port_type == FW_PORT_TYPE_QSFP) {
2447 if (p->mod_type == FW_PORT_MOD_TYPE_LR ||
2448 p->mod_type == FW_PORT_MOD_TYPE_SR ||
2449 p->mod_type == FW_PORT_MOD_TYPE_ER ||
2450 p->mod_type == FW_PORT_MOD_TYPE_LRM)
2451 cmd->port = PORT_FIBRE;
2452 else if (p->mod_type == FW_PORT_MOD_TYPE_TWINAX_PASSIVE ||
2453 p->mod_type == FW_PORT_MOD_TYPE_TWINAX_ACTIVE)
a0881cab
DM		 2454 cmd->port = PORT_DA;
2455 else
3e00a509 2456 cmd->port = PORT_OTHER;
a0881cab 2457 } else
b8ff05a9
DM		 2458 cmd->port = PORT_OTHER;
2459
2460 if (p->mdio_addr >= 0) {
2461 cmd->phy_address = p->mdio_addr;
2462 cmd->transceiver = XCVR_EXTERNAL;
2463 cmd->mdio_support = p->port_type == FW_PORT_TYPE_BT_SGMII ?
2464 MDIO_SUPPORTS_C22 : MDIO_SUPPORTS_C45;
2465 } else {
2466 cmd->phy_address = 0; /* not really, but no better option */
2467 cmd->transceiver = XCVR_INTERNAL;
2468 cmd->mdio_support = 0;
2469 }
2470
2471 cmd->supported = from_fw_linkcaps(p->port_type, p->link_cfg.supported);
2472 cmd->advertising = from_fw_linkcaps(p->port_type,
2473 p->link_cfg.advertising);
70739497
DD		 2474 ethtool_cmd_speed_set(cmd,
2475 netif_carrier_ok(dev) ? p->link_cfg.speed : 0);
b8ff05a9
DM		 2476 cmd->duplex = DUPLEX_FULL;
2477 cmd->autoneg = p->link_cfg.autoneg;
2478 cmd->maxtxpkt = 0;
2479 cmd->maxrxpkt = 0;
2480 return 0;
2481}
2482
2483static unsigned int speed_to_caps(int speed)
2484{
e8b39015 2485 if (speed == 100)
b8ff05a9 2486 return FW_PORT_CAP_SPEED_100M;
e8b39015 2487 if (speed == 1000)
b8ff05a9 2488 return FW_PORT_CAP_SPEED_1G;
e8b39015 2489 if (speed == 10000)
b8ff05a9 2490 return FW_PORT_CAP_SPEED_10G;
e8b39015 2491 if (speed == 40000)
72aca4bf 2492 return FW_PORT_CAP_SPEED_40G;
b8ff05a9
DM		 2493 return 0;
2494}
2495
2496static int set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2497{
2498 unsigned int cap;
2499 struct port_info *p = netdev_priv(dev);
2500 struct link_config *lc = &p->link_cfg;
25db0338 2501 u32 speed = ethtool_cmd_speed(cmd);
b8ff05a9
DM		 2502
2503 if (cmd->duplex != DUPLEX_FULL) /* only full-duplex supported */
2504 return -EINVAL;
2505
2506 if (!(lc->supported & FW_PORT_CAP_ANEG)) {
2507 /*
2508 * PHY offers a single speed. See if that's what's
2509 * being requested.
2510 */
2511 if (cmd->autoneg == AUTONEG_DISABLE &&
25db0338
DD		 2512 (lc->supported & speed_to_caps(speed)))
2513 return 0;
b8ff05a9
DM		 2514 return -EINVAL;
2515 }
2516
2517 if (cmd->autoneg == AUTONEG_DISABLE) {
25db0338 2518 cap = speed_to_caps(speed);
b8ff05a9 2519
72aca4bf 2520 if (!(lc->supported & cap) ||
e8b39015
BH		 2521 (speed == 1000) ||
2522 (speed == 10000) ||
72aca4bf 2523 (speed == 40000))
b8ff05a9
DM		 2524 return -EINVAL;
2525 lc->requested_speed = cap;
2526 lc->advertising = 0;
2527 } else {
2528 cap = to_fw_linkcaps(cmd->advertising);
2529 if (!(lc->supported & cap))
2530 return -EINVAL;
2531 lc->requested_speed = 0;
2532 lc->advertising = cap | FW_PORT_CAP_ANEG;
2533 }
2534 lc->autoneg = cmd->autoneg;
2535
2536 if (netif_running(dev))
060e0c75
DM		 2537 return t4_link_start(p->adapter, p->adapter->fn, p->tx_chan,
2538 lc);
b8ff05a9
DM		 2539 return 0;
2540}
2541
2542static void get_pauseparam(struct net_device *dev,
2543 struct ethtool_pauseparam *epause)
2544{
2545 struct port_info *p = netdev_priv(dev);
2546
2547 epause->autoneg = (p->link_cfg.requested_fc & PAUSE_AUTONEG) != 0;
2548 epause->rx_pause = (p->link_cfg.fc & PAUSE_RX) != 0;
2549 epause->tx_pause = (p->link_cfg.fc & PAUSE_TX) != 0;
2550}
2551
2552static int set_pauseparam(struct net_device *dev,
2553 struct ethtool_pauseparam *epause)
2554{
2555 struct port_info *p = netdev_priv(dev);
2556 struct link_config *lc = &p->link_cfg;
2557
2558 if (epause->autoneg == AUTONEG_DISABLE)
2559 lc->requested_fc = 0;
2560 else if (lc->supported & FW_PORT_CAP_ANEG)
2561 lc->requested_fc = PAUSE_AUTONEG;
2562 else
2563 return -EINVAL;
2564
2565 if (epause->rx_pause)
2566 lc->requested_fc |= PAUSE_RX;
2567 if (epause->tx_pause)
2568 lc->requested_fc |= PAUSE_TX;
2569 if (netif_running(dev))
060e0c75
DM		 2570 return t4_link_start(p->adapter, p->adapter->fn, p->tx_chan,
2571 lc);
b8ff05a9
DM		 2572 return 0;
2573}
2574
b8ff05a9
DM		 2575static void get_sge_param(struct net_device *dev, struct ethtool_ringparam *e)
2576{
2577 const struct port_info *pi = netdev_priv(dev);
2578 const struct sge *s = &pi->adapter->sge;
2579
2580 e->rx_max_pending = MAX_RX_BUFFERS;
2581 e->rx_mini_max_pending = MAX_RSPQ_ENTRIES;
2582 e->rx_jumbo_max_pending = 0;
2583 e->tx_max_pending = MAX_TXQ_ENTRIES;
2584
2585 e->rx_pending = s->ethrxq[pi->first_qset].fl.size - 8;
2586 e->rx_mini_pending = s->ethrxq[pi->first_qset].rspq.size;
2587 e->rx_jumbo_pending = 0;
2588 e->tx_pending = s->ethtxq[pi->first_qset].q.size;
2589}
2590
2591static int set_sge_param(struct net_device *dev, struct ethtool_ringparam *e)
2592{
2593 int i;
2594 const struct port_info *pi = netdev_priv(dev);
2595 struct adapter *adapter = pi->adapter;
2596 struct sge *s = &adapter->sge;
2597
2598 if (e->rx_pending > MAX_RX_BUFFERS || e->rx_jumbo_pending ||
2599 e->tx_pending > MAX_TXQ_ENTRIES ||
2600 e->rx_mini_pending > MAX_RSPQ_ENTRIES ||
2601 e->rx_mini_pending < MIN_RSPQ_ENTRIES ||
2602 e->rx_pending < MIN_FL_ENTRIES || e->tx_pending < MIN_TXQ_ENTRIES)
2603 return -EINVAL;
2604
2605 if (adapter->flags & FULL_INIT_DONE)
2606 return -EBUSY;
2607
2608 for (i = 0; i < pi->nqsets; ++i) {
2609 s->ethtxq[pi->first_qset + i].q.size = e->tx_pending;
2610 s->ethrxq[pi->first_qset + i].fl.size = e->rx_pending + 8;
2611 s->ethrxq[pi->first_qset + i].rspq.size = e->rx_mini_pending;
2612 }
2613 return 0;
2614}
2615
2616static int closest_timer(const struct sge *s, int time)
2617{
2618 int i, delta, match = 0, min_delta = INT_MAX;
2619
2620 for (i = 0; i < ARRAY_SIZE(s->timer_val); i++) {
2621 delta = time - s->timer_val[i];
2622 if (delta < 0)
2623 delta = -delta;
2624 if (delta < min_delta) {
2625 min_delta = delta;
2626 match = i;
2627 }
2628 }
2629 return match;
2630}
2631
2632static int closest_thres(const struct sge *s, int thres)
2633{
2634 int i, delta, match = 0, min_delta = INT_MAX;
2635
2636 for (i = 0; i < ARRAY_SIZE(s->counter_val); i++) {
2637 delta = thres - s->counter_val[i];
2638 if (delta < 0)
2639 delta = -delta;
2640 if (delta < min_delta) {
2641 min_delta = delta;
2642 match = i;
2643 }
2644 }
2645 return match;
2646}
2647
2648/*
2649 * Return a queue's interrupt hold-off time in us. 0 means no timer.
2650 */
2651static unsigned int qtimer_val(const struct adapter *adap,
2652 const struct sge_rspq *q)
2653{
2654 unsigned int idx = q->intr_params >> 1;
2655
2656 return idx < SGE_NTIMERS ? adap->sge.timer_val[idx] : 0;
2657}
2658
2659/**
c887ad0e 2660 * set_rspq_intr_params - set a queue's interrupt holdoff parameters
b8ff05a9
DM		 2661 * @q: the Rx queue
2662 * @us: the hold-off time in us, or 0 to disable timer
2663 * @cnt: the hold-off packet count, or 0 to disable counter
2664 *
2665 * Sets an Rx queue's interrupt hold-off time and packet count. At least
2666 * one of the two needs to be enabled for the queue to generate interrupts.
2667 */
c887ad0e
HS		 2668static int set_rspq_intr_params(struct sge_rspq *q,
2669 unsigned int us, unsigned int cnt)
b8ff05a9 2670{
c887ad0e
HS		 2671 struct adapter *adap = q->adap;
2672
b8ff05a9
DM		 2673 if ((us | cnt) == 0)
2674 cnt = 1;
2675
2676 if (cnt) {
2677 int err;
2678 u32 v, new_idx;
2679
2680 new_idx = closest_thres(&adap->sge, cnt);
2681 if (q->desc && q->pktcnt_idx != new_idx) {
2682 /* the queue has already been created, update it */
2683 v = FW_PARAMS_MNEM(FW_PARAMS_MNEM_DMAQ) |
2684 FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DMAQ_IQ_INTCNTTHRESH) |
2685 FW_PARAMS_PARAM_YZ(q->cntxt_id);
060e0c75
DM		 2686 err = t4_set_params(adap, adap->fn, adap->fn, 0, 1, &v,
2687 &new_idx);
b8ff05a9
DM		 2688 if (err)
2689 return err;
2690 }
2691 q->pktcnt_idx = new_idx;
2692 }
2693
2694 us = us == 0 ? 6 : closest_timer(&adap->sge, us);
2695 q->intr_params = QINTR_TIMER_IDX(us) | (cnt > 0 ? QINTR_CNT_EN : 0);
2696 return 0;
2697}
2698
c887ad0e
HS		 2699/**
2700 * set_rx_intr_params - set a net devices's RX interrupt holdoff paramete!
2701 * @dev: the network device
2702 * @us: the hold-off time in us, or 0 to disable timer
2703 * @cnt: the hold-off packet count, or 0 to disable counter
2704 *
2705 * Set the RX interrupt hold-off parameters for a network device.
2706 */
2707static int set_rx_intr_params(struct net_device *dev,
2708 unsigned int us, unsigned int cnt)
b8ff05a9 2709{
c887ad0e
HS		 2710 int i, err;
2711 struct port_info *pi = netdev_priv(dev);
b8ff05a9 2712 struct adapter *adap = pi->adapter;
c887ad0e
HS		 2713 struct sge_eth_rxq *q = &adap->sge.ethrxq[pi->first_qset];
2714
2715 for (i = 0; i < pi->nqsets; i++, q++) {
2716 err = set_rspq_intr_params(&q->rspq, us, cnt);
2717 if (err)
2718 return err;
d4fc9dc2 2719 }
c887ad0e
HS		 2720 return 0;
2721}
2722
2723static int set_coalesce(struct net_device *dev, struct ethtool_coalesce *c)
2724{
2725 return set_rx_intr_params(dev, c->rx_coalesce_usecs,
2726 c->rx_max_coalesced_frames);
b8ff05a9
DM		 2727}
2728
2729static int get_coalesce(struct net_device *dev, struct ethtool_coalesce *c)
2730{
2731 const struct port_info *pi = netdev_priv(dev);
2732 const struct adapter *adap = pi->adapter;
2733 const struct sge_rspq *rq = &adap->sge.ethrxq[pi->first_qset].rspq;
2734
2735 c->rx_coalesce_usecs = qtimer_val(adap, rq);
2736 c->rx_max_coalesced_frames = (rq->intr_params & QINTR_CNT_EN) ?
2737 adap->sge.counter_val[rq->pktcnt_idx] : 0;
2738 return 0;
2739}
2740
1478b3ee
DM		 2741/**
2742 * eeprom_ptov - translate a physical EEPROM address to virtual
2743 * @phys_addr: the physical EEPROM address
2744 * @fn: the PCI function number
2745 * @sz: size of function-specific area
2746 *
2747 * Translate a physical EEPROM address to virtual. The first 1K is
2748 * accessed through virtual addresses starting at 31K, the rest is
2749 * accessed through virtual addresses starting at 0.
2750 *
2751 * The mapping is as follows:
2752 * [0..1K) -> [31K..32K)
2753 * [1K..1K+A) -> [31K-A..31K)
2754 * [1K+A..ES) -> [0..ES-A-1K)
2755 *
2756 * where A = @fn * @sz, and ES = EEPROM size.
b8ff05a9 2757 */
1478b3ee 2758static int eeprom_ptov(unsigned int phys_addr, unsigned int fn, unsigned int sz)
b8ff05a9 2759{
1478b3ee 2760 fn *= sz;
b8ff05a9
DM		 2761 if (phys_addr < 1024)
2762 return phys_addr + (31 << 10);
1478b3ee
DM		 2763 if (phys_addr < 1024 + fn)
2764 return 31744 - fn + phys_addr - 1024;
b8ff05a9 2765 if (phys_addr < EEPROMSIZE)
1478b3ee 2766 return phys_addr - 1024 - fn;
b8ff05a9
DM		 2767 return -EINVAL;
2768}
2769
2770/*
2771 * The next two routines implement eeprom read/write from physical addresses.
b8ff05a9
DM		 2772 */
2773static int eeprom_rd_phys(struct adapter *adap, unsigned int phys_addr, u32 *v)
2774{
1478b3ee 2775 int vaddr = eeprom_ptov(phys_addr, adap->fn, EEPROMPFSIZE);
b8ff05a9
DM		 2776
2777 if (vaddr >= 0)
2778 vaddr = pci_read_vpd(adap->pdev, vaddr, sizeof(u32), v);
2779 return vaddr < 0 ? vaddr : 0;
2780}
2781
2782static int eeprom_wr_phys(struct adapter *adap, unsigned int phys_addr, u32 v)
2783{
1478b3ee 2784 int vaddr = eeprom_ptov(phys_addr, adap->fn, EEPROMPFSIZE);
b8ff05a9
DM		 2785
2786 if (vaddr >= 0)
2787 vaddr = pci_write_vpd(adap->pdev, vaddr, sizeof(u32), &v);
2788 return vaddr < 0 ? vaddr : 0;
2789}
2790
2791#define EEPROM_MAGIC 0x38E2F10C
2792
2793static int get_eeprom(struct net_device *dev, struct ethtool_eeprom *e,
2794 u8 *data)
2795{
2796 int i, err = 0;
2797 struct adapter *adapter = netdev2adap(dev);
2798
2799 u8 *buf = kmalloc(EEPROMSIZE, GFP_KERNEL);
2800 if (!buf)
2801 return -ENOMEM;
2802
2803 e->magic = EEPROM_MAGIC;
2804 for (i = e->offset & ~3; !err && i < e->offset + e->len; i += 4)
2805 err = eeprom_rd_phys(adapter, i, (u32 *)&buf[i]);
2806
2807 if (!err)
2808 memcpy(data, buf + e->offset, e->len);
2809 kfree(buf);
2810 return err;
2811}
2812
2813static int set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
2814 u8 *data)
2815{
2816 u8 *buf;
2817 int err = 0;
2818 u32 aligned_offset, aligned_len, *p;
2819 struct adapter *adapter = netdev2adap(dev);
2820
2821 if (eeprom->magic != EEPROM_MAGIC)
2822 return -EINVAL;
2823
2824 aligned_offset = eeprom->offset & ~3;
2825 aligned_len = (eeprom->len + (eeprom->offset & 3) + 3) & ~3;
2826
1478b3ee
DM		 2827 if (adapter->fn > 0) {
2828 u32 start = 1024 + adapter->fn * EEPROMPFSIZE;
2829
2830 if (aligned_offset < start ||
2831 aligned_offset + aligned_len > start + EEPROMPFSIZE)
2832 return -EPERM;
2833 }
2834
b8ff05a9
DM		 2835 if (aligned_offset != eeprom->offset || aligned_len != eeprom->len) {
2836 /*
2837 * RMW possibly needed for first or last words.
2838 */
2839 buf = kmalloc(aligned_len, GFP_KERNEL);
2840 if (!buf)
2841 return -ENOMEM;
2842 err = eeprom_rd_phys(adapter, aligned_offset, (u32 *)buf);
2843 if (!err && aligned_len > 4)
2844 err = eeprom_rd_phys(adapter,
2845 aligned_offset + aligned_len - 4,
2846 (u32 *)&buf[aligned_len - 4]);
2847 if (err)
2848 goto out;
2849 memcpy(buf + (eeprom->offset & 3), data, eeprom->len);
2850 } else
2851 buf = data;
2852
2853 err = t4_seeprom_wp(adapter, false);
2854 if (err)
2855 goto out;
2856
2857 for (p = (u32 *)buf; !err && aligned_len; aligned_len -= 4, p++) {
2858 err = eeprom_wr_phys(adapter, aligned_offset, *p);
2859 aligned_offset += 4;
2860 }
2861
2862 if (!err)
2863 err = t4_seeprom_wp(adapter, true);
2864out:
2865 if (buf != data)
2866 kfree(buf);
2867 return err;
2868}
2869
2870static int set_flash(struct net_device *netdev, struct ethtool_flash *ef)
2871{
2872 int ret;
2873 const struct firmware *fw;
2874 struct adapter *adap = netdev2adap(netdev);
2875
2876 ef->data[sizeof(ef->data) - 1] = '\0';
2877 ret = request_firmware(&fw, ef->data, adap->pdev_dev);
2878 if (ret < 0)
2879 return ret;
2880
2881 ret = t4_load_fw(adap, fw->data, fw->size);
2882 release_firmware(fw);
2883 if (!ret)
2884 dev_info(adap->pdev_dev, "loaded firmware %s\n", ef->data);
2885 return ret;
2886}
2887
2888#define WOL_SUPPORTED (WAKE_BCAST | WAKE_MAGIC)
2889#define BCAST_CRC 0xa0ccc1a6
2890
2891static void get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2892{
2893 wol->supported = WAKE_BCAST | WAKE_MAGIC;
2894 wol->wolopts = netdev2adap(dev)->wol;
2895 memset(&wol->sopass, 0, sizeof(wol->sopass));
2896}
2897
2898static int set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2899{
2900 int err = 0;
2901 struct port_info *pi = netdev_priv(dev);
2902
2903 if (wol->wolopts & ~WOL_SUPPORTED)
2904 return -EINVAL;
2905 t4_wol_magic_enable(pi->adapter, pi->tx_chan,
2906 (wol->wolopts & WAKE_MAGIC) ? dev->dev_addr : NULL);
2907 if (wol->wolopts & WAKE_BCAST) {
2908 err = t4_wol_pat_enable(pi->adapter, pi->tx_chan, 0xfe, ~0ULL,
2909 ~0ULL, 0, false);
2910 if (!err)
2911 err = t4_wol_pat_enable(pi->adapter, pi->tx_chan, 1,
2912 ~6ULL, ~0ULL, BCAST_CRC, true);
2913 } else
2914 t4_wol_pat_enable(pi->adapter, pi->tx_chan, 0, 0, 0, 0, false);
2915 return err;
2916}
2917
c8f44aff 2918static int cxgb_set_features(struct net_device *dev, netdev_features_t features)
87b6cf51 2919{
2ed28baa 2920 const struct port_info *pi = netdev_priv(dev);
c8f44aff 2921 netdev_features_t changed = dev->features ^ features;
19ecae2c 2922 int err;
19ecae2c 2923
f646968f 2924 if (!(changed & NETIF_F_HW_VLAN_CTAG_RX))
2ed28baa 2925 return 0;
19ecae2c 2926
2ed28baa
MM		 2927 err = t4_set_rxmode(pi->adapter, pi->adapter->fn, pi->viid, -1,
2928 -1, -1, -1,
f646968f 2929 !!(features & NETIF_F_HW_VLAN_CTAG_RX), true);
2ed28baa 2930 if (unlikely(err))
f646968f 2931 dev->features = features ^ NETIF_F_HW_VLAN_CTAG_RX;
19ecae2c 2932 return err;
87b6cf51
DM		 2933}
2934
7850f63f 2935static u32 get_rss_table_size(struct net_device *dev)
671b0060
DM		 2936{
2937 const struct port_info *pi = netdev_priv(dev);
671b0060 2938
7850f63f
BH		 2939 return pi->rss_size;
2940}
2941
fe62d001 2942static int get_rss_table(struct net_device *dev, u32 *p, u8 *key)
7850f63f
BH		 2943{
2944 const struct port_info *pi = netdev_priv(dev);
2945 unsigned int n = pi->rss_size;
2946
671b0060 2947 while (n--)
7850f63f 2948 p[n] = pi->rss[n];
671b0060
DM		 2949 return 0;
2950}
2951
fe62d001 2952static int set_rss_table(struct net_device *dev, const u32 *p, const u8 *key)
671b0060
DM		 2953{
2954 unsigned int i;
2955 struct port_info *pi = netdev_priv(dev);
2956
7850f63f
BH		 2957 for (i = 0; i < pi->rss_size; i++)
2958 pi->rss[i] = p[i];
671b0060
DM		 2959 if (pi->adapter->flags & FULL_INIT_DONE)
2960 return write_rss(pi, pi->rss);
2961 return 0;
2962}
2963
2964static int get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *info,
815c7db5 2965 u32 *rules)
671b0060 2966{
f796564a
DM		 2967 const struct port_info *pi = netdev_priv(dev);
2968
671b0060 2969 switch (info->cmd) {
f796564a
DM		 2970 case ETHTOOL_GRXFH: {
2971 unsigned int v = pi->rss_mode;
2972
2973 info->data = 0;
2974 switch (info->flow_type) {
2975 case TCP_V4_FLOW:
2976 if (v & FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN)
2977 info->data = RXH_IP_SRC | RXH_IP_DST |
2978 RXH_L4_B_0_1 | RXH_L4_B_2_3;
2979 else if (v & FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN)
2980 info->data = RXH_IP_SRC | RXH_IP_DST;
2981 break;
2982 case UDP_V4_FLOW:
2983 if ((v & FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN) &&
2984 (v & FW_RSS_VI_CONFIG_CMD_UDPEN))
2985 info->data = RXH_IP_SRC | RXH_IP_DST |
2986 RXH_L4_B_0_1 | RXH_L4_B_2_3;
2987 else if (v & FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN)
2988 info->data = RXH_IP_SRC | RXH_IP_DST;
2989 break;
2990 case SCTP_V4_FLOW:
2991 case AH_ESP_V4_FLOW:
2992 case IPV4_FLOW:
2993 if (v & FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN)
2994 info->data = RXH_IP_SRC | RXH_IP_DST;
2995 break;
2996 case TCP_V6_FLOW:
2997 if (v & FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN)
2998 info->data = RXH_IP_SRC | RXH_IP_DST |
2999 RXH_L4_B_0_1 | RXH_L4_B_2_3;
3000 else if (v & FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN)
3001 info->data = RXH_IP_SRC | RXH_IP_DST;
3002 break;
3003 case UDP_V6_FLOW:
3004 if ((v & FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN) &&
3005 (v & FW_RSS_VI_CONFIG_CMD_UDPEN))
3006 info->data = RXH_IP_SRC | RXH_IP_DST |
3007 RXH_L4_B_0_1 | RXH_L4_B_2_3;
3008 else if (v & FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN)
3009 info->data = RXH_IP_SRC | RXH_IP_DST;
3010 break;
3011 case SCTP_V6_FLOW:
3012 case AH_ESP_V6_FLOW:
3013 case IPV6_FLOW:
3014 if (v & FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN)
3015 info->data = RXH_IP_SRC | RXH_IP_DST;
3016 break;
3017 }
3018 return 0;
3019 }
671b0060 3020 case ETHTOOL_GRXRINGS:
f796564a 3021 info->data = pi->nqsets;
671b0060
DM		 3022 return 0;
3023 }
3024 return -EOPNOTSUPP;
3025}
3026
9b07be4b 3027static const struct ethtool_ops cxgb_ethtool_ops = {
b8ff05a9
DM		 3028 .get_settings = get_settings,
3029 .set_settings = set_settings,
3030 .get_drvinfo = get_drvinfo,
3031 .get_msglevel = get_msglevel,
3032 .set_msglevel = set_msglevel,
3033 .get_ringparam = get_sge_param,
3034 .set_ringparam = set_sge_param,
3035 .get_coalesce = get_coalesce,
3036 .set_coalesce = set_coalesce,
3037 .get_eeprom_len = get_eeprom_len,
3038 .get_eeprom = get_eeprom,
3039 .set_eeprom = set_eeprom,
3040 .get_pauseparam = get_pauseparam,
3041 .set_pauseparam = set_pauseparam,
b8ff05a9
DM		 3042 .get_link = ethtool_op_get_link,
3043 .get_strings = get_strings,
c5e06360 3044 .set_phys_id = identify_port,
b8ff05a9
DM		 3045 .nway_reset = restart_autoneg,
3046 .get_sset_count = get_sset_count,
3047 .get_ethtool_stats = get_stats,
3048 .get_regs_len = get_regs_len,
3049 .get_regs = get_regs,
3050 .get_wol = get_wol,
3051 .set_wol = set_wol,
671b0060 3052 .get_rxnfc = get_rxnfc,
7850f63f 3053 .get_rxfh_indir_size = get_rss_table_size,
fe62d001
BH		 3054 .get_rxfh = get_rss_table,
3055 .set_rxfh = set_rss_table,
b8ff05a9
DM		 3056 .flash_device = set_flash,
3057};
3058
3059/*
3060 * debugfs support
3061 */
b8ff05a9
DM		 3062static ssize_t mem_read(struct file *file, char __user *buf, size_t count,
3063 loff_t *ppos)
3064{
3065 loff_t pos = *ppos;
496ad9aa 3066 loff_t avail = file_inode(file)->i_size;
b8ff05a9
DM		 3067 unsigned int mem = (uintptr_t)file->private_data & 3;
3068 struct adapter *adap = file->private_data - mem;
fc5ab020
HS		 3069 __be32 *data;
3070 int ret;
b8ff05a9
DM		 3071
3072 if (pos < 0)
3073 return -EINVAL;
3074 if (pos >= avail)
3075 return 0;
3076 if (count > avail - pos)
3077 count = avail - pos;
3078
fc5ab020
HS		 3079 data = t4_alloc_mem(count);
3080 if (!data)
3081 return -ENOMEM;
b8ff05a9 3082
fc5ab020
HS		 3083 spin_lock(&adap->win0_lock);
3084 ret = t4_memory_rw(adap, 0, mem, pos, count, data, T4_MEMORY_READ);
3085 spin_unlock(&adap->win0_lock);
3086 if (ret) {
3087 t4_free_mem(data);
3088 return ret;
3089 }
3090 ret = copy_to_user(buf, data, count);
b8ff05a9 3091
fc5ab020
HS		 3092 t4_free_mem(data);
3093 if (ret)
3094 return -EFAULT;
b8ff05a9 3095
fc5ab020 3096 *ppos = pos + count;
b8ff05a9
DM		 3097 return count;
3098}
3099
3100static const struct file_operations mem_debugfs_fops = {
3101 .owner = THIS_MODULE,
234e3405 3102 .open = simple_open,
b8ff05a9 3103 .read = mem_read,
6038f373 3104 .llseek = default_llseek,
b8ff05a9
DM		 3105};
3106
91744948 3107static void add_debugfs_mem(struct adapter *adap, const char *name,
1dd06ae8 3108 unsigned int idx, unsigned int size_mb)
b8ff05a9
DM		 3109{
3110 struct dentry *de;
3111
3112 de = debugfs_create_file(name, S_IRUSR, adap->debugfs_root,
3113 (void *)adap + idx, &mem_debugfs_fops);
3114 if (de && de->d_inode)
3115 de->d_inode->i_size = size_mb << 20;
3116}
3117
91744948 3118static int setup_debugfs(struct adapter *adap)
b8ff05a9
DM		 3119{
3120 int i;
19dd37ba 3121 u32 size;
b8ff05a9
DM		 3122
3123 if (IS_ERR_OR_NULL(adap->debugfs_root))
3124 return -1;
3125
3126 i = t4_read_reg(adap, MA_TARGET_MEM_ENABLE);
19dd37ba
SR		 3127 if (i & EDRAM0_ENABLE) {
3128 size = t4_read_reg(adap, MA_EDRAM0_BAR);
3129 add_debugfs_mem(adap, "edc0", MEM_EDC0, EDRAM_SIZE_GET(size));
3130 }
3131 if (i & EDRAM1_ENABLE) {
3132 size = t4_read_reg(adap, MA_EDRAM1_BAR);
3133 add_debugfs_mem(adap, "edc1", MEM_EDC1, EDRAM_SIZE_GET(size));
3134 }
d14807dd 3135 if (is_t4(adap->params.chip)) {
19dd37ba
SR		 3136 size = t4_read_reg(adap, MA_EXT_MEMORY_BAR);
3137 if (i & EXT_MEM_ENABLE)
3138 add_debugfs_mem(adap, "mc", MEM_MC,
3139 EXT_MEM_SIZE_GET(size));
3140 } else {
3141 if (i & EXT_MEM_ENABLE) {
3142 size = t4_read_reg(adap, MA_EXT_MEMORY_BAR);
3143 add_debugfs_mem(adap, "mc0", MEM_MC0,
3144 EXT_MEM_SIZE_GET(size));
3145 }
3146 if (i & EXT_MEM1_ENABLE) {
3147 size = t4_read_reg(adap, MA_EXT_MEMORY1_BAR);
3148 add_debugfs_mem(adap, "mc1", MEM_MC1,
3149 EXT_MEM_SIZE_GET(size));
3150 }
3151 }
b8ff05a9
DM		 3152 if (adap->l2t)
3153 debugfs_create_file("l2t", S_IRUSR, adap->debugfs_root, adap,
3154 &t4_l2t_fops);
3155 return 0;
3156}
3157
3158/*
3159 * upper-layer driver support
3160 */
3161
3162/*
3163 * Allocate an active-open TID and set it to the supplied value.
3164 */
3165int cxgb4_alloc_atid(struct tid_info *t, void *data)
3166{
3167 int atid = -1;
3168
3169 spin_lock_bh(&t->atid_lock);
3170 if (t->afree) {
3171 union aopen_entry *p = t->afree;
3172
f2b7e78d 3173 atid = (p - t->atid_tab) + t->atid_base;
b8ff05a9
DM		 3174 t->afree = p->next;
3175 p->data = data;
3176 t->atids_in_use++;
3177 }
3178 spin_unlock_bh(&t->atid_lock);
3179 return atid;
3180}
3181EXPORT_SYMBOL(cxgb4_alloc_atid);
3182
3183/*
3184 * Release an active-open TID.
3185 */
3186void cxgb4_free_atid(struct tid_info *t, unsigned int atid)
3187{
f2b7e78d 3188 union aopen_entry *p = &t->atid_tab[atid - t->atid_base];
b8ff05a9
DM		 3189
3190 spin_lock_bh(&t->atid_lock);
3191 p->next = t->afree;
3192 t->afree = p;
3193 t->atids_in_use--;
3194 spin_unlock_bh(&t->atid_lock);
3195}
3196EXPORT_SYMBOL(cxgb4_free_atid);
3197
3198/*
3199 * Allocate a server TID and set it to the supplied value.
3200 */
3201int cxgb4_alloc_stid(struct tid_info *t, int family, void *data)
3202{
3203 int stid;
3204
3205 spin_lock_bh(&t->stid_lock);
3206 if (family == PF_INET) {
3207 stid = find_first_zero_bit(t->stid_bmap, t->nstids);
3208 if (stid < t->nstids)
3209 __set_bit(stid, t->stid_bmap);
3210 else
3211 stid = -1;
3212 } else {
3213 stid = bitmap_find_free_region(t->stid_bmap, t->nstids, 2);
3214 if (stid < 0)
3215 stid = -1;
3216 }
3217 if (stid >= 0) {
3218 t->stid_tab[stid].data = data;
3219 stid += t->stid_base;
15f63b74
KS		 3220 /* IPv6 requires max of 520 bits or 16 cells in TCAM
3221 * This is equivalent to 4 TIDs. With CLIP enabled it
3222 * needs 2 TIDs.
3223 */
3224 if (family == PF_INET)
3225 t->stids_in_use++;
3226 else
3227 t->stids_in_use += 4;
b8ff05a9
DM		 3228 }
3229 spin_unlock_bh(&t->stid_lock);
3230 return stid;
3231}
3232EXPORT_SYMBOL(cxgb4_alloc_stid);
3233
dca4faeb
VP		 3234/* Allocate a server filter TID and set it to the supplied value.
3235 */
3236int cxgb4_alloc_sftid(struct tid_info *t, int family, void *data)
3237{
3238 int stid;
3239
3240 spin_lock_bh(&t->stid_lock);
3241 if (family == PF_INET) {
3242 stid = find_next_zero_bit(t->stid_bmap,
3243 t->nstids + t->nsftids, t->nstids);
3244 if (stid < (t->nstids + t->nsftids))
3245 __set_bit(stid, t->stid_bmap);
3246 else
3247 stid = -1;
3248 } else {
3249 stid = -1;
3250 }
3251 if (stid >= 0) {
3252 t->stid_tab[stid].data = data;
470c60c4
KS		 3253 stid -= t->nstids;
3254 stid += t->sftid_base;
dca4faeb
VP		 3255 t->stids_in_use++;
3256 }
3257 spin_unlock_bh(&t->stid_lock);
3258 return stid;
3259}
3260EXPORT_SYMBOL(cxgb4_alloc_sftid);
3261
3262/* Release a server TID.
b8ff05a9
DM		 3263 */
3264void cxgb4_free_stid(struct tid_info *t, unsigned int stid, int family)
3265{
470c60c4
KS		 3266 /* Is it a server filter TID? */
3267 if (t->nsftids && (stid >= t->sftid_base)) {
3268 stid -= t->sftid_base;
3269 stid += t->nstids;
3270 } else {
3271 stid -= t->stid_base;
3272 }
3273
b8ff05a9
DM		 3274 spin_lock_bh(&t->stid_lock);
3275 if (family == PF_INET)
3276 __clear_bit(stid, t->stid_bmap);
3277 else
3278 bitmap_release_region(t->stid_bmap, stid, 2);
3279 t->stid_tab[stid].data = NULL;
15f63b74
KS		 3280 if (family == PF_INET)
3281 t->stids_in_use--;
3282 else
3283 t->stids_in_use -= 4;
b8ff05a9
DM		 3284 spin_unlock_bh(&t->stid_lock);
3285}
3286EXPORT_SYMBOL(cxgb4_free_stid);
3287
3288/*
3289 * Populate a TID_RELEASE WR. Caller must properly size the skb.
3290 */
3291static void mk_tid_release(struct sk_buff *skb, unsigned int chan,
3292 unsigned int tid)
3293{
3294 struct cpl_tid_release *req;
3295
3296 set_wr_txq(skb, CPL_PRIORITY_SETUP, chan);
3297 req = (struct cpl_tid_release *)__skb_put(skb, sizeof(*req));
3298 INIT_TP_WR(req, tid);
3299 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_TID_RELEASE, tid));
3300}
3301
3302/*
3303 * Queue a TID release request and if necessary schedule a work queue to
3304 * process it.
3305 */
31b9c19b 3306static void cxgb4_queue_tid_release(struct tid_info *t, unsigned int chan,
3307 unsigned int tid)
b8ff05a9
DM		 3308{
3309 void **p = &t->tid_tab[tid];
3310 struct adapter *adap = container_of(t, struct adapter, tids);
3311
3312 spin_lock_bh(&adap->tid_release_lock);
3313 *p = adap->tid_release_head;
3314 /* Low 2 bits encode the Tx channel number */
3315 adap->tid_release_head = (void **)((uintptr_t)p | chan);
3316 if (!adap->tid_release_task_busy) {
3317 adap->tid_release_task_busy = true;
3069ee9b 3318 queue_work(workq, &adap->tid_release_task);
b8ff05a9
DM		 3319 }
3320 spin_unlock_bh(&adap->tid_release_lock);
3321}
b8ff05a9
DM		 3322
3323/*
3324 * Process the list of pending TID release requests.
3325 */
3326static void process_tid_release_list(struct work_struct *work)
3327{
3328 struct sk_buff *skb;
3329 struct adapter *adap;
3330
3331 adap = container_of(work, struct adapter, tid_release_task);
3332
3333 spin_lock_bh(&adap->tid_release_lock);
3334 while (adap->tid_release_head) {
3335 void **p = adap->tid_release_head;
3336 unsigned int chan = (uintptr_t)p & 3;
3337 p = (void *)p - chan;
3338
3339 adap->tid_release_head = *p;
3340 *p = NULL;
3341 spin_unlock_bh(&adap->tid_release_lock);
3342
3343 while (!(skb = alloc_skb(sizeof(struct cpl_tid_release),
3344 GFP_KERNEL)))
3345 schedule_timeout_uninterruptible(1);
3346
3347 mk_tid_release(skb, chan, p - adap->tids.tid_tab);
3348 t4_ofld_send(adap, skb);
3349 spin_lock_bh(&adap->tid_release_lock);
3350 }
3351 adap->tid_release_task_busy = false;
3352 spin_unlock_bh(&adap->tid_release_lock);
3353}
3354
3355/*
3356 * Release a TID and inform HW. If we are unable to allocate the release
3357 * message we defer to a work queue.
3358 */
3359void cxgb4_remove_tid(struct tid_info *t, unsigned int chan, unsigned int tid)
3360{
3361 void *old;
3362 struct sk_buff *skb;
3363 struct adapter *adap = container_of(t, struct adapter, tids);
3364
3365 old = t->tid_tab[tid];
3366 skb = alloc_skb(sizeof(struct cpl_tid_release), GFP_ATOMIC);
3367 if (likely(skb)) {
3368 t->tid_tab[tid] = NULL;
3369 mk_tid_release(skb, chan, tid);
3370 t4_ofld_send(adap, skb);
3371 } else
3372 cxgb4_queue_tid_release(t, chan, tid);
3373 if (old)
3374 atomic_dec(&t->tids_in_use);
3375}
3376EXPORT_SYMBOL(cxgb4_remove_tid);
3377
3378/*
3379 * Allocate and initialize the TID tables. Returns 0 on success.
3380 */
3381static int tid_init(struct tid_info *t)
3382{
3383 size_t size;
f2b7e78d 3384 unsigned int stid_bmap_size;
b8ff05a9 3385 unsigned int natids = t->natids;
b6f8eaec 3386 struct adapter *adap = container_of(t, struct adapter, tids);
b8ff05a9 3387
dca4faeb 3388 stid_bmap_size = BITS_TO_LONGS(t->nstids + t->nsftids);
f2b7e78d
VP		 3389 size = t->ntids * sizeof(*t->tid_tab) +
3390 natids * sizeof(*t->atid_tab) +
b8ff05a9 3391 t->nstids * sizeof(*t->stid_tab) +
dca4faeb 3392 t->nsftids * sizeof(*t->stid_tab) +
f2b7e78d 3393 stid_bmap_size * sizeof(long) +
dca4faeb
VP		 3394 t->nftids * sizeof(*t->ftid_tab) +
3395 t->nsftids * sizeof(*t->ftid_tab);
f2b7e78d 3396
b8ff05a9
DM		 3397 t->tid_tab = t4_alloc_mem(size);
3398 if (!t->tid_tab)
3399 return -ENOMEM;
3400
3401 t->atid_tab = (union aopen_entry *)&t->tid_tab[t->ntids];
3402 t->stid_tab = (struct serv_entry *)&t->atid_tab[natids];
dca4faeb 3403 t->stid_bmap = (unsigned long *)&t->stid_tab[t->nstids + t->nsftids];
f2b7e78d 3404 t->ftid_tab = (struct filter_entry *)&t->stid_bmap[stid_bmap_size];
b8ff05a9
DM		 3405 spin_lock_init(&t->stid_lock);
3406 spin_lock_init(&t->atid_lock);
3407
3408 t->stids_in_use = 0;
3409 t->afree = NULL;
3410 t->atids_in_use = 0;
3411 atomic_set(&t->tids_in_use, 0);
3412
3413 /* Setup the free list for atid_tab and clear the stid bitmap. */
3414 if (natids) {
3415 while (--natids)
3416 t->atid_tab[natids - 1].next = &t->atid_tab[natids];
3417 t->afree = t->atid_tab;
3418 }
dca4faeb 3419 bitmap_zero(t->stid_bmap, t->nstids + t->nsftids);
b6f8eaec
KS		 3420 /* Reserve stid 0 for T4/T5 adapters */
3421 if (!t->stid_base &&
3422 (is_t4(adap->params.chip) || is_t5(adap->params.chip)))
3423 __set_bit(0, t->stid_bmap);
3424
b8ff05a9
DM		 3425 return 0;
3426}
3427
01bcca68
VP		 3428static int cxgb4_clip_get(const struct net_device *dev,
3429 const struct in6_addr *lip)
3430{
3431 struct adapter *adap;
3432 struct fw_clip_cmd c;
3433
3434 adap = netdev2adap(dev);
3435 memset(&c, 0, sizeof(c));
3436 c.op_to_write = htonl(FW_CMD_OP(FW_CLIP_CMD) |
3437 FW_CMD_REQUEST | FW_CMD_WRITE);
3438 c.alloc_to_len16 = htonl(F_FW_CLIP_CMD_ALLOC | FW_LEN16(c));
12f2a479
JP		 3439 c.ip_hi = *(__be64 *)(lip->s6_addr);
3440 c.ip_lo = *(__be64 *)(lip->s6_addr + 8);
01bcca68
VP		 3441 return t4_wr_mbox_meat(adap, adap->mbox, &c, sizeof(c), &c, false);
3442}
3443
3444static int cxgb4_clip_release(const struct net_device *dev,
3445 const struct in6_addr *lip)
3446{
3447 struct adapter *adap;
3448 struct fw_clip_cmd c;
3449
3450 adap = netdev2adap(dev);
3451 memset(&c, 0, sizeof(c));
3452 c.op_to_write = htonl(FW_CMD_OP(FW_CLIP_CMD) |
3453 FW_CMD_REQUEST | FW_CMD_READ);
3454 c.alloc_to_len16 = htonl(F_FW_CLIP_CMD_FREE | FW_LEN16(c));
12f2a479
JP		 3455 c.ip_hi = *(__be64 *)(lip->s6_addr);
3456 c.ip_lo = *(__be64 *)(lip->s6_addr + 8);
01bcca68
VP		 3457 return t4_wr_mbox_meat(adap, adap->mbox, &c, sizeof(c), &c, false);
3458}
3459
b8ff05a9
DM		 3460/**
3461 * cxgb4_create_server - create an IP server
3462 * @dev: the device
3463 * @stid: the server TID
3464 * @sip: local IP address to bind server to
3465 * @sport: the server's TCP port
3466 * @queue: queue to direct messages from this server to
3467 *
3468 * Create an IP server for the given port and address.
3469 * Returns <0 on error and one of the %NET_XMIT_* values on success.
3470 */
3471int cxgb4_create_server(const struct net_device *dev, unsigned int stid,
793dad94
VP		 3472 __be32 sip, __be16 sport, __be16 vlan,
3473 unsigned int queue)
b8ff05a9
DM		 3474{
3475 unsigned int chan;
3476 struct sk_buff *skb;
3477 struct adapter *adap;
3478 struct cpl_pass_open_req *req;
80f40c1f 3479 int ret;
b8ff05a9
DM		 3480
3481 skb = alloc_skb(sizeof(*req), GFP_KERNEL);
3482 if (!skb)
3483 return -ENOMEM;
3484
3485 adap = netdev2adap(dev);
3486 req = (struct cpl_pass_open_req *)__skb_put(skb, sizeof(*req));
3487 INIT_TP_WR(req, 0);
3488 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_PASS_OPEN_REQ, stid));
3489 req->local_port = sport;
3490 req->peer_port = htons(0);
3491 req->local_ip = sip;
3492 req->peer_ip = htonl(0);
e46dab4d 3493 chan = rxq_to_chan(&adap->sge, queue);
b8ff05a9
DM		 3494 req->opt0 = cpu_to_be64(TX_CHAN(chan));
3495 req->opt1 = cpu_to_be64(CONN_POLICY_ASK |
3496 SYN_RSS_ENABLE | SYN_RSS_QUEUE(queue));
80f40c1f
VP		 3497 ret = t4_mgmt_tx(adap, skb);
3498 return net_xmit_eval(ret);
b8ff05a9
DM		 3499}
3500EXPORT_SYMBOL(cxgb4_create_server);
3501
80f40c1f
VP		 3502/* cxgb4_create_server6 - create an IPv6 server
3503 * @dev: the device
3504 * @stid: the server TID
3505 * @sip: local IPv6 address to bind server to
3506 * @sport: the server's TCP port
3507 * @queue: queue to direct messages from this server to
3508 *
3509 * Create an IPv6 server for the given port and address.
3510 * Returns <0 on error and one of the %NET_XMIT_* values on success.
3511 */
3512int cxgb4_create_server6(const struct net_device *dev, unsigned int stid,
3513 const struct in6_addr *sip, __be16 sport,
3514 unsigned int queue)
3515{
3516 unsigned int chan;
3517 struct sk_buff *skb;
3518 struct adapter *adap;
3519 struct cpl_pass_open_req6 *req;
3520 int ret;
3521
3522 skb = alloc_skb(sizeof(*req), GFP_KERNEL);
3523 if (!skb)
3524 return -ENOMEM;
3525
3526 adap = netdev2adap(dev);
3527 req = (struct cpl_pass_open_req6 *)__skb_put(skb, sizeof(*req));
3528 INIT_TP_WR(req, 0);
3529 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_PASS_OPEN_REQ6, stid));
3530 req->local_port = sport;
3531 req->peer_port = htons(0);
3532 req->local_ip_hi = *(__be64 *)(sip->s6_addr);
3533 req->local_ip_lo = *(__be64 *)(sip->s6_addr + 8);
3534 req->peer_ip_hi = cpu_to_be64(0);
3535 req->peer_ip_lo = cpu_to_be64(0);
3536 chan = rxq_to_chan(&adap->sge, queue);
3537 req->opt0 = cpu_to_be64(TX_CHAN(chan));
3538 req->opt1 = cpu_to_be64(CONN_POLICY_ASK |
3539 SYN_RSS_ENABLE | SYN_RSS_QUEUE(queue));
3540 ret = t4_mgmt_tx(adap, skb);
3541 return net_xmit_eval(ret);
3542}
3543EXPORT_SYMBOL(cxgb4_create_server6);
3544
3545int cxgb4_remove_server(const struct net_device *dev, unsigned int stid,
3546 unsigned int queue, bool ipv6)
3547{
3548 struct sk_buff *skb;
3549 struct adapter *adap;
3550 struct cpl_close_listsvr_req *req;
3551 int ret;
3552
3553 adap = netdev2adap(dev);
3554
3555 skb = alloc_skb(sizeof(*req), GFP_KERNEL);
3556 if (!skb)
3557 return -ENOMEM;
3558
3559 req = (struct cpl_close_listsvr_req *)__skb_put(skb, sizeof(*req));
3560 INIT_TP_WR(req, 0);
3561 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_CLOSE_LISTSRV_REQ, stid));
3562 req->reply_ctrl = htons(NO_REPLY(0) | (ipv6 ? LISTSVR_IPV6(1) :
3563 LISTSVR_IPV6(0)) | QUEUENO(queue));
3564 ret = t4_mgmt_tx(adap, skb);
3565 return net_xmit_eval(ret);
3566}
3567EXPORT_SYMBOL(cxgb4_remove_server);
3568
b8ff05a9
DM		 3569/**
3570 * cxgb4_best_mtu - find the entry in the MTU table closest to an MTU
3571 * @mtus: the HW MTU table
3572 * @mtu: the target MTU
3573 * @idx: index of selected entry in the MTU table
3574 *
3575 * Returns the index and the value in the HW MTU table that is closest to
3576 * but does not exceed @mtu, unless @mtu is smaller than any value in the
3577 * table, in which case that smallest available value is selected.
3578 */
3579unsigned int cxgb4_best_mtu(const unsigned short *mtus, unsigned short mtu,
3580 unsigned int *idx)
3581{
3582 unsigned int i = 0;
3583
3584 while (i < NMTUS - 1 && mtus[i + 1] <= mtu)
3585 ++i;
3586 if (idx)
3587 *idx = i;
3588 return mtus[i];
3589}
3590EXPORT_SYMBOL(cxgb4_best_mtu);
3591
92e7ae71
HS		 3592/**
3593 * cxgb4_best_aligned_mtu - find best MTU, [hopefully] data size aligned
3594 * @mtus: the HW MTU table
3595 * @header_size: Header Size
3596 * @data_size_max: maximum Data Segment Size
3597 * @data_size_align: desired Data Segment Size Alignment (2^N)
3598 * @mtu_idxp: HW MTU Table Index return value pointer (possibly NULL)
3599 *
3600 * Similar to cxgb4_best_mtu() but instead of searching the Hardware
3601 * MTU Table based solely on a Maximum MTU parameter, we break that
3602 * parameter up into a Header Size and Maximum Data Segment Size, and
3603 * provide a desired Data Segment Size Alignment. If we find an MTU in
3604 * the Hardware MTU Table which will result in a Data Segment Size with
3605 * the requested alignment _and_ that MTU isn't "too far" from the
3606 * closest MTU, then we'll return that rather than the closest MTU.
3607 */
3608unsigned int cxgb4_best_aligned_mtu(const unsigned short *mtus,
3609 unsigned short header_size,
3610 unsigned short data_size_max,
3611 unsigned short data_size_align,
3612 unsigned int *mtu_idxp)
3613{
3614 unsigned short max_mtu = header_size + data_size_max;
3615 unsigned short data_size_align_mask = data_size_align - 1;
3616 int mtu_idx, aligned_mtu_idx;
3617
3618 /* Scan the MTU Table till we find an MTU which is larger than our
3619 * Maximum MTU or we reach the end of the table. Along the way,
3620 * record the last MTU found, if any, which will result in a Data
3621 * Segment Length matching the requested alignment.
3622 */
3623 for (mtu_idx = 0, aligned_mtu_idx = -1; mtu_idx < NMTUS; mtu_idx++) {
3624 unsigned short data_size = mtus[mtu_idx] - header_size;
3625
3626 /* If this MTU minus the Header Size would result in a
3627 * Data Segment Size of the desired alignment, remember it.
3628 */
3629 if ((data_size & data_size_align_mask) == 0)
3630 aligned_mtu_idx = mtu_idx;
3631
3632 /* If we're not at the end of the Hardware MTU Table and the
3633 * next element is larger than our Maximum MTU, drop out of
3634 * the loop.
3635 */
3636 if (mtu_idx+1 < NMTUS && mtus[mtu_idx+1] > max_mtu)
3637 break;
3638 }
3639
3640 /* If we fell out of the loop because we ran to the end of the table,
3641 * then we just have to use the last [largest] entry.
3642 */
3643 if (mtu_idx == NMTUS)
3644 mtu_idx--;
3645
3646 /* If we found an MTU which resulted in the requested Data Segment
3647 * Length alignment and that's "not far" from the largest MTU which is
3648 * less than or equal to the maximum MTU, then use that.
3649 */
3650 if (aligned_mtu_idx >= 0 &&
3651 mtu_idx - aligned_mtu_idx <= 1)
3652 mtu_idx = aligned_mtu_idx;
3653
3654 /* If the caller has passed in an MTU Index pointer, pass the
3655 * MTU Index back. Return the MTU value.
3656 */
3657 if (mtu_idxp)
3658 *mtu_idxp = mtu_idx;
3659 return mtus[mtu_idx];
3660}
3661EXPORT_SYMBOL(cxgb4_best_aligned_mtu);
3662
b8ff05a9
DM		 3663/**
3664 * cxgb4_port_chan - get the HW channel of a port
3665 * @dev: the net device for the port
3666 *
3667 * Return the HW Tx channel of the given port.
3668 */
3669unsigned int cxgb4_port_chan(const struct net_device *dev)
3670{
3671 return netdev2pinfo(dev)->tx_chan;
3672}
3673EXPORT_SYMBOL(cxgb4_port_chan);
3674
881806bc
VP		 3675unsigned int cxgb4_dbfifo_count(const struct net_device *dev, int lpfifo)
3676{
3677 struct adapter *adap = netdev2adap(dev);
2cc301d2 3678 u32 v1, v2, lp_count, hp_count;
881806bc 3679
2cc301d2
SR		 3680 v1 = t4_read_reg(adap, A_SGE_DBFIFO_STATUS);
3681 v2 = t4_read_reg(adap, SGE_DBFIFO_STATUS2);
d14807dd 3682 if (is_t4(adap->params.chip)) {
2cc301d2
SR		 3683 lp_count = G_LP_COUNT(v1);
3684 hp_count = G_HP_COUNT(v1);
3685 } else {
3686 lp_count = G_LP_COUNT_T5(v1);
3687 hp_count = G_HP_COUNT_T5(v2);
3688 }
3689 return lpfifo ? lp_count : hp_count;
881806bc
VP		 3690}
3691EXPORT_SYMBOL(cxgb4_dbfifo_count);
3692
b8ff05a9
DM		 3693/**
3694 * cxgb4_port_viid - get the VI id of a port
3695 * @dev: the net device for the port
3696 *
3697 * Return the VI id of the given port.
3698 */
3699unsigned int cxgb4_port_viid(const struct net_device *dev)
3700{
3701 return netdev2pinfo(dev)->viid;
3702}
3703EXPORT_SYMBOL(cxgb4_port_viid);
3704
3705/**
3706 * cxgb4_port_idx - get the index of a port
3707 * @dev: the net device for the port
3708 *
3709 * Return the index of the given port.
3710 */
3711unsigned int cxgb4_port_idx(const struct net_device *dev)
3712{
3713 return netdev2pinfo(dev)->port_id;
3714}
3715EXPORT_SYMBOL(cxgb4_port_idx);
3716
b8ff05a9
DM		 3717void cxgb4_get_tcp_stats(struct pci_dev *pdev, struct tp_tcp_stats *v4,
3718 struct tp_tcp_stats *v6)
3719{
3720 struct adapter *adap = pci_get_drvdata(pdev);
3721
3722 spin_lock(&adap->stats_lock);
3723 t4_tp_get_tcp_stats(adap, v4, v6);
3724 spin_unlock(&adap->stats_lock);
3725}
3726EXPORT_SYMBOL(cxgb4_get_tcp_stats);
3727
3728void cxgb4_iscsi_init(struct net_device *dev, unsigned int tag_mask,
3729 const unsigned int *pgsz_order)
3730{
3731 struct adapter *adap = netdev2adap(dev);
3732
3733 t4_write_reg(adap, ULP_RX_ISCSI_TAGMASK, tag_mask);
3734 t4_write_reg(adap, ULP_RX_ISCSI_PSZ, HPZ0(pgsz_order[0]) |
3735 HPZ1(pgsz_order[1]) | HPZ2(pgsz_order[2]) |
3736 HPZ3(pgsz_order[3]));
3737}
3738EXPORT_SYMBOL(cxgb4_iscsi_init);
3739
3069ee9b
VP		 3740int cxgb4_flush_eq_cache(struct net_device *dev)
3741{
3742 struct adapter *adap = netdev2adap(dev);
3743 int ret;
3744
3745 ret = t4_fwaddrspace_write(adap, adap->mbox,
3746 0xe1000000 + A_SGE_CTXT_CMD, 0x20000000);
3747 return ret;
3748}
3749EXPORT_SYMBOL(cxgb4_flush_eq_cache);
3750
3751static int read_eq_indices(struct adapter *adap, u16 qid, u16 *pidx, u16 *cidx)
3752{
3753 u32 addr = t4_read_reg(adap, A_SGE_DBQ_CTXT_BADDR) + 24 * qid + 8;
3754 __be64 indices;
3755 int ret;
3756
fc5ab020
HS		 3757 spin_lock(&adap->win0_lock);
3758 ret = t4_memory_rw(adap, 0, MEM_EDC0, addr,
3759 sizeof(indices), (__be32 *)&indices,
3760 T4_MEMORY_READ);
3761 spin_unlock(&adap->win0_lock);
3069ee9b 3762 if (!ret) {
404d9e3f
VP		 3763 *cidx = (be64_to_cpu(indices) >> 25) & 0xffff;
3764 *pidx = (be64_to_cpu(indices) >> 9) & 0xffff;
3069ee9b
VP		 3765 }
3766 return ret;
3767}
3768
3769int cxgb4_sync_txq_pidx(struct net_device *dev, u16 qid, u16 pidx,
3770 u16 size)
3771{
3772 struct adapter *adap = netdev2adap(dev);
3773 u16 hw_pidx, hw_cidx;
3774 int ret;
3775
3776 ret = read_eq_indices(adap, qid, &hw_pidx, &hw_cidx);
3777 if (ret)
3778 goto out;
3779
3780 if (pidx != hw_pidx) {
3781 u16 delta;
3782
3783 if (pidx >= hw_pidx)
3784 delta = pidx - hw_pidx;
3785 else
3786 delta = size - hw_pidx + pidx;
3787 wmb();
840f3000
VP		 3788 t4_write_reg(adap, MYPF_REG(SGE_PF_KDOORBELL),
3789 QID(qid) | PIDX(delta));
3069ee9b
VP		 3790 }
3791out:
3792 return ret;
3793}
3794EXPORT_SYMBOL(cxgb4_sync_txq_pidx);
3795
3cbdb928
VP		 3796void cxgb4_disable_db_coalescing(struct net_device *dev)
3797{
3798 struct adapter *adap;
3799
3800 adap = netdev2adap(dev);
3801 t4_set_reg_field(adap, A_SGE_DOORBELL_CONTROL, F_NOCOALESCE,
3802 F_NOCOALESCE);
3803}
3804EXPORT_SYMBOL(cxgb4_disable_db_coalescing);
3805
3806void cxgb4_enable_db_coalescing(struct net_device *dev)
3807{
3808 struct adapter *adap;
3809
3810 adap = netdev2adap(dev);
3811 t4_set_reg_field(adap, A_SGE_DOORBELL_CONTROL, F_NOCOALESCE, 0);
3812}
3813EXPORT_SYMBOL(cxgb4_enable_db_coalescing);
3814
b8ff05a9
DM		 3815static struct pci_driver cxgb4_driver;
3816
3817static void check_neigh_update(struct neighbour *neigh)
3818{
3819 const struct device *parent;
3820 const struct net_device *netdev = neigh->dev;
3821
3822 if (netdev->priv_flags & IFF_802_1Q_VLAN)
3823 netdev = vlan_dev_real_dev(netdev);
3824 parent = netdev->dev.parent;
3825 if (parent && parent->driver == &cxgb4_driver.driver)
3826 t4_l2t_update(dev_get_drvdata(parent), neigh);
3827}
3828
3829static int netevent_cb(struct notifier_block *nb, unsigned long event,
3830 void *data)
3831{
3832 switch (event) {
3833 case NETEVENT_NEIGH_UPDATE:
3834 check_neigh_update(data);
3835 break;
b8ff05a9
DM		 3836 case NETEVENT_REDIRECT:
3837 default:
3838 break;
3839 }
3840 return 0;
3841}
3842
3843static bool netevent_registered;
3844static struct notifier_block cxgb4_netevent_nb = {
3845 .notifier_call = netevent_cb
3846};
3847
3069ee9b
VP		 3848static void drain_db_fifo(struct adapter *adap, int usecs)
3849{
2cc301d2 3850 u32 v1, v2, lp_count, hp_count;
3069ee9b
VP		 3851
3852 do {
2cc301d2
SR		 3853 v1 = t4_read_reg(adap, A_SGE_DBFIFO_STATUS);
3854 v2 = t4_read_reg(adap, SGE_DBFIFO_STATUS2);
d14807dd 3855 if (is_t4(adap->params.chip)) {
2cc301d2
SR		 3856 lp_count = G_LP_COUNT(v1);
3857 hp_count = G_HP_COUNT(v1);
3858 } else {
3859 lp_count = G_LP_COUNT_T5(v1);
3860 hp_count = G_HP_COUNT_T5(v2);
3861 }
3862
3863 if (lp_count == 0 && hp_count == 0)
3864 break;
3069ee9b
VP		 3865 set_current_state(TASK_UNINTERRUPTIBLE);
3866 schedule_timeout(usecs_to_jiffies(usecs));
3069ee9b
VP		 3867 } while (1);
3868}
3869
3870static void disable_txq_db(struct sge_txq *q)
3871{
05eb2389
SW		 3872 unsigned long flags;
3873
3874 spin_lock_irqsave(&q->db_lock, flags);
3069ee9b 3875 q->db_disabled = 1;
05eb2389 3876 spin_unlock_irqrestore(&q->db_lock, flags);
3069ee9b
VP		 3877}
3878
05eb2389 3879static void enable_txq_db(struct adapter *adap, struct sge_txq *q)
3069ee9b
VP		 3880{
3881 spin_lock_irq(&q->db_lock);
05eb2389
SW		 3882 if (q->db_pidx_inc) {
3883 /* Make sure that all writes to the TX descriptors
3884 * are committed before we tell HW about them.
3885 */
3886 wmb();
3887 t4_write_reg(adap, MYPF_REG(SGE_PF_KDOORBELL),
3888 QID(q->cntxt_id) | PIDX(q->db_pidx_inc));
3889 q->db_pidx_inc = 0;
3890 }
3069ee9b
VP		 3891 q->db_disabled = 0;
3892 spin_unlock_irq(&q->db_lock);
3893}
3894
3895static void disable_dbs(struct adapter *adap)
3896{
3897 int i;
3898
3899 for_each_ethrxq(&adap->sge, i)
3900 disable_txq_db(&adap->sge.ethtxq[i].q);
3901 for_each_ofldrxq(&adap->sge, i)
3902 disable_txq_db(&adap->sge.ofldtxq[i].q);
3903 for_each_port(adap, i)
3904 disable_txq_db(&adap->sge.ctrlq[i].q);
3905}
3906
3907static void enable_dbs(struct adapter *adap)
3908{
3909 int i;
3910
3911 for_each_ethrxq(&adap->sge, i)
05eb2389 3912 enable_txq_db(adap, &adap->sge.ethtxq[i].q);
3069ee9b 3913 for_each_ofldrxq(&adap->sge, i)
05eb2389 3914 enable_txq_db(adap, &adap->sge.ofldtxq[i].q);
3069ee9b 3915 for_each_port(adap, i)
05eb2389
SW		 3916 enable_txq_db(adap, &adap->sge.ctrlq[i].q);
3917}
3918
3919static void notify_rdma_uld(struct adapter *adap, enum cxgb4_control cmd)
3920{
3921 if (adap->uld_handle[CXGB4_ULD_RDMA])
3922 ulds[CXGB4_ULD_RDMA].control(adap->uld_handle[CXGB4_ULD_RDMA],
3923 cmd);
3924}
3925
3926static void process_db_full(struct work_struct *work)
3927{
3928 struct adapter *adap;
3929
3930 adap = container_of(work, struct adapter, db_full_task);
3931
3932 drain_db_fifo(adap, dbfifo_drain_delay);
3933 enable_dbs(adap);
3934 notify_rdma_uld(adap, CXGB4_CONTROL_DB_EMPTY);
3935 t4_set_reg_field(adap, SGE_INT_ENABLE3,
3936 DBFIFO_HP_INT | DBFIFO_LP_INT,
3937 DBFIFO_HP_INT | DBFIFO_LP_INT);
3069ee9b
VP		 3938}
3939
3940static void sync_txq_pidx(struct adapter *adap, struct sge_txq *q)
3941{
3942 u16 hw_pidx, hw_cidx;
3943 int ret;
3944
05eb2389 3945 spin_lock_irq(&q->db_lock);
3069ee9b
VP		 3946 ret = read_eq_indices(adap, (u16)q->cntxt_id, &hw_pidx, &hw_cidx);
3947 if (ret)
3948 goto out;
3949 if (q->db_pidx != hw_pidx) {
3950 u16 delta;
3951
3952 if (q->db_pidx >= hw_pidx)
3953 delta = q->db_pidx - hw_pidx;
3954 else
3955 delta = q->size - hw_pidx + q->db_pidx;
3956 wmb();
840f3000
VP		 3957 t4_write_reg(adap, MYPF_REG(SGE_PF_KDOORBELL),
3958 QID(q->cntxt_id) | PIDX(delta));
3069ee9b
VP		 3959 }
3960out:
3961 q->db_disabled = 0;
05eb2389
SW		 3962 q->db_pidx_inc = 0;
3963 spin_unlock_irq(&q->db_lock);
3069ee9b
VP		 3964 if (ret)
3965 CH_WARN(adap, "DB drop recovery failed.\n");
3966}
3967static void recover_all_queues(struct adapter *adap)
3968{
3969 int i;
3970
3971 for_each_ethrxq(&adap->sge, i)
3972 sync_txq_pidx(adap, &adap->sge.ethtxq[i].q);
3973 for_each_ofldrxq(&adap->sge, i)
3974 sync_txq_pidx(adap, &adap->sge.ofldtxq[i].q);
3975 for_each_port(adap, i)
3976 sync_txq_pidx(adap, &adap->sge.ctrlq[i].q);
3977}
3978
881806bc
VP		 3979static void process_db_drop(struct work_struct *work)
3980{
3981 struct adapter *adap;
881806bc 3982
3069ee9b 3983 adap = container_of(work, struct adapter, db_drop_task);
881806bc 3984
d14807dd 3985 if (is_t4(adap->params.chip)) {
05eb2389 3986 drain_db_fifo(adap, dbfifo_drain_delay);
2cc301d2 3987 notify_rdma_uld(adap, CXGB4_CONTROL_DB_DROP);
05eb2389 3988 drain_db_fifo(adap, dbfifo_drain_delay);
2cc301d2 3989 recover_all_queues(adap);
05eb2389 3990 drain_db_fifo(adap, dbfifo_drain_delay);
2cc301d2 3991 enable_dbs(adap);
05eb2389 3992 notify_rdma_uld(adap, CXGB4_CONTROL_DB_EMPTY);
2cc301d2
SR		 3993 } else {
3994 u32 dropped_db = t4_read_reg(adap, 0x010ac);
3995 u16 qid = (dropped_db >> 15) & 0x1ffff;
3996 u16 pidx_inc = dropped_db & 0x1fff;
3997 unsigned int s_qpp;
3998 unsigned short udb_density;
3999 unsigned long qpshift;
4000 int page;
4001 u32 udb;
4002
4003 dev_warn(adap->pdev_dev,
4004 "Dropped DB 0x%x qid %d bar2 %d coalesce %d pidx %d\n",
4005 dropped_db, qid,
4006 (dropped_db >> 14) & 1,
4007 (dropped_db >> 13) & 1,
4008 pidx_inc);
4009
4010 drain_db_fifo(adap, 1);
4011
4012 s_qpp = QUEUESPERPAGEPF1 * adap->fn;
4013 udb_density = 1 << QUEUESPERPAGEPF0_GET(t4_read_reg(adap,
4014 SGE_EGRESS_QUEUES_PER_PAGE_PF) >> s_qpp);
4015 qpshift = PAGE_SHIFT - ilog2(udb_density);
4016 udb = qid << qpshift;
4017 udb &= PAGE_MASK;
4018 page = udb / PAGE_SIZE;
4019 udb += (qid - (page * udb_density)) * 128;
4020
4021 writel(PIDX(pidx_inc), adap->bar2 + udb + 8);
4022
4023 /* Re-enable BAR2 WC */
4024 t4_set_reg_field(adap, 0x10b0, 1<<15, 1<<15);
4025 }
4026
3069ee9b 4027 t4_set_reg_field(adap, A_SGE_DOORBELL_CONTROL, F_DROPPED_DB, 0);
881806bc
VP		 4028}
4029
4030void t4_db_full(struct adapter *adap)
4031{
d14807dd 4032 if (is_t4(adap->params.chip)) {
05eb2389
SW		 4033 disable_dbs(adap);
4034 notify_rdma_uld(adap, CXGB4_CONTROL_DB_FULL);
2cc301d2
SR		 4035 t4_set_reg_field(adap, SGE_INT_ENABLE3,
4036 DBFIFO_HP_INT | DBFIFO_LP_INT, 0);
4037 queue_work(workq, &adap->db_full_task);
4038 }
881806bc
VP		 4039}
4040
4041void t4_db_dropped(struct adapter *adap)
4042{
05eb2389
SW		 4043 if (is_t4(adap->params.chip)) {
4044 disable_dbs(adap);
4045 notify_rdma_uld(adap, CXGB4_CONTROL_DB_FULL);
4046 }
4047 queue_work(workq, &adap->db_drop_task);
881806bc
VP		 4048}
4049
b8ff05a9
DM		 4050static void uld_attach(struct adapter *adap, unsigned int uld)
4051{
4052 void *handle;
4053 struct cxgb4_lld_info lli;
dca4faeb 4054 unsigned short i;
b8ff05a9
DM		 4055
4056 lli.pdev = adap->pdev;
35b1de55 4057 lli.pf = adap->fn;
b8ff05a9
DM		 4058 lli.l2t = adap->l2t;
4059 lli.tids = &adap->tids;
4060 lli.ports = adap->port;
4061 lli.vr = &adap->vres;
4062 lli.mtus = adap->params.mtus;
4063 if (uld == CXGB4_ULD_RDMA) {
4064 lli.rxq_ids = adap->sge.rdma_rxq;
cf38be6d 4065 lli.ciq_ids = adap->sge.rdma_ciq;
b8ff05a9 4066 lli.nrxq = adap->sge.rdmaqs;
cf38be6d 4067 lli.nciq = adap->sge.rdmaciqs;
b8ff05a9
DM		 4068 } else if (uld == CXGB4_ULD_ISCSI) {
4069 lli.rxq_ids = adap->sge.ofld_rxq;
4070 lli.nrxq = adap->sge.ofldqsets;
4071 }
4072 lli.ntxq = adap->sge.ofldqsets;
4073 lli.nchan = adap->params.nports;
4074 lli.nports = adap->params.nports;
4075 lli.wr_cred = adap->params.ofldq_wr_cred;
d14807dd 4076 lli.adapter_type = adap->params.chip;
b8ff05a9
DM		 4077 lli.iscsi_iolen = MAXRXDATA_GET(t4_read_reg(adap, TP_PARA_REG2));
4078 lli.udb_density = 1 << QUEUESPERPAGEPF0_GET(
060e0c75
DM		 4079 t4_read_reg(adap, SGE_EGRESS_QUEUES_PER_PAGE_PF) >>
4080 (adap->fn * 4));
b8ff05a9 4081 lli.ucq_density = 1 << QUEUESPERPAGEPF0_GET(
060e0c75
DM		 4082 t4_read_reg(adap, SGE_INGRESS_QUEUES_PER_PAGE_PF) >>
4083 (adap->fn * 4));
dcf7b6f5 4084 lli.filt_mode = adap->params.tp.vlan_pri_map;
dca4faeb
VP		 4085 /* MODQ_REQ_MAP sets queues 0-3 to chan 0-3 */
4086 for (i = 0; i < NCHAN; i++)
4087 lli.tx_modq[i] = i;
b8ff05a9
DM		 4088 lli.gts_reg = adap->regs + MYPF_REG(SGE_PF_GTS);
4089 lli.db_reg = adap->regs + MYPF_REG(SGE_PF_KDOORBELL);
4090 lli.fw_vers = adap->params.fw_vers;
3069ee9b 4091 lli.dbfifo_int_thresh = dbfifo_int_thresh;
dca4faeb
VP		 4092 lli.sge_pktshift = adap->sge.pktshift;
4093 lli.enable_fw_ofld_conn = adap->flags & FW_OFLD_CONN;
1ac0f095 4094 lli.ulptx_memwrite_dsgl = adap->params.ulptx_memwrite_dsgl;
b8ff05a9
DM		 4095
4096 handle = ulds[uld].add(&lli);
4097 if (IS_ERR(handle)) {
4098 dev_warn(adap->pdev_dev,
4099 "could not attach to the %s driver, error %ld\n",
4100 uld_str[uld], PTR_ERR(handle));
4101 return;
4102 }
4103
4104 adap->uld_handle[uld] = handle;
4105
4106 if (!netevent_registered) {
4107 register_netevent_notifier(&cxgb4_netevent_nb);
4108 netevent_registered = true;
4109 }
e29f5dbc
DM		 4110
4111 if (adap->flags & FULL_INIT_DONE)
4112 ulds[uld].state_change(handle, CXGB4_STATE_UP);
b8ff05a9
DM		 4113}
4114
4115static void attach_ulds(struct adapter *adap)
4116{
4117 unsigned int i;
4118
01bcca68
VP		 4119 spin_lock(&adap_rcu_lock);
4120 list_add_tail_rcu(&adap->rcu_node, &adap_rcu_list);
4121 spin_unlock(&adap_rcu_lock);
4122
b8ff05a9
DM		 4123 mutex_lock(&uld_mutex);
4124 list_add_tail(&adap->list_node, &adapter_list);
4125 for (i = 0; i < CXGB4_ULD_MAX; i++)
4126 if (ulds[i].add)
4127 uld_attach(adap, i);
4128 mutex_unlock(&uld_mutex);
4129}
4130
4131static void detach_ulds(struct adapter *adap)
4132{
4133 unsigned int i;
4134
4135 mutex_lock(&uld_mutex);
4136 list_del(&adap->list_node);
4137 for (i = 0; i < CXGB4_ULD_MAX; i++)
4138 if (adap->uld_handle[i]) {
4139 ulds[i].state_change(adap->uld_handle[i],
4140 CXGB4_STATE_DETACH);
4141 adap->uld_handle[i] = NULL;
4142 }
4143 if (netevent_registered && list_empty(&adapter_list)) {
4144 unregister_netevent_notifier(&cxgb4_netevent_nb);
4145 netevent_registered = false;
4146 }
4147 mutex_unlock(&uld_mutex);
01bcca68
VP		 4148
4149 spin_lock(&adap_rcu_lock);
4150 list_del_rcu(&adap->rcu_node);
4151 spin_unlock(&adap_rcu_lock);
b8ff05a9
DM		 4152}
4153
4154static void notify_ulds(struct adapter *adap, enum cxgb4_state new_state)
4155{
4156 unsigned int i;
4157
4158 mutex_lock(&uld_mutex);
4159 for (i = 0; i < CXGB4_ULD_MAX; i++)
4160 if (adap->uld_handle[i])
4161 ulds[i].state_change(adap->uld_handle[i], new_state);
4162 mutex_unlock(&uld_mutex);
4163}
4164
4165/**
4166 * cxgb4_register_uld - register an upper-layer driver
4167 * @type: the ULD type
4168 * @p: the ULD methods
4169 *
4170 * Registers an upper-layer driver with this driver and notifies the ULD
4171 * about any presently available devices that support its type. Returns
4172 * %-EBUSY if a ULD of the same type is already registered.
4173 */
4174int cxgb4_register_uld(enum cxgb4_uld type, const struct cxgb4_uld_info *p)
4175{
4176 int ret = 0;
4177 struct adapter *adap;
4178
4179 if (type >= CXGB4_ULD_MAX)
4180 return -EINVAL;
4181 mutex_lock(&uld_mutex);
4182 if (ulds[type].add) {
4183 ret = -EBUSY;
4184 goto out;
4185 }
4186 ulds[type] = *p;
4187 list_for_each_entry(adap, &adapter_list, list_node)
4188 uld_attach(adap, type);
4189out: mutex_unlock(&uld_mutex);
4190 return ret;
4191}
4192EXPORT_SYMBOL(cxgb4_register_uld);
4193
4194/**
4195 * cxgb4_unregister_uld - unregister an upper-layer driver
4196 * @type: the ULD type
4197 *
4198 * Unregisters an existing upper-layer driver.
4199 */
4200int cxgb4_unregister_uld(enum cxgb4_uld type)
4201{
4202 struct adapter *adap;
4203
4204 if (type >= CXGB4_ULD_MAX)
4205 return -EINVAL;
4206 mutex_lock(&uld_mutex);
4207 list_for_each_entry(adap, &adapter_list, list_node)
4208 adap->uld_handle[type] = NULL;
4209 ulds[type].add = NULL;
4210 mutex_unlock(&uld_mutex);
4211 return 0;
4212}
4213EXPORT_SYMBOL(cxgb4_unregister_uld);
4214
01bcca68 4215/* Check if netdev on which event is occured belongs to us or not. Return
ee9a33b2
LR		 4216 * success (true) if it belongs otherwise failure (false).
4217 * Called with rcu_read_lock() held.
01bcca68 4218 */
ee9a33b2 4219static bool cxgb4_netdev(const struct net_device *netdev)
01bcca68
VP		 4220{
4221 struct adapter *adap;
4222 int i;
4223
01bcca68
VP		 4224 list_for_each_entry_rcu(adap, &adap_rcu_list, rcu_node)
4225 for (i = 0; i < MAX_NPORTS; i++)
ee9a33b2
LR		 4226 if (adap->port[i] == netdev)
4227 return true;
4228 return false;
01bcca68
VP		 4229}
4230
4231static int clip_add(struct net_device *event_dev, struct inet6_ifaddr *ifa,
4232 unsigned long event)
4233{
4234 int ret = NOTIFY_DONE;
4235
4236 rcu_read_lock();
4237 if (cxgb4_netdev(event_dev)) {
4238 switch (event) {
4239 case NETDEV_UP:
4240 ret = cxgb4_clip_get(event_dev,
4241 (const struct in6_addr *)ifa->addr.s6_addr);
4242 if (ret < 0) {
4243 rcu_read_unlock();
4244 return ret;
4245 }
4246 ret = NOTIFY_OK;
4247 break;
4248 case NETDEV_DOWN:
4249 cxgb4_clip_release(event_dev,
4250 (const struct in6_addr *)ifa->addr.s6_addr);
4251 ret = NOTIFY_OK;
4252 break;
4253 default:
4254 break;
4255 }
4256 }
4257 rcu_read_unlock();
4258 return ret;
4259}
4260
4261static int cxgb4_inet6addr_handler(struct notifier_block *this,
4262 unsigned long event, void *data)
4263{
4264 struct inet6_ifaddr *ifa = data;
4265 struct net_device *event_dev;
4266 int ret = NOTIFY_DONE;
01bcca68 4267 struct bonding *bond = netdev_priv(ifa->idev->dev);
9caff1e7 4268 struct list_head *iter;
01bcca68
VP		 4269 struct slave *slave;
4270 struct pci_dev *first_pdev = NULL;
4271
4272 if (ifa->idev->dev->priv_flags & IFF_802_1Q_VLAN) {
4273 event_dev = vlan_dev_real_dev(ifa->idev->dev);
4274 ret = clip_add(event_dev, ifa, event);
4275 } else if (ifa->idev->dev->flags & IFF_MASTER) {
4276 /* It is possible that two different adapters are bonded in one
4277 * bond. We need to find such different adapters and add clip
4278 * in all of them only once.
4279 */
4280 read_lock(&bond->lock);
9caff1e7 4281 bond_for_each_slave(bond, slave, iter) {
01bcca68
VP		 4282 if (!first_pdev) {
4283 ret = clip_add(slave->dev, ifa, event);
4284 /* If clip_add is success then only initialize
4285 * first_pdev since it means it is our device
4286 */
4287 if (ret == NOTIFY_OK)
4288 first_pdev = to_pci_dev(
4289 slave->dev->dev.parent);
4290 } else if (first_pdev !=
4291 to_pci_dev(slave->dev->dev.parent))
4292 ret = clip_add(slave->dev, ifa, event);
4293 }
4294 read_unlock(&bond->lock);
4295 } else
4296 ret = clip_add(ifa->idev->dev, ifa, event);
4297
4298 return ret;
4299}
4300
4301static struct notifier_block cxgb4_inet6addr_notifier = {
4302 .notifier_call = cxgb4_inet6addr_handler
4303};
4304
4305/* Retrieves IPv6 addresses from a root device (bond, vlan) associated with
4306 * a physical device.
4307 * The physical device reference is needed to send the actul CLIP command.
4308 */
4309static int update_dev_clip(struct net_device *root_dev, struct net_device *dev)
4310{
4311 struct inet6_dev *idev = NULL;
4312 struct inet6_ifaddr *ifa;
4313 int ret = 0;
4314
4315 idev = __in6_dev_get(root_dev);
4316 if (!idev)
4317 return ret;
4318
4319 read_lock_bh(&idev->lock);
4320 list_for_each_entry(ifa, &idev->addr_list, if_list) {
4321 ret = cxgb4_clip_get(dev,
4322 (const struct in6_addr *)ifa->addr.s6_addr);
4323 if (ret < 0)
4324 break;
4325 }
4326 read_unlock_bh(&idev->lock);
4327
4328 return ret;
4329}
4330
4331static int update_root_dev_clip(struct net_device *dev)
4332{
4333 struct net_device *root_dev = NULL;
4334 int i, ret = 0;
4335
4336 /* First populate the real net device's IPv6 addresses */
4337 ret = update_dev_clip(dev, dev);
4338 if (ret)
4339 return ret;
4340
4341 /* Parse all bond and vlan devices layered on top of the physical dev */
4342 for (i = 0; i < VLAN_N_VID; i++) {
f06c7f9f 4343 root_dev = __vlan_find_dev_deep_rcu(dev, htons(ETH_P_8021Q), i);
01bcca68
VP		 4344 if (!root_dev)
4345 continue;
4346
4347 ret = update_dev_clip(root_dev, dev);
4348 if (ret)
4349 break;
4350 }
4351 return ret;
4352}
4353
4354static void update_clip(const struct adapter *adap)
4355{
4356 int i;
4357 struct net_device *dev;
4358 int ret;
4359
4360 rcu_read_lock();
4361
4362 for (i = 0; i < MAX_NPORTS; i++) {
4363 dev = adap->port[i];
4364 ret = 0;
4365
4366 if (dev)
4367 ret = update_root_dev_clip(dev);
4368
4369 if (ret < 0)
4370 break;
4371 }
4372 rcu_read_unlock();
4373}
4374
b8ff05a9
DM		 4375/**
4376 * cxgb_up - enable the adapter
4377 * @adap: adapter being enabled
4378 *
4379 * Called when the first port is enabled, this function performs the
4380 * actions necessary to make an adapter operational, such as completing
4381 * the initialization of HW modules, and enabling interrupts.
4382 *
4383 * Must be called with the rtnl lock held.
4384 */
4385static int cxgb_up(struct adapter *adap)
4386{
aaefae9b 4387 int err;
b8ff05a9 4388
aaefae9b
DM		 4389 err = setup_sge_queues(adap);
4390 if (err)
4391 goto out;
4392 err = setup_rss(adap);
4393 if (err)
4394 goto freeq;
b8ff05a9
DM		 4395
4396 if (adap->flags & USING_MSIX) {
aaefae9b 4397 name_msix_vecs(adap);
b8ff05a9
DM		 4398 err = request_irq(adap->msix_info[0].vec, t4_nondata_intr, 0,
4399 adap->msix_info[0].desc, adap);
4400 if (err)
4401 goto irq_err;
4402
4403 err = request_msix_queue_irqs(adap);
4404 if (err) {
4405 free_irq(adap->msix_info[0].vec, adap);
4406 goto irq_err;
4407 }
4408 } else {
4409 err = request_irq(adap->pdev->irq, t4_intr_handler(adap),
4410 (adap->flags & USING_MSI) ? 0 : IRQF_SHARED,
b1a3c2b6 4411 adap->port[0]->name, adap);
b8ff05a9
DM		 4412 if (err)
4413 goto irq_err;
4414 }
4415 enable_rx(adap);
4416 t4_sge_start(adap);
4417 t4_intr_enable(adap);
aaefae9b 4418 adap->flags |= FULL_INIT_DONE;
b8ff05a9 4419 notify_ulds(adap, CXGB4_STATE_UP);
01bcca68 4420 update_clip(adap);
b8ff05a9
DM		 4421 out:
4422 return err;
4423 irq_err:
4424 dev_err(adap->pdev_dev, "request_irq failed, err %d\n", err);
aaefae9b
DM		 4425 freeq:
4426 t4_free_sge_resources(adap);
b8ff05a9
DM		 4427 goto out;
4428}
4429
4430static void cxgb_down(struct adapter *adapter)
4431{
4432 t4_intr_disable(adapter);
4433 cancel_work_sync(&adapter->tid_release_task);
881806bc
VP		 4434 cancel_work_sync(&adapter->db_full_task);
4435 cancel_work_sync(&adapter->db_drop_task);
b8ff05a9 4436 adapter->tid_release_task_busy = false;
204dc3c0 4437 adapter->tid_release_head = NULL;
b8ff05a9
DM		 4438
4439 if (adapter->flags & USING_MSIX) {
4440 free_msix_queue_irqs(adapter);
4441 free_irq(adapter->msix_info[0].vec, adapter);
4442 } else
4443 free_irq(adapter->pdev->irq, adapter);
4444 quiesce_rx(adapter);
aaefae9b
DM		 4445 t4_sge_stop(adapter);
4446 t4_free_sge_resources(adapter);
4447 adapter->flags &= ~FULL_INIT_DONE;
b8ff05a9
DM		 4448}
4449
4450/*
4451 * net_device operations
4452 */
4453static int cxgb_open(struct net_device *dev)
4454{
4455 int err;
4456 struct port_info *pi = netdev_priv(dev);
4457 struct adapter *adapter = pi->adapter;
4458
6a3c869a
DM		 4459 netif_carrier_off(dev);
4460
aaefae9b
DM		 4461 if (!(adapter->flags & FULL_INIT_DONE)) {
4462 err = cxgb_up(adapter);
4463 if (err < 0)
4464 return err;
4465 }
b8ff05a9 4466
f68707b8
DM		 4467 err = link_start(dev);
4468 if (!err)
4469 netif_tx_start_all_queues(dev);
4470 return err;
b8ff05a9
DM		 4471}
4472
4473static int cxgb_close(struct net_device *dev)
4474{
b8ff05a9
DM		 4475 struct port_info *pi = netdev_priv(dev);
4476 struct adapter *adapter = pi->adapter;
4477
4478 netif_tx_stop_all_queues(dev);
4479 netif_carrier_off(dev);
060e0c75 4480 return t4_enable_vi(adapter, adapter->fn, pi->viid, false, false);
b8ff05a9
DM		 4481}
4482
f2b7e78d
VP		 4483/* Return an error number if the indicated filter isn't writable ...
4484 */
4485static int writable_filter(struct filter_entry *f)
4486{
4487 if (f->locked)
4488 return -EPERM;
4489 if (f->pending)
4490 return -EBUSY;
4491
4492 return 0;
4493}
4494
4495/* Delete the filter at the specified index (if valid). The checks for all
4496 * the common problems with doing this like the filter being locked, currently
4497 * pending in another operation, etc.
4498 */
4499static int delete_filter(struct adapter *adapter, unsigned int fidx)
4500{
4501 struct filter_entry *f;
4502 int ret;
4503
dca4faeb 4504 if (fidx >= adapter->tids.nftids + adapter->tids.nsftids)
f2b7e78d
VP		 4505 return -EINVAL;
4506
4507 f = &adapter->tids.ftid_tab[fidx];
4508 ret = writable_filter(f);
4509 if (ret)
4510 return ret;
4511 if (f->valid)
4512 return del_filter_wr(adapter, fidx);
4513
4514 return 0;
4515}
4516
dca4faeb 4517int cxgb4_create_server_filter(const struct net_device *dev, unsigned int stid,
793dad94
VP		 4518 __be32 sip, __be16 sport, __be16 vlan,
4519 unsigned int queue, unsigned char port, unsigned char mask)
dca4faeb
VP		 4520{
4521 int ret;
4522 struct filter_entry *f;
4523 struct adapter *adap;
4524 int i;
4525 u8 *val;
4526
4527 adap = netdev2adap(dev);
4528
1cab775c 4529 /* Adjust stid to correct filter index */
470c60c4 4530 stid -= adap->tids.sftid_base;
1cab775c
VP		 4531 stid += adap->tids.nftids;
4532
dca4faeb
VP		 4533 /* Check to make sure the filter requested is writable ...
4534 */
4535 f = &adap->tids.ftid_tab[stid];
4536 ret = writable_filter(f);
4537 if (ret)
4538 return ret;
4539
4540 /* Clear out any old resources being used by the filter before
4541 * we start constructing the new filter.
4542 */
4543 if (f->valid)
4544 clear_filter(adap, f);
4545
4546 /* Clear out filter specifications */
4547 memset(&f->fs, 0, sizeof(struct ch_filter_specification));
4548 f->fs.val.lport = cpu_to_be16(sport);
4549 f->fs.mask.lport = ~0;
4550 val = (u8 *)&sip;
793dad94 4551 if ((val[0] | val[1] | val[2] | val[3]) != 0) {
dca4faeb
VP		 4552 for (i = 0; i < 4; i++) {
4553 f->fs.val.lip[i] = val[i];
4554 f->fs.mask.lip[i] = ~0;
4555 }
dcf7b6f5 4556 if (adap->params.tp.vlan_pri_map & F_PORT) {
793dad94
VP		 4557 f->fs.val.iport = port;
4558 f->fs.mask.iport = mask;
4559 }
4560 }
dca4faeb 4561
dcf7b6f5 4562 if (adap->params.tp.vlan_pri_map & F_PROTOCOL) {
7c89e555
KS		 4563 f->fs.val.proto = IPPROTO_TCP;
4564 f->fs.mask.proto = ~0;
4565 }
4566
dca4faeb
VP		 4567 f->fs.dirsteer = 1;
4568 f->fs.iq = queue;
4569 /* Mark filter as locked */
4570 f->locked = 1;
4571 f->fs.rpttid = 1;
4572
4573 ret = set_filter_wr(adap, stid);
4574 if (ret) {
4575 clear_filter(adap, f);
4576 return ret;
4577 }
4578
4579 return 0;
4580}
4581EXPORT_SYMBOL(cxgb4_create_server_filter);
4582
4583int cxgb4_remove_server_filter(const struct net_device *dev, unsigned int stid,
4584 unsigned int queue, bool ipv6)
4585{
4586 int ret;
4587 struct filter_entry *f;
4588 struct adapter *adap;
4589
4590 adap = netdev2adap(dev);
1cab775c
VP		 4591
4592 /* Adjust stid to correct filter index */
470c60c4 4593 stid -= adap->tids.sftid_base;
1cab775c
VP		 4594 stid += adap->tids.nftids;
4595
dca4faeb
VP		 4596 f = &adap->tids.ftid_tab[stid];
4597 /* Unlock the filter */
4598 f->locked = 0;
4599
4600 ret = delete_filter(adap, stid);
4601 if (ret)
4602 return ret;
4603
4604 return 0;
4605}
4606EXPORT_SYMBOL(cxgb4_remove_server_filter);
4607
f5152c90
DM		 4608static struct rtnl_link_stats64 *cxgb_get_stats(struct net_device *dev,
4609 struct rtnl_link_stats64 *ns)
b8ff05a9
DM		 4610{
4611 struct port_stats stats;
4612 struct port_info *p = netdev_priv(dev);
4613 struct adapter *adapter = p->adapter;
b8ff05a9 4614
9fe6cb58
GS		 4615 /* Block retrieving statistics during EEH error
4616 * recovery. Otherwise, the recovery might fail
4617 * and the PCI device will be removed permanently
4618 */
b8ff05a9 4619 spin_lock(&adapter->stats_lock);
9fe6cb58
GS		 4620 if (!netif_device_present(dev)) {
4621 spin_unlock(&adapter->stats_lock);
4622 return ns;
4623 }
b8ff05a9
DM		 4624 t4_get_port_stats(adapter, p->tx_chan, &stats);
4625 spin_unlock(&adapter->stats_lock);
4626
4627 ns->tx_bytes = stats.tx_octets;
4628 ns->tx_packets = stats.tx_frames;
4629 ns->rx_bytes = stats.rx_octets;
4630 ns->rx_packets = stats.rx_frames;
4631 ns->multicast = stats.rx_mcast_frames;
4632
4633 /* detailed rx_errors */
4634 ns->rx_length_errors = stats.rx_jabber + stats.rx_too_long +
4635 stats.rx_runt;
4636 ns->rx_over_errors = 0;
4637 ns->rx_crc_errors = stats.rx_fcs_err;
4638 ns->rx_frame_errors = stats.rx_symbol_err;
4639 ns->rx_fifo_errors = stats.rx_ovflow0 + stats.rx_ovflow1 +
4640 stats.rx_ovflow2 + stats.rx_ovflow3 +
4641 stats.rx_trunc0 + stats.rx_trunc1 +
4642 stats.rx_trunc2 + stats.rx_trunc3;
4643 ns->rx_missed_errors = 0;
4644
4645 /* detailed tx_errors */
4646 ns->tx_aborted_errors = 0;
4647 ns->tx_carrier_errors = 0;
4648 ns->tx_fifo_errors = 0;
4649 ns->tx_heartbeat_errors = 0;
4650 ns->tx_window_errors = 0;
4651
4652 ns->tx_errors = stats.tx_error_frames;
4653 ns->rx_errors = stats.rx_symbol_err + stats.rx_fcs_err +
4654 ns->rx_length_errors + stats.rx_len_err + ns->rx_fifo_errors;
4655 return ns;
4656}
4657
4658static int cxgb_ioctl(struct net_device *dev, struct ifreq *req, int cmd)
4659{
060e0c75 4660 unsigned int mbox;
b8ff05a9
DM		 4661 int ret = 0, prtad, devad;
4662 struct port_info *pi = netdev_priv(dev);
4663 struct mii_ioctl_data *data = (struct mii_ioctl_data *)&req->ifr_data;
4664
4665 switch (cmd) {
4666 case SIOCGMIIPHY:
4667 if (pi->mdio_addr < 0)
4668 return -EOPNOTSUPP;
4669 data->phy_id = pi->mdio_addr;
4670 break;
4671 case SIOCGMIIREG:
4672 case SIOCSMIIREG:
4673 if (mdio_phy_id_is_c45(data->phy_id)) {
4674 prtad = mdio_phy_id_prtad(data->phy_id);
4675 devad = mdio_phy_id_devad(data->phy_id);
4676 } else if (data->phy_id < 32) {
4677 prtad = data->phy_id;
4678 devad = 0;
4679 data->reg_num &= 0x1f;
4680 } else
4681 return -EINVAL;
4682
060e0c75 4683 mbox = pi->adapter->fn;
b8ff05a9 4684 if (cmd == SIOCGMIIREG)
060e0c75 4685 ret = t4_mdio_rd(pi->adapter, mbox, prtad, devad,
b8ff05a9
DM		 4686 data->reg_num, &data->val_out);
4687 else
060e0c75 4688 ret = t4_mdio_wr(pi->adapter, mbox, prtad, devad,
b8ff05a9
DM		 4689 data->reg_num, data->val_in);
4690 break;
4691 default:
4692 return -EOPNOTSUPP;
4693 }
4694 return ret;
4695}
4696
4697static void cxgb_set_rxmode(struct net_device *dev)
4698{
4699 /* unfortunately we can't return errors to the stack */
4700 set_rxmode(dev, -1, false);
4701}
4702
4703static int cxgb_change_mtu(struct net_device *dev, int new_mtu)
4704{
4705 int ret;
4706 struct port_info *pi = netdev_priv(dev);
4707
4708 if (new_mtu < 81 || new_mtu > MAX_MTU) /* accommodate SACK */
4709 return -EINVAL;
060e0c75
DM		 4710 ret = t4_set_rxmode(pi->adapter, pi->adapter->fn, pi->viid, new_mtu, -1,
4711 -1, -1, -1, true);
b8ff05a9
DM		 4712 if (!ret)
4713 dev->mtu = new_mtu;
4714 return ret;
4715}
4716
4717static int cxgb_set_mac_addr(struct net_device *dev, void *p)
4718{
4719 int ret;
4720 struct sockaddr *addr = p;
4721 struct port_info *pi = netdev_priv(dev);
4722
4723 if (!is_valid_ether_addr(addr->sa_data))
504f9b5a 4724 return -EADDRNOTAVAIL;
b8ff05a9 4725
060e0c75
DM		 4726 ret = t4_change_mac(pi->adapter, pi->adapter->fn, pi->viid,
4727 pi->xact_addr_filt, addr->sa_data, true, true);
b8ff05a9
DM		 4728 if (ret < 0)
4729 return ret;
4730
4731 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
4732 pi->xact_addr_filt = ret;
4733 return 0;
4734}
4735
b8ff05a9
DM		 4736#ifdef CONFIG_NET_POLL_CONTROLLER
4737static void cxgb_netpoll(struct net_device *dev)
4738{
4739 struct port_info *pi = netdev_priv(dev);
4740 struct adapter *adap = pi->adapter;
4741
4742 if (adap->flags & USING_MSIX) {
4743 int i;
4744 struct sge_eth_rxq *rx = &adap->sge.ethrxq[pi->first_qset];
4745
4746 for (i = pi->nqsets; i; i--, rx++)
4747 t4_sge_intr_msix(0, &rx->rspq);
4748 } else
4749 t4_intr_handler(adap)(0, adap);
4750}
4751#endif
4752
4753static const struct net_device_ops cxgb4_netdev_ops = {
4754 .ndo_open = cxgb_open,
4755 .ndo_stop = cxgb_close,
4756 .ndo_start_xmit = t4_eth_xmit,
688848b1 4757 .ndo_select_queue = cxgb_select_queue,
9be793bf 4758 .ndo_get_stats64 = cxgb_get_stats,
b8ff05a9
DM		 4759 .ndo_set_rx_mode = cxgb_set_rxmode,
4760 .ndo_set_mac_address = cxgb_set_mac_addr,
2ed28baa 4761 .ndo_set_features = cxgb_set_features,
b8ff05a9
DM		 4762 .ndo_validate_addr = eth_validate_addr,
4763 .ndo_do_ioctl = cxgb_ioctl,
4764 .ndo_change_mtu = cxgb_change_mtu,
b8ff05a9
DM		 4765#ifdef CONFIG_NET_POLL_CONTROLLER
4766 .ndo_poll_controller = cxgb_netpoll,
4767#endif
4768};
4769
4770void t4_fatal_err(struct adapter *adap)
4771{
4772 t4_set_reg_field(adap, SGE_CONTROL, GLOBALENABLE, 0);
4773 t4_intr_disable(adap);
4774 dev_alert(adap->pdev_dev, "encountered fatal error, adapter stopped\n");
4775}
4776
0abfd152
HS		 4777/* Return the specified PCI-E Configuration Space register from our Physical
4778 * Function. We try first via a Firmware LDST Command since we prefer to let
4779 * the firmware own all of these registers, but if that fails we go for it
4780 * directly ourselves.
4781 */
4782static u32 t4_read_pcie_cfg4(struct adapter *adap, int reg)
4783{
4784 struct fw_ldst_cmd ldst_cmd;
4785 u32 val;
4786 int ret;
4787
4788 /* Construct and send the Firmware LDST Command to retrieve the
4789 * specified PCI-E Configuration Space register.
4790 */
4791 memset(&ldst_cmd, 0, sizeof(ldst_cmd));
4792 ldst_cmd.op_to_addrspace =
4793 htonl(FW_CMD_OP(FW_LDST_CMD) |
4794 FW_CMD_REQUEST |
4795 FW_CMD_READ |
4796 FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_FUNC_PCIE));
4797 ldst_cmd.cycles_to_len16 = htonl(FW_LEN16(ldst_cmd));
4798 ldst_cmd.u.pcie.select_naccess = FW_LDST_CMD_NACCESS(1);
4799 ldst_cmd.u.pcie.ctrl_to_fn =
4800 (FW_LDST_CMD_LC | FW_LDST_CMD_FN(adap->fn));
4801 ldst_cmd.u.pcie.r = reg;
4802 ret = t4_wr_mbox(adap, adap->mbox, &ldst_cmd, sizeof(ldst_cmd),
4803 &ldst_cmd);
4804
4805 /* If the LDST Command suucceeded, exctract the returned register
4806 * value. Otherwise read it directly ourself.
4807 */
4808 if (ret == 0)
4809 val = ntohl(ldst_cmd.u.pcie.data[0]);
4810 else
4811 t4_hw_pci_read_cfg4(adap, reg, &val);
4812
4813 return val;
4814}
4815
b8ff05a9
DM		 4816static void setup_memwin(struct adapter *adap)
4817{
0abfd152 4818 u32 mem_win0_base, mem_win1_base, mem_win2_base, mem_win2_aperture;
b8ff05a9 4819
d14807dd 4820 if (is_t4(adap->params.chip)) {
0abfd152
HS		 4821 u32 bar0;
4822
4823 /* Truncation intentional: we only read the bottom 32-bits of
4824 * the 64-bit BAR0/BAR1 ... We use the hardware backdoor
4825 * mechanism to read BAR0 instead of using
4826 * pci_resource_start() because we could be operating from
4827 * within a Virtual Machine which is trapping our accesses to
4828 * our Configuration Space and we need to set up the PCI-E
4829 * Memory Window decoders with the actual addresses which will
4830 * be coming across the PCI-E link.
4831 */
4832 bar0 = t4_read_pcie_cfg4(adap, PCI_BASE_ADDRESS_0);
4833 bar0 &= PCI_BASE_ADDRESS_MEM_MASK;
4834 adap->t4_bar0 = bar0;
4835
19dd37ba
SR		 4836 mem_win0_base = bar0 + MEMWIN0_BASE;
4837 mem_win1_base = bar0 + MEMWIN1_BASE;
4838 mem_win2_base = bar0 + MEMWIN2_BASE;
0abfd152 4839 mem_win2_aperture = MEMWIN2_APERTURE;
19dd37ba
SR		 4840 } else {
4841 /* For T5, only relative offset inside the PCIe BAR is passed */
4842 mem_win0_base = MEMWIN0_BASE;
0abfd152 4843 mem_win1_base = MEMWIN1_BASE;
19dd37ba 4844 mem_win2_base = MEMWIN2_BASE_T5;
0abfd152 4845 mem_win2_aperture = MEMWIN2_APERTURE_T5;
19dd37ba 4846 }
b8ff05a9 4847 t4_write_reg(adap, PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN, 0),
19dd37ba 4848 mem_win0_base | BIR(0) |
b8ff05a9
DM		 4849 WINDOW(ilog2(MEMWIN0_APERTURE) - 10));
4850 t4_write_reg(adap, PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN, 1),
19dd37ba 4851 mem_win1_base | BIR(0) |
b8ff05a9
DM		 4852 WINDOW(ilog2(MEMWIN1_APERTURE) - 10));
4853 t4_write_reg(adap, PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN, 2),
19dd37ba 4854 mem_win2_base | BIR(0) |
0abfd152
HS		 4855 WINDOW(ilog2(mem_win2_aperture) - 10));
4856 t4_read_reg(adap, PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN, 2));
636f9d37
VP		 4857}
4858
4859static void setup_memwin_rdma(struct adapter *adap)
4860{
1ae970e0 4861 if (adap->vres.ocq.size) {
0abfd152
HS		 4862 u32 start;
4863 unsigned int sz_kb;
1ae970e0 4864
0abfd152
HS		 4865 start = t4_read_pcie_cfg4(adap, PCI_BASE_ADDRESS_2);
4866 start &= PCI_BASE_ADDRESS_MEM_MASK;
4867 start += OCQ_WIN_OFFSET(adap->pdev, &adap->vres);
1ae970e0
DM		 4868 sz_kb = roundup_pow_of_two(adap->vres.ocq.size) >> 10;
4869 t4_write_reg(adap,
4870 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN, 3),
4871 start | BIR(1) | WINDOW(ilog2(sz_kb)));
4872 t4_write_reg(adap,
4873 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET, 3),
4874 adap->vres.ocq.start);
4875 t4_read_reg(adap,
4876 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET, 3));
4877 }
b8ff05a9
DM		 4878}
4879
02b5fb8e
DM		 4880static int adap_init1(struct adapter *adap, struct fw_caps_config_cmd *c)
4881{
4882 u32 v;
4883 int ret;
4884
4885 /* get device capabilities */
4886 memset(c, 0, sizeof(*c));
4887 c->op_to_write = htonl(FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
4888 FW_CMD_REQUEST | FW_CMD_READ);
ce91a923 4889 c->cfvalid_to_len16 = htonl(FW_LEN16(*c));
060e0c75 4890 ret = t4_wr_mbox(adap, adap->fn, c, sizeof(*c), c);
02b5fb8e
DM		 4891 if (ret < 0)
4892 return ret;
4893
4894 /* select capabilities we'll be using */
4895 if (c->niccaps & htons(FW_CAPS_CONFIG_NIC_VM)) {
4896 if (!vf_acls)
4897 c->niccaps ^= htons(FW_CAPS_CONFIG_NIC_VM);
4898 else
4899 c->niccaps = htons(FW_CAPS_CONFIG_NIC_VM);
4900 } else if (vf_acls) {
4901 dev_err(adap->pdev_dev, "virtualization ACLs not supported");
4902 return ret;
4903 }
4904 c->op_to_write = htonl(FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
4905 FW_CMD_REQUEST | FW_CMD_WRITE);
060e0c75 4906 ret = t4_wr_mbox(adap, adap->fn, c, sizeof(*c), NULL);
02b5fb8e
DM		 4907 if (ret < 0)
4908 return ret;
4909
060e0c75 4910 ret = t4_config_glbl_rss(adap, adap->fn,
02b5fb8e
DM		 4911 FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL,
4912 FW_RSS_GLB_CONFIG_CMD_TNLMAPEN |
4913 FW_RSS_GLB_CONFIG_CMD_TNLALLLKP);
4914 if (ret < 0)
4915 return ret;
4916
060e0c75
DM		 4917 ret = t4_cfg_pfvf(adap, adap->fn, adap->fn, 0, MAX_EGRQ, 64, MAX_INGQ,
4918 0, 0, 4, 0xf, 0xf, 16, FW_CMD_CAP_PF, FW_CMD_CAP_PF);
02b5fb8e
DM		 4919 if (ret < 0)
4920 return ret;
4921
4922 t4_sge_init(adap);
4923
02b5fb8e
DM		 4924 /* tweak some settings */
4925 t4_write_reg(adap, TP_SHIFT_CNT, 0x64f8849);
4926 t4_write_reg(adap, ULP_RX_TDDP_PSZ, HPZ0(PAGE_SHIFT - 12));
4927 t4_write_reg(adap, TP_PIO_ADDR, TP_INGRESS_CONFIG);
4928 v = t4_read_reg(adap, TP_PIO_DATA);
4929 t4_write_reg(adap, TP_PIO_DATA, v & ~CSUM_HAS_PSEUDO_HDR);
060e0c75 4930
dca4faeb
VP		 4931 /* first 4 Tx modulation queues point to consecutive Tx channels */
4932 adap->params.tp.tx_modq_map = 0xE4;
4933 t4_write_reg(adap, A_TP_TX_MOD_QUEUE_REQ_MAP,
4934 V_TX_MOD_QUEUE_REQ_MAP(adap->params.tp.tx_modq_map));
4935
4936 /* associate each Tx modulation queue with consecutive Tx channels */
4937 v = 0x84218421;
4938 t4_write_indirect(adap, TP_PIO_ADDR, TP_PIO_DATA,
4939 &v, 1, A_TP_TX_SCHED_HDR);
4940 t4_write_indirect(adap, TP_PIO_ADDR, TP_PIO_DATA,
4941 &v, 1, A_TP_TX_SCHED_FIFO);
4942 t4_write_indirect(adap, TP_PIO_ADDR, TP_PIO_DATA,
4943 &v, 1, A_TP_TX_SCHED_PCMD);
4944
4945#define T4_TX_MODQ_10G_WEIGHT_DEFAULT 16 /* in KB units */
4946 if (is_offload(adap)) {
4947 t4_write_reg(adap, A_TP_TX_MOD_QUEUE_WEIGHT0,
4948 V_TX_MODQ_WEIGHT0(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
4949 V_TX_MODQ_WEIGHT1(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
4950 V_TX_MODQ_WEIGHT2(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
4951 V_TX_MODQ_WEIGHT3(T4_TX_MODQ_10G_WEIGHT_DEFAULT));
4952 t4_write_reg(adap, A_TP_TX_MOD_CHANNEL_WEIGHT,
4953 V_TX_MODQ_WEIGHT0(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
4954 V_TX_MODQ_WEIGHT1(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
4955 V_TX_MODQ_WEIGHT2(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
4956 V_TX_MODQ_WEIGHT3(T4_TX_MODQ_10G_WEIGHT_DEFAULT));
4957 }
4958
060e0c75
DM		 4959 /* get basic stuff going */
4960 return t4_early_init(adap, adap->fn);
02b5fb8e
DM		 4961}
4962
b8ff05a9
DM		 4963/*
4964 * Max # of ATIDs. The absolute HW max is 16K but we keep it lower.
4965 */
4966#define MAX_ATIDS 8192U
4967
636f9d37
VP		 4968/*
4969 * Phase 0 of initialization: contact FW, obtain config, perform basic init.
4970 *
4971 * If the firmware we're dealing with has Configuration File support, then
4972 * we use that to perform all configuration
4973 */
4974
4975/*
4976 * Tweak configuration based on module parameters, etc. Most of these have
4977 * defaults assigned to them by Firmware Configuration Files (if we're using
4978 * them) but need to be explicitly set if we're using hard-coded
4979 * initialization. But even in the case of using Firmware Configuration
4980 * Files, we'd like to expose the ability to change these via module
4981 * parameters so these are essentially common tweaks/settings for
4982 * Configuration Files and hard-coded initialization ...
4983 */
4984static int adap_init0_tweaks(struct adapter *adapter)
4985{
4986 /*
4987 * Fix up various Host-Dependent Parameters like Page Size, Cache
4988 * Line Size, etc. The firmware default is for a 4KB Page Size and
4989 * 64B Cache Line Size ...
4990 */
4991 t4_fixup_host_params(adapter, PAGE_SIZE, L1_CACHE_BYTES);
4992
4993 /*
4994 * Process module parameters which affect early initialization.
4995 */
4996 if (rx_dma_offset != 2 && rx_dma_offset != 0) {
4997 dev_err(&adapter->pdev->dev,
4998 "Ignoring illegal rx_dma_offset=%d, using 2\n",
4999 rx_dma_offset);
5000 rx_dma_offset = 2;
5001 }
5002 t4_set_reg_field(adapter, SGE_CONTROL,
5003 PKTSHIFT_MASK,
5004 PKTSHIFT(rx_dma_offset));
5005
5006 /*
5007 * Don't include the "IP Pseudo Header" in CPL_RX_PKT checksums: Linux
5008 * adds the pseudo header itself.
5009 */
5010 t4_tp_wr_bits_indirect(adapter, TP_INGRESS_CONFIG,
5011 CSUM_HAS_PSEUDO_HDR, 0);
5012
5013 return 0;
5014}
5015
5016/*
5017 * Attempt to initialize the adapter via a Firmware Configuration File.
5018 */
5019static int adap_init0_config(struct adapter *adapter, int reset)
5020{
5021 struct fw_caps_config_cmd caps_cmd;
5022 const struct firmware *cf;
5023 unsigned long mtype = 0, maddr = 0;
5024 u32 finiver, finicsum, cfcsum;
16e47624
HS		 5025 int ret;
5026 int config_issued = 0;
0a57a536 5027 char *fw_config_file, fw_config_file_path[256];
16e47624 5028 char *config_name = NULL;
636f9d37
VP		 5029
5030 /*
5031 * Reset device if necessary.
5032 */
5033 if (reset) {
5034 ret = t4_fw_reset(adapter, adapter->mbox,
5035 PIORSTMODE | PIORST);
5036 if (ret < 0)
5037 goto bye;
5038 }
5039
5040 /*
5041 * If we have a T4 configuration file under /lib/firmware/cxgb4/,
5042 * then use that. Otherwise, use the configuration file stored
5043 * in the adapter flash ...
5044 */
d14807dd 5045 switch (CHELSIO_CHIP_VERSION(adapter->params.chip)) {
0a57a536 5046 case CHELSIO_T4:
16e47624 5047 fw_config_file = FW4_CFNAME;
0a57a536
SR		 5048 break;
5049 case CHELSIO_T5:
5050 fw_config_file = FW5_CFNAME;
5051 break;
5052 default:
5053 dev_err(adapter->pdev_dev, "Device %d is not supported\n",
5054 adapter->pdev->device);
5055 ret = -EINVAL;
5056 goto bye;
5057 }
5058
5059 ret = request_firmware(&cf, fw_config_file, adapter->pdev_dev);
636f9d37 5060 if (ret < 0) {
16e47624 5061 config_name = "On FLASH";
636f9d37
VP		 5062 mtype = FW_MEMTYPE_CF_FLASH;
5063 maddr = t4_flash_cfg_addr(adapter);
5064 } else {
5065 u32 params[7], val[7];
5066
16e47624
HS		 5067 sprintf(fw_config_file_path,
5068 "/lib/firmware/%s", fw_config_file);
5069 config_name = fw_config_file_path;
5070
636f9d37
VP		 5071 if (cf->size >= FLASH_CFG_MAX_SIZE)
5072 ret = -ENOMEM;
5073 else {
5074 params[0] = (FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
5075 FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_CF));
5076 ret = t4_query_params(adapter, adapter->mbox,
5077 adapter->fn, 0, 1, params, val);
5078 if (ret == 0) {
5079 /*
fc5ab020 5080 * For t4_memory_rw() below addresses and
636f9d37
VP		 5081 * sizes have to be in terms of multiples of 4
5082 * bytes. So, if the Configuration File isn't
5083 * a multiple of 4 bytes in length we'll have
5084 * to write that out separately since we can't
5085 * guarantee that the bytes following the
5086 * residual byte in the buffer returned by
5087 * request_firmware() are zeroed out ...
5088 */
5089 size_t resid = cf->size & 0x3;
5090 size_t size = cf->size & ~0x3;
5091 __be32 *data = (__be32 *)cf->data;
5092
5093 mtype = FW_PARAMS_PARAM_Y_GET(val[0]);
5094 maddr = FW_PARAMS_PARAM_Z_GET(val[0]) << 16;
5095
fc5ab020
HS		 5096 spin_lock(&adapter->win0_lock);
5097 ret = t4_memory_rw(adapter, 0, mtype, maddr,
5098 size, data, T4_MEMORY_WRITE);
636f9d37
VP		 5099 if (ret == 0 && resid != 0) {
5100 union {
5101 __be32 word;
5102 char buf[4];
5103 } last;
5104 int i;
5105
5106 last.word = data[size >> 2];
5107 for (i = resid; i < 4; i++)
5108 last.buf[i] = 0;
fc5ab020
HS		 5109 ret = t4_memory_rw(adapter, 0, mtype,
5110 maddr + size,
5111 4, &last.word,
5112 T4_MEMORY_WRITE);
636f9d37 5113 }
fc5ab020 5114 spin_unlock(&adapter->win0_lock);
636f9d37
VP		 5115 }
5116 }
5117
5118 release_firmware(cf);
5119 if (ret)
5120 goto bye;
5121 }
5122
5123 /*
5124 * Issue a Capability Configuration command to the firmware to get it
5125 * to parse the Configuration File. We don't use t4_fw_config_file()
5126 * because we want the ability to modify various features after we've
5127 * processed the configuration file ...
5128 */
5129 memset(&caps_cmd, 0, sizeof(caps_cmd));
5130 caps_cmd.op_to_write =
5131 htonl(FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
5132 FW_CMD_REQUEST |
5133 FW_CMD_READ);
ce91a923 5134 caps_cmd.cfvalid_to_len16 =
636f9d37
VP		 5135 htonl(FW_CAPS_CONFIG_CMD_CFVALID |
5136 FW_CAPS_CONFIG_CMD_MEMTYPE_CF(mtype) |
5137 FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(maddr >> 16) |
5138 FW_LEN16(caps_cmd));
5139 ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd, sizeof(caps_cmd),
5140 &caps_cmd);
16e47624
HS		 5141
5142 /* If the CAPS_CONFIG failed with an ENOENT (for a Firmware
5143 * Configuration File in FLASH), our last gasp effort is to use the
5144 * Firmware Configuration File which is embedded in the firmware. A
5145 * very few early versions of the firmware didn't have one embedded
5146 * but we can ignore those.
5147 */
5148 if (ret == -ENOENT) {
5149 memset(&caps_cmd, 0, sizeof(caps_cmd));
5150 caps_cmd.op_to_write =
5151 htonl(FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
5152 FW_CMD_REQUEST |
5153 FW_CMD_READ);
5154 caps_cmd.cfvalid_to_len16 = htonl(FW_LEN16(caps_cmd));
5155 ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd,
5156 sizeof(caps_cmd), &caps_cmd);
5157 config_name = "Firmware Default";
5158 }
5159
5160 config_issued = 1;
636f9d37
VP		 5161 if (ret < 0)
5162 goto bye;
5163
5164 finiver = ntohl(caps_cmd.finiver);
5165 finicsum = ntohl(caps_cmd.finicsum);
5166 cfcsum = ntohl(caps_cmd.cfcsum);
5167 if (finicsum != cfcsum)
5168 dev_warn(adapter->pdev_dev, "Configuration File checksum "\
5169 "mismatch: [fini] csum=%#x, computed csum=%#x\n",
5170 finicsum, cfcsum);
5171
636f9d37
VP		 5172 /*
5173 * And now tell the firmware to use the configuration we just loaded.
5174 */
5175 caps_cmd.op_to_write =
5176 htonl(FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
5177 FW_CMD_REQUEST |
5178 FW_CMD_WRITE);
ce91a923 5179 caps_cmd.cfvalid_to_len16 = htonl(FW_LEN16(caps_cmd));
636f9d37
VP		 5180 ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd, sizeof(caps_cmd),
5181 NULL);
5182 if (ret < 0)
5183 goto bye;
5184
5185 /*
5186 * Tweak configuration based on system architecture, module
5187 * parameters, etc.
5188 */
5189 ret = adap_init0_tweaks(adapter);
5190 if (ret < 0)
5191 goto bye;
5192
5193 /*
5194 * And finally tell the firmware to initialize itself using the
5195 * parameters from the Configuration File.
5196 */
5197 ret = t4_fw_initialize(adapter, adapter->mbox);
5198 if (ret < 0)
5199 goto bye;
5200
5201 /*
5202 * Return successfully and note that we're operating with parameters
5203 * not supplied by the driver, rather than from hard-wired
5204 * initialization constants burried in the driver.
5205 */
5206 adapter->flags |= USING_SOFT_PARAMS;
5207 dev_info(adapter->pdev_dev, "Successfully configured using Firmware "\
16e47624
HS		 5208 "Configuration File \"%s\", version %#x, computed checksum %#x\n",
5209 config_name, finiver, cfcsum);
636f9d37
VP		 5210 return 0;
5211
5212 /*
5213 * Something bad happened. Return the error ... (If the "error"
5214 * is that there's no Configuration File on the adapter we don't
5215 * want to issue a warning since this is fairly common.)
5216 */
5217bye:
16e47624
HS		 5218 if (config_issued && ret != -ENOENT)
5219 dev_warn(adapter->pdev_dev, "\"%s\" configuration file error %d\n",
5220 config_name, -ret);
636f9d37
VP		 5221 return ret;
5222}
5223
13ee15d3
VP		 5224/*
5225 * Attempt to initialize the adapter via hard-coded, driver supplied
5226 * parameters ...
5227 */
5228static int adap_init0_no_config(struct adapter *adapter, int reset)
5229{
5230 struct sge *s = &adapter->sge;
5231 struct fw_caps_config_cmd caps_cmd;
5232 u32 v;
5233 int i, ret;
5234
5235 /*
5236 * Reset device if necessary
5237 */
5238 if (reset) {
5239 ret = t4_fw_reset(adapter, adapter->mbox,
5240 PIORSTMODE | PIORST);
5241 if (ret < 0)
5242 goto bye;
5243 }
5244
5245 /*
5246 * Get device capabilities and select which we'll be using.
5247 */
5248 memset(&caps_cmd, 0, sizeof(caps_cmd));
5249 caps_cmd.op_to_write = htonl(FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
5250 FW_CMD_REQUEST | FW_CMD_READ);
ce91a923 5251 caps_cmd.cfvalid_to_len16 = htonl(FW_LEN16(caps_cmd));
13ee15d3
VP		 5252 ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd, sizeof(caps_cmd),
5253 &caps_cmd);
5254 if (ret < 0)
5255 goto bye;
5256
13ee15d3
VP		 5257 if (caps_cmd.niccaps & htons(FW_CAPS_CONFIG_NIC_VM)) {
5258 if (!vf_acls)
5259 caps_cmd.niccaps ^= htons(FW_CAPS_CONFIG_NIC_VM);
5260 else
5261 caps_cmd.niccaps = htons(FW_CAPS_CONFIG_NIC_VM);
5262 } else if (vf_acls) {
5263 dev_err(adapter->pdev_dev, "virtualization ACLs not supported");
5264 goto bye;
5265 }
5266 caps_cmd.op_to_write = htonl(FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
5267 FW_CMD_REQUEST | FW_CMD_WRITE);
5268 ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd, sizeof(caps_cmd),
5269 NULL);
5270 if (ret < 0)
5271 goto bye;
5272
5273 /*
5274 * Tweak configuration based on system architecture, module
5275 * parameters, etc.
5276 */
5277 ret = adap_init0_tweaks(adapter);
5278 if (ret < 0)
5279 goto bye;
5280
5281 /*
5282 * Select RSS Global Mode we want to use. We use "Basic Virtual"
5283 * mode which maps each Virtual Interface to its own section of
5284 * the RSS Table and we turn on all map and hash enables ...
5285 */
5286 adapter->flags |= RSS_TNLALLLOOKUP;
5287 ret = t4_config_glbl_rss(adapter, adapter->mbox,
5288 FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL,
5289 FW_RSS_GLB_CONFIG_CMD_TNLMAPEN |
5290 FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ |
5291 ((adapter->flags & RSS_TNLALLLOOKUP) ?
5292 FW_RSS_GLB_CONFIG_CMD_TNLALLLKP : 0));
5293 if (ret < 0)
5294 goto bye;
5295
5296 /*
5297 * Set up our own fundamental resource provisioning ...
5298 */
5299 ret = t4_cfg_pfvf(adapter, adapter->mbox, adapter->fn, 0,
5300 PFRES_NEQ, PFRES_NETHCTRL,
5301 PFRES_NIQFLINT, PFRES_NIQ,
5302 PFRES_TC, PFRES_NVI,
5303 FW_PFVF_CMD_CMASK_MASK,
5304 pfvfres_pmask(adapter, adapter->fn, 0),
5305 PFRES_NEXACTF,
5306 PFRES_R_CAPS, PFRES_WX_CAPS);
5307 if (ret < 0)
5308 goto bye;
5309
5310 /*
5311 * Perform low level SGE initialization. We need to do this before we
5312 * send the firmware the INITIALIZE command because that will cause
5313 * any other PF Drivers which are waiting for the Master
5314 * Initialization to proceed forward.
5315 */
5316 for (i = 0; i < SGE_NTIMERS - 1; i++)
5317 s->timer_val[i] = min(intr_holdoff[i], MAX_SGE_TIMERVAL);
5318 s->timer_val[SGE_NTIMERS - 1] = MAX_SGE_TIMERVAL;
5319 s->counter_val[0] = 1;
5320 for (i = 1; i < SGE_NCOUNTERS; i++)
5321 s->counter_val[i] = min(intr_cnt[i - 1],
5322 THRESHOLD_0_GET(THRESHOLD_0_MASK));
5323 t4_sge_init(adapter);
5324
5325#ifdef CONFIG_PCI_IOV
5326 /*
5327 * Provision resource limits for Virtual Functions. We currently
5328 * grant them all the same static resource limits except for the Port
5329 * Access Rights Mask which we're assigning based on the PF. All of
5330 * the static provisioning stuff for both the PF and VF really needs
5331 * to be managed in a persistent manner for each device which the
5332 * firmware controls.
5333 */
5334 {
5335 int pf, vf;
5336
7d6727cf 5337 for (pf = 0; pf < ARRAY_SIZE(num_vf); pf++) {
13ee15d3
VP		 5338 if (num_vf[pf] <= 0)
5339 continue;
5340
5341 /* VF numbering starts at 1! */
5342 for (vf = 1; vf <= num_vf[pf]; vf++) {
5343 ret = t4_cfg_pfvf(adapter, adapter->mbox,
5344 pf, vf,
5345 VFRES_NEQ, VFRES_NETHCTRL,
5346 VFRES_NIQFLINT, VFRES_NIQ,
5347 VFRES_TC, VFRES_NVI,
1f1e4958 5348 FW_PFVF_CMD_CMASK_MASK,
13ee15d3
VP		 5349 pfvfres_pmask(
5350 adapter, pf, vf),
5351 VFRES_NEXACTF,
5352 VFRES_R_CAPS, VFRES_WX_CAPS);
5353 if (ret < 0)
5354 dev_warn(adapter->pdev_dev,
5355 "failed to "\
5356 "provision pf/vf=%d/%d; "
5357 "err=%d\n", pf, vf, ret);
5358 }
5359 }
5360 }
5361#endif
5362
5363 /*
5364 * Set up the default filter mode. Later we'll want to implement this
5365 * via a firmware command, etc. ... This needs to be done before the
5366 * firmare initialization command ... If the selected set of fields
5367 * isn't equal to the default value, we'll need to make sure that the
5368 * field selections will fit in the 36-bit budget.
5369 */
5370 if (tp_vlan_pri_map != TP_VLAN_PRI_MAP_DEFAULT) {
404d9e3f 5371 int j, bits = 0;
13ee15d3 5372
404d9e3f
VP		 5373 for (j = TP_VLAN_PRI_MAP_FIRST; j <= TP_VLAN_PRI_MAP_LAST; j++)
5374 switch (tp_vlan_pri_map & (1 << j)) {
13ee15d3
VP		 5375 case 0:
5376 /* compressed filter field not enabled */
5377 break;
5378 case FCOE_MASK:
5379 bits += 1;
5380 break;
5381 case PORT_MASK:
5382 bits += 3;
5383 break;
5384 case VNIC_ID_MASK:
5385 bits += 17;
5386 break;
5387 case VLAN_MASK:
5388 bits += 17;
5389 break;
5390 case TOS_MASK:
5391 bits += 8;
5392 break;
5393 case PROTOCOL_MASK:
5394 bits += 8;
5395 break;
5396 case ETHERTYPE_MASK:
5397 bits += 16;
5398 break;
5399 case MACMATCH_MASK:
5400 bits += 9;
5401 break;
5402 case MPSHITTYPE_MASK:
5403 bits += 3;
5404 break;
5405 case FRAGMENTATION_MASK:
5406 bits += 1;
5407 break;
5408 }
5409
5410 if (bits > 36) {
5411 dev_err(adapter->pdev_dev,
5412 "tp_vlan_pri_map=%#x needs %d bits > 36;"\
5413 " using %#x\n", tp_vlan_pri_map, bits,
5414 TP_VLAN_PRI_MAP_DEFAULT);
5415 tp_vlan_pri_map = TP_VLAN_PRI_MAP_DEFAULT;
5416 }
5417 }
5418 v = tp_vlan_pri_map;
5419 t4_write_indirect(adapter, TP_PIO_ADDR, TP_PIO_DATA,
5420 &v, 1, TP_VLAN_PRI_MAP);
5421
5422 /*
5423 * We need Five Tuple Lookup mode to be set in TP_GLOBAL_CONFIG order
5424 * to support any of the compressed filter fields above. Newer
5425 * versions of the firmware do this automatically but it doesn't hurt
5426 * to set it here. Meanwhile, we do _not_ need to set Lookup Every
5427 * Packet in TP_INGRESS_CONFIG to support matching non-TCP packets
5428 * since the firmware automatically turns this on and off when we have
5429 * a non-zero number of filters active (since it does have a
5430 * performance impact).
5431 */
5432 if (tp_vlan_pri_map)
5433 t4_set_reg_field(adapter, TP_GLOBAL_CONFIG,
5434 FIVETUPLELOOKUP_MASK,
5435 FIVETUPLELOOKUP_MASK);
5436
5437 /*
5438 * Tweak some settings.
5439 */
5440 t4_write_reg(adapter, TP_SHIFT_CNT, SYNSHIFTMAX(6) |
5441 RXTSHIFTMAXR1(4) | RXTSHIFTMAXR2(15) |
5442 PERSHIFTBACKOFFMAX(8) | PERSHIFTMAX(8) |
5443 KEEPALIVEMAXR1(4) | KEEPALIVEMAXR2(9));
5444
5445 /*
5446 * Get basic stuff going by issuing the Firmware Initialize command.
5447 * Note that this _must_ be after all PFVF commands ...
5448 */
5449 ret = t4_fw_initialize(adapter, adapter->mbox);
5450 if (ret < 0)
5451 goto bye;
5452
5453 /*
5454 * Return successfully!
5455 */
5456 dev_info(adapter->pdev_dev, "Successfully configured using built-in "\
5457 "driver parameters\n");
5458 return 0;
5459
5460 /*
5461 * Something bad happened. Return the error ...
5462 */
5463bye:
5464 return ret;
5465}
5466
16e47624
HS		 5467static struct fw_info fw_info_array[] = {
5468 {
5469 .chip = CHELSIO_T4,
5470 .fs_name = FW4_CFNAME,
5471 .fw_mod_name = FW4_FNAME,
5472 .fw_hdr = {
5473 .chip = FW_HDR_CHIP_T4,
5474 .fw_ver = __cpu_to_be32(FW_VERSION(T4)),
5475 .intfver_nic = FW_INTFVER(T4, NIC),
5476 .intfver_vnic = FW_INTFVER(T4, VNIC),
5477 .intfver_ri = FW_INTFVER(T4, RI),
5478 .intfver_iscsi = FW_INTFVER(T4, ISCSI),
5479 .intfver_fcoe = FW_INTFVER(T4, FCOE),
5480 },
5481 }, {
5482 .chip = CHELSIO_T5,
5483 .fs_name = FW5_CFNAME,
5484 .fw_mod_name = FW5_FNAME,
5485 .fw_hdr = {
5486 .chip = FW_HDR_CHIP_T5,
5487 .fw_ver = __cpu_to_be32(FW_VERSION(T5)),
5488 .intfver_nic = FW_INTFVER(T5, NIC),
5489 .intfver_vnic = FW_INTFVER(T5, VNIC),
5490 .intfver_ri = FW_INTFVER(T5, RI),
5491 .intfver_iscsi = FW_INTFVER(T5, ISCSI),
5492 .intfver_fcoe = FW_INTFVER(T5, FCOE),
5493 },
5494 }
5495};
5496
5497static struct fw_info *find_fw_info(int chip)
5498{
5499 int i;
5500
5501 for (i = 0; i < ARRAY_SIZE(fw_info_array); i++) {
5502 if (fw_info_array[i].chip == chip)
5503 return &fw_info_array[i];
5504 }
5505 return NULL;
5506}
5507
b8ff05a9
DM		 5508/*
5509 * Phase 0 of initialization: contact FW, obtain config, perform basic init.
5510 */
5511static int adap_init0(struct adapter *adap)
5512{
5513 int ret;
5514 u32 v, port_vec;
5515 enum dev_state state;
5516 u32 params[7], val[7];
9a4da2cd 5517 struct fw_caps_config_cmd caps_cmd;
dcf7b6f5 5518 int reset = 1;
b8ff05a9 5519
636f9d37
VP		 5520 /*
5521 * Contact FW, advertising Master capability (and potentially forcing
5522 * ourselves as the Master PF if our module parameter force_init is
5523 * set).
5524 */
5525 ret = t4_fw_hello(adap, adap->mbox, adap->fn,
5526 force_init ? MASTER_MUST : MASTER_MAY,
5527 &state);
b8ff05a9
DM		 5528 if (ret < 0) {
5529 dev_err(adap->pdev_dev, "could not connect to FW, error %d\n",
5530 ret);
5531 return ret;
5532 }
636f9d37
VP		 5533 if (ret == adap->mbox)
5534 adap->flags |= MASTER_PF;
5535 if (force_init && state == DEV_STATE_INIT)
5536 state = DEV_STATE_UNINIT;
b8ff05a9 5537
636f9d37
VP		 5538 /*
5539 * If we're the Master PF Driver and the device is uninitialized,
5540 * then let's consider upgrading the firmware ... (We always want
5541 * to check the firmware version number in order to A. get it for
5542 * later reporting and B. to warn if the currently loaded firmware
5543 * is excessively mismatched relative to the driver.)
5544 */
16e47624
HS		 5545 t4_get_fw_version(adap, &adap->params.fw_vers);
5546 t4_get_tp_version(adap, &adap->params.tp_vers);
636f9d37 5547 if ((adap->flags & MASTER_PF) && state != DEV_STATE_INIT) {
16e47624
HS		 5548 struct fw_info *fw_info;
5549 struct fw_hdr *card_fw;
5550 const struct firmware *fw;
5551 const u8 *fw_data = NULL;
5552 unsigned int fw_size = 0;
5553
5554 /* This is the firmware whose headers the driver was compiled
5555 * against
5556 */
5557 fw_info = find_fw_info(CHELSIO_CHIP_VERSION(adap->params.chip));
5558 if (fw_info == NULL) {
5559 dev_err(adap->pdev_dev,
5560 "unable to get firmware info for chip %d.\n",
5561 CHELSIO_CHIP_VERSION(adap->params.chip));
5562 return -EINVAL;
636f9d37 5563 }
16e47624
HS		 5564
5565 /* allocate memory to read the header of the firmware on the
5566 * card
5567 */
5568 card_fw = t4_alloc_mem(sizeof(*card_fw));
5569
5570 /* Get FW from from /lib/firmware/ */
5571 ret = request_firmware(&fw, fw_info->fw_mod_name,
5572 adap->pdev_dev);
5573 if (ret < 0) {
5574 dev_err(adap->pdev_dev,
5575 "unable to load firmware image %s, error %d\n",
5576 fw_info->fw_mod_name, ret);
5577 } else {
5578 fw_data = fw->data;
5579 fw_size = fw->size;
5580 }
5581
5582 /* upgrade FW logic */
5583 ret = t4_prep_fw(adap, fw_info, fw_data, fw_size, card_fw,
5584 state, &reset);
5585
5586 /* Cleaning up */
5587 if (fw != NULL)
5588 release_firmware(fw);
5589 t4_free_mem(card_fw);
5590
636f9d37 5591 if (ret < 0)
16e47624 5592 goto bye;
636f9d37 5593 }
b8ff05a9 5594
636f9d37
VP		 5595 /*
5596 * Grab VPD parameters. This should be done after we establish a
5597 * connection to the firmware since some of the VPD parameters
5598 * (notably the Core Clock frequency) are retrieved via requests to
5599 * the firmware. On the other hand, we need these fairly early on
5600 * so we do this right after getting ahold of the firmware.
5601 */
5602 ret = get_vpd_params(adap, &adap->params.vpd);
a0881cab
DM		 5603 if (ret < 0)
5604 goto bye;
a0881cab 5605
636f9d37 5606 /*
13ee15d3
VP		 5607 * Find out what ports are available to us. Note that we need to do
5608 * this before calling adap_init0_no_config() since it needs nports
5609 * and portvec ...
636f9d37
VP		 5610 */
5611 v =
5612 FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
5613 FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_PORTVEC);
5614 ret = t4_query_params(adap, adap->mbox, adap->fn, 0, 1, &v, &port_vec);
a0881cab
DM		 5615 if (ret < 0)
5616 goto bye;
5617
636f9d37
VP		 5618 adap->params.nports = hweight32(port_vec);
5619 adap->params.portvec = port_vec;
5620
5621 /*
5622 * If the firmware is initialized already (and we're not forcing a
5623 * master initialization), note that we're living with existing
5624 * adapter parameters. Otherwise, it's time to try initializing the
5625 * adapter ...
5626 */
5627 if (state == DEV_STATE_INIT) {
5628 dev_info(adap->pdev_dev, "Coming up as %s: "\
5629 "Adapter already initialized\n",
5630 adap->flags & MASTER_PF ? "MASTER" : "SLAVE");
5631 adap->flags |= USING_SOFT_PARAMS;
5632 } else {
5633 dev_info(adap->pdev_dev, "Coming up as MASTER: "\
5634 "Initializing adapter\n");
636f9d37
VP		 5635
5636 /*
5637 * If the firmware doesn't support Configuration
5638 * Files warn user and exit,
5639 */
5640 if (ret < 0)
13ee15d3 5641 dev_warn(adap->pdev_dev, "Firmware doesn't support "
636f9d37 5642 "configuration file.\n");
13ee15d3
VP		 5643 if (force_old_init)
5644 ret = adap_init0_no_config(adap, reset);
636f9d37
VP		 5645 else {
5646 /*
13ee15d3
VP		 5647 * Find out whether we're dealing with a version of
5648 * the firmware which has configuration file support.
636f9d37 5649 */
13ee15d3
VP		 5650 params[0] = (FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
5651 FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_CF));
5652 ret = t4_query_params(adap, adap->mbox, adap->fn, 0, 1,
5653 params, val);
636f9d37 5654
13ee15d3
VP		 5655 /*
5656 * If the firmware doesn't support Configuration
5657 * Files, use the old Driver-based, hard-wired
5658 * initialization. Otherwise, try using the
5659 * Configuration File support and fall back to the
5660 * Driver-based initialization if there's no
5661 * Configuration File found.
5662 */
5663 if (ret < 0)
5664 ret = adap_init0_no_config(adap, reset);
5665 else {
5666 /*
5667 * The firmware provides us with a memory
5668 * buffer where we can load a Configuration
5669 * File from the host if we want to override
5670 * the Configuration File in flash.
5671 */
5672
5673 ret = adap_init0_config(adap, reset);
5674 if (ret == -ENOENT) {
5675 dev_info(adap->pdev_dev,
5676 "No Configuration File present "
16e47624 5677 "on adapter. Using hard-wired "
13ee15d3
VP		 5678 "configuration parameters.\n");
5679 ret = adap_init0_no_config(adap, reset);
5680 }
636f9d37
VP		 5681 }
5682 }
5683 if (ret < 0) {
5684 dev_err(adap->pdev_dev,
5685 "could not initialize adapter, error %d\n",
5686 -ret);
5687 goto bye;
5688 }
5689 }
5690
5691 /*
5692 * If we're living with non-hard-coded parameters (either from a
5693 * Firmware Configuration File or values programmed by a different PF
5694 * Driver), give the SGE code a chance to pull in anything that it
5695 * needs ... Note that this must be called after we retrieve our VPD
5696 * parameters in order to know how to convert core ticks to seconds.
5697 */
5698 if (adap->flags & USING_SOFT_PARAMS) {
5699 ret = t4_sge_init(adap);
5700 if (ret < 0)
5701 goto bye;
5702 }
5703
9a4da2cd
VP		 5704 if (is_bypass_device(adap->pdev->device))
5705 adap->params.bypass = 1;
5706
636f9d37
VP		 5707 /*
5708 * Grab some of our basic fundamental operating parameters.
5709 */
5710#define FW_PARAM_DEV(param) \
5711 (FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | \
5712 FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_##param))
5713
b8ff05a9 5714#define FW_PARAM_PFVF(param) \
636f9d37
VP		 5715 FW_PARAMS_MNEM(FW_PARAMS_MNEM_PFVF) | \
5716 FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_PFVF_##param)| \
5717 FW_PARAMS_PARAM_Y(0) | \
5718 FW_PARAMS_PARAM_Z(0)
b8ff05a9 5719
636f9d37 5720 params[0] = FW_PARAM_PFVF(EQ_START);
b8ff05a9
DM		 5721 params[1] = FW_PARAM_PFVF(L2T_START);
5722 params[2] = FW_PARAM_PFVF(L2T_END);
5723 params[3] = FW_PARAM_PFVF(FILTER_START);
5724 params[4] = FW_PARAM_PFVF(FILTER_END);
e46dab4d 5725 params[5] = FW_PARAM_PFVF(IQFLINT_START);
636f9d37 5726 ret = t4_query_params(adap, adap->mbox, adap->fn, 0, 6, params, val);
b8ff05a9
DM		 5727 if (ret < 0)
5728 goto bye;
636f9d37
VP		 5729 adap->sge.egr_start = val[0];
5730 adap->l2t_start = val[1];
5731 adap->l2t_end = val[2];
b8ff05a9
DM		 5732 adap->tids.ftid_base = val[3];
5733 adap->tids.nftids = val[4] - val[3] + 1;
e46dab4d 5734 adap->sge.ingr_start = val[5];
b8ff05a9 5735
636f9d37
VP		 5736 /* query params related to active filter region */
5737 params[0] = FW_PARAM_PFVF(ACTIVE_FILTER_START);
5738 params[1] = FW_PARAM_PFVF(ACTIVE_FILTER_END);
5739 ret = t4_query_params(adap, adap->mbox, adap->fn, 0, 2, params, val);
5740 /* If Active filter size is set we enable establishing
5741 * offload connection through firmware work request
5742 */
5743 if ((val[0] != val[1]) && (ret >= 0)) {
5744 adap->flags |= FW_OFLD_CONN;
5745 adap->tids.aftid_base = val[0];
5746 adap->tids.aftid_end = val[1];
5747 }
5748
b407a4a9
VP		 5749 /* If we're running on newer firmware, let it know that we're
5750 * prepared to deal with encapsulated CPL messages. Older
5751 * firmware won't understand this and we'll just get
5752 * unencapsulated messages ...
5753 */
5754 params[0] = FW_PARAM_PFVF(CPLFW4MSG_ENCAP);
5755 val[0] = 1;
5756 (void) t4_set_params(adap, adap->mbox, adap->fn, 0, 1, params, val);
5757
1ac0f095
KS		 5758 /*
5759 * Find out whether we're allowed to use the T5+ ULPTX MEMWRITE DSGL
5760 * capability. Earlier versions of the firmware didn't have the
5761 * ULPTX_MEMWRITE_DSGL so we'll interpret a query failure as no
5762 * permission to use ULPTX MEMWRITE DSGL.
5763 */
5764 if (is_t4(adap->params.chip)) {
5765 adap->params.ulptx_memwrite_dsgl = false;
5766 } else {
5767 params[0] = FW_PARAM_DEV(ULPTX_MEMWRITE_DSGL);
5768 ret = t4_query_params(adap, adap->mbox, adap->fn, 0,
5769 1, params, val);
5770 adap->params.ulptx_memwrite_dsgl = (ret == 0 && val[0] != 0);
5771 }
5772
636f9d37
VP		 5773 /*
5774 * Get device capabilities so we can determine what resources we need
5775 * to manage.
5776 */
5777 memset(&caps_cmd, 0, sizeof(caps_cmd));
9a4da2cd 5778 caps_cmd.op_to_write = htonl(FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
13ee15d3 5779 FW_CMD_REQUEST | FW_CMD_READ);
ce91a923 5780 caps_cmd.cfvalid_to_len16 = htonl(FW_LEN16(caps_cmd));
636f9d37
VP		 5781 ret = t4_wr_mbox(adap, adap->mbox, &caps_cmd, sizeof(caps_cmd),
5782 &caps_cmd);
5783 if (ret < 0)
5784 goto bye;
5785
13ee15d3 5786 if (caps_cmd.ofldcaps) {
b8ff05a9
DM		 5787 /* query offload-related parameters */
5788 params[0] = FW_PARAM_DEV(NTID);
5789 params[1] = FW_PARAM_PFVF(SERVER_START);
5790 params[2] = FW_PARAM_PFVF(SERVER_END);
5791 params[3] = FW_PARAM_PFVF(TDDP_START);
5792 params[4] = FW_PARAM_PFVF(TDDP_END);
5793 params[5] = FW_PARAM_DEV(FLOWC_BUFFIFO_SZ);
636f9d37
VP		 5794 ret = t4_query_params(adap, adap->mbox, adap->fn, 0, 6,
5795 params, val);
b8ff05a9
DM		 5796 if (ret < 0)
5797 goto bye;
5798 adap->tids.ntids = val[0];
5799 adap->tids.natids = min(adap->tids.ntids / 2, MAX_ATIDS);
5800 adap->tids.stid_base = val[1];
5801 adap->tids.nstids = val[2] - val[1] + 1;
636f9d37
VP		 5802 /*
5803 * Setup server filter region. Divide the availble filter
5804 * region into two parts. Regular filters get 1/3rd and server
5805 * filters get 2/3rd part. This is only enabled if workarond
5806 * path is enabled.
5807 * 1. For regular filters.
5808 * 2. Server filter: This are special filters which are used
5809 * to redirect SYN packets to offload queue.
5810 */
5811 if (adap->flags & FW_OFLD_CONN && !is_bypass(adap)) {
5812 adap->tids.sftid_base = adap->tids.ftid_base +
5813 DIV_ROUND_UP(adap->tids.nftids, 3);
5814 adap->tids.nsftids = adap->tids.nftids -
5815 DIV_ROUND_UP(adap->tids.nftids, 3);
5816 adap->tids.nftids = adap->tids.sftid_base -
5817 adap->tids.ftid_base;
5818 }
b8ff05a9
DM		 5819 adap->vres.ddp.start = val[3];
5820 adap->vres.ddp.size = val[4] - val[3] + 1;
5821 adap->params.ofldq_wr_cred = val[5];
636f9d37 5822
b8ff05a9
DM		 5823 adap->params.offload = 1;
5824 }
636f9d37 5825 if (caps_cmd.rdmacaps) {
b8ff05a9
DM		 5826 params[0] = FW_PARAM_PFVF(STAG_START);
5827 params[1] = FW_PARAM_PFVF(STAG_END);
5828 params[2] = FW_PARAM_PFVF(RQ_START);
5829 params[3] = FW_PARAM_PFVF(RQ_END);
5830 params[4] = FW_PARAM_PFVF(PBL_START);
5831 params[5] = FW_PARAM_PFVF(PBL_END);
636f9d37
VP		 5832 ret = t4_query_params(adap, adap->mbox, adap->fn, 0, 6,
5833 params, val);
b8ff05a9
DM		 5834 if (ret < 0)
5835 goto bye;
5836 adap->vres.stag.start = val[0];
5837 adap->vres.stag.size = val[1] - val[0] + 1;
5838 adap->vres.rq.start = val[2];
5839 adap->vres.rq.size = val[3] - val[2] + 1;
5840 adap->vres.pbl.start = val[4];
5841 adap->vres.pbl.size = val[5] - val[4] + 1;
a0881cab
DM		 5842
5843 params[0] = FW_PARAM_PFVF(SQRQ_START);
5844 params[1] = FW_PARAM_PFVF(SQRQ_END);
5845 params[2] = FW_PARAM_PFVF(CQ_START);
5846 params[3] = FW_PARAM_PFVF(CQ_END);
1ae970e0
DM		 5847 params[4] = FW_PARAM_PFVF(OCQ_START);
5848 params[5] = FW_PARAM_PFVF(OCQ_END);
636f9d37 5849 ret = t4_query_params(adap, 0, 0, 0, 6, params, val);
a0881cab
DM		 5850 if (ret < 0)
5851 goto bye;
5852 adap->vres.qp.start = val[0];
5853 adap->vres.qp.size = val[1] - val[0] + 1;
5854 adap->vres.cq.start = val[2];
5855 adap->vres.cq.size = val[3] - val[2] + 1;
1ae970e0
DM		 5856 adap->vres.ocq.start = val[4];
5857 adap->vres.ocq.size = val[5] - val[4] + 1;
b8ff05a9 5858 }
636f9d37 5859 if (caps_cmd.iscsicaps) {
b8ff05a9
DM		 5860 params[0] = FW_PARAM_PFVF(ISCSI_START);
5861 params[1] = FW_PARAM_PFVF(ISCSI_END);
636f9d37
VP		 5862 ret = t4_query_params(adap, adap->mbox, adap->fn, 0, 2,
5863 params, val);
b8ff05a9
DM		 5864 if (ret < 0)
5865 goto bye;
5866 adap->vres.iscsi.start = val[0];
5867 adap->vres.iscsi.size = val[1] - val[0] + 1;
5868 }
5869#undef FW_PARAM_PFVF
5870#undef FW_PARAM_DEV
5871
92e7ae71
HS		 5872 /* The MTU/MSS Table is initialized by now, so load their values. If
5873 * we're initializing the adapter, then we'll make any modifications
5874 * we want to the MTU/MSS Table and also initialize the congestion
5875 * parameters.
636f9d37 5876 */
b8ff05a9 5877 t4_read_mtu_tbl(adap, adap->params.mtus, NULL);
92e7ae71
HS		 5878 if (state != DEV_STATE_INIT) {
5879 int i;
5880
5881 /* The default MTU Table contains values 1492 and 1500.
5882 * However, for TCP, it's better to have two values which are
5883 * a multiple of 8 +/- 4 bytes apart near this popular MTU.
5884 * This allows us to have a TCP Data Payload which is a
5885 * multiple of 8 regardless of what combination of TCP Options
5886 * are in use (always a multiple of 4 bytes) which is
5887 * important for performance reasons. For instance, if no
5888 * options are in use, then we have a 20-byte IP header and a
5889 * 20-byte TCP header. In this case, a 1500-byte MSS would
5890 * result in a TCP Data Payload of 1500 - 40 == 1460 bytes
5891 * which is not a multiple of 8. So using an MSS of 1488 in
5892 * this case results in a TCP Data Payload of 1448 bytes which
5893 * is a multiple of 8. On the other hand, if 12-byte TCP Time
5894 * Stamps have been negotiated, then an MTU of 1500 bytes
5895 * results in a TCP Data Payload of 1448 bytes which, as
5896 * above, is a multiple of 8 bytes ...
5897 */
5898 for (i = 0; i < NMTUS; i++)
5899 if (adap->params.mtus[i] == 1492) {
5900 adap->params.mtus[i] = 1488;
5901 break;
5902 }
7ee9ff94 5903
92e7ae71
HS		 5904 t4_load_mtus(adap, adap->params.mtus, adap->params.a_wnd,
5905 adap->params.b_wnd);
5906 }
dcf7b6f5 5907 t4_init_tp_params(adap);
636f9d37 5908 adap->flags |= FW_OK;
b8ff05a9
DM		 5909 return 0;
5910
5911 /*
636f9d37
VP		 5912 * Something bad happened. If a command timed out or failed with EIO
5913 * FW does not operate within its spec or something catastrophic
5914 * happened to HW/FW, stop issuing commands.
b8ff05a9 5915 */
636f9d37
VP		 5916bye:
5917 if (ret != -ETIMEDOUT && ret != -EIO)
5918 t4_fw_bye(adap, adap->mbox);
b8ff05a9
DM		 5919 return ret;
5920}
5921
204dc3c0
DM		 5922/* EEH callbacks */
5923
5924static pci_ers_result_t eeh_err_detected(struct pci_dev *pdev,
5925 pci_channel_state_t state)
5926{
5927 int i;
5928 struct adapter *adap = pci_get_drvdata(pdev);
5929
5930 if (!adap)
5931 goto out;
5932
5933 rtnl_lock();
5934 adap->flags &= ~FW_OK;
5935 notify_ulds(adap, CXGB4_STATE_START_RECOVERY);
9fe6cb58 5936 spin_lock(&adap->stats_lock);
204dc3c0
DM		 5937 for_each_port(adap, i) {
5938 struct net_device *dev = adap->port[i];
5939
5940 netif_device_detach(dev);
5941 netif_carrier_off(dev);
5942 }
9fe6cb58 5943 spin_unlock(&adap->stats_lock);
204dc3c0
DM		 5944 if (adap->flags & FULL_INIT_DONE)
5945 cxgb_down(adap);
5946 rtnl_unlock();
144be3d9
GS		 5947 if ((adap->flags & DEV_ENABLED)) {
5948 pci_disable_device(pdev);
5949 adap->flags &= ~DEV_ENABLED;
5950 }
204dc3c0
DM		 5951out: return state == pci_channel_io_perm_failure ?
5952 PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_NEED_RESET;
5953}
5954
5955static pci_ers_result_t eeh_slot_reset(struct pci_dev *pdev)
5956{
5957 int i, ret;
5958 struct fw_caps_config_cmd c;
5959 struct adapter *adap = pci_get_drvdata(pdev);
5960
5961 if (!adap) {
5962 pci_restore_state(pdev);
5963 pci_save_state(pdev);
5964 return PCI_ERS_RESULT_RECOVERED;
5965 }
5966
144be3d9
GS		 5967 if (!(adap->flags & DEV_ENABLED)) {
5968 if (pci_enable_device(pdev)) {
5969 dev_err(&pdev->dev, "Cannot reenable PCI "
5970 "device after reset\n");
5971 return PCI_ERS_RESULT_DISCONNECT;
5972 }
5973 adap->flags |= DEV_ENABLED;
204dc3c0
DM		 5974 }
5975
5976 pci_set_master(pdev);
5977 pci_restore_state(pdev);
5978 pci_save_state(pdev);
5979 pci_cleanup_aer_uncorrect_error_status(pdev);
5980
5981 if (t4_wait_dev_ready(adap) < 0)
5982 return PCI_ERS_RESULT_DISCONNECT;
777c2300 5983 if (t4_fw_hello(adap, adap->fn, adap->fn, MASTER_MUST, NULL) < 0)
204dc3c0
DM		 5984 return PCI_ERS_RESULT_DISCONNECT;
5985 adap->flags |= FW_OK;
5986 if (adap_init1(adap, &c))
5987 return PCI_ERS_RESULT_DISCONNECT;
5988
5989 for_each_port(adap, i) {
5990 struct port_info *p = adap2pinfo(adap, i);
5991
060e0c75
DM		 5992 ret = t4_alloc_vi(adap, adap->fn, p->tx_chan, adap->fn, 0, 1,
5993 NULL, NULL);
204dc3c0
DM		 5994 if (ret < 0)
5995 return PCI_ERS_RESULT_DISCONNECT;
5996 p->viid = ret;
5997 p->xact_addr_filt = -1;
5998 }
5999
6000 t4_load_mtus(adap, adap->params.mtus, adap->params.a_wnd,
6001 adap->params.b_wnd);
1ae970e0 6002 setup_memwin(adap);
204dc3c0
DM		 6003 if (cxgb_up(adap))
6004 return PCI_ERS_RESULT_DISCONNECT;
6005 return PCI_ERS_RESULT_RECOVERED;
6006}
6007
6008static void eeh_resume(struct pci_dev *pdev)
6009{
6010 int i;
6011 struct adapter *adap = pci_get_drvdata(pdev);
6012
6013 if (!adap)
6014 return;
6015
6016 rtnl_lock();
6017 for_each_port(adap, i) {
6018 struct net_device *dev = adap->port[i];
6019
6020 if (netif_running(dev)) {
6021 link_start(dev);
6022 cxgb_set_rxmode(dev);
6023 }
6024 netif_device_attach(dev);
6025 }
6026 rtnl_unlock();
6027}
6028
3646f0e5 6029static const struct pci_error_handlers cxgb4_eeh = {
204dc3c0
DM		 6030 .error_detected = eeh_err_detected,
6031 .slot_reset = eeh_slot_reset,
6032 .resume = eeh_resume,
6033};
6034
57d8b764 6035static inline bool is_x_10g_port(const struct link_config *lc)
b8ff05a9 6036{
57d8b764
KS		 6037 return (lc->supported & FW_PORT_CAP_SPEED_10G) != 0 ||
6038 (lc->supported & FW_PORT_CAP_SPEED_40G) != 0;
b8ff05a9
DM		 6039}
6040
c887ad0e
HS		 6041static inline void init_rspq(struct adapter *adap, struct sge_rspq *q,
6042 unsigned int us, unsigned int cnt,
b8ff05a9
DM		 6043 unsigned int size, unsigned int iqe_size)
6044{
c887ad0e
HS		 6045 q->adap = adap;
6046 set_rspq_intr_params(q, us, cnt);
b8ff05a9
DM		 6047 q->iqe_len = iqe_size;
6048 q->size = size;
6049}
6050
6051/*
6052 * Perform default configuration of DMA queues depending on the number and type
6053 * of ports we found and the number of available CPUs. Most settings can be
6054 * modified by the admin prior to actual use.
6055 */
91744948 6056static void cfg_queues(struct adapter *adap)
b8ff05a9
DM		 6057{
6058 struct sge *s = &adap->sge;
688848b1
AB		 6059 int i, n10g = 0, qidx = 0;
6060#ifndef CONFIG_CHELSIO_T4_DCB
6061 int q10g = 0;
6062#endif
cf38be6d 6063 int ciq_size;
b8ff05a9
DM		 6064
6065 for_each_port(adap, i)
57d8b764 6066 n10g += is_x_10g_port(&adap2pinfo(adap, i)->link_cfg);
688848b1
AB		 6067#ifdef CONFIG_CHELSIO_T4_DCB
6068 /* For Data Center Bridging support we need to be able to support up
6069 * to 8 Traffic Priorities; each of which will be assigned to its
6070 * own TX Queue in order to prevent Head-Of-Line Blocking.
6071 */
6072 if (adap->params.nports * 8 > MAX_ETH_QSETS) {
6073 dev_err(adap->pdev_dev, "MAX_ETH_QSETS=%d < %d!\n",
6074 MAX_ETH_QSETS, adap->params.nports * 8);
6075 BUG_ON(1);
6076 }
b8ff05a9 6077
688848b1
AB		 6078 for_each_port(adap, i) {
6079 struct port_info *pi = adap2pinfo(adap, i);
6080
6081 pi->first_qset = qidx;
6082 pi->nqsets = 8;
6083 qidx += pi->nqsets;
6084 }
6085#else /* !CONFIG_CHELSIO_T4_DCB */
b8ff05a9
DM		 6086 /*
6087 * We default to 1 queue per non-10G port and up to # of cores queues
6088 * per 10G port.
6089 */
6090 if (n10g)
6091 q10g = (MAX_ETH_QSETS - (adap->params.nports - n10g)) / n10g;
5952dde7
YM		 6092 if (q10g > netif_get_num_default_rss_queues())
6093 q10g = netif_get_num_default_rss_queues();
b8ff05a9
DM		 6094
6095 for_each_port(adap, i) {
6096 struct port_info *pi = adap2pinfo(adap, i);
6097
6098 pi->first_qset = qidx;
57d8b764 6099 pi->nqsets = is_x_10g_port(&pi->link_cfg) ? q10g : 1;
b8ff05a9
DM		 6100 qidx += pi->nqsets;
6101 }
688848b1 6102#endif /* !CONFIG_CHELSIO_T4_DCB */
b8ff05a9
DM		 6103
6104 s->ethqsets = qidx;
6105 s->max_ethqsets = qidx; /* MSI-X may lower it later */
6106
6107 if (is_offload(adap)) {
6108 /*
6109 * For offload we use 1 queue/channel if all ports are up to 1G,
6110 * otherwise we divide all available queues amongst the channels
6111 * capped by the number of available cores.
6112 */
6113 if (n10g) {
6114 i = min_t(int, ARRAY_SIZE(s->ofldrxq),
6115 num_online_cpus());
6116 s->ofldqsets = roundup(i, adap->params.nports);
6117 } else
6118 s->ofldqsets = adap->params.nports;
6119 /* For RDMA one Rx queue per channel suffices */
6120 s->rdmaqs = adap->params.nports;
cf38be6d 6121 s->rdmaciqs = adap->params.nports;
b8ff05a9
DM		 6122 }
6123
6124 for (i = 0; i < ARRAY_SIZE(s->ethrxq); i++) {
6125 struct sge_eth_rxq *r = &s->ethrxq[i];
6126
c887ad0e 6127 init_rspq(adap, &r->rspq, 5, 10, 1024, 64);
b8ff05a9
DM		 6128 r->fl.size = 72;
6129 }
6130
6131 for (i = 0; i < ARRAY_SIZE(s->ethtxq); i++)
6132 s->ethtxq[i].q.size = 1024;
6133
6134 for (i = 0; i < ARRAY_SIZE(s->ctrlq); i++)
6135 s->ctrlq[i].q.size = 512;
6136
6137 for (i = 0; i < ARRAY_SIZE(s->ofldtxq); i++)
6138 s->ofldtxq[i].q.size = 1024;
6139
6140 for (i = 0; i < ARRAY_SIZE(s->ofldrxq); i++) {
6141 struct sge_ofld_rxq *r = &s->ofldrxq[i];
6142
c887ad0e 6143 init_rspq(adap, &r->rspq, 5, 1, 1024, 64);
b8ff05a9
DM		 6144 r->rspq.uld = CXGB4_ULD_ISCSI;
6145 r->fl.size = 72;
6146 }
6147
6148 for (i = 0; i < ARRAY_SIZE(s->rdmarxq); i++) {
6149 struct sge_ofld_rxq *r = &s->rdmarxq[i];
6150
c887ad0e 6151 init_rspq(adap, &r->rspq, 5, 1, 511, 64);
b8ff05a9
DM		 6152 r->rspq.uld = CXGB4_ULD_RDMA;
6153 r->fl.size = 72;
6154 }
6155
cf38be6d
HS		 6156 ciq_size = 64 + adap->vres.cq.size + adap->tids.nftids;
6157 if (ciq_size > SGE_MAX_IQ_SIZE) {
6158 CH_WARN(adap, "CIQ size too small for available IQs\n");
6159 ciq_size = SGE_MAX_IQ_SIZE;
6160 }
6161
6162 for (i = 0; i < ARRAY_SIZE(s->rdmaciq); i++) {
6163 struct sge_ofld_rxq *r = &s->rdmaciq[i];
6164
c887ad0e 6165 init_rspq(adap, &r->rspq, 5, 1, ciq_size, 64);
cf38be6d
HS		 6166 r->rspq.uld = CXGB4_ULD_RDMA;
6167 }
6168
c887ad0e
HS		 6169 init_rspq(adap, &s->fw_evtq, 0, 1, 1024, 64);
6170 init_rspq(adap, &s->intrq, 0, 1, 2 * MAX_INGQ, 64);
b8ff05a9
DM		 6171}
6172
6173/*
6174 * Reduce the number of Ethernet queues across all ports to at most n.
6175 * n provides at least one queue per port.
6176 */
91744948 6177static void reduce_ethqs(struct adapter *adap, int n)
b8ff05a9
DM		 6178{
6179 int i;
6180 struct port_info *pi;
6181
6182 while (n < adap->sge.ethqsets)
6183 for_each_port(adap, i) {
6184 pi = adap2pinfo(adap, i);
6185 if (pi->nqsets > 1) {
6186 pi->nqsets--;
6187 adap->sge.ethqsets--;
6188 if (adap->sge.ethqsets <= n)
6189 break;
6190 }
6191 }
6192
6193 n = 0;
6194 for_each_port(adap, i) {
6195 pi = adap2pinfo(adap, i);
6196 pi->first_qset = n;
6197 n += pi->nqsets;
6198 }
6199}
6200
6201/* 2 MSI-X vectors needed for the FW queue and non-data interrupts */
6202#define EXTRA_VECS 2
6203
91744948 6204static int enable_msix(struct adapter *adap)
b8ff05a9
DM		 6205{
6206 int ofld_need = 0;
c32ad224 6207 int i, want, need;
b8ff05a9
DM		 6208 struct sge *s = &adap->sge;
6209 unsigned int nchan = adap->params.nports;
6210 struct msix_entry entries[MAX_INGQ + 1];
6211
6212 for (i = 0; i < ARRAY_SIZE(entries); ++i)
6213 entries[i].entry = i;
6214
6215 want = s->max_ethqsets + EXTRA_VECS;
6216 if (is_offload(adap)) {
cf38be6d 6217 want += s->rdmaqs + s->rdmaciqs + s->ofldqsets;
b8ff05a9 6218 /* need nchan for each possible ULD */
cf38be6d 6219 ofld_need = 3 * nchan;
b8ff05a9 6220 }
688848b1
AB		 6221#ifdef CONFIG_CHELSIO_T4_DCB
6222 /* For Data Center Bridging we need 8 Ethernet TX Priority Queues for
6223 * each port.
6224 */
6225 need = 8 * adap->params.nports + EXTRA_VECS + ofld_need;
6226#else
b8ff05a9 6227 need = adap->params.nports + EXTRA_VECS + ofld_need;
688848b1 6228#endif
c32ad224
AG		 6229 want = pci_enable_msix_range(adap->pdev, entries, need, want);
6230 if (want < 0)
6231 return want;
b8ff05a9 6232
c32ad224
AG		 6233 /*
6234 * Distribute available vectors to the various queue groups.
6235 * Every group gets its minimum requirement and NIC gets top
6236 * priority for leftovers.
6237 */
6238 i = want - EXTRA_VECS - ofld_need;
6239 if (i < s->max_ethqsets) {
6240 s->max_ethqsets = i;
6241 if (i < s->ethqsets)
6242 reduce_ethqs(adap, i);
6243 }
6244 if (is_offload(adap)) {
6245 i = want - EXTRA_VECS - s->max_ethqsets;
6246 i -= ofld_need - nchan;
6247 s->ofldqsets = (i / nchan) * nchan; /* round down */
6248 }
6249 for (i = 0; i < want; ++i)
6250 adap->msix_info[i].vec = entries[i].vector;
6251
6252 return 0;
b8ff05a9
DM		 6253}
6254
6255#undef EXTRA_VECS
6256
91744948 6257static int init_rss(struct adapter *adap)
671b0060
DM		 6258{
6259 unsigned int i, j;
6260
6261 for_each_port(adap, i) {
6262 struct port_info *pi = adap2pinfo(adap, i);
6263
6264 pi->rss = kcalloc(pi->rss_size, sizeof(u16), GFP_KERNEL);
6265 if (!pi->rss)
6266 return -ENOMEM;
6267 for (j = 0; j < pi->rss_size; j++)
278bc429 6268 pi->rss[j] = ethtool_rxfh_indir_default(j, pi->nqsets);
671b0060
DM		 6269 }
6270 return 0;
6271}
6272
91744948 6273static void print_port_info(const struct net_device *dev)
b8ff05a9 6274{
b8ff05a9 6275 char buf[80];
118969ed 6276 char *bufp = buf;
f1a051b9 6277 const char *spd = "";
118969ed
DM		 6278 const struct port_info *pi = netdev_priv(dev);
6279 const struct adapter *adap = pi->adapter;
f1a051b9
DM		 6280
6281 if (adap->params.pci.speed == PCI_EXP_LNKSTA_CLS_2_5GB)
6282 spd = " 2.5 GT/s";
6283 else if (adap->params.pci.speed == PCI_EXP_LNKSTA_CLS_5_0GB)
6284 spd = " 5 GT/s";
d2e752db
RD		 6285 else if (adap->params.pci.speed == PCI_EXP_LNKSTA_CLS_8_0GB)
6286 spd = " 8 GT/s";
b8ff05a9 6287
118969ed
DM		 6288 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_100M)
6289 bufp += sprintf(bufp, "100/");
6290 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_1G)
6291 bufp += sprintf(bufp, "1000/");
6292 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_10G)
6293 bufp += sprintf(bufp, "10G/");
72aca4bf
KS		 6294 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_40G)
6295 bufp += sprintf(bufp, "40G/");
118969ed
DM		 6296 if (bufp != buf)
6297 --bufp;
72aca4bf 6298 sprintf(bufp, "BASE-%s", t4_get_port_type_description(pi->port_type));
118969ed
DM		 6299
6300 netdev_info(dev, "Chelsio %s rev %d %s %sNIC PCIe x%d%s%s\n",
0a57a536 6301 adap->params.vpd.id,
d14807dd 6302 CHELSIO_CHIP_RELEASE(adap->params.chip), buf,
118969ed
DM		 6303 is_offload(adap) ? "R" : "", adap->params.pci.width, spd,
6304 (adap->flags & USING_MSIX) ? " MSI-X" :
6305 (adap->flags & USING_MSI) ? " MSI" : "");
a94cd705
KS		 6306 netdev_info(dev, "S/N: %s, P/N: %s\n",
6307 adap->params.vpd.sn, adap->params.vpd.pn);
b8ff05a9
DM		 6308}
6309
91744948 6310static void enable_pcie_relaxed_ordering(struct pci_dev *dev)
ef306b50 6311{
e5c8ae5f 6312 pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_RELAX_EN);
ef306b50
DM		 6313}
6314
06546391
DM		 6315/*
6316 * Free the following resources:
6317 * - memory used for tables
6318 * - MSI/MSI-X
6319 * - net devices
6320 * - resources FW is holding for us
6321 */
6322static void free_some_resources(struct adapter *adapter)
6323{
6324 unsigned int i;
6325
6326 t4_free_mem(adapter->l2t);
6327 t4_free_mem(adapter->tids.tid_tab);
6328 disable_msi(adapter);
6329
6330 for_each_port(adapter, i)
671b0060
DM		 6331 if (adapter->port[i]) {
6332 kfree(adap2pinfo(adapter, i)->rss);
06546391 6333 free_netdev(adapter->port[i]);
671b0060 6334 }
06546391 6335 if (adapter->flags & FW_OK)
060e0c75 6336 t4_fw_bye(adapter, adapter->fn);
06546391
DM		 6337}
6338
2ed28baa 6339#define TSO_FLAGS (NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_TSO_ECN)
35d35682 6340#define VLAN_FEAT (NETIF_F_SG | NETIF_F_IP_CSUM | TSO_FLAGS | \
b8ff05a9 6341 NETIF_F_IPV6_CSUM | NETIF_F_HIGHDMA)
22adfe0a 6342#define SEGMENT_SIZE 128
b8ff05a9 6343
1dd06ae8 6344static int init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
b8ff05a9 6345{
22adfe0a 6346 int func, i, err, s_qpp, qpp, num_seg;
b8ff05a9 6347 struct port_info *pi;
c8f44aff 6348 bool highdma = false;
b8ff05a9
DM		 6349 struct adapter *adapter = NULL;
6350
6351 printk_once(KERN_INFO "%s - version %s\n", DRV_DESC, DRV_VERSION);
6352
6353 err = pci_request_regions(pdev, KBUILD_MODNAME);
6354 if (err) {
6355 /* Just info, some other driver may have claimed the device. */
6356 dev_info(&pdev->dev, "cannot obtain PCI resources\n");
6357 return err;
6358 }
6359
b8ff05a9
DM		 6360 err = pci_enable_device(pdev);
6361 if (err) {
6362 dev_err(&pdev->dev, "cannot enable PCI device\n");
6363 goto out_release_regions;
6364 }
6365
6366 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
c8f44aff 6367 highdma = true;
b8ff05a9
DM		 6368 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
6369 if (err) {
6370 dev_err(&pdev->dev, "unable to obtain 64-bit DMA for "
6371 "coherent allocations\n");
6372 goto out_disable_device;
6373 }
6374 } else {
6375 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
6376 if (err) {
6377 dev_err(&pdev->dev, "no usable DMA configuration\n");
6378 goto out_disable_device;
6379 }
6380 }
6381
6382 pci_enable_pcie_error_reporting(pdev);
ef306b50 6383 enable_pcie_relaxed_ordering(pdev);
b8ff05a9
DM		 6384 pci_set_master(pdev);
6385 pci_save_state(pdev);
6386
6387 adapter = kzalloc(sizeof(*adapter), GFP_KERNEL);
6388 if (!adapter) {
6389 err = -ENOMEM;
6390 goto out_disable_device;
6391 }
6392
144be3d9
GS		 6393 /* PCI device has been enabled */
6394 adapter->flags |= DEV_ENABLED;
6395
b8ff05a9
DM		 6396 adapter->regs = pci_ioremap_bar(pdev, 0);
6397 if (!adapter->regs) {
6398 dev_err(&pdev->dev, "cannot map device registers\n");
6399 err = -ENOMEM;
6400 goto out_free_adapter;
6401 }
6402
35b1de55
HS		 6403 /* We control everything through one PF */
6404 func = SOURCEPF_GET(readl(adapter->regs + PL_WHOAMI));
6405 if ((pdev->device == 0xa000 && func != 0) ||
6406 func != ent->driver_data) {
6407 pci_save_state(pdev); /* to restore SR-IOV later */
6408 err = 0;
6409 goto out_unmap_bar0;
6410 }
6411
b8ff05a9
DM		 6412 adapter->pdev = pdev;
6413 adapter->pdev_dev = &pdev->dev;
3069ee9b 6414 adapter->mbox = func;
060e0c75 6415 adapter->fn = func;
b8ff05a9
DM		 6416 adapter->msg_enable = dflt_msg_enable;
6417 memset(adapter->chan_map, 0xff, sizeof(adapter->chan_map));
6418
6419 spin_lock_init(&adapter->stats_lock);
6420 spin_lock_init(&adapter->tid_release_lock);
6421
6422 INIT_WORK(&adapter->tid_release_task, process_tid_release_list);
881806bc
VP		 6423 INIT_WORK(&adapter->db_full_task, process_db_full);
6424 INIT_WORK(&adapter->db_drop_task, process_db_drop);
b8ff05a9
DM		 6425
6426 err = t4_prep_adapter(adapter);
6427 if (err)
22adfe0a
SR		 6428 goto out_unmap_bar0;
6429
d14807dd 6430 if (!is_t4(adapter->params.chip)) {
22adfe0a
SR		 6431 s_qpp = QUEUESPERPAGEPF1 * adapter->fn;
6432 qpp = 1 << QUEUESPERPAGEPF0_GET(t4_read_reg(adapter,
6433 SGE_EGRESS_QUEUES_PER_PAGE_PF) >> s_qpp);
6434 num_seg = PAGE_SIZE / SEGMENT_SIZE;
6435
6436 /* Each segment size is 128B. Write coalescing is enabled only
6437 * when SGE_EGRESS_QUEUES_PER_PAGE_PF reg value for the
6438 * queue is less no of segments that can be accommodated in
6439 * a page size.
6440 */
6441 if (qpp > num_seg) {
6442 dev_err(&pdev->dev,
6443 "Incorrect number of egress queues per page\n");
6444 err = -EINVAL;
6445 goto out_unmap_bar0;
6446 }
6447 adapter->bar2 = ioremap_wc(pci_resource_start(pdev, 2),
6448 pci_resource_len(pdev, 2));
6449 if (!adapter->bar2) {
6450 dev_err(&pdev->dev, "cannot map device bar2 region\n");
6451 err = -ENOMEM;
6452 goto out_unmap_bar0;
6453 }
6454 }
6455
636f9d37 6456 setup_memwin(adapter);
b8ff05a9 6457 err = adap_init0(adapter);
636f9d37 6458 setup_memwin_rdma(adapter);
b8ff05a9
DM		 6459 if (err)
6460 goto out_unmap_bar;
6461
6462 for_each_port(adapter, i) {
6463 struct net_device *netdev;
6464
6465 netdev = alloc_etherdev_mq(sizeof(struct port_info),
6466 MAX_ETH_QSETS);
6467 if (!netdev) {
6468 err = -ENOMEM;
6469 goto out_free_dev;
6470 }
6471
6472 SET_NETDEV_DEV(netdev, &pdev->dev);
6473
6474 adapter->port[i] = netdev;
6475 pi = netdev_priv(netdev);
6476 pi->adapter = adapter;
6477 pi->xact_addr_filt = -1;
b8ff05a9 6478 pi->port_id = i;
b8ff05a9
DM		 6479 netdev->irq = pdev->irq;
6480
2ed28baa
MM		 6481 netdev->hw_features = NETIF_F_SG | TSO_FLAGS |
6482 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
6483 NETIF_F_RXCSUM | NETIF_F_RXHASH |
f646968f 6484 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
c8f44aff
MM		 6485 if (highdma)
6486 netdev->hw_features |= NETIF_F_HIGHDMA;
6487 netdev->features |= netdev->hw_features;
b8ff05a9
DM		 6488 netdev->vlan_features = netdev->features & VLAN_FEAT;
6489
01789349
JP		 6490 netdev->priv_flags |= IFF_UNICAST_FLT;
6491
b8ff05a9 6492 netdev->netdev_ops = &cxgb4_netdev_ops;
688848b1
AB		 6493#ifdef CONFIG_CHELSIO_T4_DCB
6494 netdev->dcbnl_ops = &cxgb4_dcb_ops;
6495 cxgb4_dcb_state_init(netdev);
6496#endif
7ad24ea4 6497 netdev->ethtool_ops = &cxgb_ethtool_ops;
b8ff05a9
DM		 6498 }
6499
6500 pci_set_drvdata(pdev, adapter);
6501
6502 if (adapter->flags & FW_OK) {
060e0c75 6503 err = t4_port_init(adapter, func, func, 0);
b8ff05a9
DM		 6504 if (err)
6505 goto out_free_dev;
6506 }
6507
6508 /*
6509 * Configure queues and allocate tables now, they can be needed as
6510 * soon as the first register_netdev completes.
6511 */
6512 cfg_queues(adapter);
6513
6514 adapter->l2t = t4_init_l2t();
6515 if (!adapter->l2t) {
6516 /* We tolerate a lack of L2T, giving up some functionality */
6517 dev_warn(&pdev->dev, "could not allocate L2T, continuing\n");
6518 adapter->params.offload = 0;
6519 }
6520
6521 if (is_offload(adapter) && tid_init(&adapter->tids) < 0) {
6522 dev_warn(&pdev->dev, "could not allocate TID table, "
6523 "continuing\n");
6524 adapter->params.offload = 0;
6525 }
6526
f7cabcdd
DM		 6527 /* See what interrupts we'll be using */
6528 if (msi > 1 && enable_msix(adapter) == 0)
6529 adapter->flags |= USING_MSIX;
6530 else if (msi > 0 && pci_enable_msi(pdev) == 0)
6531 adapter->flags |= USING_MSI;
6532
671b0060
DM		 6533 err = init_rss(adapter);
6534 if (err)
6535 goto out_free_dev;
6536
b8ff05a9
DM		 6537 /*
6538 * The card is now ready to go. If any errors occur during device
6539 * registration we do not fail the whole card but rather proceed only
6540 * with the ports we manage to register successfully. However we must
6541 * register at least one net device.
6542 */
6543 for_each_port(adapter, i) {
a57cabe0
DM		 6544 pi = adap2pinfo(adapter, i);
6545 netif_set_real_num_tx_queues(adapter->port[i], pi->nqsets);
6546 netif_set_real_num_rx_queues(adapter->port[i], pi->nqsets);
6547
b8ff05a9
DM		 6548 err = register_netdev(adapter->port[i]);
6549 if (err)
b1a3c2b6 6550 break;
b1a3c2b6
DM		 6551 adapter->chan_map[pi->tx_chan] = i;
6552 print_port_info(adapter->port[i]);
b8ff05a9 6553 }
b1a3c2b6 6554 if (i == 0) {
b8ff05a9
DM		 6555 dev_err(&pdev->dev, "could not register any net devices\n");
6556 goto out_free_dev;
6557 }
b1a3c2b6
DM		 6558 if (err) {
6559 dev_warn(&pdev->dev, "only %d net devices registered\n", i);
6560 err = 0;
6403eab1 6561 }
b8ff05a9
DM		 6562
6563 if (cxgb4_debugfs_root) {
6564 adapter->debugfs_root = debugfs_create_dir(pci_name(pdev),
6565 cxgb4_debugfs_root);
6566 setup_debugfs(adapter);
6567 }
6568
6482aa7c
DLR		 6569 /* PCIe EEH recovery on powerpc platforms needs fundamental reset */
6570 pdev->needs_freset = 1;
6571
b8ff05a9
DM		 6572 if (is_offload(adapter))
6573 attach_ulds(adapter);
6574
b8ff05a9 6575#ifdef CONFIG_PCI_IOV
7d6727cf 6576 if (func < ARRAY_SIZE(num_vf) && num_vf[func] > 0)
b8ff05a9
DM		 6577 if (pci_enable_sriov(pdev, num_vf[func]) == 0)
6578 dev_info(&pdev->dev,
6579 "instantiated %u virtual functions\n",
6580 num_vf[func]);
6581#endif
6582 return 0;
6583
6584 out_free_dev:
06546391 6585 free_some_resources(adapter);
b8ff05a9 6586 out_unmap_bar:
d14807dd 6587 if (!is_t4(adapter->params.chip))
22adfe0a
SR		 6588 iounmap(adapter->bar2);
6589 out_unmap_bar0:
b8ff05a9
DM		 6590 iounmap(adapter->regs);
6591 out_free_adapter:
6592 kfree(adapter);
6593 out_disable_device:
6594 pci_disable_pcie_error_reporting(pdev);
6595 pci_disable_device(pdev);
6596 out_release_regions:
6597 pci_release_regions(pdev);
b8ff05a9
DM		 6598 return err;
6599}
6600
91744948 6601static void remove_one(struct pci_dev *pdev)
b8ff05a9
DM		 6602{
6603 struct adapter *adapter = pci_get_drvdata(pdev);
6604
636f9d37 6605#ifdef CONFIG_PCI_IOV
b8ff05a9
DM		 6606 pci_disable_sriov(pdev);
6607
636f9d37
VP		 6608#endif
6609
b8ff05a9
DM		 6610 if (adapter) {
6611 int i;
6612
6613 if (is_offload(adapter))
6614 detach_ulds(adapter);
6615
6616 for_each_port(adapter, i)
8f3a7676 6617 if (adapter->port[i]->reg_state == NETREG_REGISTERED)
b8ff05a9
DM		 6618 unregister_netdev(adapter->port[i]);
6619
6620 if (adapter->debugfs_root)
6621 debugfs_remove_recursive(adapter->debugfs_root);
6622
f2b7e78d
VP		 6623 /* If we allocated filters, free up state associated with any
6624 * valid filters ...
6625 */
6626 if (adapter->tids.ftid_tab) {
6627 struct filter_entry *f = &adapter->tids.ftid_tab[0];
dca4faeb
VP		 6628 for (i = 0; i < (adapter->tids.nftids +
6629 adapter->tids.nsftids); i++, f++)
f2b7e78d
VP		 6630 if (f->valid)
6631 clear_filter(adapter, f);
6632 }
6633
aaefae9b
DM		 6634 if (adapter->flags & FULL_INIT_DONE)
6635 cxgb_down(adapter);
b8ff05a9 6636
06546391 6637 free_some_resources(adapter);
b8ff05a9 6638 iounmap(adapter->regs);
d14807dd 6639 if (!is_t4(adapter->params.chip))
22adfe0a 6640 iounmap(adapter->bar2);
b8ff05a9 6641 pci_disable_pcie_error_reporting(pdev);
144be3d9
GS		 6642 if ((adapter->flags & DEV_ENABLED)) {
6643 pci_disable_device(pdev);
6644 adapter->flags &= ~DEV_ENABLED;
6645 }
b8ff05a9 6646 pci_release_regions(pdev);
ee9a33b2 6647 synchronize_rcu();
8b662fe7 6648 kfree(adapter);
a069ec91 6649 } else
b8ff05a9
DM		 6650 pci_release_regions(pdev);
6651}
6652
6653static struct pci_driver cxgb4_driver = {
6654 .name = KBUILD_MODNAME,
6655 .id_table = cxgb4_pci_tbl,
6656 .probe = init_one,
91744948 6657 .remove = remove_one,
687d705c 6658 .shutdown = remove_one,
204dc3c0 6659 .err_handler = &cxgb4_eeh,
b8ff05a9
DM		 6660};
6661
6662static int __init cxgb4_init_module(void)
6663{
6664 int ret;
6665
3069ee9b
VP		 6666 workq = create_singlethread_workqueue("cxgb4");
6667 if (!workq)
6668 return -ENOMEM;
6669
b8ff05a9
DM		 6670 /* Debugfs support is optional, just warn if this fails */
6671 cxgb4_debugfs_root = debugfs_create_dir(KBUILD_MODNAME, NULL);
6672 if (!cxgb4_debugfs_root)
428ac43f 6673 pr_warn("could not create debugfs entry, continuing\n");
b8ff05a9
DM		 6674
6675 ret = pci_register_driver(&cxgb4_driver);
73a695f8 6676 if (ret < 0) {
b8ff05a9 6677 debugfs_remove(cxgb4_debugfs_root);
73a695f8
WY		 6678 destroy_workqueue(workq);
6679 }
01bcca68
VP		 6680
6681 register_inet6addr_notifier(&cxgb4_inet6addr_notifier);
6682
b8ff05a9
DM		 6683 return ret;
6684}
6685
6686static void __exit cxgb4_cleanup_module(void)
6687{
01bcca68 6688 unregister_inet6addr_notifier(&cxgb4_inet6addr_notifier);
b8ff05a9
DM		 6689 pci_unregister_driver(&cxgb4_driver);
6690 debugfs_remove(cxgb4_debugfs_root); /* NULL ok */
3069ee9b
VP		 6691 flush_workqueue(workq);
6692 destroy_workqueue(workq);
b8ff05a9
DM		 6693}
6694
6695module_init(cxgb4_init_module);
6696module_exit(cxgb4_cleanup_module);
Linux kernel - Deliverables
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