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fd3a4790 DM |
1 | /* |
2 | * This file is part of the Chelsio T4 Ethernet driver for Linux. | |
3 | * | |
ce100b8b | 4 | * Copyright (c) 2003-2014 Chelsio Communications, Inc. All rights reserved. |
fd3a4790 DM |
5 | * |
6 | * This software is available to you under a choice of one of two | |
7 | * licenses. You may choose to be licensed under the terms of the GNU | |
8 | * General Public License (GPL) Version 2, available from the file | |
9 | * COPYING in the main directory of this source tree, or the | |
10 | * OpenIB.org BSD license below: | |
11 | * | |
12 | * Redistribution and use in source and binary forms, with or | |
13 | * without modification, are permitted provided that the following | |
14 | * conditions are met: | |
15 | * | |
16 | * - Redistributions of source code must retain the above | |
17 | * copyright notice, this list of conditions and the following | |
18 | * disclaimer. | |
19 | * | |
20 | * - Redistributions in binary form must reproduce the above | |
21 | * copyright notice, this list of conditions and the following | |
22 | * disclaimer in the documentation and/or other materials | |
23 | * provided with the distribution. | |
24 | * | |
25 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
26 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
27 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
28 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
29 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
30 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
31 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
32 | * SOFTWARE. | |
33 | */ | |
34 | ||
35 | #include <linux/skbuff.h> | |
36 | #include <linux/netdevice.h> | |
37 | #include <linux/etherdevice.h> | |
38 | #include <linux/if_vlan.h> | |
39 | #include <linux/ip.h> | |
40 | #include <linux/dma-mapping.h> | |
41 | #include <linux/jiffies.h> | |
70c71606 | 42 | #include <linux/prefetch.h> |
ee40fa06 | 43 | #include <linux/export.h> |
fd3a4790 DM |
44 | #include <net/ipv6.h> |
45 | #include <net/tcp.h> | |
46 | #include "cxgb4.h" | |
47 | #include "t4_regs.h" | |
48 | #include "t4_msg.h" | |
49 | #include "t4fw_api.h" | |
50 | ||
51 | /* | |
52 | * Rx buffer size. We use largish buffers if possible but settle for single | |
53 | * pages under memory shortage. | |
54 | */ | |
55 | #if PAGE_SHIFT >= 16 | |
56 | # define FL_PG_ORDER 0 | |
57 | #else | |
58 | # define FL_PG_ORDER (16 - PAGE_SHIFT) | |
59 | #endif | |
60 | ||
61 | /* RX_PULL_LEN should be <= RX_COPY_THRES */ | |
62 | #define RX_COPY_THRES 256 | |
63 | #define RX_PULL_LEN 128 | |
64 | ||
65 | /* | |
66 | * Main body length for sk_buffs used for Rx Ethernet packets with fragments. | |
67 | * Should be >= RX_PULL_LEN but possibly bigger to give pskb_may_pull some room. | |
68 | */ | |
69 | #define RX_PKT_SKB_LEN 512 | |
70 | ||
fd3a4790 DM |
71 | /* |
72 | * Max number of Tx descriptors we clean up at a time. Should be modest as | |
73 | * freeing skbs isn't cheap and it happens while holding locks. We just need | |
74 | * to free packets faster than they arrive, we eventually catch up and keep | |
75 | * the amortized cost reasonable. Must be >= 2 * TXQ_STOP_THRES. | |
76 | */ | |
77 | #define MAX_TX_RECLAIM 16 | |
78 | ||
79 | /* | |
80 | * Max number of Rx buffers we replenish at a time. Again keep this modest, | |
81 | * allocating buffers isn't cheap either. | |
82 | */ | |
83 | #define MAX_RX_REFILL 16U | |
84 | ||
85 | /* | |
86 | * Period of the Rx queue check timer. This timer is infrequent as it has | |
87 | * something to do only when the system experiences severe memory shortage. | |
88 | */ | |
89 | #define RX_QCHECK_PERIOD (HZ / 2) | |
90 | ||
91 | /* | |
92 | * Period of the Tx queue check timer. | |
93 | */ | |
94 | #define TX_QCHECK_PERIOD (HZ / 2) | |
95 | ||
0f4d201f KS |
96 | /* SGE Hung Ingress DMA Threshold Warning time (in Hz) and Warning Repeat Rate |
97 | * (in RX_QCHECK_PERIOD multiples). If we find one of the SGE Ingress DMA | |
98 | * State Machines in the same state for this amount of time (in HZ) then we'll | |
99 | * issue a warning about a potential hang. We'll repeat the warning as the | |
100 | * SGE Ingress DMA Channel appears to be hung every N RX_QCHECK_PERIODs till | |
101 | * the situation clears. If the situation clears, we'll note that as well. | |
102 | */ | |
103 | #define SGE_IDMA_WARN_THRESH (1 * HZ) | |
104 | #define SGE_IDMA_WARN_REPEAT (20 * RX_QCHECK_PERIOD) | |
105 | ||
fd3a4790 DM |
106 | /* |
107 | * Max number of Tx descriptors to be reclaimed by the Tx timer. | |
108 | */ | |
109 | #define MAX_TIMER_TX_RECLAIM 100 | |
110 | ||
111 | /* | |
112 | * Timer index used when backing off due to memory shortage. | |
113 | */ | |
114 | #define NOMEM_TMR_IDX (SGE_NTIMERS - 1) | |
115 | ||
116 | /* | |
117 | * An FL with <= FL_STARVE_THRES buffers is starving and a periodic timer will | |
118 | * attempt to refill it. | |
119 | */ | |
120 | #define FL_STARVE_THRES 4 | |
121 | ||
122 | /* | |
123 | * Suspend an Ethernet Tx queue with fewer available descriptors than this. | |
124 | * This is the same as calc_tx_descs() for a TSO packet with | |
125 | * nr_frags == MAX_SKB_FRAGS. | |
126 | */ | |
127 | #define ETHTXQ_STOP_THRES \ | |
128 | (1 + DIV_ROUND_UP((3 * MAX_SKB_FRAGS) / 2 + (MAX_SKB_FRAGS & 1), 8)) | |
129 | ||
130 | /* | |
131 | * Suspension threshold for non-Ethernet Tx queues. We require enough room | |
132 | * for a full sized WR. | |
133 | */ | |
134 | #define TXQ_STOP_THRES (SGE_MAX_WR_LEN / sizeof(struct tx_desc)) | |
135 | ||
136 | /* | |
137 | * Max Tx descriptor space we allow for an Ethernet packet to be inlined | |
138 | * into a WR. | |
139 | */ | |
140 | #define MAX_IMM_TX_PKT_LEN 128 | |
141 | ||
142 | /* | |
143 | * Max size of a WR sent through a control Tx queue. | |
144 | */ | |
145 | #define MAX_CTRL_WR_LEN SGE_MAX_WR_LEN | |
146 | ||
fd3a4790 DM |
147 | struct tx_sw_desc { /* SW state per Tx descriptor */ |
148 | struct sk_buff *skb; | |
149 | struct ulptx_sgl *sgl; | |
150 | }; | |
151 | ||
152 | struct rx_sw_desc { /* SW state per Rx descriptor */ | |
153 | struct page *page; | |
154 | dma_addr_t dma_addr; | |
155 | }; | |
156 | ||
157 | /* | |
52367a76 VP |
158 | * Rx buffer sizes for "useskbs" Free List buffers (one ingress packet pe skb |
159 | * buffer). We currently only support two sizes for 1500- and 9000-byte MTUs. | |
160 | * We could easily support more but there doesn't seem to be much need for | |
161 | * that ... | |
162 | */ | |
163 | #define FL_MTU_SMALL 1500 | |
164 | #define FL_MTU_LARGE 9000 | |
165 | ||
166 | static inline unsigned int fl_mtu_bufsize(struct adapter *adapter, | |
167 | unsigned int mtu) | |
168 | { | |
169 | struct sge *s = &adapter->sge; | |
170 | ||
171 | return ALIGN(s->pktshift + ETH_HLEN + VLAN_HLEN + mtu, s->fl_align); | |
172 | } | |
173 | ||
174 | #define FL_MTU_SMALL_BUFSIZE(adapter) fl_mtu_bufsize(adapter, FL_MTU_SMALL) | |
175 | #define FL_MTU_LARGE_BUFSIZE(adapter) fl_mtu_bufsize(adapter, FL_MTU_LARGE) | |
176 | ||
177 | /* | |
178 | * Bits 0..3 of rx_sw_desc.dma_addr have special meaning. The hardware uses | |
179 | * these to specify the buffer size as an index into the SGE Free List Buffer | |
180 | * Size register array. We also use bit 4, when the buffer has been unmapped | |
181 | * for DMA, but this is of course never sent to the hardware and is only used | |
182 | * to prevent double unmappings. All of the above requires that the Free List | |
183 | * Buffers which we allocate have the bottom 5 bits free (0) -- i.e. are | |
184 | * 32-byte or or a power of 2 greater in alignment. Since the SGE's minimal | |
185 | * Free List Buffer alignment is 32 bytes, this works out for us ... | |
fd3a4790 DM |
186 | */ |
187 | enum { | |
52367a76 VP |
188 | RX_BUF_FLAGS = 0x1f, /* bottom five bits are special */ |
189 | RX_BUF_SIZE = 0x0f, /* bottom three bits are for buf sizes */ | |
190 | RX_UNMAPPED_BUF = 0x10, /* buffer is not mapped */ | |
191 | ||
192 | /* | |
193 | * XXX We shouldn't depend on being able to use these indices. | |
194 | * XXX Especially when some other Master PF has initialized the | |
195 | * XXX adapter or we use the Firmware Configuration File. We | |
196 | * XXX should really search through the Host Buffer Size register | |
197 | * XXX array for the appropriately sized buffer indices. | |
198 | */ | |
199 | RX_SMALL_PG_BUF = 0x0, /* small (PAGE_SIZE) page buffer */ | |
200 | RX_LARGE_PG_BUF = 0x1, /* buffer large (FL_PG_ORDER) page buffer */ | |
201 | ||
202 | RX_SMALL_MTU_BUF = 0x2, /* small MTU buffer */ | |
203 | RX_LARGE_MTU_BUF = 0x3, /* large MTU buffer */ | |
fd3a4790 DM |
204 | }; |
205 | ||
206 | static inline dma_addr_t get_buf_addr(const struct rx_sw_desc *d) | |
207 | { | |
52367a76 | 208 | return d->dma_addr & ~(dma_addr_t)RX_BUF_FLAGS; |
fd3a4790 DM |
209 | } |
210 | ||
211 | static inline bool is_buf_mapped(const struct rx_sw_desc *d) | |
212 | { | |
213 | return !(d->dma_addr & RX_UNMAPPED_BUF); | |
214 | } | |
215 | ||
216 | /** | |
217 | * txq_avail - return the number of available slots in a Tx queue | |
218 | * @q: the Tx queue | |
219 | * | |
220 | * Returns the number of descriptors in a Tx queue available to write new | |
221 | * packets. | |
222 | */ | |
223 | static inline unsigned int txq_avail(const struct sge_txq *q) | |
224 | { | |
225 | return q->size - 1 - q->in_use; | |
226 | } | |
227 | ||
228 | /** | |
229 | * fl_cap - return the capacity of a free-buffer list | |
230 | * @fl: the FL | |
231 | * | |
232 | * Returns the capacity of a free-buffer list. The capacity is less than | |
233 | * the size because one descriptor needs to be left unpopulated, otherwise | |
234 | * HW will think the FL is empty. | |
235 | */ | |
236 | static inline unsigned int fl_cap(const struct sge_fl *fl) | |
237 | { | |
238 | return fl->size - 8; /* 1 descriptor = 8 buffers */ | |
239 | } | |
240 | ||
241 | static inline bool fl_starving(const struct sge_fl *fl) | |
242 | { | |
243 | return fl->avail - fl->pend_cred <= FL_STARVE_THRES; | |
244 | } | |
245 | ||
246 | static int map_skb(struct device *dev, const struct sk_buff *skb, | |
247 | dma_addr_t *addr) | |
248 | { | |
249 | const skb_frag_t *fp, *end; | |
250 | const struct skb_shared_info *si; | |
251 | ||
252 | *addr = dma_map_single(dev, skb->data, skb_headlen(skb), DMA_TO_DEVICE); | |
253 | if (dma_mapping_error(dev, *addr)) | |
254 | goto out_err; | |
255 | ||
256 | si = skb_shinfo(skb); | |
257 | end = &si->frags[si->nr_frags]; | |
258 | ||
259 | for (fp = si->frags; fp < end; fp++) { | |
e91b0f24 IC |
260 | *++addr = skb_frag_dma_map(dev, fp, 0, skb_frag_size(fp), |
261 | DMA_TO_DEVICE); | |
fd3a4790 DM |
262 | if (dma_mapping_error(dev, *addr)) |
263 | goto unwind; | |
264 | } | |
265 | return 0; | |
266 | ||
267 | unwind: | |
268 | while (fp-- > si->frags) | |
9e903e08 | 269 | dma_unmap_page(dev, *--addr, skb_frag_size(fp), DMA_TO_DEVICE); |
fd3a4790 DM |
270 | |
271 | dma_unmap_single(dev, addr[-1], skb_headlen(skb), DMA_TO_DEVICE); | |
272 | out_err: | |
273 | return -ENOMEM; | |
274 | } | |
275 | ||
276 | #ifdef CONFIG_NEED_DMA_MAP_STATE | |
277 | static void unmap_skb(struct device *dev, const struct sk_buff *skb, | |
278 | const dma_addr_t *addr) | |
279 | { | |
280 | const skb_frag_t *fp, *end; | |
281 | const struct skb_shared_info *si; | |
282 | ||
283 | dma_unmap_single(dev, *addr++, skb_headlen(skb), DMA_TO_DEVICE); | |
284 | ||
285 | si = skb_shinfo(skb); | |
286 | end = &si->frags[si->nr_frags]; | |
287 | for (fp = si->frags; fp < end; fp++) | |
9e903e08 | 288 | dma_unmap_page(dev, *addr++, skb_frag_size(fp), DMA_TO_DEVICE); |
fd3a4790 DM |
289 | } |
290 | ||
291 | /** | |
292 | * deferred_unmap_destructor - unmap a packet when it is freed | |
293 | * @skb: the packet | |
294 | * | |
295 | * This is the packet destructor used for Tx packets that need to remain | |
296 | * mapped until they are freed rather than until their Tx descriptors are | |
297 | * freed. | |
298 | */ | |
299 | static void deferred_unmap_destructor(struct sk_buff *skb) | |
300 | { | |
301 | unmap_skb(skb->dev->dev.parent, skb, (dma_addr_t *)skb->head); | |
302 | } | |
303 | #endif | |
304 | ||
305 | static void unmap_sgl(struct device *dev, const struct sk_buff *skb, | |
306 | const struct ulptx_sgl *sgl, const struct sge_txq *q) | |
307 | { | |
308 | const struct ulptx_sge_pair *p; | |
309 | unsigned int nfrags = skb_shinfo(skb)->nr_frags; | |
310 | ||
311 | if (likely(skb_headlen(skb))) | |
312 | dma_unmap_single(dev, be64_to_cpu(sgl->addr0), ntohl(sgl->len0), | |
313 | DMA_TO_DEVICE); | |
314 | else { | |
315 | dma_unmap_page(dev, be64_to_cpu(sgl->addr0), ntohl(sgl->len0), | |
316 | DMA_TO_DEVICE); | |
317 | nfrags--; | |
318 | } | |
319 | ||
320 | /* | |
321 | * the complexity below is because of the possibility of a wrap-around | |
322 | * in the middle of an SGL | |
323 | */ | |
324 | for (p = sgl->sge; nfrags >= 2; nfrags -= 2) { | |
325 | if (likely((u8 *)(p + 1) <= (u8 *)q->stat)) { | |
326 | unmap: dma_unmap_page(dev, be64_to_cpu(p->addr[0]), | |
327 | ntohl(p->len[0]), DMA_TO_DEVICE); | |
328 | dma_unmap_page(dev, be64_to_cpu(p->addr[1]), | |
329 | ntohl(p->len[1]), DMA_TO_DEVICE); | |
330 | p++; | |
331 | } else if ((u8 *)p == (u8 *)q->stat) { | |
332 | p = (const struct ulptx_sge_pair *)q->desc; | |
333 | goto unmap; | |
334 | } else if ((u8 *)p + 8 == (u8 *)q->stat) { | |
335 | const __be64 *addr = (const __be64 *)q->desc; | |
336 | ||
337 | dma_unmap_page(dev, be64_to_cpu(addr[0]), | |
338 | ntohl(p->len[0]), DMA_TO_DEVICE); | |
339 | dma_unmap_page(dev, be64_to_cpu(addr[1]), | |
340 | ntohl(p->len[1]), DMA_TO_DEVICE); | |
341 | p = (const struct ulptx_sge_pair *)&addr[2]; | |
342 | } else { | |
343 | const __be64 *addr = (const __be64 *)q->desc; | |
344 | ||
345 | dma_unmap_page(dev, be64_to_cpu(p->addr[0]), | |
346 | ntohl(p->len[0]), DMA_TO_DEVICE); | |
347 | dma_unmap_page(dev, be64_to_cpu(addr[0]), | |
348 | ntohl(p->len[1]), DMA_TO_DEVICE); | |
349 | p = (const struct ulptx_sge_pair *)&addr[1]; | |
350 | } | |
351 | } | |
352 | if (nfrags) { | |
353 | __be64 addr; | |
354 | ||
355 | if ((u8 *)p == (u8 *)q->stat) | |
356 | p = (const struct ulptx_sge_pair *)q->desc; | |
357 | addr = (u8 *)p + 16 <= (u8 *)q->stat ? p->addr[0] : | |
358 | *(const __be64 *)q->desc; | |
359 | dma_unmap_page(dev, be64_to_cpu(addr), ntohl(p->len[0]), | |
360 | DMA_TO_DEVICE); | |
361 | } | |
362 | } | |
363 | ||
364 | /** | |
365 | * free_tx_desc - reclaims Tx descriptors and their buffers | |
366 | * @adapter: the adapter | |
367 | * @q: the Tx queue to reclaim descriptors from | |
368 | * @n: the number of descriptors to reclaim | |
369 | * @unmap: whether the buffers should be unmapped for DMA | |
370 | * | |
371 | * Reclaims Tx descriptors from an SGE Tx queue and frees the associated | |
372 | * Tx buffers. Called with the Tx queue lock held. | |
373 | */ | |
374 | static void free_tx_desc(struct adapter *adap, struct sge_txq *q, | |
375 | unsigned int n, bool unmap) | |
376 | { | |
377 | struct tx_sw_desc *d; | |
378 | unsigned int cidx = q->cidx; | |
379 | struct device *dev = adap->pdev_dev; | |
380 | ||
381 | d = &q->sdesc[cidx]; | |
382 | while (n--) { | |
383 | if (d->skb) { /* an SGL is present */ | |
384 | if (unmap) | |
385 | unmap_sgl(dev, d->skb, d->sgl, q); | |
a7525198 | 386 | dev_consume_skb_any(d->skb); |
fd3a4790 DM |
387 | d->skb = NULL; |
388 | } | |
389 | ++d; | |
390 | if (++cidx == q->size) { | |
391 | cidx = 0; | |
392 | d = q->sdesc; | |
393 | } | |
394 | } | |
395 | q->cidx = cidx; | |
396 | } | |
397 | ||
398 | /* | |
399 | * Return the number of reclaimable descriptors in a Tx queue. | |
400 | */ | |
401 | static inline int reclaimable(const struct sge_txq *q) | |
402 | { | |
403 | int hw_cidx = ntohs(q->stat->cidx); | |
404 | hw_cidx -= q->cidx; | |
405 | return hw_cidx < 0 ? hw_cidx + q->size : hw_cidx; | |
406 | } | |
407 | ||
408 | /** | |
409 | * reclaim_completed_tx - reclaims completed Tx descriptors | |
410 | * @adap: the adapter | |
411 | * @q: the Tx queue to reclaim completed descriptors from | |
412 | * @unmap: whether the buffers should be unmapped for DMA | |
413 | * | |
414 | * Reclaims Tx descriptors that the SGE has indicated it has processed, | |
415 | * and frees the associated buffers if possible. Called with the Tx | |
416 | * queue locked. | |
417 | */ | |
418 | static inline void reclaim_completed_tx(struct adapter *adap, struct sge_txq *q, | |
419 | bool unmap) | |
420 | { | |
421 | int avail = reclaimable(q); | |
422 | ||
423 | if (avail) { | |
424 | /* | |
425 | * Limit the amount of clean up work we do at a time to keep | |
426 | * the Tx lock hold time O(1). | |
427 | */ | |
428 | if (avail > MAX_TX_RECLAIM) | |
429 | avail = MAX_TX_RECLAIM; | |
430 | ||
431 | free_tx_desc(adap, q, avail, unmap); | |
432 | q->in_use -= avail; | |
433 | } | |
434 | } | |
435 | ||
52367a76 VP |
436 | static inline int get_buf_size(struct adapter *adapter, |
437 | const struct rx_sw_desc *d) | |
fd3a4790 | 438 | { |
52367a76 VP |
439 | struct sge *s = &adapter->sge; |
440 | unsigned int rx_buf_size_idx = d->dma_addr & RX_BUF_SIZE; | |
441 | int buf_size; | |
442 | ||
443 | switch (rx_buf_size_idx) { | |
444 | case RX_SMALL_PG_BUF: | |
445 | buf_size = PAGE_SIZE; | |
446 | break; | |
447 | ||
448 | case RX_LARGE_PG_BUF: | |
449 | buf_size = PAGE_SIZE << s->fl_pg_order; | |
450 | break; | |
451 | ||
452 | case RX_SMALL_MTU_BUF: | |
453 | buf_size = FL_MTU_SMALL_BUFSIZE(adapter); | |
454 | break; | |
455 | ||
456 | case RX_LARGE_MTU_BUF: | |
457 | buf_size = FL_MTU_LARGE_BUFSIZE(adapter); | |
458 | break; | |
459 | ||
460 | default: | |
461 | BUG_ON(1); | |
462 | } | |
463 | ||
464 | return buf_size; | |
fd3a4790 DM |
465 | } |
466 | ||
467 | /** | |
468 | * free_rx_bufs - free the Rx buffers on an SGE free list | |
469 | * @adap: the adapter | |
470 | * @q: the SGE free list to free buffers from | |
471 | * @n: how many buffers to free | |
472 | * | |
473 | * Release the next @n buffers on an SGE free-buffer Rx queue. The | |
474 | * buffers must be made inaccessible to HW before calling this function. | |
475 | */ | |
476 | static void free_rx_bufs(struct adapter *adap, struct sge_fl *q, int n) | |
477 | { | |
478 | while (n--) { | |
479 | struct rx_sw_desc *d = &q->sdesc[q->cidx]; | |
480 | ||
481 | if (is_buf_mapped(d)) | |
482 | dma_unmap_page(adap->pdev_dev, get_buf_addr(d), | |
52367a76 VP |
483 | get_buf_size(adap, d), |
484 | PCI_DMA_FROMDEVICE); | |
fd3a4790 DM |
485 | put_page(d->page); |
486 | d->page = NULL; | |
487 | if (++q->cidx == q->size) | |
488 | q->cidx = 0; | |
489 | q->avail--; | |
490 | } | |
491 | } | |
492 | ||
493 | /** | |
494 | * unmap_rx_buf - unmap the current Rx buffer on an SGE free list | |
495 | * @adap: the adapter | |
496 | * @q: the SGE free list | |
497 | * | |
498 | * Unmap the current buffer on an SGE free-buffer Rx queue. The | |
499 | * buffer must be made inaccessible to HW before calling this function. | |
500 | * | |
501 | * This is similar to @free_rx_bufs above but does not free the buffer. | |
502 | * Do note that the FL still loses any further access to the buffer. | |
503 | */ | |
504 | static void unmap_rx_buf(struct adapter *adap, struct sge_fl *q) | |
505 | { | |
506 | struct rx_sw_desc *d = &q->sdesc[q->cidx]; | |
507 | ||
508 | if (is_buf_mapped(d)) | |
509 | dma_unmap_page(adap->pdev_dev, get_buf_addr(d), | |
52367a76 | 510 | get_buf_size(adap, d), PCI_DMA_FROMDEVICE); |
fd3a4790 DM |
511 | d->page = NULL; |
512 | if (++q->cidx == q->size) | |
513 | q->cidx = 0; | |
514 | q->avail--; | |
515 | } | |
516 | ||
517 | static inline void ring_fl_db(struct adapter *adap, struct sge_fl *q) | |
518 | { | |
0a57a536 | 519 | u32 val; |
fd3a4790 | 520 | if (q->pend_cred >= 8) { |
0a57a536 | 521 | val = PIDX(q->pend_cred / 8); |
d14807dd | 522 | if (!is_t4(adap->params.chip)) |
0a57a536 | 523 | val |= DBTYPE(1); |
d63a6dcf | 524 | val |= DBPRIO(1); |
fd3a4790 | 525 | wmb(); |
d63a6dcf HS |
526 | |
527 | /* If we're on T4, use the old doorbell mechanism; otherwise | |
528 | * use the new BAR2 mechanism. | |
529 | */ | |
530 | if (is_t4(adap->params.chip)) { | |
531 | t4_write_reg(adap, MYPF_REG(SGE_PF_KDOORBELL), | |
532 | val | QID(q->cntxt_id)); | |
533 | } else { | |
534 | writel(val, adap->bar2 + q->udb + SGE_UDB_KDOORBELL); | |
535 | ||
536 | /* This Write memory Barrier will force the write to | |
537 | * the User Doorbell area to be flushed. | |
538 | */ | |
539 | wmb(); | |
540 | } | |
fd3a4790 DM |
541 | q->pend_cred &= 7; |
542 | } | |
543 | } | |
544 | ||
545 | static inline void set_rx_sw_desc(struct rx_sw_desc *sd, struct page *pg, | |
546 | dma_addr_t mapping) | |
547 | { | |
548 | sd->page = pg; | |
549 | sd->dma_addr = mapping; /* includes size low bits */ | |
550 | } | |
551 | ||
552 | /** | |
553 | * refill_fl - refill an SGE Rx buffer ring | |
554 | * @adap: the adapter | |
555 | * @q: the ring to refill | |
556 | * @n: the number of new buffers to allocate | |
557 | * @gfp: the gfp flags for the allocations | |
558 | * | |
559 | * (Re)populate an SGE free-buffer queue with up to @n new packet buffers, | |
560 | * allocated with the supplied gfp flags. The caller must assure that | |
561 | * @n does not exceed the queue's capacity. If afterwards the queue is | |
562 | * found critically low mark it as starving in the bitmap of starving FLs. | |
563 | * | |
564 | * Returns the number of buffers allocated. | |
565 | */ | |
566 | static unsigned int refill_fl(struct adapter *adap, struct sge_fl *q, int n, | |
567 | gfp_t gfp) | |
568 | { | |
52367a76 | 569 | struct sge *s = &adap->sge; |
fd3a4790 DM |
570 | struct page *pg; |
571 | dma_addr_t mapping; | |
572 | unsigned int cred = q->avail; | |
573 | __be64 *d = &q->desc[q->pidx]; | |
574 | struct rx_sw_desc *sd = &q->sdesc[q->pidx]; | |
575 | ||
1f2149c1 | 576 | gfp |= __GFP_NOWARN | __GFP_COLD; |
fd3a4790 | 577 | |
52367a76 VP |
578 | if (s->fl_pg_order == 0) |
579 | goto alloc_small_pages; | |
580 | ||
fd3a4790 DM |
581 | /* |
582 | * Prefer large buffers | |
583 | */ | |
584 | while (n) { | |
52367a76 | 585 | pg = alloc_pages(gfp | __GFP_COMP, s->fl_pg_order); |
fd3a4790 DM |
586 | if (unlikely(!pg)) { |
587 | q->large_alloc_failed++; | |
588 | break; /* fall back to single pages */ | |
589 | } | |
590 | ||
591 | mapping = dma_map_page(adap->pdev_dev, pg, 0, | |
52367a76 | 592 | PAGE_SIZE << s->fl_pg_order, |
fd3a4790 DM |
593 | PCI_DMA_FROMDEVICE); |
594 | if (unlikely(dma_mapping_error(adap->pdev_dev, mapping))) { | |
52367a76 | 595 | __free_pages(pg, s->fl_pg_order); |
fd3a4790 DM |
596 | goto out; /* do not try small pages for this error */ |
597 | } | |
52367a76 | 598 | mapping |= RX_LARGE_PG_BUF; |
fd3a4790 DM |
599 | *d++ = cpu_to_be64(mapping); |
600 | ||
601 | set_rx_sw_desc(sd, pg, mapping); | |
602 | sd++; | |
603 | ||
604 | q->avail++; | |
605 | if (++q->pidx == q->size) { | |
606 | q->pidx = 0; | |
607 | sd = q->sdesc; | |
608 | d = q->desc; | |
609 | } | |
610 | n--; | |
611 | } | |
fd3a4790 | 612 | |
52367a76 | 613 | alloc_small_pages: |
fd3a4790 | 614 | while (n--) { |
0614002b | 615 | pg = __skb_alloc_page(gfp, NULL); |
fd3a4790 DM |
616 | if (unlikely(!pg)) { |
617 | q->alloc_failed++; | |
618 | break; | |
619 | } | |
620 | ||
621 | mapping = dma_map_page(adap->pdev_dev, pg, 0, PAGE_SIZE, | |
622 | PCI_DMA_FROMDEVICE); | |
623 | if (unlikely(dma_mapping_error(adap->pdev_dev, mapping))) { | |
1f2149c1 | 624 | put_page(pg); |
fd3a4790 DM |
625 | goto out; |
626 | } | |
627 | *d++ = cpu_to_be64(mapping); | |
628 | ||
629 | set_rx_sw_desc(sd, pg, mapping); | |
630 | sd++; | |
631 | ||
632 | q->avail++; | |
633 | if (++q->pidx == q->size) { | |
634 | q->pidx = 0; | |
635 | sd = q->sdesc; | |
636 | d = q->desc; | |
637 | } | |
638 | } | |
639 | ||
640 | out: cred = q->avail - cred; | |
641 | q->pend_cred += cred; | |
642 | ring_fl_db(adap, q); | |
643 | ||
644 | if (unlikely(fl_starving(q))) { | |
645 | smp_wmb(); | |
e46dab4d DM |
646 | set_bit(q->cntxt_id - adap->sge.egr_start, |
647 | adap->sge.starving_fl); | |
fd3a4790 DM |
648 | } |
649 | ||
650 | return cred; | |
651 | } | |
652 | ||
653 | static inline void __refill_fl(struct adapter *adap, struct sge_fl *fl) | |
654 | { | |
655 | refill_fl(adap, fl, min(MAX_RX_REFILL, fl_cap(fl) - fl->avail), | |
656 | GFP_ATOMIC); | |
657 | } | |
658 | ||
659 | /** | |
660 | * alloc_ring - allocate resources for an SGE descriptor ring | |
661 | * @dev: the PCI device's core device | |
662 | * @nelem: the number of descriptors | |
663 | * @elem_size: the size of each descriptor | |
664 | * @sw_size: the size of the SW state associated with each ring element | |
665 | * @phys: the physical address of the allocated ring | |
666 | * @metadata: address of the array holding the SW state for the ring | |
667 | * @stat_size: extra space in HW ring for status information | |
ad6bad3e | 668 | * @node: preferred node for memory allocations |
fd3a4790 DM |
669 | * |
670 | * Allocates resources for an SGE descriptor ring, such as Tx queues, | |
671 | * free buffer lists, or response queues. Each SGE ring requires | |
672 | * space for its HW descriptors plus, optionally, space for the SW state | |
673 | * associated with each HW entry (the metadata). The function returns | |
674 | * three values: the virtual address for the HW ring (the return value | |
675 | * of the function), the bus address of the HW ring, and the address | |
676 | * of the SW ring. | |
677 | */ | |
678 | static void *alloc_ring(struct device *dev, size_t nelem, size_t elem_size, | |
679 | size_t sw_size, dma_addr_t *phys, void *metadata, | |
ad6bad3e | 680 | size_t stat_size, int node) |
fd3a4790 DM |
681 | { |
682 | size_t len = nelem * elem_size + stat_size; | |
683 | void *s = NULL; | |
684 | void *p = dma_alloc_coherent(dev, len, phys, GFP_KERNEL); | |
685 | ||
686 | if (!p) | |
687 | return NULL; | |
688 | if (sw_size) { | |
ad6bad3e | 689 | s = kzalloc_node(nelem * sw_size, GFP_KERNEL, node); |
fd3a4790 DM |
690 | |
691 | if (!s) { | |
692 | dma_free_coherent(dev, len, p, *phys); | |
693 | return NULL; | |
694 | } | |
695 | } | |
696 | if (metadata) | |
697 | *(void **)metadata = s; | |
698 | memset(p, 0, len); | |
699 | return p; | |
700 | } | |
701 | ||
702 | /** | |
703 | * sgl_len - calculates the size of an SGL of the given capacity | |
704 | * @n: the number of SGL entries | |
705 | * | |
706 | * Calculates the number of flits needed for a scatter/gather list that | |
707 | * can hold the given number of entries. | |
708 | */ | |
709 | static inline unsigned int sgl_len(unsigned int n) | |
710 | { | |
711 | n--; | |
712 | return (3 * n) / 2 + (n & 1) + 2; | |
713 | } | |
714 | ||
715 | /** | |
716 | * flits_to_desc - returns the num of Tx descriptors for the given flits | |
717 | * @n: the number of flits | |
718 | * | |
719 | * Returns the number of Tx descriptors needed for the supplied number | |
720 | * of flits. | |
721 | */ | |
722 | static inline unsigned int flits_to_desc(unsigned int n) | |
723 | { | |
724 | BUG_ON(n > SGE_MAX_WR_LEN / 8); | |
725 | return DIV_ROUND_UP(n, 8); | |
726 | } | |
727 | ||
728 | /** | |
729 | * is_eth_imm - can an Ethernet packet be sent as immediate data? | |
730 | * @skb: the packet | |
731 | * | |
732 | * Returns whether an Ethernet packet is small enough to fit as | |
0034b298 | 733 | * immediate data. Return value corresponds to headroom required. |
fd3a4790 DM |
734 | */ |
735 | static inline int is_eth_imm(const struct sk_buff *skb) | |
736 | { | |
0034b298 KS |
737 | int hdrlen = skb_shinfo(skb)->gso_size ? |
738 | sizeof(struct cpl_tx_pkt_lso_core) : 0; | |
739 | ||
740 | hdrlen += sizeof(struct cpl_tx_pkt); | |
741 | if (skb->len <= MAX_IMM_TX_PKT_LEN - hdrlen) | |
742 | return hdrlen; | |
743 | return 0; | |
fd3a4790 DM |
744 | } |
745 | ||
746 | /** | |
747 | * calc_tx_flits - calculate the number of flits for a packet Tx WR | |
748 | * @skb: the packet | |
749 | * | |
750 | * Returns the number of flits needed for a Tx WR for the given Ethernet | |
751 | * packet, including the needed WR and CPL headers. | |
752 | */ | |
753 | static inline unsigned int calc_tx_flits(const struct sk_buff *skb) | |
754 | { | |
755 | unsigned int flits; | |
0034b298 | 756 | int hdrlen = is_eth_imm(skb); |
fd3a4790 | 757 | |
0034b298 KS |
758 | if (hdrlen) |
759 | return DIV_ROUND_UP(skb->len + hdrlen, sizeof(__be64)); | |
fd3a4790 DM |
760 | |
761 | flits = sgl_len(skb_shinfo(skb)->nr_frags + 1) + 4; | |
762 | if (skb_shinfo(skb)->gso_size) | |
763 | flits += 2; | |
764 | return flits; | |
765 | } | |
766 | ||
767 | /** | |
768 | * calc_tx_descs - calculate the number of Tx descriptors for a packet | |
769 | * @skb: the packet | |
770 | * | |
771 | * Returns the number of Tx descriptors needed for the given Ethernet | |
772 | * packet, including the needed WR and CPL headers. | |
773 | */ | |
774 | static inline unsigned int calc_tx_descs(const struct sk_buff *skb) | |
775 | { | |
776 | return flits_to_desc(calc_tx_flits(skb)); | |
777 | } | |
778 | ||
779 | /** | |
780 | * write_sgl - populate a scatter/gather list for a packet | |
781 | * @skb: the packet | |
782 | * @q: the Tx queue we are writing into | |
783 | * @sgl: starting location for writing the SGL | |
784 | * @end: points right after the end of the SGL | |
785 | * @start: start offset into skb main-body data to include in the SGL | |
786 | * @addr: the list of bus addresses for the SGL elements | |
787 | * | |
788 | * Generates a gather list for the buffers that make up a packet. | |
789 | * The caller must provide adequate space for the SGL that will be written. | |
790 | * The SGL includes all of the packet's page fragments and the data in its | |
791 | * main body except for the first @start bytes. @sgl must be 16-byte | |
792 | * aligned and within a Tx descriptor with available space. @end points | |
793 | * right after the end of the SGL but does not account for any potential | |
794 | * wrap around, i.e., @end > @sgl. | |
795 | */ | |
796 | static void write_sgl(const struct sk_buff *skb, struct sge_txq *q, | |
797 | struct ulptx_sgl *sgl, u64 *end, unsigned int start, | |
798 | const dma_addr_t *addr) | |
799 | { | |
800 | unsigned int i, len; | |
801 | struct ulptx_sge_pair *to; | |
802 | const struct skb_shared_info *si = skb_shinfo(skb); | |
803 | unsigned int nfrags = si->nr_frags; | |
804 | struct ulptx_sge_pair buf[MAX_SKB_FRAGS / 2 + 1]; | |
805 | ||
806 | len = skb_headlen(skb) - start; | |
807 | if (likely(len)) { | |
808 | sgl->len0 = htonl(len); | |
809 | sgl->addr0 = cpu_to_be64(addr[0] + start); | |
810 | nfrags++; | |
811 | } else { | |
9e903e08 | 812 | sgl->len0 = htonl(skb_frag_size(&si->frags[0])); |
fd3a4790 DM |
813 | sgl->addr0 = cpu_to_be64(addr[1]); |
814 | } | |
815 | ||
816 | sgl->cmd_nsge = htonl(ULPTX_CMD(ULP_TX_SC_DSGL) | ULPTX_NSGE(nfrags)); | |
817 | if (likely(--nfrags == 0)) | |
818 | return; | |
819 | /* | |
820 | * Most of the complexity below deals with the possibility we hit the | |
821 | * end of the queue in the middle of writing the SGL. For this case | |
822 | * only we create the SGL in a temporary buffer and then copy it. | |
823 | */ | |
824 | to = (u8 *)end > (u8 *)q->stat ? buf : sgl->sge; | |
825 | ||
826 | for (i = (nfrags != si->nr_frags); nfrags >= 2; nfrags -= 2, to++) { | |
9e903e08 ED |
827 | to->len[0] = cpu_to_be32(skb_frag_size(&si->frags[i])); |
828 | to->len[1] = cpu_to_be32(skb_frag_size(&si->frags[++i])); | |
fd3a4790 DM |
829 | to->addr[0] = cpu_to_be64(addr[i]); |
830 | to->addr[1] = cpu_to_be64(addr[++i]); | |
831 | } | |
832 | if (nfrags) { | |
9e903e08 | 833 | to->len[0] = cpu_to_be32(skb_frag_size(&si->frags[i])); |
fd3a4790 DM |
834 | to->len[1] = cpu_to_be32(0); |
835 | to->addr[0] = cpu_to_be64(addr[i + 1]); | |
836 | } | |
837 | if (unlikely((u8 *)end > (u8 *)q->stat)) { | |
838 | unsigned int part0 = (u8 *)q->stat - (u8 *)sgl->sge, part1; | |
839 | ||
840 | if (likely(part0)) | |
841 | memcpy(sgl->sge, buf, part0); | |
842 | part1 = (u8 *)end - (u8 *)q->stat; | |
843 | memcpy(q->desc, (u8 *)buf + part0, part1); | |
844 | end = (void *)q->desc + part1; | |
845 | } | |
846 | if ((uintptr_t)end & 8) /* 0-pad to multiple of 16 */ | |
64699336 | 847 | *end = 0; |
fd3a4790 DM |
848 | } |
849 | ||
22adfe0a SR |
850 | /* This function copies 64 byte coalesced work request to |
851 | * memory mapped BAR2 space(user space writes). | |
852 | * For coalesced WR SGE, fetches data from the FIFO instead of from Host. | |
853 | */ | |
854 | static void cxgb_pio_copy(u64 __iomem *dst, u64 *src) | |
855 | { | |
856 | int count = 8; | |
857 | ||
858 | while (count) { | |
859 | writeq(*src, dst); | |
860 | src++; | |
861 | dst++; | |
862 | count--; | |
863 | } | |
864 | } | |
865 | ||
fd3a4790 DM |
866 | /** |
867 | * ring_tx_db - check and potentially ring a Tx queue's doorbell | |
868 | * @adap: the adapter | |
869 | * @q: the Tx queue | |
870 | * @n: number of new descriptors to give to HW | |
871 | * | |
872 | * Ring the doorbel for a Tx queue. | |
873 | */ | |
874 | static inline void ring_tx_db(struct adapter *adap, struct sge_txq *q, int n) | |
875 | { | |
876 | wmb(); /* write descriptors before telling HW */ | |
d63a6dcf HS |
877 | |
878 | if (is_t4(adap->params.chip)) { | |
879 | u32 val = PIDX(n); | |
880 | unsigned long flags; | |
881 | ||
882 | /* For T4 we need to participate in the Doorbell Recovery | |
883 | * mechanism. | |
884 | */ | |
885 | spin_lock_irqsave(&q->db_lock, flags); | |
886 | if (!q->db_disabled) | |
22adfe0a | 887 | t4_write_reg(adap, MYPF_REG(SGE_PF_KDOORBELL), |
d63a6dcf HS |
888 | QID(q->cntxt_id) | val); |
889 | else | |
890 | q->db_pidx_inc += n; | |
891 | q->db_pidx = q->pidx; | |
892 | spin_unlock_irqrestore(&q->db_lock, flags); | |
893 | } else { | |
894 | u32 val = PIDX_T5(n); | |
895 | ||
896 | /* T4 and later chips share the same PIDX field offset within | |
897 | * the doorbell, but T5 and later shrank the field in order to | |
898 | * gain a bit for Doorbell Priority. The field was absurdly | |
899 | * large in the first place (14 bits) so we just use the T5 | |
900 | * and later limits and warn if a Queue ID is too large. | |
901 | */ | |
902 | WARN_ON(val & DBPRIO(1)); | |
903 | ||
904 | /* For T5 and later we use the Write-Combine mapped BAR2 User | |
905 | * Doorbell mechanism. If we're only writing a single TX | |
906 | * Descriptor and TX Write Combining hasn't been disabled, we | |
907 | * can use the Write Combining Gather Buffer; otherwise we use | |
908 | * the simple doorbell. | |
909 | */ | |
910 | if (n == 1) { | |
911 | int index = (q->pidx | |
912 | ? (q->pidx - 1) | |
913 | : (q->size - 1)); | |
914 | unsigned int *wr = (unsigned int *)&q->desc[index]; | |
915 | ||
916 | cxgb_pio_copy((u64 __iomem *) | |
917 | (adap->bar2 + q->udb + | |
918 | SGE_UDB_WCDOORBELL), | |
919 | (u64 *)wr); | |
22adfe0a | 920 | } else { |
d63a6dcf | 921 | writel(val, adap->bar2 + q->udb + SGE_UDB_KDOORBELL); |
22adfe0a | 922 | } |
d63a6dcf HS |
923 | |
924 | /* This Write Memory Barrier will force the write to the User | |
925 | * Doorbell area to be flushed. This is needed to prevent | |
926 | * writes on different CPUs for the same queue from hitting | |
927 | * the adapter out of order. This is required when some Work | |
928 | * Requests take the Write Combine Gather Buffer path (user | |
929 | * doorbell area offset [SGE_UDB_WCDOORBELL..+63]) and some | |
930 | * take the traditional path where we simply increment the | |
931 | * PIDX (User Doorbell area SGE_UDB_KDOORBELL) and have the | |
932 | * hardware DMA read the actual Work Request. | |
933 | */ | |
934 | wmb(); | |
935 | } | |
fd3a4790 DM |
936 | } |
937 | ||
938 | /** | |
939 | * inline_tx_skb - inline a packet's data into Tx descriptors | |
940 | * @skb: the packet | |
941 | * @q: the Tx queue where the packet will be inlined | |
942 | * @pos: starting position in the Tx queue where to inline the packet | |
943 | * | |
944 | * Inline a packet's contents directly into Tx descriptors, starting at | |
945 | * the given position within the Tx DMA ring. | |
946 | * Most of the complexity of this operation is dealing with wrap arounds | |
947 | * in the middle of the packet we want to inline. | |
948 | */ | |
949 | static void inline_tx_skb(const struct sk_buff *skb, const struct sge_txq *q, | |
950 | void *pos) | |
951 | { | |
952 | u64 *p; | |
953 | int left = (void *)q->stat - pos; | |
954 | ||
955 | if (likely(skb->len <= left)) { | |
956 | if (likely(!skb->data_len)) | |
957 | skb_copy_from_linear_data(skb, pos, skb->len); | |
958 | else | |
959 | skb_copy_bits(skb, 0, pos, skb->len); | |
960 | pos += skb->len; | |
961 | } else { | |
962 | skb_copy_bits(skb, 0, pos, left); | |
963 | skb_copy_bits(skb, left, q->desc, skb->len - left); | |
964 | pos = (void *)q->desc + (skb->len - left); | |
965 | } | |
966 | ||
967 | /* 0-pad to multiple of 16 */ | |
968 | p = PTR_ALIGN(pos, 8); | |
969 | if ((uintptr_t)p & 8) | |
970 | *p = 0; | |
971 | } | |
972 | ||
973 | /* | |
974 | * Figure out what HW csum a packet wants and return the appropriate control | |
975 | * bits. | |
976 | */ | |
977 | static u64 hwcsum(const struct sk_buff *skb) | |
978 | { | |
979 | int csum_type; | |
980 | const struct iphdr *iph = ip_hdr(skb); | |
981 | ||
982 | if (iph->version == 4) { | |
983 | if (iph->protocol == IPPROTO_TCP) | |
984 | csum_type = TX_CSUM_TCPIP; | |
985 | else if (iph->protocol == IPPROTO_UDP) | |
986 | csum_type = TX_CSUM_UDPIP; | |
987 | else { | |
988 | nocsum: /* | |
989 | * unknown protocol, disable HW csum | |
990 | * and hope a bad packet is detected | |
991 | */ | |
992 | return TXPKT_L4CSUM_DIS; | |
993 | } | |
994 | } else { | |
995 | /* | |
996 | * this doesn't work with extension headers | |
997 | */ | |
998 | const struct ipv6hdr *ip6h = (const struct ipv6hdr *)iph; | |
999 | ||
1000 | if (ip6h->nexthdr == IPPROTO_TCP) | |
1001 | csum_type = TX_CSUM_TCPIP6; | |
1002 | else if (ip6h->nexthdr == IPPROTO_UDP) | |
1003 | csum_type = TX_CSUM_UDPIP6; | |
1004 | else | |
1005 | goto nocsum; | |
1006 | } | |
1007 | ||
1008 | if (likely(csum_type >= TX_CSUM_TCPIP)) | |
1009 | return TXPKT_CSUM_TYPE(csum_type) | | |
1010 | TXPKT_IPHDR_LEN(skb_network_header_len(skb)) | | |
1011 | TXPKT_ETHHDR_LEN(skb_network_offset(skb) - ETH_HLEN); | |
1012 | else { | |
1013 | int start = skb_transport_offset(skb); | |
1014 | ||
1015 | return TXPKT_CSUM_TYPE(csum_type) | TXPKT_CSUM_START(start) | | |
1016 | TXPKT_CSUM_LOC(start + skb->csum_offset); | |
1017 | } | |
1018 | } | |
1019 | ||
1020 | static void eth_txq_stop(struct sge_eth_txq *q) | |
1021 | { | |
1022 | netif_tx_stop_queue(q->txq); | |
1023 | q->q.stops++; | |
1024 | } | |
1025 | ||
1026 | static inline void txq_advance(struct sge_txq *q, unsigned int n) | |
1027 | { | |
1028 | q->in_use += n; | |
1029 | q->pidx += n; | |
1030 | if (q->pidx >= q->size) | |
1031 | q->pidx -= q->size; | |
1032 | } | |
1033 | ||
1034 | /** | |
1035 | * t4_eth_xmit - add a packet to an Ethernet Tx queue | |
1036 | * @skb: the packet | |
1037 | * @dev: the egress net device | |
1038 | * | |
1039 | * Add a packet to an SGE Ethernet Tx queue. Runs with softirqs disabled. | |
1040 | */ | |
1041 | netdev_tx_t t4_eth_xmit(struct sk_buff *skb, struct net_device *dev) | |
1042 | { | |
0034b298 | 1043 | int len; |
fd3a4790 DM |
1044 | u32 wr_mid; |
1045 | u64 cntrl, *end; | |
1046 | int qidx, credits; | |
1047 | unsigned int flits, ndesc; | |
1048 | struct adapter *adap; | |
1049 | struct sge_eth_txq *q; | |
1050 | const struct port_info *pi; | |
1051 | struct fw_eth_tx_pkt_wr *wr; | |
1052 | struct cpl_tx_pkt_core *cpl; | |
1053 | const struct skb_shared_info *ssi; | |
1054 | dma_addr_t addr[MAX_SKB_FRAGS + 1]; | |
0034b298 | 1055 | bool immediate = false; |
fd3a4790 DM |
1056 | |
1057 | /* | |
1058 | * The chip min packet length is 10 octets but play safe and reject | |
1059 | * anything shorter than an Ethernet header. | |
1060 | */ | |
1061 | if (unlikely(skb->len < ETH_HLEN)) { | |
a7525198 | 1062 | out_free: dev_kfree_skb_any(skb); |
fd3a4790 DM |
1063 | return NETDEV_TX_OK; |
1064 | } | |
1065 | ||
1066 | pi = netdev_priv(dev); | |
1067 | adap = pi->adapter; | |
1068 | qidx = skb_get_queue_mapping(skb); | |
1069 | q = &adap->sge.ethtxq[qidx + pi->first_qset]; | |
1070 | ||
1071 | reclaim_completed_tx(adap, &q->q, true); | |
1072 | ||
1073 | flits = calc_tx_flits(skb); | |
1074 | ndesc = flits_to_desc(flits); | |
1075 | credits = txq_avail(&q->q) - ndesc; | |
1076 | ||
1077 | if (unlikely(credits < 0)) { | |
1078 | eth_txq_stop(q); | |
1079 | dev_err(adap->pdev_dev, | |
1080 | "%s: Tx ring %u full while queue awake!\n", | |
1081 | dev->name, qidx); | |
1082 | return NETDEV_TX_BUSY; | |
1083 | } | |
1084 | ||
0034b298 KS |
1085 | if (is_eth_imm(skb)) |
1086 | immediate = true; | |
1087 | ||
1088 | if (!immediate && | |
fd3a4790 DM |
1089 | unlikely(map_skb(adap->pdev_dev, skb, addr) < 0)) { |
1090 | q->mapping_err++; | |
1091 | goto out_free; | |
1092 | } | |
1093 | ||
1094 | wr_mid = FW_WR_LEN16(DIV_ROUND_UP(flits, 2)); | |
1095 | if (unlikely(credits < ETHTXQ_STOP_THRES)) { | |
1096 | eth_txq_stop(q); | |
1097 | wr_mid |= FW_WR_EQUEQ | FW_WR_EQUIQ; | |
1098 | } | |
1099 | ||
1100 | wr = (void *)&q->q.desc[q->q.pidx]; | |
1101 | wr->equiq_to_len16 = htonl(wr_mid); | |
1102 | wr->r3 = cpu_to_be64(0); | |
1103 | end = (u64 *)wr + flits; | |
1104 | ||
0034b298 | 1105 | len = immediate ? skb->len : 0; |
fd3a4790 DM |
1106 | ssi = skb_shinfo(skb); |
1107 | if (ssi->gso_size) { | |
625ac6ae | 1108 | struct cpl_tx_pkt_lso *lso = (void *)wr; |
fd3a4790 DM |
1109 | bool v6 = (ssi->gso_type & SKB_GSO_TCPV6) != 0; |
1110 | int l3hdr_len = skb_network_header_len(skb); | |
1111 | int eth_xtra_len = skb_network_offset(skb) - ETH_HLEN; | |
1112 | ||
0034b298 | 1113 | len += sizeof(*lso); |
fd3a4790 | 1114 | wr->op_immdlen = htonl(FW_WR_OP(FW_ETH_TX_PKT_WR) | |
0034b298 | 1115 | FW_WR_IMMDLEN(len)); |
625ac6ae DM |
1116 | lso->c.lso_ctrl = htonl(LSO_OPCODE(CPL_TX_PKT_LSO) | |
1117 | LSO_FIRST_SLICE | LSO_LAST_SLICE | | |
1118 | LSO_IPV6(v6) | | |
1119 | LSO_ETHHDR_LEN(eth_xtra_len / 4) | | |
1120 | LSO_IPHDR_LEN(l3hdr_len / 4) | | |
1121 | LSO_TCPHDR_LEN(tcp_hdr(skb)->doff)); | |
1122 | lso->c.ipid_ofst = htons(0); | |
1123 | lso->c.mss = htons(ssi->gso_size); | |
1124 | lso->c.seqno_offset = htonl(0); | |
1125 | lso->c.len = htonl(skb->len); | |
fd3a4790 DM |
1126 | cpl = (void *)(lso + 1); |
1127 | cntrl = TXPKT_CSUM_TYPE(v6 ? TX_CSUM_TCPIP6 : TX_CSUM_TCPIP) | | |
1128 | TXPKT_IPHDR_LEN(l3hdr_len) | | |
1129 | TXPKT_ETHHDR_LEN(eth_xtra_len); | |
1130 | q->tso++; | |
1131 | q->tx_cso += ssi->gso_segs; | |
1132 | } else { | |
ca71de6b | 1133 | len += sizeof(*cpl); |
fd3a4790 DM |
1134 | wr->op_immdlen = htonl(FW_WR_OP(FW_ETH_TX_PKT_WR) | |
1135 | FW_WR_IMMDLEN(len)); | |
1136 | cpl = (void *)(wr + 1); | |
1137 | if (skb->ip_summed == CHECKSUM_PARTIAL) { | |
1138 | cntrl = hwcsum(skb) | TXPKT_IPCSUM_DIS; | |
1139 | q->tx_cso++; | |
1140 | } else | |
1141 | cntrl = TXPKT_L4CSUM_DIS | TXPKT_IPCSUM_DIS; | |
1142 | } | |
1143 | ||
1144 | if (vlan_tx_tag_present(skb)) { | |
1145 | q->vlan_ins++; | |
1146 | cntrl |= TXPKT_VLAN_VLD | TXPKT_VLAN(vlan_tx_tag_get(skb)); | |
1147 | } | |
1148 | ||
1149 | cpl->ctrl0 = htonl(TXPKT_OPCODE(CPL_TX_PKT_XT) | | |
1707aec9 | 1150 | TXPKT_INTF(pi->tx_chan) | TXPKT_PF(adap->fn)); |
fd3a4790 DM |
1151 | cpl->pack = htons(0); |
1152 | cpl->len = htons(skb->len); | |
1153 | cpl->ctrl1 = cpu_to_be64(cntrl); | |
1154 | ||
0034b298 | 1155 | if (immediate) { |
fd3a4790 | 1156 | inline_tx_skb(skb, &q->q, cpl + 1); |
a7525198 | 1157 | dev_consume_skb_any(skb); |
fd3a4790 DM |
1158 | } else { |
1159 | int last_desc; | |
1160 | ||
1161 | write_sgl(skb, &q->q, (struct ulptx_sgl *)(cpl + 1), end, 0, | |
1162 | addr); | |
1163 | skb_orphan(skb); | |
1164 | ||
1165 | last_desc = q->q.pidx + ndesc - 1; | |
1166 | if (last_desc >= q->q.size) | |
1167 | last_desc -= q->q.size; | |
1168 | q->q.sdesc[last_desc].skb = skb; | |
1169 | q->q.sdesc[last_desc].sgl = (struct ulptx_sgl *)(cpl + 1); | |
1170 | } | |
1171 | ||
1172 | txq_advance(&q->q, ndesc); | |
1173 | ||
1174 | ring_tx_db(adap, &q->q, ndesc); | |
1175 | return NETDEV_TX_OK; | |
1176 | } | |
1177 | ||
1178 | /** | |
1179 | * reclaim_completed_tx_imm - reclaim completed control-queue Tx descs | |
1180 | * @q: the SGE control Tx queue | |
1181 | * | |
1182 | * This is a variant of reclaim_completed_tx() that is used for Tx queues | |
1183 | * that send only immediate data (presently just the control queues) and | |
1184 | * thus do not have any sk_buffs to release. | |
1185 | */ | |
1186 | static inline void reclaim_completed_tx_imm(struct sge_txq *q) | |
1187 | { | |
1188 | int hw_cidx = ntohs(q->stat->cidx); | |
1189 | int reclaim = hw_cidx - q->cidx; | |
1190 | ||
1191 | if (reclaim < 0) | |
1192 | reclaim += q->size; | |
1193 | ||
1194 | q->in_use -= reclaim; | |
1195 | q->cidx = hw_cidx; | |
1196 | } | |
1197 | ||
1198 | /** | |
1199 | * is_imm - check whether a packet can be sent as immediate data | |
1200 | * @skb: the packet | |
1201 | * | |
1202 | * Returns true if a packet can be sent as a WR with immediate data. | |
1203 | */ | |
1204 | static inline int is_imm(const struct sk_buff *skb) | |
1205 | { | |
1206 | return skb->len <= MAX_CTRL_WR_LEN; | |
1207 | } | |
1208 | ||
1209 | /** | |
1210 | * ctrlq_check_stop - check if a control queue is full and should stop | |
1211 | * @q: the queue | |
1212 | * @wr: most recent WR written to the queue | |
1213 | * | |
1214 | * Check if a control queue has become full and should be stopped. | |
1215 | * We clean up control queue descriptors very lazily, only when we are out. | |
1216 | * If the queue is still full after reclaiming any completed descriptors | |
1217 | * we suspend it and have the last WR wake it up. | |
1218 | */ | |
1219 | static void ctrlq_check_stop(struct sge_ctrl_txq *q, struct fw_wr_hdr *wr) | |
1220 | { | |
1221 | reclaim_completed_tx_imm(&q->q); | |
1222 | if (unlikely(txq_avail(&q->q) < TXQ_STOP_THRES)) { | |
1223 | wr->lo |= htonl(FW_WR_EQUEQ | FW_WR_EQUIQ); | |
1224 | q->q.stops++; | |
1225 | q->full = 1; | |
1226 | } | |
1227 | } | |
1228 | ||
1229 | /** | |
1230 | * ctrl_xmit - send a packet through an SGE control Tx queue | |
1231 | * @q: the control queue | |
1232 | * @skb: the packet | |
1233 | * | |
1234 | * Send a packet through an SGE control Tx queue. Packets sent through | |
1235 | * a control queue must fit entirely as immediate data. | |
1236 | */ | |
1237 | static int ctrl_xmit(struct sge_ctrl_txq *q, struct sk_buff *skb) | |
1238 | { | |
1239 | unsigned int ndesc; | |
1240 | struct fw_wr_hdr *wr; | |
1241 | ||
1242 | if (unlikely(!is_imm(skb))) { | |
1243 | WARN_ON(1); | |
1244 | dev_kfree_skb(skb); | |
1245 | return NET_XMIT_DROP; | |
1246 | } | |
1247 | ||
1248 | ndesc = DIV_ROUND_UP(skb->len, sizeof(struct tx_desc)); | |
1249 | spin_lock(&q->sendq.lock); | |
1250 | ||
1251 | if (unlikely(q->full)) { | |
1252 | skb->priority = ndesc; /* save for restart */ | |
1253 | __skb_queue_tail(&q->sendq, skb); | |
1254 | spin_unlock(&q->sendq.lock); | |
1255 | return NET_XMIT_CN; | |
1256 | } | |
1257 | ||
1258 | wr = (struct fw_wr_hdr *)&q->q.desc[q->q.pidx]; | |
1259 | inline_tx_skb(skb, &q->q, wr); | |
1260 | ||
1261 | txq_advance(&q->q, ndesc); | |
1262 | if (unlikely(txq_avail(&q->q) < TXQ_STOP_THRES)) | |
1263 | ctrlq_check_stop(q, wr); | |
1264 | ||
1265 | ring_tx_db(q->adap, &q->q, ndesc); | |
1266 | spin_unlock(&q->sendq.lock); | |
1267 | ||
1268 | kfree_skb(skb); | |
1269 | return NET_XMIT_SUCCESS; | |
1270 | } | |
1271 | ||
1272 | /** | |
1273 | * restart_ctrlq - restart a suspended control queue | |
1274 | * @data: the control queue to restart | |
1275 | * | |
1276 | * Resumes transmission on a suspended Tx control queue. | |
1277 | */ | |
1278 | static void restart_ctrlq(unsigned long data) | |
1279 | { | |
1280 | struct sk_buff *skb; | |
1281 | unsigned int written = 0; | |
1282 | struct sge_ctrl_txq *q = (struct sge_ctrl_txq *)data; | |
1283 | ||
1284 | spin_lock(&q->sendq.lock); | |
1285 | reclaim_completed_tx_imm(&q->q); | |
1286 | BUG_ON(txq_avail(&q->q) < TXQ_STOP_THRES); /* q should be empty */ | |
1287 | ||
1288 | while ((skb = __skb_dequeue(&q->sendq)) != NULL) { | |
1289 | struct fw_wr_hdr *wr; | |
1290 | unsigned int ndesc = skb->priority; /* previously saved */ | |
1291 | ||
1292 | /* | |
1293 | * Write descriptors and free skbs outside the lock to limit | |
1294 | * wait times. q->full is still set so new skbs will be queued. | |
1295 | */ | |
1296 | spin_unlock(&q->sendq.lock); | |
1297 | ||
1298 | wr = (struct fw_wr_hdr *)&q->q.desc[q->q.pidx]; | |
1299 | inline_tx_skb(skb, &q->q, wr); | |
1300 | kfree_skb(skb); | |
1301 | ||
1302 | written += ndesc; | |
1303 | txq_advance(&q->q, ndesc); | |
1304 | if (unlikely(txq_avail(&q->q) < TXQ_STOP_THRES)) { | |
1305 | unsigned long old = q->q.stops; | |
1306 | ||
1307 | ctrlq_check_stop(q, wr); | |
1308 | if (q->q.stops != old) { /* suspended anew */ | |
1309 | spin_lock(&q->sendq.lock); | |
1310 | goto ringdb; | |
1311 | } | |
1312 | } | |
1313 | if (written > 16) { | |
1314 | ring_tx_db(q->adap, &q->q, written); | |
1315 | written = 0; | |
1316 | } | |
1317 | spin_lock(&q->sendq.lock); | |
1318 | } | |
1319 | q->full = 0; | |
1320 | ringdb: if (written) | |
1321 | ring_tx_db(q->adap, &q->q, written); | |
1322 | spin_unlock(&q->sendq.lock); | |
1323 | } | |
1324 | ||
1325 | /** | |
1326 | * t4_mgmt_tx - send a management message | |
1327 | * @adap: the adapter | |
1328 | * @skb: the packet containing the management message | |
1329 | * | |
1330 | * Send a management message through control queue 0. | |
1331 | */ | |
1332 | int t4_mgmt_tx(struct adapter *adap, struct sk_buff *skb) | |
1333 | { | |
1334 | int ret; | |
1335 | ||
1336 | local_bh_disable(); | |
1337 | ret = ctrl_xmit(&adap->sge.ctrlq[0], skb); | |
1338 | local_bh_enable(); | |
1339 | return ret; | |
1340 | } | |
1341 | ||
1342 | /** | |
1343 | * is_ofld_imm - check whether a packet can be sent as immediate data | |
1344 | * @skb: the packet | |
1345 | * | |
1346 | * Returns true if a packet can be sent as an offload WR with immediate | |
1347 | * data. We currently use the same limit as for Ethernet packets. | |
1348 | */ | |
1349 | static inline int is_ofld_imm(const struct sk_buff *skb) | |
1350 | { | |
1351 | return skb->len <= MAX_IMM_TX_PKT_LEN; | |
1352 | } | |
1353 | ||
1354 | /** | |
1355 | * calc_tx_flits_ofld - calculate # of flits for an offload packet | |
1356 | * @skb: the packet | |
1357 | * | |
1358 | * Returns the number of flits needed for the given offload packet. | |
1359 | * These packets are already fully constructed and no additional headers | |
1360 | * will be added. | |
1361 | */ | |
1362 | static inline unsigned int calc_tx_flits_ofld(const struct sk_buff *skb) | |
1363 | { | |
1364 | unsigned int flits, cnt; | |
1365 | ||
1366 | if (is_ofld_imm(skb)) | |
1367 | return DIV_ROUND_UP(skb->len, 8); | |
1368 | ||
1369 | flits = skb_transport_offset(skb) / 8U; /* headers */ | |
1370 | cnt = skb_shinfo(skb)->nr_frags; | |
15dd16c2 | 1371 | if (skb_tail_pointer(skb) != skb_transport_header(skb)) |
fd3a4790 DM |
1372 | cnt++; |
1373 | return flits + sgl_len(cnt); | |
1374 | } | |
1375 | ||
1376 | /** | |
1377 | * txq_stop_maperr - stop a Tx queue due to I/O MMU exhaustion | |
1378 | * @adap: the adapter | |
1379 | * @q: the queue to stop | |
1380 | * | |
1381 | * Mark a Tx queue stopped due to I/O MMU exhaustion and resulting | |
1382 | * inability to map packets. A periodic timer attempts to restart | |
1383 | * queues so marked. | |
1384 | */ | |
1385 | static void txq_stop_maperr(struct sge_ofld_txq *q) | |
1386 | { | |
1387 | q->mapping_err++; | |
1388 | q->q.stops++; | |
e46dab4d DM |
1389 | set_bit(q->q.cntxt_id - q->adap->sge.egr_start, |
1390 | q->adap->sge.txq_maperr); | |
fd3a4790 DM |
1391 | } |
1392 | ||
1393 | /** | |
1394 | * ofldtxq_stop - stop an offload Tx queue that has become full | |
1395 | * @q: the queue to stop | |
1396 | * @skb: the packet causing the queue to become full | |
1397 | * | |
1398 | * Stops an offload Tx queue that has become full and modifies the packet | |
1399 | * being written to request a wakeup. | |
1400 | */ | |
1401 | static void ofldtxq_stop(struct sge_ofld_txq *q, struct sk_buff *skb) | |
1402 | { | |
1403 | struct fw_wr_hdr *wr = (struct fw_wr_hdr *)skb->data; | |
1404 | ||
1405 | wr->lo |= htonl(FW_WR_EQUEQ | FW_WR_EQUIQ); | |
1406 | q->q.stops++; | |
1407 | q->full = 1; | |
1408 | } | |
1409 | ||
1410 | /** | |
1411 | * service_ofldq - restart a suspended offload queue | |
1412 | * @q: the offload queue | |
1413 | * | |
1414 | * Services an offload Tx queue by moving packets from its packet queue | |
1415 | * to the HW Tx ring. The function starts and ends with the queue locked. | |
1416 | */ | |
1417 | static void service_ofldq(struct sge_ofld_txq *q) | |
1418 | { | |
1419 | u64 *pos; | |
1420 | int credits; | |
1421 | struct sk_buff *skb; | |
1422 | unsigned int written = 0; | |
1423 | unsigned int flits, ndesc; | |
1424 | ||
1425 | while ((skb = skb_peek(&q->sendq)) != NULL && !q->full) { | |
1426 | /* | |
1427 | * We drop the lock but leave skb on sendq, thus retaining | |
1428 | * exclusive access to the state of the queue. | |
1429 | */ | |
1430 | spin_unlock(&q->sendq.lock); | |
1431 | ||
1432 | reclaim_completed_tx(q->adap, &q->q, false); | |
1433 | ||
1434 | flits = skb->priority; /* previously saved */ | |
1435 | ndesc = flits_to_desc(flits); | |
1436 | credits = txq_avail(&q->q) - ndesc; | |
1437 | BUG_ON(credits < 0); | |
1438 | if (unlikely(credits < TXQ_STOP_THRES)) | |
1439 | ofldtxq_stop(q, skb); | |
1440 | ||
1441 | pos = (u64 *)&q->q.desc[q->q.pidx]; | |
1442 | if (is_ofld_imm(skb)) | |
1443 | inline_tx_skb(skb, &q->q, pos); | |
1444 | else if (map_skb(q->adap->pdev_dev, skb, | |
1445 | (dma_addr_t *)skb->head)) { | |
1446 | txq_stop_maperr(q); | |
1447 | spin_lock(&q->sendq.lock); | |
1448 | break; | |
1449 | } else { | |
1450 | int last_desc, hdr_len = skb_transport_offset(skb); | |
1451 | ||
1452 | memcpy(pos, skb->data, hdr_len); | |
1453 | write_sgl(skb, &q->q, (void *)pos + hdr_len, | |
1454 | pos + flits, hdr_len, | |
1455 | (dma_addr_t *)skb->head); | |
1456 | #ifdef CONFIG_NEED_DMA_MAP_STATE | |
1457 | skb->dev = q->adap->port[0]; | |
1458 | skb->destructor = deferred_unmap_destructor; | |
1459 | #endif | |
1460 | last_desc = q->q.pidx + ndesc - 1; | |
1461 | if (last_desc >= q->q.size) | |
1462 | last_desc -= q->q.size; | |
1463 | q->q.sdesc[last_desc].skb = skb; | |
1464 | } | |
1465 | ||
1466 | txq_advance(&q->q, ndesc); | |
1467 | written += ndesc; | |
1468 | if (unlikely(written > 32)) { | |
1469 | ring_tx_db(q->adap, &q->q, written); | |
1470 | written = 0; | |
1471 | } | |
1472 | ||
1473 | spin_lock(&q->sendq.lock); | |
1474 | __skb_unlink(skb, &q->sendq); | |
1475 | if (is_ofld_imm(skb)) | |
1476 | kfree_skb(skb); | |
1477 | } | |
1478 | if (likely(written)) | |
1479 | ring_tx_db(q->adap, &q->q, written); | |
1480 | } | |
1481 | ||
1482 | /** | |
1483 | * ofld_xmit - send a packet through an offload queue | |
1484 | * @q: the Tx offload queue | |
1485 | * @skb: the packet | |
1486 | * | |
1487 | * Send an offload packet through an SGE offload queue. | |
1488 | */ | |
1489 | static int ofld_xmit(struct sge_ofld_txq *q, struct sk_buff *skb) | |
1490 | { | |
1491 | skb->priority = calc_tx_flits_ofld(skb); /* save for restart */ | |
1492 | spin_lock(&q->sendq.lock); | |
1493 | __skb_queue_tail(&q->sendq, skb); | |
1494 | if (q->sendq.qlen == 1) | |
1495 | service_ofldq(q); | |
1496 | spin_unlock(&q->sendq.lock); | |
1497 | return NET_XMIT_SUCCESS; | |
1498 | } | |
1499 | ||
1500 | /** | |
1501 | * restart_ofldq - restart a suspended offload queue | |
1502 | * @data: the offload queue to restart | |
1503 | * | |
1504 | * Resumes transmission on a suspended Tx offload queue. | |
1505 | */ | |
1506 | static void restart_ofldq(unsigned long data) | |
1507 | { | |
1508 | struct sge_ofld_txq *q = (struct sge_ofld_txq *)data; | |
1509 | ||
1510 | spin_lock(&q->sendq.lock); | |
1511 | q->full = 0; /* the queue actually is completely empty now */ | |
1512 | service_ofldq(q); | |
1513 | spin_unlock(&q->sendq.lock); | |
1514 | } | |
1515 | ||
1516 | /** | |
1517 | * skb_txq - return the Tx queue an offload packet should use | |
1518 | * @skb: the packet | |
1519 | * | |
1520 | * Returns the Tx queue an offload packet should use as indicated by bits | |
1521 | * 1-15 in the packet's queue_mapping. | |
1522 | */ | |
1523 | static inline unsigned int skb_txq(const struct sk_buff *skb) | |
1524 | { | |
1525 | return skb->queue_mapping >> 1; | |
1526 | } | |
1527 | ||
1528 | /** | |
1529 | * is_ctrl_pkt - return whether an offload packet is a control packet | |
1530 | * @skb: the packet | |
1531 | * | |
1532 | * Returns whether an offload packet should use an OFLD or a CTRL | |
1533 | * Tx queue as indicated by bit 0 in the packet's queue_mapping. | |
1534 | */ | |
1535 | static inline unsigned int is_ctrl_pkt(const struct sk_buff *skb) | |
1536 | { | |
1537 | return skb->queue_mapping & 1; | |
1538 | } | |
1539 | ||
1540 | static inline int ofld_send(struct adapter *adap, struct sk_buff *skb) | |
1541 | { | |
1542 | unsigned int idx = skb_txq(skb); | |
1543 | ||
4fe44dd7 KS |
1544 | if (unlikely(is_ctrl_pkt(skb))) { |
1545 | /* Single ctrl queue is a requirement for LE workaround path */ | |
1546 | if (adap->tids.nsftids) | |
1547 | idx = 0; | |
fd3a4790 | 1548 | return ctrl_xmit(&adap->sge.ctrlq[idx], skb); |
4fe44dd7 | 1549 | } |
fd3a4790 DM |
1550 | return ofld_xmit(&adap->sge.ofldtxq[idx], skb); |
1551 | } | |
1552 | ||
1553 | /** | |
1554 | * t4_ofld_send - send an offload packet | |
1555 | * @adap: the adapter | |
1556 | * @skb: the packet | |
1557 | * | |
1558 | * Sends an offload packet. We use the packet queue_mapping to select the | |
1559 | * appropriate Tx queue as follows: bit 0 indicates whether the packet | |
1560 | * should be sent as regular or control, bits 1-15 select the queue. | |
1561 | */ | |
1562 | int t4_ofld_send(struct adapter *adap, struct sk_buff *skb) | |
1563 | { | |
1564 | int ret; | |
1565 | ||
1566 | local_bh_disable(); | |
1567 | ret = ofld_send(adap, skb); | |
1568 | local_bh_enable(); | |
1569 | return ret; | |
1570 | } | |
1571 | ||
1572 | /** | |
1573 | * cxgb4_ofld_send - send an offload packet | |
1574 | * @dev: the net device | |
1575 | * @skb: the packet | |
1576 | * | |
1577 | * Sends an offload packet. This is an exported version of @t4_ofld_send, | |
1578 | * intended for ULDs. | |
1579 | */ | |
1580 | int cxgb4_ofld_send(struct net_device *dev, struct sk_buff *skb) | |
1581 | { | |
1582 | return t4_ofld_send(netdev2adap(dev), skb); | |
1583 | } | |
1584 | EXPORT_SYMBOL(cxgb4_ofld_send); | |
1585 | ||
e91b0f24 | 1586 | static inline void copy_frags(struct sk_buff *skb, |
fd3a4790 DM |
1587 | const struct pkt_gl *gl, unsigned int offset) |
1588 | { | |
e91b0f24 | 1589 | int i; |
fd3a4790 DM |
1590 | |
1591 | /* usually there's just one frag */ | |
e91b0f24 IC |
1592 | __skb_fill_page_desc(skb, 0, gl->frags[0].page, |
1593 | gl->frags[0].offset + offset, | |
1594 | gl->frags[0].size - offset); | |
1595 | skb_shinfo(skb)->nr_frags = gl->nfrags; | |
1596 | for (i = 1; i < gl->nfrags; i++) | |
1597 | __skb_fill_page_desc(skb, i, gl->frags[i].page, | |
1598 | gl->frags[i].offset, | |
1599 | gl->frags[i].size); | |
fd3a4790 DM |
1600 | |
1601 | /* get a reference to the last page, we don't own it */ | |
e91b0f24 | 1602 | get_page(gl->frags[gl->nfrags - 1].page); |
fd3a4790 DM |
1603 | } |
1604 | ||
1605 | /** | |
1606 | * cxgb4_pktgl_to_skb - build an sk_buff from a packet gather list | |
1607 | * @gl: the gather list | |
1608 | * @skb_len: size of sk_buff main body if it carries fragments | |
1609 | * @pull_len: amount of data to move to the sk_buff's main body | |
1610 | * | |
1611 | * Builds an sk_buff from the given packet gather list. Returns the | |
1612 | * sk_buff or %NULL if sk_buff allocation failed. | |
1613 | */ | |
1614 | struct sk_buff *cxgb4_pktgl_to_skb(const struct pkt_gl *gl, | |
1615 | unsigned int skb_len, unsigned int pull_len) | |
1616 | { | |
1617 | struct sk_buff *skb; | |
1618 | ||
1619 | /* | |
1620 | * Below we rely on RX_COPY_THRES being less than the smallest Rx buffer | |
1621 | * size, which is expected since buffers are at least PAGE_SIZEd. | |
1622 | * In this case packets up to RX_COPY_THRES have only one fragment. | |
1623 | */ | |
1624 | if (gl->tot_len <= RX_COPY_THRES) { | |
1625 | skb = dev_alloc_skb(gl->tot_len); | |
1626 | if (unlikely(!skb)) | |
1627 | goto out; | |
1628 | __skb_put(skb, gl->tot_len); | |
1629 | skb_copy_to_linear_data(skb, gl->va, gl->tot_len); | |
1630 | } else { | |
1631 | skb = dev_alloc_skb(skb_len); | |
1632 | if (unlikely(!skb)) | |
1633 | goto out; | |
1634 | __skb_put(skb, pull_len); | |
1635 | skb_copy_to_linear_data(skb, gl->va, pull_len); | |
1636 | ||
e91b0f24 | 1637 | copy_frags(skb, gl, pull_len); |
fd3a4790 DM |
1638 | skb->len = gl->tot_len; |
1639 | skb->data_len = skb->len - pull_len; | |
1640 | skb->truesize += skb->data_len; | |
1641 | } | |
1642 | out: return skb; | |
1643 | } | |
1644 | EXPORT_SYMBOL(cxgb4_pktgl_to_skb); | |
1645 | ||
1646 | /** | |
1647 | * t4_pktgl_free - free a packet gather list | |
1648 | * @gl: the gather list | |
1649 | * | |
1650 | * Releases the pages of a packet gather list. We do not own the last | |
1651 | * page on the list and do not free it. | |
1652 | */ | |
de498c89 | 1653 | static void t4_pktgl_free(const struct pkt_gl *gl) |
fd3a4790 DM |
1654 | { |
1655 | int n; | |
e91b0f24 | 1656 | const struct page_frag *p; |
fd3a4790 DM |
1657 | |
1658 | for (p = gl->frags, n = gl->nfrags - 1; n--; p++) | |
1659 | put_page(p->page); | |
1660 | } | |
1661 | ||
1662 | /* | |
1663 | * Process an MPS trace packet. Give it an unused protocol number so it won't | |
1664 | * be delivered to anyone and send it to the stack for capture. | |
1665 | */ | |
1666 | static noinline int handle_trace_pkt(struct adapter *adap, | |
1667 | const struct pkt_gl *gl) | |
1668 | { | |
1669 | struct sk_buff *skb; | |
fd3a4790 DM |
1670 | |
1671 | skb = cxgb4_pktgl_to_skb(gl, RX_PULL_LEN, RX_PULL_LEN); | |
1672 | if (unlikely(!skb)) { | |
1673 | t4_pktgl_free(gl); | |
1674 | return 0; | |
1675 | } | |
1676 | ||
d14807dd | 1677 | if (is_t4(adap->params.chip)) |
0a57a536 SR |
1678 | __skb_pull(skb, sizeof(struct cpl_trace_pkt)); |
1679 | else | |
1680 | __skb_pull(skb, sizeof(struct cpl_t5_trace_pkt)); | |
1681 | ||
fd3a4790 DM |
1682 | skb_reset_mac_header(skb); |
1683 | skb->protocol = htons(0xffff); | |
1684 | skb->dev = adap->port[0]; | |
1685 | netif_receive_skb(skb); | |
1686 | return 0; | |
1687 | } | |
1688 | ||
1689 | static void do_gro(struct sge_eth_rxq *rxq, const struct pkt_gl *gl, | |
1690 | const struct cpl_rx_pkt *pkt) | |
1691 | { | |
52367a76 VP |
1692 | struct adapter *adapter = rxq->rspq.adap; |
1693 | struct sge *s = &adapter->sge; | |
fd3a4790 DM |
1694 | int ret; |
1695 | struct sk_buff *skb; | |
1696 | ||
1697 | skb = napi_get_frags(&rxq->rspq.napi); | |
1698 | if (unlikely(!skb)) { | |
1699 | t4_pktgl_free(gl); | |
1700 | rxq->stats.rx_drops++; | |
1701 | return; | |
1702 | } | |
1703 | ||
52367a76 VP |
1704 | copy_frags(skb, gl, s->pktshift); |
1705 | skb->len = gl->tot_len - s->pktshift; | |
fd3a4790 DM |
1706 | skb->data_len = skb->len; |
1707 | skb->truesize += skb->data_len; | |
1708 | skb->ip_summed = CHECKSUM_UNNECESSARY; | |
1709 | skb_record_rx_queue(skb, rxq->rspq.idx); | |
87b6cf51 | 1710 | if (rxq->rspq.netdev->features & NETIF_F_RXHASH) |
8264989c TH |
1711 | skb_set_hash(skb, (__force u32)pkt->rsshdr.hash_val, |
1712 | PKT_HASH_TYPE_L3); | |
fd3a4790 DM |
1713 | |
1714 | if (unlikely(pkt->vlan_ex)) { | |
86a9bad3 | 1715 | __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), ntohs(pkt->vlan)); |
fd3a4790 | 1716 | rxq->stats.vlan_ex++; |
fd3a4790 DM |
1717 | } |
1718 | ret = napi_gro_frags(&rxq->rspq.napi); | |
19ecae2c | 1719 | if (ret == GRO_HELD) |
fd3a4790 DM |
1720 | rxq->stats.lro_pkts++; |
1721 | else if (ret == GRO_MERGED || ret == GRO_MERGED_FREE) | |
1722 | rxq->stats.lro_merged++; | |
1723 | rxq->stats.pkts++; | |
1724 | rxq->stats.rx_cso++; | |
1725 | } | |
1726 | ||
1727 | /** | |
1728 | * t4_ethrx_handler - process an ingress ethernet packet | |
1729 | * @q: the response queue that received the packet | |
1730 | * @rsp: the response queue descriptor holding the RX_PKT message | |
1731 | * @si: the gather list of packet fragments | |
1732 | * | |
1733 | * Process an ingress ethernet packet and deliver it to the stack. | |
1734 | */ | |
1735 | int t4_ethrx_handler(struct sge_rspq *q, const __be64 *rsp, | |
1736 | const struct pkt_gl *si) | |
1737 | { | |
1738 | bool csum_ok; | |
1739 | struct sk_buff *skb; | |
fd3a4790 DM |
1740 | const struct cpl_rx_pkt *pkt; |
1741 | struct sge_eth_rxq *rxq = container_of(q, struct sge_eth_rxq, rspq); | |
52367a76 | 1742 | struct sge *s = &q->adap->sge; |
d14807dd | 1743 | int cpl_trace_pkt = is_t4(q->adap->params.chip) ? |
0a57a536 | 1744 | CPL_TRACE_PKT : CPL_TRACE_PKT_T5; |
fd3a4790 | 1745 | |
0a57a536 | 1746 | if (unlikely(*(u8 *)rsp == cpl_trace_pkt)) |
fd3a4790 DM |
1747 | return handle_trace_pkt(q->adap, si); |
1748 | ||
87b6cf51 | 1749 | pkt = (const struct cpl_rx_pkt *)rsp; |
cca2822d HS |
1750 | csum_ok = pkt->csum_calc && !pkt->err_vec && |
1751 | (q->netdev->features & NETIF_F_RXCSUM); | |
fd3a4790 DM |
1752 | if ((pkt->l2info & htonl(RXF_TCP)) && |
1753 | (q->netdev->features & NETIF_F_GRO) && csum_ok && !pkt->ip_frag) { | |
1754 | do_gro(rxq, si, pkt); | |
1755 | return 0; | |
1756 | } | |
1757 | ||
1758 | skb = cxgb4_pktgl_to_skb(si, RX_PKT_SKB_LEN, RX_PULL_LEN); | |
1759 | if (unlikely(!skb)) { | |
1760 | t4_pktgl_free(si); | |
1761 | rxq->stats.rx_drops++; | |
1762 | return 0; | |
1763 | } | |
1764 | ||
52367a76 | 1765 | __skb_pull(skb, s->pktshift); /* remove ethernet header padding */ |
fd3a4790 DM |
1766 | skb->protocol = eth_type_trans(skb, q->netdev); |
1767 | skb_record_rx_queue(skb, q->idx); | |
87b6cf51 | 1768 | if (skb->dev->features & NETIF_F_RXHASH) |
8264989c TH |
1769 | skb_set_hash(skb, (__force u32)pkt->rsshdr.hash_val, |
1770 | PKT_HASH_TYPE_L3); | |
87b6cf51 | 1771 | |
fd3a4790 DM |
1772 | rxq->stats.pkts++; |
1773 | ||
cca2822d | 1774 | if (csum_ok && (pkt->l2info & htonl(RXF_UDP | RXF_TCP))) { |
ba5d3c66 | 1775 | if (!pkt->ip_frag) { |
fd3a4790 | 1776 | skb->ip_summed = CHECKSUM_UNNECESSARY; |
ba5d3c66 DM |
1777 | rxq->stats.rx_cso++; |
1778 | } else if (pkt->l2info & htonl(RXF_IP)) { | |
fd3a4790 DM |
1779 | __sum16 c = (__force __sum16)pkt->csum; |
1780 | skb->csum = csum_unfold(c); | |
1781 | skb->ip_summed = CHECKSUM_COMPLETE; | |
ba5d3c66 | 1782 | rxq->stats.rx_cso++; |
fd3a4790 | 1783 | } |
fd3a4790 | 1784 | } else |
bc8acf2c | 1785 | skb_checksum_none_assert(skb); |
fd3a4790 DM |
1786 | |
1787 | if (unlikely(pkt->vlan_ex)) { | |
86a9bad3 | 1788 | __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), ntohs(pkt->vlan)); |
fd3a4790 | 1789 | rxq->stats.vlan_ex++; |
19ecae2c DM |
1790 | } |
1791 | netif_receive_skb(skb); | |
fd3a4790 DM |
1792 | return 0; |
1793 | } | |
1794 | ||
1795 | /** | |
1796 | * restore_rx_bufs - put back a packet's Rx buffers | |
1797 | * @si: the packet gather list | |
1798 | * @q: the SGE free list | |
1799 | * @frags: number of FL buffers to restore | |
1800 | * | |
1801 | * Puts back on an FL the Rx buffers associated with @si. The buffers | |
1802 | * have already been unmapped and are left unmapped, we mark them so to | |
1803 | * prevent further unmapping attempts. | |
1804 | * | |
1805 | * This function undoes a series of @unmap_rx_buf calls when we find out | |
1806 | * that the current packet can't be processed right away afterall and we | |
1807 | * need to come back to it later. This is a very rare event and there's | |
1808 | * no effort to make this particularly efficient. | |
1809 | */ | |
1810 | static void restore_rx_bufs(const struct pkt_gl *si, struct sge_fl *q, | |
1811 | int frags) | |
1812 | { | |
1813 | struct rx_sw_desc *d; | |
1814 | ||
1815 | while (frags--) { | |
1816 | if (q->cidx == 0) | |
1817 | q->cidx = q->size - 1; | |
1818 | else | |
1819 | q->cidx--; | |
1820 | d = &q->sdesc[q->cidx]; | |
1821 | d->page = si->frags[frags].page; | |
1822 | d->dma_addr |= RX_UNMAPPED_BUF; | |
1823 | q->avail++; | |
1824 | } | |
1825 | } | |
1826 | ||
1827 | /** | |
1828 | * is_new_response - check if a response is newly written | |
1829 | * @r: the response descriptor | |
1830 | * @q: the response queue | |
1831 | * | |
1832 | * Returns true if a response descriptor contains a yet unprocessed | |
1833 | * response. | |
1834 | */ | |
1835 | static inline bool is_new_response(const struct rsp_ctrl *r, | |
1836 | const struct sge_rspq *q) | |
1837 | { | |
1838 | return RSPD_GEN(r->type_gen) == q->gen; | |
1839 | } | |
1840 | ||
1841 | /** | |
1842 | * rspq_next - advance to the next entry in a response queue | |
1843 | * @q: the queue | |
1844 | * | |
1845 | * Updates the state of a response queue to advance it to the next entry. | |
1846 | */ | |
1847 | static inline void rspq_next(struct sge_rspq *q) | |
1848 | { | |
1849 | q->cur_desc = (void *)q->cur_desc + q->iqe_len; | |
1850 | if (unlikely(++q->cidx == q->size)) { | |
1851 | q->cidx = 0; | |
1852 | q->gen ^= 1; | |
1853 | q->cur_desc = q->desc; | |
1854 | } | |
1855 | } | |
1856 | ||
1857 | /** | |
1858 | * process_responses - process responses from an SGE response queue | |
1859 | * @q: the ingress queue to process | |
1860 | * @budget: how many responses can be processed in this round | |
1861 | * | |
1862 | * Process responses from an SGE response queue up to the supplied budget. | |
1863 | * Responses include received packets as well as control messages from FW | |
1864 | * or HW. | |
1865 | * | |
1866 | * Additionally choose the interrupt holdoff time for the next interrupt | |
1867 | * on this queue. If the system is under memory shortage use a fairly | |
1868 | * long delay to help recovery. | |
1869 | */ | |
1870 | static int process_responses(struct sge_rspq *q, int budget) | |
1871 | { | |
1872 | int ret, rsp_type; | |
1873 | int budget_left = budget; | |
1874 | const struct rsp_ctrl *rc; | |
1875 | struct sge_eth_rxq *rxq = container_of(q, struct sge_eth_rxq, rspq); | |
52367a76 VP |
1876 | struct adapter *adapter = q->adap; |
1877 | struct sge *s = &adapter->sge; | |
fd3a4790 DM |
1878 | |
1879 | while (likely(budget_left)) { | |
1880 | rc = (void *)q->cur_desc + (q->iqe_len - sizeof(*rc)); | |
1881 | if (!is_new_response(rc, q)) | |
1882 | break; | |
1883 | ||
1884 | rmb(); | |
1885 | rsp_type = RSPD_TYPE(rc->type_gen); | |
1886 | if (likely(rsp_type == RSP_TYPE_FLBUF)) { | |
e91b0f24 | 1887 | struct page_frag *fp; |
fd3a4790 DM |
1888 | struct pkt_gl si; |
1889 | const struct rx_sw_desc *rsd; | |
1890 | u32 len = ntohl(rc->pldbuflen_qid), bufsz, frags; | |
1891 | ||
1892 | if (len & RSPD_NEWBUF) { | |
1893 | if (likely(q->offset > 0)) { | |
1894 | free_rx_bufs(q->adap, &rxq->fl, 1); | |
1895 | q->offset = 0; | |
1896 | } | |
1704d748 | 1897 | len = RSPD_LEN(len); |
fd3a4790 DM |
1898 | } |
1899 | si.tot_len = len; | |
1900 | ||
1901 | /* gather packet fragments */ | |
1902 | for (frags = 0, fp = si.frags; ; frags++, fp++) { | |
1903 | rsd = &rxq->fl.sdesc[rxq->fl.cidx]; | |
52367a76 | 1904 | bufsz = get_buf_size(adapter, rsd); |
fd3a4790 | 1905 | fp->page = rsd->page; |
e91b0f24 IC |
1906 | fp->offset = q->offset; |
1907 | fp->size = min(bufsz, len); | |
1908 | len -= fp->size; | |
fd3a4790 DM |
1909 | if (!len) |
1910 | break; | |
1911 | unmap_rx_buf(q->adap, &rxq->fl); | |
1912 | } | |
1913 | ||
1914 | /* | |
1915 | * Last buffer remains mapped so explicitly make it | |
1916 | * coherent for CPU access. | |
1917 | */ | |
1918 | dma_sync_single_for_cpu(q->adap->pdev_dev, | |
1919 | get_buf_addr(rsd), | |
e91b0f24 | 1920 | fp->size, DMA_FROM_DEVICE); |
fd3a4790 DM |
1921 | |
1922 | si.va = page_address(si.frags[0].page) + | |
e91b0f24 | 1923 | si.frags[0].offset; |
fd3a4790 DM |
1924 | prefetch(si.va); |
1925 | ||
1926 | si.nfrags = frags + 1; | |
1927 | ret = q->handler(q, q->cur_desc, &si); | |
1928 | if (likely(ret == 0)) | |
52367a76 | 1929 | q->offset += ALIGN(fp->size, s->fl_align); |
fd3a4790 DM |
1930 | else |
1931 | restore_rx_bufs(&si, &rxq->fl, frags); | |
1932 | } else if (likely(rsp_type == RSP_TYPE_CPL)) { | |
1933 | ret = q->handler(q, q->cur_desc, NULL); | |
1934 | } else { | |
1935 | ret = q->handler(q, (const __be64 *)rc, CXGB4_MSG_AN); | |
1936 | } | |
1937 | ||
1938 | if (unlikely(ret)) { | |
1939 | /* couldn't process descriptor, back off for recovery */ | |
1940 | q->next_intr_params = QINTR_TIMER_IDX(NOMEM_TMR_IDX); | |
1941 | break; | |
1942 | } | |
1943 | ||
1944 | rspq_next(q); | |
1945 | budget_left--; | |
1946 | } | |
1947 | ||
1948 | if (q->offset >= 0 && rxq->fl.size - rxq->fl.avail >= 16) | |
1949 | __refill_fl(q->adap, &rxq->fl); | |
1950 | return budget - budget_left; | |
1951 | } | |
1952 | ||
1953 | /** | |
1954 | * napi_rx_handler - the NAPI handler for Rx processing | |
1955 | * @napi: the napi instance | |
1956 | * @budget: how many packets we can process in this round | |
1957 | * | |
1958 | * Handler for new data events when using NAPI. This does not need any | |
1959 | * locking or protection from interrupts as data interrupts are off at | |
1960 | * this point and other adapter interrupts do not interfere (the latter | |
1961 | * in not a concern at all with MSI-X as non-data interrupts then have | |
1962 | * a separate handler). | |
1963 | */ | |
1964 | static int napi_rx_handler(struct napi_struct *napi, int budget) | |
1965 | { | |
1966 | unsigned int params; | |
1967 | struct sge_rspq *q = container_of(napi, struct sge_rspq, napi); | |
1968 | int work_done = process_responses(q, budget); | |
d63a6dcf | 1969 | u32 val; |
fd3a4790 DM |
1970 | |
1971 | if (likely(work_done < budget)) { | |
1972 | napi_complete(napi); | |
1973 | params = q->next_intr_params; | |
1974 | q->next_intr_params = q->intr_params; | |
1975 | } else | |
1976 | params = QINTR_TIMER_IDX(7); | |
1977 | ||
d63a6dcf HS |
1978 | val = CIDXINC(work_done) | SEINTARM(params); |
1979 | if (is_t4(q->adap->params.chip)) { | |
1980 | t4_write_reg(q->adap, MYPF_REG(SGE_PF_GTS), | |
1981 | val | INGRESSQID((u32)q->cntxt_id)); | |
1982 | } else { | |
1983 | writel(val, q->adap->bar2 + q->udb + SGE_UDB_GTS); | |
1984 | wmb(); | |
1985 | } | |
fd3a4790 DM |
1986 | return work_done; |
1987 | } | |
1988 | ||
1989 | /* | |
1990 | * The MSI-X interrupt handler for an SGE response queue. | |
1991 | */ | |
1992 | irqreturn_t t4_sge_intr_msix(int irq, void *cookie) | |
1993 | { | |
1994 | struct sge_rspq *q = cookie; | |
1995 | ||
1996 | napi_schedule(&q->napi); | |
1997 | return IRQ_HANDLED; | |
1998 | } | |
1999 | ||
2000 | /* | |
2001 | * Process the indirect interrupt entries in the interrupt queue and kick off | |
2002 | * NAPI for each queue that has generated an entry. | |
2003 | */ | |
2004 | static unsigned int process_intrq(struct adapter *adap) | |
2005 | { | |
2006 | unsigned int credits; | |
2007 | const struct rsp_ctrl *rc; | |
2008 | struct sge_rspq *q = &adap->sge.intrq; | |
d63a6dcf | 2009 | u32 val; |
fd3a4790 DM |
2010 | |
2011 | spin_lock(&adap->sge.intrq_lock); | |
2012 | for (credits = 0; ; credits++) { | |
2013 | rc = (void *)q->cur_desc + (q->iqe_len - sizeof(*rc)); | |
2014 | if (!is_new_response(rc, q)) | |
2015 | break; | |
2016 | ||
2017 | rmb(); | |
2018 | if (RSPD_TYPE(rc->type_gen) == RSP_TYPE_INTR) { | |
2019 | unsigned int qid = ntohl(rc->pldbuflen_qid); | |
2020 | ||
e46dab4d | 2021 | qid -= adap->sge.ingr_start; |
fd3a4790 DM |
2022 | napi_schedule(&adap->sge.ingr_map[qid]->napi); |
2023 | } | |
2024 | ||
2025 | rspq_next(q); | |
2026 | } | |
2027 | ||
d63a6dcf HS |
2028 | val = CIDXINC(credits) | SEINTARM(q->intr_params); |
2029 | if (is_t4(adap->params.chip)) { | |
2030 | t4_write_reg(adap, MYPF_REG(SGE_PF_GTS), | |
2031 | val | INGRESSQID(q->cntxt_id)); | |
2032 | } else { | |
2033 | writel(val, adap->bar2 + q->udb + SGE_UDB_GTS); | |
2034 | wmb(); | |
2035 | } | |
fd3a4790 DM |
2036 | spin_unlock(&adap->sge.intrq_lock); |
2037 | return credits; | |
2038 | } | |
2039 | ||
2040 | /* | |
2041 | * The MSI interrupt handler, which handles data events from SGE response queues | |
2042 | * as well as error and other async events as they all use the same MSI vector. | |
2043 | */ | |
2044 | static irqreturn_t t4_intr_msi(int irq, void *cookie) | |
2045 | { | |
2046 | struct adapter *adap = cookie; | |
2047 | ||
2048 | t4_slow_intr_handler(adap); | |
2049 | process_intrq(adap); | |
2050 | return IRQ_HANDLED; | |
2051 | } | |
2052 | ||
2053 | /* | |
2054 | * Interrupt handler for legacy INTx interrupts. | |
2055 | * Handles data events from SGE response queues as well as error and other | |
2056 | * async events as they all use the same interrupt line. | |
2057 | */ | |
2058 | static irqreturn_t t4_intr_intx(int irq, void *cookie) | |
2059 | { | |
2060 | struct adapter *adap = cookie; | |
2061 | ||
2062 | t4_write_reg(adap, MYPF_REG(PCIE_PF_CLI), 0); | |
2063 | if (t4_slow_intr_handler(adap) | process_intrq(adap)) | |
2064 | return IRQ_HANDLED; | |
2065 | return IRQ_NONE; /* probably shared interrupt */ | |
2066 | } | |
2067 | ||
2068 | /** | |
2069 | * t4_intr_handler - select the top-level interrupt handler | |
2070 | * @adap: the adapter | |
2071 | * | |
2072 | * Selects the top-level interrupt handler based on the type of interrupts | |
2073 | * (MSI-X, MSI, or INTx). | |
2074 | */ | |
2075 | irq_handler_t t4_intr_handler(struct adapter *adap) | |
2076 | { | |
2077 | if (adap->flags & USING_MSIX) | |
2078 | return t4_sge_intr_msix; | |
2079 | if (adap->flags & USING_MSI) | |
2080 | return t4_intr_msi; | |
2081 | return t4_intr_intx; | |
2082 | } | |
2083 | ||
2084 | static void sge_rx_timer_cb(unsigned long data) | |
2085 | { | |
2086 | unsigned long m; | |
0f4d201f | 2087 | unsigned int i, idma_same_state_cnt[2]; |
fd3a4790 DM |
2088 | struct adapter *adap = (struct adapter *)data; |
2089 | struct sge *s = &adap->sge; | |
2090 | ||
2091 | for (i = 0; i < ARRAY_SIZE(s->starving_fl); i++) | |
2092 | for (m = s->starving_fl[i]; m; m &= m - 1) { | |
2093 | struct sge_eth_rxq *rxq; | |
2094 | unsigned int id = __ffs(m) + i * BITS_PER_LONG; | |
2095 | struct sge_fl *fl = s->egr_map[id]; | |
2096 | ||
2097 | clear_bit(id, s->starving_fl); | |
4e857c58 | 2098 | smp_mb__after_atomic(); |
fd3a4790 DM |
2099 | |
2100 | if (fl_starving(fl)) { | |
2101 | rxq = container_of(fl, struct sge_eth_rxq, fl); | |
2102 | if (napi_reschedule(&rxq->rspq.napi)) | |
2103 | fl->starving++; | |
2104 | else | |
2105 | set_bit(id, s->starving_fl); | |
2106 | } | |
2107 | } | |
2108 | ||
2109 | t4_write_reg(adap, SGE_DEBUG_INDEX, 13); | |
0f4d201f KS |
2110 | idma_same_state_cnt[0] = t4_read_reg(adap, SGE_DEBUG_DATA_HIGH); |
2111 | idma_same_state_cnt[1] = t4_read_reg(adap, SGE_DEBUG_DATA_LOW); | |
2112 | ||
2113 | for (i = 0; i < 2; i++) { | |
2114 | u32 debug0, debug11; | |
2115 | ||
2116 | /* If the Ingress DMA Same State Counter ("timer") is less | |
2117 | * than 1s, then we can reset our synthesized Stall Timer and | |
2118 | * continue. If we have previously emitted warnings about a | |
2119 | * potential stalled Ingress Queue, issue a note indicating | |
2120 | * that the Ingress Queue has resumed forward progress. | |
2121 | */ | |
2122 | if (idma_same_state_cnt[i] < s->idma_1s_thresh) { | |
2123 | if (s->idma_stalled[i] >= SGE_IDMA_WARN_THRESH) | |
2124 | CH_WARN(adap, "SGE idma%d, queue%u,resumed after %d sec\n", | |
2125 | i, s->idma_qid[i], | |
2126 | s->idma_stalled[i]/HZ); | |
2127 | s->idma_stalled[i] = 0; | |
2128 | continue; | |
2129 | } | |
2130 | ||
2131 | /* Synthesize an SGE Ingress DMA Same State Timer in the Hz | |
2132 | * domain. The first time we get here it'll be because we | |
2133 | * passed the 1s Threshold; each additional time it'll be | |
2134 | * because the RX Timer Callback is being fired on its regular | |
2135 | * schedule. | |
2136 | * | |
2137 | * If the stall is below our Potential Hung Ingress Queue | |
2138 | * Warning Threshold, continue. | |
2139 | */ | |
2140 | if (s->idma_stalled[i] == 0) | |
2141 | s->idma_stalled[i] = HZ; | |
2142 | else | |
2143 | s->idma_stalled[i] += RX_QCHECK_PERIOD; | |
2144 | ||
2145 | if (s->idma_stalled[i] < SGE_IDMA_WARN_THRESH) | |
2146 | continue; | |
2147 | ||
2148 | /* We'll issue a warning every SGE_IDMA_WARN_REPEAT Hz */ | |
2149 | if (((s->idma_stalled[i] - HZ) % SGE_IDMA_WARN_REPEAT) != 0) | |
2150 | continue; | |
2151 | ||
2152 | /* Read and save the SGE IDMA State and Queue ID information. | |
2153 | * We do this every time in case it changes across time ... | |
2154 | */ | |
2155 | t4_write_reg(adap, SGE_DEBUG_INDEX, 0); | |
2156 | debug0 = t4_read_reg(adap, SGE_DEBUG_DATA_LOW); | |
2157 | s->idma_state[i] = (debug0 >> (i * 9)) & 0x3f; | |
2158 | ||
2159 | t4_write_reg(adap, SGE_DEBUG_INDEX, 11); | |
2160 | debug11 = t4_read_reg(adap, SGE_DEBUG_DATA_LOW); | |
2161 | s->idma_qid[i] = (debug11 >> (i * 16)) & 0xffff; | |
2162 | ||
2163 | CH_WARN(adap, "SGE idma%u, queue%u, maybe stuck state%u %dsecs (debug0=%#x, debug11=%#x)\n", | |
2164 | i, s->idma_qid[i], s->idma_state[i], | |
2165 | s->idma_stalled[i]/HZ, debug0, debug11); | |
2166 | t4_sge_decode_idma_state(adap, s->idma_state[i]); | |
2167 | } | |
fd3a4790 DM |
2168 | |
2169 | mod_timer(&s->rx_timer, jiffies + RX_QCHECK_PERIOD); | |
2170 | } | |
2171 | ||
2172 | static void sge_tx_timer_cb(unsigned long data) | |
2173 | { | |
2174 | unsigned long m; | |
2175 | unsigned int i, budget; | |
2176 | struct adapter *adap = (struct adapter *)data; | |
2177 | struct sge *s = &adap->sge; | |
2178 | ||
2179 | for (i = 0; i < ARRAY_SIZE(s->txq_maperr); i++) | |
2180 | for (m = s->txq_maperr[i]; m; m &= m - 1) { | |
2181 | unsigned long id = __ffs(m) + i * BITS_PER_LONG; | |
2182 | struct sge_ofld_txq *txq = s->egr_map[id]; | |
2183 | ||
2184 | clear_bit(id, s->txq_maperr); | |
2185 | tasklet_schedule(&txq->qresume_tsk); | |
2186 | } | |
2187 | ||
2188 | budget = MAX_TIMER_TX_RECLAIM; | |
2189 | i = s->ethtxq_rover; | |
2190 | do { | |
2191 | struct sge_eth_txq *q = &s->ethtxq[i]; | |
2192 | ||
2193 | if (q->q.in_use && | |
2194 | time_after_eq(jiffies, q->txq->trans_start + HZ / 100) && | |
2195 | __netif_tx_trylock(q->txq)) { | |
2196 | int avail = reclaimable(&q->q); | |
2197 | ||
2198 | if (avail) { | |
2199 | if (avail > budget) | |
2200 | avail = budget; | |
2201 | ||
2202 | free_tx_desc(adap, &q->q, avail, true); | |
2203 | q->q.in_use -= avail; | |
2204 | budget -= avail; | |
2205 | } | |
2206 | __netif_tx_unlock(q->txq); | |
2207 | } | |
2208 | ||
2209 | if (++i >= s->ethqsets) | |
2210 | i = 0; | |
2211 | } while (budget && i != s->ethtxq_rover); | |
2212 | s->ethtxq_rover = i; | |
2213 | mod_timer(&s->tx_timer, jiffies + (budget ? TX_QCHECK_PERIOD : 2)); | |
2214 | } | |
2215 | ||
d63a6dcf HS |
2216 | /** |
2217 | * udb_address - return the BAR2 User Doorbell address for a Queue | |
2218 | * @adap: the adapter | |
2219 | * @cntxt_id: the Queue Context ID | |
2220 | * @qpp: Queues Per Page (for all PFs) | |
2221 | * | |
2222 | * Returns the BAR2 address of the user Doorbell associated with the | |
2223 | * indicated Queue Context ID. Note that this is only applicable | |
2224 | * for T5 and later. | |
2225 | */ | |
2226 | static u64 udb_address(struct adapter *adap, unsigned int cntxt_id, | |
2227 | unsigned int qpp) | |
2228 | { | |
2229 | u64 udb; | |
2230 | unsigned int s_qpp; | |
2231 | unsigned short udb_density; | |
2232 | unsigned long qpshift; | |
2233 | int page; | |
2234 | ||
2235 | BUG_ON(is_t4(adap->params.chip)); | |
2236 | ||
2237 | s_qpp = (QUEUESPERPAGEPF0 + | |
2238 | (QUEUESPERPAGEPF1 - QUEUESPERPAGEPF0) * adap->fn); | |
2239 | udb_density = 1 << ((qpp >> s_qpp) & QUEUESPERPAGEPF0_MASK); | |
2240 | qpshift = PAGE_SHIFT - ilog2(udb_density); | |
2241 | udb = cntxt_id << qpshift; | |
2242 | udb &= PAGE_MASK; | |
2243 | page = udb / PAGE_SIZE; | |
2244 | udb += (cntxt_id - (page * udb_density)) * SGE_UDB_SIZE; | |
2245 | ||
2246 | return udb; | |
2247 | } | |
2248 | ||
2249 | static u64 udb_address_eq(struct adapter *adap, unsigned int cntxt_id) | |
2250 | { | |
2251 | return udb_address(adap, cntxt_id, | |
2252 | t4_read_reg(adap, SGE_EGRESS_QUEUES_PER_PAGE_PF)); | |
2253 | } | |
2254 | ||
2255 | static u64 udb_address_iq(struct adapter *adap, unsigned int cntxt_id) | |
2256 | { | |
2257 | return udb_address(adap, cntxt_id, | |
2258 | t4_read_reg(adap, SGE_INGRESS_QUEUES_PER_PAGE_PF)); | |
2259 | } | |
2260 | ||
fd3a4790 DM |
2261 | int t4_sge_alloc_rxq(struct adapter *adap, struct sge_rspq *iq, bool fwevtq, |
2262 | struct net_device *dev, int intr_idx, | |
2263 | struct sge_fl *fl, rspq_handler_t hnd) | |
2264 | { | |
2265 | int ret, flsz = 0; | |
2266 | struct fw_iq_cmd c; | |
52367a76 | 2267 | struct sge *s = &adap->sge; |
fd3a4790 DM |
2268 | struct port_info *pi = netdev_priv(dev); |
2269 | ||
2270 | /* Size needs to be multiple of 16, including status entry. */ | |
2271 | iq->size = roundup(iq->size, 16); | |
2272 | ||
2273 | iq->desc = alloc_ring(adap->pdev_dev, iq->size, iq->iqe_len, 0, | |
ad6bad3e | 2274 | &iq->phys_addr, NULL, 0, NUMA_NO_NODE); |
fd3a4790 DM |
2275 | if (!iq->desc) |
2276 | return -ENOMEM; | |
2277 | ||
2278 | memset(&c, 0, sizeof(c)); | |
2279 | c.op_to_vfn = htonl(FW_CMD_OP(FW_IQ_CMD) | FW_CMD_REQUEST | | |
2280 | FW_CMD_WRITE | FW_CMD_EXEC | | |
060e0c75 | 2281 | FW_IQ_CMD_PFN(adap->fn) | FW_IQ_CMD_VFN(0)); |
fd3a4790 DM |
2282 | c.alloc_to_len16 = htonl(FW_IQ_CMD_ALLOC | FW_IQ_CMD_IQSTART(1) | |
2283 | FW_LEN16(c)); | |
2284 | c.type_to_iqandstindex = htonl(FW_IQ_CMD_TYPE(FW_IQ_TYPE_FL_INT_CAP) | | |
2285 | FW_IQ_CMD_IQASYNCH(fwevtq) | FW_IQ_CMD_VIID(pi->viid) | | |
2286 | FW_IQ_CMD_IQANDST(intr_idx < 0) | FW_IQ_CMD_IQANUD(1) | | |
2287 | FW_IQ_CMD_IQANDSTINDEX(intr_idx >= 0 ? intr_idx : | |
2288 | -intr_idx - 1)); | |
2289 | c.iqdroprss_to_iqesize = htons(FW_IQ_CMD_IQPCIECH(pi->tx_chan) | | |
2290 | FW_IQ_CMD_IQGTSMODE | | |
2291 | FW_IQ_CMD_IQINTCNTTHRESH(iq->pktcnt_idx) | | |
2292 | FW_IQ_CMD_IQESIZE(ilog2(iq->iqe_len) - 4)); | |
2293 | c.iqsize = htons(iq->size); | |
2294 | c.iqaddr = cpu_to_be64(iq->phys_addr); | |
2295 | ||
2296 | if (fl) { | |
2297 | fl->size = roundup(fl->size, 8); | |
2298 | fl->desc = alloc_ring(adap->pdev_dev, fl->size, sizeof(__be64), | |
2299 | sizeof(struct rx_sw_desc), &fl->addr, | |
52367a76 | 2300 | &fl->sdesc, s->stat_len, NUMA_NO_NODE); |
fd3a4790 DM |
2301 | if (!fl->desc) |
2302 | goto fl_nomem; | |
2303 | ||
52367a76 | 2304 | flsz = fl->size / 8 + s->stat_len / sizeof(struct tx_desc); |
ce91a923 | 2305 | c.iqns_to_fl0congen = htonl(FW_IQ_CMD_FL0PACKEN(1) | |
ef306b50 DM |
2306 | FW_IQ_CMD_FL0FETCHRO(1) | |
2307 | FW_IQ_CMD_FL0DATARO(1) | | |
ce91a923 | 2308 | FW_IQ_CMD_FL0PADEN(1)); |
fd3a4790 DM |
2309 | c.fl0dcaen_to_fl0cidxfthresh = htons(FW_IQ_CMD_FL0FBMIN(2) | |
2310 | FW_IQ_CMD_FL0FBMAX(3)); | |
2311 | c.fl0size = htons(flsz); | |
2312 | c.fl0addr = cpu_to_be64(fl->addr); | |
2313 | } | |
2314 | ||
060e0c75 | 2315 | ret = t4_wr_mbox(adap, adap->fn, &c, sizeof(c), &c); |
fd3a4790 DM |
2316 | if (ret) |
2317 | goto err; | |
2318 | ||
2319 | netif_napi_add(dev, &iq->napi, napi_rx_handler, 64); | |
2320 | iq->cur_desc = iq->desc; | |
2321 | iq->cidx = 0; | |
2322 | iq->gen = 1; | |
2323 | iq->next_intr_params = iq->intr_params; | |
2324 | iq->cntxt_id = ntohs(c.iqid); | |
2325 | iq->abs_id = ntohs(c.physiqid); | |
d63a6dcf HS |
2326 | if (!is_t4(adap->params.chip)) |
2327 | iq->udb = udb_address_iq(adap, iq->cntxt_id); | |
fd3a4790 | 2328 | iq->size--; /* subtract status entry */ |
fd3a4790 DM |
2329 | iq->netdev = dev; |
2330 | iq->handler = hnd; | |
2331 | ||
2332 | /* set offset to -1 to distinguish ingress queues without FL */ | |
2333 | iq->offset = fl ? 0 : -1; | |
2334 | ||
e46dab4d | 2335 | adap->sge.ingr_map[iq->cntxt_id - adap->sge.ingr_start] = iq; |
fd3a4790 DM |
2336 | |
2337 | if (fl) { | |
62718b32 | 2338 | fl->cntxt_id = ntohs(c.fl0id); |
fd3a4790 DM |
2339 | fl->avail = fl->pend_cred = 0; |
2340 | fl->pidx = fl->cidx = 0; | |
2341 | fl->alloc_failed = fl->large_alloc_failed = fl->starving = 0; | |
e46dab4d | 2342 | adap->sge.egr_map[fl->cntxt_id - adap->sge.egr_start] = fl; |
d63a6dcf HS |
2343 | |
2344 | /* Note, we must initialize the Free List User Doorbell | |
2345 | * address before refilling the Free List! | |
2346 | */ | |
2347 | if (!is_t4(adap->params.chip)) | |
2348 | fl->udb = udb_address_eq(adap, fl->cntxt_id); | |
fd3a4790 DM |
2349 | refill_fl(adap, fl, fl_cap(fl), GFP_KERNEL); |
2350 | } | |
2351 | return 0; | |
2352 | ||
2353 | fl_nomem: | |
2354 | ret = -ENOMEM; | |
2355 | err: | |
2356 | if (iq->desc) { | |
2357 | dma_free_coherent(adap->pdev_dev, iq->size * iq->iqe_len, | |
2358 | iq->desc, iq->phys_addr); | |
2359 | iq->desc = NULL; | |
2360 | } | |
2361 | if (fl && fl->desc) { | |
2362 | kfree(fl->sdesc); | |
2363 | fl->sdesc = NULL; | |
2364 | dma_free_coherent(adap->pdev_dev, flsz * sizeof(struct tx_desc), | |
2365 | fl->desc, fl->addr); | |
2366 | fl->desc = NULL; | |
2367 | } | |
2368 | return ret; | |
2369 | } | |
2370 | ||
2371 | static void init_txq(struct adapter *adap, struct sge_txq *q, unsigned int id) | |
2372 | { | |
22adfe0a | 2373 | q->cntxt_id = id; |
d63a6dcf HS |
2374 | if (!is_t4(adap->params.chip)) |
2375 | q->udb = udb_address_eq(adap, q->cntxt_id); | |
22adfe0a | 2376 | |
fd3a4790 DM |
2377 | q->in_use = 0; |
2378 | q->cidx = q->pidx = 0; | |
2379 | q->stops = q->restarts = 0; | |
2380 | q->stat = (void *)&q->desc[q->size]; | |
3069ee9b | 2381 | spin_lock_init(&q->db_lock); |
e46dab4d | 2382 | adap->sge.egr_map[id - adap->sge.egr_start] = q; |
fd3a4790 DM |
2383 | } |
2384 | ||
2385 | int t4_sge_alloc_eth_txq(struct adapter *adap, struct sge_eth_txq *txq, | |
2386 | struct net_device *dev, struct netdev_queue *netdevq, | |
2387 | unsigned int iqid) | |
2388 | { | |
2389 | int ret, nentries; | |
2390 | struct fw_eq_eth_cmd c; | |
52367a76 | 2391 | struct sge *s = &adap->sge; |
fd3a4790 DM |
2392 | struct port_info *pi = netdev_priv(dev); |
2393 | ||
2394 | /* Add status entries */ | |
52367a76 | 2395 | nentries = txq->q.size + s->stat_len / sizeof(struct tx_desc); |
fd3a4790 DM |
2396 | |
2397 | txq->q.desc = alloc_ring(adap->pdev_dev, txq->q.size, | |
2398 | sizeof(struct tx_desc), sizeof(struct tx_sw_desc), | |
52367a76 | 2399 | &txq->q.phys_addr, &txq->q.sdesc, s->stat_len, |
ad6bad3e | 2400 | netdev_queue_numa_node_read(netdevq)); |
fd3a4790 DM |
2401 | if (!txq->q.desc) |
2402 | return -ENOMEM; | |
2403 | ||
2404 | memset(&c, 0, sizeof(c)); | |
2405 | c.op_to_vfn = htonl(FW_CMD_OP(FW_EQ_ETH_CMD) | FW_CMD_REQUEST | | |
2406 | FW_CMD_WRITE | FW_CMD_EXEC | | |
060e0c75 | 2407 | FW_EQ_ETH_CMD_PFN(adap->fn) | FW_EQ_ETH_CMD_VFN(0)); |
fd3a4790 DM |
2408 | c.alloc_to_len16 = htonl(FW_EQ_ETH_CMD_ALLOC | |
2409 | FW_EQ_ETH_CMD_EQSTART | FW_LEN16(c)); | |
08f1a1b9 HS |
2410 | c.viid_pkd = htonl(FW_EQ_ETH_CMD_AUTOEQUEQE | |
2411 | FW_EQ_ETH_CMD_VIID(pi->viid)); | |
fd3a4790 DM |
2412 | c.fetchszm_to_iqid = htonl(FW_EQ_ETH_CMD_HOSTFCMODE(2) | |
2413 | FW_EQ_ETH_CMD_PCIECHN(pi->tx_chan) | | |
ef306b50 | 2414 | FW_EQ_ETH_CMD_FETCHRO(1) | |
fd3a4790 DM |
2415 | FW_EQ_ETH_CMD_IQID(iqid)); |
2416 | c.dcaen_to_eqsize = htonl(FW_EQ_ETH_CMD_FBMIN(2) | | |
2417 | FW_EQ_ETH_CMD_FBMAX(3) | | |
2418 | FW_EQ_ETH_CMD_CIDXFTHRESH(5) | | |
2419 | FW_EQ_ETH_CMD_EQSIZE(nentries)); | |
2420 | c.eqaddr = cpu_to_be64(txq->q.phys_addr); | |
2421 | ||
060e0c75 | 2422 | ret = t4_wr_mbox(adap, adap->fn, &c, sizeof(c), &c); |
fd3a4790 DM |
2423 | if (ret) { |
2424 | kfree(txq->q.sdesc); | |
2425 | txq->q.sdesc = NULL; | |
2426 | dma_free_coherent(adap->pdev_dev, | |
2427 | nentries * sizeof(struct tx_desc), | |
2428 | txq->q.desc, txq->q.phys_addr); | |
2429 | txq->q.desc = NULL; | |
2430 | return ret; | |
2431 | } | |
2432 | ||
2433 | init_txq(adap, &txq->q, FW_EQ_ETH_CMD_EQID_GET(ntohl(c.eqid_pkd))); | |
2434 | txq->txq = netdevq; | |
2435 | txq->tso = txq->tx_cso = txq->vlan_ins = 0; | |
2436 | txq->mapping_err = 0; | |
2437 | return 0; | |
2438 | } | |
2439 | ||
2440 | int t4_sge_alloc_ctrl_txq(struct adapter *adap, struct sge_ctrl_txq *txq, | |
2441 | struct net_device *dev, unsigned int iqid, | |
2442 | unsigned int cmplqid) | |
2443 | { | |
2444 | int ret, nentries; | |
2445 | struct fw_eq_ctrl_cmd c; | |
52367a76 | 2446 | struct sge *s = &adap->sge; |
fd3a4790 DM |
2447 | struct port_info *pi = netdev_priv(dev); |
2448 | ||
2449 | /* Add status entries */ | |
52367a76 | 2450 | nentries = txq->q.size + s->stat_len / sizeof(struct tx_desc); |
fd3a4790 DM |
2451 | |
2452 | txq->q.desc = alloc_ring(adap->pdev_dev, nentries, | |
2453 | sizeof(struct tx_desc), 0, &txq->q.phys_addr, | |
ad6bad3e | 2454 | NULL, 0, NUMA_NO_NODE); |
fd3a4790 DM |
2455 | if (!txq->q.desc) |
2456 | return -ENOMEM; | |
2457 | ||
2458 | c.op_to_vfn = htonl(FW_CMD_OP(FW_EQ_CTRL_CMD) | FW_CMD_REQUEST | | |
2459 | FW_CMD_WRITE | FW_CMD_EXEC | | |
060e0c75 DM |
2460 | FW_EQ_CTRL_CMD_PFN(adap->fn) | |
2461 | FW_EQ_CTRL_CMD_VFN(0)); | |
fd3a4790 DM |
2462 | c.alloc_to_len16 = htonl(FW_EQ_CTRL_CMD_ALLOC | |
2463 | FW_EQ_CTRL_CMD_EQSTART | FW_LEN16(c)); | |
2464 | c.cmpliqid_eqid = htonl(FW_EQ_CTRL_CMD_CMPLIQID(cmplqid)); | |
2465 | c.physeqid_pkd = htonl(0); | |
2466 | c.fetchszm_to_iqid = htonl(FW_EQ_CTRL_CMD_HOSTFCMODE(2) | | |
2467 | FW_EQ_CTRL_CMD_PCIECHN(pi->tx_chan) | | |
ef306b50 | 2468 | FW_EQ_CTRL_CMD_FETCHRO | |
fd3a4790 DM |
2469 | FW_EQ_CTRL_CMD_IQID(iqid)); |
2470 | c.dcaen_to_eqsize = htonl(FW_EQ_CTRL_CMD_FBMIN(2) | | |
2471 | FW_EQ_CTRL_CMD_FBMAX(3) | | |
2472 | FW_EQ_CTRL_CMD_CIDXFTHRESH(5) | | |
2473 | FW_EQ_CTRL_CMD_EQSIZE(nentries)); | |
2474 | c.eqaddr = cpu_to_be64(txq->q.phys_addr); | |
2475 | ||
060e0c75 | 2476 | ret = t4_wr_mbox(adap, adap->fn, &c, sizeof(c), &c); |
fd3a4790 DM |
2477 | if (ret) { |
2478 | dma_free_coherent(adap->pdev_dev, | |
2479 | nentries * sizeof(struct tx_desc), | |
2480 | txq->q.desc, txq->q.phys_addr); | |
2481 | txq->q.desc = NULL; | |
2482 | return ret; | |
2483 | } | |
2484 | ||
2485 | init_txq(adap, &txq->q, FW_EQ_CTRL_CMD_EQID_GET(ntohl(c.cmpliqid_eqid))); | |
2486 | txq->adap = adap; | |
2487 | skb_queue_head_init(&txq->sendq); | |
2488 | tasklet_init(&txq->qresume_tsk, restart_ctrlq, (unsigned long)txq); | |
2489 | txq->full = 0; | |
2490 | return 0; | |
2491 | } | |
2492 | ||
2493 | int t4_sge_alloc_ofld_txq(struct adapter *adap, struct sge_ofld_txq *txq, | |
2494 | struct net_device *dev, unsigned int iqid) | |
2495 | { | |
2496 | int ret, nentries; | |
2497 | struct fw_eq_ofld_cmd c; | |
52367a76 | 2498 | struct sge *s = &adap->sge; |
fd3a4790 DM |
2499 | struct port_info *pi = netdev_priv(dev); |
2500 | ||
2501 | /* Add status entries */ | |
52367a76 | 2502 | nentries = txq->q.size + s->stat_len / sizeof(struct tx_desc); |
fd3a4790 DM |
2503 | |
2504 | txq->q.desc = alloc_ring(adap->pdev_dev, txq->q.size, | |
2505 | sizeof(struct tx_desc), sizeof(struct tx_sw_desc), | |
52367a76 | 2506 | &txq->q.phys_addr, &txq->q.sdesc, s->stat_len, |
ad6bad3e | 2507 | NUMA_NO_NODE); |
fd3a4790 DM |
2508 | if (!txq->q.desc) |
2509 | return -ENOMEM; | |
2510 | ||
2511 | memset(&c, 0, sizeof(c)); | |
2512 | c.op_to_vfn = htonl(FW_CMD_OP(FW_EQ_OFLD_CMD) | FW_CMD_REQUEST | | |
2513 | FW_CMD_WRITE | FW_CMD_EXEC | | |
060e0c75 DM |
2514 | FW_EQ_OFLD_CMD_PFN(adap->fn) | |
2515 | FW_EQ_OFLD_CMD_VFN(0)); | |
fd3a4790 DM |
2516 | c.alloc_to_len16 = htonl(FW_EQ_OFLD_CMD_ALLOC | |
2517 | FW_EQ_OFLD_CMD_EQSTART | FW_LEN16(c)); | |
2518 | c.fetchszm_to_iqid = htonl(FW_EQ_OFLD_CMD_HOSTFCMODE(2) | | |
2519 | FW_EQ_OFLD_CMD_PCIECHN(pi->tx_chan) | | |
ef306b50 | 2520 | FW_EQ_OFLD_CMD_FETCHRO(1) | |
fd3a4790 DM |
2521 | FW_EQ_OFLD_CMD_IQID(iqid)); |
2522 | c.dcaen_to_eqsize = htonl(FW_EQ_OFLD_CMD_FBMIN(2) | | |
2523 | FW_EQ_OFLD_CMD_FBMAX(3) | | |
2524 | FW_EQ_OFLD_CMD_CIDXFTHRESH(5) | | |
2525 | FW_EQ_OFLD_CMD_EQSIZE(nentries)); | |
2526 | c.eqaddr = cpu_to_be64(txq->q.phys_addr); | |
2527 | ||
060e0c75 | 2528 | ret = t4_wr_mbox(adap, adap->fn, &c, sizeof(c), &c); |
fd3a4790 DM |
2529 | if (ret) { |
2530 | kfree(txq->q.sdesc); | |
2531 | txq->q.sdesc = NULL; | |
2532 | dma_free_coherent(adap->pdev_dev, | |
2533 | nentries * sizeof(struct tx_desc), | |
2534 | txq->q.desc, txq->q.phys_addr); | |
2535 | txq->q.desc = NULL; | |
2536 | return ret; | |
2537 | } | |
2538 | ||
2539 | init_txq(adap, &txq->q, FW_EQ_OFLD_CMD_EQID_GET(ntohl(c.eqid_pkd))); | |
2540 | txq->adap = adap; | |
2541 | skb_queue_head_init(&txq->sendq); | |
2542 | tasklet_init(&txq->qresume_tsk, restart_ofldq, (unsigned long)txq); | |
2543 | txq->full = 0; | |
2544 | txq->mapping_err = 0; | |
2545 | return 0; | |
2546 | } | |
2547 | ||
2548 | static void free_txq(struct adapter *adap, struct sge_txq *q) | |
2549 | { | |
52367a76 VP |
2550 | struct sge *s = &adap->sge; |
2551 | ||
fd3a4790 | 2552 | dma_free_coherent(adap->pdev_dev, |
52367a76 | 2553 | q->size * sizeof(struct tx_desc) + s->stat_len, |
fd3a4790 DM |
2554 | q->desc, q->phys_addr); |
2555 | q->cntxt_id = 0; | |
2556 | q->sdesc = NULL; | |
2557 | q->desc = NULL; | |
2558 | } | |
2559 | ||
2560 | static void free_rspq_fl(struct adapter *adap, struct sge_rspq *rq, | |
2561 | struct sge_fl *fl) | |
2562 | { | |
52367a76 | 2563 | struct sge *s = &adap->sge; |
fd3a4790 DM |
2564 | unsigned int fl_id = fl ? fl->cntxt_id : 0xffff; |
2565 | ||
e46dab4d | 2566 | adap->sge.ingr_map[rq->cntxt_id - adap->sge.ingr_start] = NULL; |
060e0c75 DM |
2567 | t4_iq_free(adap, adap->fn, adap->fn, 0, FW_IQ_TYPE_FL_INT_CAP, |
2568 | rq->cntxt_id, fl_id, 0xffff); | |
fd3a4790 DM |
2569 | dma_free_coherent(adap->pdev_dev, (rq->size + 1) * rq->iqe_len, |
2570 | rq->desc, rq->phys_addr); | |
2571 | netif_napi_del(&rq->napi); | |
2572 | rq->netdev = NULL; | |
2573 | rq->cntxt_id = rq->abs_id = 0; | |
2574 | rq->desc = NULL; | |
2575 | ||
2576 | if (fl) { | |
2577 | free_rx_bufs(adap, fl, fl->avail); | |
52367a76 | 2578 | dma_free_coherent(adap->pdev_dev, fl->size * 8 + s->stat_len, |
fd3a4790 DM |
2579 | fl->desc, fl->addr); |
2580 | kfree(fl->sdesc); | |
2581 | fl->sdesc = NULL; | |
2582 | fl->cntxt_id = 0; | |
2583 | fl->desc = NULL; | |
2584 | } | |
2585 | } | |
2586 | ||
5fa76694 HS |
2587 | /** |
2588 | * t4_free_ofld_rxqs - free a block of consecutive Rx queues | |
2589 | * @adap: the adapter | |
2590 | * @n: number of queues | |
2591 | * @q: pointer to first queue | |
2592 | * | |
2593 | * Release the resources of a consecutive block of offload Rx queues. | |
2594 | */ | |
2595 | void t4_free_ofld_rxqs(struct adapter *adap, int n, struct sge_ofld_rxq *q) | |
2596 | { | |
2597 | for ( ; n; n--, q++) | |
2598 | if (q->rspq.desc) | |
2599 | free_rspq_fl(adap, &q->rspq, | |
2600 | q->fl.size ? &q->fl : NULL); | |
2601 | } | |
2602 | ||
fd3a4790 DM |
2603 | /** |
2604 | * t4_free_sge_resources - free SGE resources | |
2605 | * @adap: the adapter | |
2606 | * | |
2607 | * Frees resources used by the SGE queue sets. | |
2608 | */ | |
2609 | void t4_free_sge_resources(struct adapter *adap) | |
2610 | { | |
2611 | int i; | |
2612 | struct sge_eth_rxq *eq = adap->sge.ethrxq; | |
2613 | struct sge_eth_txq *etq = adap->sge.ethtxq; | |
fd3a4790 DM |
2614 | |
2615 | /* clean up Ethernet Tx/Rx queues */ | |
2616 | for (i = 0; i < adap->sge.ethqsets; i++, eq++, etq++) { | |
2617 | if (eq->rspq.desc) | |
5fa76694 HS |
2618 | free_rspq_fl(adap, &eq->rspq, |
2619 | eq->fl.size ? &eq->fl : NULL); | |
fd3a4790 | 2620 | if (etq->q.desc) { |
060e0c75 DM |
2621 | t4_eth_eq_free(adap, adap->fn, adap->fn, 0, |
2622 | etq->q.cntxt_id); | |
fd3a4790 DM |
2623 | free_tx_desc(adap, &etq->q, etq->q.in_use, true); |
2624 | kfree(etq->q.sdesc); | |
2625 | free_txq(adap, &etq->q); | |
2626 | } | |
2627 | } | |
2628 | ||
2629 | /* clean up RDMA and iSCSI Rx queues */ | |
5fa76694 HS |
2630 | t4_free_ofld_rxqs(adap, adap->sge.ofldqsets, adap->sge.ofldrxq); |
2631 | t4_free_ofld_rxqs(adap, adap->sge.rdmaqs, adap->sge.rdmarxq); | |
2632 | t4_free_ofld_rxqs(adap, adap->sge.rdmaciqs, adap->sge.rdmaciq); | |
fd3a4790 DM |
2633 | |
2634 | /* clean up offload Tx queues */ | |
2635 | for (i = 0; i < ARRAY_SIZE(adap->sge.ofldtxq); i++) { | |
2636 | struct sge_ofld_txq *q = &adap->sge.ofldtxq[i]; | |
2637 | ||
2638 | if (q->q.desc) { | |
2639 | tasklet_kill(&q->qresume_tsk); | |
060e0c75 DM |
2640 | t4_ofld_eq_free(adap, adap->fn, adap->fn, 0, |
2641 | q->q.cntxt_id); | |
fd3a4790 DM |
2642 | free_tx_desc(adap, &q->q, q->q.in_use, false); |
2643 | kfree(q->q.sdesc); | |
2644 | __skb_queue_purge(&q->sendq); | |
2645 | free_txq(adap, &q->q); | |
2646 | } | |
2647 | } | |
2648 | ||
2649 | /* clean up control Tx queues */ | |
2650 | for (i = 0; i < ARRAY_SIZE(adap->sge.ctrlq); i++) { | |
2651 | struct sge_ctrl_txq *cq = &adap->sge.ctrlq[i]; | |
2652 | ||
2653 | if (cq->q.desc) { | |
2654 | tasklet_kill(&cq->qresume_tsk); | |
060e0c75 DM |
2655 | t4_ctrl_eq_free(adap, adap->fn, adap->fn, 0, |
2656 | cq->q.cntxt_id); | |
fd3a4790 DM |
2657 | __skb_queue_purge(&cq->sendq); |
2658 | free_txq(adap, &cq->q); | |
2659 | } | |
2660 | } | |
2661 | ||
2662 | if (adap->sge.fw_evtq.desc) | |
2663 | free_rspq_fl(adap, &adap->sge.fw_evtq, NULL); | |
2664 | ||
2665 | if (adap->sge.intrq.desc) | |
2666 | free_rspq_fl(adap, &adap->sge.intrq, NULL); | |
2667 | ||
2668 | /* clear the reverse egress queue map */ | |
2669 | memset(adap->sge.egr_map, 0, sizeof(adap->sge.egr_map)); | |
2670 | } | |
2671 | ||
2672 | void t4_sge_start(struct adapter *adap) | |
2673 | { | |
2674 | adap->sge.ethtxq_rover = 0; | |
2675 | mod_timer(&adap->sge.rx_timer, jiffies + RX_QCHECK_PERIOD); | |
2676 | mod_timer(&adap->sge.tx_timer, jiffies + TX_QCHECK_PERIOD); | |
2677 | } | |
2678 | ||
2679 | /** | |
2680 | * t4_sge_stop - disable SGE operation | |
2681 | * @adap: the adapter | |
2682 | * | |
2683 | * Stop tasklets and timers associated with the DMA engine. Note that | |
2684 | * this is effective only if measures have been taken to disable any HW | |
2685 | * events that may restart them. | |
2686 | */ | |
2687 | void t4_sge_stop(struct adapter *adap) | |
2688 | { | |
2689 | int i; | |
2690 | struct sge *s = &adap->sge; | |
2691 | ||
2692 | if (in_interrupt()) /* actions below require waiting */ | |
2693 | return; | |
2694 | ||
2695 | if (s->rx_timer.function) | |
2696 | del_timer_sync(&s->rx_timer); | |
2697 | if (s->tx_timer.function) | |
2698 | del_timer_sync(&s->tx_timer); | |
2699 | ||
2700 | for (i = 0; i < ARRAY_SIZE(s->ofldtxq); i++) { | |
2701 | struct sge_ofld_txq *q = &s->ofldtxq[i]; | |
2702 | ||
2703 | if (q->q.desc) | |
2704 | tasklet_kill(&q->qresume_tsk); | |
2705 | } | |
2706 | for (i = 0; i < ARRAY_SIZE(s->ctrlq); i++) { | |
2707 | struct sge_ctrl_txq *cq = &s->ctrlq[i]; | |
2708 | ||
2709 | if (cq->q.desc) | |
2710 | tasklet_kill(&cq->qresume_tsk); | |
2711 | } | |
2712 | } | |
2713 | ||
2714 | /** | |
2715 | * t4_sge_init - initialize SGE | |
2716 | * @adap: the adapter | |
2717 | * | |
2718 | * Performs SGE initialization needed every time after a chip reset. | |
2719 | * We do not initialize any of the queues here, instead the driver | |
2720 | * top-level must request them individually. | |
52367a76 VP |
2721 | * |
2722 | * Called in two different modes: | |
2723 | * | |
2724 | * 1. Perform actual hardware initialization and record hard-coded | |
2725 | * parameters which were used. This gets used when we're the | |
2726 | * Master PF and the Firmware Configuration File support didn't | |
2727 | * work for some reason. | |
2728 | * | |
2729 | * 2. We're not the Master PF or initialization was performed with | |
2730 | * a Firmware Configuration File. In this case we need to grab | |
2731 | * any of the SGE operating parameters that we need to have in | |
2732 | * order to do our job and make sure we can live with them ... | |
fd3a4790 | 2733 | */ |
52367a76 VP |
2734 | |
2735 | static int t4_sge_init_soft(struct adapter *adap) | |
fd3a4790 DM |
2736 | { |
2737 | struct sge *s = &adap->sge; | |
52367a76 VP |
2738 | u32 fl_small_pg, fl_large_pg, fl_small_mtu, fl_large_mtu; |
2739 | u32 timer_value_0_and_1, timer_value_2_and_3, timer_value_4_and_5; | |
2740 | u32 ingress_rx_threshold; | |
fd3a4790 | 2741 | |
52367a76 VP |
2742 | /* |
2743 | * Verify that CPL messages are going to the Ingress Queue for | |
2744 | * process_responses() and that only packet data is going to the | |
2745 | * Free Lists. | |
2746 | */ | |
2747 | if ((t4_read_reg(adap, SGE_CONTROL) & RXPKTCPLMODE_MASK) != | |
2748 | RXPKTCPLMODE(X_RXPKTCPLMODE_SPLIT)) { | |
2749 | dev_err(adap->pdev_dev, "bad SGE CPL MODE\n"); | |
2750 | return -EINVAL; | |
2751 | } | |
2752 | ||
2753 | /* | |
2754 | * Validate the Host Buffer Register Array indices that we want to | |
2755 | * use ... | |
2756 | * | |
2757 | * XXX Note that we should really read through the Host Buffer Size | |
2758 | * XXX register array and find the indices of the Buffer Sizes which | |
2759 | * XXX meet our needs! | |
2760 | */ | |
2761 | #define READ_FL_BUF(x) \ | |
2762 | t4_read_reg(adap, SGE_FL_BUFFER_SIZE0+(x)*sizeof(u32)) | |
2763 | ||
2764 | fl_small_pg = READ_FL_BUF(RX_SMALL_PG_BUF); | |
2765 | fl_large_pg = READ_FL_BUF(RX_LARGE_PG_BUF); | |
2766 | fl_small_mtu = READ_FL_BUF(RX_SMALL_MTU_BUF); | |
2767 | fl_large_mtu = READ_FL_BUF(RX_LARGE_MTU_BUF); | |
2768 | ||
92ddcc7b KS |
2769 | /* We only bother using the Large Page logic if the Large Page Buffer |
2770 | * is larger than our Page Size Buffer. | |
2771 | */ | |
2772 | if (fl_large_pg <= fl_small_pg) | |
2773 | fl_large_pg = 0; | |
2774 | ||
52367a76 VP |
2775 | #undef READ_FL_BUF |
2776 | ||
92ddcc7b KS |
2777 | /* The Page Size Buffer must be exactly equal to our Page Size and the |
2778 | * Large Page Size Buffer should be 0 (per above) or a power of 2. | |
2779 | */ | |
52367a76 | 2780 | if (fl_small_pg != PAGE_SIZE || |
92ddcc7b | 2781 | (fl_large_pg & (fl_large_pg-1)) != 0) { |
52367a76 VP |
2782 | dev_err(adap->pdev_dev, "bad SGE FL page buffer sizes [%d, %d]\n", |
2783 | fl_small_pg, fl_large_pg); | |
2784 | return -EINVAL; | |
2785 | } | |
2786 | if (fl_large_pg) | |
2787 | s->fl_pg_order = ilog2(fl_large_pg) - PAGE_SHIFT; | |
2788 | ||
2789 | if (fl_small_mtu < FL_MTU_SMALL_BUFSIZE(adap) || | |
2790 | fl_large_mtu < FL_MTU_LARGE_BUFSIZE(adap)) { | |
2791 | dev_err(adap->pdev_dev, "bad SGE FL MTU sizes [%d, %d]\n", | |
2792 | fl_small_mtu, fl_large_mtu); | |
2793 | return -EINVAL; | |
2794 | } | |
2795 | ||
2796 | /* | |
2797 | * Retrieve our RX interrupt holdoff timer values and counter | |
2798 | * threshold values from the SGE parameters. | |
2799 | */ | |
2800 | timer_value_0_and_1 = t4_read_reg(adap, SGE_TIMER_VALUE_0_AND_1); | |
2801 | timer_value_2_and_3 = t4_read_reg(adap, SGE_TIMER_VALUE_2_AND_3); | |
2802 | timer_value_4_and_5 = t4_read_reg(adap, SGE_TIMER_VALUE_4_AND_5); | |
2803 | s->timer_val[0] = core_ticks_to_us(adap, | |
2804 | TIMERVALUE0_GET(timer_value_0_and_1)); | |
2805 | s->timer_val[1] = core_ticks_to_us(adap, | |
2806 | TIMERVALUE1_GET(timer_value_0_and_1)); | |
2807 | s->timer_val[2] = core_ticks_to_us(adap, | |
2808 | TIMERVALUE2_GET(timer_value_2_and_3)); | |
2809 | s->timer_val[3] = core_ticks_to_us(adap, | |
2810 | TIMERVALUE3_GET(timer_value_2_and_3)); | |
2811 | s->timer_val[4] = core_ticks_to_us(adap, | |
2812 | TIMERVALUE4_GET(timer_value_4_and_5)); | |
2813 | s->timer_val[5] = core_ticks_to_us(adap, | |
2814 | TIMERVALUE5_GET(timer_value_4_and_5)); | |
2815 | ||
2816 | ingress_rx_threshold = t4_read_reg(adap, SGE_INGRESS_RX_THRESHOLD); | |
2817 | s->counter_val[0] = THRESHOLD_0_GET(ingress_rx_threshold); | |
2818 | s->counter_val[1] = THRESHOLD_1_GET(ingress_rx_threshold); | |
2819 | s->counter_val[2] = THRESHOLD_2_GET(ingress_rx_threshold); | |
2820 | s->counter_val[3] = THRESHOLD_3_GET(ingress_rx_threshold); | |
2821 | ||
2822 | return 0; | |
2823 | } | |
2824 | ||
2825 | static int t4_sge_init_hard(struct adapter *adap) | |
2826 | { | |
2827 | struct sge *s = &adap->sge; | |
2828 | ||
2829 | /* | |
2830 | * Set up our basic SGE mode to deliver CPL messages to our Ingress | |
2831 | * Queue and Packet Date to the Free List. | |
2832 | */ | |
2833 | t4_set_reg_field(adap, SGE_CONTROL, RXPKTCPLMODE_MASK, | |
2834 | RXPKTCPLMODE_MASK); | |
060e0c75 | 2835 | |
3069ee9b VP |
2836 | /* |
2837 | * Set up to drop DOORBELL writes when the DOORBELL FIFO overflows | |
2838 | * and generate an interrupt when this occurs so we can recover. | |
2839 | */ | |
d14807dd | 2840 | if (is_t4(adap->params.chip)) { |
0a57a536 SR |
2841 | t4_set_reg_field(adap, A_SGE_DBFIFO_STATUS, |
2842 | V_HP_INT_THRESH(M_HP_INT_THRESH) | | |
2843 | V_LP_INT_THRESH(M_LP_INT_THRESH), | |
2844 | V_HP_INT_THRESH(dbfifo_int_thresh) | | |
2845 | V_LP_INT_THRESH(dbfifo_int_thresh)); | |
2846 | } else { | |
2847 | t4_set_reg_field(adap, A_SGE_DBFIFO_STATUS, | |
2848 | V_LP_INT_THRESH_T5(M_LP_INT_THRESH_T5), | |
2849 | V_LP_INT_THRESH_T5(dbfifo_int_thresh)); | |
2850 | t4_set_reg_field(adap, SGE_DBFIFO_STATUS2, | |
2851 | V_HP_INT_THRESH_T5(M_HP_INT_THRESH_T5), | |
2852 | V_HP_INT_THRESH_T5(dbfifo_int_thresh)); | |
2853 | } | |
881806bc VP |
2854 | t4_set_reg_field(adap, A_SGE_DOORBELL_CONTROL, F_ENABLE_DROP, |
2855 | F_ENABLE_DROP); | |
2856 | ||
52367a76 VP |
2857 | /* |
2858 | * SGE_FL_BUFFER_SIZE0 (RX_SMALL_PG_BUF) is set up by | |
2859 | * t4_fixup_host_params(). | |
2860 | */ | |
2861 | s->fl_pg_order = FL_PG_ORDER; | |
2862 | if (s->fl_pg_order) | |
2863 | t4_write_reg(adap, | |
2864 | SGE_FL_BUFFER_SIZE0+RX_LARGE_PG_BUF*sizeof(u32), | |
2865 | PAGE_SIZE << FL_PG_ORDER); | |
2866 | t4_write_reg(adap, SGE_FL_BUFFER_SIZE0+RX_SMALL_MTU_BUF*sizeof(u32), | |
2867 | FL_MTU_SMALL_BUFSIZE(adap)); | |
2868 | t4_write_reg(adap, SGE_FL_BUFFER_SIZE0+RX_LARGE_MTU_BUF*sizeof(u32), | |
2869 | FL_MTU_LARGE_BUFSIZE(adap)); | |
2870 | ||
2871 | /* | |
2872 | * Note that the SGE Ingress Packet Count Interrupt Threshold and | |
2873 | * Timer Holdoff values must be supplied by our caller. | |
2874 | */ | |
fd3a4790 DM |
2875 | t4_write_reg(adap, SGE_INGRESS_RX_THRESHOLD, |
2876 | THRESHOLD_0(s->counter_val[0]) | | |
2877 | THRESHOLD_1(s->counter_val[1]) | | |
2878 | THRESHOLD_2(s->counter_val[2]) | | |
2879 | THRESHOLD_3(s->counter_val[3])); | |
2880 | t4_write_reg(adap, SGE_TIMER_VALUE_0_AND_1, | |
2881 | TIMERVALUE0(us_to_core_ticks(adap, s->timer_val[0])) | | |
2882 | TIMERVALUE1(us_to_core_ticks(adap, s->timer_val[1]))); | |
2883 | t4_write_reg(adap, SGE_TIMER_VALUE_2_AND_3, | |
52367a76 VP |
2884 | TIMERVALUE2(us_to_core_ticks(adap, s->timer_val[2])) | |
2885 | TIMERVALUE3(us_to_core_ticks(adap, s->timer_val[3]))); | |
fd3a4790 | 2886 | t4_write_reg(adap, SGE_TIMER_VALUE_4_AND_5, |
52367a76 VP |
2887 | TIMERVALUE4(us_to_core_ticks(adap, s->timer_val[4])) | |
2888 | TIMERVALUE5(us_to_core_ticks(adap, s->timer_val[5]))); | |
2889 | ||
2890 | return 0; | |
2891 | } | |
2892 | ||
2893 | int t4_sge_init(struct adapter *adap) | |
2894 | { | |
2895 | struct sge *s = &adap->sge; | |
c2b955e0 KS |
2896 | u32 sge_control, sge_conm_ctrl; |
2897 | int ret, egress_threshold; | |
52367a76 VP |
2898 | |
2899 | /* | |
2900 | * Ingress Padding Boundary and Egress Status Page Size are set up by | |
2901 | * t4_fixup_host_params(). | |
2902 | */ | |
2903 | sge_control = t4_read_reg(adap, SGE_CONTROL); | |
2904 | s->pktshift = PKTSHIFT_GET(sge_control); | |
2905 | s->stat_len = (sge_control & EGRSTATUSPAGESIZE_MASK) ? 128 : 64; | |
2906 | s->fl_align = 1 << (INGPADBOUNDARY_GET(sge_control) + | |
2907 | X_INGPADBOUNDARY_SHIFT); | |
2908 | ||
2909 | if (adap->flags & USING_SOFT_PARAMS) | |
2910 | ret = t4_sge_init_soft(adap); | |
2911 | else | |
2912 | ret = t4_sge_init_hard(adap); | |
2913 | if (ret < 0) | |
2914 | return ret; | |
2915 | ||
2916 | /* | |
2917 | * A FL with <= fl_starve_thres buffers is starving and a periodic | |
2918 | * timer will attempt to refill it. This needs to be larger than the | |
2919 | * SGE's Egress Congestion Threshold. If it isn't, then we can get | |
2920 | * stuck waiting for new packets while the SGE is waiting for us to | |
2921 | * give it more Free List entries. (Note that the SGE's Egress | |
c2b955e0 KS |
2922 | * Congestion Threshold is in units of 2 Free List pointers.) For T4, |
2923 | * there was only a single field to control this. For T5 there's the | |
2924 | * original field which now only applies to Unpacked Mode Free List | |
2925 | * buffers and a new field which only applies to Packed Mode Free List | |
2926 | * buffers. | |
52367a76 | 2927 | */ |
c2b955e0 KS |
2928 | sge_conm_ctrl = t4_read_reg(adap, SGE_CONM_CTRL); |
2929 | if (is_t4(adap->params.chip)) | |
2930 | egress_threshold = EGRTHRESHOLD_GET(sge_conm_ctrl); | |
2931 | else | |
2932 | egress_threshold = EGRTHRESHOLDPACKING_GET(sge_conm_ctrl); | |
2933 | s->fl_starve_thres = 2*egress_threshold + 1; | |
52367a76 | 2934 | |
fd3a4790 DM |
2935 | setup_timer(&s->rx_timer, sge_rx_timer_cb, (unsigned long)adap); |
2936 | setup_timer(&s->tx_timer, sge_tx_timer_cb, (unsigned long)adap); | |
0f4d201f KS |
2937 | s->idma_1s_thresh = core_ticks_per_usec(adap) * 1000000; /* 1 s */ |
2938 | s->idma_stalled[0] = 0; | |
2939 | s->idma_stalled[1] = 0; | |
fd3a4790 | 2940 | spin_lock_init(&s->intrq_lock); |
52367a76 VP |
2941 | |
2942 | return 0; | |
fd3a4790 | 2943 | } |