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fd3a4790 DM |
1 | /* |
2 | * This file is part of the Chelsio T4 Ethernet driver for Linux. | |
3 | * | |
ce100b8b | 4 | * Copyright (c) 2003-2014 Chelsio Communications, Inc. All rights reserved. |
fd3a4790 DM |
5 | * |
6 | * This software is available to you under a choice of one of two | |
7 | * licenses. You may choose to be licensed under the terms of the GNU | |
8 | * General Public License (GPL) Version 2, available from the file | |
9 | * COPYING in the main directory of this source tree, or the | |
10 | * OpenIB.org BSD license below: | |
11 | * | |
12 | * Redistribution and use in source and binary forms, with or | |
13 | * without modification, are permitted provided that the following | |
14 | * conditions are met: | |
15 | * | |
16 | * - Redistributions of source code must retain the above | |
17 | * copyright notice, this list of conditions and the following | |
18 | * disclaimer. | |
19 | * | |
20 | * - Redistributions in binary form must reproduce the above | |
21 | * copyright notice, this list of conditions and the following | |
22 | * disclaimer in the documentation and/or other materials | |
23 | * provided with the distribution. | |
24 | * | |
25 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
26 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
27 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
28 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
29 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
30 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
31 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
32 | * SOFTWARE. | |
33 | */ | |
34 | ||
35 | #include <linux/skbuff.h> | |
36 | #include <linux/netdevice.h> | |
37 | #include <linux/etherdevice.h> | |
38 | #include <linux/if_vlan.h> | |
39 | #include <linux/ip.h> | |
40 | #include <linux/dma-mapping.h> | |
41 | #include <linux/jiffies.h> | |
70c71606 | 42 | #include <linux/prefetch.h> |
ee40fa06 | 43 | #include <linux/export.h> |
fd3a4790 DM |
44 | #include <net/ipv6.h> |
45 | #include <net/tcp.h> | |
46 | #include "cxgb4.h" | |
47 | #include "t4_regs.h" | |
f612b815 | 48 | #include "t4_values.h" |
fd3a4790 DM |
49 | #include "t4_msg.h" |
50 | #include "t4fw_api.h" | |
51 | ||
52 | /* | |
53 | * Rx buffer size. We use largish buffers if possible but settle for single | |
54 | * pages under memory shortage. | |
55 | */ | |
56 | #if PAGE_SHIFT >= 16 | |
57 | # define FL_PG_ORDER 0 | |
58 | #else | |
59 | # define FL_PG_ORDER (16 - PAGE_SHIFT) | |
60 | #endif | |
61 | ||
62 | /* RX_PULL_LEN should be <= RX_COPY_THRES */ | |
63 | #define RX_COPY_THRES 256 | |
64 | #define RX_PULL_LEN 128 | |
65 | ||
66 | /* | |
67 | * Main body length for sk_buffs used for Rx Ethernet packets with fragments. | |
68 | * Should be >= RX_PULL_LEN but possibly bigger to give pskb_may_pull some room. | |
69 | */ | |
70 | #define RX_PKT_SKB_LEN 512 | |
71 | ||
fd3a4790 DM |
72 | /* |
73 | * Max number of Tx descriptors we clean up at a time. Should be modest as | |
74 | * freeing skbs isn't cheap and it happens while holding locks. We just need | |
75 | * to free packets faster than they arrive, we eventually catch up and keep | |
76 | * the amortized cost reasonable. Must be >= 2 * TXQ_STOP_THRES. | |
77 | */ | |
78 | #define MAX_TX_RECLAIM 16 | |
79 | ||
80 | /* | |
81 | * Max number of Rx buffers we replenish at a time. Again keep this modest, | |
82 | * allocating buffers isn't cheap either. | |
83 | */ | |
84 | #define MAX_RX_REFILL 16U | |
85 | ||
86 | /* | |
87 | * Period of the Rx queue check timer. This timer is infrequent as it has | |
88 | * something to do only when the system experiences severe memory shortage. | |
89 | */ | |
90 | #define RX_QCHECK_PERIOD (HZ / 2) | |
91 | ||
92 | /* | |
93 | * Period of the Tx queue check timer. | |
94 | */ | |
95 | #define TX_QCHECK_PERIOD (HZ / 2) | |
96 | ||
0f4d201f KS |
97 | /* SGE Hung Ingress DMA Threshold Warning time (in Hz) and Warning Repeat Rate |
98 | * (in RX_QCHECK_PERIOD multiples). If we find one of the SGE Ingress DMA | |
99 | * State Machines in the same state for this amount of time (in HZ) then we'll | |
100 | * issue a warning about a potential hang. We'll repeat the warning as the | |
101 | * SGE Ingress DMA Channel appears to be hung every N RX_QCHECK_PERIODs till | |
102 | * the situation clears. If the situation clears, we'll note that as well. | |
103 | */ | |
104 | #define SGE_IDMA_WARN_THRESH (1 * HZ) | |
105 | #define SGE_IDMA_WARN_REPEAT (20 * RX_QCHECK_PERIOD) | |
106 | ||
fd3a4790 DM |
107 | /* |
108 | * Max number of Tx descriptors to be reclaimed by the Tx timer. | |
109 | */ | |
110 | #define MAX_TIMER_TX_RECLAIM 100 | |
111 | ||
112 | /* | |
113 | * Timer index used when backing off due to memory shortage. | |
114 | */ | |
115 | #define NOMEM_TMR_IDX (SGE_NTIMERS - 1) | |
116 | ||
117 | /* | |
118 | * An FL with <= FL_STARVE_THRES buffers is starving and a periodic timer will | |
119 | * attempt to refill it. | |
120 | */ | |
121 | #define FL_STARVE_THRES 4 | |
122 | ||
123 | /* | |
124 | * Suspend an Ethernet Tx queue with fewer available descriptors than this. | |
125 | * This is the same as calc_tx_descs() for a TSO packet with | |
126 | * nr_frags == MAX_SKB_FRAGS. | |
127 | */ | |
128 | #define ETHTXQ_STOP_THRES \ | |
129 | (1 + DIV_ROUND_UP((3 * MAX_SKB_FRAGS) / 2 + (MAX_SKB_FRAGS & 1), 8)) | |
130 | ||
131 | /* | |
132 | * Suspension threshold for non-Ethernet Tx queues. We require enough room | |
133 | * for a full sized WR. | |
134 | */ | |
135 | #define TXQ_STOP_THRES (SGE_MAX_WR_LEN / sizeof(struct tx_desc)) | |
136 | ||
137 | /* | |
138 | * Max Tx descriptor space we allow for an Ethernet packet to be inlined | |
139 | * into a WR. | |
140 | */ | |
141 | #define MAX_IMM_TX_PKT_LEN 128 | |
142 | ||
143 | /* | |
144 | * Max size of a WR sent through a control Tx queue. | |
145 | */ | |
146 | #define MAX_CTRL_WR_LEN SGE_MAX_WR_LEN | |
147 | ||
fd3a4790 DM |
148 | struct tx_sw_desc { /* SW state per Tx descriptor */ |
149 | struct sk_buff *skb; | |
150 | struct ulptx_sgl *sgl; | |
151 | }; | |
152 | ||
153 | struct rx_sw_desc { /* SW state per Rx descriptor */ | |
154 | struct page *page; | |
155 | dma_addr_t dma_addr; | |
156 | }; | |
157 | ||
158 | /* | |
52367a76 VP |
159 | * Rx buffer sizes for "useskbs" Free List buffers (one ingress packet pe skb |
160 | * buffer). We currently only support two sizes for 1500- and 9000-byte MTUs. | |
161 | * We could easily support more but there doesn't seem to be much need for | |
162 | * that ... | |
163 | */ | |
164 | #define FL_MTU_SMALL 1500 | |
165 | #define FL_MTU_LARGE 9000 | |
166 | ||
167 | static inline unsigned int fl_mtu_bufsize(struct adapter *adapter, | |
168 | unsigned int mtu) | |
169 | { | |
170 | struct sge *s = &adapter->sge; | |
171 | ||
172 | return ALIGN(s->pktshift + ETH_HLEN + VLAN_HLEN + mtu, s->fl_align); | |
173 | } | |
174 | ||
175 | #define FL_MTU_SMALL_BUFSIZE(adapter) fl_mtu_bufsize(adapter, FL_MTU_SMALL) | |
176 | #define FL_MTU_LARGE_BUFSIZE(adapter) fl_mtu_bufsize(adapter, FL_MTU_LARGE) | |
177 | ||
178 | /* | |
179 | * Bits 0..3 of rx_sw_desc.dma_addr have special meaning. The hardware uses | |
180 | * these to specify the buffer size as an index into the SGE Free List Buffer | |
181 | * Size register array. We also use bit 4, when the buffer has been unmapped | |
182 | * for DMA, but this is of course never sent to the hardware and is only used | |
183 | * to prevent double unmappings. All of the above requires that the Free List | |
184 | * Buffers which we allocate have the bottom 5 bits free (0) -- i.e. are | |
185 | * 32-byte or or a power of 2 greater in alignment. Since the SGE's minimal | |
186 | * Free List Buffer alignment is 32 bytes, this works out for us ... | |
fd3a4790 DM |
187 | */ |
188 | enum { | |
52367a76 VP |
189 | RX_BUF_FLAGS = 0x1f, /* bottom five bits are special */ |
190 | RX_BUF_SIZE = 0x0f, /* bottom three bits are for buf sizes */ | |
191 | RX_UNMAPPED_BUF = 0x10, /* buffer is not mapped */ | |
192 | ||
193 | /* | |
194 | * XXX We shouldn't depend on being able to use these indices. | |
195 | * XXX Especially when some other Master PF has initialized the | |
196 | * XXX adapter or we use the Firmware Configuration File. We | |
197 | * XXX should really search through the Host Buffer Size register | |
198 | * XXX array for the appropriately sized buffer indices. | |
199 | */ | |
200 | RX_SMALL_PG_BUF = 0x0, /* small (PAGE_SIZE) page buffer */ | |
201 | RX_LARGE_PG_BUF = 0x1, /* buffer large (FL_PG_ORDER) page buffer */ | |
202 | ||
203 | RX_SMALL_MTU_BUF = 0x2, /* small MTU buffer */ | |
204 | RX_LARGE_MTU_BUF = 0x3, /* large MTU buffer */ | |
fd3a4790 DM |
205 | }; |
206 | ||
e553ec3f HS |
207 | static int timer_pkt_quota[] = {1, 1, 2, 3, 4, 5}; |
208 | #define MIN_NAPI_WORK 1 | |
209 | ||
fd3a4790 DM |
210 | static inline dma_addr_t get_buf_addr(const struct rx_sw_desc *d) |
211 | { | |
52367a76 | 212 | return d->dma_addr & ~(dma_addr_t)RX_BUF_FLAGS; |
fd3a4790 DM |
213 | } |
214 | ||
215 | static inline bool is_buf_mapped(const struct rx_sw_desc *d) | |
216 | { | |
217 | return !(d->dma_addr & RX_UNMAPPED_BUF); | |
218 | } | |
219 | ||
220 | /** | |
221 | * txq_avail - return the number of available slots in a Tx queue | |
222 | * @q: the Tx queue | |
223 | * | |
224 | * Returns the number of descriptors in a Tx queue available to write new | |
225 | * packets. | |
226 | */ | |
227 | static inline unsigned int txq_avail(const struct sge_txq *q) | |
228 | { | |
229 | return q->size - 1 - q->in_use; | |
230 | } | |
231 | ||
232 | /** | |
233 | * fl_cap - return the capacity of a free-buffer list | |
234 | * @fl: the FL | |
235 | * | |
236 | * Returns the capacity of a free-buffer list. The capacity is less than | |
237 | * the size because one descriptor needs to be left unpopulated, otherwise | |
238 | * HW will think the FL is empty. | |
239 | */ | |
240 | static inline unsigned int fl_cap(const struct sge_fl *fl) | |
241 | { | |
242 | return fl->size - 8; /* 1 descriptor = 8 buffers */ | |
243 | } | |
244 | ||
245 | static inline bool fl_starving(const struct sge_fl *fl) | |
246 | { | |
247 | return fl->avail - fl->pend_cred <= FL_STARVE_THRES; | |
248 | } | |
249 | ||
250 | static int map_skb(struct device *dev, const struct sk_buff *skb, | |
251 | dma_addr_t *addr) | |
252 | { | |
253 | const skb_frag_t *fp, *end; | |
254 | const struct skb_shared_info *si; | |
255 | ||
256 | *addr = dma_map_single(dev, skb->data, skb_headlen(skb), DMA_TO_DEVICE); | |
257 | if (dma_mapping_error(dev, *addr)) | |
258 | goto out_err; | |
259 | ||
260 | si = skb_shinfo(skb); | |
261 | end = &si->frags[si->nr_frags]; | |
262 | ||
263 | for (fp = si->frags; fp < end; fp++) { | |
e91b0f24 IC |
264 | *++addr = skb_frag_dma_map(dev, fp, 0, skb_frag_size(fp), |
265 | DMA_TO_DEVICE); | |
fd3a4790 DM |
266 | if (dma_mapping_error(dev, *addr)) |
267 | goto unwind; | |
268 | } | |
269 | return 0; | |
270 | ||
271 | unwind: | |
272 | while (fp-- > si->frags) | |
9e903e08 | 273 | dma_unmap_page(dev, *--addr, skb_frag_size(fp), DMA_TO_DEVICE); |
fd3a4790 DM |
274 | |
275 | dma_unmap_single(dev, addr[-1], skb_headlen(skb), DMA_TO_DEVICE); | |
276 | out_err: | |
277 | return -ENOMEM; | |
278 | } | |
279 | ||
280 | #ifdef CONFIG_NEED_DMA_MAP_STATE | |
281 | static void unmap_skb(struct device *dev, const struct sk_buff *skb, | |
282 | const dma_addr_t *addr) | |
283 | { | |
284 | const skb_frag_t *fp, *end; | |
285 | const struct skb_shared_info *si; | |
286 | ||
287 | dma_unmap_single(dev, *addr++, skb_headlen(skb), DMA_TO_DEVICE); | |
288 | ||
289 | si = skb_shinfo(skb); | |
290 | end = &si->frags[si->nr_frags]; | |
291 | for (fp = si->frags; fp < end; fp++) | |
9e903e08 | 292 | dma_unmap_page(dev, *addr++, skb_frag_size(fp), DMA_TO_DEVICE); |
fd3a4790 DM |
293 | } |
294 | ||
295 | /** | |
296 | * deferred_unmap_destructor - unmap a packet when it is freed | |
297 | * @skb: the packet | |
298 | * | |
299 | * This is the packet destructor used for Tx packets that need to remain | |
300 | * mapped until they are freed rather than until their Tx descriptors are | |
301 | * freed. | |
302 | */ | |
303 | static void deferred_unmap_destructor(struct sk_buff *skb) | |
304 | { | |
305 | unmap_skb(skb->dev->dev.parent, skb, (dma_addr_t *)skb->head); | |
306 | } | |
307 | #endif | |
308 | ||
309 | static void unmap_sgl(struct device *dev, const struct sk_buff *skb, | |
310 | const struct ulptx_sgl *sgl, const struct sge_txq *q) | |
311 | { | |
312 | const struct ulptx_sge_pair *p; | |
313 | unsigned int nfrags = skb_shinfo(skb)->nr_frags; | |
314 | ||
315 | if (likely(skb_headlen(skb))) | |
316 | dma_unmap_single(dev, be64_to_cpu(sgl->addr0), ntohl(sgl->len0), | |
317 | DMA_TO_DEVICE); | |
318 | else { | |
319 | dma_unmap_page(dev, be64_to_cpu(sgl->addr0), ntohl(sgl->len0), | |
320 | DMA_TO_DEVICE); | |
321 | nfrags--; | |
322 | } | |
323 | ||
324 | /* | |
325 | * the complexity below is because of the possibility of a wrap-around | |
326 | * in the middle of an SGL | |
327 | */ | |
328 | for (p = sgl->sge; nfrags >= 2; nfrags -= 2) { | |
329 | if (likely((u8 *)(p + 1) <= (u8 *)q->stat)) { | |
330 | unmap: dma_unmap_page(dev, be64_to_cpu(p->addr[0]), | |
331 | ntohl(p->len[0]), DMA_TO_DEVICE); | |
332 | dma_unmap_page(dev, be64_to_cpu(p->addr[1]), | |
333 | ntohl(p->len[1]), DMA_TO_DEVICE); | |
334 | p++; | |
335 | } else if ((u8 *)p == (u8 *)q->stat) { | |
336 | p = (const struct ulptx_sge_pair *)q->desc; | |
337 | goto unmap; | |
338 | } else if ((u8 *)p + 8 == (u8 *)q->stat) { | |
339 | const __be64 *addr = (const __be64 *)q->desc; | |
340 | ||
341 | dma_unmap_page(dev, be64_to_cpu(addr[0]), | |
342 | ntohl(p->len[0]), DMA_TO_DEVICE); | |
343 | dma_unmap_page(dev, be64_to_cpu(addr[1]), | |
344 | ntohl(p->len[1]), DMA_TO_DEVICE); | |
345 | p = (const struct ulptx_sge_pair *)&addr[2]; | |
346 | } else { | |
347 | const __be64 *addr = (const __be64 *)q->desc; | |
348 | ||
349 | dma_unmap_page(dev, be64_to_cpu(p->addr[0]), | |
350 | ntohl(p->len[0]), DMA_TO_DEVICE); | |
351 | dma_unmap_page(dev, be64_to_cpu(addr[0]), | |
352 | ntohl(p->len[1]), DMA_TO_DEVICE); | |
353 | p = (const struct ulptx_sge_pair *)&addr[1]; | |
354 | } | |
355 | } | |
356 | if (nfrags) { | |
357 | __be64 addr; | |
358 | ||
359 | if ((u8 *)p == (u8 *)q->stat) | |
360 | p = (const struct ulptx_sge_pair *)q->desc; | |
361 | addr = (u8 *)p + 16 <= (u8 *)q->stat ? p->addr[0] : | |
362 | *(const __be64 *)q->desc; | |
363 | dma_unmap_page(dev, be64_to_cpu(addr), ntohl(p->len[0]), | |
364 | DMA_TO_DEVICE); | |
365 | } | |
366 | } | |
367 | ||
368 | /** | |
369 | * free_tx_desc - reclaims Tx descriptors and their buffers | |
370 | * @adapter: the adapter | |
371 | * @q: the Tx queue to reclaim descriptors from | |
372 | * @n: the number of descriptors to reclaim | |
373 | * @unmap: whether the buffers should be unmapped for DMA | |
374 | * | |
375 | * Reclaims Tx descriptors from an SGE Tx queue and frees the associated | |
376 | * Tx buffers. Called with the Tx queue lock held. | |
377 | */ | |
378 | static void free_tx_desc(struct adapter *adap, struct sge_txq *q, | |
379 | unsigned int n, bool unmap) | |
380 | { | |
381 | struct tx_sw_desc *d; | |
382 | unsigned int cidx = q->cidx; | |
383 | struct device *dev = adap->pdev_dev; | |
384 | ||
385 | d = &q->sdesc[cidx]; | |
386 | while (n--) { | |
387 | if (d->skb) { /* an SGL is present */ | |
388 | if (unmap) | |
389 | unmap_sgl(dev, d->skb, d->sgl, q); | |
a7525198 | 390 | dev_consume_skb_any(d->skb); |
fd3a4790 DM |
391 | d->skb = NULL; |
392 | } | |
393 | ++d; | |
394 | if (++cidx == q->size) { | |
395 | cidx = 0; | |
396 | d = q->sdesc; | |
397 | } | |
398 | } | |
399 | q->cidx = cidx; | |
400 | } | |
401 | ||
402 | /* | |
403 | * Return the number of reclaimable descriptors in a Tx queue. | |
404 | */ | |
405 | static inline int reclaimable(const struct sge_txq *q) | |
406 | { | |
407 | int hw_cidx = ntohs(q->stat->cidx); | |
408 | hw_cidx -= q->cidx; | |
409 | return hw_cidx < 0 ? hw_cidx + q->size : hw_cidx; | |
410 | } | |
411 | ||
412 | /** | |
413 | * reclaim_completed_tx - reclaims completed Tx descriptors | |
414 | * @adap: the adapter | |
415 | * @q: the Tx queue to reclaim completed descriptors from | |
416 | * @unmap: whether the buffers should be unmapped for DMA | |
417 | * | |
418 | * Reclaims Tx descriptors that the SGE has indicated it has processed, | |
419 | * and frees the associated buffers if possible. Called with the Tx | |
420 | * queue locked. | |
421 | */ | |
422 | static inline void reclaim_completed_tx(struct adapter *adap, struct sge_txq *q, | |
423 | bool unmap) | |
424 | { | |
425 | int avail = reclaimable(q); | |
426 | ||
427 | if (avail) { | |
428 | /* | |
429 | * Limit the amount of clean up work we do at a time to keep | |
430 | * the Tx lock hold time O(1). | |
431 | */ | |
432 | if (avail > MAX_TX_RECLAIM) | |
433 | avail = MAX_TX_RECLAIM; | |
434 | ||
435 | free_tx_desc(adap, q, avail, unmap); | |
436 | q->in_use -= avail; | |
437 | } | |
438 | } | |
439 | ||
52367a76 VP |
440 | static inline int get_buf_size(struct adapter *adapter, |
441 | const struct rx_sw_desc *d) | |
fd3a4790 | 442 | { |
52367a76 VP |
443 | struct sge *s = &adapter->sge; |
444 | unsigned int rx_buf_size_idx = d->dma_addr & RX_BUF_SIZE; | |
445 | int buf_size; | |
446 | ||
447 | switch (rx_buf_size_idx) { | |
448 | case RX_SMALL_PG_BUF: | |
449 | buf_size = PAGE_SIZE; | |
450 | break; | |
451 | ||
452 | case RX_LARGE_PG_BUF: | |
453 | buf_size = PAGE_SIZE << s->fl_pg_order; | |
454 | break; | |
455 | ||
456 | case RX_SMALL_MTU_BUF: | |
457 | buf_size = FL_MTU_SMALL_BUFSIZE(adapter); | |
458 | break; | |
459 | ||
460 | case RX_LARGE_MTU_BUF: | |
461 | buf_size = FL_MTU_LARGE_BUFSIZE(adapter); | |
462 | break; | |
463 | ||
464 | default: | |
465 | BUG_ON(1); | |
466 | } | |
467 | ||
468 | return buf_size; | |
fd3a4790 DM |
469 | } |
470 | ||
471 | /** | |
472 | * free_rx_bufs - free the Rx buffers on an SGE free list | |
473 | * @adap: the adapter | |
474 | * @q: the SGE free list to free buffers from | |
475 | * @n: how many buffers to free | |
476 | * | |
477 | * Release the next @n buffers on an SGE free-buffer Rx queue. The | |
478 | * buffers must be made inaccessible to HW before calling this function. | |
479 | */ | |
480 | static void free_rx_bufs(struct adapter *adap, struct sge_fl *q, int n) | |
481 | { | |
482 | while (n--) { | |
483 | struct rx_sw_desc *d = &q->sdesc[q->cidx]; | |
484 | ||
485 | if (is_buf_mapped(d)) | |
486 | dma_unmap_page(adap->pdev_dev, get_buf_addr(d), | |
52367a76 VP |
487 | get_buf_size(adap, d), |
488 | PCI_DMA_FROMDEVICE); | |
fd3a4790 DM |
489 | put_page(d->page); |
490 | d->page = NULL; | |
491 | if (++q->cidx == q->size) | |
492 | q->cidx = 0; | |
493 | q->avail--; | |
494 | } | |
495 | } | |
496 | ||
497 | /** | |
498 | * unmap_rx_buf - unmap the current Rx buffer on an SGE free list | |
499 | * @adap: the adapter | |
500 | * @q: the SGE free list | |
501 | * | |
502 | * Unmap the current buffer on an SGE free-buffer Rx queue. The | |
503 | * buffer must be made inaccessible to HW before calling this function. | |
504 | * | |
505 | * This is similar to @free_rx_bufs above but does not free the buffer. | |
506 | * Do note that the FL still loses any further access to the buffer. | |
507 | */ | |
508 | static void unmap_rx_buf(struct adapter *adap, struct sge_fl *q) | |
509 | { | |
510 | struct rx_sw_desc *d = &q->sdesc[q->cidx]; | |
511 | ||
512 | if (is_buf_mapped(d)) | |
513 | dma_unmap_page(adap->pdev_dev, get_buf_addr(d), | |
52367a76 | 514 | get_buf_size(adap, d), PCI_DMA_FROMDEVICE); |
fd3a4790 DM |
515 | d->page = NULL; |
516 | if (++q->cidx == q->size) | |
517 | q->cidx = 0; | |
518 | q->avail--; | |
519 | } | |
520 | ||
521 | static inline void ring_fl_db(struct adapter *adap, struct sge_fl *q) | |
522 | { | |
0a57a536 | 523 | u32 val; |
fd3a4790 | 524 | if (q->pend_cred >= 8) { |
f612b815 HS |
525 | if (is_t4(adap->params.chip)) |
526 | val = PIDX_V(q->pend_cred / 8); | |
527 | else | |
528 | val = PIDX_T5_V(q->pend_cred / 8) | | |
529 | DBTYPE_F; | |
530 | val |= DBPRIO_F; | |
fd3a4790 | 531 | wmb(); |
d63a6dcf | 532 | |
df64e4d3 HS |
533 | /* If we don't have access to the new User Doorbell (T5+), use |
534 | * the old doorbell mechanism; otherwise use the new BAR2 | |
535 | * mechanism. | |
d63a6dcf | 536 | */ |
df64e4d3 | 537 | if (unlikely(q->bar2_addr == NULL)) { |
f612b815 HS |
538 | t4_write_reg(adap, MYPF_REG(SGE_PF_KDOORBELL_A), |
539 | val | QID_V(q->cntxt_id)); | |
d63a6dcf | 540 | } else { |
f612b815 | 541 | writel(val | QID_V(q->bar2_qid), |
df64e4d3 | 542 | q->bar2_addr + SGE_UDB_KDOORBELL); |
d63a6dcf HS |
543 | |
544 | /* This Write memory Barrier will force the write to | |
545 | * the User Doorbell area to be flushed. | |
546 | */ | |
547 | wmb(); | |
548 | } | |
fd3a4790 DM |
549 | q->pend_cred &= 7; |
550 | } | |
551 | } | |
552 | ||
553 | static inline void set_rx_sw_desc(struct rx_sw_desc *sd, struct page *pg, | |
554 | dma_addr_t mapping) | |
555 | { | |
556 | sd->page = pg; | |
557 | sd->dma_addr = mapping; /* includes size low bits */ | |
558 | } | |
559 | ||
560 | /** | |
561 | * refill_fl - refill an SGE Rx buffer ring | |
562 | * @adap: the adapter | |
563 | * @q: the ring to refill | |
564 | * @n: the number of new buffers to allocate | |
565 | * @gfp: the gfp flags for the allocations | |
566 | * | |
567 | * (Re)populate an SGE free-buffer queue with up to @n new packet buffers, | |
568 | * allocated with the supplied gfp flags. The caller must assure that | |
569 | * @n does not exceed the queue's capacity. If afterwards the queue is | |
570 | * found critically low mark it as starving in the bitmap of starving FLs. | |
571 | * | |
572 | * Returns the number of buffers allocated. | |
573 | */ | |
574 | static unsigned int refill_fl(struct adapter *adap, struct sge_fl *q, int n, | |
575 | gfp_t gfp) | |
576 | { | |
52367a76 | 577 | struct sge *s = &adap->sge; |
fd3a4790 DM |
578 | struct page *pg; |
579 | dma_addr_t mapping; | |
580 | unsigned int cred = q->avail; | |
581 | __be64 *d = &q->desc[q->pidx]; | |
582 | struct rx_sw_desc *sd = &q->sdesc[q->pidx]; | |
583 | ||
aa9cd31c | 584 | gfp |= __GFP_NOWARN; |
fd3a4790 | 585 | |
52367a76 VP |
586 | if (s->fl_pg_order == 0) |
587 | goto alloc_small_pages; | |
588 | ||
fd3a4790 DM |
589 | /* |
590 | * Prefer large buffers | |
591 | */ | |
592 | while (n) { | |
aa9cd31c | 593 | pg = __dev_alloc_pages(gfp, s->fl_pg_order); |
fd3a4790 DM |
594 | if (unlikely(!pg)) { |
595 | q->large_alloc_failed++; | |
596 | break; /* fall back to single pages */ | |
597 | } | |
598 | ||
599 | mapping = dma_map_page(adap->pdev_dev, pg, 0, | |
52367a76 | 600 | PAGE_SIZE << s->fl_pg_order, |
fd3a4790 DM |
601 | PCI_DMA_FROMDEVICE); |
602 | if (unlikely(dma_mapping_error(adap->pdev_dev, mapping))) { | |
52367a76 | 603 | __free_pages(pg, s->fl_pg_order); |
fd3a4790 DM |
604 | goto out; /* do not try small pages for this error */ |
605 | } | |
52367a76 | 606 | mapping |= RX_LARGE_PG_BUF; |
fd3a4790 DM |
607 | *d++ = cpu_to_be64(mapping); |
608 | ||
609 | set_rx_sw_desc(sd, pg, mapping); | |
610 | sd++; | |
611 | ||
612 | q->avail++; | |
613 | if (++q->pidx == q->size) { | |
614 | q->pidx = 0; | |
615 | sd = q->sdesc; | |
616 | d = q->desc; | |
617 | } | |
618 | n--; | |
619 | } | |
fd3a4790 | 620 | |
52367a76 | 621 | alloc_small_pages: |
fd3a4790 | 622 | while (n--) { |
aa9cd31c | 623 | pg = __dev_alloc_page(gfp); |
fd3a4790 DM |
624 | if (unlikely(!pg)) { |
625 | q->alloc_failed++; | |
626 | break; | |
627 | } | |
628 | ||
629 | mapping = dma_map_page(adap->pdev_dev, pg, 0, PAGE_SIZE, | |
630 | PCI_DMA_FROMDEVICE); | |
631 | if (unlikely(dma_mapping_error(adap->pdev_dev, mapping))) { | |
1f2149c1 | 632 | put_page(pg); |
fd3a4790 DM |
633 | goto out; |
634 | } | |
635 | *d++ = cpu_to_be64(mapping); | |
636 | ||
637 | set_rx_sw_desc(sd, pg, mapping); | |
638 | sd++; | |
639 | ||
640 | q->avail++; | |
641 | if (++q->pidx == q->size) { | |
642 | q->pidx = 0; | |
643 | sd = q->sdesc; | |
644 | d = q->desc; | |
645 | } | |
646 | } | |
647 | ||
648 | out: cred = q->avail - cred; | |
649 | q->pend_cred += cred; | |
650 | ring_fl_db(adap, q); | |
651 | ||
652 | if (unlikely(fl_starving(q))) { | |
653 | smp_wmb(); | |
e46dab4d DM |
654 | set_bit(q->cntxt_id - adap->sge.egr_start, |
655 | adap->sge.starving_fl); | |
fd3a4790 DM |
656 | } |
657 | ||
658 | return cred; | |
659 | } | |
660 | ||
661 | static inline void __refill_fl(struct adapter *adap, struct sge_fl *fl) | |
662 | { | |
663 | refill_fl(adap, fl, min(MAX_RX_REFILL, fl_cap(fl) - fl->avail), | |
664 | GFP_ATOMIC); | |
665 | } | |
666 | ||
667 | /** | |
668 | * alloc_ring - allocate resources for an SGE descriptor ring | |
669 | * @dev: the PCI device's core device | |
670 | * @nelem: the number of descriptors | |
671 | * @elem_size: the size of each descriptor | |
672 | * @sw_size: the size of the SW state associated with each ring element | |
673 | * @phys: the physical address of the allocated ring | |
674 | * @metadata: address of the array holding the SW state for the ring | |
675 | * @stat_size: extra space in HW ring for status information | |
ad6bad3e | 676 | * @node: preferred node for memory allocations |
fd3a4790 DM |
677 | * |
678 | * Allocates resources for an SGE descriptor ring, such as Tx queues, | |
679 | * free buffer lists, or response queues. Each SGE ring requires | |
680 | * space for its HW descriptors plus, optionally, space for the SW state | |
681 | * associated with each HW entry (the metadata). The function returns | |
682 | * three values: the virtual address for the HW ring (the return value | |
683 | * of the function), the bus address of the HW ring, and the address | |
684 | * of the SW ring. | |
685 | */ | |
686 | static void *alloc_ring(struct device *dev, size_t nelem, size_t elem_size, | |
687 | size_t sw_size, dma_addr_t *phys, void *metadata, | |
ad6bad3e | 688 | size_t stat_size, int node) |
fd3a4790 DM |
689 | { |
690 | size_t len = nelem * elem_size + stat_size; | |
691 | void *s = NULL; | |
692 | void *p = dma_alloc_coherent(dev, len, phys, GFP_KERNEL); | |
693 | ||
694 | if (!p) | |
695 | return NULL; | |
696 | if (sw_size) { | |
ad6bad3e | 697 | s = kzalloc_node(nelem * sw_size, GFP_KERNEL, node); |
fd3a4790 DM |
698 | |
699 | if (!s) { | |
700 | dma_free_coherent(dev, len, p, *phys); | |
701 | return NULL; | |
702 | } | |
703 | } | |
704 | if (metadata) | |
705 | *(void **)metadata = s; | |
706 | memset(p, 0, len); | |
707 | return p; | |
708 | } | |
709 | ||
710 | /** | |
711 | * sgl_len - calculates the size of an SGL of the given capacity | |
712 | * @n: the number of SGL entries | |
713 | * | |
714 | * Calculates the number of flits needed for a scatter/gather list that | |
715 | * can hold the given number of entries. | |
716 | */ | |
717 | static inline unsigned int sgl_len(unsigned int n) | |
718 | { | |
719 | n--; | |
720 | return (3 * n) / 2 + (n & 1) + 2; | |
721 | } | |
722 | ||
723 | /** | |
724 | * flits_to_desc - returns the num of Tx descriptors for the given flits | |
725 | * @n: the number of flits | |
726 | * | |
727 | * Returns the number of Tx descriptors needed for the supplied number | |
728 | * of flits. | |
729 | */ | |
730 | static inline unsigned int flits_to_desc(unsigned int n) | |
731 | { | |
732 | BUG_ON(n > SGE_MAX_WR_LEN / 8); | |
733 | return DIV_ROUND_UP(n, 8); | |
734 | } | |
735 | ||
736 | /** | |
737 | * is_eth_imm - can an Ethernet packet be sent as immediate data? | |
738 | * @skb: the packet | |
739 | * | |
740 | * Returns whether an Ethernet packet is small enough to fit as | |
0034b298 | 741 | * immediate data. Return value corresponds to headroom required. |
fd3a4790 DM |
742 | */ |
743 | static inline int is_eth_imm(const struct sk_buff *skb) | |
744 | { | |
0034b298 KS |
745 | int hdrlen = skb_shinfo(skb)->gso_size ? |
746 | sizeof(struct cpl_tx_pkt_lso_core) : 0; | |
747 | ||
748 | hdrlen += sizeof(struct cpl_tx_pkt); | |
749 | if (skb->len <= MAX_IMM_TX_PKT_LEN - hdrlen) | |
750 | return hdrlen; | |
751 | return 0; | |
fd3a4790 DM |
752 | } |
753 | ||
754 | /** | |
755 | * calc_tx_flits - calculate the number of flits for a packet Tx WR | |
756 | * @skb: the packet | |
757 | * | |
758 | * Returns the number of flits needed for a Tx WR for the given Ethernet | |
759 | * packet, including the needed WR and CPL headers. | |
760 | */ | |
761 | static inline unsigned int calc_tx_flits(const struct sk_buff *skb) | |
762 | { | |
763 | unsigned int flits; | |
0034b298 | 764 | int hdrlen = is_eth_imm(skb); |
fd3a4790 | 765 | |
0034b298 KS |
766 | if (hdrlen) |
767 | return DIV_ROUND_UP(skb->len + hdrlen, sizeof(__be64)); | |
fd3a4790 DM |
768 | |
769 | flits = sgl_len(skb_shinfo(skb)->nr_frags + 1) + 4; | |
770 | if (skb_shinfo(skb)->gso_size) | |
771 | flits += 2; | |
772 | return flits; | |
773 | } | |
774 | ||
775 | /** | |
776 | * calc_tx_descs - calculate the number of Tx descriptors for a packet | |
777 | * @skb: the packet | |
778 | * | |
779 | * Returns the number of Tx descriptors needed for the given Ethernet | |
780 | * packet, including the needed WR and CPL headers. | |
781 | */ | |
782 | static inline unsigned int calc_tx_descs(const struct sk_buff *skb) | |
783 | { | |
784 | return flits_to_desc(calc_tx_flits(skb)); | |
785 | } | |
786 | ||
787 | /** | |
788 | * write_sgl - populate a scatter/gather list for a packet | |
789 | * @skb: the packet | |
790 | * @q: the Tx queue we are writing into | |
791 | * @sgl: starting location for writing the SGL | |
792 | * @end: points right after the end of the SGL | |
793 | * @start: start offset into skb main-body data to include in the SGL | |
794 | * @addr: the list of bus addresses for the SGL elements | |
795 | * | |
796 | * Generates a gather list for the buffers that make up a packet. | |
797 | * The caller must provide adequate space for the SGL that will be written. | |
798 | * The SGL includes all of the packet's page fragments and the data in its | |
799 | * main body except for the first @start bytes. @sgl must be 16-byte | |
800 | * aligned and within a Tx descriptor with available space. @end points | |
801 | * right after the end of the SGL but does not account for any potential | |
802 | * wrap around, i.e., @end > @sgl. | |
803 | */ | |
804 | static void write_sgl(const struct sk_buff *skb, struct sge_txq *q, | |
805 | struct ulptx_sgl *sgl, u64 *end, unsigned int start, | |
806 | const dma_addr_t *addr) | |
807 | { | |
808 | unsigned int i, len; | |
809 | struct ulptx_sge_pair *to; | |
810 | const struct skb_shared_info *si = skb_shinfo(skb); | |
811 | unsigned int nfrags = si->nr_frags; | |
812 | struct ulptx_sge_pair buf[MAX_SKB_FRAGS / 2 + 1]; | |
813 | ||
814 | len = skb_headlen(skb) - start; | |
815 | if (likely(len)) { | |
816 | sgl->len0 = htonl(len); | |
817 | sgl->addr0 = cpu_to_be64(addr[0] + start); | |
818 | nfrags++; | |
819 | } else { | |
9e903e08 | 820 | sgl->len0 = htonl(skb_frag_size(&si->frags[0])); |
fd3a4790 DM |
821 | sgl->addr0 = cpu_to_be64(addr[1]); |
822 | } | |
823 | ||
d7990b0c | 824 | sgl->cmd_nsge = htonl(ULPTX_CMD_V(ULP_TX_SC_DSGL) | ULPTX_NSGE(nfrags)); |
fd3a4790 DM |
825 | if (likely(--nfrags == 0)) |
826 | return; | |
827 | /* | |
828 | * Most of the complexity below deals with the possibility we hit the | |
829 | * end of the queue in the middle of writing the SGL. For this case | |
830 | * only we create the SGL in a temporary buffer and then copy it. | |
831 | */ | |
832 | to = (u8 *)end > (u8 *)q->stat ? buf : sgl->sge; | |
833 | ||
834 | for (i = (nfrags != si->nr_frags); nfrags >= 2; nfrags -= 2, to++) { | |
9e903e08 ED |
835 | to->len[0] = cpu_to_be32(skb_frag_size(&si->frags[i])); |
836 | to->len[1] = cpu_to_be32(skb_frag_size(&si->frags[++i])); | |
fd3a4790 DM |
837 | to->addr[0] = cpu_to_be64(addr[i]); |
838 | to->addr[1] = cpu_to_be64(addr[++i]); | |
839 | } | |
840 | if (nfrags) { | |
9e903e08 | 841 | to->len[0] = cpu_to_be32(skb_frag_size(&si->frags[i])); |
fd3a4790 DM |
842 | to->len[1] = cpu_to_be32(0); |
843 | to->addr[0] = cpu_to_be64(addr[i + 1]); | |
844 | } | |
845 | if (unlikely((u8 *)end > (u8 *)q->stat)) { | |
846 | unsigned int part0 = (u8 *)q->stat - (u8 *)sgl->sge, part1; | |
847 | ||
848 | if (likely(part0)) | |
849 | memcpy(sgl->sge, buf, part0); | |
850 | part1 = (u8 *)end - (u8 *)q->stat; | |
851 | memcpy(q->desc, (u8 *)buf + part0, part1); | |
852 | end = (void *)q->desc + part1; | |
853 | } | |
854 | if ((uintptr_t)end & 8) /* 0-pad to multiple of 16 */ | |
64699336 | 855 | *end = 0; |
fd3a4790 DM |
856 | } |
857 | ||
df64e4d3 HS |
858 | /* This function copies 64 byte coalesced work request to |
859 | * memory mapped BAR2 space. For coalesced WR SGE fetches | |
860 | * data from the FIFO instead of from Host. | |
22adfe0a | 861 | */ |
df64e4d3 | 862 | static void cxgb_pio_copy(u64 __iomem *dst, u64 *src) |
22adfe0a | 863 | { |
df64e4d3 | 864 | int count = 8; |
22adfe0a SR |
865 | |
866 | while (count) { | |
867 | writeq(*src, dst); | |
868 | src++; | |
869 | dst++; | |
870 | count--; | |
871 | } | |
872 | } | |
873 | ||
fd3a4790 DM |
874 | /** |
875 | * ring_tx_db - check and potentially ring a Tx queue's doorbell | |
876 | * @adap: the adapter | |
877 | * @q: the Tx queue | |
878 | * @n: number of new descriptors to give to HW | |
879 | * | |
880 | * Ring the doorbel for a Tx queue. | |
881 | */ | |
882 | static inline void ring_tx_db(struct adapter *adap, struct sge_txq *q, int n) | |
883 | { | |
884 | wmb(); /* write descriptors before telling HW */ | |
d63a6dcf | 885 | |
df64e4d3 HS |
886 | /* If we don't have access to the new User Doorbell (T5+), use the old |
887 | * doorbell mechanism; otherwise use the new BAR2 mechanism. | |
888 | */ | |
889 | if (unlikely(q->bar2_addr == NULL)) { | |
f612b815 | 890 | u32 val = PIDX_V(n); |
d63a6dcf HS |
891 | unsigned long flags; |
892 | ||
893 | /* For T4 we need to participate in the Doorbell Recovery | |
894 | * mechanism. | |
895 | */ | |
896 | spin_lock_irqsave(&q->db_lock, flags); | |
897 | if (!q->db_disabled) | |
f612b815 HS |
898 | t4_write_reg(adap, MYPF_REG(SGE_PF_KDOORBELL_A), |
899 | QID_V(q->cntxt_id) | val); | |
d63a6dcf HS |
900 | else |
901 | q->db_pidx_inc += n; | |
902 | q->db_pidx = q->pidx; | |
903 | spin_unlock_irqrestore(&q->db_lock, flags); | |
904 | } else { | |
f612b815 | 905 | u32 val = PIDX_T5_V(n); |
d63a6dcf HS |
906 | |
907 | /* T4 and later chips share the same PIDX field offset within | |
908 | * the doorbell, but T5 and later shrank the field in order to | |
909 | * gain a bit for Doorbell Priority. The field was absurdly | |
910 | * large in the first place (14 bits) so we just use the T5 | |
911 | * and later limits and warn if a Queue ID is too large. | |
912 | */ | |
f612b815 | 913 | WARN_ON(val & DBPRIO_F); |
d63a6dcf | 914 | |
df64e4d3 HS |
915 | /* If we're only writing a single TX Descriptor and we can use |
916 | * Inferred QID registers, we can use the Write Combining | |
917 | * Gather Buffer; otherwise we use the simple doorbell. | |
d63a6dcf | 918 | */ |
df64e4d3 | 919 | if (n == 1 && q->bar2_qid == 0) { |
d63a6dcf HS |
920 | int index = (q->pidx |
921 | ? (q->pidx - 1) | |
922 | : (q->size - 1)); | |
df64e4d3 | 923 | u64 *wr = (u64 *)&q->desc[index]; |
d63a6dcf | 924 | |
df64e4d3 HS |
925 | cxgb_pio_copy((u64 __iomem *) |
926 | (q->bar2_addr + SGE_UDB_WCDOORBELL), | |
927 | wr); | |
22adfe0a | 928 | } else { |
f612b815 | 929 | writel(val | QID_V(q->bar2_qid), |
df64e4d3 | 930 | q->bar2_addr + SGE_UDB_KDOORBELL); |
22adfe0a | 931 | } |
d63a6dcf HS |
932 | |
933 | /* This Write Memory Barrier will force the write to the User | |
934 | * Doorbell area to be flushed. This is needed to prevent | |
935 | * writes on different CPUs for the same queue from hitting | |
936 | * the adapter out of order. This is required when some Work | |
937 | * Requests take the Write Combine Gather Buffer path (user | |
938 | * doorbell area offset [SGE_UDB_WCDOORBELL..+63]) and some | |
939 | * take the traditional path where we simply increment the | |
940 | * PIDX (User Doorbell area SGE_UDB_KDOORBELL) and have the | |
941 | * hardware DMA read the actual Work Request. | |
942 | */ | |
943 | wmb(); | |
944 | } | |
fd3a4790 DM |
945 | } |
946 | ||
947 | /** | |
948 | * inline_tx_skb - inline a packet's data into Tx descriptors | |
949 | * @skb: the packet | |
950 | * @q: the Tx queue where the packet will be inlined | |
951 | * @pos: starting position in the Tx queue where to inline the packet | |
952 | * | |
953 | * Inline a packet's contents directly into Tx descriptors, starting at | |
954 | * the given position within the Tx DMA ring. | |
955 | * Most of the complexity of this operation is dealing with wrap arounds | |
956 | * in the middle of the packet we want to inline. | |
957 | */ | |
958 | static void inline_tx_skb(const struct sk_buff *skb, const struct sge_txq *q, | |
959 | void *pos) | |
960 | { | |
961 | u64 *p; | |
962 | int left = (void *)q->stat - pos; | |
963 | ||
964 | if (likely(skb->len <= left)) { | |
965 | if (likely(!skb->data_len)) | |
966 | skb_copy_from_linear_data(skb, pos, skb->len); | |
967 | else | |
968 | skb_copy_bits(skb, 0, pos, skb->len); | |
969 | pos += skb->len; | |
970 | } else { | |
971 | skb_copy_bits(skb, 0, pos, left); | |
972 | skb_copy_bits(skb, left, q->desc, skb->len - left); | |
973 | pos = (void *)q->desc + (skb->len - left); | |
974 | } | |
975 | ||
976 | /* 0-pad to multiple of 16 */ | |
977 | p = PTR_ALIGN(pos, 8); | |
978 | if ((uintptr_t)p & 8) | |
979 | *p = 0; | |
980 | } | |
981 | ||
982 | /* | |
983 | * Figure out what HW csum a packet wants and return the appropriate control | |
984 | * bits. | |
985 | */ | |
986 | static u64 hwcsum(const struct sk_buff *skb) | |
987 | { | |
988 | int csum_type; | |
989 | const struct iphdr *iph = ip_hdr(skb); | |
990 | ||
991 | if (iph->version == 4) { | |
992 | if (iph->protocol == IPPROTO_TCP) | |
993 | csum_type = TX_CSUM_TCPIP; | |
994 | else if (iph->protocol == IPPROTO_UDP) | |
995 | csum_type = TX_CSUM_UDPIP; | |
996 | else { | |
997 | nocsum: /* | |
998 | * unknown protocol, disable HW csum | |
999 | * and hope a bad packet is detected | |
1000 | */ | |
1001 | return TXPKT_L4CSUM_DIS; | |
1002 | } | |
1003 | } else { | |
1004 | /* | |
1005 | * this doesn't work with extension headers | |
1006 | */ | |
1007 | const struct ipv6hdr *ip6h = (const struct ipv6hdr *)iph; | |
1008 | ||
1009 | if (ip6h->nexthdr == IPPROTO_TCP) | |
1010 | csum_type = TX_CSUM_TCPIP6; | |
1011 | else if (ip6h->nexthdr == IPPROTO_UDP) | |
1012 | csum_type = TX_CSUM_UDPIP6; | |
1013 | else | |
1014 | goto nocsum; | |
1015 | } | |
1016 | ||
1017 | if (likely(csum_type >= TX_CSUM_TCPIP)) | |
1018 | return TXPKT_CSUM_TYPE(csum_type) | | |
1019 | TXPKT_IPHDR_LEN(skb_network_header_len(skb)) | | |
1020 | TXPKT_ETHHDR_LEN(skb_network_offset(skb) - ETH_HLEN); | |
1021 | else { | |
1022 | int start = skb_transport_offset(skb); | |
1023 | ||
1024 | return TXPKT_CSUM_TYPE(csum_type) | TXPKT_CSUM_START(start) | | |
1025 | TXPKT_CSUM_LOC(start + skb->csum_offset); | |
1026 | } | |
1027 | } | |
1028 | ||
1029 | static void eth_txq_stop(struct sge_eth_txq *q) | |
1030 | { | |
1031 | netif_tx_stop_queue(q->txq); | |
1032 | q->q.stops++; | |
1033 | } | |
1034 | ||
1035 | static inline void txq_advance(struct sge_txq *q, unsigned int n) | |
1036 | { | |
1037 | q->in_use += n; | |
1038 | q->pidx += n; | |
1039 | if (q->pidx >= q->size) | |
1040 | q->pidx -= q->size; | |
1041 | } | |
1042 | ||
1043 | /** | |
1044 | * t4_eth_xmit - add a packet to an Ethernet Tx queue | |
1045 | * @skb: the packet | |
1046 | * @dev: the egress net device | |
1047 | * | |
1048 | * Add a packet to an SGE Ethernet Tx queue. Runs with softirqs disabled. | |
1049 | */ | |
1050 | netdev_tx_t t4_eth_xmit(struct sk_buff *skb, struct net_device *dev) | |
1051 | { | |
0034b298 | 1052 | int len; |
fd3a4790 DM |
1053 | u32 wr_mid; |
1054 | u64 cntrl, *end; | |
1055 | int qidx, credits; | |
1056 | unsigned int flits, ndesc; | |
1057 | struct adapter *adap; | |
1058 | struct sge_eth_txq *q; | |
1059 | const struct port_info *pi; | |
1060 | struct fw_eth_tx_pkt_wr *wr; | |
1061 | struct cpl_tx_pkt_core *cpl; | |
1062 | const struct skb_shared_info *ssi; | |
1063 | dma_addr_t addr[MAX_SKB_FRAGS + 1]; | |
0034b298 | 1064 | bool immediate = false; |
fd3a4790 DM |
1065 | |
1066 | /* | |
1067 | * The chip min packet length is 10 octets but play safe and reject | |
1068 | * anything shorter than an Ethernet header. | |
1069 | */ | |
1070 | if (unlikely(skb->len < ETH_HLEN)) { | |
a7525198 | 1071 | out_free: dev_kfree_skb_any(skb); |
fd3a4790 DM |
1072 | return NETDEV_TX_OK; |
1073 | } | |
1074 | ||
1075 | pi = netdev_priv(dev); | |
1076 | adap = pi->adapter; | |
1077 | qidx = skb_get_queue_mapping(skb); | |
1078 | q = &adap->sge.ethtxq[qidx + pi->first_qset]; | |
1079 | ||
1080 | reclaim_completed_tx(adap, &q->q, true); | |
1081 | ||
1082 | flits = calc_tx_flits(skb); | |
1083 | ndesc = flits_to_desc(flits); | |
1084 | credits = txq_avail(&q->q) - ndesc; | |
1085 | ||
1086 | if (unlikely(credits < 0)) { | |
1087 | eth_txq_stop(q); | |
1088 | dev_err(adap->pdev_dev, | |
1089 | "%s: Tx ring %u full while queue awake!\n", | |
1090 | dev->name, qidx); | |
1091 | return NETDEV_TX_BUSY; | |
1092 | } | |
1093 | ||
0034b298 KS |
1094 | if (is_eth_imm(skb)) |
1095 | immediate = true; | |
1096 | ||
1097 | if (!immediate && | |
fd3a4790 DM |
1098 | unlikely(map_skb(adap->pdev_dev, skb, addr) < 0)) { |
1099 | q->mapping_err++; | |
1100 | goto out_free; | |
1101 | } | |
1102 | ||
e2ac9628 | 1103 | wr_mid = FW_WR_LEN16_V(DIV_ROUND_UP(flits, 2)); |
fd3a4790 DM |
1104 | if (unlikely(credits < ETHTXQ_STOP_THRES)) { |
1105 | eth_txq_stop(q); | |
e2ac9628 | 1106 | wr_mid |= FW_WR_EQUEQ_F | FW_WR_EQUIQ_F; |
fd3a4790 DM |
1107 | } |
1108 | ||
1109 | wr = (void *)&q->q.desc[q->q.pidx]; | |
1110 | wr->equiq_to_len16 = htonl(wr_mid); | |
1111 | wr->r3 = cpu_to_be64(0); | |
1112 | end = (u64 *)wr + flits; | |
1113 | ||
0034b298 | 1114 | len = immediate ? skb->len : 0; |
fd3a4790 DM |
1115 | ssi = skb_shinfo(skb); |
1116 | if (ssi->gso_size) { | |
625ac6ae | 1117 | struct cpl_tx_pkt_lso *lso = (void *)wr; |
fd3a4790 DM |
1118 | bool v6 = (ssi->gso_type & SKB_GSO_TCPV6) != 0; |
1119 | int l3hdr_len = skb_network_header_len(skb); | |
1120 | int eth_xtra_len = skb_network_offset(skb) - ETH_HLEN; | |
1121 | ||
0034b298 | 1122 | len += sizeof(*lso); |
e2ac9628 HS |
1123 | wr->op_immdlen = htonl(FW_WR_OP_V(FW_ETH_TX_PKT_WR) | |
1124 | FW_WR_IMMDLEN_V(len)); | |
625ac6ae DM |
1125 | lso->c.lso_ctrl = htonl(LSO_OPCODE(CPL_TX_PKT_LSO) | |
1126 | LSO_FIRST_SLICE | LSO_LAST_SLICE | | |
1127 | LSO_IPV6(v6) | | |
1128 | LSO_ETHHDR_LEN(eth_xtra_len / 4) | | |
1129 | LSO_IPHDR_LEN(l3hdr_len / 4) | | |
1130 | LSO_TCPHDR_LEN(tcp_hdr(skb)->doff)); | |
1131 | lso->c.ipid_ofst = htons(0); | |
1132 | lso->c.mss = htons(ssi->gso_size); | |
1133 | lso->c.seqno_offset = htonl(0); | |
7207c0d1 HS |
1134 | if (is_t4(adap->params.chip)) |
1135 | lso->c.len = htonl(skb->len); | |
1136 | else | |
1137 | lso->c.len = htonl(LSO_T5_XFER_SIZE(skb->len)); | |
fd3a4790 DM |
1138 | cpl = (void *)(lso + 1); |
1139 | cntrl = TXPKT_CSUM_TYPE(v6 ? TX_CSUM_TCPIP6 : TX_CSUM_TCPIP) | | |
1140 | TXPKT_IPHDR_LEN(l3hdr_len) | | |
1141 | TXPKT_ETHHDR_LEN(eth_xtra_len); | |
1142 | q->tso++; | |
1143 | q->tx_cso += ssi->gso_segs; | |
1144 | } else { | |
ca71de6b | 1145 | len += sizeof(*cpl); |
e2ac9628 HS |
1146 | wr->op_immdlen = htonl(FW_WR_OP_V(FW_ETH_TX_PKT_WR) | |
1147 | FW_WR_IMMDLEN_V(len)); | |
fd3a4790 DM |
1148 | cpl = (void *)(wr + 1); |
1149 | if (skb->ip_summed == CHECKSUM_PARTIAL) { | |
1150 | cntrl = hwcsum(skb) | TXPKT_IPCSUM_DIS; | |
1151 | q->tx_cso++; | |
1152 | } else | |
1153 | cntrl = TXPKT_L4CSUM_DIS | TXPKT_IPCSUM_DIS; | |
1154 | } | |
1155 | ||
1156 | if (vlan_tx_tag_present(skb)) { | |
1157 | q->vlan_ins++; | |
1158 | cntrl |= TXPKT_VLAN_VLD | TXPKT_VLAN(vlan_tx_tag_get(skb)); | |
1159 | } | |
1160 | ||
1161 | cpl->ctrl0 = htonl(TXPKT_OPCODE(CPL_TX_PKT_XT) | | |
1707aec9 | 1162 | TXPKT_INTF(pi->tx_chan) | TXPKT_PF(adap->fn)); |
fd3a4790 DM |
1163 | cpl->pack = htons(0); |
1164 | cpl->len = htons(skb->len); | |
1165 | cpl->ctrl1 = cpu_to_be64(cntrl); | |
1166 | ||
0034b298 | 1167 | if (immediate) { |
fd3a4790 | 1168 | inline_tx_skb(skb, &q->q, cpl + 1); |
a7525198 | 1169 | dev_consume_skb_any(skb); |
fd3a4790 DM |
1170 | } else { |
1171 | int last_desc; | |
1172 | ||
1173 | write_sgl(skb, &q->q, (struct ulptx_sgl *)(cpl + 1), end, 0, | |
1174 | addr); | |
1175 | skb_orphan(skb); | |
1176 | ||
1177 | last_desc = q->q.pidx + ndesc - 1; | |
1178 | if (last_desc >= q->q.size) | |
1179 | last_desc -= q->q.size; | |
1180 | q->q.sdesc[last_desc].skb = skb; | |
1181 | q->q.sdesc[last_desc].sgl = (struct ulptx_sgl *)(cpl + 1); | |
1182 | } | |
1183 | ||
1184 | txq_advance(&q->q, ndesc); | |
1185 | ||
1186 | ring_tx_db(adap, &q->q, ndesc); | |
1187 | return NETDEV_TX_OK; | |
1188 | } | |
1189 | ||
1190 | /** | |
1191 | * reclaim_completed_tx_imm - reclaim completed control-queue Tx descs | |
1192 | * @q: the SGE control Tx queue | |
1193 | * | |
1194 | * This is a variant of reclaim_completed_tx() that is used for Tx queues | |
1195 | * that send only immediate data (presently just the control queues) and | |
1196 | * thus do not have any sk_buffs to release. | |
1197 | */ | |
1198 | static inline void reclaim_completed_tx_imm(struct sge_txq *q) | |
1199 | { | |
1200 | int hw_cidx = ntohs(q->stat->cidx); | |
1201 | int reclaim = hw_cidx - q->cidx; | |
1202 | ||
1203 | if (reclaim < 0) | |
1204 | reclaim += q->size; | |
1205 | ||
1206 | q->in_use -= reclaim; | |
1207 | q->cidx = hw_cidx; | |
1208 | } | |
1209 | ||
1210 | /** | |
1211 | * is_imm - check whether a packet can be sent as immediate data | |
1212 | * @skb: the packet | |
1213 | * | |
1214 | * Returns true if a packet can be sent as a WR with immediate data. | |
1215 | */ | |
1216 | static inline int is_imm(const struct sk_buff *skb) | |
1217 | { | |
1218 | return skb->len <= MAX_CTRL_WR_LEN; | |
1219 | } | |
1220 | ||
1221 | /** | |
1222 | * ctrlq_check_stop - check if a control queue is full and should stop | |
1223 | * @q: the queue | |
1224 | * @wr: most recent WR written to the queue | |
1225 | * | |
1226 | * Check if a control queue has become full and should be stopped. | |
1227 | * We clean up control queue descriptors very lazily, only when we are out. | |
1228 | * If the queue is still full after reclaiming any completed descriptors | |
1229 | * we suspend it and have the last WR wake it up. | |
1230 | */ | |
1231 | static void ctrlq_check_stop(struct sge_ctrl_txq *q, struct fw_wr_hdr *wr) | |
1232 | { | |
1233 | reclaim_completed_tx_imm(&q->q); | |
1234 | if (unlikely(txq_avail(&q->q) < TXQ_STOP_THRES)) { | |
e2ac9628 | 1235 | wr->lo |= htonl(FW_WR_EQUEQ_F | FW_WR_EQUIQ_F); |
fd3a4790 DM |
1236 | q->q.stops++; |
1237 | q->full = 1; | |
1238 | } | |
1239 | } | |
1240 | ||
1241 | /** | |
1242 | * ctrl_xmit - send a packet through an SGE control Tx queue | |
1243 | * @q: the control queue | |
1244 | * @skb: the packet | |
1245 | * | |
1246 | * Send a packet through an SGE control Tx queue. Packets sent through | |
1247 | * a control queue must fit entirely as immediate data. | |
1248 | */ | |
1249 | static int ctrl_xmit(struct sge_ctrl_txq *q, struct sk_buff *skb) | |
1250 | { | |
1251 | unsigned int ndesc; | |
1252 | struct fw_wr_hdr *wr; | |
1253 | ||
1254 | if (unlikely(!is_imm(skb))) { | |
1255 | WARN_ON(1); | |
1256 | dev_kfree_skb(skb); | |
1257 | return NET_XMIT_DROP; | |
1258 | } | |
1259 | ||
1260 | ndesc = DIV_ROUND_UP(skb->len, sizeof(struct tx_desc)); | |
1261 | spin_lock(&q->sendq.lock); | |
1262 | ||
1263 | if (unlikely(q->full)) { | |
1264 | skb->priority = ndesc; /* save for restart */ | |
1265 | __skb_queue_tail(&q->sendq, skb); | |
1266 | spin_unlock(&q->sendq.lock); | |
1267 | return NET_XMIT_CN; | |
1268 | } | |
1269 | ||
1270 | wr = (struct fw_wr_hdr *)&q->q.desc[q->q.pidx]; | |
1271 | inline_tx_skb(skb, &q->q, wr); | |
1272 | ||
1273 | txq_advance(&q->q, ndesc); | |
1274 | if (unlikely(txq_avail(&q->q) < TXQ_STOP_THRES)) | |
1275 | ctrlq_check_stop(q, wr); | |
1276 | ||
1277 | ring_tx_db(q->adap, &q->q, ndesc); | |
1278 | spin_unlock(&q->sendq.lock); | |
1279 | ||
1280 | kfree_skb(skb); | |
1281 | return NET_XMIT_SUCCESS; | |
1282 | } | |
1283 | ||
1284 | /** | |
1285 | * restart_ctrlq - restart a suspended control queue | |
1286 | * @data: the control queue to restart | |
1287 | * | |
1288 | * Resumes transmission on a suspended Tx control queue. | |
1289 | */ | |
1290 | static void restart_ctrlq(unsigned long data) | |
1291 | { | |
1292 | struct sk_buff *skb; | |
1293 | unsigned int written = 0; | |
1294 | struct sge_ctrl_txq *q = (struct sge_ctrl_txq *)data; | |
1295 | ||
1296 | spin_lock(&q->sendq.lock); | |
1297 | reclaim_completed_tx_imm(&q->q); | |
1298 | BUG_ON(txq_avail(&q->q) < TXQ_STOP_THRES); /* q should be empty */ | |
1299 | ||
1300 | while ((skb = __skb_dequeue(&q->sendq)) != NULL) { | |
1301 | struct fw_wr_hdr *wr; | |
1302 | unsigned int ndesc = skb->priority; /* previously saved */ | |
1303 | ||
1304 | /* | |
1305 | * Write descriptors and free skbs outside the lock to limit | |
1306 | * wait times. q->full is still set so new skbs will be queued. | |
1307 | */ | |
1308 | spin_unlock(&q->sendq.lock); | |
1309 | ||
1310 | wr = (struct fw_wr_hdr *)&q->q.desc[q->q.pidx]; | |
1311 | inline_tx_skb(skb, &q->q, wr); | |
1312 | kfree_skb(skb); | |
1313 | ||
1314 | written += ndesc; | |
1315 | txq_advance(&q->q, ndesc); | |
1316 | if (unlikely(txq_avail(&q->q) < TXQ_STOP_THRES)) { | |
1317 | unsigned long old = q->q.stops; | |
1318 | ||
1319 | ctrlq_check_stop(q, wr); | |
1320 | if (q->q.stops != old) { /* suspended anew */ | |
1321 | spin_lock(&q->sendq.lock); | |
1322 | goto ringdb; | |
1323 | } | |
1324 | } | |
1325 | if (written > 16) { | |
1326 | ring_tx_db(q->adap, &q->q, written); | |
1327 | written = 0; | |
1328 | } | |
1329 | spin_lock(&q->sendq.lock); | |
1330 | } | |
1331 | q->full = 0; | |
1332 | ringdb: if (written) | |
1333 | ring_tx_db(q->adap, &q->q, written); | |
1334 | spin_unlock(&q->sendq.lock); | |
1335 | } | |
1336 | ||
1337 | /** | |
1338 | * t4_mgmt_tx - send a management message | |
1339 | * @adap: the adapter | |
1340 | * @skb: the packet containing the management message | |
1341 | * | |
1342 | * Send a management message through control queue 0. | |
1343 | */ | |
1344 | int t4_mgmt_tx(struct adapter *adap, struct sk_buff *skb) | |
1345 | { | |
1346 | int ret; | |
1347 | ||
1348 | local_bh_disable(); | |
1349 | ret = ctrl_xmit(&adap->sge.ctrlq[0], skb); | |
1350 | local_bh_enable(); | |
1351 | return ret; | |
1352 | } | |
1353 | ||
1354 | /** | |
1355 | * is_ofld_imm - check whether a packet can be sent as immediate data | |
1356 | * @skb: the packet | |
1357 | * | |
1358 | * Returns true if a packet can be sent as an offload WR with immediate | |
1359 | * data. We currently use the same limit as for Ethernet packets. | |
1360 | */ | |
1361 | static inline int is_ofld_imm(const struct sk_buff *skb) | |
1362 | { | |
1363 | return skb->len <= MAX_IMM_TX_PKT_LEN; | |
1364 | } | |
1365 | ||
1366 | /** | |
1367 | * calc_tx_flits_ofld - calculate # of flits for an offload packet | |
1368 | * @skb: the packet | |
1369 | * | |
1370 | * Returns the number of flits needed for the given offload packet. | |
1371 | * These packets are already fully constructed and no additional headers | |
1372 | * will be added. | |
1373 | */ | |
1374 | static inline unsigned int calc_tx_flits_ofld(const struct sk_buff *skb) | |
1375 | { | |
1376 | unsigned int flits, cnt; | |
1377 | ||
1378 | if (is_ofld_imm(skb)) | |
1379 | return DIV_ROUND_UP(skb->len, 8); | |
1380 | ||
1381 | flits = skb_transport_offset(skb) / 8U; /* headers */ | |
1382 | cnt = skb_shinfo(skb)->nr_frags; | |
15dd16c2 | 1383 | if (skb_tail_pointer(skb) != skb_transport_header(skb)) |
fd3a4790 DM |
1384 | cnt++; |
1385 | return flits + sgl_len(cnt); | |
1386 | } | |
1387 | ||
1388 | /** | |
1389 | * txq_stop_maperr - stop a Tx queue due to I/O MMU exhaustion | |
1390 | * @adap: the adapter | |
1391 | * @q: the queue to stop | |
1392 | * | |
1393 | * Mark a Tx queue stopped due to I/O MMU exhaustion and resulting | |
1394 | * inability to map packets. A periodic timer attempts to restart | |
1395 | * queues so marked. | |
1396 | */ | |
1397 | static void txq_stop_maperr(struct sge_ofld_txq *q) | |
1398 | { | |
1399 | q->mapping_err++; | |
1400 | q->q.stops++; | |
e46dab4d DM |
1401 | set_bit(q->q.cntxt_id - q->adap->sge.egr_start, |
1402 | q->adap->sge.txq_maperr); | |
fd3a4790 DM |
1403 | } |
1404 | ||
1405 | /** | |
1406 | * ofldtxq_stop - stop an offload Tx queue that has become full | |
1407 | * @q: the queue to stop | |
1408 | * @skb: the packet causing the queue to become full | |
1409 | * | |
1410 | * Stops an offload Tx queue that has become full and modifies the packet | |
1411 | * being written to request a wakeup. | |
1412 | */ | |
1413 | static void ofldtxq_stop(struct sge_ofld_txq *q, struct sk_buff *skb) | |
1414 | { | |
1415 | struct fw_wr_hdr *wr = (struct fw_wr_hdr *)skb->data; | |
1416 | ||
e2ac9628 | 1417 | wr->lo |= htonl(FW_WR_EQUEQ_F | FW_WR_EQUIQ_F); |
fd3a4790 DM |
1418 | q->q.stops++; |
1419 | q->full = 1; | |
1420 | } | |
1421 | ||
1422 | /** | |
1423 | * service_ofldq - restart a suspended offload queue | |
1424 | * @q: the offload queue | |
1425 | * | |
1426 | * Services an offload Tx queue by moving packets from its packet queue | |
1427 | * to the HW Tx ring. The function starts and ends with the queue locked. | |
1428 | */ | |
1429 | static void service_ofldq(struct sge_ofld_txq *q) | |
1430 | { | |
1431 | u64 *pos; | |
1432 | int credits; | |
1433 | struct sk_buff *skb; | |
1434 | unsigned int written = 0; | |
1435 | unsigned int flits, ndesc; | |
1436 | ||
1437 | while ((skb = skb_peek(&q->sendq)) != NULL && !q->full) { | |
1438 | /* | |
1439 | * We drop the lock but leave skb on sendq, thus retaining | |
1440 | * exclusive access to the state of the queue. | |
1441 | */ | |
1442 | spin_unlock(&q->sendq.lock); | |
1443 | ||
1444 | reclaim_completed_tx(q->adap, &q->q, false); | |
1445 | ||
1446 | flits = skb->priority; /* previously saved */ | |
1447 | ndesc = flits_to_desc(flits); | |
1448 | credits = txq_avail(&q->q) - ndesc; | |
1449 | BUG_ON(credits < 0); | |
1450 | if (unlikely(credits < TXQ_STOP_THRES)) | |
1451 | ofldtxq_stop(q, skb); | |
1452 | ||
1453 | pos = (u64 *)&q->q.desc[q->q.pidx]; | |
1454 | if (is_ofld_imm(skb)) | |
1455 | inline_tx_skb(skb, &q->q, pos); | |
1456 | else if (map_skb(q->adap->pdev_dev, skb, | |
1457 | (dma_addr_t *)skb->head)) { | |
1458 | txq_stop_maperr(q); | |
1459 | spin_lock(&q->sendq.lock); | |
1460 | break; | |
1461 | } else { | |
1462 | int last_desc, hdr_len = skb_transport_offset(skb); | |
1463 | ||
1464 | memcpy(pos, skb->data, hdr_len); | |
1465 | write_sgl(skb, &q->q, (void *)pos + hdr_len, | |
1466 | pos + flits, hdr_len, | |
1467 | (dma_addr_t *)skb->head); | |
1468 | #ifdef CONFIG_NEED_DMA_MAP_STATE | |
1469 | skb->dev = q->adap->port[0]; | |
1470 | skb->destructor = deferred_unmap_destructor; | |
1471 | #endif | |
1472 | last_desc = q->q.pidx + ndesc - 1; | |
1473 | if (last_desc >= q->q.size) | |
1474 | last_desc -= q->q.size; | |
1475 | q->q.sdesc[last_desc].skb = skb; | |
1476 | } | |
1477 | ||
1478 | txq_advance(&q->q, ndesc); | |
1479 | written += ndesc; | |
1480 | if (unlikely(written > 32)) { | |
1481 | ring_tx_db(q->adap, &q->q, written); | |
1482 | written = 0; | |
1483 | } | |
1484 | ||
1485 | spin_lock(&q->sendq.lock); | |
1486 | __skb_unlink(skb, &q->sendq); | |
1487 | if (is_ofld_imm(skb)) | |
1488 | kfree_skb(skb); | |
1489 | } | |
1490 | if (likely(written)) | |
1491 | ring_tx_db(q->adap, &q->q, written); | |
1492 | } | |
1493 | ||
1494 | /** | |
1495 | * ofld_xmit - send a packet through an offload queue | |
1496 | * @q: the Tx offload queue | |
1497 | * @skb: the packet | |
1498 | * | |
1499 | * Send an offload packet through an SGE offload queue. | |
1500 | */ | |
1501 | static int ofld_xmit(struct sge_ofld_txq *q, struct sk_buff *skb) | |
1502 | { | |
1503 | skb->priority = calc_tx_flits_ofld(skb); /* save for restart */ | |
1504 | spin_lock(&q->sendq.lock); | |
1505 | __skb_queue_tail(&q->sendq, skb); | |
1506 | if (q->sendq.qlen == 1) | |
1507 | service_ofldq(q); | |
1508 | spin_unlock(&q->sendq.lock); | |
1509 | return NET_XMIT_SUCCESS; | |
1510 | } | |
1511 | ||
1512 | /** | |
1513 | * restart_ofldq - restart a suspended offload queue | |
1514 | * @data: the offload queue to restart | |
1515 | * | |
1516 | * Resumes transmission on a suspended Tx offload queue. | |
1517 | */ | |
1518 | static void restart_ofldq(unsigned long data) | |
1519 | { | |
1520 | struct sge_ofld_txq *q = (struct sge_ofld_txq *)data; | |
1521 | ||
1522 | spin_lock(&q->sendq.lock); | |
1523 | q->full = 0; /* the queue actually is completely empty now */ | |
1524 | service_ofldq(q); | |
1525 | spin_unlock(&q->sendq.lock); | |
1526 | } | |
1527 | ||
1528 | /** | |
1529 | * skb_txq - return the Tx queue an offload packet should use | |
1530 | * @skb: the packet | |
1531 | * | |
1532 | * Returns the Tx queue an offload packet should use as indicated by bits | |
1533 | * 1-15 in the packet's queue_mapping. | |
1534 | */ | |
1535 | static inline unsigned int skb_txq(const struct sk_buff *skb) | |
1536 | { | |
1537 | return skb->queue_mapping >> 1; | |
1538 | } | |
1539 | ||
1540 | /** | |
1541 | * is_ctrl_pkt - return whether an offload packet is a control packet | |
1542 | * @skb: the packet | |
1543 | * | |
1544 | * Returns whether an offload packet should use an OFLD or a CTRL | |
1545 | * Tx queue as indicated by bit 0 in the packet's queue_mapping. | |
1546 | */ | |
1547 | static inline unsigned int is_ctrl_pkt(const struct sk_buff *skb) | |
1548 | { | |
1549 | return skb->queue_mapping & 1; | |
1550 | } | |
1551 | ||
1552 | static inline int ofld_send(struct adapter *adap, struct sk_buff *skb) | |
1553 | { | |
1554 | unsigned int idx = skb_txq(skb); | |
1555 | ||
4fe44dd7 KS |
1556 | if (unlikely(is_ctrl_pkt(skb))) { |
1557 | /* Single ctrl queue is a requirement for LE workaround path */ | |
1558 | if (adap->tids.nsftids) | |
1559 | idx = 0; | |
fd3a4790 | 1560 | return ctrl_xmit(&adap->sge.ctrlq[idx], skb); |
4fe44dd7 | 1561 | } |
fd3a4790 DM |
1562 | return ofld_xmit(&adap->sge.ofldtxq[idx], skb); |
1563 | } | |
1564 | ||
1565 | /** | |
1566 | * t4_ofld_send - send an offload packet | |
1567 | * @adap: the adapter | |
1568 | * @skb: the packet | |
1569 | * | |
1570 | * Sends an offload packet. We use the packet queue_mapping to select the | |
1571 | * appropriate Tx queue as follows: bit 0 indicates whether the packet | |
1572 | * should be sent as regular or control, bits 1-15 select the queue. | |
1573 | */ | |
1574 | int t4_ofld_send(struct adapter *adap, struct sk_buff *skb) | |
1575 | { | |
1576 | int ret; | |
1577 | ||
1578 | local_bh_disable(); | |
1579 | ret = ofld_send(adap, skb); | |
1580 | local_bh_enable(); | |
1581 | return ret; | |
1582 | } | |
1583 | ||
1584 | /** | |
1585 | * cxgb4_ofld_send - send an offload packet | |
1586 | * @dev: the net device | |
1587 | * @skb: the packet | |
1588 | * | |
1589 | * Sends an offload packet. This is an exported version of @t4_ofld_send, | |
1590 | * intended for ULDs. | |
1591 | */ | |
1592 | int cxgb4_ofld_send(struct net_device *dev, struct sk_buff *skb) | |
1593 | { | |
1594 | return t4_ofld_send(netdev2adap(dev), skb); | |
1595 | } | |
1596 | EXPORT_SYMBOL(cxgb4_ofld_send); | |
1597 | ||
e91b0f24 | 1598 | static inline void copy_frags(struct sk_buff *skb, |
fd3a4790 DM |
1599 | const struct pkt_gl *gl, unsigned int offset) |
1600 | { | |
e91b0f24 | 1601 | int i; |
fd3a4790 DM |
1602 | |
1603 | /* usually there's just one frag */ | |
e91b0f24 IC |
1604 | __skb_fill_page_desc(skb, 0, gl->frags[0].page, |
1605 | gl->frags[0].offset + offset, | |
1606 | gl->frags[0].size - offset); | |
1607 | skb_shinfo(skb)->nr_frags = gl->nfrags; | |
1608 | for (i = 1; i < gl->nfrags; i++) | |
1609 | __skb_fill_page_desc(skb, i, gl->frags[i].page, | |
1610 | gl->frags[i].offset, | |
1611 | gl->frags[i].size); | |
fd3a4790 DM |
1612 | |
1613 | /* get a reference to the last page, we don't own it */ | |
e91b0f24 | 1614 | get_page(gl->frags[gl->nfrags - 1].page); |
fd3a4790 DM |
1615 | } |
1616 | ||
1617 | /** | |
1618 | * cxgb4_pktgl_to_skb - build an sk_buff from a packet gather list | |
1619 | * @gl: the gather list | |
1620 | * @skb_len: size of sk_buff main body if it carries fragments | |
1621 | * @pull_len: amount of data to move to the sk_buff's main body | |
1622 | * | |
1623 | * Builds an sk_buff from the given packet gather list. Returns the | |
1624 | * sk_buff or %NULL if sk_buff allocation failed. | |
1625 | */ | |
1626 | struct sk_buff *cxgb4_pktgl_to_skb(const struct pkt_gl *gl, | |
1627 | unsigned int skb_len, unsigned int pull_len) | |
1628 | { | |
1629 | struct sk_buff *skb; | |
1630 | ||
1631 | /* | |
1632 | * Below we rely on RX_COPY_THRES being less than the smallest Rx buffer | |
1633 | * size, which is expected since buffers are at least PAGE_SIZEd. | |
1634 | * In this case packets up to RX_COPY_THRES have only one fragment. | |
1635 | */ | |
1636 | if (gl->tot_len <= RX_COPY_THRES) { | |
1637 | skb = dev_alloc_skb(gl->tot_len); | |
1638 | if (unlikely(!skb)) | |
1639 | goto out; | |
1640 | __skb_put(skb, gl->tot_len); | |
1641 | skb_copy_to_linear_data(skb, gl->va, gl->tot_len); | |
1642 | } else { | |
1643 | skb = dev_alloc_skb(skb_len); | |
1644 | if (unlikely(!skb)) | |
1645 | goto out; | |
1646 | __skb_put(skb, pull_len); | |
1647 | skb_copy_to_linear_data(skb, gl->va, pull_len); | |
1648 | ||
e91b0f24 | 1649 | copy_frags(skb, gl, pull_len); |
fd3a4790 DM |
1650 | skb->len = gl->tot_len; |
1651 | skb->data_len = skb->len - pull_len; | |
1652 | skb->truesize += skb->data_len; | |
1653 | } | |
1654 | out: return skb; | |
1655 | } | |
1656 | EXPORT_SYMBOL(cxgb4_pktgl_to_skb); | |
1657 | ||
1658 | /** | |
1659 | * t4_pktgl_free - free a packet gather list | |
1660 | * @gl: the gather list | |
1661 | * | |
1662 | * Releases the pages of a packet gather list. We do not own the last | |
1663 | * page on the list and do not free it. | |
1664 | */ | |
de498c89 | 1665 | static void t4_pktgl_free(const struct pkt_gl *gl) |
fd3a4790 DM |
1666 | { |
1667 | int n; | |
e91b0f24 | 1668 | const struct page_frag *p; |
fd3a4790 DM |
1669 | |
1670 | for (p = gl->frags, n = gl->nfrags - 1; n--; p++) | |
1671 | put_page(p->page); | |
1672 | } | |
1673 | ||
1674 | /* | |
1675 | * Process an MPS trace packet. Give it an unused protocol number so it won't | |
1676 | * be delivered to anyone and send it to the stack for capture. | |
1677 | */ | |
1678 | static noinline int handle_trace_pkt(struct adapter *adap, | |
1679 | const struct pkt_gl *gl) | |
1680 | { | |
1681 | struct sk_buff *skb; | |
fd3a4790 DM |
1682 | |
1683 | skb = cxgb4_pktgl_to_skb(gl, RX_PULL_LEN, RX_PULL_LEN); | |
1684 | if (unlikely(!skb)) { | |
1685 | t4_pktgl_free(gl); | |
1686 | return 0; | |
1687 | } | |
1688 | ||
d14807dd | 1689 | if (is_t4(adap->params.chip)) |
0a57a536 SR |
1690 | __skb_pull(skb, sizeof(struct cpl_trace_pkt)); |
1691 | else | |
1692 | __skb_pull(skb, sizeof(struct cpl_t5_trace_pkt)); | |
1693 | ||
fd3a4790 DM |
1694 | skb_reset_mac_header(skb); |
1695 | skb->protocol = htons(0xffff); | |
1696 | skb->dev = adap->port[0]; | |
1697 | netif_receive_skb(skb); | |
1698 | return 0; | |
1699 | } | |
1700 | ||
1701 | static void do_gro(struct sge_eth_rxq *rxq, const struct pkt_gl *gl, | |
1702 | const struct cpl_rx_pkt *pkt) | |
1703 | { | |
52367a76 VP |
1704 | struct adapter *adapter = rxq->rspq.adap; |
1705 | struct sge *s = &adapter->sge; | |
fd3a4790 DM |
1706 | int ret; |
1707 | struct sk_buff *skb; | |
1708 | ||
1709 | skb = napi_get_frags(&rxq->rspq.napi); | |
1710 | if (unlikely(!skb)) { | |
1711 | t4_pktgl_free(gl); | |
1712 | rxq->stats.rx_drops++; | |
1713 | return; | |
1714 | } | |
1715 | ||
52367a76 VP |
1716 | copy_frags(skb, gl, s->pktshift); |
1717 | skb->len = gl->tot_len - s->pktshift; | |
fd3a4790 DM |
1718 | skb->data_len = skb->len; |
1719 | skb->truesize += skb->data_len; | |
1720 | skb->ip_summed = CHECKSUM_UNNECESSARY; | |
1721 | skb_record_rx_queue(skb, rxq->rspq.idx); | |
87b6cf51 | 1722 | if (rxq->rspq.netdev->features & NETIF_F_RXHASH) |
8264989c TH |
1723 | skb_set_hash(skb, (__force u32)pkt->rsshdr.hash_val, |
1724 | PKT_HASH_TYPE_L3); | |
fd3a4790 DM |
1725 | |
1726 | if (unlikely(pkt->vlan_ex)) { | |
86a9bad3 | 1727 | __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), ntohs(pkt->vlan)); |
fd3a4790 | 1728 | rxq->stats.vlan_ex++; |
fd3a4790 DM |
1729 | } |
1730 | ret = napi_gro_frags(&rxq->rspq.napi); | |
19ecae2c | 1731 | if (ret == GRO_HELD) |
fd3a4790 DM |
1732 | rxq->stats.lro_pkts++; |
1733 | else if (ret == GRO_MERGED || ret == GRO_MERGED_FREE) | |
1734 | rxq->stats.lro_merged++; | |
1735 | rxq->stats.pkts++; | |
1736 | rxq->stats.rx_cso++; | |
1737 | } | |
1738 | ||
1739 | /** | |
1740 | * t4_ethrx_handler - process an ingress ethernet packet | |
1741 | * @q: the response queue that received the packet | |
1742 | * @rsp: the response queue descriptor holding the RX_PKT message | |
1743 | * @si: the gather list of packet fragments | |
1744 | * | |
1745 | * Process an ingress ethernet packet and deliver it to the stack. | |
1746 | */ | |
1747 | int t4_ethrx_handler(struct sge_rspq *q, const __be64 *rsp, | |
1748 | const struct pkt_gl *si) | |
1749 | { | |
1750 | bool csum_ok; | |
1751 | struct sk_buff *skb; | |
fd3a4790 DM |
1752 | const struct cpl_rx_pkt *pkt; |
1753 | struct sge_eth_rxq *rxq = container_of(q, struct sge_eth_rxq, rspq); | |
52367a76 | 1754 | struct sge *s = &q->adap->sge; |
d14807dd | 1755 | int cpl_trace_pkt = is_t4(q->adap->params.chip) ? |
0a57a536 | 1756 | CPL_TRACE_PKT : CPL_TRACE_PKT_T5; |
fd3a4790 | 1757 | |
0a57a536 | 1758 | if (unlikely(*(u8 *)rsp == cpl_trace_pkt)) |
fd3a4790 DM |
1759 | return handle_trace_pkt(q->adap, si); |
1760 | ||
87b6cf51 | 1761 | pkt = (const struct cpl_rx_pkt *)rsp; |
cca2822d HS |
1762 | csum_ok = pkt->csum_calc && !pkt->err_vec && |
1763 | (q->netdev->features & NETIF_F_RXCSUM); | |
fd3a4790 DM |
1764 | if ((pkt->l2info & htonl(RXF_TCP)) && |
1765 | (q->netdev->features & NETIF_F_GRO) && csum_ok && !pkt->ip_frag) { | |
1766 | do_gro(rxq, si, pkt); | |
1767 | return 0; | |
1768 | } | |
1769 | ||
1770 | skb = cxgb4_pktgl_to_skb(si, RX_PKT_SKB_LEN, RX_PULL_LEN); | |
1771 | if (unlikely(!skb)) { | |
1772 | t4_pktgl_free(si); | |
1773 | rxq->stats.rx_drops++; | |
1774 | return 0; | |
1775 | } | |
1776 | ||
52367a76 | 1777 | __skb_pull(skb, s->pktshift); /* remove ethernet header padding */ |
fd3a4790 DM |
1778 | skb->protocol = eth_type_trans(skb, q->netdev); |
1779 | skb_record_rx_queue(skb, q->idx); | |
87b6cf51 | 1780 | if (skb->dev->features & NETIF_F_RXHASH) |
8264989c TH |
1781 | skb_set_hash(skb, (__force u32)pkt->rsshdr.hash_val, |
1782 | PKT_HASH_TYPE_L3); | |
87b6cf51 | 1783 | |
fd3a4790 DM |
1784 | rxq->stats.pkts++; |
1785 | ||
cca2822d | 1786 | if (csum_ok && (pkt->l2info & htonl(RXF_UDP | RXF_TCP))) { |
ba5d3c66 | 1787 | if (!pkt->ip_frag) { |
fd3a4790 | 1788 | skb->ip_summed = CHECKSUM_UNNECESSARY; |
ba5d3c66 DM |
1789 | rxq->stats.rx_cso++; |
1790 | } else if (pkt->l2info & htonl(RXF_IP)) { | |
fd3a4790 DM |
1791 | __sum16 c = (__force __sum16)pkt->csum; |
1792 | skb->csum = csum_unfold(c); | |
1793 | skb->ip_summed = CHECKSUM_COMPLETE; | |
ba5d3c66 | 1794 | rxq->stats.rx_cso++; |
fd3a4790 | 1795 | } |
fd3a4790 | 1796 | } else |
bc8acf2c | 1797 | skb_checksum_none_assert(skb); |
fd3a4790 DM |
1798 | |
1799 | if (unlikely(pkt->vlan_ex)) { | |
86a9bad3 | 1800 | __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), ntohs(pkt->vlan)); |
fd3a4790 | 1801 | rxq->stats.vlan_ex++; |
19ecae2c DM |
1802 | } |
1803 | netif_receive_skb(skb); | |
fd3a4790 DM |
1804 | return 0; |
1805 | } | |
1806 | ||
1807 | /** | |
1808 | * restore_rx_bufs - put back a packet's Rx buffers | |
1809 | * @si: the packet gather list | |
1810 | * @q: the SGE free list | |
1811 | * @frags: number of FL buffers to restore | |
1812 | * | |
1813 | * Puts back on an FL the Rx buffers associated with @si. The buffers | |
1814 | * have already been unmapped and are left unmapped, we mark them so to | |
1815 | * prevent further unmapping attempts. | |
1816 | * | |
1817 | * This function undoes a series of @unmap_rx_buf calls when we find out | |
1818 | * that the current packet can't be processed right away afterall and we | |
1819 | * need to come back to it later. This is a very rare event and there's | |
1820 | * no effort to make this particularly efficient. | |
1821 | */ | |
1822 | static void restore_rx_bufs(const struct pkt_gl *si, struct sge_fl *q, | |
1823 | int frags) | |
1824 | { | |
1825 | struct rx_sw_desc *d; | |
1826 | ||
1827 | while (frags--) { | |
1828 | if (q->cidx == 0) | |
1829 | q->cidx = q->size - 1; | |
1830 | else | |
1831 | q->cidx--; | |
1832 | d = &q->sdesc[q->cidx]; | |
1833 | d->page = si->frags[frags].page; | |
1834 | d->dma_addr |= RX_UNMAPPED_BUF; | |
1835 | q->avail++; | |
1836 | } | |
1837 | } | |
1838 | ||
1839 | /** | |
1840 | * is_new_response - check if a response is newly written | |
1841 | * @r: the response descriptor | |
1842 | * @q: the response queue | |
1843 | * | |
1844 | * Returns true if a response descriptor contains a yet unprocessed | |
1845 | * response. | |
1846 | */ | |
1847 | static inline bool is_new_response(const struct rsp_ctrl *r, | |
1848 | const struct sge_rspq *q) | |
1849 | { | |
1850 | return RSPD_GEN(r->type_gen) == q->gen; | |
1851 | } | |
1852 | ||
1853 | /** | |
1854 | * rspq_next - advance to the next entry in a response queue | |
1855 | * @q: the queue | |
1856 | * | |
1857 | * Updates the state of a response queue to advance it to the next entry. | |
1858 | */ | |
1859 | static inline void rspq_next(struct sge_rspq *q) | |
1860 | { | |
1861 | q->cur_desc = (void *)q->cur_desc + q->iqe_len; | |
1862 | if (unlikely(++q->cidx == q->size)) { | |
1863 | q->cidx = 0; | |
1864 | q->gen ^= 1; | |
1865 | q->cur_desc = q->desc; | |
1866 | } | |
1867 | } | |
1868 | ||
1869 | /** | |
1870 | * process_responses - process responses from an SGE response queue | |
1871 | * @q: the ingress queue to process | |
1872 | * @budget: how many responses can be processed in this round | |
1873 | * | |
1874 | * Process responses from an SGE response queue up to the supplied budget. | |
1875 | * Responses include received packets as well as control messages from FW | |
1876 | * or HW. | |
1877 | * | |
1878 | * Additionally choose the interrupt holdoff time for the next interrupt | |
1879 | * on this queue. If the system is under memory shortage use a fairly | |
1880 | * long delay to help recovery. | |
1881 | */ | |
1882 | static int process_responses(struct sge_rspq *q, int budget) | |
1883 | { | |
1884 | int ret, rsp_type; | |
1885 | int budget_left = budget; | |
1886 | const struct rsp_ctrl *rc; | |
1887 | struct sge_eth_rxq *rxq = container_of(q, struct sge_eth_rxq, rspq); | |
52367a76 VP |
1888 | struct adapter *adapter = q->adap; |
1889 | struct sge *s = &adapter->sge; | |
fd3a4790 DM |
1890 | |
1891 | while (likely(budget_left)) { | |
1892 | rc = (void *)q->cur_desc + (q->iqe_len - sizeof(*rc)); | |
1893 | if (!is_new_response(rc, q)) | |
1894 | break; | |
1895 | ||
1896 | rmb(); | |
1897 | rsp_type = RSPD_TYPE(rc->type_gen); | |
1898 | if (likely(rsp_type == RSP_TYPE_FLBUF)) { | |
e91b0f24 | 1899 | struct page_frag *fp; |
fd3a4790 DM |
1900 | struct pkt_gl si; |
1901 | const struct rx_sw_desc *rsd; | |
1902 | u32 len = ntohl(rc->pldbuflen_qid), bufsz, frags; | |
1903 | ||
1904 | if (len & RSPD_NEWBUF) { | |
1905 | if (likely(q->offset > 0)) { | |
1906 | free_rx_bufs(q->adap, &rxq->fl, 1); | |
1907 | q->offset = 0; | |
1908 | } | |
1704d748 | 1909 | len = RSPD_LEN(len); |
fd3a4790 DM |
1910 | } |
1911 | si.tot_len = len; | |
1912 | ||
1913 | /* gather packet fragments */ | |
1914 | for (frags = 0, fp = si.frags; ; frags++, fp++) { | |
1915 | rsd = &rxq->fl.sdesc[rxq->fl.cidx]; | |
52367a76 | 1916 | bufsz = get_buf_size(adapter, rsd); |
fd3a4790 | 1917 | fp->page = rsd->page; |
e91b0f24 IC |
1918 | fp->offset = q->offset; |
1919 | fp->size = min(bufsz, len); | |
1920 | len -= fp->size; | |
fd3a4790 DM |
1921 | if (!len) |
1922 | break; | |
1923 | unmap_rx_buf(q->adap, &rxq->fl); | |
1924 | } | |
1925 | ||
1926 | /* | |
1927 | * Last buffer remains mapped so explicitly make it | |
1928 | * coherent for CPU access. | |
1929 | */ | |
1930 | dma_sync_single_for_cpu(q->adap->pdev_dev, | |
1931 | get_buf_addr(rsd), | |
e91b0f24 | 1932 | fp->size, DMA_FROM_DEVICE); |
fd3a4790 DM |
1933 | |
1934 | si.va = page_address(si.frags[0].page) + | |
e91b0f24 | 1935 | si.frags[0].offset; |
fd3a4790 DM |
1936 | prefetch(si.va); |
1937 | ||
1938 | si.nfrags = frags + 1; | |
1939 | ret = q->handler(q, q->cur_desc, &si); | |
1940 | if (likely(ret == 0)) | |
52367a76 | 1941 | q->offset += ALIGN(fp->size, s->fl_align); |
fd3a4790 DM |
1942 | else |
1943 | restore_rx_bufs(&si, &rxq->fl, frags); | |
1944 | } else if (likely(rsp_type == RSP_TYPE_CPL)) { | |
1945 | ret = q->handler(q, q->cur_desc, NULL); | |
1946 | } else { | |
1947 | ret = q->handler(q, (const __be64 *)rc, CXGB4_MSG_AN); | |
1948 | } | |
1949 | ||
1950 | if (unlikely(ret)) { | |
1951 | /* couldn't process descriptor, back off for recovery */ | |
1952 | q->next_intr_params = QINTR_TIMER_IDX(NOMEM_TMR_IDX); | |
1953 | break; | |
1954 | } | |
1955 | ||
1956 | rspq_next(q); | |
1957 | budget_left--; | |
1958 | } | |
1959 | ||
1960 | if (q->offset >= 0 && rxq->fl.size - rxq->fl.avail >= 16) | |
1961 | __refill_fl(q->adap, &rxq->fl); | |
1962 | return budget - budget_left; | |
1963 | } | |
1964 | ||
1965 | /** | |
1966 | * napi_rx_handler - the NAPI handler for Rx processing | |
1967 | * @napi: the napi instance | |
1968 | * @budget: how many packets we can process in this round | |
1969 | * | |
1970 | * Handler for new data events when using NAPI. This does not need any | |
1971 | * locking or protection from interrupts as data interrupts are off at | |
1972 | * this point and other adapter interrupts do not interfere (the latter | |
1973 | * in not a concern at all with MSI-X as non-data interrupts then have | |
1974 | * a separate handler). | |
1975 | */ | |
1976 | static int napi_rx_handler(struct napi_struct *napi, int budget) | |
1977 | { | |
1978 | unsigned int params; | |
1979 | struct sge_rspq *q = container_of(napi, struct sge_rspq, napi); | |
1980 | int work_done = process_responses(q, budget); | |
d63a6dcf | 1981 | u32 val; |
fd3a4790 DM |
1982 | |
1983 | if (likely(work_done < budget)) { | |
e553ec3f HS |
1984 | int timer_index; |
1985 | ||
fd3a4790 | 1986 | napi_complete(napi); |
e553ec3f HS |
1987 | timer_index = QINTR_TIMER_IDX_GET(q->next_intr_params); |
1988 | ||
1989 | if (q->adaptive_rx) { | |
1990 | if (work_done > max(timer_pkt_quota[timer_index], | |
1991 | MIN_NAPI_WORK)) | |
1992 | timer_index = (timer_index + 1); | |
1993 | else | |
1994 | timer_index = timer_index - 1; | |
1995 | ||
1996 | timer_index = clamp(timer_index, 0, SGE_TIMERREGS - 1); | |
1997 | q->next_intr_params = QINTR_TIMER_IDX(timer_index) | | |
1998 | V_QINTR_CNT_EN; | |
1999 | params = q->next_intr_params; | |
2000 | } else { | |
2001 | params = q->next_intr_params; | |
2002 | q->next_intr_params = q->intr_params; | |
2003 | } | |
fd3a4790 DM |
2004 | } else |
2005 | params = QINTR_TIMER_IDX(7); | |
2006 | ||
f612b815 | 2007 | val = CIDXINC_V(work_done) | SEINTARM_V(params); |
df64e4d3 HS |
2008 | |
2009 | /* If we don't have access to the new User GTS (T5+), use the old | |
2010 | * doorbell mechanism; otherwise use the new BAR2 mechanism. | |
2011 | */ | |
2012 | if (unlikely(q->bar2_addr == NULL)) { | |
f612b815 HS |
2013 | t4_write_reg(q->adap, MYPF_REG(SGE_PF_GTS_A), |
2014 | val | INGRESSQID_V((u32)q->cntxt_id)); | |
d63a6dcf | 2015 | } else { |
f612b815 | 2016 | writel(val | INGRESSQID_V(q->bar2_qid), |
df64e4d3 | 2017 | q->bar2_addr + SGE_UDB_GTS); |
d63a6dcf HS |
2018 | wmb(); |
2019 | } | |
fd3a4790 DM |
2020 | return work_done; |
2021 | } | |
2022 | ||
2023 | /* | |
2024 | * The MSI-X interrupt handler for an SGE response queue. | |
2025 | */ | |
2026 | irqreturn_t t4_sge_intr_msix(int irq, void *cookie) | |
2027 | { | |
2028 | struct sge_rspq *q = cookie; | |
2029 | ||
2030 | napi_schedule(&q->napi); | |
2031 | return IRQ_HANDLED; | |
2032 | } | |
2033 | ||
2034 | /* | |
2035 | * Process the indirect interrupt entries in the interrupt queue and kick off | |
2036 | * NAPI for each queue that has generated an entry. | |
2037 | */ | |
2038 | static unsigned int process_intrq(struct adapter *adap) | |
2039 | { | |
2040 | unsigned int credits; | |
2041 | const struct rsp_ctrl *rc; | |
2042 | struct sge_rspq *q = &adap->sge.intrq; | |
d63a6dcf | 2043 | u32 val; |
fd3a4790 DM |
2044 | |
2045 | spin_lock(&adap->sge.intrq_lock); | |
2046 | for (credits = 0; ; credits++) { | |
2047 | rc = (void *)q->cur_desc + (q->iqe_len - sizeof(*rc)); | |
2048 | if (!is_new_response(rc, q)) | |
2049 | break; | |
2050 | ||
2051 | rmb(); | |
2052 | if (RSPD_TYPE(rc->type_gen) == RSP_TYPE_INTR) { | |
2053 | unsigned int qid = ntohl(rc->pldbuflen_qid); | |
2054 | ||
e46dab4d | 2055 | qid -= adap->sge.ingr_start; |
fd3a4790 DM |
2056 | napi_schedule(&adap->sge.ingr_map[qid]->napi); |
2057 | } | |
2058 | ||
2059 | rspq_next(q); | |
2060 | } | |
2061 | ||
f612b815 | 2062 | val = CIDXINC_V(credits) | SEINTARM_V(q->intr_params); |
df64e4d3 HS |
2063 | |
2064 | /* If we don't have access to the new User GTS (T5+), use the old | |
2065 | * doorbell mechanism; otherwise use the new BAR2 mechanism. | |
2066 | */ | |
2067 | if (unlikely(q->bar2_addr == NULL)) { | |
f612b815 HS |
2068 | t4_write_reg(adap, MYPF_REG(SGE_PF_GTS_A), |
2069 | val | INGRESSQID_V(q->cntxt_id)); | |
d63a6dcf | 2070 | } else { |
f612b815 | 2071 | writel(val | INGRESSQID_V(q->bar2_qid), |
df64e4d3 | 2072 | q->bar2_addr + SGE_UDB_GTS); |
d63a6dcf HS |
2073 | wmb(); |
2074 | } | |
fd3a4790 DM |
2075 | spin_unlock(&adap->sge.intrq_lock); |
2076 | return credits; | |
2077 | } | |
2078 | ||
2079 | /* | |
2080 | * The MSI interrupt handler, which handles data events from SGE response queues | |
2081 | * as well as error and other async events as they all use the same MSI vector. | |
2082 | */ | |
2083 | static irqreturn_t t4_intr_msi(int irq, void *cookie) | |
2084 | { | |
2085 | struct adapter *adap = cookie; | |
2086 | ||
2087 | t4_slow_intr_handler(adap); | |
2088 | process_intrq(adap); | |
2089 | return IRQ_HANDLED; | |
2090 | } | |
2091 | ||
2092 | /* | |
2093 | * Interrupt handler for legacy INTx interrupts. | |
2094 | * Handles data events from SGE response queues as well as error and other | |
2095 | * async events as they all use the same interrupt line. | |
2096 | */ | |
2097 | static irqreturn_t t4_intr_intx(int irq, void *cookie) | |
2098 | { | |
2099 | struct adapter *adap = cookie; | |
2100 | ||
2101 | t4_write_reg(adap, MYPF_REG(PCIE_PF_CLI), 0); | |
2102 | if (t4_slow_intr_handler(adap) | process_intrq(adap)) | |
2103 | return IRQ_HANDLED; | |
2104 | return IRQ_NONE; /* probably shared interrupt */ | |
2105 | } | |
2106 | ||
2107 | /** | |
2108 | * t4_intr_handler - select the top-level interrupt handler | |
2109 | * @adap: the adapter | |
2110 | * | |
2111 | * Selects the top-level interrupt handler based on the type of interrupts | |
2112 | * (MSI-X, MSI, or INTx). | |
2113 | */ | |
2114 | irq_handler_t t4_intr_handler(struct adapter *adap) | |
2115 | { | |
2116 | if (adap->flags & USING_MSIX) | |
2117 | return t4_sge_intr_msix; | |
2118 | if (adap->flags & USING_MSI) | |
2119 | return t4_intr_msi; | |
2120 | return t4_intr_intx; | |
2121 | } | |
2122 | ||
2123 | static void sge_rx_timer_cb(unsigned long data) | |
2124 | { | |
2125 | unsigned long m; | |
0f4d201f | 2126 | unsigned int i, idma_same_state_cnt[2]; |
fd3a4790 DM |
2127 | struct adapter *adap = (struct adapter *)data; |
2128 | struct sge *s = &adap->sge; | |
2129 | ||
2130 | for (i = 0; i < ARRAY_SIZE(s->starving_fl); i++) | |
2131 | for (m = s->starving_fl[i]; m; m &= m - 1) { | |
2132 | struct sge_eth_rxq *rxq; | |
2133 | unsigned int id = __ffs(m) + i * BITS_PER_LONG; | |
2134 | struct sge_fl *fl = s->egr_map[id]; | |
2135 | ||
2136 | clear_bit(id, s->starving_fl); | |
4e857c58 | 2137 | smp_mb__after_atomic(); |
fd3a4790 DM |
2138 | |
2139 | if (fl_starving(fl)) { | |
2140 | rxq = container_of(fl, struct sge_eth_rxq, fl); | |
2141 | if (napi_reschedule(&rxq->rspq.napi)) | |
2142 | fl->starving++; | |
2143 | else | |
2144 | set_bit(id, s->starving_fl); | |
2145 | } | |
2146 | } | |
2147 | ||
2148 | t4_write_reg(adap, SGE_DEBUG_INDEX, 13); | |
0f4d201f KS |
2149 | idma_same_state_cnt[0] = t4_read_reg(adap, SGE_DEBUG_DATA_HIGH); |
2150 | idma_same_state_cnt[1] = t4_read_reg(adap, SGE_DEBUG_DATA_LOW); | |
2151 | ||
2152 | for (i = 0; i < 2; i++) { | |
2153 | u32 debug0, debug11; | |
2154 | ||
2155 | /* If the Ingress DMA Same State Counter ("timer") is less | |
2156 | * than 1s, then we can reset our synthesized Stall Timer and | |
2157 | * continue. If we have previously emitted warnings about a | |
2158 | * potential stalled Ingress Queue, issue a note indicating | |
2159 | * that the Ingress Queue has resumed forward progress. | |
2160 | */ | |
2161 | if (idma_same_state_cnt[i] < s->idma_1s_thresh) { | |
2162 | if (s->idma_stalled[i] >= SGE_IDMA_WARN_THRESH) | |
2163 | CH_WARN(adap, "SGE idma%d, queue%u,resumed after %d sec\n", | |
2164 | i, s->idma_qid[i], | |
2165 | s->idma_stalled[i]/HZ); | |
2166 | s->idma_stalled[i] = 0; | |
2167 | continue; | |
2168 | } | |
2169 | ||
2170 | /* Synthesize an SGE Ingress DMA Same State Timer in the Hz | |
2171 | * domain. The first time we get here it'll be because we | |
2172 | * passed the 1s Threshold; each additional time it'll be | |
2173 | * because the RX Timer Callback is being fired on its regular | |
2174 | * schedule. | |
2175 | * | |
2176 | * If the stall is below our Potential Hung Ingress Queue | |
2177 | * Warning Threshold, continue. | |
2178 | */ | |
2179 | if (s->idma_stalled[i] == 0) | |
2180 | s->idma_stalled[i] = HZ; | |
2181 | else | |
2182 | s->idma_stalled[i] += RX_QCHECK_PERIOD; | |
2183 | ||
2184 | if (s->idma_stalled[i] < SGE_IDMA_WARN_THRESH) | |
2185 | continue; | |
2186 | ||
2187 | /* We'll issue a warning every SGE_IDMA_WARN_REPEAT Hz */ | |
2188 | if (((s->idma_stalled[i] - HZ) % SGE_IDMA_WARN_REPEAT) != 0) | |
2189 | continue; | |
2190 | ||
2191 | /* Read and save the SGE IDMA State and Queue ID information. | |
2192 | * We do this every time in case it changes across time ... | |
2193 | */ | |
2194 | t4_write_reg(adap, SGE_DEBUG_INDEX, 0); | |
2195 | debug0 = t4_read_reg(adap, SGE_DEBUG_DATA_LOW); | |
2196 | s->idma_state[i] = (debug0 >> (i * 9)) & 0x3f; | |
2197 | ||
2198 | t4_write_reg(adap, SGE_DEBUG_INDEX, 11); | |
2199 | debug11 = t4_read_reg(adap, SGE_DEBUG_DATA_LOW); | |
2200 | s->idma_qid[i] = (debug11 >> (i * 16)) & 0xffff; | |
2201 | ||
2202 | CH_WARN(adap, "SGE idma%u, queue%u, maybe stuck state%u %dsecs (debug0=%#x, debug11=%#x)\n", | |
2203 | i, s->idma_qid[i], s->idma_state[i], | |
2204 | s->idma_stalled[i]/HZ, debug0, debug11); | |
2205 | t4_sge_decode_idma_state(adap, s->idma_state[i]); | |
2206 | } | |
fd3a4790 DM |
2207 | |
2208 | mod_timer(&s->rx_timer, jiffies + RX_QCHECK_PERIOD); | |
2209 | } | |
2210 | ||
2211 | static void sge_tx_timer_cb(unsigned long data) | |
2212 | { | |
2213 | unsigned long m; | |
2214 | unsigned int i, budget; | |
2215 | struct adapter *adap = (struct adapter *)data; | |
2216 | struct sge *s = &adap->sge; | |
2217 | ||
2218 | for (i = 0; i < ARRAY_SIZE(s->txq_maperr); i++) | |
2219 | for (m = s->txq_maperr[i]; m; m &= m - 1) { | |
2220 | unsigned long id = __ffs(m) + i * BITS_PER_LONG; | |
2221 | struct sge_ofld_txq *txq = s->egr_map[id]; | |
2222 | ||
2223 | clear_bit(id, s->txq_maperr); | |
2224 | tasklet_schedule(&txq->qresume_tsk); | |
2225 | } | |
2226 | ||
2227 | budget = MAX_TIMER_TX_RECLAIM; | |
2228 | i = s->ethtxq_rover; | |
2229 | do { | |
2230 | struct sge_eth_txq *q = &s->ethtxq[i]; | |
2231 | ||
2232 | if (q->q.in_use && | |
2233 | time_after_eq(jiffies, q->txq->trans_start + HZ / 100) && | |
2234 | __netif_tx_trylock(q->txq)) { | |
2235 | int avail = reclaimable(&q->q); | |
2236 | ||
2237 | if (avail) { | |
2238 | if (avail > budget) | |
2239 | avail = budget; | |
2240 | ||
2241 | free_tx_desc(adap, &q->q, avail, true); | |
2242 | q->q.in_use -= avail; | |
2243 | budget -= avail; | |
2244 | } | |
2245 | __netif_tx_unlock(q->txq); | |
2246 | } | |
2247 | ||
2248 | if (++i >= s->ethqsets) | |
2249 | i = 0; | |
2250 | } while (budget && i != s->ethtxq_rover); | |
2251 | s->ethtxq_rover = i; | |
2252 | mod_timer(&s->tx_timer, jiffies + (budget ? TX_QCHECK_PERIOD : 2)); | |
2253 | } | |
2254 | ||
d63a6dcf | 2255 | /** |
df64e4d3 HS |
2256 | * bar2_address - return the BAR2 address for an SGE Queue's Registers |
2257 | * @adapter: the adapter | |
2258 | * @qid: the SGE Queue ID | |
2259 | * @qtype: the SGE Queue Type (Egress or Ingress) | |
2260 | * @pbar2_qid: BAR2 Queue ID or 0 for Queue ID inferred SGE Queues | |
d63a6dcf | 2261 | * |
df64e4d3 HS |
2262 | * Returns the BAR2 address for the SGE Queue Registers associated with |
2263 | * @qid. If BAR2 SGE Registers aren't available, returns NULL. Also | |
2264 | * returns the BAR2 Queue ID to be used with writes to the BAR2 SGE | |
2265 | * Queue Registers. If the BAR2 Queue ID is 0, then "Inferred Queue ID" | |
2266 | * Registers are supported (e.g. the Write Combining Doorbell Buffer). | |
2267 | */ | |
2268 | static void __iomem *bar2_address(struct adapter *adapter, | |
2269 | unsigned int qid, | |
2270 | enum t4_bar2_qtype qtype, | |
2271 | unsigned int *pbar2_qid) | |
2272 | { | |
2273 | u64 bar2_qoffset; | |
2274 | int ret; | |
d63a6dcf | 2275 | |
dd0bcc0b | 2276 | ret = cxgb4_t4_bar2_sge_qregs(adapter, qid, qtype, |
df64e4d3 HS |
2277 | &bar2_qoffset, pbar2_qid); |
2278 | if (ret) | |
2279 | return NULL; | |
d63a6dcf | 2280 | |
df64e4d3 | 2281 | return adapter->bar2 + bar2_qoffset; |
d63a6dcf HS |
2282 | } |
2283 | ||
fd3a4790 DM |
2284 | int t4_sge_alloc_rxq(struct adapter *adap, struct sge_rspq *iq, bool fwevtq, |
2285 | struct net_device *dev, int intr_idx, | |
2286 | struct sge_fl *fl, rspq_handler_t hnd) | |
2287 | { | |
2288 | int ret, flsz = 0; | |
2289 | struct fw_iq_cmd c; | |
52367a76 | 2290 | struct sge *s = &adap->sge; |
fd3a4790 DM |
2291 | struct port_info *pi = netdev_priv(dev); |
2292 | ||
2293 | /* Size needs to be multiple of 16, including status entry. */ | |
2294 | iq->size = roundup(iq->size, 16); | |
2295 | ||
2296 | iq->desc = alloc_ring(adap->pdev_dev, iq->size, iq->iqe_len, 0, | |
ad6bad3e | 2297 | &iq->phys_addr, NULL, 0, NUMA_NO_NODE); |
fd3a4790 DM |
2298 | if (!iq->desc) |
2299 | return -ENOMEM; | |
2300 | ||
2301 | memset(&c, 0, sizeof(c)); | |
e2ac9628 HS |
2302 | c.op_to_vfn = htonl(FW_CMD_OP_V(FW_IQ_CMD) | FW_CMD_REQUEST_F | |
2303 | FW_CMD_WRITE_F | FW_CMD_EXEC_F | | |
6e4b51a6 HS |
2304 | FW_IQ_CMD_PFN_V(adap->fn) | FW_IQ_CMD_VFN_V(0)); |
2305 | c.alloc_to_len16 = htonl(FW_IQ_CMD_ALLOC_F | FW_IQ_CMD_IQSTART_F | | |
fd3a4790 | 2306 | FW_LEN16(c)); |
6e4b51a6 HS |
2307 | c.type_to_iqandstindex = htonl(FW_IQ_CMD_TYPE_V(FW_IQ_TYPE_FL_INT_CAP) | |
2308 | FW_IQ_CMD_IQASYNCH_V(fwevtq) | FW_IQ_CMD_VIID_V(pi->viid) | | |
2309 | FW_IQ_CMD_IQANDST_V(intr_idx < 0) | FW_IQ_CMD_IQANUD_V(1) | | |
2310 | FW_IQ_CMD_IQANDSTINDEX_V(intr_idx >= 0 ? intr_idx : | |
fd3a4790 | 2311 | -intr_idx - 1)); |
6e4b51a6 HS |
2312 | c.iqdroprss_to_iqesize = htons(FW_IQ_CMD_IQPCIECH_V(pi->tx_chan) | |
2313 | FW_IQ_CMD_IQGTSMODE_F | | |
2314 | FW_IQ_CMD_IQINTCNTTHRESH_V(iq->pktcnt_idx) | | |
2315 | FW_IQ_CMD_IQESIZE_V(ilog2(iq->iqe_len) - 4)); | |
fd3a4790 DM |
2316 | c.iqsize = htons(iq->size); |
2317 | c.iqaddr = cpu_to_be64(iq->phys_addr); | |
2318 | ||
2319 | if (fl) { | |
2320 | fl->size = roundup(fl->size, 8); | |
2321 | fl->desc = alloc_ring(adap->pdev_dev, fl->size, sizeof(__be64), | |
2322 | sizeof(struct rx_sw_desc), &fl->addr, | |
52367a76 | 2323 | &fl->sdesc, s->stat_len, NUMA_NO_NODE); |
fd3a4790 DM |
2324 | if (!fl->desc) |
2325 | goto fl_nomem; | |
2326 | ||
52367a76 | 2327 | flsz = fl->size / 8 + s->stat_len / sizeof(struct tx_desc); |
6e4b51a6 HS |
2328 | c.iqns_to_fl0congen = htonl(FW_IQ_CMD_FL0PACKEN_F | |
2329 | FW_IQ_CMD_FL0FETCHRO_F | | |
2330 | FW_IQ_CMD_FL0DATARO_F | | |
2331 | FW_IQ_CMD_FL0PADEN_F); | |
2332 | c.fl0dcaen_to_fl0cidxfthresh = htons(FW_IQ_CMD_FL0FBMIN_V(2) | | |
2333 | FW_IQ_CMD_FL0FBMAX_V(3)); | |
fd3a4790 DM |
2334 | c.fl0size = htons(flsz); |
2335 | c.fl0addr = cpu_to_be64(fl->addr); | |
2336 | } | |
2337 | ||
060e0c75 | 2338 | ret = t4_wr_mbox(adap, adap->fn, &c, sizeof(c), &c); |
fd3a4790 DM |
2339 | if (ret) |
2340 | goto err; | |
2341 | ||
2342 | netif_napi_add(dev, &iq->napi, napi_rx_handler, 64); | |
2343 | iq->cur_desc = iq->desc; | |
2344 | iq->cidx = 0; | |
2345 | iq->gen = 1; | |
2346 | iq->next_intr_params = iq->intr_params; | |
2347 | iq->cntxt_id = ntohs(c.iqid); | |
2348 | iq->abs_id = ntohs(c.physiqid); | |
df64e4d3 HS |
2349 | iq->bar2_addr = bar2_address(adap, |
2350 | iq->cntxt_id, | |
2351 | T4_BAR2_QTYPE_INGRESS, | |
2352 | &iq->bar2_qid); | |
fd3a4790 | 2353 | iq->size--; /* subtract status entry */ |
fd3a4790 DM |
2354 | iq->netdev = dev; |
2355 | iq->handler = hnd; | |
2356 | ||
2357 | /* set offset to -1 to distinguish ingress queues without FL */ | |
2358 | iq->offset = fl ? 0 : -1; | |
2359 | ||
e46dab4d | 2360 | adap->sge.ingr_map[iq->cntxt_id - adap->sge.ingr_start] = iq; |
fd3a4790 DM |
2361 | |
2362 | if (fl) { | |
62718b32 | 2363 | fl->cntxt_id = ntohs(c.fl0id); |
fd3a4790 DM |
2364 | fl->avail = fl->pend_cred = 0; |
2365 | fl->pidx = fl->cidx = 0; | |
2366 | fl->alloc_failed = fl->large_alloc_failed = fl->starving = 0; | |
e46dab4d | 2367 | adap->sge.egr_map[fl->cntxt_id - adap->sge.egr_start] = fl; |
d63a6dcf | 2368 | |
df64e4d3 HS |
2369 | /* Note, we must initialize the BAR2 Free List User Doorbell |
2370 | * information before refilling the Free List! | |
d63a6dcf | 2371 | */ |
df64e4d3 HS |
2372 | fl->bar2_addr = bar2_address(adap, |
2373 | fl->cntxt_id, | |
2374 | T4_BAR2_QTYPE_EGRESS, | |
2375 | &fl->bar2_qid); | |
fd3a4790 DM |
2376 | refill_fl(adap, fl, fl_cap(fl), GFP_KERNEL); |
2377 | } | |
2378 | return 0; | |
2379 | ||
2380 | fl_nomem: | |
2381 | ret = -ENOMEM; | |
2382 | err: | |
2383 | if (iq->desc) { | |
2384 | dma_free_coherent(adap->pdev_dev, iq->size * iq->iqe_len, | |
2385 | iq->desc, iq->phys_addr); | |
2386 | iq->desc = NULL; | |
2387 | } | |
2388 | if (fl && fl->desc) { | |
2389 | kfree(fl->sdesc); | |
2390 | fl->sdesc = NULL; | |
2391 | dma_free_coherent(adap->pdev_dev, flsz * sizeof(struct tx_desc), | |
2392 | fl->desc, fl->addr); | |
2393 | fl->desc = NULL; | |
2394 | } | |
2395 | return ret; | |
2396 | } | |
2397 | ||
2398 | static void init_txq(struct adapter *adap, struct sge_txq *q, unsigned int id) | |
2399 | { | |
22adfe0a | 2400 | q->cntxt_id = id; |
df64e4d3 HS |
2401 | q->bar2_addr = bar2_address(adap, |
2402 | q->cntxt_id, | |
2403 | T4_BAR2_QTYPE_EGRESS, | |
2404 | &q->bar2_qid); | |
fd3a4790 DM |
2405 | q->in_use = 0; |
2406 | q->cidx = q->pidx = 0; | |
2407 | q->stops = q->restarts = 0; | |
2408 | q->stat = (void *)&q->desc[q->size]; | |
3069ee9b | 2409 | spin_lock_init(&q->db_lock); |
e46dab4d | 2410 | adap->sge.egr_map[id - adap->sge.egr_start] = q; |
fd3a4790 DM |
2411 | } |
2412 | ||
2413 | int t4_sge_alloc_eth_txq(struct adapter *adap, struct sge_eth_txq *txq, | |
2414 | struct net_device *dev, struct netdev_queue *netdevq, | |
2415 | unsigned int iqid) | |
2416 | { | |
2417 | int ret, nentries; | |
2418 | struct fw_eq_eth_cmd c; | |
52367a76 | 2419 | struct sge *s = &adap->sge; |
fd3a4790 DM |
2420 | struct port_info *pi = netdev_priv(dev); |
2421 | ||
2422 | /* Add status entries */ | |
52367a76 | 2423 | nentries = txq->q.size + s->stat_len / sizeof(struct tx_desc); |
fd3a4790 DM |
2424 | |
2425 | txq->q.desc = alloc_ring(adap->pdev_dev, txq->q.size, | |
2426 | sizeof(struct tx_desc), sizeof(struct tx_sw_desc), | |
52367a76 | 2427 | &txq->q.phys_addr, &txq->q.sdesc, s->stat_len, |
ad6bad3e | 2428 | netdev_queue_numa_node_read(netdevq)); |
fd3a4790 DM |
2429 | if (!txq->q.desc) |
2430 | return -ENOMEM; | |
2431 | ||
2432 | memset(&c, 0, sizeof(c)); | |
e2ac9628 HS |
2433 | c.op_to_vfn = htonl(FW_CMD_OP_V(FW_EQ_ETH_CMD) | FW_CMD_REQUEST_F | |
2434 | FW_CMD_WRITE_F | FW_CMD_EXEC_F | | |
6e4b51a6 HS |
2435 | FW_EQ_ETH_CMD_PFN_V(adap->fn) | |
2436 | FW_EQ_ETH_CMD_VFN_V(0)); | |
2437 | c.alloc_to_len16 = htonl(FW_EQ_ETH_CMD_ALLOC_F | | |
2438 | FW_EQ_ETH_CMD_EQSTART_F | FW_LEN16(c)); | |
2439 | c.viid_pkd = htonl(FW_EQ_ETH_CMD_AUTOEQUEQE_F | | |
2440 | FW_EQ_ETH_CMD_VIID_V(pi->viid)); | |
2441 | c.fetchszm_to_iqid = htonl(FW_EQ_ETH_CMD_HOSTFCMODE_V(2) | | |
2442 | FW_EQ_ETH_CMD_PCIECHN_V(pi->tx_chan) | | |
2443 | FW_EQ_ETH_CMD_FETCHRO_V(1) | | |
2444 | FW_EQ_ETH_CMD_IQID_V(iqid)); | |
2445 | c.dcaen_to_eqsize = htonl(FW_EQ_ETH_CMD_FBMIN_V(2) | | |
2446 | FW_EQ_ETH_CMD_FBMAX_V(3) | | |
2447 | FW_EQ_ETH_CMD_CIDXFTHRESH_V(5) | | |
2448 | FW_EQ_ETH_CMD_EQSIZE_V(nentries)); | |
fd3a4790 DM |
2449 | c.eqaddr = cpu_to_be64(txq->q.phys_addr); |
2450 | ||
060e0c75 | 2451 | ret = t4_wr_mbox(adap, adap->fn, &c, sizeof(c), &c); |
fd3a4790 DM |
2452 | if (ret) { |
2453 | kfree(txq->q.sdesc); | |
2454 | txq->q.sdesc = NULL; | |
2455 | dma_free_coherent(adap->pdev_dev, | |
2456 | nentries * sizeof(struct tx_desc), | |
2457 | txq->q.desc, txq->q.phys_addr); | |
2458 | txq->q.desc = NULL; | |
2459 | return ret; | |
2460 | } | |
2461 | ||
6e4b51a6 | 2462 | init_txq(adap, &txq->q, FW_EQ_ETH_CMD_EQID_G(ntohl(c.eqid_pkd))); |
fd3a4790 DM |
2463 | txq->txq = netdevq; |
2464 | txq->tso = txq->tx_cso = txq->vlan_ins = 0; | |
2465 | txq->mapping_err = 0; | |
2466 | return 0; | |
2467 | } | |
2468 | ||
2469 | int t4_sge_alloc_ctrl_txq(struct adapter *adap, struct sge_ctrl_txq *txq, | |
2470 | struct net_device *dev, unsigned int iqid, | |
2471 | unsigned int cmplqid) | |
2472 | { | |
2473 | int ret, nentries; | |
2474 | struct fw_eq_ctrl_cmd c; | |
52367a76 | 2475 | struct sge *s = &adap->sge; |
fd3a4790 DM |
2476 | struct port_info *pi = netdev_priv(dev); |
2477 | ||
2478 | /* Add status entries */ | |
52367a76 | 2479 | nentries = txq->q.size + s->stat_len / sizeof(struct tx_desc); |
fd3a4790 DM |
2480 | |
2481 | txq->q.desc = alloc_ring(adap->pdev_dev, nentries, | |
2482 | sizeof(struct tx_desc), 0, &txq->q.phys_addr, | |
ad6bad3e | 2483 | NULL, 0, NUMA_NO_NODE); |
fd3a4790 DM |
2484 | if (!txq->q.desc) |
2485 | return -ENOMEM; | |
2486 | ||
e2ac9628 HS |
2487 | c.op_to_vfn = htonl(FW_CMD_OP_V(FW_EQ_CTRL_CMD) | FW_CMD_REQUEST_F | |
2488 | FW_CMD_WRITE_F | FW_CMD_EXEC_F | | |
6e4b51a6 HS |
2489 | FW_EQ_CTRL_CMD_PFN_V(adap->fn) | |
2490 | FW_EQ_CTRL_CMD_VFN_V(0)); | |
2491 | c.alloc_to_len16 = htonl(FW_EQ_CTRL_CMD_ALLOC_F | | |
2492 | FW_EQ_CTRL_CMD_EQSTART_F | FW_LEN16(c)); | |
2493 | c.cmpliqid_eqid = htonl(FW_EQ_CTRL_CMD_CMPLIQID_V(cmplqid)); | |
fd3a4790 | 2494 | c.physeqid_pkd = htonl(0); |
6e4b51a6 HS |
2495 | c.fetchszm_to_iqid = htonl(FW_EQ_CTRL_CMD_HOSTFCMODE_V(2) | |
2496 | FW_EQ_CTRL_CMD_PCIECHN_V(pi->tx_chan) | | |
2497 | FW_EQ_CTRL_CMD_FETCHRO_F | | |
2498 | FW_EQ_CTRL_CMD_IQID_V(iqid)); | |
2499 | c.dcaen_to_eqsize = htonl(FW_EQ_CTRL_CMD_FBMIN_V(2) | | |
2500 | FW_EQ_CTRL_CMD_FBMAX_V(3) | | |
2501 | FW_EQ_CTRL_CMD_CIDXFTHRESH_V(5) | | |
2502 | FW_EQ_CTRL_CMD_EQSIZE_V(nentries)); | |
fd3a4790 DM |
2503 | c.eqaddr = cpu_to_be64(txq->q.phys_addr); |
2504 | ||
060e0c75 | 2505 | ret = t4_wr_mbox(adap, adap->fn, &c, sizeof(c), &c); |
fd3a4790 DM |
2506 | if (ret) { |
2507 | dma_free_coherent(adap->pdev_dev, | |
2508 | nentries * sizeof(struct tx_desc), | |
2509 | txq->q.desc, txq->q.phys_addr); | |
2510 | txq->q.desc = NULL; | |
2511 | return ret; | |
2512 | } | |
2513 | ||
6e4b51a6 | 2514 | init_txq(adap, &txq->q, FW_EQ_CTRL_CMD_EQID_G(ntohl(c.cmpliqid_eqid))); |
fd3a4790 DM |
2515 | txq->adap = adap; |
2516 | skb_queue_head_init(&txq->sendq); | |
2517 | tasklet_init(&txq->qresume_tsk, restart_ctrlq, (unsigned long)txq); | |
2518 | txq->full = 0; | |
2519 | return 0; | |
2520 | } | |
2521 | ||
2522 | int t4_sge_alloc_ofld_txq(struct adapter *adap, struct sge_ofld_txq *txq, | |
2523 | struct net_device *dev, unsigned int iqid) | |
2524 | { | |
2525 | int ret, nentries; | |
2526 | struct fw_eq_ofld_cmd c; | |
52367a76 | 2527 | struct sge *s = &adap->sge; |
fd3a4790 DM |
2528 | struct port_info *pi = netdev_priv(dev); |
2529 | ||
2530 | /* Add status entries */ | |
52367a76 | 2531 | nentries = txq->q.size + s->stat_len / sizeof(struct tx_desc); |
fd3a4790 DM |
2532 | |
2533 | txq->q.desc = alloc_ring(adap->pdev_dev, txq->q.size, | |
2534 | sizeof(struct tx_desc), sizeof(struct tx_sw_desc), | |
52367a76 | 2535 | &txq->q.phys_addr, &txq->q.sdesc, s->stat_len, |
ad6bad3e | 2536 | NUMA_NO_NODE); |
fd3a4790 DM |
2537 | if (!txq->q.desc) |
2538 | return -ENOMEM; | |
2539 | ||
2540 | memset(&c, 0, sizeof(c)); | |
e2ac9628 HS |
2541 | c.op_to_vfn = htonl(FW_CMD_OP_V(FW_EQ_OFLD_CMD) | FW_CMD_REQUEST_F | |
2542 | FW_CMD_WRITE_F | FW_CMD_EXEC_F | | |
6e4b51a6 HS |
2543 | FW_EQ_OFLD_CMD_PFN_V(adap->fn) | |
2544 | FW_EQ_OFLD_CMD_VFN_V(0)); | |
2545 | c.alloc_to_len16 = htonl(FW_EQ_OFLD_CMD_ALLOC_F | | |
2546 | FW_EQ_OFLD_CMD_EQSTART_F | FW_LEN16(c)); | |
2547 | c.fetchszm_to_iqid = htonl(FW_EQ_OFLD_CMD_HOSTFCMODE_V(2) | | |
2548 | FW_EQ_OFLD_CMD_PCIECHN_V(pi->tx_chan) | | |
2549 | FW_EQ_OFLD_CMD_FETCHRO_F | | |
2550 | FW_EQ_OFLD_CMD_IQID_V(iqid)); | |
2551 | c.dcaen_to_eqsize = htonl(FW_EQ_OFLD_CMD_FBMIN_V(2) | | |
2552 | FW_EQ_OFLD_CMD_FBMAX_V(3) | | |
2553 | FW_EQ_OFLD_CMD_CIDXFTHRESH_V(5) | | |
2554 | FW_EQ_OFLD_CMD_EQSIZE_V(nentries)); | |
fd3a4790 DM |
2555 | c.eqaddr = cpu_to_be64(txq->q.phys_addr); |
2556 | ||
060e0c75 | 2557 | ret = t4_wr_mbox(adap, adap->fn, &c, sizeof(c), &c); |
fd3a4790 DM |
2558 | if (ret) { |
2559 | kfree(txq->q.sdesc); | |
2560 | txq->q.sdesc = NULL; | |
2561 | dma_free_coherent(adap->pdev_dev, | |
2562 | nentries * sizeof(struct tx_desc), | |
2563 | txq->q.desc, txq->q.phys_addr); | |
2564 | txq->q.desc = NULL; | |
2565 | return ret; | |
2566 | } | |
2567 | ||
6e4b51a6 | 2568 | init_txq(adap, &txq->q, FW_EQ_OFLD_CMD_EQID_G(ntohl(c.eqid_pkd))); |
fd3a4790 DM |
2569 | txq->adap = adap; |
2570 | skb_queue_head_init(&txq->sendq); | |
2571 | tasklet_init(&txq->qresume_tsk, restart_ofldq, (unsigned long)txq); | |
2572 | txq->full = 0; | |
2573 | txq->mapping_err = 0; | |
2574 | return 0; | |
2575 | } | |
2576 | ||
2577 | static void free_txq(struct adapter *adap, struct sge_txq *q) | |
2578 | { | |
52367a76 VP |
2579 | struct sge *s = &adap->sge; |
2580 | ||
fd3a4790 | 2581 | dma_free_coherent(adap->pdev_dev, |
52367a76 | 2582 | q->size * sizeof(struct tx_desc) + s->stat_len, |
fd3a4790 DM |
2583 | q->desc, q->phys_addr); |
2584 | q->cntxt_id = 0; | |
2585 | q->sdesc = NULL; | |
2586 | q->desc = NULL; | |
2587 | } | |
2588 | ||
2589 | static void free_rspq_fl(struct adapter *adap, struct sge_rspq *rq, | |
2590 | struct sge_fl *fl) | |
2591 | { | |
52367a76 | 2592 | struct sge *s = &adap->sge; |
fd3a4790 DM |
2593 | unsigned int fl_id = fl ? fl->cntxt_id : 0xffff; |
2594 | ||
e46dab4d | 2595 | adap->sge.ingr_map[rq->cntxt_id - adap->sge.ingr_start] = NULL; |
060e0c75 DM |
2596 | t4_iq_free(adap, adap->fn, adap->fn, 0, FW_IQ_TYPE_FL_INT_CAP, |
2597 | rq->cntxt_id, fl_id, 0xffff); | |
fd3a4790 DM |
2598 | dma_free_coherent(adap->pdev_dev, (rq->size + 1) * rq->iqe_len, |
2599 | rq->desc, rq->phys_addr); | |
2600 | netif_napi_del(&rq->napi); | |
2601 | rq->netdev = NULL; | |
2602 | rq->cntxt_id = rq->abs_id = 0; | |
2603 | rq->desc = NULL; | |
2604 | ||
2605 | if (fl) { | |
2606 | free_rx_bufs(adap, fl, fl->avail); | |
52367a76 | 2607 | dma_free_coherent(adap->pdev_dev, fl->size * 8 + s->stat_len, |
fd3a4790 DM |
2608 | fl->desc, fl->addr); |
2609 | kfree(fl->sdesc); | |
2610 | fl->sdesc = NULL; | |
2611 | fl->cntxt_id = 0; | |
2612 | fl->desc = NULL; | |
2613 | } | |
2614 | } | |
2615 | ||
5fa76694 HS |
2616 | /** |
2617 | * t4_free_ofld_rxqs - free a block of consecutive Rx queues | |
2618 | * @adap: the adapter | |
2619 | * @n: number of queues | |
2620 | * @q: pointer to first queue | |
2621 | * | |
2622 | * Release the resources of a consecutive block of offload Rx queues. | |
2623 | */ | |
2624 | void t4_free_ofld_rxqs(struct adapter *adap, int n, struct sge_ofld_rxq *q) | |
2625 | { | |
2626 | for ( ; n; n--, q++) | |
2627 | if (q->rspq.desc) | |
2628 | free_rspq_fl(adap, &q->rspq, | |
2629 | q->fl.size ? &q->fl : NULL); | |
2630 | } | |
2631 | ||
fd3a4790 DM |
2632 | /** |
2633 | * t4_free_sge_resources - free SGE resources | |
2634 | * @adap: the adapter | |
2635 | * | |
2636 | * Frees resources used by the SGE queue sets. | |
2637 | */ | |
2638 | void t4_free_sge_resources(struct adapter *adap) | |
2639 | { | |
2640 | int i; | |
2641 | struct sge_eth_rxq *eq = adap->sge.ethrxq; | |
2642 | struct sge_eth_txq *etq = adap->sge.ethtxq; | |
fd3a4790 DM |
2643 | |
2644 | /* clean up Ethernet Tx/Rx queues */ | |
2645 | for (i = 0; i < adap->sge.ethqsets; i++, eq++, etq++) { | |
2646 | if (eq->rspq.desc) | |
5fa76694 HS |
2647 | free_rspq_fl(adap, &eq->rspq, |
2648 | eq->fl.size ? &eq->fl : NULL); | |
fd3a4790 | 2649 | if (etq->q.desc) { |
060e0c75 DM |
2650 | t4_eth_eq_free(adap, adap->fn, adap->fn, 0, |
2651 | etq->q.cntxt_id); | |
fd3a4790 DM |
2652 | free_tx_desc(adap, &etq->q, etq->q.in_use, true); |
2653 | kfree(etq->q.sdesc); | |
2654 | free_txq(adap, &etq->q); | |
2655 | } | |
2656 | } | |
2657 | ||
2658 | /* clean up RDMA and iSCSI Rx queues */ | |
5fa76694 HS |
2659 | t4_free_ofld_rxqs(adap, adap->sge.ofldqsets, adap->sge.ofldrxq); |
2660 | t4_free_ofld_rxqs(adap, adap->sge.rdmaqs, adap->sge.rdmarxq); | |
2661 | t4_free_ofld_rxqs(adap, adap->sge.rdmaciqs, adap->sge.rdmaciq); | |
fd3a4790 DM |
2662 | |
2663 | /* clean up offload Tx queues */ | |
2664 | for (i = 0; i < ARRAY_SIZE(adap->sge.ofldtxq); i++) { | |
2665 | struct sge_ofld_txq *q = &adap->sge.ofldtxq[i]; | |
2666 | ||
2667 | if (q->q.desc) { | |
2668 | tasklet_kill(&q->qresume_tsk); | |
060e0c75 DM |
2669 | t4_ofld_eq_free(adap, adap->fn, adap->fn, 0, |
2670 | q->q.cntxt_id); | |
fd3a4790 DM |
2671 | free_tx_desc(adap, &q->q, q->q.in_use, false); |
2672 | kfree(q->q.sdesc); | |
2673 | __skb_queue_purge(&q->sendq); | |
2674 | free_txq(adap, &q->q); | |
2675 | } | |
2676 | } | |
2677 | ||
2678 | /* clean up control Tx queues */ | |
2679 | for (i = 0; i < ARRAY_SIZE(adap->sge.ctrlq); i++) { | |
2680 | struct sge_ctrl_txq *cq = &adap->sge.ctrlq[i]; | |
2681 | ||
2682 | if (cq->q.desc) { | |
2683 | tasklet_kill(&cq->qresume_tsk); | |
060e0c75 DM |
2684 | t4_ctrl_eq_free(adap, adap->fn, adap->fn, 0, |
2685 | cq->q.cntxt_id); | |
fd3a4790 DM |
2686 | __skb_queue_purge(&cq->sendq); |
2687 | free_txq(adap, &cq->q); | |
2688 | } | |
2689 | } | |
2690 | ||
2691 | if (adap->sge.fw_evtq.desc) | |
2692 | free_rspq_fl(adap, &adap->sge.fw_evtq, NULL); | |
2693 | ||
2694 | if (adap->sge.intrq.desc) | |
2695 | free_rspq_fl(adap, &adap->sge.intrq, NULL); | |
2696 | ||
2697 | /* clear the reverse egress queue map */ | |
2698 | memset(adap->sge.egr_map, 0, sizeof(adap->sge.egr_map)); | |
2699 | } | |
2700 | ||
2701 | void t4_sge_start(struct adapter *adap) | |
2702 | { | |
2703 | adap->sge.ethtxq_rover = 0; | |
2704 | mod_timer(&adap->sge.rx_timer, jiffies + RX_QCHECK_PERIOD); | |
2705 | mod_timer(&adap->sge.tx_timer, jiffies + TX_QCHECK_PERIOD); | |
2706 | } | |
2707 | ||
2708 | /** | |
2709 | * t4_sge_stop - disable SGE operation | |
2710 | * @adap: the adapter | |
2711 | * | |
2712 | * Stop tasklets and timers associated with the DMA engine. Note that | |
2713 | * this is effective only if measures have been taken to disable any HW | |
2714 | * events that may restart them. | |
2715 | */ | |
2716 | void t4_sge_stop(struct adapter *adap) | |
2717 | { | |
2718 | int i; | |
2719 | struct sge *s = &adap->sge; | |
2720 | ||
2721 | if (in_interrupt()) /* actions below require waiting */ | |
2722 | return; | |
2723 | ||
2724 | if (s->rx_timer.function) | |
2725 | del_timer_sync(&s->rx_timer); | |
2726 | if (s->tx_timer.function) | |
2727 | del_timer_sync(&s->tx_timer); | |
2728 | ||
2729 | for (i = 0; i < ARRAY_SIZE(s->ofldtxq); i++) { | |
2730 | struct sge_ofld_txq *q = &s->ofldtxq[i]; | |
2731 | ||
2732 | if (q->q.desc) | |
2733 | tasklet_kill(&q->qresume_tsk); | |
2734 | } | |
2735 | for (i = 0; i < ARRAY_SIZE(s->ctrlq); i++) { | |
2736 | struct sge_ctrl_txq *cq = &s->ctrlq[i]; | |
2737 | ||
2738 | if (cq->q.desc) | |
2739 | tasklet_kill(&cq->qresume_tsk); | |
2740 | } | |
2741 | } | |
2742 | ||
2743 | /** | |
2744 | * t4_sge_init - initialize SGE | |
2745 | * @adap: the adapter | |
2746 | * | |
2747 | * Performs SGE initialization needed every time after a chip reset. | |
2748 | * We do not initialize any of the queues here, instead the driver | |
2749 | * top-level must request them individually. | |
52367a76 VP |
2750 | * |
2751 | * Called in two different modes: | |
2752 | * | |
2753 | * 1. Perform actual hardware initialization and record hard-coded | |
2754 | * parameters which were used. This gets used when we're the | |
2755 | * Master PF and the Firmware Configuration File support didn't | |
2756 | * work for some reason. | |
2757 | * | |
2758 | * 2. We're not the Master PF or initialization was performed with | |
2759 | * a Firmware Configuration File. In this case we need to grab | |
2760 | * any of the SGE operating parameters that we need to have in | |
2761 | * order to do our job and make sure we can live with them ... | |
fd3a4790 | 2762 | */ |
52367a76 VP |
2763 | |
2764 | static int t4_sge_init_soft(struct adapter *adap) | |
fd3a4790 DM |
2765 | { |
2766 | struct sge *s = &adap->sge; | |
52367a76 VP |
2767 | u32 fl_small_pg, fl_large_pg, fl_small_mtu, fl_large_mtu; |
2768 | u32 timer_value_0_and_1, timer_value_2_and_3, timer_value_4_and_5; | |
2769 | u32 ingress_rx_threshold; | |
fd3a4790 | 2770 | |
52367a76 VP |
2771 | /* |
2772 | * Verify that CPL messages are going to the Ingress Queue for | |
2773 | * process_responses() and that only packet data is going to the | |
2774 | * Free Lists. | |
2775 | */ | |
f612b815 HS |
2776 | if ((t4_read_reg(adap, SGE_CONTROL_A) & RXPKTCPLMODE_F) != |
2777 | RXPKTCPLMODE_V(RXPKTCPLMODE_SPLIT_X)) { | |
52367a76 VP |
2778 | dev_err(adap->pdev_dev, "bad SGE CPL MODE\n"); |
2779 | return -EINVAL; | |
2780 | } | |
2781 | ||
2782 | /* | |
2783 | * Validate the Host Buffer Register Array indices that we want to | |
2784 | * use ... | |
2785 | * | |
2786 | * XXX Note that we should really read through the Host Buffer Size | |
2787 | * XXX register array and find the indices of the Buffer Sizes which | |
2788 | * XXX meet our needs! | |
2789 | */ | |
2790 | #define READ_FL_BUF(x) \ | |
f612b815 | 2791 | t4_read_reg(adap, SGE_FL_BUFFER_SIZE0_A+(x)*sizeof(u32)) |
52367a76 VP |
2792 | |
2793 | fl_small_pg = READ_FL_BUF(RX_SMALL_PG_BUF); | |
2794 | fl_large_pg = READ_FL_BUF(RX_LARGE_PG_BUF); | |
2795 | fl_small_mtu = READ_FL_BUF(RX_SMALL_MTU_BUF); | |
2796 | fl_large_mtu = READ_FL_BUF(RX_LARGE_MTU_BUF); | |
2797 | ||
92ddcc7b KS |
2798 | /* We only bother using the Large Page logic if the Large Page Buffer |
2799 | * is larger than our Page Size Buffer. | |
2800 | */ | |
2801 | if (fl_large_pg <= fl_small_pg) | |
2802 | fl_large_pg = 0; | |
2803 | ||
52367a76 VP |
2804 | #undef READ_FL_BUF |
2805 | ||
92ddcc7b KS |
2806 | /* The Page Size Buffer must be exactly equal to our Page Size and the |
2807 | * Large Page Size Buffer should be 0 (per above) or a power of 2. | |
2808 | */ | |
52367a76 | 2809 | if (fl_small_pg != PAGE_SIZE || |
92ddcc7b | 2810 | (fl_large_pg & (fl_large_pg-1)) != 0) { |
52367a76 VP |
2811 | dev_err(adap->pdev_dev, "bad SGE FL page buffer sizes [%d, %d]\n", |
2812 | fl_small_pg, fl_large_pg); | |
2813 | return -EINVAL; | |
2814 | } | |
2815 | if (fl_large_pg) | |
2816 | s->fl_pg_order = ilog2(fl_large_pg) - PAGE_SHIFT; | |
2817 | ||
2818 | if (fl_small_mtu < FL_MTU_SMALL_BUFSIZE(adap) || | |
2819 | fl_large_mtu < FL_MTU_LARGE_BUFSIZE(adap)) { | |
2820 | dev_err(adap->pdev_dev, "bad SGE FL MTU sizes [%d, %d]\n", | |
2821 | fl_small_mtu, fl_large_mtu); | |
2822 | return -EINVAL; | |
2823 | } | |
2824 | ||
2825 | /* | |
2826 | * Retrieve our RX interrupt holdoff timer values and counter | |
2827 | * threshold values from the SGE parameters. | |
2828 | */ | |
2829 | timer_value_0_and_1 = t4_read_reg(adap, SGE_TIMER_VALUE_0_AND_1); | |
2830 | timer_value_2_and_3 = t4_read_reg(adap, SGE_TIMER_VALUE_2_AND_3); | |
2831 | timer_value_4_and_5 = t4_read_reg(adap, SGE_TIMER_VALUE_4_AND_5); | |
2832 | s->timer_val[0] = core_ticks_to_us(adap, | |
2833 | TIMERVALUE0_GET(timer_value_0_and_1)); | |
2834 | s->timer_val[1] = core_ticks_to_us(adap, | |
2835 | TIMERVALUE1_GET(timer_value_0_and_1)); | |
2836 | s->timer_val[2] = core_ticks_to_us(adap, | |
2837 | TIMERVALUE2_GET(timer_value_2_and_3)); | |
2838 | s->timer_val[3] = core_ticks_to_us(adap, | |
2839 | TIMERVALUE3_GET(timer_value_2_and_3)); | |
2840 | s->timer_val[4] = core_ticks_to_us(adap, | |
2841 | TIMERVALUE4_GET(timer_value_4_and_5)); | |
2842 | s->timer_val[5] = core_ticks_to_us(adap, | |
2843 | TIMERVALUE5_GET(timer_value_4_and_5)); | |
2844 | ||
f612b815 HS |
2845 | ingress_rx_threshold = t4_read_reg(adap, SGE_INGRESS_RX_THRESHOLD_A); |
2846 | s->counter_val[0] = THRESHOLD_0_G(ingress_rx_threshold); | |
2847 | s->counter_val[1] = THRESHOLD_1_G(ingress_rx_threshold); | |
2848 | s->counter_val[2] = THRESHOLD_2_G(ingress_rx_threshold); | |
2849 | s->counter_val[3] = THRESHOLD_3_G(ingress_rx_threshold); | |
52367a76 VP |
2850 | |
2851 | return 0; | |
2852 | } | |
2853 | ||
2854 | static int t4_sge_init_hard(struct adapter *adap) | |
2855 | { | |
2856 | struct sge *s = &adap->sge; | |
2857 | ||
2858 | /* | |
2859 | * Set up our basic SGE mode to deliver CPL messages to our Ingress | |
2860 | * Queue and Packet Date to the Free List. | |
2861 | */ | |
f612b815 | 2862 | t4_set_reg_field(adap, SGE_CONTROL_A, RXPKTCPLMODE_F, RXPKTCPLMODE_F); |
060e0c75 | 2863 | |
3069ee9b VP |
2864 | /* |
2865 | * Set up to drop DOORBELL writes when the DOORBELL FIFO overflows | |
2866 | * and generate an interrupt when this occurs so we can recover. | |
2867 | */ | |
d14807dd | 2868 | if (is_t4(adap->params.chip)) { |
0a57a536 SR |
2869 | t4_set_reg_field(adap, A_SGE_DBFIFO_STATUS, |
2870 | V_HP_INT_THRESH(M_HP_INT_THRESH) | | |
2871 | V_LP_INT_THRESH(M_LP_INT_THRESH), | |
2872 | V_HP_INT_THRESH(dbfifo_int_thresh) | | |
2873 | V_LP_INT_THRESH(dbfifo_int_thresh)); | |
2874 | } else { | |
2875 | t4_set_reg_field(adap, A_SGE_DBFIFO_STATUS, | |
2876 | V_LP_INT_THRESH_T5(M_LP_INT_THRESH_T5), | |
2877 | V_LP_INT_THRESH_T5(dbfifo_int_thresh)); | |
2878 | t4_set_reg_field(adap, SGE_DBFIFO_STATUS2, | |
2879 | V_HP_INT_THRESH_T5(M_HP_INT_THRESH_T5), | |
2880 | V_HP_INT_THRESH_T5(dbfifo_int_thresh)); | |
2881 | } | |
881806bc VP |
2882 | t4_set_reg_field(adap, A_SGE_DOORBELL_CONTROL, F_ENABLE_DROP, |
2883 | F_ENABLE_DROP); | |
2884 | ||
52367a76 VP |
2885 | /* |
2886 | * SGE_FL_BUFFER_SIZE0 (RX_SMALL_PG_BUF) is set up by | |
2887 | * t4_fixup_host_params(). | |
2888 | */ | |
2889 | s->fl_pg_order = FL_PG_ORDER; | |
2890 | if (s->fl_pg_order) | |
2891 | t4_write_reg(adap, | |
f612b815 | 2892 | SGE_FL_BUFFER_SIZE0_A+RX_LARGE_PG_BUF*sizeof(u32), |
52367a76 | 2893 | PAGE_SIZE << FL_PG_ORDER); |
f612b815 | 2894 | t4_write_reg(adap, SGE_FL_BUFFER_SIZE0_A+RX_SMALL_MTU_BUF*sizeof(u32), |
52367a76 | 2895 | FL_MTU_SMALL_BUFSIZE(adap)); |
f612b815 | 2896 | t4_write_reg(adap, SGE_FL_BUFFER_SIZE0_A+RX_LARGE_MTU_BUF*sizeof(u32), |
52367a76 VP |
2897 | FL_MTU_LARGE_BUFSIZE(adap)); |
2898 | ||
2899 | /* | |
2900 | * Note that the SGE Ingress Packet Count Interrupt Threshold and | |
2901 | * Timer Holdoff values must be supplied by our caller. | |
2902 | */ | |
f612b815 HS |
2903 | t4_write_reg(adap, SGE_INGRESS_RX_THRESHOLD_A, |
2904 | THRESHOLD_0_V(s->counter_val[0]) | | |
2905 | THRESHOLD_1_V(s->counter_val[1]) | | |
2906 | THRESHOLD_2_V(s->counter_val[2]) | | |
2907 | THRESHOLD_3_V(s->counter_val[3])); | |
fd3a4790 DM |
2908 | t4_write_reg(adap, SGE_TIMER_VALUE_0_AND_1, |
2909 | TIMERVALUE0(us_to_core_ticks(adap, s->timer_val[0])) | | |
2910 | TIMERVALUE1(us_to_core_ticks(adap, s->timer_val[1]))); | |
2911 | t4_write_reg(adap, SGE_TIMER_VALUE_2_AND_3, | |
52367a76 VP |
2912 | TIMERVALUE2(us_to_core_ticks(adap, s->timer_val[2])) | |
2913 | TIMERVALUE3(us_to_core_ticks(adap, s->timer_val[3]))); | |
fd3a4790 | 2914 | t4_write_reg(adap, SGE_TIMER_VALUE_4_AND_5, |
52367a76 VP |
2915 | TIMERVALUE4(us_to_core_ticks(adap, s->timer_val[4])) | |
2916 | TIMERVALUE5(us_to_core_ticks(adap, s->timer_val[5]))); | |
2917 | ||
2918 | return 0; | |
2919 | } | |
2920 | ||
2921 | int t4_sge_init(struct adapter *adap) | |
2922 | { | |
2923 | struct sge *s = &adap->sge; | |
ce8f407a HS |
2924 | u32 sge_control, sge_control2, sge_conm_ctrl; |
2925 | unsigned int ingpadboundary, ingpackboundary; | |
c2b955e0 | 2926 | int ret, egress_threshold; |
52367a76 VP |
2927 | |
2928 | /* | |
2929 | * Ingress Padding Boundary and Egress Status Page Size are set up by | |
2930 | * t4_fixup_host_params(). | |
2931 | */ | |
f612b815 HS |
2932 | sge_control = t4_read_reg(adap, SGE_CONTROL_A); |
2933 | s->pktshift = PKTSHIFT_G(sge_control); | |
2934 | s->stat_len = (sge_control & EGRSTATUSPAGESIZE_F) ? 128 : 64; | |
ce8f407a HS |
2935 | |
2936 | /* T4 uses a single control field to specify both the PCIe Padding and | |
2937 | * Packing Boundary. T5 introduced the ability to specify these | |
2938 | * separately. The actual Ingress Packet Data alignment boundary | |
2939 | * within Packed Buffer Mode is the maximum of these two | |
2940 | * specifications. | |
2941 | */ | |
f612b815 HS |
2942 | ingpadboundary = 1 << (INGPADBOUNDARY_G(sge_control) + |
2943 | INGPADBOUNDARY_SHIFT_X); | |
ce8f407a HS |
2944 | if (is_t4(adap->params.chip)) { |
2945 | s->fl_align = ingpadboundary; | |
2946 | } else { | |
2947 | /* T5 has a different interpretation of one of the PCIe Packing | |
2948 | * Boundary values. | |
2949 | */ | |
2950 | sge_control2 = t4_read_reg(adap, SGE_CONTROL2_A); | |
2951 | ingpackboundary = INGPACKBOUNDARY_G(sge_control2); | |
2952 | if (ingpackboundary == INGPACKBOUNDARY_16B_X) | |
2953 | ingpackboundary = 16; | |
2954 | else | |
2955 | ingpackboundary = 1 << (ingpackboundary + | |
2956 | INGPACKBOUNDARY_SHIFT_X); | |
2957 | ||
2958 | s->fl_align = max(ingpadboundary, ingpackboundary); | |
2959 | } | |
52367a76 VP |
2960 | |
2961 | if (adap->flags & USING_SOFT_PARAMS) | |
2962 | ret = t4_sge_init_soft(adap); | |
2963 | else | |
2964 | ret = t4_sge_init_hard(adap); | |
2965 | if (ret < 0) | |
2966 | return ret; | |
2967 | ||
2968 | /* | |
2969 | * A FL with <= fl_starve_thres buffers is starving and a periodic | |
2970 | * timer will attempt to refill it. This needs to be larger than the | |
2971 | * SGE's Egress Congestion Threshold. If it isn't, then we can get | |
2972 | * stuck waiting for new packets while the SGE is waiting for us to | |
2973 | * give it more Free List entries. (Note that the SGE's Egress | |
c2b955e0 KS |
2974 | * Congestion Threshold is in units of 2 Free List pointers.) For T4, |
2975 | * there was only a single field to control this. For T5 there's the | |
2976 | * original field which now only applies to Unpacked Mode Free List | |
2977 | * buffers and a new field which only applies to Packed Mode Free List | |
2978 | * buffers. | |
52367a76 | 2979 | */ |
f612b815 | 2980 | sge_conm_ctrl = t4_read_reg(adap, SGE_CONM_CTRL_A); |
c2b955e0 | 2981 | if (is_t4(adap->params.chip)) |
f612b815 | 2982 | egress_threshold = EGRTHRESHOLD_G(sge_conm_ctrl); |
c2b955e0 | 2983 | else |
f612b815 | 2984 | egress_threshold = EGRTHRESHOLDPACKING_G(sge_conm_ctrl); |
c2b955e0 | 2985 | s->fl_starve_thres = 2*egress_threshold + 1; |
52367a76 | 2986 | |
fd3a4790 DM |
2987 | setup_timer(&s->rx_timer, sge_rx_timer_cb, (unsigned long)adap); |
2988 | setup_timer(&s->tx_timer, sge_tx_timer_cb, (unsigned long)adap); | |
0f4d201f KS |
2989 | s->idma_1s_thresh = core_ticks_per_usec(adap) * 1000000; /* 1 s */ |
2990 | s->idma_stalled[0] = 0; | |
2991 | s->idma_stalled[1] = 0; | |
fd3a4790 | 2992 | spin_lock_init(&s->intrq_lock); |
52367a76 VP |
2993 | |
2994 | return 0; | |
fd3a4790 | 2995 | } |