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16f8bd4b CL |
1 | /* |
2 | * This file is part of the Chelsio T4 PCI-E SR-IOV Virtual Function Ethernet | |
3 | * driver for Linux. | |
4 | * | |
5 | * Copyright (c) 2009-2010 Chelsio Communications, Inc. All rights reserved. | |
6 | * | |
7 | * This software is available to you under a choice of one of two | |
8 | * licenses. You may choose to be licensed under the terms of the GNU | |
9 | * General Public License (GPL) Version 2, available from the file | |
10 | * COPYING in the main directory of this source tree, or the | |
11 | * OpenIB.org BSD license below: | |
12 | * | |
13 | * Redistribution and use in source and binary forms, with or | |
14 | * without modification, are permitted provided that the following | |
15 | * conditions are met: | |
16 | * | |
17 | * - Redistributions of source code must retain the above | |
18 | * copyright notice, this list of conditions and the following | |
19 | * disclaimer. | |
20 | * | |
21 | * - Redistributions in binary form must reproduce the above | |
22 | * copyright notice, this list of conditions and the following | |
23 | * disclaimer in the documentation and/or other materials | |
24 | * provided with the distribution. | |
25 | * | |
26 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
27 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
28 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
29 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
30 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
31 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
32 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
33 | * SOFTWARE. | |
34 | */ | |
35 | ||
36 | #ifndef __T4VF_COMMON_H__ | |
37 | #define __T4VF_COMMON_H__ | |
38 | ||
39 | #include "../cxgb4/t4fw_api.h" | |
40 | ||
622c62b5 | 41 | #define CHELSIO_CHIP_CODE(version, revision) (((version) << 4) | (revision)) |
70ee3666 | 42 | #define CHELSIO_CHIP_VERSION(code) (((code) >> 4) & 0xf) |
622c62b5 SR |
43 | #define CHELSIO_CHIP_RELEASE(code) ((code) & 0xf) |
44 | ||
70ee3666 HS |
45 | /* All T4 and later chips have their PCI-E Device IDs encoded as 0xVFPP where: |
46 | * | |
47 | * V = "4" for T4; "5" for T5, etc. or | |
48 | * = "a" for T4 FPGA; "b" for T4 FPGA, etc. | |
49 | * F = "0" for PF 0..3; "4".."7" for PF4..7; and "8" for VFs | |
50 | * PP = adapter product designation | |
51 | */ | |
622c62b5 SR |
52 | #define CHELSIO_T4 0x4 |
53 | #define CHELSIO_T5 0x5 | |
54 | ||
55 | enum chip_type { | |
70ee3666 HS |
56 | T4_A1 = CHELSIO_CHIP_CODE(CHELSIO_T4, 1), |
57 | T4_A2 = CHELSIO_CHIP_CODE(CHELSIO_T4, 2), | |
622c62b5 | 58 | T4_FIRST_REV = T4_A1, |
70ee3666 | 59 | T4_LAST_REV = T4_A2, |
622c62b5 | 60 | |
70ee3666 HS |
61 | T5_A0 = CHELSIO_CHIP_CODE(CHELSIO_T5, 0), |
62 | T5_A1 = CHELSIO_CHIP_CODE(CHELSIO_T5, 1), | |
63 | T5_FIRST_REV = T5_A0, | |
622c62b5 SR |
64 | T5_LAST_REV = T5_A1, |
65 | }; | |
66 | ||
16f8bd4b CL |
67 | /* |
68 | * The "len16" field of a Firmware Command Structure ... | |
69 | */ | |
70 | #define FW_LEN16(fw_struct) FW_CMD_LEN16(sizeof(fw_struct) / 16) | |
71 | ||
72 | /* | |
73 | * Per-VF statistics. | |
74 | */ | |
75 | struct t4vf_port_stats { | |
76 | /* | |
77 | * TX statistics. | |
78 | */ | |
79 | u64 tx_bcast_bytes; /* broadcast */ | |
80 | u64 tx_bcast_frames; | |
81 | u64 tx_mcast_bytes; /* multicast */ | |
82 | u64 tx_mcast_frames; | |
83 | u64 tx_ucast_bytes; /* unicast */ | |
84 | u64 tx_ucast_frames; | |
85 | u64 tx_drop_frames; /* TX dropped frames */ | |
86 | u64 tx_offload_bytes; /* offload */ | |
87 | u64 tx_offload_frames; | |
88 | ||
89 | /* | |
90 | * RX statistics. | |
91 | */ | |
92 | u64 rx_bcast_bytes; /* broadcast */ | |
93 | u64 rx_bcast_frames; | |
94 | u64 rx_mcast_bytes; /* multicast */ | |
95 | u64 rx_mcast_frames; | |
96 | u64 rx_ucast_bytes; | |
97 | u64 rx_ucast_frames; /* unicast */ | |
98 | ||
99 | u64 rx_err_frames; /* RX error frames */ | |
100 | }; | |
101 | ||
102 | /* | |
103 | * Per-"port" (Virtual Interface) link configuration ... | |
104 | */ | |
105 | struct link_config { | |
106 | unsigned int supported; /* link capabilities */ | |
107 | unsigned int advertising; /* advertised capabilities */ | |
108 | unsigned short requested_speed; /* speed user has requested */ | |
109 | unsigned short speed; /* actual link speed */ | |
110 | unsigned char requested_fc; /* flow control user has requested */ | |
111 | unsigned char fc; /* actual link flow control */ | |
112 | unsigned char autoneg; /* autonegotiating? */ | |
113 | unsigned char link_ok; /* link up? */ | |
114 | }; | |
115 | ||
116 | enum { | |
117 | PAUSE_RX = 1 << 0, | |
118 | PAUSE_TX = 1 << 1, | |
119 | PAUSE_AUTONEG = 1 << 2 | |
120 | }; | |
121 | ||
122 | /* | |
123 | * General device parameters ... | |
124 | */ | |
125 | struct dev_params { | |
126 | u32 fwrev; /* firmware version */ | |
127 | u32 tprev; /* TP Microcode Version */ | |
128 | }; | |
129 | ||
130 | /* | |
131 | * Scatter Gather Engine parameters. These are almost all determined by the | |
132 | * Physical Function Driver. We just need to grab them to see within which | |
133 | * environment we're playing ... | |
134 | */ | |
135 | struct sge_params { | |
136 | u32 sge_control; /* padding, boundaries, lengths, etc. */ | |
ce8f407a | 137 | u32 sge_control2; /* T5: more of the same */ |
16f8bd4b CL |
138 | u32 sge_host_page_size; /* RDMA page sizes */ |
139 | u32 sge_queues_per_page; /* RDMA queues/page */ | |
140 | u32 sge_user_mode_limits; /* limits for BAR2 user mode accesses */ | |
141 | u32 sge_fl_buffer_size[16]; /* free list buffer sizes */ | |
142 | u32 sge_ingress_rx_threshold; /* RX counter interrupt threshold[4] */ | |
50d21a66 | 143 | u32 sge_congestion_control; /* congestion thresholds, etc. */ |
16f8bd4b CL |
144 | u32 sge_timer_value_0_and_1; /* interrupt coalescing timer values */ |
145 | u32 sge_timer_value_2_and_3; | |
146 | u32 sge_timer_value_4_and_5; | |
147 | }; | |
148 | ||
149 | /* | |
150 | * Vital Product Data parameters. | |
151 | */ | |
152 | struct vpd_params { | |
153 | u32 cclk; /* Core Clock (KHz) */ | |
154 | }; | |
155 | ||
156 | /* | |
157 | * Global Receive Side Scaling (RSS) parameters in host-native format. | |
158 | */ | |
159 | struct rss_params { | |
160 | unsigned int mode; /* RSS mode */ | |
161 | union { | |
162 | struct { | |
65495745 HH |
163 | unsigned int synmapen:1; /* SYN Map Enable */ |
164 | unsigned int syn4tupenipv6:1; /* enable hashing 4-tuple IPv6 SYNs */ | |
165 | unsigned int syn2tupenipv6:1; /* enable hashing 2-tuple IPv6 SYNs */ | |
166 | unsigned int syn4tupenipv4:1; /* enable hashing 4-tuple IPv4 SYNs */ | |
167 | unsigned int syn2tupenipv4:1; /* enable hashing 2-tuple IPv4 SYNs */ | |
168 | unsigned int ofdmapen:1; /* Offload Map Enable */ | |
169 | unsigned int tnlmapen:1; /* Tunnel Map Enable */ | |
170 | unsigned int tnlalllookup:1; /* Tunnel All Lookup */ | |
171 | unsigned int hashtoeplitz:1; /* use Toeplitz hash */ | |
16f8bd4b CL |
172 | } basicvirtual; |
173 | } u; | |
174 | }; | |
175 | ||
176 | /* | |
177 | * Virtual Interface RSS Configuration in host-native format. | |
178 | */ | |
179 | union rss_vi_config { | |
180 | struct { | |
181 | u16 defaultq; /* Ingress Queue ID for !tnlalllookup */ | |
65495745 HH |
182 | unsigned int ip6fourtupen:1; /* hash 4-tuple IPv6 ingress packets */ |
183 | unsigned int ip6twotupen:1; /* hash 2-tuple IPv6 ingress packets */ | |
184 | unsigned int ip4fourtupen:1; /* hash 4-tuple IPv4 ingress packets */ | |
185 | unsigned int ip4twotupen:1; /* hash 2-tuple IPv4 ingress packets */ | |
16f8bd4b CL |
186 | int udpen; /* hash 4-tuple UDP ingress packets */ |
187 | } basicvirtual; | |
188 | }; | |
189 | ||
190 | /* | |
191 | * Maximum resources provisioned for a PCI VF. | |
192 | */ | |
193 | struct vf_resources { | |
194 | unsigned int nvi; /* N virtual interfaces */ | |
195 | unsigned int neq; /* N egress Qs */ | |
196 | unsigned int nethctrl; /* N egress ETH or CTRL Qs */ | |
197 | unsigned int niqflint; /* N ingress Qs/w free list(s) & intr */ | |
198 | unsigned int niq; /* N ingress Qs */ | |
199 | unsigned int tc; /* PCI-E traffic class */ | |
200 | unsigned int pmask; /* port access rights mask */ | |
201 | unsigned int nexactf; /* N exact MPS filters */ | |
202 | unsigned int r_caps; /* read capabilities */ | |
203 | unsigned int wx_caps; /* write/execute capabilities */ | |
204 | }; | |
205 | ||
206 | /* | |
207 | * Per-"adapter" (Virtual Function) parameters. | |
208 | */ | |
209 | struct adapter_params { | |
210 | struct dev_params dev; /* general device parameters */ | |
211 | struct sge_params sge; /* Scatter Gather Engine */ | |
212 | struct vpd_params vpd; /* Vital Product Data */ | |
213 | struct rss_params rss; /* Receive Side Scaling */ | |
214 | struct vf_resources vfres; /* Virtual Function Resource limits */ | |
70ee3666 | 215 | enum chip_type chip; /* chip code */ |
16f8bd4b CL |
216 | u8 nports; /* # of Ethernet "ports" */ |
217 | }; | |
218 | ||
219 | #include "adapter.h" | |
220 | ||
221 | #ifndef PCI_VENDOR_ID_CHELSIO | |
222 | # define PCI_VENDOR_ID_CHELSIO 0x1425 | |
223 | #endif | |
224 | ||
225 | #define for_each_port(adapter, iter) \ | |
226 | for (iter = 0; iter < (adapter)->params.nports; iter++) | |
227 | ||
228 | static inline bool is_10g_port(const struct link_config *lc) | |
229 | { | |
230 | return (lc->supported & SUPPORTED_10000baseT_Full) != 0; | |
231 | } | |
232 | ||
897d55df HS |
233 | static inline bool is_x_10g_port(const struct link_config *lc) |
234 | { | |
235 | return (lc->supported & FW_PORT_CAP_SPEED_10G) != 0 || | |
236 | (lc->supported & FW_PORT_CAP_SPEED_40G) != 0; | |
237 | } | |
238 | ||
16f8bd4b CL |
239 | static inline unsigned int core_ticks_per_usec(const struct adapter *adapter) |
240 | { | |
241 | return adapter->params.vpd.cclk / 1000; | |
242 | } | |
243 | ||
244 | static inline unsigned int us_to_core_ticks(const struct adapter *adapter, | |
245 | unsigned int us) | |
246 | { | |
247 | return (us * adapter->params.vpd.cclk) / 1000; | |
248 | } | |
249 | ||
250 | static inline unsigned int core_ticks_to_us(const struct adapter *adapter, | |
251 | unsigned int ticks) | |
252 | { | |
253 | return (ticks * 1000) / adapter->params.vpd.cclk; | |
254 | } | |
255 | ||
256 | int t4vf_wr_mbox_core(struct adapter *, const void *, int, void *, bool); | |
257 | ||
258 | static inline int t4vf_wr_mbox(struct adapter *adapter, const void *cmd, | |
259 | int size, void *rpl) | |
260 | { | |
261 | return t4vf_wr_mbox_core(adapter, cmd, size, rpl, true); | |
262 | } | |
263 | ||
264 | static inline int t4vf_wr_mbox_ns(struct adapter *adapter, const void *cmd, | |
265 | int size, void *rpl) | |
266 | { | |
267 | return t4vf_wr_mbox_core(adapter, cmd, size, rpl, false); | |
268 | } | |
269 | ||
622c62b5 SR |
270 | static inline int is_t4(enum chip_type chip) |
271 | { | |
70ee3666 | 272 | return CHELSIO_CHIP_VERSION(chip) == CHELSIO_T4; |
622c62b5 SR |
273 | } |
274 | ||
d289f864 BP |
275 | int t4vf_wait_dev_ready(struct adapter *); |
276 | int t4vf_port_init(struct adapter *, int); | |
16f8bd4b | 277 | |
e68e6133 | 278 | int t4vf_fw_reset(struct adapter *); |
16f8bd4b CL |
279 | int t4vf_set_params(struct adapter *, unsigned int, const u32 *, const u32 *); |
280 | ||
281 | int t4vf_get_sge_params(struct adapter *); | |
282 | int t4vf_get_vpd_params(struct adapter *); | |
283 | int t4vf_get_dev_params(struct adapter *); | |
284 | int t4vf_get_rss_glb_config(struct adapter *); | |
285 | int t4vf_get_vfres(struct adapter *); | |
286 | ||
287 | int t4vf_read_rss_vi_config(struct adapter *, unsigned int, | |
288 | union rss_vi_config *); | |
289 | int t4vf_write_rss_vi_config(struct adapter *, unsigned int, | |
290 | union rss_vi_config *); | |
291 | int t4vf_config_rss_range(struct adapter *, unsigned int, int, int, | |
292 | const u16 *, int); | |
293 | ||
294 | int t4vf_alloc_vi(struct adapter *, int); | |
295 | int t4vf_free_vi(struct adapter *, int); | |
296 | int t4vf_enable_vi(struct adapter *, unsigned int, bool, bool); | |
297 | int t4vf_identify_port(struct adapter *, unsigned int, unsigned int); | |
298 | ||
299 | int t4vf_set_rxmode(struct adapter *, unsigned int, int, int, int, int, int, | |
300 | bool); | |
301 | int t4vf_alloc_mac_filt(struct adapter *, unsigned int, bool, unsigned int, | |
302 | const u8 **, u16 *, u64 *, bool); | |
303 | int t4vf_change_mac(struct adapter *, unsigned int, int, const u8 *, bool); | |
304 | int t4vf_set_addr_hash(struct adapter *, unsigned int, bool, u64, bool); | |
305 | int t4vf_get_port_stats(struct adapter *, int, struct t4vf_port_stats *); | |
306 | ||
307 | int t4vf_iq_free(struct adapter *, unsigned int, unsigned int, unsigned int, | |
308 | unsigned int); | |
309 | int t4vf_eth_eq_free(struct adapter *, unsigned int); | |
310 | ||
311 | int t4vf_handle_fw_rpl(struct adapter *, const __be64 *); | |
312 | ||
313 | #endif /* __T4VF_COMMON_H__ */ |