[deliverable/linux.git] / drivers / net / ethernet / chelsio / cxgb4vf / t4vf_common.h

/*
 * This file is part of the Chelsio T4 PCI-E SR-IOV Virtual Function Ethernet
 * driver for Linux.
 *
 * Copyright (c) 2009-2010 Chelsio Communications, Inc. All rights reserved.
 *
 * This software is available to you under a choice of one of two
 * licenses.  You may choose to be licensed under the terms of the GNU
 * General Public License (GPL) Version 2, available from the file
 * COPYING in the main directory of this source tree, or the
 * OpenIB.org BSD license below:
 *
 *     Redistribution and use in source and binary forms, with or
 *     without modification, are permitted provided that the following
 *     conditions are met:
 *
 *      - Redistributions of source code must retain the above
 *        copyright notice, this list of conditions and the following
 *        disclaimer.
 *
 *      - Redistributions in binary form must reproduce the above
 *        copyright notice, this list of conditions and the following
 *        disclaimer in the documentation and/or other materials
 *        provided with the distribution.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
 * SOFTWARE.
 */

#ifndef __T4VF_COMMON_H__
#define __T4VF_COMMON_H__

#include "../cxgb4/t4fw_api.h"

#define CHELSIO_CHIP_CODE(version, revision) (((version) << 4) | (revision))
#define CHELSIO_CHIP_VERSION(code) (((code) >> 4) & 0xf)
#define CHELSIO_CHIP_RELEASE(code) ((code) & 0xf)

/* All T4 and later chips have their PCI-E Device IDs encoded as 0xVFPP where:
 *
 *   V  = "4" for T4; "5" for T5, etc. or
 *      = "a" for T4 FPGA; "b" for T4 FPGA, etc.
 *   F  = "0" for PF 0..3; "4".."7" for PF4..7; and "8" for VFs
 *   PP = adapter product designation
 */
#define CHELSIO_T4		0x4
#define CHELSIO_T5		0x5

enum chip_type {
	T4_A1 = CHELSIO_CHIP_CODE(CHELSIO_T4, 1),
	T4_A2 = CHELSIO_CHIP_CODE(CHELSIO_T4, 2),
	T4_FIRST_REV	= T4_A1,
	T4_LAST_REV	= T4_A2,

	T5_A0 = CHELSIO_CHIP_CODE(CHELSIO_T5, 0),
	T5_A1 = CHELSIO_CHIP_CODE(CHELSIO_T5, 1),
	T5_FIRST_REV	= T5_A0,
	T5_LAST_REV	= T5_A1,
};

/*
 * The "len16" field of a Firmware Command Structure ...
 */
#define FW_LEN16(fw_struct) FW_CMD_LEN16(sizeof(fw_struct) / 16)

/*
 * Per-VF statistics.
 */
struct t4vf_port_stats {
	/*
	 * TX statistics.
	 */
	u64 tx_bcast_bytes;		/* broadcast */
	u64 tx_bcast_frames;
	u64 tx_mcast_bytes;		/* multicast */
	u64 tx_mcast_frames;
	u64 tx_ucast_bytes;		/* unicast */
	u64 tx_ucast_frames;
	u64 tx_drop_frames;		/* TX dropped frames */
	u64 tx_offload_bytes;		/* offload */
	u64 tx_offload_frames;

	/*
	 * RX statistics.
	 */
	u64 rx_bcast_bytes;		/* broadcast */
	u64 rx_bcast_frames;
	u64 rx_mcast_bytes;		/* multicast */
	u64 rx_mcast_frames;
	u64 rx_ucast_bytes;
	u64 rx_ucast_frames;		/* unicast */

	u64 rx_err_frames;		/* RX error frames */
};

/*
 * Per-"port" (Virtual Interface) link configuration ...
 */
struct link_config {
	unsigned int   supported;        /* link capabilities */
	unsigned int   advertising;      /* advertised capabilities */
	unsigned short requested_speed;  /* speed user has requested */
	unsigned short speed;            /* actual link speed */
	unsigned char  requested_fc;     /* flow control user has requested */
	unsigned char  fc;               /* actual link flow control */
	unsigned char  autoneg;          /* autonegotiating? */
	unsigned char  link_ok;          /* link up? */
};

enum {
	PAUSE_RX      = 1 << 0,
	PAUSE_TX      = 1 << 1,
	PAUSE_AUTONEG = 1 << 2
};

/*
 * General device parameters ...
 */
struct dev_params {
	u32 fwrev;			/* firmware version */
	u32 tprev;			/* TP Microcode Version */
};

/*
 * Scatter Gather Engine parameters.  These are almost all determined by the
 * Physical Function Driver.  We just need to grab them to see within which
 * environment we're playing ...
 */
struct sge_params {
	u32 sge_control;		/* padding, boundaries, lengths, etc. */
	u32 sge_control2;		/* T5: more of the same */
	u32 sge_host_page_size;		/* RDMA page sizes */
	u32 sge_queues_per_page;	/* RDMA queues/page */
	u32 sge_user_mode_limits;	/* limits for BAR2 user mode accesses */
	u32 sge_fl_buffer_size[16];	/* free list buffer sizes */
	u32 sge_ingress_rx_threshold;	/* RX counter interrupt threshold[4] */
	u32 sge_timer_value_0_and_1;	/* interrupt coalescing timer values */
	u32 sge_timer_value_2_and_3;
	u32 sge_timer_value_4_and_5;
};

/*
 * Vital Product Data parameters.
 */
struct vpd_params {
	u32 cclk;			/* Core Clock (KHz) */
};

/*
 * Global Receive Side Scaling (RSS) parameters in host-native format.
 */
struct rss_params {
	unsigned int mode;		/* RSS mode */
	union {
	    struct {
		unsigned int synmapen:1;	/* SYN Map Enable */
		unsigned int syn4tupenipv6:1;	/* enable hashing 4-tuple IPv6 SYNs */
		unsigned int syn2tupenipv6:1;	/* enable hashing 2-tuple IPv6 SYNs */
		unsigned int syn4tupenipv4:1;	/* enable hashing 4-tuple IPv4 SYNs */
		unsigned int syn2tupenipv4:1;	/* enable hashing 2-tuple IPv4 SYNs */
		unsigned int ofdmapen:1;	/* Offload Map Enable */
		unsigned int tnlmapen:1;	/* Tunnel Map Enable */
		unsigned int tnlalllookup:1;	/* Tunnel All Lookup */
		unsigned int hashtoeplitz:1;	/* use Toeplitz hash */
	    } basicvirtual;
	} u;
};

/*
 * Virtual Interface RSS Configuration in host-native format.
 */
union rss_vi_config {
    struct {
	u16 defaultq;			/* Ingress Queue ID for !tnlalllookup */
	unsigned int ip6fourtupen:1;	/* hash 4-tuple IPv6 ingress packets */
	unsigned int ip6twotupen:1;	/* hash 2-tuple IPv6 ingress packets */
	unsigned int ip4fourtupen:1;	/* hash 4-tuple IPv4 ingress packets */
	unsigned int ip4twotupen:1;	/* hash 2-tuple IPv4 ingress packets */
	int udpen;			/* hash 4-tuple UDP ingress packets */
    } basicvirtual;
};

/*
 * Maximum resources provisioned for a PCI VF.
 */
struct vf_resources {
	unsigned int nvi;		/* N virtual interfaces */
	unsigned int neq;		/* N egress Qs */
	unsigned int nethctrl;		/* N egress ETH or CTRL Qs */
	unsigned int niqflint;		/* N ingress Qs/w free list(s) & intr */
	unsigned int niq;		/* N ingress Qs */
	unsigned int tc;		/* PCI-E traffic class */
	unsigned int pmask;		/* port access rights mask */
	unsigned int nexactf;		/* N exact MPS filters */
	unsigned int r_caps;		/* read capabilities */
	unsigned int wx_caps;		/* write/execute capabilities */
};

/*
 * Per-"adapter" (Virtual Function) parameters.
 */
struct adapter_params {
	struct dev_params dev;		/* general device parameters */
	struct sge_params sge;		/* Scatter Gather Engine */
	struct vpd_params vpd;		/* Vital Product Data */
	struct rss_params rss;		/* Receive Side Scaling */
	struct vf_resources vfres;	/* Virtual Function Resource limits */
	enum chip_type chip;		/* chip code */
	u8 nports;			/* # of Ethernet "ports" */
};

#include "adapter.h"

#ifndef PCI_VENDOR_ID_CHELSIO
# define PCI_VENDOR_ID_CHELSIO 0x1425
#endif

#define for_each_port(adapter, iter) \
	for (iter = 0; iter < (adapter)->params.nports; iter++)

static inline bool is_10g_port(const struct link_config *lc)
{
	return (lc->supported & SUPPORTED_10000baseT_Full) != 0;
}

static inline bool is_x_10g_port(const struct link_config *lc)
{
	return (lc->supported & FW_PORT_CAP_SPEED_10G) != 0 ||
		(lc->supported & FW_PORT_CAP_SPEED_40G) != 0;
}

static inline unsigned int core_ticks_per_usec(const struct adapter *adapter)
{
	return adapter->params.vpd.cclk / 1000;
}

static inline unsigned int us_to_core_ticks(const struct adapter *adapter,
					    unsigned int us)
{
	return (us * adapter->params.vpd.cclk) / 1000;
}

static inline unsigned int core_ticks_to_us(const struct adapter *adapter,
					    unsigned int ticks)
{
	return (ticks * 1000) / adapter->params.vpd.cclk;
}

int t4vf_wr_mbox_core(struct adapter *, const void *, int, void *, bool);

static inline int t4vf_wr_mbox(struct adapter *adapter, const void *cmd,
			       int size, void *rpl)
{
	return t4vf_wr_mbox_core(adapter, cmd, size, rpl, true);
}

static inline int t4vf_wr_mbox_ns(struct adapter *adapter, const void *cmd,
				  int size, void *rpl)
{
	return t4vf_wr_mbox_core(adapter, cmd, size, rpl, false);
}

static inline int is_t4(enum chip_type chip)
{
	return CHELSIO_CHIP_VERSION(chip) == CHELSIO_T4;
}

int t4vf_wait_dev_ready(struct adapter *);
int t4vf_port_init(struct adapter *, int);

int t4vf_fw_reset(struct adapter *);
int t4vf_set_params(struct adapter *, unsigned int, const u32 *, const u32 *);

int t4vf_get_sge_params(struct adapter *);
int t4vf_get_vpd_params(struct adapter *);
int t4vf_get_dev_params(struct adapter *);
int t4vf_get_rss_glb_config(struct adapter *);
int t4vf_get_vfres(struct adapter *);

int t4vf_read_rss_vi_config(struct adapter *, unsigned int,
			    union rss_vi_config *);
int t4vf_write_rss_vi_config(struct adapter *, unsigned int,
			     union rss_vi_config *);
int t4vf_config_rss_range(struct adapter *, unsigned int, int, int,
			  const u16 *, int);

int t4vf_alloc_vi(struct adapter *, int);
int t4vf_free_vi(struct adapter *, int);
int t4vf_enable_vi(struct adapter *, unsigned int, bool, bool);
int t4vf_identify_port(struct adapter *, unsigned int, unsigned int);

int t4vf_set_rxmode(struct adapter *, unsigned int, int, int, int, int, int,
		    bool);
int t4vf_alloc_mac_filt(struct adapter *, unsigned int, bool, unsigned int,
			const u8 **, u16 *, u64 *, bool);
int t4vf_change_mac(struct adapter *, unsigned int, int, const u8 *, bool);
int t4vf_set_addr_hash(struct adapter *, unsigned int, bool, u64, bool);
int t4vf_get_port_stats(struct adapter *, int, struct t4vf_port_stats *);

int t4vf_iq_free(struct adapter *, unsigned int, unsigned int, unsigned int,
		 unsigned int);
int t4vf_eth_eq_free(struct adapter *, unsigned int);

int t4vf_handle_fw_rpl(struct adapter *, const __be64 *);

#endif /* __T4VF_COMMON_H__ */
Commit	Line	Data
16f8bd4b CL	1	/*
	2	* This file is part of the Chelsio T4 PCI-E SR-IOV Virtual Function Ethernet
	3	* driver for Linux.
	4	*
	5	* Copyright (c) 2009-2010 Chelsio Communications, Inc. All rights reserved.
	6	*
	7	* This software is available to you under a choice of one of two
	8	* licenses. You may choose to be licensed under the terms of the GNU
	9	* General Public License (GPL) Version 2, available from the file
	10	* COPYING in the main directory of this source tree, or the
	11	* OpenIB.org BSD license below:
	12	*
	13	* Redistribution and use in source and binary forms, with or
	14	* without modification, are permitted provided that the following
	15	* conditions are met:
	16	*
	17	* - Redistributions of source code must retain the above
	18	* copyright notice, this list of conditions and the following
	19	* disclaimer.
	20	*
	21	* - Redistributions in binary form must reproduce the above
	22	* copyright notice, this list of conditions and the following
	23	* disclaimer in the documentation and/or other materials
	24	* provided with the distribution.
	25	*
	26	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	27	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
	28	* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	29	* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
	30	* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
	31	* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
	32	* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
	33	* SOFTWARE.
	34	*/
	35
	36	#ifndef __T4VF_COMMON_H__
	37	#define __T4VF_COMMON_H__
	38
	39	#include "../cxgb4/t4fw_api.h"
	40
622c62b5	41	#define CHELSIO_CHIP_CODE(version, revision) (((version) << 4) \| (revision))
70ee3666	42	#define CHELSIO_CHIP_VERSION(code) (((code) >> 4) & 0xf)
622c62b5 SR	43	#define CHELSIO_CHIP_RELEASE(code) ((code) & 0xf)
622c62b5 SR	44
70ee3666 HS	45	/* All T4 and later chips have their PCI-E Device IDs encoded as 0xVFPP where:
	46	*
	47	* V = "4" for T4; "5" for T5, etc. or
	48	* = "a" for T4 FPGA; "b" for T4 FPGA, etc.
	49	* F = "0" for PF 0..3; "4".."7" for PF4..7; and "8" for VFs
	50	* PP = adapter product designation
	51	*/
622c62b5 SR	52	#define CHELSIO_T4 0x4
	53	#define CHELSIO_T5 0x5
	54
	55	enum chip_type {
70ee3666 HS	56	T4_A1 = CHELSIO_CHIP_CODE(CHELSIO_T4, 1),
70ee3666 HS	57	T4_A2 = CHELSIO_CHIP_CODE(CHELSIO_T4, 2),
622c62b5	58	T4_FIRST_REV = T4_A1,
70ee3666	59	T4_LAST_REV = T4_A2,
622c62b5	60
70ee3666 HS	61	T5_A0 = CHELSIO_CHIP_CODE(CHELSIO_T5, 0),
	62	T5_A1 = CHELSIO_CHIP_CODE(CHELSIO_T5, 1),
	63	T5_FIRST_REV = T5_A0,
622c62b5 SR	64	T5_LAST_REV = T5_A1,
	65	};
	66
16f8bd4b CL	67	/*
	68	* The "len16" field of a Firmware Command Structure ...
	69	*/
	70	#define FW_LEN16(fw_struct) FW_CMD_LEN16(sizeof(fw_struct) / 16)
	71
	72	/*
	73	* Per-VF statistics.
	74	*/
	75	struct t4vf_port_stats {
	76	/*
	77	* TX statistics.
	78	*/
	79	u64 tx_bcast_bytes; /* broadcast */
	80	u64 tx_bcast_frames;
	81	u64 tx_mcast_bytes; /* multicast */
	82	u64 tx_mcast_frames;
	83	u64 tx_ucast_bytes; /* unicast */
	84	u64 tx_ucast_frames;
	85	u64 tx_drop_frames; /* TX dropped frames */
	86	u64 tx_offload_bytes; /* offload */
	87	u64 tx_offload_frames;
	88
	89	/*
	90	* RX statistics.
	91	*/
	92	u64 rx_bcast_bytes; /* broadcast */
	93	u64 rx_bcast_frames;
	94	u64 rx_mcast_bytes; /* multicast */
	95	u64 rx_mcast_frames;
	96	u64 rx_ucast_bytes;
	97	u64 rx_ucast_frames; /* unicast */
	98
	99	u64 rx_err_frames; /* RX error frames */
	100	};
	101
	102	/*
	103	* Per-"port" (Virtual Interface) link configuration ...
	104	*/
	105	struct link_config {
	106	unsigned int supported; /* link capabilities */
	107	unsigned int advertising; /* advertised capabilities */
	108	unsigned short requested_speed; /* speed user has requested */
	109	unsigned short speed; /* actual link speed */
	110	unsigned char requested_fc; /* flow control user has requested */
	111	unsigned char fc; /* actual link flow control */
	112	unsigned char autoneg; /* autonegotiating? */
	113	unsigned char link_ok; /* link up? */
	114	};
	115
	116	enum {
	117	PAUSE_RX = 1 << 0,
	118	PAUSE_TX = 1 << 1,
	119	PAUSE_AUTONEG = 1 << 2
	120	};
	121
	122	/*
	123	* General device parameters ...
	124	*/
	125	struct dev_params {
	126	u32 fwrev; /* firmware version */
	127	u32 tprev; /* TP Microcode Version */
	128	};
	129
	130	/*
131	* Scatter Gather Engine parameters. These are almost all determined by the
132	* Physical Function Driver. We just need to grab them to see within which
133	* environment we're playing ...
134	*/
135	struct sge_params {
136	u32 sge_control; /* padding, boundaries, lengths, etc. */
ce8f407a	137	u32 sge_control2; /* T5: more of the same */
16f8bd4b CL	138	u32 sge_host_page_size; /* RDMA page sizes */
	139	u32 sge_queues_per_page; /* RDMA queues/page */
	140	u32 sge_user_mode_limits; /* limits for BAR2 user mode accesses */
	141	u32 sge_fl_buffer_size[16]; /* free list buffer sizes */
	142	u32 sge_ingress_rx_threshold; /* RX counter interrupt threshold[4] */
	143	u32 sge_timer_value_0_and_1; /* interrupt coalescing timer values */
	144	u32 sge_timer_value_2_and_3;
	145	u32 sge_timer_value_4_and_5;
	146	};
	147
	148	/*
	149	* Vital Product Data parameters.
	150	*/
	151	struct vpd_params {
	152	u32 cclk; /* Core Clock (KHz) */
	153	};
	154
	155	/*
	156	* Global Receive Side Scaling (RSS) parameters in host-native format.
	157	*/
	158	struct rss_params {
	159	unsigned int mode; /* RSS mode */
	160	union {
	161	struct {
65495745 HH	162	unsigned int synmapen:1; /* SYN Map Enable */
	163	unsigned int syn4tupenipv6:1; /* enable hashing 4-tuple IPv6 SYNs */
	164	unsigned int syn2tupenipv6:1; /* enable hashing 2-tuple IPv6 SYNs */
	165	unsigned int syn4tupenipv4:1; /* enable hashing 4-tuple IPv4 SYNs */
	166	unsigned int syn2tupenipv4:1; /* enable hashing 2-tuple IPv4 SYNs */
	167	unsigned int ofdmapen:1; /* Offload Map Enable */
	168	unsigned int tnlmapen:1; /* Tunnel Map Enable */
	169	unsigned int tnlalllookup:1; /* Tunnel All Lookup */
	170	unsigned int hashtoeplitz:1; /* use Toeplitz hash */
16f8bd4b CL	171	} basicvirtual;
	172	} u;
	173	};
	174
	175	/*
	176	* Virtual Interface RSS Configuration in host-native format.
	177	*/
	178	union rss_vi_config {
	179	struct {
	180	u16 defaultq; /* Ingress Queue ID for !tnlalllookup */
65495745 HH	181	unsigned int ip6fourtupen:1; /* hash 4-tuple IPv6 ingress packets */
	182	unsigned int ip6twotupen:1; /* hash 2-tuple IPv6 ingress packets */
	183	unsigned int ip4fourtupen:1; /* hash 4-tuple IPv4 ingress packets */
	184	unsigned int ip4twotupen:1; /* hash 2-tuple IPv4 ingress packets */
16f8bd4b CL	185	int udpen; /* hash 4-tuple UDP ingress packets */
	186	} basicvirtual;
	187	};
	188
	189	/*
	190	* Maximum resources provisioned for a PCI VF.
	191	*/
	192	struct vf_resources {
	193	unsigned int nvi; /* N virtual interfaces */
	194	unsigned int neq; /* N egress Qs */
	195	unsigned int nethctrl; /* N egress ETH or CTRL Qs */
	196	unsigned int niqflint; /* N ingress Qs/w free list(s) & intr */
	197	unsigned int niq; /* N ingress Qs */
	198	unsigned int tc; /* PCI-E traffic class */
	199	unsigned int pmask; /* port access rights mask */
	200	unsigned int nexactf; /* N exact MPS filters */
	201	unsigned int r_caps; /* read capabilities */
	202	unsigned int wx_caps; /* write/execute capabilities */
	203	};
	204
	205	/*
	206	* Per-"adapter" (Virtual Function) parameters.
	207	*/
	208	struct adapter_params {
	209	struct dev_params dev; /* general device parameters */
	210	struct sge_params sge; /* Scatter Gather Engine */
	211	struct vpd_params vpd; /* Vital Product Data */
	212	struct rss_params rss; /* Receive Side Scaling */
	213	struct vf_resources vfres; /* Virtual Function Resource limits */
70ee3666	214	enum chip_type chip; /* chip code */
16f8bd4b CL	215	u8 nports; /* # of Ethernet "ports" */
	216	};
	217
	218	#include "adapter.h"
	219
	220	#ifndef PCI_VENDOR_ID_CHELSIO
	221	# define PCI_VENDOR_ID_CHELSIO 0x1425
	222	#endif
	223
	224	#define for_each_port(adapter, iter) \
	225	for (iter = 0; iter < (adapter)->params.nports; iter++)
	226
	227	static inline bool is_10g_port(const struct link_config *lc)
	228	{
	229	return (lc->supported & SUPPORTED_10000baseT_Full) != 0;
	230	}
	231
897d55df HS	232	static inline bool is_x_10g_port(const struct link_config *lc)
	233	{
	234	return (lc->supported & FW_PORT_CAP_SPEED_10G) != 0 \|\|
	235	(lc->supported & FW_PORT_CAP_SPEED_40G) != 0;
	236	}
	237
16f8bd4b CL	238	static inline unsigned int core_ticks_per_usec(const struct adapter *adapter)
	239	{
	240	return adapter->params.vpd.cclk / 1000;
	241	}
	242
	243	static inline unsigned int us_to_core_ticks(const struct adapter *adapter,
	244	unsigned int us)
	245	{
	246	return (us * adapter->params.vpd.cclk) / 1000;
	247	}
	248
	249	static inline unsigned int core_ticks_to_us(const struct adapter *adapter,
	250	unsigned int ticks)
	251	{
	252	return (ticks * 1000) / adapter->params.vpd.cclk;
	253	}
	254
	255	int t4vf_wr_mbox_core(struct adapter , const void , int, void *, bool);
	256
	257	static inline int t4vf_wr_mbox(struct adapter adapter, const void cmd,
	258	int size, void *rpl)
	259	{
	260	return t4vf_wr_mbox_core(adapter, cmd, size, rpl, true);
	261	}
	262
	263	static inline int t4vf_wr_mbox_ns(struct adapter adapter, const void cmd,
	264	int size, void *rpl)
	265	{
	266	return t4vf_wr_mbox_core(adapter, cmd, size, rpl, false);
	267	}
	268
622c62b5 SR	269	static inline int is_t4(enum chip_type chip)
622c62b5 SR	270	{
70ee3666	271	return CHELSIO_CHIP_VERSION(chip) == CHELSIO_T4;
622c62b5 SR	272	}
622c62b5 SR	273
d289f864 BP	274	int t4vf_wait_dev_ready(struct adapter *);
d289f864 BP	275	int t4vf_port_init(struct adapter *, int);
16f8bd4b	276
e68e6133	277	int t4vf_fw_reset(struct adapter *);
16f8bd4b CL	278	int t4vf_set_params(struct adapter , unsigned int, const u32 , const u32 *);
	279
	280	int t4vf_get_sge_params(struct adapter *);
	281	int t4vf_get_vpd_params(struct adapter *);
	282	int t4vf_get_dev_params(struct adapter *);
	283	int t4vf_get_rss_glb_config(struct adapter *);
	284	int t4vf_get_vfres(struct adapter *);
	285
	286	int t4vf_read_rss_vi_config(struct adapter *, unsigned int,
	287	union rss_vi_config *);
	288	int t4vf_write_rss_vi_config(struct adapter *, unsigned int,
	289	union rss_vi_config *);
	290	int t4vf_config_rss_range(struct adapter *, unsigned int, int, int,
	291	const u16 *, int);
	292
	293	int t4vf_alloc_vi(struct adapter *, int);
	294	int t4vf_free_vi(struct adapter *, int);
	295	int t4vf_enable_vi(struct adapter *, unsigned int, bool, bool);
	296	int t4vf_identify_port(struct adapter *, unsigned int, unsigned int);
	297
	298	int t4vf_set_rxmode(struct adapter *, unsigned int, int, int, int, int, int,
	299	bool);
	300	int t4vf_alloc_mac_filt(struct adapter *, unsigned int, bool, unsigned int,
	301	const u8 *, u16 , u64 *, bool);
	302	int t4vf_change_mac(struct adapter , unsigned int, int, const u8 , bool);
	303	int t4vf_set_addr_hash(struct adapter *, unsigned int, bool, u64, bool);
	304	int t4vf_get_port_stats(struct adapter , int, struct t4vf_port_stats );
	305
	306	int t4vf_iq_free(struct adapter *, unsigned int, unsigned int, unsigned int,
	307	unsigned int);
	308	int t4vf_eth_eq_free(struct adapter *, unsigned int);
	309
	310	int t4vf_handle_fw_rpl(struct adapter , const __be64 );
	311
	312	#endif /* __T4VF_COMMON_H__ */