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dm9000: handle initial link status
[deliverable/linux.git] / drivers / net / ethernet / davicom / dm9000.c
CommitLineData
a1365275 1/*
41c340f0 2 * Davicom DM9000 Fast Ethernet driver for Linux.
a1365275
SH		 3 * Copyright (C) 1997 Sten Wang
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
41c340f0 15 * (C) Copyright 1997-1998 DAVICOM Semiconductor,Inc. All Rights Reserved.
9ef9ac51 16 *
41c340f0
BD		 17 * Additional updates, Copyright:
18 * Ben Dooks <ben@simtec.co.uk>
19 * Sascha Hauer <s.hauer@pengutronix.de>
a1365275
SH		 20 */
21
22#include <linux/module.h>
23#include <linux/ioport.h>
24#include <linux/netdevice.h>
25#include <linux/etherdevice.h>
a6b7a407 26#include <linux/interrupt.h>
a1365275 27#include <linux/skbuff.h>
a1365275
SH		 28#include <linux/spinlock.h>
29#include <linux/crc32.h>
30#include <linux/mii.h>
0b8bf1ba
TF		 31#include <linux/of.h>
32#include <linux/of_net.h>
7da99859 33#include <linux/ethtool.h>
a1365275
SH		 34#include <linux/dm9000.h>
35#include <linux/delay.h>
d052d1be 36#include <linux/platform_device.h>
4e4fc05a 37#include <linux/irq.h>
5a0e3ad6 38#include <linux/slab.h>
a1365275
SH		 39
40#include <asm/delay.h>
41#include <asm/irq.h>
42#include <asm/io.h>
43
44#include "dm9000.h"
45
46/* Board/System/Debug information/definition ---------------- */
47
48#define DM9000_PHY 0x40 /* PHY address 0x01 */
49
59eae1fa
BD		 50#define CARDNAME "dm9000"
51#define DRV_VERSION "1.31"
a1365275 52
a1365275
SH		 53/*
54 * Transmit timeout, default 5 seconds.
55 */
56static int watchdog = 5000;
57module_param(watchdog, int, 0400);
58MODULE_PARM_DESC(watchdog, "transmit timeout in milliseconds");
59
2e025c71
VZ		 60/*
61 * Debug messages level
62 */
63static int debug;
64module_param(debug, int, 0644);
65MODULE_PARM_DESC(debug, "dm9000 debug level (0-4)");
66
9a2f037c
BD		 67/* DM9000 register address locking.
68 *
69 * The DM9000 uses an address register to control where data written
70 * to the data register goes. This means that the address register
71 * must be preserved over interrupts or similar calls.
72 *
73 * During interrupt and other critical calls, a spinlock is used to
74 * protect the system, but the calls themselves save the address
75 * in the address register in case they are interrupting another
76 * access to the device.
77 *
78 * For general accesses a lock is provided so that calls which are
79 * allowed to sleep are serialised so that the address register does
80 * not need to be saved. This lock also serves to serialise access
81 * to the EEPROM and PHY access registers which are shared between
82 * these two devices.
83 */
84
6d406b3c
BD		 85/* The driver supports the original DM9000E, and now the two newer
86 * devices, DM9000A and DM9000B.
87 */
88
89enum dm9000_type {
90 TYPE_DM9000E, /* original DM9000 */
91 TYPE_DM9000A,
92 TYPE_DM9000B
93};
94
a1365275
SH		 95/* Structure/enum declaration ------------------------------- */
96typedef struct board_info {
97
59eae1fa
BD		 98 void __iomem *io_addr; /* Register I/O base address */
99 void __iomem *io_data; /* Data I/O address */
100 u16 irq; /* IRQ */
a1365275 101
59eae1fa
BD		 102 u16 tx_pkt_cnt;
103 u16 queue_pkt_len;
104 u16 queue_start_addr;
5dcc60b7 105 u16 queue_ip_summed;
59eae1fa
BD		 106 u16 dbug_cnt;
107 u8 io_mode; /* 0:word, 2:byte */
108 u8 phy_addr;
109 u8 imr_all;
110
111 unsigned int flags;
5b22721d
BS		 112 unsigned int in_suspend:1;
113 unsigned int wake_supported:1;
a1365275 114
6d406b3c 115 enum dm9000_type type;
5b2b4ff0 116
a1365275
SH		 117 void (*inblk)(void __iomem *port, void *data, int length);
118 void (*outblk)(void __iomem *port, void *data, int length);
119 void (*dumpblk)(void __iomem *port, int length);
120
a76836f9
BD		 121 struct device *dev; /* parent device */
122
a1365275
SH		 123 struct resource *addr_res; /* resources found */
124 struct resource *data_res;
125 struct resource *addr_req; /* resources requested */
126 struct resource *data_req;
127 struct resource *irq_res;
128
c029f444
BD		 129 int irq_wake;
130
9a2f037c
BD		 131 struct mutex addr_lock; /* phy and eeprom access lock */
132
8f5bf5f2
BD		 133 struct delayed_work phy_poll;
134 struct net_device *ndev;
135
59eae1fa 136 spinlock_t lock;
a1365275
SH		 137
138 struct mii_if_info mii;
59eae1fa 139 u32 msg_enable;
c029f444 140 u32 wake_state;
5dcc60b7 141
5dcc60b7 142 int ip_summed;
a1365275
SH		 143} board_info_t;
144
5b2b4ff0
BD		 145/* debug code */
146
147#define dm9000_dbg(db, lev, msg...) do { \
2e025c71 148 if ((lev) < debug) { \
5b2b4ff0
BD		 149 dev_dbg(db->dev, msg); \
150 } \
151} while (0)
152
7da99859
BD		 153static inline board_info_t *to_dm9000_board(struct net_device *dev)
154{
4cf1653a 155 return netdev_priv(dev);
7da99859
BD		 156}
157
a1365275
SH		 158/* DM9000 network board routine ---------------------------- */
159
a1365275
SH		 160/*
161 * Read a byte from I/O port
162 */
163static u8
5b22721d 164ior(board_info_t *db, int reg)
a1365275
SH		 165{
166 writeb(reg, db->io_addr);
167 return readb(db->io_data);
168}
169
170/*
171 * Write a byte to I/O port
172 */
173
174static void
5b22721d 175iow(board_info_t *db, int reg, int value)
a1365275
SH		 176{
177 writeb(reg, db->io_addr);
178 writeb(value, db->io_data);
179}
180
09ee9f87
MA		 181static void
182dm9000_reset(board_info_t *db)
183{
184 dev_dbg(db->dev, "resetting device\n");
185
186 /* Reset DM9000, see DM9000 Application Notes V1.22 Jun 11, 2004 page 29
187 * The essential point is that we have to do a double reset, and the
188 * instruction is to set LBK into MAC internal loopback mode.
189 */
751bb6fd 190 iow(db, DM9000_NCR, NCR_RST | NCR_MAC_LBK);
09ee9f87
MA		 191 udelay(100); /* Application note says at least 20 us */
192 if (ior(db, DM9000_NCR) & 1)
193 dev_err(db->dev, "dm9000 did not respond to first reset\n");
194
195 iow(db, DM9000_NCR, 0);
751bb6fd 196 iow(db, DM9000_NCR, NCR_RST | NCR_MAC_LBK);
09ee9f87
MA		 197 udelay(100);
198 if (ior(db, DM9000_NCR) & 1)
199 dev_err(db->dev, "dm9000 did not respond to second reset\n");
200}
201
a1365275
SH		 202/* routines for sending block to chip */
203
204static void dm9000_outblk_8bit(void __iomem *reg, void *data, int count)
205{
daadaf6f 206 iowrite8_rep(reg, data, count);
a1365275
SH		 207}
208
209static void dm9000_outblk_16bit(void __iomem *reg, void *data, int count)
210{
daadaf6f 211 iowrite16_rep(reg, data, (count+1) >> 1);
a1365275
SH		 212}
213
214static void dm9000_outblk_32bit(void __iomem *reg, void *data, int count)
215{
daadaf6f 216 iowrite32_rep(reg, data, (count+3) >> 2);
a1365275
SH		 217}
218
219/* input block from chip to memory */
220
221static void dm9000_inblk_8bit(void __iomem *reg, void *data, int count)
222{
daadaf6f 223 ioread8_rep(reg, data, count);
a1365275
SH		 224}
225
226
227static void dm9000_inblk_16bit(void __iomem *reg, void *data, int count)
228{
daadaf6f 229 ioread16_rep(reg, data, (count+1) >> 1);
a1365275
SH		 230}
231
232static void dm9000_inblk_32bit(void __iomem *reg, void *data, int count)
233{
daadaf6f 234 ioread32_rep(reg, data, (count+3) >> 2);
a1365275
SH		 235}
236
237/* dump block from chip to null */
238
239static void dm9000_dumpblk_8bit(void __iomem *reg, int count)
240{
241 int i;
242 int tmp;
243
244 for (i = 0; i < count; i++)
245 tmp = readb(reg);
246}
247
248static void dm9000_dumpblk_16bit(void __iomem *reg, int count)
249{
250 int i;
251 int tmp;
252
253 count = (count + 1) >> 1;
254
255 for (i = 0; i < count; i++)
256 tmp = readw(reg);
257}
258
259static void dm9000_dumpblk_32bit(void __iomem *reg, int count)
260{
261 int i;
262 int tmp;
263
264 count = (count + 3) >> 2;
265
266 for (i = 0; i < count; i++)
267 tmp = readl(reg);
268}
269
6741f40d
JC		 270/*
271 * Sleep, either by using msleep() or if we are suspending, then
272 * use mdelay() to sleep.
273 */
274static void dm9000_msleep(board_info_t *db, unsigned int ms)
275{
276 if (db->in_suspend)
277 mdelay(ms);
278 else
279 msleep(ms);
280}
281
282/* Read a word from phyxcer */
283static int
284dm9000_phy_read(struct net_device *dev, int phy_reg_unused, int reg)
285{
286 board_info_t *db = netdev_priv(dev);
287 unsigned long flags;
288 unsigned int reg_save;
289 int ret;
290
291 mutex_lock(&db->addr_lock);
292
293 spin_lock_irqsave(&db->lock, flags);
294
295 /* Save previous register address */
296 reg_save = readb(db->io_addr);
297
298 /* Fill the phyxcer register into REG_0C */
299 iow(db, DM9000_EPAR, DM9000_PHY | reg);
300
301 /* Issue phyxcer read command */
302 iow(db, DM9000_EPCR, EPCR_ERPRR | EPCR_EPOS);
303
304 writeb(reg_save, db->io_addr);
305 spin_unlock_irqrestore(&db->lock, flags);
306
307 dm9000_msleep(db, 1); /* Wait read complete */
308
309 spin_lock_irqsave(&db->lock, flags);
310 reg_save = readb(db->io_addr);
311
312 iow(db, DM9000_EPCR, 0x0); /* Clear phyxcer read command */
313
314 /* The read data keeps on REG_0D & REG_0E */
315 ret = (ior(db, DM9000_EPDRH) << 8) | ior(db, DM9000_EPDRL);
316
317 /* restore the previous address */
318 writeb(reg_save, db->io_addr);
319 spin_unlock_irqrestore(&db->lock, flags);
320
321 mutex_unlock(&db->addr_lock);
322
323 dm9000_dbg(db, 5, "phy_read[%02x] -> %04x\n", reg, ret);
324 return ret;
325}
326
327/* Write a word to phyxcer */
328static void
329dm9000_phy_write(struct net_device *dev,
330 int phyaddr_unused, int reg, int value)
331{
332 board_info_t *db = netdev_priv(dev);
333 unsigned long flags;
334 unsigned long reg_save;
335
336 dm9000_dbg(db, 5, "phy_write[%02x] = %04x\n", reg, value);
337 mutex_lock(&db->addr_lock);
338
339 spin_lock_irqsave(&db->lock, flags);
340
341 /* Save previous register address */
342 reg_save = readb(db->io_addr);
343
344 /* Fill the phyxcer register into REG_0C */
345 iow(db, DM9000_EPAR, DM9000_PHY | reg);
346
347 /* Fill the written data into REG_0D & REG_0E */
348 iow(db, DM9000_EPDRL, value);
349 iow(db, DM9000_EPDRH, value >> 8);
350
351 /* Issue phyxcer write command */
352 iow(db, DM9000_EPCR, EPCR_EPOS | EPCR_ERPRW);
353
354 writeb(reg_save, db->io_addr);
355 spin_unlock_irqrestore(&db->lock, flags);
356
357 dm9000_msleep(db, 1); /* Wait write complete */
358
359 spin_lock_irqsave(&db->lock, flags);
360 reg_save = readb(db->io_addr);
361
362 iow(db, DM9000_EPCR, 0x0); /* Clear phyxcer write command */
363
364 /* restore the previous address */
365 writeb(reg_save, db->io_addr);
366
367 spin_unlock_irqrestore(&db->lock, flags);
368 mutex_unlock(&db->addr_lock);
369}
370
a1365275
SH		 371/* dm9000_set_io
372 *
373 * select the specified set of io routines to use with the
374 * device
375 */
376
377static void dm9000_set_io(struct board_info *db, int byte_width)
378{
379 /* use the size of the data resource to work out what IO
380 * routines we want to use
381 */
382
383 switch (byte_width) {
384 case 1:
385 db->dumpblk = dm9000_dumpblk_8bit;
386 db->outblk = dm9000_outblk_8bit;
387 db->inblk = dm9000_inblk_8bit;
388 break;
389
a1365275
SH		 390
391 case 3:
a76836f9
BD		 392 dev_dbg(db->dev, ": 3 byte IO, falling back to 16bit\n");
393 case 2:
a1365275
SH		 394 db->dumpblk = dm9000_dumpblk_16bit;
395 db->outblk = dm9000_outblk_16bit;
396 db->inblk = dm9000_inblk_16bit;
397 break;
398
399 case 4:
400 default:
401 db->dumpblk = dm9000_dumpblk_32bit;
402 db->outblk = dm9000_outblk_32bit;
403 db->inblk = dm9000_inblk_32bit;
404 break;
405 }
406}
407
8f5bf5f2
BD		 408static void dm9000_schedule_poll(board_info_t *db)
409{
6d406b3c
BD		 410 if (db->type == TYPE_DM9000E)
411 schedule_delayed_work(&db->phy_poll, HZ * 2);
8f5bf5f2 412}
a1365275 413
f8d79e79
BD		 414static int dm9000_ioctl(struct net_device *dev, struct ifreq *req, int cmd)
415{
416 board_info_t *dm = to_dm9000_board(dev);
417
418 if (!netif_running(dev))
419 return -EINVAL;
420
421 return generic_mii_ioctl(&dm->mii, if_mii(req), cmd, NULL);
422}
423
424static unsigned int
425dm9000_read_locked(board_info_t *db, int reg)
a1365275 426{
a1365275 427 unsigned long flags;
f8d79e79 428 unsigned int ret;
a1365275 429
f8d79e79
BD		 430 spin_lock_irqsave(&db->lock, flags);
431 ret = ior(db, reg);
432 spin_unlock_irqrestore(&db->lock, flags);
a1365275 433
f8d79e79
BD		 434 return ret;
435}
a1365275 436
f8d79e79
BD		 437static int dm9000_wait_eeprom(board_info_t *db)
438{
439 unsigned int status;
440 int timeout = 8; /* wait max 8msec */
441
442 /* The DM9000 data sheets say we should be able to
443 * poll the ERRE bit in EPCR to wait for the EEPROM
444 * operation. From testing several chips, this bit
445 * does not seem to work.
446 *
447 * We attempt to use the bit, but fall back to the
448 * timeout (which is why we do not return an error
449 * on expiry) to say that the EEPROM operation has
450 * completed.
451 */
452
453 while (1) {
454 status = dm9000_read_locked(db, DM9000_EPCR);
455
456 if ((status & EPCR_ERRE) == 0)
457 break;
458
2fcf06ca
BD		 459 msleep(1);
460
f8d79e79
BD		 461 if (timeout-- < 0) {
462 dev_dbg(db->dev, "timeout waiting EEPROM\n");
463 break;
464 }
465 }
466
467 return 0;
a1365275
SH		 468}
469
2fd0e33f 470/*
f8d79e79 471 * Read a word data from EEPROM
2fd0e33f 472 */
f8d79e79
BD		 473static void
474dm9000_read_eeprom(board_info_t *db, int offset, u8 *to)
2fd0e33f 475{
f8d79e79
BD		 476 unsigned long flags;
477
478 if (db->flags & DM9000_PLATF_NO_EEPROM) {
479 to[0] = 0xff;
480 to[1] = 0xff;
481 return;
482 }
483
484 mutex_lock(&db->addr_lock);
485
486 spin_lock_irqsave(&db->lock, flags);
487
488 iow(db, DM9000_EPAR, offset);
489 iow(db, DM9000_EPCR, EPCR_ERPRR);
490
491 spin_unlock_irqrestore(&db->lock, flags);
492
493 dm9000_wait_eeprom(db);
494
495 /* delay for at-least 150uS */
496 msleep(1);
497
498 spin_lock_irqsave(&db->lock, flags);
499
500 iow(db, DM9000_EPCR, 0x0);
501
502 to[0] = ior(db, DM9000_EPDRL);
503 to[1] = ior(db, DM9000_EPDRH);
504
505 spin_unlock_irqrestore(&db->lock, flags);
506
507 mutex_unlock(&db->addr_lock);
2fd0e33f 508}
a1365275 509
f8d79e79
BD		 510/*
511 * Write a word data to SROM
512 */
513static void
514dm9000_write_eeprom(board_info_t *db, int offset, u8 *data)
f42d8aea 515{
f8d79e79 516 unsigned long flags;
f42d8aea 517
f8d79e79
BD		 518 if (db->flags & DM9000_PLATF_NO_EEPROM)
519 return;
f42d8aea 520
f8d79e79
BD		 521 mutex_lock(&db->addr_lock);
522
523 spin_lock_irqsave(&db->lock, flags);
524 iow(db, DM9000_EPAR, offset);
525 iow(db, DM9000_EPDRH, data[1]);
526 iow(db, DM9000_EPDRL, data[0]);
527 iow(db, DM9000_EPCR, EPCR_WEP | EPCR_ERPRW);
528 spin_unlock_irqrestore(&db->lock, flags);
529
530 dm9000_wait_eeprom(db);
531
532 mdelay(1); /* wait at least 150uS to clear */
533
534 spin_lock_irqsave(&db->lock, flags);
535 iow(db, DM9000_EPCR, 0);
536 spin_unlock_irqrestore(&db->lock, flags);
537
538 mutex_unlock(&db->addr_lock);
f42d8aea
BD		 539}
540
7da99859
BD		 541/* ethtool ops */
542
543static void dm9000_get_drvinfo(struct net_device *dev,
544 struct ethtool_drvinfo *info)
545{
546 board_info_t *dm = to_dm9000_board(dev);
547
7826d43f
JP		 548 strlcpy(info->driver, CARDNAME, sizeof(info->driver));
549 strlcpy(info->version, DRV_VERSION, sizeof(info->version));
550 strlcpy(info->bus_info, to_platform_device(dm->dev)->name,
551 sizeof(info->bus_info));
7da99859
BD		 552}
553
e662ee02
BD		 554static u32 dm9000_get_msglevel(struct net_device *dev)
555{
556 board_info_t *dm = to_dm9000_board(dev);
557
558 return dm->msg_enable;
559}
560
561static void dm9000_set_msglevel(struct net_device *dev, u32 value)
562{
563 board_info_t *dm = to_dm9000_board(dev);
564
565 dm->msg_enable = value;
566}
567
7da99859
BD		 568static int dm9000_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
569{
570 board_info_t *dm = to_dm9000_board(dev);
7da99859 571
7da99859 572 mii_ethtool_gset(&dm->mii, cmd);
7da99859
BD		 573 return 0;
574}
575
576static int dm9000_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
577{
578 board_info_t *dm = to_dm9000_board(dev);
7da99859 579
9a2f037c 580 return mii_ethtool_sset(&dm->mii, cmd);
7da99859
BD		 581}
582
583static int dm9000_nway_reset(struct net_device *dev)
584{
585 board_info_t *dm = to_dm9000_board(dev);
586 return mii_nway_restart(&dm->mii);
587}
588
c8f44aff
MM		 589static int dm9000_set_features(struct net_device *dev,
590 netdev_features_t features)
5dcc60b7
YP		 591{
592 board_info_t *dm = to_dm9000_board(dev);
c8f44aff 593 netdev_features_t changed = dev->features ^ features;
c88fcb3d 594 unsigned long flags;
5dcc60b7 595
c88fcb3d 596 if (!(changed & NETIF_F_RXCSUM))
5dcc60b7 597 return 0;
380fefb2
BS		 598
599 spin_lock_irqsave(&dm->lock, flags);
c88fcb3d 600 iow(dm, DM9000_RCSR, (features & NETIF_F_RXCSUM) ? RCSR_CSUM : 0);
380fefb2
BS		 601 spin_unlock_irqrestore(&dm->lock, flags);
602
c88fcb3d 603 return 0;
5dcc60b7
YP		 604}
605
7da99859
BD		 606static u32 dm9000_get_link(struct net_device *dev)
607{
608 board_info_t *dm = to_dm9000_board(dev);
aa1eb452
BD		 609 u32 ret;
610
611 if (dm->flags & DM9000_PLATF_EXT_PHY)
612 ret = mii_link_ok(&dm->mii);
613 else
614 ret = dm9000_read_locked(dm, DM9000_NSR) & NSR_LINKST ? 1 : 0;
615
616 return ret;
7da99859
BD		 617}
618
29d52e54
BD		 619#define DM_EEPROM_MAGIC (0x444D394B)
620
621static int dm9000_get_eeprom_len(struct net_device *dev)
622{
623 return 128;
624}
625
626static int dm9000_get_eeprom(struct net_device *dev,
627 struct ethtool_eeprom *ee, u8 *data)
628{
629 board_info_t *dm = to_dm9000_board(dev);
630 int offset = ee->offset;
631 int len = ee->len;
632 int i;
633
634 /* EEPROM access is aligned to two bytes */
635
636 if ((len & 1) != 0 || (offset & 1) != 0)
637 return -EINVAL;
638
bb44fb70
BD		 639 if (dm->flags & DM9000_PLATF_NO_EEPROM)
640 return -ENOENT;
641
29d52e54
BD		 642 ee->magic = DM_EEPROM_MAGIC;
643
644 for (i = 0; i < len; i += 2)
645 dm9000_read_eeprom(dm, (offset + i) / 2, data + i);
646
647 return 0;
648}
649
650static int dm9000_set_eeprom(struct net_device *dev,
651 struct ethtool_eeprom *ee, u8 *data)
652{
653 board_info_t *dm = to_dm9000_board(dev);
654 int offset = ee->offset;
655 int len = ee->len;
40d15cd0 656 int done;
29d52e54
BD		 657
658 /* EEPROM access is aligned to two bytes */
659
bb44fb70
BD		 660 if (dm->flags & DM9000_PLATF_NO_EEPROM)
661 return -ENOENT;
662
29d52e54
BD		 663 if (ee->magic != DM_EEPROM_MAGIC)
664 return -EINVAL;
665
40d15cd0
BD		 666 while (len > 0) {
667 if (len & 1 || offset & 1) {
668 int which = offset & 1;
669 u8 tmp[2];
670
671 dm9000_read_eeprom(dm, offset / 2, tmp);
672 tmp[which] = *data;
673 dm9000_write_eeprom(dm, offset / 2, tmp);
674
675 done = 1;
676 } else {
677 dm9000_write_eeprom(dm, offset / 2, data);
678 done = 2;
679 }
680
681 data += done;
682 offset += done;
683 len -= done;
684 }
29d52e54
BD		 685
686 return 0;
687}
688
c029f444
BD		 689static void dm9000_get_wol(struct net_device *dev, struct ethtool_wolinfo *w)
690{
691 board_info_t *dm = to_dm9000_board(dev);
692
693 memset(w, 0, sizeof(struct ethtool_wolinfo));
694
695 /* note, we could probably support wake-phy too */
696 w->supported = dm->wake_supported ? WAKE_MAGIC : 0;
697 w->wolopts = dm->wake_state;
698}
699
700static int dm9000_set_wol(struct net_device *dev, struct ethtool_wolinfo *w)
701{
702 board_info_t *dm = to_dm9000_board(dev);
703 unsigned long flags;
704 u32 opts = w->wolopts;
705 u32 wcr = 0;
706
707 if (!dm->wake_supported)
708 return -EOPNOTSUPP;
709
710 if (opts & ~WAKE_MAGIC)
711 return -EINVAL;
712
713 if (opts & WAKE_MAGIC)
714 wcr |= WCR_MAGICEN;
715
716 mutex_lock(&dm->addr_lock);
717
718 spin_lock_irqsave(&dm->lock, flags);
719 iow(dm, DM9000_WCR, wcr);
720 spin_unlock_irqrestore(&dm->lock, flags);
721
722 mutex_unlock(&dm->addr_lock);
723
724 if (dm->wake_state != opts) {
725 /* change in wol state, update IRQ state */
726
727 if (!dm->wake_state)
dced35ae 728 irq_set_irq_wake(dm->irq_wake, 1);
83b98fb4 729 else if (dm->wake_state && !opts)
dced35ae 730 irq_set_irq_wake(dm->irq_wake, 0);
c029f444
BD		 731 }
732
733 dm->wake_state = opts;
734 return 0;
735}
736
7da99859
BD		 737static const struct ethtool_ops dm9000_ethtool_ops = {
738 .get_drvinfo = dm9000_get_drvinfo,
739 .get_settings = dm9000_get_settings,
740 .set_settings = dm9000_set_settings,
e662ee02
BD		 741 .get_msglevel = dm9000_get_msglevel,
742 .set_msglevel = dm9000_set_msglevel,
7da99859
BD		 743 .nway_reset = dm9000_nway_reset,
744 .get_link = dm9000_get_link,
c029f444
BD		 745 .get_wol = dm9000_get_wol,
746 .set_wol = dm9000_set_wol,
5b22721d
BS		 747 .get_eeprom_len = dm9000_get_eeprom_len,
748 .get_eeprom = dm9000_get_eeprom,
749 .set_eeprom = dm9000_set_eeprom,
7da99859
BD		 750};
751
f8dd0ecb
BD		 752static void dm9000_show_carrier(board_info_t *db,
753 unsigned carrier, unsigned nsr)
754{
727a282f 755 int lpa;
f8dd0ecb 756 struct net_device *ndev = db->ndev;
727a282f 757 struct mii_if_info *mii = &db->mii;
f8dd0ecb
BD		 758 unsigned ncr = dm9000_read_locked(db, DM9000_NCR);
759
727a282f
NK		 760 if (carrier) {
761 lpa = mii->mdio_read(mii->dev, mii->phy_id, MII_LPA);
762 dev_info(db->dev,
763 "%s: link up, %dMbps, %s-duplex, lpa 0x%04X\n",
f8dd0ecb 764 ndev->name, (nsr & NSR_SPEED) ? 10 : 100,
727a282f
NK		 765 (ncr & NCR_FDX) ? "full" : "half", lpa);
766 } else {
f8dd0ecb 767 dev_info(db->dev, "%s: link down\n", ndev->name);
727a282f 768 }
f8dd0ecb
BD		 769}
770
8f5bf5f2
BD		 771static void
772dm9000_poll_work(struct work_struct *w)
773{
bf6aede7 774 struct delayed_work *dw = to_delayed_work(w);
8f5bf5f2 775 board_info_t *db = container_of(dw, board_info_t, phy_poll);
f8dd0ecb
BD		 776 struct net_device *ndev = db->ndev;
777
778 if (db->flags & DM9000_PLATF_SIMPLE_PHY &&
779 !(db->flags & DM9000_PLATF_EXT_PHY)) {
780 unsigned nsr = dm9000_read_locked(db, DM9000_NSR);
781 unsigned old_carrier = netif_carrier_ok(ndev) ? 1 : 0;
782 unsigned new_carrier;
8f5bf5f2 783
f8dd0ecb
BD		 784 new_carrier = (nsr & NSR_LINKST) ? 1 : 0;
785
786 if (old_carrier != new_carrier) {
787 if (netif_msg_link(db))
788 dm9000_show_carrier(db, new_carrier, nsr);
789
790 if (!new_carrier)
791 netif_carrier_off(ndev);
792 else
793 netif_carrier_on(ndev);
794 }
795 } else
796 mii_check_media(&db->mii, netif_msg_link(db), 0);
5b22721d 797
f8dd0ecb 798 if (netif_running(ndev))
8f5bf5f2
BD		 799 dm9000_schedule_poll(db);
800}
7da99859 801
a1365275
SH		 802/* dm9000_release_board
803 *
804 * release a board, and any mapped resources
805 */
806
807static void
808dm9000_release_board(struct platform_device *pdev, struct board_info *db)
809{
a1365275
SH		 810 /* unmap our resources */
811
812 iounmap(db->io_addr);
813 iounmap(db->io_data);
814
815 /* release the resources */
816
9088fa4f
BD		 817 release_resource(db->data_req);
818 kfree(db->data_req);
a1365275 819
9088fa4f
BD		 820 release_resource(db->addr_req);
821 kfree(db->addr_req);
a1365275
SH		 822}
823
6d406b3c
BD		 824static unsigned char dm9000_type_to_char(enum dm9000_type type)
825{
826 switch (type) {
827 case TYPE_DM9000E: return 'e';
828 case TYPE_DM9000A: return 'a';
829 case TYPE_DM9000B: return 'b';
830 }
831
832 return '?';
833}
834
a1365275 835/*
f8d79e79 836 * Set DM9000 multicast address
a1365275 837 */
f8d79e79 838static void
380fefb2 839dm9000_hash_table_unlocked(struct net_device *dev)
a1365275 840{
4cf1653a 841 board_info_t *db = netdev_priv(dev);
22bedad3 842 struct netdev_hw_addr *ha;
f8d79e79
BD		 843 int i, oft;
844 u32 hash_val;
35e729ac 845 u16 hash_table[4] = { 0, 0, 0, 0x8000 }; /* broadcast address */
f8d79e79 846 u8 rcr = RCR_DIS_LONG | RCR_DIS_CRC | RCR_RXEN;
a1365275 847
f8d79e79 848 dm9000_dbg(db, 1, "entering %s\n", __func__);
a1365275 849
f8d79e79
BD		 850 for (i = 0, oft = DM9000_PAR; i < 6; i++, oft++)
851 iow(db, oft, dev->dev_addr[i]);
a1365275 852
f8d79e79
BD		 853 if (dev->flags & IFF_PROMISC)
854 rcr |= RCR_PRMSC;
8f5bf5f2 855
f8d79e79
BD		 856 if (dev->flags & IFF_ALLMULTI)
857 rcr |= RCR_ALL;
08c3f57c 858
f8d79e79 859 /* the multicast address in Hash Table : 64 bits */
22bedad3
JP		 860 netdev_for_each_mc_addr(ha, dev) {
861 hash_val = ether_crc_le(6, ha->addr) & 0x3f;
f8d79e79 862 hash_table[hash_val / 16] |= (u16) 1 << (hash_val % 16);
08c3f57c
LP		 863 }
864
f8d79e79
BD		 865 /* Write the hash table to MAC MD table */
866 for (i = 0, oft = DM9000_MAR; i < 4; i++) {
867 iow(db, oft++, hash_table[i]);
868 iow(db, oft++, hash_table[i] >> 8);
08c3f57c
LP		 869 }
870
f8d79e79 871 iow(db, DM9000_RCR, rcr);
380fefb2
BS		 872}
873
874static void
875dm9000_hash_table(struct net_device *dev)
876{
877 board_info_t *db = netdev_priv(dev);
878 unsigned long flags;
879
880 spin_lock_irqsave(&db->lock, flags);
881 dm9000_hash_table_unlocked(dev);
f8d79e79
BD		 882 spin_unlock_irqrestore(&db->lock, flags);
883}
08c3f57c 884
17ad78de
AR		 885static void
886dm9000_mask_interrupts(board_info_t *db)
887{
888 iow(db, DM9000_IMR, IMR_PAR);
889}
890
891static void
892dm9000_unmask_interrupts(board_info_t *db)
893{
894 iow(db, DM9000_IMR, db->imr_all);
895}
896
f8d79e79 897/*
1ae5dc34 898 * Initialize dm9000 board
f8d79e79
BD		 899 */
900static void
901dm9000_init_dm9000(struct net_device *dev)
902{
4cf1653a 903 board_info_t *db = netdev_priv(dev);
f8d79e79 904 unsigned int imr;
c029f444 905 unsigned int ncr;
08c3f57c 906
f8d79e79 907 dm9000_dbg(db, 1, "entering %s\n", __func__);
08c3f57c 908
751bb6fd 909 dm9000_reset(db);
17ad78de 910 dm9000_mask_interrupts(db);
751bb6fd 911
f8d79e79
BD		 912 /* I/O mode */
913 db->io_mode = ior(db, DM9000_ISR) >> 6; /* ISR bit7:6 keeps I/O mode */
08c3f57c 914
5dcc60b7 915 /* Checksum mode */
c88fcb3d 916 if (dev->hw_features & NETIF_F_RXCSUM)
56d37f17 917 iow(db, DM9000_RCSR,
c88fcb3d 918 (dev->features & NETIF_F_RXCSUM) ? RCSR_CSUM : 0);
5dcc60b7 919
f8d79e79 920 iow(db, DM9000_GPCR, GPCR_GEP_CNTL); /* Let GPIO0 output */
677d7d28 921 iow(db, DM9000_GPR, 0);
08c3f57c 922
6649b205
NK		 923 /* If we are dealing with DM9000B, some extra steps are required: a
924 * manual phy reset, and setting init params.
925 */
926 if (db->type == TYPE_DM9000B) {
927 dm9000_phy_write(dev, 0, MII_BMCR, BMCR_RESET);
928 dm9000_phy_write(dev, 0, MII_DM_DSPCR, DSPCR_INIT_PARAM);
929 }
6741f40d 930
c029f444
BD		 931 ncr = (db->flags & DM9000_PLATF_EXT_PHY) ? NCR_EXT_PHY : 0;
932
933 /* if wol is needed, then always set NCR_WAKEEN otherwise we end
934 * up dumping the wake events if we disable this. There is already
935 * a wake-mask in DM9000_WCR */
936 if (db->wake_supported)
937 ncr |= NCR_WAKEEN;
938
939 iow(db, DM9000_NCR, ncr);
33ba5091 940
a1365275
SH		 941 /* Program operating register */
942 iow(db, DM9000_TCR, 0); /* TX Polling clear */
943 iow(db, DM9000_BPTR, 0x3f); /* Less 3Kb, 200us */
944 iow(db, DM9000_FCR, 0xff); /* Flow Control */
945 iow(db, DM9000_SMCR, 0); /* Special Mode */
946 /* clear TX status */
947 iow(db, DM9000_NSR, NSR_WAKEST | NSR_TX2END | NSR_TX1END);
948 iow(db, DM9000_ISR, ISR_CLR_STATUS); /* Clear interrupt status */
949
950 /* Set address filter table */
380fefb2 951 dm9000_hash_table_unlocked(dev);
a1365275 952
6d406b3c
BD		 953 imr = IMR_PAR | IMR_PTM | IMR_PRM;
954 if (db->type != TYPE_DM9000E)
955 imr |= IMR_LNKCHNG;
956
957 db->imr_all = imr;
958
a1365275
SH		 959 /* Init Driver variable */
960 db->tx_pkt_cnt = 0;
961 db->queue_pkt_len = 0;
1ae5dc34 962 dev->trans_start = jiffies;
a1365275
SH		 963}
964
f8d79e79
BD		 965/* Our watchdog timed out. Called by the networking layer */
966static void dm9000_timeout(struct net_device *dev)
967{
4cf1653a 968 board_info_t *db = netdev_priv(dev);
f8d79e79
BD		 969 u8 reg_save;
970 unsigned long flags;
971
972 /* Save previous register address */
f8d79e79 973 spin_lock_irqsave(&db->lock, flags);
8dde9242 974 reg_save = readb(db->io_addr);
f8d79e79
BD		 975
976 netif_stop_queue(dev);
f8d79e79 977 dm9000_init_dm9000(dev);
17ad78de 978 dm9000_unmask_interrupts(db);
f8d79e79 979 /* We can accept TX packets again */
1ae5dc34 980 dev->trans_start = jiffies; /* prevent tx timeout */
f8d79e79
BD		 981 netif_wake_queue(dev);
982
983 /* Restore previous register address */
984 writeb(reg_save, db->io_addr);
985 spin_unlock_irqrestore(&db->lock, flags);
986}
987
5dcc60b7
YP		 988static void dm9000_send_packet(struct net_device *dev,
989 int ip_summed,
990 u16 pkt_len)
991{
992 board_info_t *dm = to_dm9000_board(dev);
993
994 /* The DM9000 is not smart enough to leave fragmented packets alone. */
995 if (dm->ip_summed != ip_summed) {
996 if (ip_summed == CHECKSUM_NONE)
997 iow(dm, DM9000_TCCR, 0);
998 else
999 iow(dm, DM9000_TCCR, TCCR_IP | TCCR_UDP | TCCR_TCP);
1000 dm->ip_summed = ip_summed;
1001 }
1002
1003 /* Set TX length to DM9000 */
1004 iow(dm, DM9000_TXPLL, pkt_len);
1005 iow(dm, DM9000_TXPLH, pkt_len >> 8);
1006
1007 /* Issue TX polling command */
1008 iow(dm, DM9000_TCR, TCR_TXREQ); /* Cleared after TX complete */
1009}
1010
a1365275
SH		 1011/*
1012 * Hardware start transmission.
1013 * Send a packet to media from the upper layer.
1014 */
1015static int
1016dm9000_start_xmit(struct sk_buff *skb, struct net_device *dev)
1017{
c46ac946 1018 unsigned long flags;
4cf1653a 1019 board_info_t *db = netdev_priv(dev);
a1365275 1020
5b2b4ff0 1021 dm9000_dbg(db, 3, "%s:\n", __func__);
a1365275
SH		 1022
1023 if (db->tx_pkt_cnt > 1)
5b548140 1024 return NETDEV_TX_BUSY;
a1365275 1025
c46ac946 1026 spin_lock_irqsave(&db->lock, flags);
a1365275
SH		 1027
1028 /* Move data to DM9000 TX RAM */
1029 writeb(DM9000_MWCMD, db->io_addr);
1030
1031 (db->outblk)(db->io_data, skb->data, skb->len);
09f75cd7 1032 dev->stats.tx_bytes += skb->len;
a1365275 1033
c46ac946 1034 db->tx_pkt_cnt++;
a1365275 1035 /* TX control: First packet immediately send, second packet queue */
c46ac946 1036 if (db->tx_pkt_cnt == 1) {
5dcc60b7 1037 dm9000_send_packet(dev, skb->ip_summed, skb->len);
a1365275
SH		 1038 } else {
1039 /* Second packet */
a1365275 1040 db->queue_pkt_len = skb->len;
5dcc60b7 1041 db->queue_ip_summed = skb->ip_summed;
c46ac946 1042 netif_stop_queue(dev);
a1365275
SH		 1043 }
1044
c46ac946
FW		 1045 spin_unlock_irqrestore(&db->lock, flags);
1046
a1365275 1047 /* free this SKB */
2c3d0bc0 1048 dev_consume_skb_any(skb);
a1365275 1049
6ed10654 1050 return NETDEV_TX_OK;
a1365275
SH		 1051}
1052
a1365275 1053/*
f8d79e79
BD		 1054 * DM9000 interrupt handler
1055 * receive the packet to upper layer, free the transmitted packet
a1365275 1056 */
f8d79e79
BD		 1057
1058static void dm9000_tx_done(struct net_device *dev, board_info_t *db)
a1365275 1059{
f8d79e79 1060 int tx_status = ior(db, DM9000_NSR); /* Got TX status */
a1365275 1061
f8d79e79
BD		 1062 if (tx_status & (NSR_TX2END | NSR_TX1END)) {
1063 /* One packet sent complete */
1064 db->tx_pkt_cnt--;
1065 dev->stats.tx_packets++;
a1365275 1066
f8d79e79
BD		 1067 if (netif_msg_tx_done(db))
1068 dev_dbg(db->dev, "tx done, NSR %02x\n", tx_status);
c991d168 1069
a1365275 1070 /* Queue packet check & send */
5dcc60b7
YP		 1071 if (db->tx_pkt_cnt > 0)
1072 dm9000_send_packet(dev, db->queue_ip_summed,
1073 db->queue_pkt_len);
a1365275
SH		 1074 netif_wake_queue(dev);
1075 }
1076}
1077
a1365275 1078struct dm9000_rxhdr {
93116573
BD		 1079 u8 RxPktReady;
1080 u8 RxStatus;
8b9fc8ae 1081 __le16 RxLen;
ba2d3587 1082} __packed;
a1365275
SH		 1083
1084/*
1085 * Received a packet and pass to upper layer
1086 */
1087static void
1088dm9000_rx(struct net_device *dev)
1089{
4cf1653a 1090 board_info_t *db = netdev_priv(dev);
a1365275
SH		 1091 struct dm9000_rxhdr rxhdr;
1092 struct sk_buff *skb;
1093 u8 rxbyte, *rdptr;
6478fac6 1094 bool GoodPacket;
a1365275
SH		 1095 int RxLen;
1096
1097 /* Check packet ready or not */
1098 do {
1099 ior(db, DM9000_MRCMDX); /* Dummy read */
1100
1101 /* Get most updated data */
1102 rxbyte = readb(db->io_data);
1103
1104 /* Status check: this byte must be 0 or 1 */
5dcc60b7 1105 if (rxbyte & DM9000_PKT_ERR) {
a76836f9 1106 dev_warn(db->dev, "status check fail: %d\n", rxbyte);
a1365275 1107 iow(db, DM9000_RCR, 0x00); /* Stop Device */
a1365275
SH		 1108 return;
1109 }
1110
5dcc60b7 1111 if (!(rxbyte & DM9000_PKT_RDY))
a1365275
SH		 1112 return;
1113
1114 /* A packet ready now & Get status/length */
6478fac6 1115 GoodPacket = true;
a1365275
SH		 1116 writeb(DM9000_MRCMD, db->io_addr);
1117
1118 (db->inblk)(db->io_data, &rxhdr, sizeof(rxhdr));
1119
93116573 1120 RxLen = le16_to_cpu(rxhdr.RxLen);
a1365275 1121
c991d168
BD		 1122 if (netif_msg_rx_status(db))
1123 dev_dbg(db->dev, "RX: status %02x, length %04x\n",
1124 rxhdr.RxStatus, RxLen);
1125
a1365275
SH		 1126 /* Packet Status check */
1127 if (RxLen < 0x40) {
6478fac6 1128 GoodPacket = false;
c991d168
BD		 1129 if (netif_msg_rx_err(db))
1130 dev_dbg(db->dev, "RX: Bad Packet (runt)\n");
a1365275
SH		 1131 }
1132
1133 if (RxLen > DM9000_PKT_MAX) {
a76836f9 1134 dev_dbg(db->dev, "RST: RX Len:%x\n", RxLen);
a1365275
SH		 1135 }
1136
f8e5e776
BD		 1137 /* rxhdr.RxStatus is identical to RSR register. */
1138 if (rxhdr.RxStatus & (RSR_FOE | RSR_CE | RSR_AE |
1139 RSR_PLE | RSR_RWTO |
1140 RSR_LCS | RSR_RF)) {
6478fac6 1141 GoodPacket = false;
f8e5e776 1142 if (rxhdr.RxStatus & RSR_FOE) {
c991d168
BD		 1143 if (netif_msg_rx_err(db))
1144 dev_dbg(db->dev, "fifo error\n");
09f75cd7 1145 dev->stats.rx_fifo_errors++;
a1365275 1146 }
f8e5e776 1147 if (rxhdr.RxStatus & RSR_CE) {
c991d168
BD		 1148 if (netif_msg_rx_err(db))
1149 dev_dbg(db->dev, "crc error\n");
09f75cd7 1150 dev->stats.rx_crc_errors++;
a1365275 1151 }
f8e5e776 1152 if (rxhdr.RxStatus & RSR_RF) {
c991d168
BD		 1153 if (netif_msg_rx_err(db))
1154 dev_dbg(db->dev, "length error\n");
09f75cd7 1155 dev->stats.rx_length_errors++;
a1365275
SH		 1156 }
1157 }
1158
1159 /* Move data from DM9000 */
8e95a202 1160 if (GoodPacket &&
21a4e469 1161 ((skb = netdev_alloc_skb(dev, RxLen + 4)) != NULL)) {
a1365275
SH		 1162 skb_reserve(skb, 2);
1163 rdptr = (u8 *) skb_put(skb, RxLen - 4);
1164
1165 /* Read received packet from RX SRAM */
1166
1167 (db->inblk)(db->io_data, rdptr, RxLen);
09f75cd7 1168 dev->stats.rx_bytes += RxLen;
a1365275
SH		 1169
1170 /* Pass to upper layer */
1171 skb->protocol = eth_type_trans(skb, dev);
c88fcb3d 1172 if (dev->features & NETIF_F_RXCSUM) {
5dcc60b7
YP		 1173 if ((((rxbyte & 0x1c) << 3) & rxbyte) == 0)
1174 skb->ip_summed = CHECKSUM_UNNECESSARY;
1175 else
bc8acf2c 1176 skb_checksum_none_assert(skb);
5dcc60b7 1177 }
a1365275 1178 netif_rx(skb);
09f75cd7 1179 dev->stats.rx_packets++;
a1365275
SH		 1180
1181 } else {
1182 /* need to dump the packet's data */
1183
1184 (db->dumpblk)(db->io_data, RxLen);
1185 }
5dcc60b7 1186 } while (rxbyte & DM9000_PKT_RDY);
a1365275
SH		 1187}
1188
f8d79e79 1189static irqreturn_t dm9000_interrupt(int irq, void *dev_id)
39c341a8 1190{
f8d79e79 1191 struct net_device *dev = dev_id;
4cf1653a 1192 board_info_t *db = netdev_priv(dev);
f8d79e79 1193 int int_status;
e3162d38 1194 unsigned long flags;
f8d79e79 1195 u8 reg_save;
39c341a8 1196
f8d79e79 1197 dm9000_dbg(db, 3, "entering %s\n", __func__);
39c341a8 1198
f8d79e79 1199 /* A real interrupt coming */
39c341a8 1200
e3162d38
DB		 1201 /* holders of db->lock must always block IRQs */
1202 spin_lock_irqsave(&db->lock, flags);
39c341a8 1203
f8d79e79
BD		 1204 /* Save previous register address */
1205 reg_save = readb(db->io_addr);
39c341a8 1206
17ad78de 1207 dm9000_mask_interrupts(db);
f8d79e79
BD		 1208 /* Got DM9000 interrupt status */
1209 int_status = ior(db, DM9000_ISR); /* Got ISR */
1210 iow(db, DM9000_ISR, int_status); /* Clear ISR status */
39c341a8 1211
f8d79e79
BD		 1212 if (netif_msg_intr(db))
1213 dev_dbg(db->dev, "interrupt status %02x\n", int_status);
1214
1215 /* Received the coming packet */
1216 if (int_status & ISR_PRS)
1217 dm9000_rx(dev);
1218
1219 /* Trnasmit Interrupt check */
1220 if (int_status & ISR_PTS)
1221 dm9000_tx_done(dev, db);
1222
1223 if (db->type != TYPE_DM9000E) {
1224 if (int_status & ISR_LNKCHNG) {
1225 /* fire a link-change request */
1226 schedule_delayed_work(&db->phy_poll, 1);
39c341a8
BD		 1227 }
1228 }
1229
17ad78de 1230 dm9000_unmask_interrupts(db);
f8d79e79
BD		 1231 /* Restore previous register address */
1232 writeb(reg_save, db->io_addr);
1233
e3162d38 1234 spin_unlock_irqrestore(&db->lock, flags);
f8d79e79
BD		 1235
1236 return IRQ_HANDLED;
39c341a8
BD		 1237}
1238
c029f444
BD		 1239static irqreturn_t dm9000_wol_interrupt(int irq, void *dev_id)
1240{
1241 struct net_device *dev = dev_id;
1242 board_info_t *db = netdev_priv(dev);
1243 unsigned long flags;
1244 unsigned nsr, wcr;
1245
1246 spin_lock_irqsave(&db->lock, flags);
1247
1248 nsr = ior(db, DM9000_NSR);
1249 wcr = ior(db, DM9000_WCR);
1250
1251 dev_dbg(db->dev, "%s: NSR=0x%02x, WCR=0x%02x\n", __func__, nsr, wcr);
1252
1253 if (nsr & NSR_WAKEST) {
1254 /* clear, so we can avoid */
1255 iow(db, DM9000_NSR, NSR_WAKEST);
1256
1257 if (wcr & WCR_LINKST)
1258 dev_info(db->dev, "wake by link status change\n");
1259 if (wcr & WCR_SAMPLEST)
1260 dev_info(db->dev, "wake by sample packet\n");
5b22721d 1261 if (wcr & WCR_MAGICST)
c029f444
BD		 1262 dev_info(db->dev, "wake by magic packet\n");
1263 if (!(wcr & (WCR_LINKST | WCR_SAMPLEST | WCR_MAGICST)))
1264 dev_err(db->dev, "wake signalled with no reason? "
1265 "NSR=0x%02x, WSR=0x%02x\n", nsr, wcr);
c029f444
BD		 1266 }
1267
1268 spin_unlock_irqrestore(&db->lock, flags);
1269
1270 return (nsr & NSR_WAKEST) ? IRQ_HANDLED : IRQ_NONE;
1271}
1272
f8d79e79 1273#ifdef CONFIG_NET_POLL_CONTROLLER
a1365275 1274/*
f8d79e79 1275 *Used by netconsole
a1365275 1276 */
f8d79e79 1277static void dm9000_poll_controller(struct net_device *dev)
a1365275 1278{
f8d79e79
BD		 1279 disable_irq(dev->irq);
1280 dm9000_interrupt(dev->irq, dev);
1281 enable_irq(dev->irq);
1282}
1283#endif
9a2f037c 1284
f8d79e79
BD		 1285/*
1286 * Open the interface.
1287 * The interface is opened whenever "ifconfig" actives it.
1288 */
1289static int
1290dm9000_open(struct net_device *dev)
1291{
4cf1653a 1292 board_info_t *db = netdev_priv(dev);
f8d79e79 1293 unsigned long irqflags = db->irq_res->flags & IRQF_TRIGGER_MASK;
621ddcb0 1294
f8d79e79
BD		 1295 if (netif_msg_ifup(db))
1296 dev_dbg(db->dev, "enabling %s\n", dev->name);
621ddcb0 1297
f8d79e79
BD		 1298 /* If there is no IRQ type specified, default to something that
1299 * may work, and tell the user that this is a problem */
621ddcb0 1300
6b50d038
AR		 1301 if (irqflags == IRQF_TRIGGER_NONE)
1302 irqflags = irq_get_trigger_type(dev->irq);
1303
6ff4ff06 1304 if (irqflags == IRQF_TRIGGER_NONE)
f8d79e79 1305 dev_warn(db->dev, "WARNING: no IRQ resource flags set.\n");
6ff4ff06 1306
f8d79e79 1307 irqflags |= IRQF_SHARED;
39c341a8 1308
108f518c
HN		 1309 /* GPIO0 on pre-activate PHY, Reg 1F is not set by reset */
1310 iow(db, DM9000_GPR, 0); /* REG_1F bit0 activate phyxcer */
1311 mdelay(1); /* delay needs by DM9000B */
1312
f8d79e79 1313 /* Initialize DM9000 board */
f8d79e79 1314 dm9000_init_dm9000(dev);
621ddcb0 1315
6979d5dd
MB		 1316 if (request_irq(dev->irq, dm9000_interrupt, irqflags, dev->name, dev))
1317 return -EAGAIN;
17ad78de
AR		 1318 /* Now that we have an interrupt handler hooked up we can unmask
1319 * our interrupts
1320 */
1321 dm9000_unmask_interrupts(db);
6979d5dd 1322
f8d79e79
BD		 1323 /* Init driver variable */
1324 db->dbug_cnt = 0;
86c62fab 1325
f8d79e79
BD		 1326 mii_check_media(&db->mii, netif_msg_link(db), 1);
1327 netif_start_queue(dev);
5b22721d 1328
aac6d022
AR		 1329 /* Poll initial link status */
1330 schedule_delayed_work(&db->phy_poll, 1);
9a2f037c 1331
f8d79e79
BD		 1332 return 0;
1333}
621ddcb0 1334
f8d79e79
BD		 1335static void
1336dm9000_shutdown(struct net_device *dev)
1337{
4cf1653a 1338 board_info_t *db = netdev_priv(dev);
f8d79e79
BD		 1339
1340 /* RESET device */
1341 dm9000_phy_write(dev, 0, MII_BMCR, BMCR_RESET); /* PHY RESET */
1342 iow(db, DM9000_GPR, 0x01); /* Power-Down PHY */
17ad78de 1343 dm9000_mask_interrupts(db);
f8d79e79
BD		 1344 iow(db, DM9000_RCR, 0x00); /* Disable RX */
1345}
1346
1347/*
1348 * Stop the interface.
1349 * The interface is stopped when it is brought.
1350 */
1351static int
1352dm9000_stop(struct net_device *ndev)
1353{
4cf1653a 1354 board_info_t *db = netdev_priv(ndev);
f8d79e79
BD		 1355
1356 if (netif_msg_ifdown(db))
1357 dev_dbg(db->dev, "shutting down %s\n", ndev->name);
1358
1359 cancel_delayed_work_sync(&db->phy_poll);
1360
1361 netif_stop_queue(ndev);
1362 netif_carrier_off(ndev);
1363
1364 /* free interrupt */
1365 free_irq(ndev->irq, ndev);
1366
1367 dm9000_shutdown(ndev);
1368
1369 return 0;
1370}
1371
d88106b7
AB		 1372static const struct net_device_ops dm9000_netdev_ops = {
1373 .ndo_open = dm9000_open,
1374 .ndo_stop = dm9000_stop,
1375 .ndo_start_xmit = dm9000_start_xmit,
1376 .ndo_tx_timeout = dm9000_timeout,
afc4b13d 1377 .ndo_set_rx_mode = dm9000_hash_table,
d88106b7
AB		 1378 .ndo_do_ioctl = dm9000_ioctl,
1379 .ndo_change_mtu = eth_change_mtu,
c88fcb3d 1380 .ndo_set_features = dm9000_set_features,
d88106b7
AB		 1381 .ndo_validate_addr = eth_validate_addr,
1382 .ndo_set_mac_address = eth_mac_addr,
1383#ifdef CONFIG_NET_POLL_CONTROLLER
1384 .ndo_poll_controller = dm9000_poll_controller,
1385#endif
1386};
1387
0b8bf1ba
TF		 1388static struct dm9000_plat_data *dm9000_parse_dt(struct device *dev)
1389{
1390 struct dm9000_plat_data *pdata;
1391 struct device_node *np = dev->of_node;
1392 const void *mac_addr;
1393
1394 if (!IS_ENABLED(CONFIG_OF) || !np)
1395 return NULL;
1396
1397 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
1398 if (!pdata)
1399 return ERR_PTR(-ENOMEM);
1400
1401 if (of_find_property(np, "davicom,ext-phy", NULL))
1402 pdata->flags |= DM9000_PLATF_EXT_PHY;
1403 if (of_find_property(np, "davicom,no-eeprom", NULL))
1404 pdata->flags |= DM9000_PLATF_NO_EEPROM;
1405
1406 mac_addr = of_get_mac_address(np);
1407 if (mac_addr)
1408 memcpy(pdata->dev_addr, mac_addr, sizeof(pdata->dev_addr));
1409
1410 return pdata;
1411}
1412
f8d79e79
BD		 1413/*
1414 * Search DM9000 board, allocate space and register it
1415 */
6b6a3e7f 1416static int
f8d79e79
BD		 1417dm9000_probe(struct platform_device *pdev)
1418{
cd4e2e4b 1419 struct dm9000_plat_data *pdata = dev_get_platdata(&pdev->dev);
f8d79e79
BD		 1420 struct board_info *db; /* Point a board information structure */
1421 struct net_device *ndev;
1422 const unsigned char *mac_src;
1423 int ret = 0;
1424 int iosize;
1425 int i;
1426 u32 id_val;
1427
0b8bf1ba
TF		 1428 if (!pdata) {
1429 pdata = dm9000_parse_dt(&pdev->dev);
1430 if (IS_ERR(pdata))
1431 return PTR_ERR(pdata);
1432 }
1433
f8d79e79
BD		 1434 /* Init network device */
1435 ndev = alloc_etherdev(sizeof(struct board_info));
41de8d4c 1436 if (!ndev)
f8d79e79 1437 return -ENOMEM;
f8d79e79
BD		 1438
1439 SET_NETDEV_DEV(ndev, &pdev->dev);
1440
1441 dev_dbg(&pdev->dev, "dm9000_probe()\n");
1442
1443 /* setup board info structure */
4cf1653a 1444 db = netdev_priv(ndev);
f8d79e79
BD		 1445
1446 db->dev = &pdev->dev;
1447 db->ndev = ndev;
1448
1449 spin_lock_init(&db->lock);
1450 mutex_init(&db->addr_lock);
1451
1452 INIT_DELAYED_WORK(&db->phy_poll, dm9000_poll_work);
1453
1454 db->addr_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1455 db->data_res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1456 db->irq_res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1457
1458 if (db->addr_res == NULL || db->data_res == NULL ||
1459 db->irq_res == NULL) {
1460 dev_err(db->dev, "insufficient resources\n");
1461 ret = -ENOENT;
1462 goto out;
1463 }
1464
c029f444
BD		 1465 db->irq_wake = platform_get_irq(pdev, 1);
1466 if (db->irq_wake >= 0) {
1467 dev_dbg(db->dev, "wakeup irq %d\n", db->irq_wake);
1468
1469 ret = request_irq(db->irq_wake, dm9000_wol_interrupt,
1470 IRQF_SHARED, dev_name(db->dev), ndev);
1471 if (ret) {
1472 dev_err(db->dev, "cannot get wakeup irq (%d)\n", ret);
1473 } else {
1474
1475 /* test to see if irq is really wakeup capable */
dced35ae 1476 ret = irq_set_irq_wake(db->irq_wake, 1);
c029f444
BD		 1477 if (ret) {
1478 dev_err(db->dev, "irq %d cannot set wakeup (%d)\n",
1479 db->irq_wake, ret);
1480 ret = 0;
1481 } else {
dced35ae 1482 irq_set_irq_wake(db->irq_wake, 0);
c029f444
BD		 1483 db->wake_supported = 1;
1484 }
1485 }
1486 }
1487
ec282e92 1488 iosize = resource_size(db->addr_res);
f8d79e79
BD		 1489 db->addr_req = request_mem_region(db->addr_res->start, iosize,
1490 pdev->name);
1491
1492 if (db->addr_req == NULL) {
1493 dev_err(db->dev, "cannot claim address reg area\n");
1494 ret = -EIO;
1495 goto out;
1496 }
1497
1498 db->io_addr = ioremap(db->addr_res->start, iosize);
1499
1500 if (db->io_addr == NULL) {
1501 dev_err(db->dev, "failed to ioremap address reg\n");
1502 ret = -EINVAL;
1503 goto out;
1504 }
1505
ec282e92 1506 iosize = resource_size(db->data_res);
f8d79e79
BD		 1507 db->data_req = request_mem_region(db->data_res->start, iosize,
1508 pdev->name);
1509
1510 if (db->data_req == NULL) {
1511 dev_err(db->dev, "cannot claim data reg area\n");
1512 ret = -EIO;
1513 goto out;
1514 }
1515
1516 db->io_data = ioremap(db->data_res->start, iosize);
1517
1518 if (db->io_data == NULL) {
1519 dev_err(db->dev, "failed to ioremap data reg\n");
1520 ret = -EINVAL;
1521 goto out;
1522 }
1523
1524 /* fill in parameters for net-dev structure */
1525 ndev->base_addr = (unsigned long)db->io_addr;
1526 ndev->irq = db->irq_res->start;
1527
1528 /* ensure at least we have a default set of IO routines */
1529 dm9000_set_io(db, iosize);
1530
1531 /* check to see if anything is being over-ridden */
1532 if (pdata != NULL) {
1533 /* check to see if the driver wants to over-ride the
1534 * default IO width */
1535
1536 if (pdata->flags & DM9000_PLATF_8BITONLY)
1537 dm9000_set_io(db, 1);
1538
1539 if (pdata->flags & DM9000_PLATF_16BITONLY)
1540 dm9000_set_io(db, 2);
1541
1542 if (pdata->flags & DM9000_PLATF_32BITONLY)
1543 dm9000_set_io(db, 4);
1544
1545 /* check to see if there are any IO routine
1546 * over-rides */
1547
1548 if (pdata->inblk != NULL)
1549 db->inblk = pdata->inblk;
1550
1551 if (pdata->outblk != NULL)
1552 db->outblk = pdata->outblk;
1553
1554 if (pdata->dumpblk != NULL)
1555 db->dumpblk = pdata->dumpblk;
1556
1557 db->flags = pdata->flags;
1558 }
1559
f8dd0ecb
BD		 1560#ifdef CONFIG_DM9000_FORCE_SIMPLE_PHY_POLL
1561 db->flags |= DM9000_PLATF_SIMPLE_PHY;
1562#endif
1563
751bb6fd 1564 dm9000_reset(db);
f8d79e79
BD		 1565
1566 /* try multiple times, DM9000 sometimes gets the read wrong */
1567 for (i = 0; i < 8; i++) {
1568 id_val = ior(db, DM9000_VIDL);
1569 id_val |= (u32)ior(db, DM9000_VIDH) << 8;
1570 id_val |= (u32)ior(db, DM9000_PIDL) << 16;
1571 id_val |= (u32)ior(db, DM9000_PIDH) << 24;
1572
1573 if (id_val == DM9000_ID)
1574 break;
1575 dev_err(db->dev, "read wrong id 0x%08x\n", id_val);
1576 }
1577
1578 if (id_val != DM9000_ID) {
1579 dev_err(db->dev, "wrong id: 0x%08x\n", id_val);
1580 ret = -ENODEV;
1581 goto out;
1582 }
1583
1584 /* Identify what type of DM9000 we are working on */
1585
1586 id_val = ior(db, DM9000_CHIPR);
1587 dev_dbg(db->dev, "dm9000 revision 0x%02x\n", id_val);
1588
1589 switch (id_val) {
1590 case CHIPR_DM9000A:
1591 db->type = TYPE_DM9000A;
1592 break;
1593 case CHIPR_DM9000B:
1594 db->type = TYPE_DM9000B;
1595 break;
1596 default:
1597 dev_dbg(db->dev, "ID %02x => defaulting to DM9000E\n", id_val);
1598 db->type = TYPE_DM9000E;
1599 }
1600
5dcc60b7
YP		 1601 /* dm9000a/b are capable of hardware checksum offload */
1602 if (db->type == TYPE_DM9000A || db->type == TYPE_DM9000B) {
c88fcb3d
MM		 1603 ndev->hw_features = NETIF_F_RXCSUM | NETIF_F_IP_CSUM;
1604 ndev->features |= ndev->hw_features;
5dcc60b7
YP		 1605 }
1606
f8d79e79
BD		 1607 /* from this point we assume that we have found a DM9000 */
1608
1609 /* driver system function */
1610 ether_setup(ndev);
1611
d88106b7
AB		 1612 ndev->netdev_ops = &dm9000_netdev_ops;
1613 ndev->watchdog_timeo = msecs_to_jiffies(watchdog);
1614 ndev->ethtool_ops = &dm9000_ethtool_ops;
f8d79e79
BD		 1615
1616 db->msg_enable = NETIF_MSG_LINK;
1617 db->mii.phy_id_mask = 0x1f;
1618 db->mii.reg_num_mask = 0x1f;
1619 db->mii.force_media = 0;
1620 db->mii.full_duplex = 0;
1621 db->mii.dev = ndev;
1622 db->mii.mdio_read = dm9000_phy_read;
1623 db->mii.mdio_write = dm9000_phy_write;
1624
1625 mac_src = "eeprom";
1626
1627 /* try reading the node address from the attached EEPROM */
1628 for (i = 0; i < 6; i += 2)
1629 dm9000_read_eeprom(db, i / 2, ndev->dev_addr+i);
1630
fe414248
LP		 1631 if (!is_valid_ether_addr(ndev->dev_addr) && pdata != NULL) {
1632 mac_src = "platform data";
d458cdf7 1633 memcpy(ndev->dev_addr, pdata->dev_addr, ETH_ALEN);
fe414248
LP		 1634 }
1635
f8d79e79
BD		 1636 if (!is_valid_ether_addr(ndev->dev_addr)) {
1637 /* try reading from mac */
5b22721d 1638
f8d79e79
BD		 1639 mac_src = "chip";
1640 for (i = 0; i < 6; i++)
1641 ndev->dev_addr[i] = ior(db, i+DM9000_PAR);
1642 }
1643
85e6b8c5 1644 if (!is_valid_ether_addr(ndev->dev_addr)) {
f8d79e79
BD		 1645 dev_warn(db->dev, "%s: Invalid ethernet MAC address. Please "
1646 "set using ifconfig\n", ndev->name);
1647
f2cedb63 1648 eth_hw_addr_random(ndev);
85e6b8c5
BD		 1649 mac_src = "random";
1650 }
1651
1652
f8d79e79
BD		 1653 platform_set_drvdata(pdev, ndev);
1654 ret = register_netdev(ndev);
1655
e174961c
JB		 1656 if (ret == 0)
1657 printk(KERN_INFO "%s: dm9000%c at %p,%p IRQ %d MAC: %pM (%s)\n",
f8d79e79
BD		 1658 ndev->name, dm9000_type_to_char(db->type),
1659 db->io_addr, db->io_data, ndev->irq,
e174961c 1660 ndev->dev_addr, mac_src);
f8d79e79
BD		 1661 return 0;
1662
1663out:
1664 dev_err(db->dev, "not found (%d).\n", ret);
1665
1666 dm9000_release_board(pdev, db);
1667 free_netdev(ndev);
1668
1669 return ret;
1670}
1671
a1365275 1672static int
69222e2c 1673dm9000_drv_suspend(struct device *dev)
a1365275 1674{
69222e2c
MR		 1675 struct platform_device *pdev = to_platform_device(dev);
1676 struct net_device *ndev = platform_get_drvdata(pdev);
321f69a4 1677 board_info_t *db;
a1365275 1678
9480e307 1679 if (ndev) {
4cf1653a 1680 db = netdev_priv(ndev);
321f69a4
BD		 1681 db->in_suspend = 1;
1682
c029f444
BD		 1683 if (!netif_running(ndev))
1684 return 0;
1685
1686 netif_device_detach(ndev);
1687
1688 /* only shutdown if not using WoL */
1689 if (!db->wake_state)
a1365275 1690 dm9000_shutdown(ndev);
a1365275
SH		 1691 }
1692 return 0;
1693}
1694
1695static int
69222e2c 1696dm9000_drv_resume(struct device *dev)
a1365275 1697{
69222e2c
MR		 1698 struct platform_device *pdev = to_platform_device(dev);
1699 struct net_device *ndev = platform_get_drvdata(pdev);
4cf1653a 1700 board_info_t *db = netdev_priv(ndev);
a1365275 1701
9480e307 1702 if (ndev) {
a1365275 1703 if (netif_running(ndev)) {
c029f444
BD		 1704 /* reset if we were not in wake mode to ensure if
1705 * the device was powered off it is in a known state */
1706 if (!db->wake_state) {
c029f444 1707 dm9000_init_dm9000(ndev);
17ad78de 1708 dm9000_unmask_interrupts(db);
c029f444 1709 }
a1365275
SH		 1710
1711 netif_device_attach(ndev);
1712 }
321f69a4
BD		 1713
1714 db->in_suspend = 0;
a1365275
SH		 1715 }
1716 return 0;
1717}
1718
47145210 1719static const struct dev_pm_ops dm9000_drv_pm_ops = {
69222e2c
MR		 1720 .suspend = dm9000_drv_suspend,
1721 .resume = dm9000_drv_resume,
1722};
1723
6b6a3e7f 1724static int
3ae5eaec 1725dm9000_drv_remove(struct platform_device *pdev)
a1365275 1726{
3ae5eaec 1727 struct net_device *ndev = platform_get_drvdata(pdev);
a1365275 1728
a1365275 1729 unregister_netdev(ndev);
ece49153 1730 dm9000_release_board(pdev, netdev_priv(ndev));
9fd9f9b6 1731 free_netdev(ndev); /* free device structure */
a1365275 1732
a76836f9 1733 dev_dbg(&pdev->dev, "released and freed device\n");
a1365275
SH		 1734 return 0;
1735}
1736
0b8bf1ba
TF		 1737#ifdef CONFIG_OF
1738static const struct of_device_id dm9000_of_matches[] = {
1739 { .compatible = "davicom,dm9000", },
1740 { /* sentinel */ }
1741};
1742MODULE_DEVICE_TABLE(of, dm9000_of_matches);
1743#endif
1744
3ae5eaec 1745static struct platform_driver dm9000_driver = {
5d22a312
BD		 1746 .driver = {
1747 .name = "dm9000",
1748 .owner = THIS_MODULE,
69222e2c 1749 .pm = &dm9000_drv_pm_ops,
0b8bf1ba 1750 .of_match_table = of_match_ptr(dm9000_of_matches),
5d22a312 1751 },
a1365275 1752 .probe = dm9000_probe,
6b6a3e7f 1753 .remove = dm9000_drv_remove,
a1365275
SH		 1754};
1755
a8f9c3e4 1756module_platform_driver(dm9000_driver);
a1365275
SH		 1757
1758MODULE_AUTHOR("Sascha Hauer, Ben Dooks");
1759MODULE_DESCRIPTION("Davicom DM9000 network driver");
1760MODULE_LICENSE("GPL");
72abb461 1761MODULE_ALIAS("platform:dm9000");
Linux kernel - Deliverables
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