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drivers/net: Convert compare_ether_addr to ether_addr_equal
[deliverable/linux.git] / drivers / net / ethernet / dec / ewrk3.c
CommitLineData
1da177e4
LT		 1/* ewrk3.c: A DIGITAL EtherWORKS 3 ethernet driver for Linux.
2
3 Written 1994 by David C. Davies.
4
5 Copyright 1994 Digital Equipment Corporation.
6
7 This software may be used and distributed according to the terms of
8 the GNU General Public License, incorporated herein by reference.
9
10 This driver is written for the Digital Equipment Corporation series
11 of EtherWORKS ethernet cards:
12
13 DE203 Turbo (BNC)
14 DE204 Turbo (TP)
15 DE205 Turbo (TP BNC)
16
17 The driver has been tested on a relatively busy network using the DE205
18 card and benchmarked with 'ttcp': it transferred 16M of data at 975kB/s
19 (7.8Mb/s) to a DECstation 5000/200.
20
21 The author may be reached at davies@maniac.ultranet.com.
22
23 =========================================================================
24 This driver has been written substantially from scratch, although its
25 inheritance of style and stack interface from 'depca.c' and in turn from
26 Donald Becker's 'lance.c' should be obvious.
27
28 The DE203/4/5 boards all use a new proprietary chip in place of the
29 LANCE chip used in prior cards (DEPCA, DE100, DE200/1/2, DE210, DE422).
30 Use the depca.c driver in the standard distribution for the LANCE based
31 cards from DIGITAL; this driver will not work with them.
32
33 The DE203/4/5 cards have 2 main modes: shared memory and I/O only. I/O
34 only makes all the card accesses through I/O transactions and no high
35 (shared) memory is used. This mode provides a >48% performance penalty
36 and is deprecated in this driver, although allowed to provide initial
37 setup when hardstrapped.
38
39 The shared memory mode comes in 3 flavours: 2kB, 32kB and 64kB. There is
40 no point in using any mode other than the 2kB mode - their performances
41 are virtually identical, although the driver has been tested in the 2kB
42 and 32kB modes. I would suggest you uncomment the line:
43
44 FORCE_2K_MODE;
45
46 to allow the driver to configure the card as a 2kB card at your current
47 base address, thus leaving more room to clutter your system box with
48 other memory hungry boards.
49
50 As many ISA and EISA cards can be supported under this driver as you
51 wish, limited primarily by the available IRQ lines, rather than by the
52 available I/O addresses (24 ISA, 16 EISA). I have checked different
53 configurations of multiple depca cards and ewrk3 cards and have not
54 found a problem yet (provided you have at least depca.c v0.38) ...
55
56 The board IRQ setting must be at an unused IRQ which is auto-probed
57 using Donald Becker's autoprobe routines. All these cards are at
58 {5,10,11,15}.
59
60 No 16MB memory limitation should exist with this driver as DMA is not
61 used and the common memory area is in low memory on the network card (my
62 current system has 20MB and I've not had problems yet).
63
64 The ability to load this driver as a loadable module has been included
65 and used extensively during the driver development (to save those long
66 reboot sequences). To utilise this ability, you have to do 8 things:
67
68 0) have a copy of the loadable modules code installed on your system.
69 1) copy ewrk3.c from the /linux/drivers/net directory to your favourite
70 temporary directory.
71 2) edit the source code near line 1898 to reflect the I/O address and
72 IRQ you're using.
73 3) compile ewrk3.c, but include -DMODULE in the command line to ensure
74 that the correct bits are compiled (see end of source code).
75 4) if you are wanting to add a new card, goto 5. Otherwise, recompile a
76 kernel with the ewrk3 configuration turned off and reboot.
77 5) insmod ewrk3.o
78 [Alan Cox: Changed this so you can insmod ewrk3.o irq=x io=y]
79 [Adam Kropelin: now accepts irq=x1,x2 io=y1,y2 for multiple cards]
80 6) run the net startup bits for your new eth?? interface manually
81 (usually /etc/rc.inet[12] at boot time).
82 7) enjoy!
83
84 Note that autoprobing is not allowed in loadable modules - the system is
85 already up and running and you're messing with interrupts.
86
87 To unload a module, turn off the associated interface
88 'ifconfig eth?? down' then 'rmmod ewrk3'.
89
90 Promiscuous mode has been turned off in this driver, but all the
91 multicast address bits have been turned on. This improved the send
92 performance on a busy network by about 13%.
93
94 Ioctl's have now been provided (primarily because I wanted to grab some
95 packet size statistics). They are patterned after 'plipconfig.c' from a
96 suggestion by Alan Cox. Using these ioctls, you can enable promiscuous
97 mode, add/delete multicast addresses, change the hardware address, get
98 packet size distribution statistics and muck around with the control and
99 status register. I'll add others if and when the need arises.
100
101 TO DO:
102 ------
103
104
105 Revision History
106 ----------------
107
108 Version Date Description
109
110 0.1 26-aug-94 Initial writing. ALPHA code release.
111 0.11 31-aug-94 Fixed: 2k mode memory base calc.,
112 LeMAC version calc.,
113 IRQ vector assignments during autoprobe.
114 0.12 31-aug-94 Tested working on LeMAC2 (DE20[345]-AC) card.
115 Fixed up MCA hash table algorithm.
116 0.20 4-sep-94 Added IOCTL functionality.
117 0.21 14-sep-94 Added I/O mode.
118 0.21axp 15-sep-94 Special version for ALPHA AXP Linux V1.0.
119 0.22 16-sep-94 Added more IOCTLs & tidied up.
120 0.23 21-sep-94 Added transmit cut through.
121 0.24 31-oct-94 Added uid checks in some ioctls.
122 0.30 1-nov-94 BETA code release.
123 0.31 5-dec-94 Added check/allocate region code.
124 0.32 16-jan-95 Broadcast packet fix.
125 0.33 10-Feb-95 Fix recognition bug reported by <bkm@star.rl.ac.uk>.
126 0.40 27-Dec-95 Rationalise MODULE and autoprobe code.
127 Rewrite for portability & updated.
128 ALPHA support from <jestabro@amt.tay1.dec.com>
129 Added verify_area() calls in ewrk3_ioctl() from
130 suggestion by <heiko@colossus.escape.de>.
131 Add new multicasting code.
132 0.41 20-Jan-96 Fix IRQ set up problem reported by
133 <kenneth@bbs.sas.ntu.ac.sg>.
134 0.42 22-Apr-96 Fix alloc_device() bug <jari@markkus2.fimr.fi>
135 0.43 16-Aug-96 Update alloc_device() to conform to de4x5.c
136 0.44 08-Nov-01 use library crc32 functions <Matt_Domsch@dell.com>
137 0.45 19-Jul-02 fix unaligned access on alpha <martin@bruli.net>
138 0.46 10-Oct-02 Multiple NIC support when module <akropel1@rochester.rr.com>
139 0.47 18-Oct-02 ethtool support <akropel1@rochester.rr.com>
140 0.48 18-Oct-02 cli/sti removal for 2.5 <vda@port.imtp.ilyichevsk.odessa.ua>
141 ioctl locking, signature search cleanup <akropel1@rochester.rr.com>
142
143 =========================================================================
144 */
145
146#include <linux/module.h>
147#include <linux/kernel.h>
d43c36dc 148#include <linux/sched.h>
1da177e4
LT		 149#include <linux/string.h>
150#include <linux/errno.h>
151#include <linux/ioport.h>
152#include <linux/slab.h>
153#include <linux/interrupt.h>
154#include <linux/delay.h>
155#include <linux/init.h>
156#include <linux/crc32.h>
157#include <linux/netdevice.h>
158#include <linux/etherdevice.h>
159#include <linux/skbuff.h>
160#include <linux/ethtool.h>
161#include <linux/time.h>
162#include <linux/types.h>
163#include <linux/unistd.h>
164#include <linux/ctype.h>
165#include <linux/bitops.h>
166
167#include <asm/io.h>
168#include <asm/dma.h>
169#include <asm/uaccess.h>
170
171#include "ewrk3.h"
172
173#define DRV_NAME "ewrk3"
174#define DRV_VERSION "0.48"
175
176static char version[] __initdata =
177DRV_NAME ":v" DRV_VERSION " 2002/10/18 davies@maniac.ultranet.com\n";
178
179#ifdef EWRK3_DEBUG
180static int ewrk3_debug = EWRK3_DEBUG;
181#else
182static int ewrk3_debug = 1;
183#endif
184
185#define EWRK3_NDA 0xffe0 /* No Device Address */
186
187#define PROBE_LENGTH 32
188#define ETH_PROM_SIG 0xAA5500FFUL
189
190#ifndef EWRK3_SIGNATURE
191#define EWRK3_SIGNATURE {"DE203","DE204","DE205",""}
192#define EWRK3_STRLEN 8
193#endif
194
195#ifndef EWRK3_RAM_BASE_ADDRESSES
196#define EWRK3_RAM_BASE_ADDRESSES {0xc0000,0xd0000,0x00000}
197#endif
198
199/*
200 ** Sets up the I/O area for the autoprobe.
201 */
202#define EWRK3_IO_BASE 0x100 /* Start address for probe search */
203#define EWRK3_IOP_INC 0x20 /* I/O address increment */
204#define EWRK3_TOTAL_SIZE 0x20 /* required I/O address length */
205
206#ifndef MAX_NUM_EWRK3S
207#define MAX_NUM_EWRK3S 21
208#endif
209
210#ifndef EWRK3_EISA_IO_PORTS
211#define EWRK3_EISA_IO_PORTS 0x0c00 /* I/O port base address, slot 0 */
212#endif
213
214#ifndef MAX_EISA_SLOTS
215#define MAX_EISA_SLOTS 16
216#define EISA_SLOT_INC 0x1000
217#endif
218
219#define QUEUE_PKT_TIMEOUT (1*HZ) /* Jiffies */
220
221/*
222 ** EtherWORKS 3 shared memory window sizes
223 */
224#define IO_ONLY 0x00
225#define SHMEM_2K 0x800
226#define SHMEM_32K 0x8000
227#define SHMEM_64K 0x10000
228
229/*
230 ** EtherWORKS 3 IRQ ENABLE/DISABLE
231 */
232#define ENABLE_IRQs { \
233 icr |= lp->irq_mask;\
234 outb(icr, EWRK3_ICR); /* Enable the IRQs */\
235}
236
237#define DISABLE_IRQs { \
238 icr = inb(EWRK3_ICR);\
239 icr &= ~lp->irq_mask;\
240 outb(icr, EWRK3_ICR); /* Disable the IRQs */\
241}
242
243/*
244 ** EtherWORKS 3 START/STOP
245 */
246#define START_EWRK3 { \
247 csr = inb(EWRK3_CSR);\
248 csr &= ~(CSR_TXD|CSR_RXD);\
249 outb(csr, EWRK3_CSR); /* Enable the TX and/or RX */\
250}
251
252#define STOP_EWRK3 { \
253 csr = (CSR_TXD|CSR_RXD);\
254 outb(csr, EWRK3_CSR); /* Disable the TX and/or RX */\
255}
256
257/*
258 ** The EtherWORKS 3 private structure
259 */
260#define EWRK3_PKT_STAT_SZ 16
261#define EWRK3_PKT_BIN_SZ 128 /* Should be >=100 unless you
262 increase EWRK3_PKT_STAT_SZ */
263
264struct ewrk3_stats {
265 u32 bins[EWRK3_PKT_STAT_SZ];
266 u32 unicast;
267 u32 multicast;
268 u32 broadcast;
269 u32 excessive_collisions;
270 u32 tx_underruns;
271 u32 excessive_underruns;
272};
273
274struct ewrk3_private {
275 char adapter_name[80]; /* Name exported to /proc/ioports */
276 u_long shmem_base; /* Shared memory start address */
277 void __iomem *shmem;
278 u_long shmem_length; /* Shared memory window length */
1da177e4
LT		 279 struct ewrk3_stats pktStats; /* Private stats counters */
280 u_char irq_mask; /* Adapter IRQ mask bits */
281 u_char mPage; /* Maximum 2kB Page number */
282 u_char lemac; /* Chip rev. level */
283 u_char hard_strapped; /* Don't allow a full open */
284 u_char txc; /* Transmit cut through */
285 void __iomem *mctbl; /* Pointer to the multicast table */
286 u_char led_mask; /* Used to reserve LED access for ethtool */
287 spinlock_t hw_lock;
288};
289
290/*
291 ** Force the EtherWORKS 3 card to be in 2kB MODE
292 */
293#define FORCE_2K_MODE { \
294 shmem_length = SHMEM_2K;\
295 outb(((mem_start - 0x80000) >> 11), EWRK3_MBR);\
296}
297
298/*
299 ** Public Functions
300 */
301static int ewrk3_open(struct net_device *dev);
61357325 302static netdev_tx_t ewrk3_queue_pkt(struct sk_buff *skb, struct net_device *dev);
7d12e780 303static irqreturn_t ewrk3_interrupt(int irq, void *dev_id);
1da177e4 304static int ewrk3_close(struct net_device *dev);
1da177e4
LT		 305static void set_multicast_list(struct net_device *dev);
306static int ewrk3_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
7282d491
JG		 307static const struct ethtool_ops ethtool_ops_203;
308static const struct ethtool_ops ethtool_ops;
1da177e4
LT		 309
310/*
311 ** Private functions
312 */
313static int ewrk3_hw_init(struct net_device *dev, u_long iobase);
314static void ewrk3_init(struct net_device *dev);
315static int ewrk3_rx(struct net_device *dev);
316static int ewrk3_tx(struct net_device *dev);
317static void ewrk3_timeout(struct net_device *dev);
318
319static void EthwrkSignature(char *name, char *eeprom_image);
320static int DevicePresent(u_long iobase);
321static void SetMulticastFilter(struct net_device *dev);
322static int EISA_signature(char *name, s32 eisa_id);
323
324static int Read_EEPROM(u_long iobase, u_char eaddr);
325static int Write_EEPROM(short data, u_long iobase, u_char eaddr);
326static u_char get_hw_addr(struct net_device *dev, u_char * eeprom_image, char chipType);
327
328static int ewrk3_probe1(struct net_device *dev, u_long iobase, int irq);
329static int isa_probe(struct net_device *dev, u_long iobase);
330static int eisa_probe(struct net_device *dev, u_long iobase);
331
332static u_char irq[MAX_NUM_EWRK3S+1] = {5, 0, 10, 3, 11, 9, 15, 12};
333
334static char name[EWRK3_STRLEN + 1];
335static int num_ewrks3s;
336
337/*
338 ** Miscellaneous defines...
339 */
340#define INIT_EWRK3 {\
341 outb(EEPROM_INIT, EWRK3_IOPR);\
342 mdelay(1);\
343}
344
345#ifndef MODULE
346struct net_device * __init ewrk3_probe(int unit)
347{
348 struct net_device *dev = alloc_etherdev(sizeof(struct ewrk3_private));
349 int err;
350
351 if (!dev)
352 return ERR_PTR(-ENOMEM);
353
354 if (unit >= 0) {
355 sprintf(dev->name, "eth%d", unit);
356 netdev_boot_setup_check(dev);
357 }
1da177e4
LT		 358
359 err = ewrk3_probe1(dev, dev->base_addr, dev->irq);
6aa20a22 360 if (err)
1da177e4
LT		 361 goto out;
362 return dev;
363out:
364 free_netdev(dev);
365 return ERR_PTR(err);
6aa20a22 366
1da177e4
LT		 367}
368#endif
369
370static int __init ewrk3_probe1(struct net_device *dev, u_long iobase, int irq)
371{
372 int err;
373
374 dev->base_addr = iobase;
375 dev->irq = irq;
376
377 /* Address PROM pattern */
378 err = isa_probe(dev, iobase);
6aa20a22 379 if (err != 0)
1da177e4
LT		 380 err = eisa_probe(dev, iobase);
381
382 if (err)
383 return err;
384
385 err = register_netdev(dev);
386 if (err)
387 release_region(dev->base_addr, EWRK3_TOTAL_SIZE);
388
389 return err;
390}
391
968804d9
SH		 392static const struct net_device_ops ewrk3_netdev_ops = {
393 .ndo_open = ewrk3_open,
394 .ndo_start_xmit = ewrk3_queue_pkt,
395 .ndo_stop = ewrk3_close,
afc4b13d 396 .ndo_set_rx_mode = set_multicast_list,
968804d9
SH		 397 .ndo_do_ioctl = ewrk3_ioctl,
398 .ndo_tx_timeout = ewrk3_timeout,
399 .ndo_change_mtu = eth_change_mtu,
400 .ndo_set_mac_address = eth_mac_addr,
401 .ndo_validate_addr = eth_validate_addr,
402};
403
6aa20a22 404static int __init
1da177e4
LT		 405ewrk3_hw_init(struct net_device *dev, u_long iobase)
406{
407 struct ewrk3_private *lp;
408 int i, status = 0;
409 u_long mem_start, shmem_length;
410 u_char cr, cmr, icr, nicsr, lemac, hard_strapped = 0;
411 u_char eeprom_image[EEPROM_MAX], chksum, eisa_cr = 0;
412
413 /*
414 ** Stop the EWRK3. Enable the DBR ROM. Disable interrupts and remote boot.
415 ** This also disables the EISA_ENABLE bit in the EISA Control Register.
416 */
417 if (iobase > 0x400)
418 eisa_cr = inb(EISA_CR);
419 INIT_EWRK3;
420
421 nicsr = inb(EWRK3_CSR);
422
423 icr = inb(EWRK3_ICR);
424 icr &= 0x70;
425 outb(icr, EWRK3_ICR); /* Disable all the IRQs */
426
991b5557 427 if (nicsr != (CSR_TXD | CSR_RXD))
1da177e4
LT		 428 return -ENXIO;
429
1da177e4
LT		 430 /* Check that the EEPROM is alive and well and not living on Pluto... */
431 for (chksum = 0, i = 0; i < EEPROM_MAX; i += 2) {
432 union {
433 short val;
434 char c[2];
435 } tmp;
436
437 tmp.val = (short) Read_EEPROM(iobase, (i >> 1));
438 eeprom_image[i] = tmp.c[0];
439 eeprom_image[i + 1] = tmp.c[1];
440 chksum += eeprom_image[i] + eeprom_image[i + 1];
441 }
442
443 if (chksum != 0) { /* Bad EEPROM Data! */
444 printk("%s: Device has a bad on-board EEPROM.\n", dev->name);
445 return -ENXIO;
446 }
6aa20a22 447
1da177e4 448 EthwrkSignature(name, eeprom_image);
6aa20a22 449 if (*name == '\0')
1da177e4
LT		 450 return -ENXIO;
451
452 dev->base_addr = iobase;
6aa20a22 453
1da177e4
LT		 454 if (iobase > 0x400) {
455 outb(eisa_cr, EISA_CR); /* Rewrite the EISA CR */
456 }
457 lemac = eeprom_image[EEPROM_CHIPVER];
458 cmr = inb(EWRK3_CMR);
6aa20a22 459
1da177e4
LT		 460 if (((lemac == LeMAC) && ((cmr & CMR_NO_EEPROM) != CMR_NO_EEPROM)) ||
461 ((lemac == LeMAC2) && !(cmr & CMR_HS))) {
462 printk("%s: %s at %#4lx", dev->name, name, iobase);
463 hard_strapped = 1;
464 } else if ((iobase & 0x0fff) == EWRK3_EISA_IO_PORTS) {
465 /* EISA slot address */
466 printk("%s: %s at %#4lx (EISA slot %ld)",
467 dev->name, name, iobase, ((iobase >> 12) & 0x0f));
468 } else { /* ISA port address */
469 printk("%s: %s at %#4lx", dev->name, name, iobase);
470 }
471
472 printk(", h/w address ");
473 if (lemac != LeMAC2)
474 DevicePresent(iobase); /* need after EWRK3_INIT */
475 status = get_hw_addr(dev, eeprom_image, lemac);
e174961c 476 printk("%pM\n", dev->dev_addr);
6aa20a22 477
1da177e4
LT		 478 if (status) {
479 printk(" which has an EEPROM CRC error.\n");
480 return -ENXIO;
481 }
482
483 if (lemac == LeMAC2) { /* Special LeMAC2 CMR things */
484 cmr &= ~(CMR_RA | CMR_WB | CMR_LINK | CMR_POLARITY | CMR_0WS);
485 if (eeprom_image[EEPROM_MISC0] & READ_AHEAD)
486 cmr |= CMR_RA;
487 if (eeprom_image[EEPROM_MISC0] & WRITE_BEHIND)
488 cmr |= CMR_WB;
489 if (eeprom_image[EEPROM_NETMAN0] & NETMAN_POL)
490 cmr |= CMR_POLARITY;
491 if (eeprom_image[EEPROM_NETMAN0] & NETMAN_LINK)
492 cmr |= CMR_LINK;
493 if (eeprom_image[EEPROM_MISC0] & _0WS_ENA)
494 cmr |= CMR_0WS;
495 }
496 if (eeprom_image[EEPROM_SETUP] & SETUP_DRAM)
497 cmr |= CMR_DRAM;
498 outb(cmr, EWRK3_CMR);
6aa20a22 499
1da177e4
LT		 500 cr = inb(EWRK3_CR); /* Set up the Control Register */
501 cr |= eeprom_image[EEPROM_SETUP] & SETUP_APD;
502 if (cr & SETUP_APD)
503 cr |= eeprom_image[EEPROM_SETUP] & SETUP_PS;
504 cr |= eeprom_image[EEPROM_MISC0] & FAST_BUS;
505 cr |= eeprom_image[EEPROM_MISC0] & ENA_16;
506 outb(cr, EWRK3_CR);
507
508 /*
509 ** Determine the base address and window length for the EWRK3
510 ** RAM from the memory base register.
511 */
512 mem_start = inb(EWRK3_MBR);
513 shmem_length = 0;
514 if (mem_start != 0) {
515 if ((mem_start >= 0x0a) && (mem_start <= 0x0f)) {
516 mem_start *= SHMEM_64K;
517 shmem_length = SHMEM_64K;
518 } else if ((mem_start >= 0x14) && (mem_start <= 0x1f)) {
519 mem_start *= SHMEM_32K;
520 shmem_length = SHMEM_32K;
521 } else if ((mem_start >= 0x40) && (mem_start <= 0xff)) {
522 mem_start = mem_start * SHMEM_2K + 0x80000;
523 shmem_length = SHMEM_2K;
524 } else {
525 return -ENXIO;
526 }
527 }
528 /*
529 ** See the top of this source code for comments about
530 ** uncommenting this line.
531 */
532/* FORCE_2K_MODE; */
6aa20a22 533
1da177e4
LT		 534 if (hard_strapped) {
535 printk(" is hard strapped.\n");
536 } else if (mem_start) {
537 printk(" has a %dk RAM window", (int) (shmem_length >> 10));
538 printk(" at 0x%.5lx", mem_start);
539 } else {
540 printk(" is in I/O only mode");
541 }
542
543 lp = netdev_priv(dev);
544 lp->shmem_base = mem_start;
545 lp->shmem = ioremap(mem_start, shmem_length);
546 if (!lp->shmem)
547 return -ENOMEM;
548 lp->shmem_length = shmem_length;
549 lp->lemac = lemac;
550 lp->hard_strapped = hard_strapped;
551 lp->led_mask = CR_LED;
552 spin_lock_init(&lp->hw_lock);
6aa20a22 553
1da177e4
LT		 554 lp->mPage = 64;
555 if (cmr & CMR_DRAM)
556 lp->mPage <<= 1; /* 2 DRAMS on module */
6aa20a22 557
1da177e4 558 sprintf(lp->adapter_name, "%s (%s)", name, dev->name);
6aa20a22 559
1da177e4 560 lp->irq_mask = ICR_TNEM | ICR_TXDM | ICR_RNEM | ICR_RXDM;
6aa20a22 561
1da177e4
LT		 562 if (!hard_strapped) {
563 /*
564 ** Enable EWRK3 board interrupts for autoprobing
565 */
566 icr |= ICR_IE; /* Enable interrupts */
567 outb(icr, EWRK3_ICR);
6aa20a22 568
1da177e4
LT		 569 /* The DMA channel may be passed in on this parameter. */
570 dev->dma = 0;
6aa20a22 571
1da177e4
LT		 572 /* To auto-IRQ we enable the initialization-done and DMA err,
573 interrupts. For now we will always get a DMA error. */
574 if (dev->irq < 2) {
575#ifndef MODULE
576 u_char irqnum;
577 unsigned long irq_mask;
6aa20a22 578
1da177e4
LT		 579
580 irq_mask = probe_irq_on();
6aa20a22 581
1da177e4
LT		 582 /*
583 ** Trigger a TNE interrupt.
584 */
585 icr |= ICR_TNEM;
586 outb(1, EWRK3_TDQ); /* Write to the TX done queue */
587 outb(icr, EWRK3_ICR); /* Unmask the TXD interrupt */
6aa20a22 588
1da177e4 589 irqnum = irq[((icr & IRQ_SEL) >> 4)];
6aa20a22 590
1da177e4
LT		 591 mdelay(20);
592 dev->irq = probe_irq_off(irq_mask);
593 if ((dev->irq) && (irqnum == dev->irq)) {
594 printk(" and uses IRQ%d.\n", dev->irq);
595 } else {
596 if (!dev->irq) {
597 printk(" and failed to detect IRQ line.\n");
598 } else if ((irqnum == 1) && (lemac == LeMAC2)) {
599 printk(" and an illegal IRQ line detected.\n");
600 } else {
601 printk(", but incorrect IRQ line detected.\n");
602 }
603 iounmap(lp->shmem);
604 return -ENXIO;
605 }
606
607 DISABLE_IRQs; /* Mask all interrupts */
608
609#endif /* MODULE */
610 } else {
611 printk(" and requires IRQ%d.\n", dev->irq);
612 }
613 }
614
615 if (ewrk3_debug > 1) {
616 printk(version);
617 }
618 /* The EWRK3-specific entries in the device structure. */
968804d9 619 dev->netdev_ops = &ewrk3_netdev_ops;
1da177e4
LT		 620 if (lp->adapter_name[4] == '3')
621 SET_ETHTOOL_OPS(dev, &ethtool_ops_203);
622 else
623 SET_ETHTOOL_OPS(dev, &ethtool_ops);
1da177e4 624 dev->watchdog_timeo = QUEUE_PKT_TIMEOUT;
6aa20a22 625
1da177e4
LT		 626 dev->mem_start = 0;
627
628 return 0;
629}
6aa20a22 630
1da177e4
LT		 631
632static int ewrk3_open(struct net_device *dev)
633{
634 struct ewrk3_private *lp = netdev_priv(dev);
635 u_long iobase = dev->base_addr;
0795af57 636 int status = 0;
1da177e4
LT		 637 u_char icr, csr;
638
639 /*
640 ** Stop the TX and RX...
641 */
642 STOP_EWRK3;
643
644 if (!lp->hard_strapped) {
645 if (request_irq(dev->irq, (void *) ewrk3_interrupt, 0, "ewrk3", dev)) {
646 printk("ewrk3_open(): Requested IRQ%d is busy\n", dev->irq);
647 status = -EAGAIN;
648 } else {
649
650 /*
651 ** Re-initialize the EWRK3...
652 */
653 ewrk3_init(dev);
654
655 if (ewrk3_debug > 1) {
656 printk("%s: ewrk3 open with irq %d\n", dev->name, dev->irq);
e174961c 657 printk(" physical address: %pM\n", dev->dev_addr);
1da177e4
LT		 658 if (lp->shmem_length == 0) {
659 printk(" no shared memory, I/O only mode\n");
660 } else {
661 printk(" start of shared memory: 0x%08lx\n", lp->shmem_base);
662 printk(" window length: 0x%04lx\n", lp->shmem_length);
663 }
664 printk(" # of DRAMS: %d\n", ((inb(EWRK3_CMR) & 0x02) ? 2 : 1));
665 printk(" csr: 0x%02x\n", inb(EWRK3_CSR));
666 printk(" cr: 0x%02x\n", inb(EWRK3_CR));
667 printk(" icr: 0x%02x\n", inb(EWRK3_ICR));
668 printk(" cmr: 0x%02x\n", inb(EWRK3_CMR));
669 printk(" fmqc: 0x%02x\n", inb(EWRK3_FMQC));
670 }
671 netif_start_queue(dev);
672 /*
673 ** Unmask EWRK3 board interrupts
674 */
675 icr = inb(EWRK3_ICR);
676 ENABLE_IRQs;
677
678 }
679 } else {
680 printk(KERN_ERR "%s: ewrk3 available for hard strapped set up only.\n", dev->name);
681 printk(KERN_ERR " Run the 'ewrk3setup' utility or remove the hard straps.\n");
682 return -EINVAL;
683 }
684
685 return status;
686}
687
688/*
689 ** Initialize the EtherWORKS 3 operating conditions
690 */
691static void ewrk3_init(struct net_device *dev)
692{
693 struct ewrk3_private *lp = netdev_priv(dev);
694 u_char csr, page;
695 u_long iobase = dev->base_addr;
696 int i;
697
698 /*
699 ** Enable any multicasts
700 */
701 set_multicast_list(dev);
702
703 /*
704 ** Set hardware MAC address. Address is initialized from the EEPROM
705 ** during startup but may have since been changed by the user.
706 */
707 for (i=0; i<ETH_ALEN; i++)
708 outb(dev->dev_addr[i], EWRK3_PAR0 + i);
709
710 /*
711 ** Clean out any remaining entries in all the queues here
712 */
713 while (inb(EWRK3_TQ));
714 while (inb(EWRK3_TDQ));
715 while (inb(EWRK3_RQ));
716 while (inb(EWRK3_FMQ));
717
718 /*
719 ** Write a clean free memory queue
720 */
721 for (page = 1; page < lp->mPage; page++) { /* Write the free page numbers */
722 outb(page, EWRK3_FMQ); /* to the Free Memory Queue */
723 }
724
725 START_EWRK3; /* Enable the TX and/or RX */
726}
727
728/*
729 * Transmit timeout
730 */
6aa20a22 731
1da177e4
LT		 732static void ewrk3_timeout(struct net_device *dev)
733{
734 struct ewrk3_private *lp = netdev_priv(dev);
735 u_char icr, csr;
736 u_long iobase = dev->base_addr;
6aa20a22
JG		 737
738 if (!lp->hard_strapped)
1da177e4
LT		 739 {
740 printk(KERN_WARNING"%s: transmit timed/locked out, status %04x, resetting.\n",
741 dev->name, inb(EWRK3_CSR));
742
743 /*
744 ** Mask all board interrupts
745 */
746 DISABLE_IRQs;
747
748 /*
749 ** Stop the TX and RX...
750 */
751 STOP_EWRK3;
752
753 ewrk3_init(dev);
754
755 /*
756 ** Unmask EWRK3 board interrupts
757 */
758 ENABLE_IRQs;
759
1ae5dc34 760 dev->trans_start = jiffies; /* prevent tx timeout */
1da177e4
LT		 761 netif_wake_queue(dev);
762 }
763}
764
765/*
766 ** Writes a socket buffer to the free page queue
767 */
61357325 768static netdev_tx_t ewrk3_queue_pkt(struct sk_buff *skb, struct net_device *dev)
1da177e4
LT		 769{
770 struct ewrk3_private *lp = netdev_priv(dev);
771 u_long iobase = dev->base_addr;
772 void __iomem *buf = NULL;
773 u_char icr;
774 u_char page;
775
776 spin_lock_irq (&lp->hw_lock);
777 DISABLE_IRQs;
778
779 /* if no resources available, exit, request packet be queued */
780 if (inb (EWRK3_FMQC) == 0) {
781 printk (KERN_WARNING "%s: ewrk3_queue_pkt(): No free resources...\n",
782 dev->name);
783 printk (KERN_WARNING "%s: ewrk3_queue_pkt(): CSR: %02x ICR: %02x FMQC: %02x\n",
784 dev->name, inb (EWRK3_CSR), inb (EWRK3_ICR),
785 inb (EWRK3_FMQC));
786 goto err_out;
787 }
788
789 /*
790 ** Get a free page from the FMQ
791 */
792 if ((page = inb (EWRK3_FMQ)) >= lp->mPage) {
793 printk ("ewrk3_queue_pkt(): Invalid free memory page (%d).\n",
794 (u_char) page);
795 goto err_out;
796 }
797
798
799 /*
800 ** Set up shared memory window and pointer into the window
801 */
802 if (lp->shmem_length == IO_ONLY) {
803 outb (page, EWRK3_IOPR);
804 } else if (lp->shmem_length == SHMEM_2K) {
805 buf = lp->shmem;
806 outb (page, EWRK3_MPR);
807 } else if (lp->shmem_length == SHMEM_32K) {
808 buf = (((short) page << 11) & 0x7800) + lp->shmem;
809 outb ((page >> 4), EWRK3_MPR);
810 } else if (lp->shmem_length == SHMEM_64K) {
811 buf = (((short) page << 11) & 0xf800) + lp->shmem;
812 outb ((page >> 5), EWRK3_MPR);
813 } else {
814 printk (KERN_ERR "%s: Oops - your private data area is hosed!\n",
815 dev->name);
816 BUG ();
817 }
818
819 /*
820 ** Set up the buffer control structures and copy the data from
821 ** the socket buffer to the shared memory .
822 */
823 if (lp->shmem_length == IO_ONLY) {
824 int i;
825 u_char *p = skb->data;
826 outb ((char) (TCR_QMODE | TCR_PAD | TCR_IFC), EWRK3_DATA);
827 outb ((char) (skb->len & 0xff), EWRK3_DATA);
828 outb ((char) ((skb->len >> 8) & 0xff), EWRK3_DATA);
829 outb ((char) 0x04, EWRK3_DATA);
830 for (i = 0; i < skb->len; i++) {
831 outb (*p++, EWRK3_DATA);
832 }
833 outb (page, EWRK3_TQ); /* Start sending pkt */
834 } else {
835 writeb ((char) (TCR_QMODE | TCR_PAD | TCR_IFC), buf); /* ctrl byte */
836 buf += 1;
837 writeb ((char) (skb->len & 0xff), buf); /* length (16 bit xfer) */
838 buf += 1;
839 if (lp->txc) {
840 writeb(((skb->len >> 8) & 0xff) | XCT, buf);
841 buf += 1;
842 writeb (0x04, buf); /* index byte */
843 buf += 1;
844 writeb (0x00, (buf + skb->len)); /* Write the XCT flag */
845 memcpy_toio (buf, skb->data, PRELOAD); /* Write PRELOAD bytes */
846 outb (page, EWRK3_TQ); /* Start sending pkt */
847 memcpy_toio (buf + PRELOAD,
848 skb->data + PRELOAD,
849 skb->len - PRELOAD);
850 writeb (0xff, (buf + skb->len)); /* Write the XCT flag */
851 } else {
852 writeb ((skb->len >> 8) & 0xff, buf);
853 buf += 1;
854 writeb (0x04, buf); /* index byte */
855 buf += 1;
856 memcpy_toio (buf, skb->data, skb->len); /* Write data bytes */
857 outb (page, EWRK3_TQ); /* Start sending pkt */
858 }
859 }
860
861 ENABLE_IRQs;
862 spin_unlock_irq (&lp->hw_lock);
863
09f75cd7 864 dev->stats.tx_bytes += skb->len;
1da177e4
LT		 865 dev_kfree_skb (skb);
866
867 /* Check for free resources: stop Tx queue if there are none */
868 if (inb (EWRK3_FMQC) == 0)
869 netif_stop_queue (dev);
870
6ed10654 871 return NETDEV_TX_OK;
1da177e4
LT		 872
873err_out:
874 ENABLE_IRQs;
875 spin_unlock_irq (&lp->hw_lock);
5b548140 876 return NETDEV_TX_BUSY;
1da177e4
LT		 877}
878
879/*
880 ** The EWRK3 interrupt handler.
881 */
7d12e780 882static irqreturn_t ewrk3_interrupt(int irq, void *dev_id)
1da177e4
LT		 883{
884 struct net_device *dev = dev_id;
885 struct ewrk3_private *lp;
886 u_long iobase;
887 u_char icr, cr, csr;
888
889 lp = netdev_priv(dev);
890 iobase = dev->base_addr;
891
892 /* get the interrupt information */
893 csr = inb(EWRK3_CSR);
894
895 /*
896 ** Mask the EWRK3 board interrupts and turn on the LED
897 */
898 spin_lock(&lp->hw_lock);
899 DISABLE_IRQs;
900
901 cr = inb(EWRK3_CR);
902 cr |= lp->led_mask;
903 outb(cr, EWRK3_CR);
904
905 if (csr & CSR_RNE) /* Rx interrupt (packet[s] arrived) */
906 ewrk3_rx(dev);
907
908 if (csr & CSR_TNE) /* Tx interrupt (packet sent) */
909 ewrk3_tx(dev);
910
911 /*
912 ** Now deal with the TX/RX disable flags. These are set when there
913 ** are no more resources. If resources free up then enable these
914 ** interrupts, otherwise mask them - failure to do this will result
915 ** in the system hanging in an interrupt loop.
916 */
917 if (inb(EWRK3_FMQC)) { /* any resources available? */
918 lp->irq_mask |= ICR_TXDM | ICR_RXDM; /* enable the interrupt source */
919 csr &= ~(CSR_TXD | CSR_RXD); /* ensure restart of a stalled TX or RX */
920 outb(csr, EWRK3_CSR);
921 netif_wake_queue(dev);
922 } else {
923 lp->irq_mask &= ~(ICR_TXDM | ICR_RXDM); /* disable the interrupt source */
924 }
925
926 /* Unmask the EWRK3 board interrupts and turn off the LED */
927 cr &= ~(lp->led_mask);
928 outb(cr, EWRK3_CR);
929 ENABLE_IRQs;
930 spin_unlock(&lp->hw_lock);
931 return IRQ_HANDLED;
932}
933
934/* Called with lp->hw_lock held */
935static int ewrk3_rx(struct net_device *dev)
936{
937 struct ewrk3_private *lp = netdev_priv(dev);
938 u_long iobase = dev->base_addr;
939 int i, status = 0;
940 u_char page;
941 void __iomem *buf = NULL;
942
943 while (inb(EWRK3_RQC) && !status) { /* Whilst there's incoming data */
944 if ((page = inb(EWRK3_RQ)) < lp->mPage) { /* Get next entry's buffer page */
945 /*
946 ** Set up shared memory window and pointer into the window
947 */
948 if (lp->shmem_length == IO_ONLY) {
949 outb(page, EWRK3_IOPR);
950 } else if (lp->shmem_length == SHMEM_2K) {
951 buf = lp->shmem;
952 outb(page, EWRK3_MPR);
953 } else if (lp->shmem_length == SHMEM_32K) {
954 buf = (((short) page << 11) & 0x7800) + lp->shmem;
955 outb((page >> 4), EWRK3_MPR);
956 } else if (lp->shmem_length == SHMEM_64K) {
957 buf = (((short) page << 11) & 0xf800) + lp->shmem;
958 outb((page >> 5), EWRK3_MPR);
959 } else {
960 status = -1;
961 printk("%s: Oops - your private data area is hosed!\n", dev->name);
962 }
963
964 if (!status) {
965 char rx_status;
966 int pkt_len;
967
968 if (lp->shmem_length == IO_ONLY) {
969 rx_status = inb(EWRK3_DATA);
970 pkt_len = inb(EWRK3_DATA);
971 pkt_len |= ((u_short) inb(EWRK3_DATA) << 8);
972 } else {
973 rx_status = readb(buf);
974 buf += 1;
975 pkt_len = readw(buf);
976 buf += 3;
977 }
978
979 if (!(rx_status & R_ROK)) { /* There was an error. */
09f75cd7 980 dev->stats.rx_errors++; /* Update the error stats. */
1da177e4 981 if (rx_status & R_DBE)
09f75cd7 982 dev->stats.rx_frame_errors++;
1da177e4 983 if (rx_status & R_CRC)
09f75cd7 984 dev->stats.rx_crc_errors++;
1da177e4 985 if (rx_status & R_PLL)
09f75cd7 986 dev->stats.rx_fifo_errors++;
1da177e4
LT		 987 } else {
988 struct sk_buff *skb;
21a4e469
PD		 989 skb = netdev_alloc_skb(dev,
990 pkt_len + 2);
1da177e4 991
21a4e469 992 if (skb != NULL) {
1da177e4 993 unsigned char *p;
1da177e4
LT		 994 skb_reserve(skb, 2); /* Align to 16 bytes */
995 p = skb_put(skb, pkt_len);
996
997 if (lp->shmem_length == IO_ONLY) {
998 *p = inb(EWRK3_DATA); /* dummy read */
999 for (i = 0; i < pkt_len; i++) {
1000 *p++ = inb(EWRK3_DATA);
1001 }
1002 } else {
1003 memcpy_fromio(p, buf, pkt_len);
1004 }
1005
1006 for (i = 1; i < EWRK3_PKT_STAT_SZ - 1; i++) {
1007 if (pkt_len < i * EWRK3_PKT_BIN_SZ) {
1008 lp->pktStats.bins[i]++;
1009 i = EWRK3_PKT_STAT_SZ;
1010 }
1011 }
1012 p = skb->data; /* Look at the dest addr */
d8ce2fc1
TK		 1013 if (is_multicast_ether_addr(p)) {
1014 if (is_broadcast_ether_addr(p)) {
1da177e4
LT		 1015 lp->pktStats.broadcast++;
1016 } else {
1017 lp->pktStats.multicast++;
1018 }
2e42e474
JP		 1019 } else if (ether_addr_equal(p,
1020 dev->dev_addr)) {
1da177e4
LT		 1021 lp->pktStats.unicast++;
1022 }
1023 lp->pktStats.bins[0]++; /* Duplicates stats.rx_packets */
1024 if (lp->pktStats.bins[0] == 0) { /* Reset counters */
1025 memset(&lp->pktStats, 0, sizeof(lp->pktStats));
1026 }
1027 /*
1028 ** Notify the upper protocol layers that there is another
1029 ** packet to handle
1030 */
1031 skb->protocol = eth_type_trans(skb, dev);
1032 netif_rx(skb);
1033
1034 /*
1035 ** Update stats
1036 */
09f75cd7
JG		 1037 dev->stats.rx_packets++;
1038 dev->stats.rx_bytes += pkt_len;
1da177e4
LT		 1039 } else {
1040 printk("%s: Insufficient memory; nuking packet.\n", dev->name);
09f75cd7 1041 dev->stats.rx_dropped++; /* Really, deferred. */
1da177e4
LT		 1042 break;
1043 }
1044 }
1045 }
1046 /*
1047 ** Return the received buffer to the free memory queue
1048 */
1049 outb(page, EWRK3_FMQ);
1050 } else {
1051 printk("ewrk3_rx(): Illegal page number, page %d\n", page);
1052 printk("ewrk3_rx(): CSR: %02x ICR: %02x FMQC: %02x\n", inb(EWRK3_CSR), inb(EWRK3_ICR), inb(EWRK3_FMQC));
1053 }
1054 }
1055 return status;
1056}
1057
1058/*
1059** Buffer sent - check for TX buffer errors.
1060** Called with lp->hw_lock held
1061*/
1062static int ewrk3_tx(struct net_device *dev)
1063{
1064 struct ewrk3_private *lp = netdev_priv(dev);
1065 u_long iobase = dev->base_addr;
1066 u_char tx_status;
1067
1068 while ((tx_status = inb(EWRK3_TDQ)) > 0) { /* Whilst there's old buffers */
1069 if (tx_status & T_VSTS) { /* The status is valid */
1070 if (tx_status & T_TXE) {
09f75cd7 1071 dev->stats.tx_errors++;
1da177e4 1072 if (tx_status & T_NCL)
09f75cd7 1073 dev->stats.tx_carrier_errors++;
1da177e4 1074 if (tx_status & T_LCL)
09f75cd7 1075 dev->stats.tx_window_errors++;
1da177e4
LT		 1076 if (tx_status & T_CTU) {
1077 if ((tx_status & T_COLL) ^ T_XUR) {
1078 lp->pktStats.tx_underruns++;
1079 } else {
1080 lp->pktStats.excessive_underruns++;
1081 }
1082 } else if (tx_status & T_COLL) {
1083 if ((tx_status & T_COLL) ^ T_XCOLL) {
09f75cd7 1084 dev->stats.collisions++;
1da177e4
LT		 1085 } else {
1086 lp->pktStats.excessive_collisions++;
1087 }
1088 }
1089 } else {
09f75cd7 1090 dev->stats.tx_packets++;
1da177e4
LT		 1091 }
1092 }
1093 }
1094
1095 return 0;
1096}
1097
1098static int ewrk3_close(struct net_device *dev)
1099{
1100 struct ewrk3_private *lp = netdev_priv(dev);
1101 u_long iobase = dev->base_addr;
1102 u_char icr, csr;
1103
1104 netif_stop_queue(dev);
6aa20a22 1105
1da177e4
LT		 1106 if (ewrk3_debug > 1) {
1107 printk("%s: Shutting down ethercard, status was %2.2x.\n",
1108 dev->name, inb(EWRK3_CSR));
1109 }
1110 /*
1111 ** We stop the EWRK3 here... mask interrupts and stop TX & RX
1112 */
1113 DISABLE_IRQs;
1114
1115 STOP_EWRK3;
1116
1117 /*
1118 ** Clean out the TX and RX queues here (note that one entry
1119 ** may get added to either the TXD or RX queues if the TX or RX
1120 ** just starts processing a packet before the STOP_EWRK3 command
1121 ** is received. This will be flushed in the ewrk3_open() call).
1122 */
1123 while (inb(EWRK3_TQ));
1124 while (inb(EWRK3_TDQ));
1125 while (inb(EWRK3_RQ));
1126
1127 if (!lp->hard_strapped) {
1128 free_irq(dev->irq, dev);
1129 }
1130 return 0;
1131}
1132
1da177e4
LT		 1133/*
1134 ** Set or clear the multicast filter for this adapter.
1135 */
1136static void set_multicast_list(struct net_device *dev)
1137{
1138 struct ewrk3_private *lp = netdev_priv(dev);
1139 u_long iobase = dev->base_addr;
1140 u_char csr;
1141
1142 csr = inb(EWRK3_CSR);
1143
1144 if (lp->shmem_length == IO_ONLY) {
1145 lp->mctbl = NULL;
1146 } else {
1147 lp->mctbl = lp->shmem + PAGE0_HTE;
1148 }
1149
1150 csr &= ~(CSR_PME | CSR_MCE);
1151 if (dev->flags & IFF_PROMISC) { /* set promiscuous mode */
1152 csr |= CSR_PME;
1153 outb(csr, EWRK3_CSR);
1154 } else {
1155 SetMulticastFilter(dev);
1156 csr |= CSR_MCE;
1157 outb(csr, EWRK3_CSR);
1158 }
1159}
1160
1161/*
1162 ** Calculate the hash code and update the logical address filter
1163 ** from a list of ethernet multicast addresses.
1164 ** Little endian crc one liner from Matt Thomas, DEC.
1165 **
1166 ** Note that when clearing the table, the broadcast bit must remain asserted
1167 ** to receive broadcast messages.
1168 */
1169static void SetMulticastFilter(struct net_device *dev)
1170{
1171 struct ewrk3_private *lp = netdev_priv(dev);
22bedad3 1172 struct netdev_hw_addr *ha;
1da177e4
LT		 1173 u_long iobase = dev->base_addr;
1174 int i;
498d8e23 1175 char bit, byte;
1da177e4
LT		 1176 short __iomem *p = lp->mctbl;
1177 u16 hashcode;
1178 u32 crc;
1179
1180 spin_lock_irq(&lp->hw_lock);
1181
1182 if (lp->shmem_length == IO_ONLY) {
1183 outb(0, EWRK3_IOPR);
1184 outw(PAGE0_HTE, EWRK3_PIR1);
1185 } else {
1186 outb(0, EWRK3_MPR);
1187 }
1188
1189 if (dev->flags & IFF_ALLMULTI) {
1190 for (i = 0; i < (HASH_TABLE_LEN >> 3); i++) {
1191 if (lp->shmem_length == IO_ONLY) {
1192 outb(0xff, EWRK3_DATA);
1193 } else { /* memset didn't work here */
1194 writew(0xffff, p);
1195 p++;
1196 i++;
1197 }
1198 }
1199 } else {
1200 /* Clear table except for broadcast bit */
1201 if (lp->shmem_length == IO_ONLY) {
1202 for (i = 0; i < (HASH_TABLE_LEN >> 4) - 1; i++) {
1203 outb(0x00, EWRK3_DATA);
1204 }
1205 outb(0x80, EWRK3_DATA);
1206 i++; /* insert the broadcast bit */
1207 for (; i < (HASH_TABLE_LEN >> 3); i++) {
1208 outb(0x00, EWRK3_DATA);
1209 }
1210 } else {
1211 memset_io(lp->mctbl, 0, HASH_TABLE_LEN >> 3);
1212 writeb(0x80, lp->mctbl + (HASH_TABLE_LEN >> 4) - 1);
1213 }
1214
1215 /* Update table */
22bedad3 1216 netdev_for_each_mc_addr(ha, dev) {
498d8e23
TK		 1217 crc = ether_crc_le(ETH_ALEN, ha->addr);
1218 hashcode = crc & ((1 << 9) - 1); /* hashcode is 9 LSb of CRC */
1da177e4 1219
498d8e23
TK		 1220 byte = hashcode >> 3; /* bit[3-8] -> byte in filter */
1221 bit = 1 << (hashcode & 0x07); /* bit[0-2] -> bit in byte */
1da177e4 1222
498d8e23
TK		 1223 if (lp->shmem_length == IO_ONLY) {
1224 u_char tmp;
1da177e4 1225
498d8e23
TK		 1226 outw(PAGE0_HTE + byte, EWRK3_PIR1);
1227 tmp = inb(EWRK3_DATA);
1228 tmp |= bit;
1229 outw(PAGE0_HTE + byte, EWRK3_PIR1);
1230 outb(tmp, EWRK3_DATA);
1231 } else {
1232 writeb(readb(lp->mctbl + byte) | bit, lp->mctbl + byte);
1da177e4
LT		 1233 }
1234 }
1235 }
1236
1237 spin_unlock_irq(&lp->hw_lock);
1238}
1239
1240/*
1241 ** ISA bus I/O device probe
1242 */
1243static int __init isa_probe(struct net_device *dev, u_long ioaddr)
1244{
1245 int i = num_ewrks3s, maxSlots;
1246 int ret = -ENODEV;
1247
1248 u_long iobase;
1249
1250 if (ioaddr >= 0x400)
1251 goto out;
1252
1253 if (ioaddr == 0) { /* Autoprobing */
1254 iobase = EWRK3_IO_BASE; /* Get the first slot address */
1255 maxSlots = 24;
1256 } else { /* Probe a specific location */
1257 iobase = ioaddr;
1258 maxSlots = i + 1;
1259 }
1260
1261 for (; (i < maxSlots) && (dev != NULL);
1262 iobase += EWRK3_IOP_INC, i++)
1263 {
1264 if (request_region(iobase, EWRK3_TOTAL_SIZE, DRV_NAME)) {
1265 if (DevicePresent(iobase) == 0) {
1266 int irq = dev->irq;
1267 ret = ewrk3_hw_init(dev, iobase);
1268 if (!ret)
1269 break;
1270 dev->irq = irq;
1271 }
1272 release_region(iobase, EWRK3_TOTAL_SIZE);
1273 }
1274 }
1275 out:
1276
1277 return ret;
1278}
1279
1280/*
1281 ** EISA bus I/O device probe. Probe from slot 1 since slot 0 is usually
1282 ** the motherboard.
1283 */
1284static int __init eisa_probe(struct net_device *dev, u_long ioaddr)
1285{
1286 int i, maxSlots;
1287 u_long iobase;
1288 int ret = -ENODEV;
1289
1290 if (ioaddr < 0x1000)
1291 goto out;
1292
6835d09a
AB		 1293 iobase = ioaddr;
1294 i = (ioaddr >> 12);
1295 maxSlots = i + 1;
1da177e4
LT		 1296
1297 for (i = 1; (i < maxSlots) && (dev != NULL); i++, iobase += EISA_SLOT_INC) {
1298 if (EISA_signature(name, EISA_ID) == 0) {
1299 if (request_region(iobase, EWRK3_TOTAL_SIZE, DRV_NAME) &&
1300 DevicePresent(iobase) == 0) {
1301 int irq = dev->irq;
1302 ret = ewrk3_hw_init(dev, iobase);
1303 if (!ret)
1304 break;
1305 dev->irq = irq;
1306 }
1307 release_region(iobase, EWRK3_TOTAL_SIZE);
1308 }
1309 }
1310
1311 out:
1312 return ret;
1313}
1314
1315
1316/*
1317 ** Read the EWRK3 EEPROM using this routine
1318 */
1319static int Read_EEPROM(u_long iobase, u_char eaddr)
1320{
1321 int i;
1322
1323 outb((eaddr & 0x3f), EWRK3_PIR1); /* set up 6 bits of address info */
1324 outb(EEPROM_RD, EWRK3_IOPR); /* issue read command */
1325 for (i = 0; i < 5000; i++)
1326 inb(EWRK3_CSR); /* wait 1msec */
1327
1328 return inw(EWRK3_EPROM1); /* 16 bits data return */
1329}
1330
1331/*
1332 ** Write the EWRK3 EEPROM using this routine
1333 */
1334static int Write_EEPROM(short data, u_long iobase, u_char eaddr)
1335{
1336 int i;
1337
1338 outb(EEPROM_WR_EN, EWRK3_IOPR); /* issue write enable command */
1339 for (i = 0; i < 5000; i++)
1340 inb(EWRK3_CSR); /* wait 1msec */
1341 outw(data, EWRK3_EPROM1); /* write data to register */
1342 outb((eaddr & 0x3f), EWRK3_PIR1); /* set up 6 bits of address info */
1343 outb(EEPROM_WR, EWRK3_IOPR); /* issue write command */
1344 for (i = 0; i < 75000; i++)
1345 inb(EWRK3_CSR); /* wait 15msec */
1346 outb(EEPROM_WR_DIS, EWRK3_IOPR); /* issue write disable command */
1347 for (i = 0; i < 5000; i++)
1348 inb(EWRK3_CSR); /* wait 1msec */
1349
1350 return 0;
1351}
1352
1353/*
1354 ** Look for a particular board name in the on-board EEPROM.
1355 */
1356static void __init EthwrkSignature(char *name, char *eeprom_image)
1357{
1358 int i;
1359 char *signatures[] = EWRK3_SIGNATURE;
1360
1361 for (i=0; *signatures[i] != '\0'; i++)
1362 if( !strncmp(eeprom_image+EEPROM_PNAME7, signatures[i], strlen(signatures[i])) )
1363 break;
1364
1365 if (*signatures[i] != '\0') {
1366 memcpy(name, eeprom_image+EEPROM_PNAME7, EWRK3_STRLEN);
1367 name[EWRK3_STRLEN] = '\0';
1368 } else
1369 name[0] = '\0';
1da177e4
LT		 1370}
1371
1372/*
1373 ** Look for a special sequence in the Ethernet station address PROM that
1374 ** is common across all EWRK3 products.
1375 **
1376 ** Search the Ethernet address ROM for the signature. Since the ROM address
1377 ** counter can start at an arbitrary point, the search must include the entire
1378 ** probe sequence length plus the (length_of_the_signature - 1).
1379 ** Stop the search IMMEDIATELY after the signature is found so that the
1380 ** PROM address counter is correctly positioned at the start of the
1381 ** ethernet address for later read out.
1382 */
1383
1384static int __init DevicePresent(u_long iobase)
1385{
1386 union {
1387 struct {
1388 u32 a;
1389 u32 b;
1390 } llsig;
1391 char Sig[sizeof(u32) << 1];
1392 }
1393 dev;
1394 short sigLength;
1395 char data;
1396 int i, j, status = 0;
1397
1398 dev.llsig.a = ETH_PROM_SIG;
1399 dev.llsig.b = ETH_PROM_SIG;
1400 sigLength = sizeof(u32) << 1;
1401
1402 for (i = 0, j = 0; j < sigLength && i < PROBE_LENGTH + sigLength - 1; i++) {
1403 data = inb(EWRK3_APROM);
1404 if (dev.Sig[j] == data) { /* track signature */
1405 j++;
1406 } else { /* lost signature; begin search again */
1407 if (data == dev.Sig[0]) {
1408 j = 1;
1409 } else {
1410 j = 0;
1411 }
1412 }
1413 }
1414
1415 if (j != sigLength) {
1416 status = -ENODEV; /* search failed */
1417 }
1418 return status;
1419}
1420
1421static u_char __init get_hw_addr(struct net_device *dev, u_char * eeprom_image, char chipType)
1422{
1423 int i, j, k;
1424 u_short chksum;
1425 u_char crc, lfsr, sd, status = 0;
1426 u_long iobase = dev->base_addr;
1427 u16 tmp;
1428
1429 if (chipType == LeMAC2) {
1430 for (crc = 0x6a, j = 0; j < ETH_ALEN; j++) {
1431 sd = dev->dev_addr[j] = eeprom_image[EEPROM_PADDR0 + j];
1432 outb(dev->dev_addr[j], EWRK3_PAR0 + j);
1433 for (k = 0; k < 8; k++, sd >>= 1) {
1434 lfsr = ((((crc & 0x02) >> 1) ^ (crc & 0x01)) ^ (sd & 0x01)) << 7;
1435 crc = (crc >> 1) + lfsr;
1436 }
1437 }
1438 if (crc != eeprom_image[EEPROM_PA_CRC])
1439 status = -1;
1440 } else {
1441 for (i = 0, k = 0; i < ETH_ALEN;) {
1442 k <<= 1;
1443 if (k > 0xffff)
1444 k -= 0xffff;
1445
1446 k += (u_char) (tmp = inb(EWRK3_APROM));
1447 dev->dev_addr[i] = (u_char) tmp;
1448 outb(dev->dev_addr[i], EWRK3_PAR0 + i);
1449 i++;
1450 k += (u_short) ((tmp = inb(EWRK3_APROM)) << 8);
1451 dev->dev_addr[i] = (u_char) tmp;
1452 outb(dev->dev_addr[i], EWRK3_PAR0 + i);
1453 i++;
1454
1455 if (k > 0xffff)
1456 k -= 0xffff;
1457 }
1458 if (k == 0xffff)
1459 k = 0;
1460 chksum = inb(EWRK3_APROM);
1461 chksum |= (inb(EWRK3_APROM) << 8);
1462 if (k != chksum)
1463 status = -1;
1464 }
1465
1466 return status;
1467}
1468
1469/*
1470 ** Look for a particular board name in the EISA configuration space
1471 */
1472static int __init EISA_signature(char *name, s32 eisa_id)
1473{
1474 u_long i;
1475 char *signatures[] = EWRK3_SIGNATURE;
1476 char ManCode[EWRK3_STRLEN];
1477 union {
1478 s32 ID;
1479 char Id[4];
1480 } Eisa;
1481 int status = 0;
1482
1483 *name = '\0';
1484 for (i = 0; i < 4; i++) {
1485 Eisa.Id[i] = inb(eisa_id + i);
1486 }
1487
1488 ManCode[0] = (((Eisa.Id[0] >> 2) & 0x1f) + 0x40);
1489 ManCode[1] = (((Eisa.Id[1] & 0xe0) >> 5) + ((Eisa.Id[0] & 0x03) << 3) + 0x40);
1490 ManCode[2] = (((Eisa.Id[2] >> 4) & 0x0f) + 0x30);
1491 ManCode[3] = ((Eisa.Id[2] & 0x0f) + 0x30);
1492 ManCode[4] = (((Eisa.Id[3] >> 4) & 0x0f) + 0x30);
1493 ManCode[5] = '\0';
1494
1495 for (i = 0; (*signatures[i] != '\0') && (*name == '\0'); i++) {
1496 if (strstr(ManCode, signatures[i]) != NULL) {
1497 strcpy(name, ManCode);
1498 status = 1;
1499 }
1500 }
1501
1502 return status; /* return the device name string */
1503}
1504
1505static void ewrk3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
1506{
1507 int fwrev = Read_EEPROM(dev->base_addr, EEPROM_REVLVL);
1508
1509 strcpy(info->driver, DRV_NAME);
1510 strcpy(info->version, DRV_VERSION);
1511 sprintf(info->fw_version, "%d", fwrev);
1512 strcpy(info->bus_info, "N/A");
1513 info->eedump_len = EEPROM_MAX;
1514}
1515
1516static int ewrk3_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
1517{
1518 struct ewrk3_private *lp = netdev_priv(dev);
1519 unsigned long iobase = dev->base_addr;
1520 u8 cr = inb(EWRK3_CR);
1521
1522 switch (lp->adapter_name[4]) {
1523 case '3': /* DE203 */
1524 ecmd->supported = SUPPORTED_BNC;
1525 ecmd->port = PORT_BNC;
1526 break;
1527
1528 case '4': /* DE204 */
1529 ecmd->supported = SUPPORTED_TP;
1530 ecmd->port = PORT_TP;
1531 break;
1532
1533 case '5': /* DE205 */
1534 ecmd->supported = SUPPORTED_TP | SUPPORTED_BNC | SUPPORTED_AUI;
1535 ecmd->autoneg = !(cr & CR_APD);
1536 /*
1537 ** Port is only valid if autoneg is disabled
1538 ** and even then we don't know if AUI is jumpered.
1539 */
1540 if (!ecmd->autoneg)
1541 ecmd->port = (cr & CR_PSEL) ? PORT_BNC : PORT_TP;
1542 break;
1543 }
1544
1545 ecmd->supported |= SUPPORTED_10baseT_Half;
70739497 1546 ethtool_cmd_speed_set(ecmd, SPEED_10);
1da177e4
LT		 1547 ecmd->duplex = DUPLEX_HALF;
1548 return 0;
1549}
1550
1551static int ewrk3_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
1552{
1553 struct ewrk3_private *lp = netdev_priv(dev);
1554 unsigned long iobase = dev->base_addr;
1555 unsigned long flags;
1556 u8 cr;
1557
1558 /* DE205 is the only card with anything to set */
1559 if (lp->adapter_name[4] != '5')
1560 return -EOPNOTSUPP;
1561
1562 /* Sanity-check parameters */
1563 if (ecmd->speed != SPEED_10)
1564 return -EINVAL;
1565 if (ecmd->port != PORT_TP && ecmd->port != PORT_BNC)
1566 return -EINVAL; /* AUI is not software-selectable */
1567 if (ecmd->transceiver != XCVR_INTERNAL)
1568 return -EINVAL;
1569 if (ecmd->duplex != DUPLEX_HALF)
1570 return -EINVAL;
1571 if (ecmd->phy_address != 0)
1572 return -EINVAL;
1573
1574 spin_lock_irqsave(&lp->hw_lock, flags);
1575 cr = inb(EWRK3_CR);
1576
1577 /* If Autoneg is set, change to Auto Port mode */
1578 /* Otherwise, disable Auto Port and set port explicitly */
1579 if (ecmd->autoneg) {
1580 cr &= ~CR_APD;
1581 } else {
1582 cr |= CR_APD;
1583 if (ecmd->port == PORT_TP)
1584 cr &= ~CR_PSEL; /* Force TP */
1585 else
1586 cr |= CR_PSEL; /* Force BNC */
1587 }
1588
1589 /* Commit the changes */
1590 outb(cr, EWRK3_CR);
1591 spin_unlock_irqrestore(&lp->hw_lock, flags);
1592 return 0;
1593}
1594
1595static u32 ewrk3_get_link(struct net_device *dev)
1596{
1597 unsigned long iobase = dev->base_addr;
1598 u8 cmr = inb(EWRK3_CMR);
1599 /* DE203 has BNC only and link status does not apply */
1600 /* On DE204 this is always valid since TP is the only port. */
1601 /* On DE205 this reflects TP status even if BNC or AUI is selected. */
1602 return !(cmr & CMR_LINK);
1603}
1604
7b1b3afa 1605static int ewrk3_set_phys_id(struct net_device *dev,
1606 enum ethtool_phys_id_state state)
1da177e4
LT		 1607{
1608 struct ewrk3_private *lp = netdev_priv(dev);
1609 unsigned long iobase = dev->base_addr;
1da177e4 1610 u8 cr;
1da177e4 1611
7b1b3afa 1612 spin_lock_irq(&lp->hw_lock);
1da177e4 1613
7b1b3afa 1614 switch (state) {
1615 case ETHTOOL_ID_ACTIVE:
1616 /* Prevent ISR from twiddling the LED */
1617 lp->led_mask = 0;
1618 spin_unlock_irq(&lp->hw_lock);
fce55922 1619 return 2; /* cycle on/off twice per second */
1da177e4 1620
7b1b3afa 1621 case ETHTOOL_ID_ON:
1da177e4 1622 cr = inb(EWRK3_CR);
7b1b3afa 1623 outb(cr | CR_LED, EWRK3_CR);
1624 break;
1da177e4 1625
7b1b3afa 1626 case ETHTOOL_ID_OFF:
1627 cr = inb(EWRK3_CR);
1628 outb(cr & ~CR_LED, EWRK3_CR);
1629 break;
1da177e4 1630
7b1b3afa 1631 case ETHTOOL_ID_INACTIVE:
1632 lp->led_mask = CR_LED;
1633 cr = inb(EWRK3_CR);
1634 outb(cr & ~CR_LED, EWRK3_CR);
1da177e4 1635 }
7b1b3afa 1636 spin_unlock_irq(&lp->hw_lock);
1da177e4 1637
7b1b3afa 1638 return 0;
1da177e4
LT		 1639}
1640
7282d491 1641static const struct ethtool_ops ethtool_ops_203 = {
1da177e4
LT		 1642 .get_drvinfo = ewrk3_get_drvinfo,
1643 .get_settings = ewrk3_get_settings,
1644 .set_settings = ewrk3_set_settings,
7b1b3afa 1645 .set_phys_id = ewrk3_set_phys_id,
1da177e4
LT		 1646};
1647
7282d491 1648static const struct ethtool_ops ethtool_ops = {
1da177e4
LT		 1649 .get_drvinfo = ewrk3_get_drvinfo,
1650 .get_settings = ewrk3_get_settings,
1651 .set_settings = ewrk3_set_settings,
1652 .get_link = ewrk3_get_link,
7b1b3afa 1653 .set_phys_id = ewrk3_set_phys_id,
1da177e4
LT		 1654};
1655
1656/*
1657 ** Perform IOCTL call functions here. Some are privileged operations and the
1658 ** effective uid is checked in those cases.
1659 */
1660static int ewrk3_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1661{
1662 struct ewrk3_private *lp = netdev_priv(dev);
1663 struct ewrk3_ioctl *ioc = (struct ewrk3_ioctl *) &rq->ifr_ifru;
1664 u_long iobase = dev->base_addr;
1665 int i, j, status = 0;
1666 u_char csr;
1667 unsigned long flags;
1668 union ewrk3_addr {
1669 u_char addr[HASH_TABLE_LEN * ETH_ALEN];
1670 u_short val[(HASH_TABLE_LEN * ETH_ALEN) >> 1];
1671 };
6aa20a22 1672
1da177e4
LT		 1673 union ewrk3_addr *tmp;
1674
1675 /* All we handle are private IOCTLs */
1676 if (cmd != EWRK3IOCTL)
1677 return -EOPNOTSUPP;
1678
1679 tmp = kmalloc(sizeof(union ewrk3_addr), GFP_KERNEL);
1680 if(tmp==NULL)
1681 return -ENOMEM;
1682
1683 switch (ioc->cmd) {
1684 case EWRK3_GET_HWADDR: /* Get the hardware address */
1685 for (i = 0; i < ETH_ALEN; i++) {
1686 tmp->addr[i] = dev->dev_addr[i];
1687 }
1688 ioc->len = ETH_ALEN;
1689 if (copy_to_user(ioc->data, tmp->addr, ioc->len))
1690 status = -EFAULT;
1691 break;
6aa20a22 1692
1da177e4
LT		 1693 case EWRK3_SET_HWADDR: /* Set the hardware address */
1694 if (capable(CAP_NET_ADMIN)) {
1695 spin_lock_irqsave(&lp->hw_lock, flags);
1696 csr = inb(EWRK3_CSR);
1697 csr |= (CSR_TXD | CSR_RXD);
1698 outb(csr, EWRK3_CSR); /* Disable the TX and RX */
1699 spin_unlock_irqrestore(&lp->hw_lock, flags);
1700
1701 if (copy_from_user(tmp->addr, ioc->data, ETH_ALEN)) {
1702 status = -EFAULT;
1703 break;
1704 }
1705 spin_lock_irqsave(&lp->hw_lock, flags);
1706 for (i = 0; i < ETH_ALEN; i++) {
1707 dev->dev_addr[i] = tmp->addr[i];
1708 outb(tmp->addr[i], EWRK3_PAR0 + i);
1709 }
1710
1711 csr = inb(EWRK3_CSR);
1712 csr &= ~(CSR_TXD | CSR_RXD); /* Enable the TX and RX */
1713 outb(csr, EWRK3_CSR);
1714 spin_unlock_irqrestore(&lp->hw_lock, flags);
1715 } else {
1716 status = -EPERM;
1717 }
1718
1719 break;
1720 case EWRK3_SET_PROM: /* Set Promiscuous Mode */
1721 if (capable(CAP_NET_ADMIN)) {
1722 spin_lock_irqsave(&lp->hw_lock, flags);
1723 csr = inb(EWRK3_CSR);
1724 csr |= CSR_PME;
1725 csr &= ~CSR_MCE;
1726 outb(csr, EWRK3_CSR);
1727 spin_unlock_irqrestore(&lp->hw_lock, flags);
1728 } else {
1729 status = -EPERM;
1730 }
1731
1732 break;
1733 case EWRK3_CLR_PROM: /* Clear Promiscuous Mode */
1734 if (capable(CAP_NET_ADMIN)) {
1735 spin_lock_irqsave(&lp->hw_lock, flags);
1736 csr = inb(EWRK3_CSR);
1737 csr &= ~CSR_PME;
1738 outb(csr, EWRK3_CSR);
1739 spin_unlock_irqrestore(&lp->hw_lock, flags);
1740 } else {
1741 status = -EPERM;
1742 }
1743
1744 break;
1745 case EWRK3_GET_MCA: /* Get the multicast address table */
1746 spin_lock_irqsave(&lp->hw_lock, flags);
1747 if (lp->shmem_length == IO_ONLY) {
1748 outb(0, EWRK3_IOPR);
1749 outw(PAGE0_HTE, EWRK3_PIR1);
1750 for (i = 0; i < (HASH_TABLE_LEN >> 3); i++) {
1751 tmp->addr[i] = inb(EWRK3_DATA);
1752 }
1753 } else {
1754 outb(0, EWRK3_MPR);
1755 memcpy_fromio(tmp->addr, lp->shmem + PAGE0_HTE, (HASH_TABLE_LEN >> 3));
1756 }
1757 spin_unlock_irqrestore(&lp->hw_lock, flags);
1758
1759 ioc->len = (HASH_TABLE_LEN >> 3);
1760 if (copy_to_user(ioc->data, tmp->addr, ioc->len))
1761 status = -EFAULT;
1762
1763 break;
1764 case EWRK3_SET_MCA: /* Set a multicast address */
1765 if (capable(CAP_NET_ADMIN)) {
664ffe80 1766 if (ioc->len > HASH_TABLE_LEN) {
1da177e4
LT		 1767 status = -EINVAL;
1768 break;
1769 }
1770 if (copy_from_user(tmp->addr, ioc->data, ETH_ALEN * ioc->len)) {
1771 status = -EFAULT;
1772 break;
1773 }
1774 set_multicast_list(dev);
1775 } else {
1776 status = -EPERM;
1777 }
1778
1779 break;
1780 case EWRK3_CLR_MCA: /* Clear all multicast addresses */
1781 if (capable(CAP_NET_ADMIN)) {
1782 set_multicast_list(dev);
1783 } else {
1784 status = -EPERM;
1785 }
1786
1787 break;
1788 case EWRK3_MCA_EN: /* Enable multicast addressing */
1789 if (capable(CAP_NET_ADMIN)) {
1790 spin_lock_irqsave(&lp->hw_lock, flags);
1791 csr = inb(EWRK3_CSR);
1792 csr |= CSR_MCE;
1793 csr &= ~CSR_PME;
1794 outb(csr, EWRK3_CSR);
1795 spin_unlock_irqrestore(&lp->hw_lock, flags);
1796 } else {
1797 status = -EPERM;
1798 }
1799
1800 break;
1801 case EWRK3_GET_STATS: { /* Get the driver statistics */
1802 struct ewrk3_stats *tmp_stats =
1803 kmalloc(sizeof(lp->pktStats), GFP_KERNEL);
1804 if (!tmp_stats) {
1805 status = -ENOMEM;
1806 break;
1807 }
1808
1809 spin_lock_irqsave(&lp->hw_lock, flags);
1810 memcpy(tmp_stats, &lp->pktStats, sizeof(lp->pktStats));
1811 spin_unlock_irqrestore(&lp->hw_lock, flags);
1812
1813 ioc->len = sizeof(lp->pktStats);
1814 if (copy_to_user(ioc->data, tmp_stats, sizeof(lp->pktStats)))
1815 status = -EFAULT;
1816 kfree(tmp_stats);
1817 break;
1818 }
1819 case EWRK3_CLR_STATS: /* Zero out the driver statistics */
1820 if (capable(CAP_NET_ADMIN)) {
1821 spin_lock_irqsave(&lp->hw_lock, flags);
1822 memset(&lp->pktStats, 0, sizeof(lp->pktStats));
1823 spin_unlock_irqrestore(&lp->hw_lock,flags);
1824 } else {
1825 status = -EPERM;
1826 }
1827
1828 break;
1829 case EWRK3_GET_CSR: /* Get the CSR Register contents */
1830 tmp->addr[0] = inb(EWRK3_CSR);
1831 ioc->len = 1;
1832 if (copy_to_user(ioc->data, tmp->addr, ioc->len))
1833 status = -EFAULT;
1834 break;
1835 case EWRK3_SET_CSR: /* Set the CSR Register contents */
1836 if (capable(CAP_NET_ADMIN)) {
1837 if (copy_from_user(tmp->addr, ioc->data, 1)) {
1838 status = -EFAULT;
1839 break;
1840 }
1841 outb(tmp->addr[0], EWRK3_CSR);
1842 } else {
1843 status = -EPERM;
1844 }
1845
1846 break;
1847 case EWRK3_GET_EEPROM: /* Get the EEPROM contents */
1848 if (capable(CAP_NET_ADMIN)) {
1849 for (i = 0; i < (EEPROM_MAX >> 1); i++) {
1850 tmp->val[i] = (short) Read_EEPROM(iobase, i);
1851 }
1852 i = EEPROM_MAX;
1853 tmp->addr[i++] = inb(EWRK3_CMR); /* Config/Management Reg. */
1854 for (j = 0; j < ETH_ALEN; j++) {
1855 tmp->addr[i++] = inb(EWRK3_PAR0 + j);
1856 }
1857 ioc->len = EEPROM_MAX + 1 + ETH_ALEN;
1858 if (copy_to_user(ioc->data, tmp->addr, ioc->len))
1859 status = -EFAULT;
1860 } else {
1861 status = -EPERM;
1862 }
1863
1864 break;
1865 case EWRK3_SET_EEPROM: /* Set the EEPROM contents */
1866 if (capable(CAP_NET_ADMIN)) {
1867 if (copy_from_user(tmp->addr, ioc->data, EEPROM_MAX)) {
1868 status = -EFAULT;
1869 break;
1870 }
1871 for (i = 0; i < (EEPROM_MAX >> 1); i++) {
1872 Write_EEPROM(tmp->val[i], iobase, i);
1873 }
1874 } else {
1875 status = -EPERM;
1876 }
1877
1878 break;
1879 case EWRK3_GET_CMR: /* Get the CMR Register contents */
1880 tmp->addr[0] = inb(EWRK3_CMR);
1881 ioc->len = 1;
1882 if (copy_to_user(ioc->data, tmp->addr, ioc->len))
1883 status = -EFAULT;
1884 break;
1885 case EWRK3_SET_TX_CUT_THRU: /* Set TX cut through mode */
1886 if (capable(CAP_NET_ADMIN)) {
1887 lp->txc = 1;
1888 } else {
1889 status = -EPERM;
1890 }
1891
1892 break;
1893 case EWRK3_CLR_TX_CUT_THRU: /* Clear TX cut through mode */
1894 if (capable(CAP_NET_ADMIN)) {
1895 lp->txc = 0;
1896 } else {
1897 status = -EPERM;
1898 }
1899
1900 break;
1901 default:
1902 status = -EOPNOTSUPP;
1903 }
1904 kfree(tmp);
1905 return status;
1906}
1907
1908#ifdef MODULE
1909static struct net_device *ewrk3_devs[MAX_NUM_EWRK3S];
1910static int ndevs;
1911static int io[MAX_NUM_EWRK3S+1] = { 0x300, 0, };
1912
1913/* '21' below should really be 'MAX_NUM_EWRK3S' */
1914module_param_array(io, int, NULL, 0);
1915module_param_array(irq, int, NULL, 0);
1916MODULE_PARM_DESC(io, "EtherWORKS 3 I/O base address(es)");
1917MODULE_PARM_DESC(irq, "EtherWORKS 3 IRQ number(s)");
1918
1919static __exit void ewrk3_exit_module(void)
1920{
1921 int i;
1922
1923 for( i=0; i<ndevs; i++ ) {
1924 struct net_device *dev = ewrk3_devs[i];
1925 struct ewrk3_private *lp = netdev_priv(dev);
1926 ewrk3_devs[i] = NULL;
1927 unregister_netdev(dev);
1928 release_region(dev->base_addr, EWRK3_TOTAL_SIZE);
1929 iounmap(lp->shmem);
1930 free_netdev(dev);
1931 }
1932}
1933
1934static __init int ewrk3_init_module(void)
1935{
1936 int i=0;
1937
1938 while( io[i] && irq[i] ) {
1939 struct net_device *dev
1940 = alloc_etherdev(sizeof(struct ewrk3_private));
1941
1942 if (!dev)
1943 break;
1944
1945 if (ewrk3_probe1(dev, io[i], irq[i]) != 0) {
1946 free_netdev(dev);
1947 break;
1948 }
1949
1950 ewrk3_devs[ndevs++] = dev;
1951 i++;
1952 }
1953
1954 return ndevs ? 0 : -EIO;
1955}
1956
1957
1958/* Hack for breakage in new module stuff */
1959module_exit(ewrk3_exit_module);
1960module_init(ewrk3_init_module);
1961#endif /* MODULE */
1962MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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