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net: fs_enet: Add NAPI TX
[deliverable/linux.git] / drivers / net / ethernet / dnet.c
CommitLineData
47964174
IY		 1/*
2 * Dave DNET Ethernet Controller driver
3 *
4 * Copyright (C) 2008 Dave S.r.l. <www.dave.eu>
5 * Copyright (C) 2009 Ilya Yanok, Emcraft Systems Ltd, <yanok@emcraft.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
142071b8 11#include <linux/io.h>
47964174
IY		 12#include <linux/module.h>
13#include <linux/moduleparam.h>
14#include <linux/kernel.h>
15#include <linux/types.h>
16#include <linux/slab.h>
17#include <linux/delay.h>
a6b7a407 18#include <linux/interrupt.h>
47964174
IY		 19#include <linux/netdevice.h>
20#include <linux/etherdevice.h>
21#include <linux/dma-mapping.h>
22#include <linux/platform_device.h>
23#include <linux/phy.h>
47964174
IY		 24
25#include "dnet.h"
26
27#undef DEBUG
28
29/* function for reading internal MAC register */
35f2516f 30static u16 dnet_readw_mac(struct dnet *bp, u16 reg)
47964174
IY		 31{
32 u16 data_read;
33
34 /* issue a read */
35 dnet_writel(bp, reg, MACREG_ADDR);
36
37 /* since a read/write op to the MAC is very slow,
38 * we must wait before reading the data */
39 ndelay(500);
40
41 /* read data read from the MAC register */
42 data_read = dnet_readl(bp, MACREG_DATA);
43
44 /* all done */
45 return data_read;
46}
47
48/* function for writing internal MAC register */
35f2516f 49static void dnet_writew_mac(struct dnet *bp, u16 reg, u16 val)
47964174
IY		 50{
51 /* load data to write */
52 dnet_writel(bp, val, MACREG_DATA);
53
54 /* issue a write */
55 dnet_writel(bp, reg | DNET_INTERNAL_WRITE, MACREG_ADDR);
56
57 /* since a read/write op to the MAC is very slow,
58 * we must wait before exiting */
59 ndelay(500);
60}
61
62static void __dnet_set_hwaddr(struct dnet *bp)
63{
64 u16 tmp;
65
35f2516f 66 tmp = be16_to_cpup((__be16 *)bp->dev->dev_addr);
47964174 67 dnet_writew_mac(bp, DNET_INTERNAL_MAC_ADDR_0_REG, tmp);
35f2516f 68 tmp = be16_to_cpup((__be16 *)(bp->dev->dev_addr + 2));
47964174 69 dnet_writew_mac(bp, DNET_INTERNAL_MAC_ADDR_1_REG, tmp);
35f2516f 70 tmp = be16_to_cpup((__be16 *)(bp->dev->dev_addr + 4));
47964174
IY		 71 dnet_writew_mac(bp, DNET_INTERNAL_MAC_ADDR_2_REG, tmp);
72}
73
a0a4efed 74static void dnet_get_hwaddr(struct dnet *bp)
47964174
IY		 75{
76 u16 tmp;
77 u8 addr[6];
78
79 /*
80 * from MAC docs:
81 * "Note that the MAC address is stored in the registers in Hexadecimal
82 * form. For example, to set the MAC Address to: AC-DE-48-00-00-80
83 * would require writing 0xAC (octet 0) to address 0x0B (high byte of
84 * Mac_addr[15:0]), 0xDE (octet 1) to address 0x0A (Low byte of
85 * Mac_addr[15:0]), 0x48 (octet 2) to address 0x0D (high byte of
86 * Mac_addr[15:0]), 0x00 (octet 3) to address 0x0C (Low byte of
87 * Mac_addr[15:0]), 0x00 (octet 4) to address 0x0F (high byte of
88 * Mac_addr[15:0]), and 0x80 (octet 5) to address * 0x0E (Low byte of
89 * Mac_addr[15:0]).
90 */
91 tmp = dnet_readw_mac(bp, DNET_INTERNAL_MAC_ADDR_0_REG);
35f2516f 92 *((__be16 *)addr) = cpu_to_be16(tmp);
47964174 93 tmp = dnet_readw_mac(bp, DNET_INTERNAL_MAC_ADDR_1_REG);
35f2516f 94 *((__be16 *)(addr + 2)) = cpu_to_be16(tmp);
47964174 95 tmp = dnet_readw_mac(bp, DNET_INTERNAL_MAC_ADDR_2_REG);
35f2516f 96 *((__be16 *)(addr + 4)) = cpu_to_be16(tmp);
47964174
IY		 97
98 if (is_valid_ether_addr(addr))
99 memcpy(bp->dev->dev_addr, addr, sizeof(addr));
100}
101
102static int dnet_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
103{
104 struct dnet *bp = bus->priv;
105 u16 value;
106
107 while (!(dnet_readw_mac(bp, DNET_INTERNAL_GMII_MNG_CTL_REG)
108 & DNET_INTERNAL_GMII_MNG_CMD_FIN))
109 cpu_relax();
110
111 /* only 5 bits allowed for phy-addr and reg_offset */
112 mii_id &= 0x1f;
113 regnum &= 0x1f;
114
115 /* prepare reg_value for a read */
116 value = (mii_id << 8);
117 value |= regnum;
118
119 /* write control word */
120 dnet_writew_mac(bp, DNET_INTERNAL_GMII_MNG_CTL_REG, value);
121
122 /* wait for end of transfer */
123 while (!(dnet_readw_mac(bp, DNET_INTERNAL_GMII_MNG_CTL_REG)
124 & DNET_INTERNAL_GMII_MNG_CMD_FIN))
125 cpu_relax();
126
127 value = dnet_readw_mac(bp, DNET_INTERNAL_GMII_MNG_DAT_REG);
128
129 pr_debug("mdio_read %02x:%02x <- %04x\n", mii_id, regnum, value);
130
131 return value;
132}
133
134static int dnet_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
135 u16 value)
136{
137 struct dnet *bp = bus->priv;
138 u16 tmp;
139
140 pr_debug("mdio_write %02x:%02x <- %04x\n", mii_id, regnum, value);
141
142 while (!(dnet_readw_mac(bp, DNET_INTERNAL_GMII_MNG_CTL_REG)
143 & DNET_INTERNAL_GMII_MNG_CMD_FIN))
144 cpu_relax();
145
146 /* prepare for a write operation */
147 tmp = (1 << 13);
148
149 /* only 5 bits allowed for phy-addr and reg_offset */
150 mii_id &= 0x1f;
151 regnum &= 0x1f;
152
153 /* only 16 bits on data */
154 value &= 0xffff;
155
156 /* prepare reg_value for a write */
157 tmp |= (mii_id << 8);
158 tmp |= regnum;
159
160 /* write data to write first */
161 dnet_writew_mac(bp, DNET_INTERNAL_GMII_MNG_DAT_REG, value);
162
163 /* write control word */
164 dnet_writew_mac(bp, DNET_INTERNAL_GMII_MNG_CTL_REG, tmp);
165
166 while (!(dnet_readw_mac(bp, DNET_INTERNAL_GMII_MNG_CTL_REG)
167 & DNET_INTERNAL_GMII_MNG_CMD_FIN))
168 cpu_relax();
169
170 return 0;
171}
172
47964174
IY		 173static void dnet_handle_link_change(struct net_device *dev)
174{
175 struct dnet *bp = netdev_priv(dev);
176 struct phy_device *phydev = bp->phy_dev;
177 unsigned long flags;
178 u32 mode_reg, ctl_reg;
179
180 int status_change = 0;
181
182 spin_lock_irqsave(&bp->lock, flags);
183
184 mode_reg = dnet_readw_mac(bp, DNET_INTERNAL_MODE_REG);
185 ctl_reg = dnet_readw_mac(bp, DNET_INTERNAL_RXTX_CONTROL_REG);
186
187 if (phydev->link) {
188 if (bp->duplex != phydev->duplex) {
189 if (phydev->duplex)
190 ctl_reg &=
191 ~(DNET_INTERNAL_RXTX_CONTROL_ENABLEHALFDUP);
192 else
193 ctl_reg |=
194 DNET_INTERNAL_RXTX_CONTROL_ENABLEHALFDUP;
195
196 bp->duplex = phydev->duplex;
197 status_change = 1;
198 }
199
200 if (bp->speed != phydev->speed) {
201 status_change = 1;
202 switch (phydev->speed) {
203 case 1000:
204 mode_reg |= DNET_INTERNAL_MODE_GBITEN;
205 break;
206 case 100:
207 case 10:
208 mode_reg &= ~DNET_INTERNAL_MODE_GBITEN;
209 break;
210 default:
211 printk(KERN_WARNING
212 "%s: Ack! Speed (%d) is not "
213 "10/100/1000!\n", dev->name,
214 phydev->speed);
215 break;
216 }
217 bp->speed = phydev->speed;
218 }
219 }
220
221 if (phydev->link != bp->link) {
222 if (phydev->link) {
223 mode_reg |=
224 (DNET_INTERNAL_MODE_RXEN | DNET_INTERNAL_MODE_TXEN);
225 } else {
226 mode_reg &=
227 ~(DNET_INTERNAL_MODE_RXEN |
228 DNET_INTERNAL_MODE_TXEN);
229 bp->speed = 0;
230 bp->duplex = -1;
231 }
232 bp->link = phydev->link;
233
234 status_change = 1;
235 }
236
237 if (status_change) {
238 dnet_writew_mac(bp, DNET_INTERNAL_RXTX_CONTROL_REG, ctl_reg);
239 dnet_writew_mac(bp, DNET_INTERNAL_MODE_REG, mode_reg);
240 }
241
242 spin_unlock_irqrestore(&bp->lock, flags);
243
244 if (status_change) {
245 if (phydev->link)
246 printk(KERN_INFO "%s: link up (%d/%s)\n",
247 dev->name, phydev->speed,
248 DUPLEX_FULL == phydev->duplex ? "Full" : "Half");
249 else
250 printk(KERN_INFO "%s: link down\n", dev->name);
251 }
252}
253
254static int dnet_mii_probe(struct net_device *dev)
255{
256 struct dnet *bp = netdev_priv(dev);
257 struct phy_device *phydev = NULL;
258 int phy_addr;
259
260 /* find the first phy */
261 for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++) {
262 if (bp->mii_bus->phy_map[phy_addr]) {
263 phydev = bp->mii_bus->phy_map[phy_addr];
264 break;
265 }
266 }
267
268 if (!phydev) {
269 printk(KERN_ERR "%s: no PHY found\n", dev->name);
270 return -ENODEV;
271 }
272
273 /* TODO : add pin_irq */
274
275 /* attach the mac to the phy */
276 if (bp->capabilities & DNET_HAS_RMII) {
6580f57d 277 phydev = phy_connect(dev, dev_name(&phydev->dev),
f9a8f83b 278 &dnet_handle_link_change,
47964174
IY		 279 PHY_INTERFACE_MODE_RMII);
280 } else {
6580f57d 281 phydev = phy_connect(dev, dev_name(&phydev->dev),
f9a8f83b 282 &dnet_handle_link_change,
47964174
IY		 283 PHY_INTERFACE_MODE_MII);
284 }
285
286 if (IS_ERR(phydev)) {
287 printk(KERN_ERR "%s: Could not attach to PHY\n", dev->name);
288 return PTR_ERR(phydev);
289 }
290
291 /* mask with MAC supported features */
292 if (bp->capabilities & DNET_HAS_GIGABIT)
293 phydev->supported &= PHY_GBIT_FEATURES;
294 else
295 phydev->supported &= PHY_BASIC_FEATURES;
296
297 phydev->supported |= SUPPORTED_Asym_Pause | SUPPORTED_Pause;
298
299 phydev->advertising = phydev->supported;
300
301 bp->link = 0;
302 bp->speed = 0;
303 bp->duplex = -1;
304 bp->phy_dev = phydev;
305
306 return 0;
307}
308
309static int dnet_mii_init(struct dnet *bp)
310{
311 int err, i;
312
313 bp->mii_bus = mdiobus_alloc();
314 if (bp->mii_bus == NULL)
315 return -ENOMEM;
316
317 bp->mii_bus->name = "dnet_mii_bus";
318 bp->mii_bus->read = &dnet_mdio_read;
319 bp->mii_bus->write = &dnet_mdio_write;
47964174 320
63f67830
FF		 321 snprintf(bp->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
322 bp->pdev->name, bp->pdev->id);
47964174
IY		 323
324 bp->mii_bus->priv = bp;
325
ae29223e
HS		 326 bp->mii_bus->irq = devm_kmalloc(&bp->pdev->dev,
327 sizeof(int) * PHY_MAX_ADDR, GFP_KERNEL);
47964174
IY		 328 if (!bp->mii_bus->irq) {
329 err = -ENOMEM;
330 goto err_out;
331 }
332
333 for (i = 0; i < PHY_MAX_ADDR; i++)
334 bp->mii_bus->irq[i] = PHY_POLL;
335
47964174
IY		 336 if (mdiobus_register(bp->mii_bus)) {
337 err = -ENXIO;
ae29223e 338 goto err_out;
47964174
IY		 339 }
340
341 if (dnet_mii_probe(bp->dev) != 0) {
342 err = -ENXIO;
343 goto err_out_unregister_bus;
344 }
345
346 return 0;
347
348err_out_unregister_bus:
349 mdiobus_unregister(bp->mii_bus);
47964174
IY		 350err_out:
351 mdiobus_free(bp->mii_bus);
352 return err;
353}
354
355/* For Neptune board: LINK1000 as Link LED and TX as activity LED */
35f2516f 356static int dnet_phy_marvell_fixup(struct phy_device *phydev)
47964174
IY		 357{
358 return phy_write(phydev, 0x18, 0x4148);
359}
360
361static void dnet_update_stats(struct dnet *bp)
362{
363 u32 __iomem *reg = bp->regs + DNET_RX_PKT_IGNR_CNT;
364 u32 *p = &bp->hw_stats.rx_pkt_ignr;
365 u32 *end = &bp->hw_stats.rx_byte + 1;
366
367 WARN_ON((unsigned long)(end - p - 1) !=
368 (DNET_RX_BYTE_CNT - DNET_RX_PKT_IGNR_CNT) / 4);
369
370 for (; p < end; p++, reg++)
371 *p += readl(reg);
372
373 reg = bp->regs + DNET_TX_UNICAST_CNT;
374 p = &bp->hw_stats.tx_unicast;
375 end = &bp->hw_stats.tx_byte + 1;
376
377 WARN_ON((unsigned long)(end - p - 1) !=
378 (DNET_TX_BYTE_CNT - DNET_TX_UNICAST_CNT) / 4);
379
380 for (; p < end; p++, reg++)
381 *p += readl(reg);
382}
383
384static int dnet_poll(struct napi_struct *napi, int budget)
385{
386 struct dnet *bp = container_of(napi, struct dnet, napi);
387 struct net_device *dev = bp->dev;
388 int npackets = 0;
389 unsigned int pkt_len;
390 struct sk_buff *skb;
391 unsigned int *data_ptr;
392 u32 int_enable;
393 u32 cmd_word;
394 int i;
395
396 while (npackets < budget) {
397 /*
398 * break out of while loop if there are no more
399 * packets waiting
400 */
401 if (!(dnet_readl(bp, RX_FIFO_WCNT) >> 16)) {
9fae6c3f 402 napi_complete(napi);
47964174
IY		 403 int_enable = dnet_readl(bp, INTR_ENB);
404 int_enable |= DNET_INTR_SRC_RX_CMDFIFOAF;
405 dnet_writel(bp, int_enable, INTR_ENB);
406 return 0;
407 }
408
409 cmd_word = dnet_readl(bp, RX_LEN_FIFO);
410 pkt_len = cmd_word & 0xFFFF;
411
412 if (cmd_word & 0xDF180000)
413 printk(KERN_ERR "%s packet receive error %x\n",
414 __func__, cmd_word);
415
21a4e469 416 skb = netdev_alloc_skb(dev, pkt_len + 5);
47964174
IY		 417 if (skb != NULL) {
418 /* Align IP on 16 byte boundaries */
419 skb_reserve(skb, 2);
420 /*
421 * 'skb_put()' points to the start of sk_buff
422 * data area.
423 */
424 data_ptr = (unsigned int *)skb_put(skb, pkt_len);
425 for (i = 0; i < (pkt_len + 3) >> 2; i++)
426 *data_ptr++ = dnet_readl(bp, RX_DATA_FIFO);
427 skb->protocol = eth_type_trans(skb, dev);
428 netif_receive_skb(skb);
429 npackets++;
430 } else
431 printk(KERN_NOTICE
432 "%s: No memory to allocate a sk_buff of "
433 "size %u.\n", dev->name, pkt_len);
434 }
435
436 budget -= npackets;
437
438 if (npackets < budget) {
439 /* We processed all packets available. Tell NAPI it can
440 * stop polling then re-enable rx interrupts */
9fae6c3f 441 napi_complete(napi);
47964174
IY		 442 int_enable = dnet_readl(bp, INTR_ENB);
443 int_enable |= DNET_INTR_SRC_RX_CMDFIFOAF;
444 dnet_writel(bp, int_enable, INTR_ENB);
445 return 0;
446 }
447
448 /* There are still packets waiting */
449 return 1;
450}
451
452static irqreturn_t dnet_interrupt(int irq, void *dev_id)
453{
454 struct net_device *dev = dev_id;
455 struct dnet *bp = netdev_priv(dev);
456 u32 int_src, int_enable, int_current;
457 unsigned long flags;
458 unsigned int handled = 0;
459
460 spin_lock_irqsave(&bp->lock, flags);
461
462 /* read and clear the DNET irq (clear on read) */
463 int_src = dnet_readl(bp, INTR_SRC);
464 int_enable = dnet_readl(bp, INTR_ENB);
465 int_current = int_src & int_enable;
466
467 /* restart the queue if we had stopped it for TX fifo almost full */
468 if (int_current & DNET_INTR_SRC_TX_FIFOAE) {
469 int_enable = dnet_readl(bp, INTR_ENB);
470 int_enable &= ~DNET_INTR_ENB_TX_FIFOAE;
471 dnet_writel(bp, int_enable, INTR_ENB);
472 netif_wake_queue(dev);
473 handled = 1;
474 }
475
476 /* RX FIFO error checking */
477 if (int_current &
478 (DNET_INTR_SRC_RX_CMDFIFOFF | DNET_INTR_SRC_RX_DATAFIFOFF)) {
479 printk(KERN_ERR "%s: RX fifo error %x, irq %x\n", __func__,
480 dnet_readl(bp, RX_STATUS), int_current);
481 /* we can only flush the RX FIFOs */
482 dnet_writel(bp, DNET_SYS_CTL_RXFIFOFLUSH, SYS_CTL);
483 ndelay(500);
484 dnet_writel(bp, 0, SYS_CTL);
485 handled = 1;
486 }
487
488 /* TX FIFO error checking */
489 if (int_current &
490 (DNET_INTR_SRC_TX_FIFOFULL | DNET_INTR_SRC_TX_DISCFRM)) {
491 printk(KERN_ERR "%s: TX fifo error %x, irq %x\n", __func__,
492 dnet_readl(bp, TX_STATUS), int_current);
493 /* we can only flush the TX FIFOs */
494 dnet_writel(bp, DNET_SYS_CTL_TXFIFOFLUSH, SYS_CTL);
495 ndelay(500);
496 dnet_writel(bp, 0, SYS_CTL);
497 handled = 1;
498 }
499
500 if (int_current & DNET_INTR_SRC_RX_CMDFIFOAF) {
9fae6c3f 501 if (napi_schedule_prep(&bp->napi)) {
47964174
IY		 502 /*
503 * There's no point taking any more interrupts
504 * until we have processed the buffers
505 */
506 /* Disable Rx interrupts and schedule NAPI poll */
507 int_enable = dnet_readl(bp, INTR_ENB);
508 int_enable &= ~DNET_INTR_SRC_RX_CMDFIFOAF;
509 dnet_writel(bp, int_enable, INTR_ENB);
9fae6c3f 510 __napi_schedule(&bp->napi);
47964174
IY		 511 }
512 handled = 1;
513 }
514
515 if (!handled)
516 pr_debug("%s: irq %x remains\n", __func__, int_current);
517
518 spin_unlock_irqrestore(&bp->lock, flags);
519
520 return IRQ_RETVAL(handled);
521}
522
523#ifdef DEBUG
524static inline void dnet_print_skb(struct sk_buff *skb)
525{
526 int k;
527 printk(KERN_DEBUG PFX "data:");
528 for (k = 0; k < skb->len; k++)
529 printk(" %02x", (unsigned int)skb->data[k]);
530 printk("\n");
531}
532#else
533#define dnet_print_skb(skb) do {} while (0)
534#endif
535
61357325 536static netdev_tx_t dnet_start_xmit(struct sk_buff *skb, struct net_device *dev)
47964174
IY		 537{
538
539 struct dnet *bp = netdev_priv(dev);
540 u32 tx_status, irq_enable;
541 unsigned int len, i, tx_cmd, wrsz;
542 unsigned long flags;
543 unsigned int *bufp;
544
545 tx_status = dnet_readl(bp, TX_STATUS);
546
2c5849ea
DM		 547 pr_debug("start_xmit: len %u head %p data %p\n",
548 skb->len, skb->head, skb->data);
47964174
IY		 549 dnet_print_skb(skb);
550
551 /* frame size (words) */
552 len = (skb->len + 3) >> 2;
553
554 spin_lock_irqsave(&bp->lock, flags);
555
556 tx_status = dnet_readl(bp, TX_STATUS);
557
2c5849ea 558 bufp = (unsigned int *)(((unsigned long) skb->data) & ~0x3UL);
47964174 559 wrsz = (u32) skb->len + 3;
2c5849ea 560 wrsz += ((unsigned long) skb->data) & 0x3;
47964174 561 wrsz >>= 2;
2c5849ea 562 tx_cmd = ((((unsigned long)(skb->data)) & 0x03) << 16) | (u32) skb->len;
47964174
IY		 563
564 /* check if there is enough room for the current frame */
565 if (wrsz < (DNET_FIFO_SIZE - dnet_readl(bp, TX_FIFO_WCNT))) {
566 for (i = 0; i < wrsz; i++)
567 dnet_writel(bp, *bufp++, TX_DATA_FIFO);
568
569 /*
570 * inform MAC that a packet's written and ready to be
571 * shipped out
572 */
573 dnet_writel(bp, tx_cmd, TX_LEN_FIFO);
574 }
575
576 if (dnet_readl(bp, TX_FIFO_WCNT) > DNET_FIFO_TX_DATA_AF_TH) {
577 netif_stop_queue(dev);
578 tx_status = dnet_readl(bp, INTR_SRC);
579 irq_enable = dnet_readl(bp, INTR_ENB);
580 irq_enable |= DNET_INTR_ENB_TX_FIFOAE;
581 dnet_writel(bp, irq_enable, INTR_ENB);
582 }
583
ff9b3078
RC		 584 skb_tx_timestamp(skb);
585
47964174
IY		 586 /* free the buffer */
587 dev_kfree_skb(skb);
588
589 spin_unlock_irqrestore(&bp->lock, flags);
590
6ed10654 591 return NETDEV_TX_OK;
47964174
IY		 592}
593
594static void dnet_reset_hw(struct dnet *bp)
595{
596 /* put ts_mac in IDLE state i.e. disable rx/tx */
597 dnet_writew_mac(bp, DNET_INTERNAL_MODE_REG, DNET_INTERNAL_MODE_FCEN);
598
599 /*
600 * RX FIFO almost full threshold: only cmd FIFO almost full is
601 * implemented for RX side
602 */
603 dnet_writel(bp, DNET_FIFO_RX_CMD_AF_TH, RX_FIFO_TH);
604 /*
605 * TX FIFO almost empty threshold: only data FIFO almost empty
606 * is implemented for TX side
607 */
608 dnet_writel(bp, DNET_FIFO_TX_DATA_AE_TH, TX_FIFO_TH);
609
610 /* flush rx/tx fifos */
611 dnet_writel(bp, DNET_SYS_CTL_RXFIFOFLUSH | DNET_SYS_CTL_TXFIFOFLUSH,
612 SYS_CTL);
613 msleep(1);
614 dnet_writel(bp, 0, SYS_CTL);
615}
616
617static void dnet_init_hw(struct dnet *bp)
618{
619 u32 config;
620
621 dnet_reset_hw(bp);
622 __dnet_set_hwaddr(bp);
623
624 config = dnet_readw_mac(bp, DNET_INTERNAL_RXTX_CONTROL_REG);
625
626 if (bp->dev->flags & IFF_PROMISC)
627 /* Copy All Frames */
628 config |= DNET_INTERNAL_RXTX_CONTROL_ENPROMISC;
629 if (!(bp->dev->flags & IFF_BROADCAST))
630 /* No BroadCast */
631 config |= DNET_INTERNAL_RXTX_CONTROL_RXMULTICAST;
632
633 config |= DNET_INTERNAL_RXTX_CONTROL_RXPAUSE |
634 DNET_INTERNAL_RXTX_CONTROL_RXBROADCAST |
635 DNET_INTERNAL_RXTX_CONTROL_DROPCONTROL |
636 DNET_INTERNAL_RXTX_CONTROL_DISCFXFCS;
637
638 dnet_writew_mac(bp, DNET_INTERNAL_RXTX_CONTROL_REG, config);
639
640 /* clear irq before enabling them */
641 config = dnet_readl(bp, INTR_SRC);
642
643 /* enable RX/TX interrupt, recv packet ready interrupt */
644 dnet_writel(bp, DNET_INTR_ENB_GLOBAL_ENABLE | DNET_INTR_ENB_RX_SUMMARY |
645 DNET_INTR_ENB_TX_SUMMARY | DNET_INTR_ENB_RX_FIFOERR |
646 DNET_INTR_ENB_RX_ERROR | DNET_INTR_ENB_RX_FIFOFULL |
647 DNET_INTR_ENB_TX_FIFOFULL | DNET_INTR_ENB_TX_DISCFRM |
648 DNET_INTR_ENB_RX_PKTRDY, INTR_ENB);
649}
650
651static int dnet_open(struct net_device *dev)
652{
653 struct dnet *bp = netdev_priv(dev);
654
655 /* if the phy is not yet register, retry later */
656 if (!bp->phy_dev)
657 return -EAGAIN;
658
47964174
IY		 659 napi_enable(&bp->napi);
660 dnet_init_hw(bp);
661
662 phy_start_aneg(bp->phy_dev);
663
664 /* schedule a link state check */
665 phy_start(bp->phy_dev);
666
667 netif_start_queue(dev);
668
669 return 0;
670}
671
672static int dnet_close(struct net_device *dev)
673{
674 struct dnet *bp = netdev_priv(dev);
675
676 netif_stop_queue(dev);
677 napi_disable(&bp->napi);
678
679 if (bp->phy_dev)
680 phy_stop(bp->phy_dev);
681
682 dnet_reset_hw(bp);
683 netif_carrier_off(dev);
684
685 return 0;
686}
687
688static inline void dnet_print_pretty_hwstats(struct dnet_stats *hwstat)
689{
690 pr_debug("%s\n", __func__);
691 pr_debug("----------------------------- RX statistics "
692 "-------------------------------\n");
693 pr_debug("RX_PKT_IGNR_CNT %-8x\n", hwstat->rx_pkt_ignr);
694 pr_debug("RX_LEN_CHK_ERR_CNT %-8x\n", hwstat->rx_len_chk_err);
695 pr_debug("RX_LNG_FRM_CNT %-8x\n", hwstat->rx_lng_frm);
696 pr_debug("RX_SHRT_FRM_CNT %-8x\n", hwstat->rx_shrt_frm);
697 pr_debug("RX_IPG_VIOL_CNT %-8x\n", hwstat->rx_ipg_viol);
698 pr_debug("RX_CRC_ERR_CNT %-8x\n", hwstat->rx_crc_err);
699 pr_debug("RX_OK_PKT_CNT %-8x\n", hwstat->rx_ok_pkt);
700 pr_debug("RX_CTL_FRM_CNT %-8x\n", hwstat->rx_ctl_frm);
701 pr_debug("RX_PAUSE_FRM_CNT %-8x\n", hwstat->rx_pause_frm);
702 pr_debug("RX_MULTICAST_CNT %-8x\n", hwstat->rx_multicast);
703 pr_debug("RX_BROADCAST_CNT %-8x\n", hwstat->rx_broadcast);
704 pr_debug("RX_VLAN_TAG_CNT %-8x\n", hwstat->rx_vlan_tag);
705 pr_debug("RX_PRE_SHRINK_CNT %-8x\n", hwstat->rx_pre_shrink);
706 pr_debug("RX_DRIB_NIB_CNT %-8x\n", hwstat->rx_drib_nib);
707 pr_debug("RX_UNSUP_OPCD_CNT %-8x\n", hwstat->rx_unsup_opcd);
708 pr_debug("RX_BYTE_CNT %-8x\n", hwstat->rx_byte);
709 pr_debug("----------------------------- TX statistics "
710 "-------------------------------\n");
711 pr_debug("TX_UNICAST_CNT %-8x\n", hwstat->tx_unicast);
712 pr_debug("TX_PAUSE_FRM_CNT %-8x\n", hwstat->tx_pause_frm);
713 pr_debug("TX_MULTICAST_CNT %-8x\n", hwstat->tx_multicast);
714 pr_debug("TX_BRDCAST_CNT %-8x\n", hwstat->tx_brdcast);
715 pr_debug("TX_VLAN_TAG_CNT %-8x\n", hwstat->tx_vlan_tag);
716 pr_debug("TX_BAD_FCS_CNT %-8x\n", hwstat->tx_bad_fcs);
717 pr_debug("TX_JUMBO_CNT %-8x\n", hwstat->tx_jumbo);
718 pr_debug("TX_BYTE_CNT %-8x\n", hwstat->tx_byte);
719}
720
721static struct net_device_stats *dnet_get_stats(struct net_device *dev)
722{
723
724 struct dnet *bp = netdev_priv(dev);
725 struct net_device_stats *nstat = &dev->stats;
726 struct dnet_stats *hwstat = &bp->hw_stats;
727
728 /* read stats from hardware */
729 dnet_update_stats(bp);
730
731 /* Convert HW stats into netdevice stats */
732 nstat->rx_errors = (hwstat->rx_len_chk_err +
733 hwstat->rx_lng_frm + hwstat->rx_shrt_frm +
734 /* ignore IGP violation error
735 hwstat->rx_ipg_viol + */
736 hwstat->rx_crc_err +
737 hwstat->rx_pre_shrink +
738 hwstat->rx_drib_nib + hwstat->rx_unsup_opcd);
739 nstat->tx_errors = hwstat->tx_bad_fcs;
740 nstat->rx_length_errors = (hwstat->rx_len_chk_err +
741 hwstat->rx_lng_frm +
742 hwstat->rx_shrt_frm + hwstat->rx_pre_shrink);
743 nstat->rx_crc_errors = hwstat->rx_crc_err;
744 nstat->rx_frame_errors = hwstat->rx_pre_shrink + hwstat->rx_drib_nib;
745 nstat->rx_packets = hwstat->rx_ok_pkt;
746 nstat->tx_packets = (hwstat->tx_unicast +
747 hwstat->tx_multicast + hwstat->tx_brdcast);
748 nstat->rx_bytes = hwstat->rx_byte;
749 nstat->tx_bytes = hwstat->tx_byte;
750 nstat->multicast = hwstat->rx_multicast;
751 nstat->rx_missed_errors = hwstat->rx_pkt_ignr;
752
753 dnet_print_pretty_hwstats(hwstat);
754
755 return nstat;
756}
757
758static int dnet_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
759{
760 struct dnet *bp = netdev_priv(dev);
761 struct phy_device *phydev = bp->phy_dev;
762
763 if (!phydev)
764 return -ENODEV;
765
766 return phy_ethtool_gset(phydev, cmd);
767}
768
769static int dnet_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
770{
771 struct dnet *bp = netdev_priv(dev);
772 struct phy_device *phydev = bp->phy_dev;
773
774 if (!phydev)
775 return -ENODEV;
776
777 return phy_ethtool_sset(phydev, cmd);
778}
779
780static int dnet_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
781{
782 struct dnet *bp = netdev_priv(dev);
783 struct phy_device *phydev = bp->phy_dev;
784
785 if (!netif_running(dev))
786 return -EINVAL;
787
788 if (!phydev)
789 return -ENODEV;
790
28b04113 791 return phy_mii_ioctl(phydev, rq, cmd);
47964174
IY		 792}
793
794static void dnet_get_drvinfo(struct net_device *dev,
795 struct ethtool_drvinfo *info)
796{
68aad78c
RJ		 797 strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
798 strlcpy(info->version, DRV_VERSION, sizeof(info->version));
799 strlcpy(info->bus_info, "0", sizeof(info->bus_info));
47964174
IY		 800}
801
802static const struct ethtool_ops dnet_ethtool_ops = {
803 .get_settings = dnet_get_settings,
804 .set_settings = dnet_set_settings,
805 .get_drvinfo = dnet_get_drvinfo,
806 .get_link = ethtool_op_get_link,
eb774cbe 807 .get_ts_info = ethtool_op_get_ts_info,
47964174
IY		 808};
809
810static const struct net_device_ops dnet_netdev_ops = {
811 .ndo_open = dnet_open,
812 .ndo_stop = dnet_close,
813 .ndo_get_stats = dnet_get_stats,
814 .ndo_start_xmit = dnet_start_xmit,
815 .ndo_do_ioctl = dnet_ioctl,
816 .ndo_set_mac_address = eth_mac_addr,
817 .ndo_validate_addr = eth_validate_addr,
818 .ndo_change_mtu = eth_change_mtu,
819};
820
a0a4efed 821static int dnet_probe(struct platform_device *pdev)
47964174
IY		 822{
823 struct resource *res;
824 struct net_device *dev;
825 struct dnet *bp;
826 struct phy_device *phydev;
ae29223e
HS		 827 int err;
828 unsigned int irq;
47964174 829
47964174
IY		 830 irq = platform_get_irq(pdev, 0);
831
47964174 832 dev = alloc_etherdev(sizeof(*bp));
41de8d4c 833 if (!dev)
ae29223e 834 return -ENOMEM;
47964174
IY		 835
836 /* TODO: Actually, we have some interesting features... */
837 dev->features |= 0;
838
839 bp = netdev_priv(dev);
840 bp->dev = dev;
841
b093dd96 842 platform_set_drvdata(pdev, dev);
47964174
IY		 843 SET_NETDEV_DEV(dev, &pdev->dev);
844
845 spin_lock_init(&bp->lock);
846
ae29223e
HS		 847 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
848 bp->regs = devm_ioremap_resource(&pdev->dev, res);
849 if (IS_ERR(bp->regs)) {
850 err = PTR_ERR(bp->regs);
47964174
IY		 851 goto err_out_free_dev;
852 }
853
854 dev->irq = irq;
855 err = request_irq(dev->irq, dnet_interrupt, 0, DRV_NAME, dev);
856 if (err) {
857 dev_err(&pdev->dev, "Unable to request IRQ %d (error %d)\n",
858 irq, err);
ae29223e 859 goto err_out_free_dev;
47964174
IY		 860 }
861
862 dev->netdev_ops = &dnet_netdev_ops;
863 netif_napi_add(dev, &bp->napi, dnet_poll, 64);
864 dev->ethtool_ops = &dnet_ethtool_ops;
865
866 dev->base_addr = (unsigned long)bp->regs;
867
868 bp->capabilities = dnet_readl(bp, VERCAPS) & DNET_CAPS_MASK;
869
870 dnet_get_hwaddr(bp);
871
872 if (!is_valid_ether_addr(dev->dev_addr)) {
873 /* choose a random ethernet address */
f2cedb63 874 eth_hw_addr_random(dev);
47964174
IY		 875 __dnet_set_hwaddr(bp);
876 }
877
878 err = register_netdev(dev);
879 if (err) {
880 dev_err(&pdev->dev, "Cannot register net device, aborting.\n");
881 goto err_out_free_irq;
882 }
883
884 /* register the PHY board fixup (for Marvell 88E1111) */
885 err = phy_register_fixup_for_uid(0x01410cc0, 0xfffffff0,
886 dnet_phy_marvell_fixup);
887 /* we can live without it, so just issue a warning */
888 if (err)
889 dev_warn(&pdev->dev, "Cannot register PHY board fixup.\n");
890
de140b0d
DC		 891 err = dnet_mii_init(bp);
892 if (err)
47964174
IY		 893 goto err_out_unregister_netdev;
894
895 dev_info(&pdev->dev, "Dave DNET at 0x%p (0x%08x) irq %d %pM\n",
ae29223e 896 bp->regs, (unsigned int)res->start, dev->irq, dev->dev_addr);
2381a55c 897 dev_info(&pdev->dev, "has %smdio, %sirq, %sgigabit, %sdma\n",
47964174
IY		 898 (bp->capabilities & DNET_HAS_MDIO) ? "" : "no ",
899 (bp->capabilities & DNET_HAS_IRQ) ? "" : "no ",
900 (bp->capabilities & DNET_HAS_GIGABIT) ? "" : "no ",
901 (bp->capabilities & DNET_HAS_DMA) ? "" : "no ");
902 phydev = bp->phy_dev;
903 dev_info(&pdev->dev, "attached PHY driver [%s] "
904 "(mii_bus:phy_addr=%s, irq=%d)\n",
6580f57d 905 phydev->drv->name, dev_name(&phydev->dev), phydev->irq);
47964174
IY		 906
907 return 0;
908
909err_out_unregister_netdev:
910 unregister_netdev(dev);
911err_out_free_irq:
912 free_irq(dev->irq, dev);
47964174
IY		 913err_out_free_dev:
914 free_netdev(dev);
47964174
IY		 915 return err;
916}
917
a0a4efed 918static int dnet_remove(struct platform_device *pdev)
47964174
IY		 919{
920
921 struct net_device *dev;
922 struct dnet *bp;
923
924 dev = platform_get_drvdata(pdev);
925
926 if (dev) {
927 bp = netdev_priv(dev);
928 if (bp->phy_dev)
929 phy_disconnect(bp->phy_dev);
930 mdiobus_unregister(bp->mii_bus);
47964174
IY		 931 mdiobus_free(bp->mii_bus);
932 unregister_netdev(dev);
933 free_irq(dev->irq, dev);
47964174
IY		 934 free_netdev(dev);
935 }
936
937 return 0;
938}
939
940static struct platform_driver dnet_driver = {
941 .probe = dnet_probe,
a0a4efed 942 .remove = dnet_remove,
47964174
IY		 943 .driver = {
944 .name = "dnet",
945 },
946};
947
db62f684 948module_platform_driver(dnet_driver);
47964174
IY		 949
950MODULE_LICENSE("GPL");
951MODULE_DESCRIPTION("Dave DNET Ethernet driver");
952MODULE_AUTHOR("Ilya Yanok <yanok@emcraft.com>, "
953 "Matteo Vit <matteo.vit@dave.eu>");
Linux kernel - Deliverables
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