be2net: Export board temperature using hwmon-sysfs interface.
[deliverable/linux.git] / drivers / net / ethernet / emulex / benet / be.h
CommitLineData
6b7c5b94 1/*
d19261b8 2 * Copyright (C) 2005 - 2015 Emulex
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3 * All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License version 2
7 * as published by the Free Software Foundation. The full GNU General
8 * Public License is included in this distribution in the file called COPYING.
9 *
10 * Contact Information:
d2145cde 11 * linux-drivers@emulex.com
6b7c5b94 12 *
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13 * Emulex
14 * 3333 Susan Street
15 * Costa Mesa, CA 92626
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16 */
17
18#ifndef BE_H
19#define BE_H
20
21#include <linux/pci.h>
22#include <linux/etherdevice.h>
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23#include <linux/delay.h>
24#include <net/tcp.h>
25#include <net/ip.h>
26#include <net/ipv6.h>
27#include <linux/if_vlan.h>
28#include <linux/workqueue.h>
29#include <linux/interrupt.h>
84517482 30#include <linux/firmware.h>
5a0e3ad6 31#include <linux/slab.h>
ab1594e9 32#include <linux/u64_stats_sync.h>
d658d98a 33#include <linux/cpumask.h>
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34#include <linux/hwmon.h>
35#include <linux/hwmon-sysfs.h>
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36
37#include "be_hw.h"
045508a8 38#include "be_roce.h"
6b7c5b94 39
029e9330 40#define DRV_VER "10.6.0.2"
6b7c5b94 41#define DRV_NAME "be2net"
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42#define BE_NAME "Emulex BladeEngine2"
43#define BE3_NAME "Emulex BladeEngine3"
44#define OC_NAME "Emulex OneConnect"
fe6d2a38
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45#define OC_NAME_BE OC_NAME "(be3)"
46#define OC_NAME_LANCER OC_NAME "(Lancer)"
ecedb6ae 47#define OC_NAME_SH OC_NAME "(Skyhawk)"
f3effb45 48#define DRV_DESC "Emulex OneConnect NIC Driver"
6b7c5b94 49
c4ca2374 50#define BE_VENDOR_ID 0x19a2
fe6d2a38 51#define EMULEX_VENDOR_ID 0x10df
c4ca2374 52#define BE_DEVICE_ID1 0x211
12d7ea2c 53#define BE_DEVICE_ID2 0x221
fe6d2a38
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54#define OC_DEVICE_ID1 0x700 /* Device Id for BE2 cards */
55#define OC_DEVICE_ID2 0x710 /* Device Id for BE3 cards */
56#define OC_DEVICE_ID3 0xe220 /* Device id for Lancer cards */
12f4d0a8 57#define OC_DEVICE_ID4 0xe228 /* Device id for VF in Lancer */
ecedb6ae 58#define OC_DEVICE_ID5 0x720 /* Device Id for Skyhawk cards */
76b73530 59#define OC_DEVICE_ID6 0x728 /* Device id for VF in SkyHawk */
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60#define OC_SUBSYS_DEVICE_ID1 0xE602
61#define OC_SUBSYS_DEVICE_ID2 0xE642
62#define OC_SUBSYS_DEVICE_ID3 0xE612
63#define OC_SUBSYS_DEVICE_ID4 0xE652
c4ca2374 64
6b7c5b94 65/* Number of bytes of an RX frame that are copied to skb->data */
2e588f84 66#define BE_HDR_LEN ((u16) 64)
bb349bb4
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67/* allocate extra space to allow tunneling decapsulation without head reallocation */
68#define BE_RX_SKB_ALLOC_SIZE (BE_HDR_LEN + 64)
69
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70#define BE_MAX_JUMBO_FRAME_SIZE 9018
71#define BE_MIN_MTU 256
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72#define BE_MAX_MTU (BE_MAX_JUMBO_FRAME_SIZE - \
73 (ETH_HLEN + ETH_FCS_LEN))
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74
75#define BE_NUM_VLANS_SUPPORTED 64
2632bafd 76#define BE_MAX_EQD 128u
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77#define BE_MAX_TX_FRAG_COUNT 30
78
79#define EVNT_Q_LEN 1024
80#define TX_Q_LEN 2048
81#define TX_CQ_LEN 1024
82#define RX_Q_LEN 1024 /* Does not support any other value */
83#define RX_CQ_LEN 1024
5fb379ee 84#define MCC_Q_LEN 128 /* total size not to exceed 8 pages */
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85#define MCC_CQ_LEN 256
86
10ef9ab4 87#define BE2_MAX_RSS_QS 4
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88#define BE3_MAX_RSS_QS 16
89#define BE3_MAX_TX_QS 16
90#define BE3_MAX_EVT_QS 16
e3dc867c 91#define BE3_SRIOV_MAX_EVT_QS 8
68d7bdcb 92
f2858738 93#define MAX_RSS_IFACES 15
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94#define MAX_RX_QS 32
95#define MAX_EVT_QS 32
96#define MAX_TX_QS 32
10ef9ab4 97
045508a8 98#define MAX_ROCE_EQS 5
68d7bdcb 99#define MAX_MSIX_VECTORS 32
92bf14ab 100#define MIN_MSIX_VECTORS 1
6b7c5b94 101#define BE_NAPI_WEIGHT 64
10ef9ab4 102#define MAX_RX_POST BE_NAPI_WEIGHT /* Frags posted at a time */
6b7c5b94 103#define RX_FRAGS_REFILL_WM (RX_Q_LEN - MAX_RX_POST)
69304cc9 104#define MAX_NUM_POST_ERX_DB 255u
6b7c5b94 105
7c5a5242 106#define MAX_VFS 30 /* Max VFs supported by BE3 FW */
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107#define FW_VER_LEN 32
108
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109#define RSS_INDIR_TABLE_LEN 128
110#define RSS_HASH_KEY_LEN 40
111
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112struct be_dma_mem {
113 void *va;
114 dma_addr_t dma;
115 u32 size;
116};
117
118struct be_queue_info {
119 struct be_dma_mem dma_mem;
120 u16 len;
121 u16 entry_size; /* Size of an element in the queue */
122 u16 id;
123 u16 tail, head;
124 bool created;
125 atomic_t used; /* Number of valid elements in the queue */
126};
127
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128static inline u32 MODULO(u16 val, u16 limit)
129{
130 BUG_ON(limit & (limit - 1));
131 return val & (limit - 1);
132}
133
134static inline void index_adv(u16 *index, u16 val, u16 limit)
135{
136 *index = MODULO((*index + val), limit);
137}
138
139static inline void index_inc(u16 *index, u16 limit)
140{
141 *index = MODULO((*index + 1), limit);
142}
143
144static inline void *queue_head_node(struct be_queue_info *q)
145{
146 return q->dma_mem.va + q->head * q->entry_size;
147}
148
149static inline void *queue_tail_node(struct be_queue_info *q)
150{
151 return q->dma_mem.va + q->tail * q->entry_size;
152}
153
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154static inline void *queue_index_node(struct be_queue_info *q, u16 index)
155{
156 return q->dma_mem.va + index * q->entry_size;
157}
158
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159static inline void queue_head_inc(struct be_queue_info *q)
160{
161 index_inc(&q->head, q->len);
162}
163
652bf646
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164static inline void index_dec(u16 *index, u16 limit)
165{
166 *index = MODULO((*index - 1), limit);
167}
168
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169static inline void queue_tail_inc(struct be_queue_info *q)
170{
171 index_inc(&q->tail, q->len);
172}
173
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174struct be_eq_obj {
175 struct be_queue_info q;
176 char desc[32];
177
178 /* Adaptive interrupt coalescing (AIC) info */
179 bool enable_aic;
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180 u32 min_eqd; /* in usecs */
181 u32 max_eqd; /* in usecs */
182 u32 eqd; /* configured val when aic is off */
183 u32 cur_eqd; /* in usecs */
5fb379ee 184
10ef9ab4 185 u8 idx; /* array index */
f2f781a7 186 u8 msix_idx;
d0b9cec3 187 u16 spurious_intr;
5fb379ee 188 struct napi_struct napi;
10ef9ab4 189 struct be_adapter *adapter;
d658d98a 190 cpumask_var_t affinity_mask;
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191
192#ifdef CONFIG_NET_RX_BUSY_POLL
193#define BE_EQ_IDLE 0
194#define BE_EQ_NAPI 1 /* napi owns this EQ */
195#define BE_EQ_POLL 2 /* poll owns this EQ */
196#define BE_EQ_LOCKED (BE_EQ_NAPI | BE_EQ_POLL)
197#define BE_EQ_NAPI_YIELD 4 /* napi yielded this EQ */
198#define BE_EQ_POLL_YIELD 8 /* poll yielded this EQ */
199#define BE_EQ_YIELD (BE_EQ_NAPI_YIELD | BE_EQ_POLL_YIELD)
200#define BE_EQ_USER_PEND (BE_EQ_POLL | BE_EQ_POLL_YIELD)
201 unsigned int state;
202 spinlock_t lock; /* lock to serialize napi and busy-poll */
203#endif /* CONFIG_NET_RX_BUSY_POLL */
10ef9ab4 204} ____cacheline_aligned_in_smp;
5fb379ee 205
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206struct be_aic_obj { /* Adaptive interrupt coalescing (AIC) info */
207 bool enable;
208 u32 min_eqd; /* in usecs */
209 u32 max_eqd; /* in usecs */
210 u32 prev_eqd; /* in usecs */
211 u32 et_eqd; /* configured val when aic is off */
212 ulong jiffies;
213 u64 rx_pkts_prev; /* Used to calculate RX pps */
214 u64 tx_reqs_prev; /* Used to calculate TX pps */
215};
216
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217enum {
218 NAPI_POLLING,
219 BUSY_POLLING
220};
221
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222struct be_mcc_obj {
223 struct be_queue_info q;
224 struct be_queue_info cq;
7a1e9b20 225 bool rearm_cq;
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226};
227
3abcdeda 228struct be_tx_stats {
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229 u64 tx_bytes;
230 u64 tx_pkts;
231 u64 tx_reqs;
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232 u64 tx_compl;
233 ulong tx_jiffies;
234 u32 tx_stops;
bc617526 235 u32 tx_drv_drops; /* pkts dropped by driver */
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236 /* the error counters are described in be_ethtool.c */
237 u32 tx_hdr_parse_err;
238 u32 tx_dma_err;
239 u32 tx_tso_err;
240 u32 tx_spoof_check_err;
241 u32 tx_qinq_err;
242 u32 tx_internal_parity_err;
ab1594e9
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243 struct u64_stats_sync sync;
244 struct u64_stats_sync sync_compl;
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245};
246
152ffe5b
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247/* Structure to hold some data of interest obtained from a TX CQE */
248struct be_tx_compl_info {
249 u8 status; /* Completion status */
250 u16 end_index; /* Completed TXQ Index */
251};
252
6b7c5b94 253struct be_tx_obj {
94d73aaa 254 u32 db_offset;
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255 struct be_queue_info q;
256 struct be_queue_info cq;
152ffe5b 257 struct be_tx_compl_info txcp;
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258 /* Remember the skbs that were transmitted */
259 struct sk_buff *sent_skb_list[TX_Q_LEN];
3c8def97 260 struct be_tx_stats stats;
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261 u16 pend_wrb_cnt; /* Number of WRBs yet to be given to HW */
262 u16 last_req_wrb_cnt; /* wrb cnt of the last req in the Q */
263 u16 last_req_hdr; /* index of the last req's hdr-wrb */
10ef9ab4 264} ____cacheline_aligned_in_smp;
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265
266/* Struct to remember the pages posted for rx frags */
267struct be_rx_page_info {
268 struct page *page;
e50287be 269 /* set to page-addr for last frag of the page & frag-addr otherwise */
fac6da5b 270 DEFINE_DMA_UNMAP_ADDR(bus);
6b7c5b94 271 u16 page_offset;
e50287be 272 bool last_frag; /* last frag of the page */
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273};
274
3abcdeda 275struct be_rx_stats {
3abcdeda 276 u64 rx_bytes;
3abcdeda 277 u64 rx_pkts;
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278 u32 rx_drops_no_skbs; /* skb allocation errors */
279 u32 rx_drops_no_frags; /* HW has no fetched frags */
280 u32 rx_post_fail; /* page post alloc failures */
ac124ff9 281 u32 rx_compl;
3abcdeda 282 u32 rx_mcast_pkts;
ac124ff9 283 u32 rx_compl_err; /* completions with err set */
ab1594e9 284 struct u64_stats_sync sync;
3abcdeda
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285};
286
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287struct be_rx_compl_info {
288 u32 rss_hash;
6709d952 289 u16 vlan_tag;
2e588f84 290 u16 pkt_size;
12004ae9 291 u16 port;
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292 u8 vlanf;
293 u8 num_rcvd;
294 u8 err;
295 u8 ipf;
296 u8 tcpf;
297 u8 udpf;
298 u8 ip_csum;
299 u8 l4_csum;
300 u8 ipv6;
f93f160b 301 u8 qnq;
2e588f84 302 u8 pkt_type;
e38b1706 303 u8 ip_frag;
c9c47142 304 u8 tunneled;
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305};
306
6b7c5b94 307struct be_rx_obj {
3abcdeda 308 struct be_adapter *adapter;
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309 struct be_queue_info q;
310 struct be_queue_info cq;
2e588f84 311 struct be_rx_compl_info rxcp;
6b7c5b94 312 struct be_rx_page_info page_info_tbl[RX_Q_LEN];
3abcdeda
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313 struct be_rx_stats stats;
314 u8 rss_id;
315 bool rx_post_starved; /* Zero rx frags have been posted to BE */
10ef9ab4 316} ____cacheline_aligned_in_smp;
6b7c5b94 317
609ff3bb 318struct be_drv_stats {
ac124ff9 319 u32 eth_red_drops;
d3de1540 320 u32 dma_map_errors;
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321 u32 rx_drops_no_pbuf;
322 u32 rx_drops_no_txpb;
323 u32 rx_drops_no_erx_descr;
324 u32 rx_drops_no_tpre_descr;
325 u32 rx_drops_too_many_frags;
ac124ff9
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326 u32 forwarded_packets;
327 u32 rx_drops_mtu;
328 u32 rx_crc_errors;
329 u32 rx_alignment_symbol_errors;
330 u32 rx_pause_frames;
331 u32 rx_priority_pause_frames;
332 u32 rx_control_frames;
333 u32 rx_in_range_errors;
334 u32 rx_out_range_errors;
335 u32 rx_frame_too_long;
18fb06a1 336 u32 rx_address_filtered;
ac124ff9
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337 u32 rx_dropped_too_small;
338 u32 rx_dropped_too_short;
339 u32 rx_dropped_header_too_small;
340 u32 rx_dropped_tcp_length;
341 u32 rx_dropped_runt;
342 u32 rx_ip_checksum_errs;
343 u32 rx_tcp_checksum_errs;
344 u32 rx_udp_checksum_errs;
345 u32 tx_pauseframes;
346 u32 tx_priority_pauseframes;
347 u32 tx_controlframes;
348 u32 rxpp_fifo_overflow_drop;
349 u32 rx_input_fifo_overflow_drop;
350 u32 pmem_fifo_overflow_drop;
351 u32 jabber_events;
461ae379
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352 u32 rx_roce_bytes_lsd;
353 u32 rx_roce_bytes_msd;
354 u32 rx_roce_frames;
355 u32 roce_drops_payload_len;
356 u32 roce_drops_crc;
609ff3bb
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357};
358
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359/* A vlan-id of 0xFFFF must be used to clear transparent vlan-tagging */
360#define BE_RESET_VLAN_TAG_ID 0xFFFF
361
64600ea5 362struct be_vf_cfg {
11ac75ed
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363 unsigned char mac_addr[ETH_ALEN];
364 int if_handle;
365 int pmac_id;
366 u16 vlan_tag;
367 u32 tx_rate;
bdce2ad7 368 u32 plink_tracking;
435452aa 369 u32 privileges;
e7bcbd7b 370 bool spoofchk;
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371};
372
39f1d94d
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373enum vf_state {
374 ENABLED = 0,
375 ASSIGNED = 1
376};
377
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378#define BE_FLAGS_LINK_STATUS_INIT BIT(1)
379#define BE_FLAGS_SRIOV_ENABLED BIT(2)
380#define BE_FLAGS_WORKER_SCHEDULED BIT(3)
83b06116
VV
381#define BE_FLAGS_NAPI_ENABLED BIT(6)
382#define BE_FLAGS_QNQ_ASYNC_EVT_RCVD BIT(7)
383#define BE_FLAGS_VXLAN_OFFLOADS BIT(8)
384#define BE_FLAGS_SETUP_DONE BIT(9)
21252377 385#define BE_FLAGS_EVT_INCOMPATIBLE_SFP BIT(10)
eb7dd46c 386#define BE_FLAGS_ERR_DETECTION_SCHEDULED BIT(11)
b236916a 387
c9c47142
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388#define BE_UC_PMAC_COUNT 30
389#define BE_VF_UC_PMAC_COUNT 2
f0613380 390
5c510811
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391/* Ethtool set_dump flags */
392#define LANCER_INITIATE_FW_DUMP 0x1
f0613380 393#define LANCER_DELETE_FW_DUMP 0x2
5c510811 394
42f11cf2 395struct phy_info {
21252377
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396/* From SFF-8472 spec */
397#define SFP_VENDOR_NAME_LEN 17
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398 u8 transceiver;
399 u8 autoneg;
400 u8 fc_autoneg;
401 u8 port_type;
402 u16 phy_type;
403 u16 interface_type;
404 u32 misc_params;
405 u16 auto_speeds_supported;
406 u16 fixed_speeds_supported;
407 int link_speed;
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408 u32 advertising;
409 u32 supported;
6809cee0 410 u8 cable_type;
21252377
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411 u8 vendor_name[SFP_VENDOR_NAME_LEN];
412 u8 vendor_pn[SFP_VENDOR_NAME_LEN];
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413};
414
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415struct be_resources {
416 u16 max_vfs; /* Total VFs "really" supported by FW/HW */
417 u16 max_mcast_mac;
418 u16 max_tx_qs;
419 u16 max_rss_qs;
420 u16 max_rx_qs;
f2858738 421 u16 max_cq_count;
92bf14ab
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422 u16 max_uc_mac; /* Max UC MACs programmable */
423 u16 max_vlans; /* Number of vlans supported */
f2858738
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424 u16 max_iface_count;
425 u16 max_mcc_count;
92bf14ab
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426 u16 max_evt_qs;
427 u32 if_cap_flags;
10cccf60 428 u32 vf_if_cap_flags; /* VF if capability flags */
92bf14ab
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429};
430
e2557877
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431struct rss_info {
432 u64 rss_flags;
433 u8 rsstable[RSS_INDIR_TABLE_LEN];
434 u8 rss_queue[RSS_INDIR_TABLE_LEN];
435 u8 rss_hkey[RSS_HASH_KEY_LEN];
436};
437
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438#define BE_INVALID_DIE_TEMP 0xFF
439struct be_hwmon {
440 struct device *hwmon_dev;
441 u8 be_on_die_temp; /* Unit: millidegree Celsius */
442};
443
804abcdb
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444/* Macros to read/write the 'features' word of be_wrb_params structure.
445 */
446#define BE_WRB_F_BIT(name) BE_WRB_F_##name##_BIT
447#define BE_WRB_F_MASK(name) BIT_MASK(BE_WRB_F_##name##_BIT)
448
449#define BE_WRB_F_GET(word, name) \
450 (((word) & (BE_WRB_F_MASK(name))) >> BE_WRB_F_BIT(name))
451
452#define BE_WRB_F_SET(word, name, val) \
453 ((word) |= (((val) << BE_WRB_F_BIT(name)) & BE_WRB_F_MASK(name)))
454
455/* Feature/offload bits */
456enum {
457 BE_WRB_F_CRC_BIT, /* Ethernet CRC */
458 BE_WRB_F_IPCS_BIT, /* IP csum */
459 BE_WRB_F_TCPCS_BIT, /* TCP csum */
460 BE_WRB_F_UDPCS_BIT, /* UDP csum */
461 BE_WRB_F_LSO_BIT, /* LSO */
462 BE_WRB_F_LSO6_BIT, /* LSO6 */
463 BE_WRB_F_VLAN_BIT, /* VLAN */
464 BE_WRB_F_VLAN_SKIP_HW_BIT /* Skip VLAN tag (workaround) */
465};
466
467/* The structure below provides a HW-agnostic abstraction of WRB params
468 * retrieved from a TX skb. This is in turn passed to chip specific routines
469 * during transmit, to set the corresponding params in the WRB.
470 */
471struct be_wrb_params {
472 u32 features; /* Feature bits */
473 u16 vlan_tag; /* VLAN tag */
474 u16 lso_mss; /* MSS for LSO */
475};
476
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477struct be_adapter {
478 struct pci_dev *pdev;
479 struct net_device *netdev;
480
c5b3ad4c 481 u8 __iomem *csr; /* CSR BAR used only for BE2/3 */
8788fdc2 482 u8 __iomem *db; /* Door Bell */
25848c90 483 u8 __iomem *pcicfg; /* On SH,BEx only. Shadow of PCI config space */
8788fdc2 484
2984961c 485 struct mutex mbox_lock; /* For serializing mbox cmds to BE card */
8788fdc2
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486 struct be_dma_mem mbox_mem;
487 /* Mbox mem is adjusted to align to 16 bytes. The allocated addr
488 * is stored for freeing purpose */
489 struct be_dma_mem mbox_mem_alloced;
490
491 struct be_mcc_obj mcc_obj;
492 spinlock_t mcc_lock; /* For serializing mcc cmds to BE card */
493 spinlock_t mcc_cq_lock;
6b7c5b94 494
92bf14ab
SP
495 u16 cfg_num_qs; /* configured via set-channels */
496 u16 num_evt_qs;
497 u16 num_msix_vec;
498 struct be_eq_obj eq_obj[MAX_EVT_QS];
10ef9ab4 499 struct msix_entry msix_entries[MAX_MSIX_VECTORS];
6b7c5b94
SP
500 bool isr_registered;
501
502 /* TX Rings */
92bf14ab 503 u16 num_tx_qs;
3c8def97 504 struct be_tx_obj tx_obj[MAX_TX_QS];
6b7c5b94
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505
506 /* Rx rings */
92bf14ab 507 u16 num_rx_qs;
71bb8bd0
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508 u16 num_rss_qs;
509 u16 need_def_rxq;
10ef9ab4 510 struct be_rx_obj rx_obj[MAX_RX_QS];
6b7c5b94
SP
511 u32 big_page_size; /* Compounded page size shared by rx wrbs */
512
609ff3bb 513 struct be_drv_stats drv_stats;
2632bafd 514 struct be_aic_obj aic_obj[MAX_EVT_QS];
cc4ce020
SK
515 u8 vlan_prio_bmap; /* Available Priority BitMap */
516 u16 recommended_prio; /* Recommended Priority */
5b8821b7 517 struct be_dma_mem rx_filter; /* Cmd DMA mem for rx-filter */
6b7c5b94 518
3abcdeda 519 struct be_dma_mem stats_cmd;
6b7c5b94
SP
520 /* Work queue used to perform periodic tasks like getting statistics */
521 struct delayed_work work;
609ff3bb 522 u16 work_counter;
6b7c5b94 523
eb7dd46c 524 struct delayed_work be_err_detection_work;
b236916a 525 u32 flags;
f25b119c 526 u32 cmd_privileges;
6b7c5b94 527 /* Ethtool knobs and info */
6b7c5b94 528 char fw_ver[FW_VER_LEN];
eeb65ced 529 char fw_on_flash[FW_VER_LEN];
f66b7cfd
SP
530
531 /* IFACE filtering fields */
30128031 532 int if_handle; /* Used to configure filtering */
f66b7cfd 533 u32 if_flags; /* Interface filtering flags */
fbc13f01 534 u32 *pmac_id; /* MAC addr handle used by BE card */
f66b7cfd
SP
535 u32 uc_macs; /* Count of secondary UC MAC programmed */
536 unsigned long vids[BITS_TO_LONGS(VLAN_N_VID)];
537 u16 vlans_added;
538
1a642469 539 u32 beacon_state; /* for set_phys_id */
6b7c5b94 540
f67ef7ba 541 bool eeh_error;
6589ade0 542 bool fw_timeout;
f67ef7ba
PR
543 bool hw_error;
544
6b7c5b94 545 u32 port_num;
21252377 546 char port_name;
f93f160b 547 u8 mc_type;
3486be29 548 u32 function_mode;
3abcdeda 549 u32 function_caps;
9e90c961
AK
550 u32 rx_fc; /* Rx flow control */
551 u32 tx_fc; /* Tx flow control */
b2aebe6d 552 bool stats_cmd_sent;
045508a8 553 struct {
045508a8
PP
554 u32 size;
555 u32 total_size;
556 u64 io_addr;
557 } roce_db;
558 u32 num_msix_roce_vec;
559 struct ocrdma_dev *ocrdma_dev;
560 struct list_head entry;
561
dd131e76 562 u32 flash_status;
5eeff635 563 struct completion et_cmd_compl;
ba343c77 564
bec84e6b 565 struct be_resources pool_res; /* resources available for the port */
92bf14ab
SP
566 struct be_resources res; /* resources available for the func */
567 u16 num_vfs; /* Number of VFs provisioned by PF */
39f1d94d 568 u8 virtfn;
11ac75ed
SP
569 struct be_vf_cfg *vf_cfg;
570 bool be3_native;
fe6d2a38 571 u32 sli_family;
9e1453c5 572 u8 hba_port_num;
3968fa1e 573 u16 pvid;
c9c47142 574 __be16 vxlan_port;
630f4b70 575 int vxlan_port_count;
42f11cf2 576 struct phy_info phy;
4762f6ce 577 u8 wol_cap;
76a9e08e 578 bool wol_en;
0ad3157e 579 u16 asic_rev;
bc0c3405 580 u16 qnq_vid;
941a77d5 581 u32 msg_enable;
7aeb2156 582 int be_get_temp_freq;
29e9122b 583 struct be_hwmon hwmon_info;
d5c18473 584 u8 pf_number;
e2557877 585 struct rss_info rss_info;
6b7c5b94
SP
586};
587
39f1d94d 588#define be_physfn(adapter) (!adapter->virtfn)
2c7a9dc1 589#define be_virtfn(adapter) (adapter->virtfn)
f174c7ec
VV
590#define sriov_enabled(adapter) (adapter->flags & \
591 BE_FLAGS_SRIOV_ENABLED)
bec84e6b 592
11ac75ed
SP
593#define for_all_vfs(adapter, vf_cfg, i) \
594 for (i = 0, vf_cfg = &adapter->vf_cfg[i]; i < adapter->num_vfs; \
595 i++, vf_cfg++)
ba343c77 596
5b8821b7
SP
597#define ON 1
598#define OFF 0
ca34fe38 599
92bf14ab
SP
600#define be_max_vlans(adapter) (adapter->res.max_vlans)
601#define be_max_uc(adapter) (adapter->res.max_uc_mac)
602#define be_max_mc(adapter) (adapter->res.max_mcast_mac)
bec84e6b 603#define be_max_vfs(adapter) (adapter->pool_res.max_vfs)
92bf14ab
SP
604#define be_max_rss(adapter) (adapter->res.max_rss_qs)
605#define be_max_txqs(adapter) (adapter->res.max_tx_qs)
606#define be_max_prio_txqs(adapter) (adapter->res.max_prio_tx_qs)
607#define be_max_rxqs(adapter) (adapter->res.max_rx_qs)
608#define be_max_eqs(adapter) (adapter->res.max_evt_qs)
609#define be_if_cap_flags(adapter) (adapter->res.if_cap_flags)
610
611static inline u16 be_max_qs(struct be_adapter *adapter)
612{
613 /* If no RSS, need atleast the one def RXQ */
614 u16 num = max_t(u16, be_max_rss(adapter), 1);
615
616 num = min(num, be_max_eqs(adapter));
617 return min_t(u16, num, num_online_cpus());
618}
619
f93f160b
VV
620/* Is BE in pvid_tagging mode */
621#define be_pvid_tagging_enabled(adapter) (adapter->pvid)
622
623/* Is BE in QNQ multi-channel mode */
66064dbc 624#define be_is_qnq_mode(adapter) (adapter->function_mode & QNQ_MODE)
f93f160b 625
ca34fe38
SP
626#define lancer_chip(adapter) (adapter->pdev->device == OC_DEVICE_ID3 || \
627 adapter->pdev->device == OC_DEVICE_ID4)
fe6d2a38 628
76b73530
PR
629#define skyhawk_chip(adapter) (adapter->pdev->device == OC_DEVICE_ID5 || \
630 adapter->pdev->device == OC_DEVICE_ID6)
d3bd3a5e 631
ca34fe38
SP
632#define BE3_chip(adapter) (adapter->pdev->device == BE_DEVICE_ID2 || \
633 adapter->pdev->device == OC_DEVICE_ID2)
634
635#define BE2_chip(adapter) (adapter->pdev->device == BE_DEVICE_ID1 || \
636 adapter->pdev->device == OC_DEVICE_ID1)
637
638#define BEx_chip(adapter) (BE3_chip(adapter) || BE2_chip(adapter))
d3bd3a5e 639
dbf0f2a7
SP
640#define be_roce_supported(adapter) (skyhawk_chip(adapter) && \
641 (adapter->function_mode & RDMA_ENABLED))
045508a8 642
0fc0b732 643extern const struct ethtool_ops be_ethtool_ops;
6b7c5b94 644
ac6a0c4a 645#define msix_enabled(adapter) (adapter->num_msix_vec > 0)
10ef9ab4
SP
646#define num_irqs(adapter) (msix_enabled(adapter) ? \
647 adapter->num_msix_vec : 1)
648#define tx_stats(txo) (&(txo)->stats)
649#define rx_stats(rxo) (&(rxo)->stats)
6b7c5b94 650
10ef9ab4
SP
651/* The default RXQ is the last RXQ */
652#define default_rxo(adpt) (&adpt->rx_obj[adpt->num_rx_qs - 1])
6b7c5b94 653
3abcdeda
SP
654#define for_all_rx_queues(adapter, rxo, i) \
655 for (i = 0, rxo = &adapter->rx_obj[i]; i < adapter->num_rx_qs; \
656 i++, rxo++)
657
3abcdeda 658#define for_all_rss_queues(adapter, rxo, i) \
71bb8bd0 659 for (i = 0, rxo = &adapter->rx_obj[i]; i < adapter->num_rss_qs; \
3abcdeda
SP
660 i++, rxo++)
661
3c8def97
SP
662#define for_all_tx_queues(adapter, txo, i) \
663 for (i = 0, txo = &adapter->tx_obj[i]; i < adapter->num_tx_qs; \
664 i++, txo++)
665
10ef9ab4
SP
666#define for_all_evt_queues(adapter, eqo, i) \
667 for (i = 0, eqo = &adapter->eq_obj[i]; i < adapter->num_evt_qs; \
668 i++, eqo++)
669
6384a4d0
SP
670#define for_all_rx_queues_on_eq(adapter, eqo, rxo, i) \
671 for (i = eqo->idx, rxo = &adapter->rx_obj[i]; i < adapter->num_rx_qs;\
672 i += adapter->num_evt_qs, rxo += adapter->num_evt_qs)
673
a4906ea0
SP
674#define for_all_tx_queues_on_eq(adapter, eqo, txo, i) \
675 for (i = eqo->idx, txo = &adapter->tx_obj[i]; i < adapter->num_tx_qs;\
676 i += adapter->num_evt_qs, txo += adapter->num_evt_qs)
677
10ef9ab4
SP
678#define is_mcc_eqo(eqo) (eqo->idx == 0)
679#define mcc_eqo(adapter) (&adapter->eq_obj[0])
680
6b7c5b94
SP
681#define PAGE_SHIFT_4K 12
682#define PAGE_SIZE_4K (1 << PAGE_SHIFT_4K)
683
684/* Returns number of pages spanned by the data starting at the given addr */
685#define PAGES_4K_SPANNED(_address, size) \
686 ((u32)((((size_t)(_address) & (PAGE_SIZE_4K - 1)) + \
687 (size) + (PAGE_SIZE_4K - 1)) >> PAGE_SHIFT_4K))
688
6b7c5b94
SP
689/* Returns bit offset within a DWORD of a bitfield */
690#define AMAP_BIT_OFFSET(_struct, field) \
691 (((size_t)&(((_struct *)0)->field))%32)
692
693/* Returns the bit mask of the field that is NOT shifted into location. */
694static inline u32 amap_mask(u32 bitsize)
695{
696 return (bitsize == 32 ? 0xFFFFFFFF : (1 << bitsize) - 1);
697}
698
699static inline void
700amap_set(void *ptr, u32 dw_offset, u32 mask, u32 offset, u32 value)
701{
702 u32 *dw = (u32 *) ptr + dw_offset;
703 *dw &= ~(mask << offset);
704 *dw |= (mask & value) << offset;
705}
706
707#define AMAP_SET_BITS(_struct, field, ptr, val) \
708 amap_set(ptr, \
709 offsetof(_struct, field)/32, \
710 amap_mask(sizeof(((_struct *)0)->field)), \
711 AMAP_BIT_OFFSET(_struct, field), \
712 val)
713
714static inline u32 amap_get(void *ptr, u32 dw_offset, u32 mask, u32 offset)
715{
716 u32 *dw = (u32 *) ptr;
717 return mask & (*(dw + dw_offset) >> offset);
718}
719
720#define AMAP_GET_BITS(_struct, field, ptr) \
721 amap_get(ptr, \
722 offsetof(_struct, field)/32, \
723 amap_mask(sizeof(((_struct *)0)->field)), \
724 AMAP_BIT_OFFSET(_struct, field))
725
c3c18bc1
SP
726#define GET_RX_COMPL_V0_BITS(field, ptr) \
727 AMAP_GET_BITS(struct amap_eth_rx_compl_v0, field, ptr)
728
729#define GET_RX_COMPL_V1_BITS(field, ptr) \
730 AMAP_GET_BITS(struct amap_eth_rx_compl_v1, field, ptr)
731
732#define GET_TX_COMPL_BITS(field, ptr) \
733 AMAP_GET_BITS(struct amap_eth_tx_compl, field, ptr)
734
735#define SET_TX_WRB_HDR_BITS(field, ptr, val) \
736 AMAP_SET_BITS(struct amap_eth_hdr_wrb, field, ptr, val)
737
6b7c5b94
SP
738#define be_dws_cpu_to_le(wrb, len) swap_dws(wrb, len)
739#define be_dws_le_to_cpu(wrb, len) swap_dws(wrb, len)
740static inline void swap_dws(void *wrb, int len)
741{
742#ifdef __BIG_ENDIAN
743 u32 *dw = wrb;
744 BUG_ON(len % 4);
745 do {
746 *dw = cpu_to_le32(*dw);
747 dw++;
748 len -= 4;
749 } while (len);
750#endif /* __BIG_ENDIAN */
751}
752
0532d4e3
KA
753#define be_cmd_status(status) (status > 0 ? -EIO : status)
754
6b7c5b94
SP
755static inline u8 is_tcp_pkt(struct sk_buff *skb)
756{
757 u8 val = 0;
758
759 if (ip_hdr(skb)->version == 4)
760 val = (ip_hdr(skb)->protocol == IPPROTO_TCP);
761 else if (ip_hdr(skb)->version == 6)
762 val = (ipv6_hdr(skb)->nexthdr == NEXTHDR_TCP);
763
764 return val;
765}
766
767static inline u8 is_udp_pkt(struct sk_buff *skb)
768{
769 u8 val = 0;
770
771 if (ip_hdr(skb)->version == 4)
772 val = (ip_hdr(skb)->protocol == IPPROTO_UDP);
773 else if (ip_hdr(skb)->version == 6)
774 val = (ipv6_hdr(skb)->nexthdr == NEXTHDR_UDP);
775
776 return val;
777}
778
93040ae5
SK
779static inline bool is_ipv4_pkt(struct sk_buff *skb)
780{
e8efcec5 781 return skb->protocol == htons(ETH_P_IP) && ip_hdr(skb)->version == 4;
93040ae5
SK
782}
783
4b972914
AK
784static inline bool be_multi_rxq(const struct be_adapter *adapter)
785{
786 return adapter->num_rx_qs > 1;
787}
788
6589ade0
SP
789static inline bool be_error(struct be_adapter *adapter)
790{
f67ef7ba
PR
791 return adapter->eeh_error || adapter->hw_error || adapter->fw_timeout;
792}
793
d23e946c 794static inline bool be_hw_error(struct be_adapter *adapter)
f67ef7ba
PR
795{
796 return adapter->eeh_error || adapter->hw_error;
797}
798
799static inline void be_clear_all_error(struct be_adapter *adapter)
800{
801 adapter->eeh_error = false;
802 adapter->hw_error = false;
803 adapter->fw_timeout = false;
6589ade0
SP
804}
805
31886e87
JP
806void be_cq_notify(struct be_adapter *adapter, u16 qid, bool arm,
807 u16 num_popped);
808void be_link_status_update(struct be_adapter *adapter, u8 link_status);
809void be_parse_stats(struct be_adapter *adapter);
810int be_load_fw(struct be_adapter *adapter, u8 *func);
811bool be_is_wol_supported(struct be_adapter *adapter);
812bool be_pause_supported(struct be_adapter *adapter);
813u32 be_get_fw_log_level(struct be_adapter *adapter);
68d7bdcb
SP
814int be_update_queues(struct be_adapter *adapter);
815int be_poll(struct napi_struct *napi, int budget);
20947770 816void be_eqd_update(struct be_adapter *adapter, bool force_update);
941a77d5 817
045508a8
PP
818/*
819 * internal function to initialize-cleanup roce device.
820 */
31886e87
JP
821void be_roce_dev_add(struct be_adapter *);
822void be_roce_dev_remove(struct be_adapter *);
045508a8
PP
823
824/*
825 * internal function to open-close roce device during ifup-ifdown.
826 */
31886e87
JP
827void be_roce_dev_open(struct be_adapter *);
828void be_roce_dev_close(struct be_adapter *);
d114f99a 829void be_roce_dev_shutdown(struct be_adapter *);
045508a8 830
6b7c5b94 831#endif /* BE_H */
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