Commit | Line | Data |
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6b7c5b94 | 1 | /* |
40263820 | 2 | * Copyright (C) 2005 - 2014 Emulex |
6b7c5b94 SP |
3 | * All rights reserved. |
4 | * | |
5 | * This program is free software; you can redistribute it and/or | |
6 | * modify it under the terms of the GNU General Public License version 2 | |
7 | * as published by the Free Software Foundation. The full GNU General | |
8 | * Public License is included in this distribution in the file called COPYING. | |
9 | * | |
10 | * Contact Information: | |
d2145cde | 11 | * linux-drivers@emulex.com |
6b7c5b94 | 12 | * |
d2145cde AK |
13 | * Emulex |
14 | * 3333 Susan Street | |
15 | * Costa Mesa, CA 92626 | |
6b7c5b94 SP |
16 | */ |
17 | ||
18 | #ifndef BE_H | |
19 | #define BE_H | |
20 | ||
21 | #include <linux/pci.h> | |
22 | #include <linux/etherdevice.h> | |
6b7c5b94 SP |
23 | #include <linux/delay.h> |
24 | #include <net/tcp.h> | |
25 | #include <net/ip.h> | |
26 | #include <net/ipv6.h> | |
27 | #include <linux/if_vlan.h> | |
28 | #include <linux/workqueue.h> | |
29 | #include <linux/interrupt.h> | |
84517482 | 30 | #include <linux/firmware.h> |
5a0e3ad6 | 31 | #include <linux/slab.h> |
ab1594e9 | 32 | #include <linux/u64_stats_sync.h> |
6b7c5b94 SP |
33 | |
34 | #include "be_hw.h" | |
045508a8 | 35 | #include "be_roce.h" |
6b7c5b94 | 36 | |
c346e6e5 | 37 | #define DRV_VER "10.4u" |
6b7c5b94 | 38 | #define DRV_NAME "be2net" |
00d3d51e SB |
39 | #define BE_NAME "Emulex BladeEngine2" |
40 | #define BE3_NAME "Emulex BladeEngine3" | |
41 | #define OC_NAME "Emulex OneConnect" | |
fe6d2a38 SP |
42 | #define OC_NAME_BE OC_NAME "(be3)" |
43 | #define OC_NAME_LANCER OC_NAME "(Lancer)" | |
ecedb6ae | 44 | #define OC_NAME_SH OC_NAME "(Skyhawk)" |
f3effb45 | 45 | #define DRV_DESC "Emulex OneConnect NIC Driver" |
6b7c5b94 | 46 | |
c4ca2374 | 47 | #define BE_VENDOR_ID 0x19a2 |
fe6d2a38 | 48 | #define EMULEX_VENDOR_ID 0x10df |
c4ca2374 | 49 | #define BE_DEVICE_ID1 0x211 |
12d7ea2c | 50 | #define BE_DEVICE_ID2 0x221 |
fe6d2a38 SP |
51 | #define OC_DEVICE_ID1 0x700 /* Device Id for BE2 cards */ |
52 | #define OC_DEVICE_ID2 0x710 /* Device Id for BE3 cards */ | |
53 | #define OC_DEVICE_ID3 0xe220 /* Device id for Lancer cards */ | |
12f4d0a8 | 54 | #define OC_DEVICE_ID4 0xe228 /* Device id for VF in Lancer */ |
ecedb6ae | 55 | #define OC_DEVICE_ID5 0x720 /* Device Id for Skyhawk cards */ |
76b73530 | 56 | #define OC_DEVICE_ID6 0x728 /* Device id for VF in SkyHawk */ |
4762f6ce AK |
57 | #define OC_SUBSYS_DEVICE_ID1 0xE602 |
58 | #define OC_SUBSYS_DEVICE_ID2 0xE642 | |
59 | #define OC_SUBSYS_DEVICE_ID3 0xE612 | |
60 | #define OC_SUBSYS_DEVICE_ID4 0xE652 | |
c4ca2374 | 61 | |
6b7c5b94 | 62 | /* Number of bytes of an RX frame that are copied to skb->data */ |
2e588f84 | 63 | #define BE_HDR_LEN ((u16) 64) |
bb349bb4 ED |
64 | /* allocate extra space to allow tunneling decapsulation without head reallocation */ |
65 | #define BE_RX_SKB_ALLOC_SIZE (BE_HDR_LEN + 64) | |
66 | ||
6b7c5b94 SP |
67 | #define BE_MAX_JUMBO_FRAME_SIZE 9018 |
68 | #define BE_MIN_MTU 256 | |
0d3f5cce KA |
69 | #define BE_MAX_MTU (BE_MAX_JUMBO_FRAME_SIZE - \ |
70 | (ETH_HLEN + ETH_FCS_LEN)) | |
6b7c5b94 SP |
71 | |
72 | #define BE_NUM_VLANS_SUPPORTED 64 | |
2632bafd | 73 | #define BE_MAX_EQD 128u |
6b7c5b94 SP |
74 | #define BE_MAX_TX_FRAG_COUNT 30 |
75 | ||
76 | #define EVNT_Q_LEN 1024 | |
77 | #define TX_Q_LEN 2048 | |
78 | #define TX_CQ_LEN 1024 | |
79 | #define RX_Q_LEN 1024 /* Does not support any other value */ | |
80 | #define RX_CQ_LEN 1024 | |
5fb379ee | 81 | #define MCC_Q_LEN 128 /* total size not to exceed 8 pages */ |
6b7c5b94 SP |
82 | #define MCC_CQ_LEN 256 |
83 | ||
10ef9ab4 | 84 | #define BE2_MAX_RSS_QS 4 |
68d7bdcb SP |
85 | #define BE3_MAX_RSS_QS 16 |
86 | #define BE3_MAX_TX_QS 16 | |
87 | #define BE3_MAX_EVT_QS 16 | |
e3dc867c | 88 | #define BE3_SRIOV_MAX_EVT_QS 8 |
68d7bdcb SP |
89 | |
90 | #define MAX_RX_QS 32 | |
91 | #define MAX_EVT_QS 32 | |
92 | #define MAX_TX_QS 32 | |
10ef9ab4 | 93 | |
045508a8 | 94 | #define MAX_ROCE_EQS 5 |
68d7bdcb | 95 | #define MAX_MSIX_VECTORS 32 |
92bf14ab | 96 | #define MIN_MSIX_VECTORS 1 |
6b7c5b94 | 97 | #define BE_NAPI_WEIGHT 64 |
10ef9ab4 | 98 | #define MAX_RX_POST BE_NAPI_WEIGHT /* Frags posted at a time */ |
6b7c5b94 SP |
99 | #define RX_FRAGS_REFILL_WM (RX_Q_LEN - MAX_RX_POST) |
100 | ||
7c5a5242 | 101 | #define MAX_VFS 30 /* Max VFs supported by BE3 FW */ |
8788fdc2 SP |
102 | #define FW_VER_LEN 32 |
103 | ||
e2557877 VD |
104 | #define RSS_INDIR_TABLE_LEN 128 |
105 | #define RSS_HASH_KEY_LEN 40 | |
106 | ||
6b7c5b94 SP |
107 | struct be_dma_mem { |
108 | void *va; | |
109 | dma_addr_t dma; | |
110 | u32 size; | |
111 | }; | |
112 | ||
113 | struct be_queue_info { | |
114 | struct be_dma_mem dma_mem; | |
115 | u16 len; | |
116 | u16 entry_size; /* Size of an element in the queue */ | |
117 | u16 id; | |
118 | u16 tail, head; | |
119 | bool created; | |
120 | atomic_t used; /* Number of valid elements in the queue */ | |
121 | }; | |
122 | ||
5fb379ee SP |
123 | static inline u32 MODULO(u16 val, u16 limit) |
124 | { | |
125 | BUG_ON(limit & (limit - 1)); | |
126 | return val & (limit - 1); | |
127 | } | |
128 | ||
129 | static inline void index_adv(u16 *index, u16 val, u16 limit) | |
130 | { | |
131 | *index = MODULO((*index + val), limit); | |
132 | } | |
133 | ||
134 | static inline void index_inc(u16 *index, u16 limit) | |
135 | { | |
136 | *index = MODULO((*index + 1), limit); | |
137 | } | |
138 | ||
139 | static inline void *queue_head_node(struct be_queue_info *q) | |
140 | { | |
141 | return q->dma_mem.va + q->head * q->entry_size; | |
142 | } | |
143 | ||
144 | static inline void *queue_tail_node(struct be_queue_info *q) | |
145 | { | |
146 | return q->dma_mem.va + q->tail * q->entry_size; | |
147 | } | |
148 | ||
3de09455 SK |
149 | static inline void *queue_index_node(struct be_queue_info *q, u16 index) |
150 | { | |
151 | return q->dma_mem.va + index * q->entry_size; | |
152 | } | |
153 | ||
5fb379ee SP |
154 | static inline void queue_head_inc(struct be_queue_info *q) |
155 | { | |
156 | index_inc(&q->head, q->len); | |
157 | } | |
158 | ||
652bf646 PR |
159 | static inline void index_dec(u16 *index, u16 limit) |
160 | { | |
161 | *index = MODULO((*index - 1), limit); | |
162 | } | |
163 | ||
5fb379ee SP |
164 | static inline void queue_tail_inc(struct be_queue_info *q) |
165 | { | |
166 | index_inc(&q->tail, q->len); | |
167 | } | |
168 | ||
5fb379ee SP |
169 | struct be_eq_obj { |
170 | struct be_queue_info q; | |
171 | char desc[32]; | |
172 | ||
173 | /* Adaptive interrupt coalescing (AIC) info */ | |
174 | bool enable_aic; | |
10ef9ab4 SP |
175 | u32 min_eqd; /* in usecs */ |
176 | u32 max_eqd; /* in usecs */ | |
177 | u32 eqd; /* configured val when aic is off */ | |
178 | u32 cur_eqd; /* in usecs */ | |
5fb379ee | 179 | |
10ef9ab4 | 180 | u8 idx; /* array index */ |
f2f781a7 | 181 | u8 msix_idx; |
d0b9cec3 | 182 | u16 spurious_intr; |
5fb379ee | 183 | struct napi_struct napi; |
10ef9ab4 | 184 | struct be_adapter *adapter; |
6384a4d0 SP |
185 | |
186 | #ifdef CONFIG_NET_RX_BUSY_POLL | |
187 | #define BE_EQ_IDLE 0 | |
188 | #define BE_EQ_NAPI 1 /* napi owns this EQ */ | |
189 | #define BE_EQ_POLL 2 /* poll owns this EQ */ | |
190 | #define BE_EQ_LOCKED (BE_EQ_NAPI | BE_EQ_POLL) | |
191 | #define BE_EQ_NAPI_YIELD 4 /* napi yielded this EQ */ | |
192 | #define BE_EQ_POLL_YIELD 8 /* poll yielded this EQ */ | |
193 | #define BE_EQ_YIELD (BE_EQ_NAPI_YIELD | BE_EQ_POLL_YIELD) | |
194 | #define BE_EQ_USER_PEND (BE_EQ_POLL | BE_EQ_POLL_YIELD) | |
195 | unsigned int state; | |
196 | spinlock_t lock; /* lock to serialize napi and busy-poll */ | |
197 | #endif /* CONFIG_NET_RX_BUSY_POLL */ | |
10ef9ab4 | 198 | } ____cacheline_aligned_in_smp; |
5fb379ee | 199 | |
2632bafd SP |
200 | struct be_aic_obj { /* Adaptive interrupt coalescing (AIC) info */ |
201 | bool enable; | |
202 | u32 min_eqd; /* in usecs */ | |
203 | u32 max_eqd; /* in usecs */ | |
204 | u32 prev_eqd; /* in usecs */ | |
205 | u32 et_eqd; /* configured val when aic is off */ | |
206 | ulong jiffies; | |
207 | u64 rx_pkts_prev; /* Used to calculate RX pps */ | |
208 | u64 tx_reqs_prev; /* Used to calculate TX pps */ | |
209 | }; | |
210 | ||
6384a4d0 SP |
211 | enum { |
212 | NAPI_POLLING, | |
213 | BUSY_POLLING | |
214 | }; | |
215 | ||
5fb379ee SP |
216 | struct be_mcc_obj { |
217 | struct be_queue_info q; | |
218 | struct be_queue_info cq; | |
7a1e9b20 | 219 | bool rearm_cq; |
5fb379ee SP |
220 | }; |
221 | ||
3abcdeda | 222 | struct be_tx_stats { |
ac124ff9 SP |
223 | u64 tx_bytes; |
224 | u64 tx_pkts; | |
225 | u64 tx_reqs; | |
ac124ff9 SP |
226 | u64 tx_compl; |
227 | ulong tx_jiffies; | |
228 | u32 tx_stops; | |
bc617526 | 229 | u32 tx_drv_drops; /* pkts dropped by driver */ |
512bb8a2 KA |
230 | /* the error counters are described in be_ethtool.c */ |
231 | u32 tx_hdr_parse_err; | |
232 | u32 tx_dma_err; | |
233 | u32 tx_tso_err; | |
234 | u32 tx_spoof_check_err; | |
235 | u32 tx_qinq_err; | |
236 | u32 tx_internal_parity_err; | |
ab1594e9 SP |
237 | struct u64_stats_sync sync; |
238 | struct u64_stats_sync sync_compl; | |
6b7c5b94 SP |
239 | }; |
240 | ||
6b7c5b94 | 241 | struct be_tx_obj { |
94d73aaa | 242 | u32 db_offset; |
6b7c5b94 SP |
243 | struct be_queue_info q; |
244 | struct be_queue_info cq; | |
245 | /* Remember the skbs that were transmitted */ | |
246 | struct sk_buff *sent_skb_list[TX_Q_LEN]; | |
3c8def97 | 247 | struct be_tx_stats stats; |
5f07b3c5 SP |
248 | u16 pend_wrb_cnt; /* Number of WRBs yet to be given to HW */ |
249 | u16 last_req_wrb_cnt; /* wrb cnt of the last req in the Q */ | |
250 | u16 last_req_hdr; /* index of the last req's hdr-wrb */ | |
10ef9ab4 | 251 | } ____cacheline_aligned_in_smp; |
6b7c5b94 SP |
252 | |
253 | /* Struct to remember the pages posted for rx frags */ | |
254 | struct be_rx_page_info { | |
255 | struct page *page; | |
e50287be | 256 | /* set to page-addr for last frag of the page & frag-addr otherwise */ |
fac6da5b | 257 | DEFINE_DMA_UNMAP_ADDR(bus); |
6b7c5b94 | 258 | u16 page_offset; |
e50287be | 259 | bool last_frag; /* last frag of the page */ |
6b7c5b94 SP |
260 | }; |
261 | ||
3abcdeda | 262 | struct be_rx_stats { |
3abcdeda | 263 | u64 rx_bytes; |
3abcdeda | 264 | u64 rx_pkts; |
ac124ff9 SP |
265 | u32 rx_drops_no_skbs; /* skb allocation errors */ |
266 | u32 rx_drops_no_frags; /* HW has no fetched frags */ | |
267 | u32 rx_post_fail; /* page post alloc failures */ | |
ac124ff9 | 268 | u32 rx_compl; |
3abcdeda | 269 | u32 rx_mcast_pkts; |
ac124ff9 | 270 | u32 rx_compl_err; /* completions with err set */ |
ab1594e9 | 271 | struct u64_stats_sync sync; |
3abcdeda SP |
272 | }; |
273 | ||
2e588f84 SP |
274 | struct be_rx_compl_info { |
275 | u32 rss_hash; | |
6709d952 | 276 | u16 vlan_tag; |
2e588f84 | 277 | u16 pkt_size; |
12004ae9 | 278 | u16 port; |
2e588f84 SP |
279 | u8 vlanf; |
280 | u8 num_rcvd; | |
281 | u8 err; | |
282 | u8 ipf; | |
283 | u8 tcpf; | |
284 | u8 udpf; | |
285 | u8 ip_csum; | |
286 | u8 l4_csum; | |
287 | u8 ipv6; | |
f93f160b | 288 | u8 qnq; |
2e588f84 | 289 | u8 pkt_type; |
e38b1706 | 290 | u8 ip_frag; |
c9c47142 | 291 | u8 tunneled; |
2e588f84 SP |
292 | }; |
293 | ||
6b7c5b94 | 294 | struct be_rx_obj { |
3abcdeda | 295 | struct be_adapter *adapter; |
6b7c5b94 SP |
296 | struct be_queue_info q; |
297 | struct be_queue_info cq; | |
2e588f84 | 298 | struct be_rx_compl_info rxcp; |
6b7c5b94 | 299 | struct be_rx_page_info page_info_tbl[RX_Q_LEN]; |
3abcdeda SP |
300 | struct be_rx_stats stats; |
301 | u8 rss_id; | |
302 | bool rx_post_starved; /* Zero rx frags have been posted to BE */ | |
10ef9ab4 | 303 | } ____cacheline_aligned_in_smp; |
6b7c5b94 | 304 | |
609ff3bb | 305 | struct be_drv_stats { |
9ae081c6 | 306 | u32 be_on_die_temperature; |
ac124ff9 | 307 | u32 eth_red_drops; |
d3de1540 | 308 | u32 dma_map_errors; |
ac124ff9 SP |
309 | u32 rx_drops_no_pbuf; |
310 | u32 rx_drops_no_txpb; | |
311 | u32 rx_drops_no_erx_descr; | |
312 | u32 rx_drops_no_tpre_descr; | |
313 | u32 rx_drops_too_many_frags; | |
ac124ff9 SP |
314 | u32 forwarded_packets; |
315 | u32 rx_drops_mtu; | |
316 | u32 rx_crc_errors; | |
317 | u32 rx_alignment_symbol_errors; | |
318 | u32 rx_pause_frames; | |
319 | u32 rx_priority_pause_frames; | |
320 | u32 rx_control_frames; | |
321 | u32 rx_in_range_errors; | |
322 | u32 rx_out_range_errors; | |
323 | u32 rx_frame_too_long; | |
18fb06a1 | 324 | u32 rx_address_filtered; |
ac124ff9 SP |
325 | u32 rx_dropped_too_small; |
326 | u32 rx_dropped_too_short; | |
327 | u32 rx_dropped_header_too_small; | |
328 | u32 rx_dropped_tcp_length; | |
329 | u32 rx_dropped_runt; | |
330 | u32 rx_ip_checksum_errs; | |
331 | u32 rx_tcp_checksum_errs; | |
332 | u32 rx_udp_checksum_errs; | |
333 | u32 tx_pauseframes; | |
334 | u32 tx_priority_pauseframes; | |
335 | u32 tx_controlframes; | |
336 | u32 rxpp_fifo_overflow_drop; | |
337 | u32 rx_input_fifo_overflow_drop; | |
338 | u32 pmem_fifo_overflow_drop; | |
339 | u32 jabber_events; | |
461ae379 AK |
340 | u32 rx_roce_bytes_lsd; |
341 | u32 rx_roce_bytes_msd; | |
342 | u32 rx_roce_frames; | |
343 | u32 roce_drops_payload_len; | |
344 | u32 roce_drops_crc; | |
609ff3bb AK |
345 | }; |
346 | ||
c502224e SK |
347 | /* A vlan-id of 0xFFFF must be used to clear transparent vlan-tagging */ |
348 | #define BE_RESET_VLAN_TAG_ID 0xFFFF | |
349 | ||
64600ea5 | 350 | struct be_vf_cfg { |
11ac75ed SP |
351 | unsigned char mac_addr[ETH_ALEN]; |
352 | int if_handle; | |
353 | int pmac_id; | |
354 | u16 vlan_tag; | |
355 | u32 tx_rate; | |
bdce2ad7 | 356 | u32 plink_tracking; |
435452aa | 357 | u32 privileges; |
64600ea5 AK |
358 | }; |
359 | ||
39f1d94d SP |
360 | enum vf_state { |
361 | ENABLED = 0, | |
362 | ASSIGNED = 1 | |
363 | }; | |
364 | ||
83b06116 VV |
365 | #define BE_FLAGS_LINK_STATUS_INIT BIT(1) |
366 | #define BE_FLAGS_SRIOV_ENABLED BIT(2) | |
367 | #define BE_FLAGS_WORKER_SCHEDULED BIT(3) | |
83b06116 VV |
368 | #define BE_FLAGS_NAPI_ENABLED BIT(6) |
369 | #define BE_FLAGS_QNQ_ASYNC_EVT_RCVD BIT(7) | |
370 | #define BE_FLAGS_VXLAN_OFFLOADS BIT(8) | |
371 | #define BE_FLAGS_SETUP_DONE BIT(9) | |
21252377 | 372 | #define BE_FLAGS_EVT_INCOMPATIBLE_SFP BIT(10) |
b236916a | 373 | |
c9c47142 SP |
374 | #define BE_UC_PMAC_COUNT 30 |
375 | #define BE_VF_UC_PMAC_COUNT 2 | |
f0613380 | 376 | |
5c510811 SK |
377 | /* Ethtool set_dump flags */ |
378 | #define LANCER_INITIATE_FW_DUMP 0x1 | |
f0613380 | 379 | #define LANCER_DELETE_FW_DUMP 0x2 |
5c510811 | 380 | |
42f11cf2 | 381 | struct phy_info { |
21252377 VV |
382 | /* From SFF-8472 spec */ |
383 | #define SFP_VENDOR_NAME_LEN 17 | |
42f11cf2 AK |
384 | u8 transceiver; |
385 | u8 autoneg; | |
386 | u8 fc_autoneg; | |
387 | u8 port_type; | |
388 | u16 phy_type; | |
389 | u16 interface_type; | |
390 | u32 misc_params; | |
391 | u16 auto_speeds_supported; | |
392 | u16 fixed_speeds_supported; | |
393 | int link_speed; | |
42f11cf2 AK |
394 | u32 advertising; |
395 | u32 supported; | |
6809cee0 | 396 | u8 cable_type; |
21252377 VV |
397 | u8 vendor_name[SFP_VENDOR_NAME_LEN]; |
398 | u8 vendor_pn[SFP_VENDOR_NAME_LEN]; | |
42f11cf2 AK |
399 | }; |
400 | ||
92bf14ab SP |
401 | struct be_resources { |
402 | u16 max_vfs; /* Total VFs "really" supported by FW/HW */ | |
403 | u16 max_mcast_mac; | |
404 | u16 max_tx_qs; | |
405 | u16 max_rss_qs; | |
406 | u16 max_rx_qs; | |
407 | u16 max_uc_mac; /* Max UC MACs programmable */ | |
408 | u16 max_vlans; /* Number of vlans supported */ | |
409 | u16 max_evt_qs; | |
410 | u32 if_cap_flags; | |
10cccf60 | 411 | u32 vf_if_cap_flags; /* VF if capability flags */ |
92bf14ab SP |
412 | }; |
413 | ||
e2557877 VD |
414 | struct rss_info { |
415 | u64 rss_flags; | |
416 | u8 rsstable[RSS_INDIR_TABLE_LEN]; | |
417 | u8 rss_queue[RSS_INDIR_TABLE_LEN]; | |
418 | u8 rss_hkey[RSS_HASH_KEY_LEN]; | |
419 | }; | |
420 | ||
6b7c5b94 SP |
421 | struct be_adapter { |
422 | struct pci_dev *pdev; | |
423 | struct net_device *netdev; | |
424 | ||
c5b3ad4c | 425 | u8 __iomem *csr; /* CSR BAR used only for BE2/3 */ |
8788fdc2 | 426 | u8 __iomem *db; /* Door Bell */ |
25848c90 | 427 | u8 __iomem *pcicfg; /* On SH,BEx only. Shadow of PCI config space */ |
8788fdc2 | 428 | |
2984961c | 429 | struct mutex mbox_lock; /* For serializing mbox cmds to BE card */ |
8788fdc2 SP |
430 | struct be_dma_mem mbox_mem; |
431 | /* Mbox mem is adjusted to align to 16 bytes. The allocated addr | |
432 | * is stored for freeing purpose */ | |
433 | struct be_dma_mem mbox_mem_alloced; | |
434 | ||
435 | struct be_mcc_obj mcc_obj; | |
436 | spinlock_t mcc_lock; /* For serializing mcc cmds to BE card */ | |
437 | spinlock_t mcc_cq_lock; | |
6b7c5b94 | 438 | |
92bf14ab SP |
439 | u16 cfg_num_qs; /* configured via set-channels */ |
440 | u16 num_evt_qs; | |
441 | u16 num_msix_vec; | |
442 | struct be_eq_obj eq_obj[MAX_EVT_QS]; | |
10ef9ab4 | 443 | struct msix_entry msix_entries[MAX_MSIX_VECTORS]; |
6b7c5b94 SP |
444 | bool isr_registered; |
445 | ||
446 | /* TX Rings */ | |
92bf14ab | 447 | u16 num_tx_qs; |
3c8def97 | 448 | struct be_tx_obj tx_obj[MAX_TX_QS]; |
6b7c5b94 SP |
449 | |
450 | /* Rx rings */ | |
92bf14ab | 451 | u16 num_rx_qs; |
10ef9ab4 | 452 | struct be_rx_obj rx_obj[MAX_RX_QS]; |
6b7c5b94 SP |
453 | u32 big_page_size; /* Compounded page size shared by rx wrbs */ |
454 | ||
609ff3bb | 455 | struct be_drv_stats drv_stats; |
2632bafd | 456 | struct be_aic_obj aic_obj[MAX_EVT_QS]; |
cc4ce020 SK |
457 | u8 vlan_prio_bmap; /* Available Priority BitMap */ |
458 | u16 recommended_prio; /* Recommended Priority */ | |
5b8821b7 | 459 | struct be_dma_mem rx_filter; /* Cmd DMA mem for rx-filter */ |
6b7c5b94 | 460 | |
3abcdeda | 461 | struct be_dma_mem stats_cmd; |
6b7c5b94 SP |
462 | /* Work queue used to perform periodic tasks like getting statistics */ |
463 | struct delayed_work work; | |
609ff3bb | 464 | u16 work_counter; |
6b7c5b94 | 465 | |
f67ef7ba | 466 | struct delayed_work func_recovery_work; |
b236916a | 467 | u32 flags; |
f25b119c | 468 | u32 cmd_privileges; |
6b7c5b94 | 469 | /* Ethtool knobs and info */ |
6b7c5b94 | 470 | char fw_ver[FW_VER_LEN]; |
eeb65ced | 471 | char fw_on_flash[FW_VER_LEN]; |
f66b7cfd SP |
472 | |
473 | /* IFACE filtering fields */ | |
30128031 | 474 | int if_handle; /* Used to configure filtering */ |
f66b7cfd | 475 | u32 if_flags; /* Interface filtering flags */ |
fbc13f01 | 476 | u32 *pmac_id; /* MAC addr handle used by BE card */ |
f66b7cfd SP |
477 | u32 uc_macs; /* Count of secondary UC MAC programmed */ |
478 | unsigned long vids[BITS_TO_LONGS(VLAN_N_VID)]; | |
479 | u16 vlans_added; | |
480 | ||
1a642469 | 481 | u32 beacon_state; /* for set_phys_id */ |
6b7c5b94 | 482 | |
f67ef7ba | 483 | bool eeh_error; |
6589ade0 | 484 | bool fw_timeout; |
f67ef7ba PR |
485 | bool hw_error; |
486 | ||
6b7c5b94 | 487 | u32 port_num; |
21252377 | 488 | char port_name; |
f93f160b | 489 | u8 mc_type; |
3486be29 | 490 | u32 function_mode; |
3abcdeda | 491 | u32 function_caps; |
9e90c961 AK |
492 | u32 rx_fc; /* Rx flow control */ |
493 | u32 tx_fc; /* Tx flow control */ | |
b2aebe6d | 494 | bool stats_cmd_sent; |
045508a8 | 495 | struct { |
045508a8 PP |
496 | u32 size; |
497 | u32 total_size; | |
498 | u64 io_addr; | |
499 | } roce_db; | |
500 | u32 num_msix_roce_vec; | |
501 | struct ocrdma_dev *ocrdma_dev; | |
502 | struct list_head entry; | |
503 | ||
dd131e76 | 504 | u32 flash_status; |
5eeff635 | 505 | struct completion et_cmd_compl; |
ba343c77 | 506 | |
bec84e6b | 507 | struct be_resources pool_res; /* resources available for the port */ |
92bf14ab SP |
508 | struct be_resources res; /* resources available for the func */ |
509 | u16 num_vfs; /* Number of VFs provisioned by PF */ | |
39f1d94d | 510 | u8 virtfn; |
11ac75ed SP |
511 | struct be_vf_cfg *vf_cfg; |
512 | bool be3_native; | |
fe6d2a38 | 513 | u32 sli_family; |
9e1453c5 | 514 | u8 hba_port_num; |
3968fa1e | 515 | u16 pvid; |
c9c47142 | 516 | __be16 vxlan_port; |
630f4b70 | 517 | int vxlan_port_count; |
42f11cf2 | 518 | struct phy_info phy; |
4762f6ce | 519 | u8 wol_cap; |
76a9e08e | 520 | bool wol_en; |
0ad3157e | 521 | u16 asic_rev; |
bc0c3405 | 522 | u16 qnq_vid; |
941a77d5 | 523 | u32 msg_enable; |
7aeb2156 | 524 | int be_get_temp_freq; |
d5c18473 | 525 | u8 pf_number; |
e2557877 | 526 | struct rss_info rss_info; |
6b7c5b94 SP |
527 | }; |
528 | ||
39f1d94d | 529 | #define be_physfn(adapter) (!adapter->virtfn) |
2c7a9dc1 | 530 | #define be_virtfn(adapter) (adapter->virtfn) |
f174c7ec VV |
531 | #define sriov_enabled(adapter) (adapter->flags & \ |
532 | BE_FLAGS_SRIOV_ENABLED) | |
bec84e6b | 533 | |
11ac75ed SP |
534 | #define for_all_vfs(adapter, vf_cfg, i) \ |
535 | for (i = 0, vf_cfg = &adapter->vf_cfg[i]; i < adapter->num_vfs; \ | |
536 | i++, vf_cfg++) | |
ba343c77 | 537 | |
5b8821b7 SP |
538 | #define ON 1 |
539 | #define OFF 0 | |
ca34fe38 | 540 | |
92bf14ab SP |
541 | #define be_max_vlans(adapter) (adapter->res.max_vlans) |
542 | #define be_max_uc(adapter) (adapter->res.max_uc_mac) | |
543 | #define be_max_mc(adapter) (adapter->res.max_mcast_mac) | |
bec84e6b | 544 | #define be_max_vfs(adapter) (adapter->pool_res.max_vfs) |
92bf14ab SP |
545 | #define be_max_rss(adapter) (adapter->res.max_rss_qs) |
546 | #define be_max_txqs(adapter) (adapter->res.max_tx_qs) | |
547 | #define be_max_prio_txqs(adapter) (adapter->res.max_prio_tx_qs) | |
548 | #define be_max_rxqs(adapter) (adapter->res.max_rx_qs) | |
549 | #define be_max_eqs(adapter) (adapter->res.max_evt_qs) | |
550 | #define be_if_cap_flags(adapter) (adapter->res.if_cap_flags) | |
551 | ||
552 | static inline u16 be_max_qs(struct be_adapter *adapter) | |
553 | { | |
554 | /* If no RSS, need atleast the one def RXQ */ | |
555 | u16 num = max_t(u16, be_max_rss(adapter), 1); | |
556 | ||
557 | num = min(num, be_max_eqs(adapter)); | |
558 | return min_t(u16, num, num_online_cpus()); | |
559 | } | |
560 | ||
f93f160b VV |
561 | /* Is BE in pvid_tagging mode */ |
562 | #define be_pvid_tagging_enabled(adapter) (adapter->pvid) | |
563 | ||
564 | /* Is BE in QNQ multi-channel mode */ | |
66064dbc | 565 | #define be_is_qnq_mode(adapter) (adapter->function_mode & QNQ_MODE) |
f93f160b | 566 | |
ca34fe38 SP |
567 | #define lancer_chip(adapter) (adapter->pdev->device == OC_DEVICE_ID3 || \ |
568 | adapter->pdev->device == OC_DEVICE_ID4) | |
fe6d2a38 | 569 | |
76b73530 PR |
570 | #define skyhawk_chip(adapter) (adapter->pdev->device == OC_DEVICE_ID5 || \ |
571 | adapter->pdev->device == OC_DEVICE_ID6) | |
d3bd3a5e | 572 | |
ca34fe38 SP |
573 | #define BE3_chip(adapter) (adapter->pdev->device == BE_DEVICE_ID2 || \ |
574 | adapter->pdev->device == OC_DEVICE_ID2) | |
575 | ||
576 | #define BE2_chip(adapter) (adapter->pdev->device == BE_DEVICE_ID1 || \ | |
577 | adapter->pdev->device == OC_DEVICE_ID1) | |
578 | ||
579 | #define BEx_chip(adapter) (BE3_chip(adapter) || BE2_chip(adapter)) | |
d3bd3a5e | 580 | |
dbf0f2a7 SP |
581 | #define be_roce_supported(adapter) (skyhawk_chip(adapter) && \ |
582 | (adapter->function_mode & RDMA_ENABLED)) | |
045508a8 | 583 | |
0fc0b732 | 584 | extern const struct ethtool_ops be_ethtool_ops; |
6b7c5b94 | 585 | |
ac6a0c4a | 586 | #define msix_enabled(adapter) (adapter->num_msix_vec > 0) |
10ef9ab4 SP |
587 | #define num_irqs(adapter) (msix_enabled(adapter) ? \ |
588 | adapter->num_msix_vec : 1) | |
589 | #define tx_stats(txo) (&(txo)->stats) | |
590 | #define rx_stats(rxo) (&(rxo)->stats) | |
6b7c5b94 | 591 | |
10ef9ab4 SP |
592 | /* The default RXQ is the last RXQ */ |
593 | #define default_rxo(adpt) (&adpt->rx_obj[adpt->num_rx_qs - 1]) | |
6b7c5b94 | 594 | |
3abcdeda SP |
595 | #define for_all_rx_queues(adapter, rxo, i) \ |
596 | for (i = 0, rxo = &adapter->rx_obj[i]; i < adapter->num_rx_qs; \ | |
597 | i++, rxo++) | |
598 | ||
10ef9ab4 | 599 | /* Skip the default non-rss queue (last one)*/ |
3abcdeda | 600 | #define for_all_rss_queues(adapter, rxo, i) \ |
10ef9ab4 | 601 | for (i = 0, rxo = &adapter->rx_obj[i]; i < (adapter->num_rx_qs - 1);\ |
3abcdeda SP |
602 | i++, rxo++) |
603 | ||
3c8def97 SP |
604 | #define for_all_tx_queues(adapter, txo, i) \ |
605 | for (i = 0, txo = &adapter->tx_obj[i]; i < adapter->num_tx_qs; \ | |
606 | i++, txo++) | |
607 | ||
10ef9ab4 SP |
608 | #define for_all_evt_queues(adapter, eqo, i) \ |
609 | for (i = 0, eqo = &adapter->eq_obj[i]; i < adapter->num_evt_qs; \ | |
610 | i++, eqo++) | |
611 | ||
6384a4d0 SP |
612 | #define for_all_rx_queues_on_eq(adapter, eqo, rxo, i) \ |
613 | for (i = eqo->idx, rxo = &adapter->rx_obj[i]; i < adapter->num_rx_qs;\ | |
614 | i += adapter->num_evt_qs, rxo += adapter->num_evt_qs) | |
615 | ||
a4906ea0 SP |
616 | #define for_all_tx_queues_on_eq(adapter, eqo, txo, i) \ |
617 | for (i = eqo->idx, txo = &adapter->tx_obj[i]; i < adapter->num_tx_qs;\ | |
618 | i += adapter->num_evt_qs, txo += adapter->num_evt_qs) | |
619 | ||
10ef9ab4 SP |
620 | #define is_mcc_eqo(eqo) (eqo->idx == 0) |
621 | #define mcc_eqo(adapter) (&adapter->eq_obj[0]) | |
622 | ||
6b7c5b94 SP |
623 | #define PAGE_SHIFT_4K 12 |
624 | #define PAGE_SIZE_4K (1 << PAGE_SHIFT_4K) | |
625 | ||
626 | /* Returns number of pages spanned by the data starting at the given addr */ | |
627 | #define PAGES_4K_SPANNED(_address, size) \ | |
628 | ((u32)((((size_t)(_address) & (PAGE_SIZE_4K - 1)) + \ | |
629 | (size) + (PAGE_SIZE_4K - 1)) >> PAGE_SHIFT_4K)) | |
630 | ||
6b7c5b94 SP |
631 | /* Returns bit offset within a DWORD of a bitfield */ |
632 | #define AMAP_BIT_OFFSET(_struct, field) \ | |
633 | (((size_t)&(((_struct *)0)->field))%32) | |
634 | ||
635 | /* Returns the bit mask of the field that is NOT shifted into location. */ | |
636 | static inline u32 amap_mask(u32 bitsize) | |
637 | { | |
638 | return (bitsize == 32 ? 0xFFFFFFFF : (1 << bitsize) - 1); | |
639 | } | |
640 | ||
641 | static inline void | |
642 | amap_set(void *ptr, u32 dw_offset, u32 mask, u32 offset, u32 value) | |
643 | { | |
644 | u32 *dw = (u32 *) ptr + dw_offset; | |
645 | *dw &= ~(mask << offset); | |
646 | *dw |= (mask & value) << offset; | |
647 | } | |
648 | ||
649 | #define AMAP_SET_BITS(_struct, field, ptr, val) \ | |
650 | amap_set(ptr, \ | |
651 | offsetof(_struct, field)/32, \ | |
652 | amap_mask(sizeof(((_struct *)0)->field)), \ | |
653 | AMAP_BIT_OFFSET(_struct, field), \ | |
654 | val) | |
655 | ||
656 | static inline u32 amap_get(void *ptr, u32 dw_offset, u32 mask, u32 offset) | |
657 | { | |
658 | u32 *dw = (u32 *) ptr; | |
659 | return mask & (*(dw + dw_offset) >> offset); | |
660 | } | |
661 | ||
662 | #define AMAP_GET_BITS(_struct, field, ptr) \ | |
663 | amap_get(ptr, \ | |
664 | offsetof(_struct, field)/32, \ | |
665 | amap_mask(sizeof(((_struct *)0)->field)), \ | |
666 | AMAP_BIT_OFFSET(_struct, field)) | |
667 | ||
c3c18bc1 SP |
668 | #define GET_RX_COMPL_V0_BITS(field, ptr) \ |
669 | AMAP_GET_BITS(struct amap_eth_rx_compl_v0, field, ptr) | |
670 | ||
671 | #define GET_RX_COMPL_V1_BITS(field, ptr) \ | |
672 | AMAP_GET_BITS(struct amap_eth_rx_compl_v1, field, ptr) | |
673 | ||
674 | #define GET_TX_COMPL_BITS(field, ptr) \ | |
675 | AMAP_GET_BITS(struct amap_eth_tx_compl, field, ptr) | |
676 | ||
677 | #define SET_TX_WRB_HDR_BITS(field, ptr, val) \ | |
678 | AMAP_SET_BITS(struct amap_eth_hdr_wrb, field, ptr, val) | |
679 | ||
6b7c5b94 SP |
680 | #define be_dws_cpu_to_le(wrb, len) swap_dws(wrb, len) |
681 | #define be_dws_le_to_cpu(wrb, len) swap_dws(wrb, len) | |
682 | static inline void swap_dws(void *wrb, int len) | |
683 | { | |
684 | #ifdef __BIG_ENDIAN | |
685 | u32 *dw = wrb; | |
686 | BUG_ON(len % 4); | |
687 | do { | |
688 | *dw = cpu_to_le32(*dw); | |
689 | dw++; | |
690 | len -= 4; | |
691 | } while (len); | |
692 | #endif /* __BIG_ENDIAN */ | |
693 | } | |
694 | ||
0532d4e3 KA |
695 | #define be_cmd_status(status) (status > 0 ? -EIO : status) |
696 | ||
6b7c5b94 SP |
697 | static inline u8 is_tcp_pkt(struct sk_buff *skb) |
698 | { | |
699 | u8 val = 0; | |
700 | ||
701 | if (ip_hdr(skb)->version == 4) | |
702 | val = (ip_hdr(skb)->protocol == IPPROTO_TCP); | |
703 | else if (ip_hdr(skb)->version == 6) | |
704 | val = (ipv6_hdr(skb)->nexthdr == NEXTHDR_TCP); | |
705 | ||
706 | return val; | |
707 | } | |
708 | ||
709 | static inline u8 is_udp_pkt(struct sk_buff *skb) | |
710 | { | |
711 | u8 val = 0; | |
712 | ||
713 | if (ip_hdr(skb)->version == 4) | |
714 | val = (ip_hdr(skb)->protocol == IPPROTO_UDP); | |
715 | else if (ip_hdr(skb)->version == 6) | |
716 | val = (ipv6_hdr(skb)->nexthdr == NEXTHDR_UDP); | |
717 | ||
718 | return val; | |
719 | } | |
720 | ||
93040ae5 SK |
721 | static inline bool is_ipv4_pkt(struct sk_buff *skb) |
722 | { | |
e8efcec5 | 723 | return skb->protocol == htons(ETH_P_IP) && ip_hdr(skb)->version == 4; |
93040ae5 SK |
724 | } |
725 | ||
4b972914 AK |
726 | static inline bool be_multi_rxq(const struct be_adapter *adapter) |
727 | { | |
728 | return adapter->num_rx_qs > 1; | |
729 | } | |
730 | ||
6589ade0 SP |
731 | static inline bool be_error(struct be_adapter *adapter) |
732 | { | |
f67ef7ba PR |
733 | return adapter->eeh_error || adapter->hw_error || adapter->fw_timeout; |
734 | } | |
735 | ||
d23e946c | 736 | static inline bool be_hw_error(struct be_adapter *adapter) |
f67ef7ba PR |
737 | { |
738 | return adapter->eeh_error || adapter->hw_error; | |
739 | } | |
740 | ||
741 | static inline void be_clear_all_error(struct be_adapter *adapter) | |
742 | { | |
743 | adapter->eeh_error = false; | |
744 | adapter->hw_error = false; | |
745 | adapter->fw_timeout = false; | |
6589ade0 SP |
746 | } |
747 | ||
31886e87 JP |
748 | void be_cq_notify(struct be_adapter *adapter, u16 qid, bool arm, |
749 | u16 num_popped); | |
750 | void be_link_status_update(struct be_adapter *adapter, u8 link_status); | |
751 | void be_parse_stats(struct be_adapter *adapter); | |
752 | int be_load_fw(struct be_adapter *adapter, u8 *func); | |
753 | bool be_is_wol_supported(struct be_adapter *adapter); | |
754 | bool be_pause_supported(struct be_adapter *adapter); | |
755 | u32 be_get_fw_log_level(struct be_adapter *adapter); | |
68d7bdcb SP |
756 | int be_update_queues(struct be_adapter *adapter); |
757 | int be_poll(struct napi_struct *napi, int budget); | |
941a77d5 | 758 | |
045508a8 PP |
759 | /* |
760 | * internal function to initialize-cleanup roce device. | |
761 | */ | |
31886e87 JP |
762 | void be_roce_dev_add(struct be_adapter *); |
763 | void be_roce_dev_remove(struct be_adapter *); | |
045508a8 PP |
764 | |
765 | /* | |
766 | * internal function to open-close roce device during ifup-ifdown. | |
767 | */ | |
31886e87 JP |
768 | void be_roce_dev_open(struct be_adapter *); |
769 | void be_roce_dev_close(struct be_adapter *); | |
d114f99a | 770 | void be_roce_dev_shutdown(struct be_adapter *); |
045508a8 | 771 | |
6b7c5b94 | 772 | #endif /* BE_H */ |