Commit | Line | Data |
---|---|---|
6b7c5b94 | 1 | /* |
d2145cde | 2 | * Copyright (C) 2005 - 2011 Emulex |
6b7c5b94 SP |
3 | * All rights reserved. |
4 | * | |
5 | * This program is free software; you can redistribute it and/or | |
6 | * modify it under the terms of the GNU General Public License version 2 | |
7 | * as published by the Free Software Foundation. The full GNU General | |
8 | * Public License is included in this distribution in the file called COPYING. | |
9 | * | |
10 | * Contact Information: | |
d2145cde | 11 | * linux-drivers@emulex.com |
6b7c5b94 | 12 | * |
d2145cde AK |
13 | * Emulex |
14 | * 3333 Susan Street | |
15 | * Costa Mesa, CA 92626 | |
6b7c5b94 SP |
16 | */ |
17 | ||
18 | #ifndef BE_H | |
19 | #define BE_H | |
20 | ||
21 | #include <linux/pci.h> | |
22 | #include <linux/etherdevice.h> | |
6b7c5b94 SP |
23 | #include <linux/delay.h> |
24 | #include <net/tcp.h> | |
25 | #include <net/ip.h> | |
26 | #include <net/ipv6.h> | |
27 | #include <linux/if_vlan.h> | |
28 | #include <linux/workqueue.h> | |
29 | #include <linux/interrupt.h> | |
84517482 | 30 | #include <linux/firmware.h> |
5a0e3ad6 | 31 | #include <linux/slab.h> |
ab1594e9 | 32 | #include <linux/u64_stats_sync.h> |
6b7c5b94 SP |
33 | |
34 | #include "be_hw.h" | |
35 | ||
d708f603 | 36 | #define DRV_VER "4.2.116u" |
6b7c5b94 SP |
37 | #define DRV_NAME "be2net" |
38 | #define BE_NAME "ServerEngines BladeEngine2 10Gbps NIC" | |
12d7ea2c | 39 | #define BE3_NAME "ServerEngines BladeEngine3 10Gbps NIC" |
c4ca2374 | 40 | #define OC_NAME "Emulex OneConnect 10Gbps NIC" |
fe6d2a38 SP |
41 | #define OC_NAME_BE OC_NAME "(be3)" |
42 | #define OC_NAME_LANCER OC_NAME "(Lancer)" | |
ecedb6ae | 43 | #define OC_NAME_SH OC_NAME "(Skyhawk)" |
35ecf03c | 44 | #define DRV_DESC "ServerEngines BladeEngine 10Gbps NIC Driver" |
6b7c5b94 | 45 | |
c4ca2374 | 46 | #define BE_VENDOR_ID 0x19a2 |
fe6d2a38 | 47 | #define EMULEX_VENDOR_ID 0x10df |
c4ca2374 | 48 | #define BE_DEVICE_ID1 0x211 |
12d7ea2c | 49 | #define BE_DEVICE_ID2 0x221 |
fe6d2a38 SP |
50 | #define OC_DEVICE_ID1 0x700 /* Device Id for BE2 cards */ |
51 | #define OC_DEVICE_ID2 0x710 /* Device Id for BE3 cards */ | |
52 | #define OC_DEVICE_ID3 0xe220 /* Device id for Lancer cards */ | |
12f4d0a8 | 53 | #define OC_DEVICE_ID4 0xe228 /* Device id for VF in Lancer */ |
ecedb6ae | 54 | #define OC_DEVICE_ID5 0x720 /* Device Id for Skyhawk cards */ |
4762f6ce AK |
55 | #define OC_SUBSYS_DEVICE_ID1 0xE602 |
56 | #define OC_SUBSYS_DEVICE_ID2 0xE642 | |
57 | #define OC_SUBSYS_DEVICE_ID3 0xE612 | |
58 | #define OC_SUBSYS_DEVICE_ID4 0xE652 | |
c4ca2374 AK |
59 | |
60 | static inline char *nic_name(struct pci_dev *pdev) | |
61 | { | |
12d7ea2c AK |
62 | switch (pdev->device) { |
63 | case OC_DEVICE_ID1: | |
c4ca2374 | 64 | return OC_NAME; |
e254f6ec | 65 | case OC_DEVICE_ID2: |
fe6d2a38 SP |
66 | return OC_NAME_BE; |
67 | case OC_DEVICE_ID3: | |
12f4d0a8 | 68 | case OC_DEVICE_ID4: |
fe6d2a38 | 69 | return OC_NAME_LANCER; |
12d7ea2c AK |
70 | case BE_DEVICE_ID2: |
71 | return BE3_NAME; | |
ecedb6ae AK |
72 | case OC_DEVICE_ID5: |
73 | return OC_NAME_SH; | |
12d7ea2c | 74 | default: |
c4ca2374 | 75 | return BE_NAME; |
12d7ea2c | 76 | } |
c4ca2374 AK |
77 | } |
78 | ||
6b7c5b94 | 79 | /* Number of bytes of an RX frame that are copied to skb->data */ |
2e588f84 | 80 | #define BE_HDR_LEN ((u16) 64) |
bb349bb4 ED |
81 | /* allocate extra space to allow tunneling decapsulation without head reallocation */ |
82 | #define BE_RX_SKB_ALLOC_SIZE (BE_HDR_LEN + 64) | |
83 | ||
6b7c5b94 SP |
84 | #define BE_MAX_JUMBO_FRAME_SIZE 9018 |
85 | #define BE_MIN_MTU 256 | |
86 | ||
87 | #define BE_NUM_VLANS_SUPPORTED 64 | |
10ef9ab4 | 88 | #define BE_MAX_EQD 96u |
6b7c5b94 SP |
89 | #define BE_MAX_TX_FRAG_COUNT 30 |
90 | ||
91 | #define EVNT_Q_LEN 1024 | |
92 | #define TX_Q_LEN 2048 | |
93 | #define TX_CQ_LEN 1024 | |
94 | #define RX_Q_LEN 1024 /* Does not support any other value */ | |
95 | #define RX_CQ_LEN 1024 | |
5fb379ee | 96 | #define MCC_Q_LEN 128 /* total size not to exceed 8 pages */ |
6b7c5b94 SP |
97 | #define MCC_CQ_LEN 256 |
98 | ||
10ef9ab4 SP |
99 | #define BE3_MAX_RSS_QS 8 |
100 | #define BE2_MAX_RSS_QS 4 | |
101 | #define MAX_RSS_QS BE3_MAX_RSS_QS | |
ac6a0c4a | 102 | #define MAX_RX_QS (MAX_RSS_QS + 1) /* RSS qs + 1 def Rx */ |
10ef9ab4 | 103 | |
3c8def97 | 104 | #define MAX_TX_QS 8 |
10ef9ab4 SP |
105 | #define MAX_MSIX_VECTORS MAX_RSS_QS |
106 | #define BE_TX_BUDGET 256 | |
6b7c5b94 | 107 | #define BE_NAPI_WEIGHT 64 |
10ef9ab4 | 108 | #define MAX_RX_POST BE_NAPI_WEIGHT /* Frags posted at a time */ |
6b7c5b94 SP |
109 | #define RX_FRAGS_REFILL_WM (RX_Q_LEN - MAX_RX_POST) |
110 | ||
8788fdc2 SP |
111 | #define FW_VER_LEN 32 |
112 | ||
6b7c5b94 SP |
113 | struct be_dma_mem { |
114 | void *va; | |
115 | dma_addr_t dma; | |
116 | u32 size; | |
117 | }; | |
118 | ||
119 | struct be_queue_info { | |
120 | struct be_dma_mem dma_mem; | |
121 | u16 len; | |
122 | u16 entry_size; /* Size of an element in the queue */ | |
123 | u16 id; | |
124 | u16 tail, head; | |
125 | bool created; | |
126 | atomic_t used; /* Number of valid elements in the queue */ | |
127 | }; | |
128 | ||
5fb379ee SP |
129 | static inline u32 MODULO(u16 val, u16 limit) |
130 | { | |
131 | BUG_ON(limit & (limit - 1)); | |
132 | return val & (limit - 1); | |
133 | } | |
134 | ||
135 | static inline void index_adv(u16 *index, u16 val, u16 limit) | |
136 | { | |
137 | *index = MODULO((*index + val), limit); | |
138 | } | |
139 | ||
140 | static inline void index_inc(u16 *index, u16 limit) | |
141 | { | |
142 | *index = MODULO((*index + 1), limit); | |
143 | } | |
144 | ||
145 | static inline void *queue_head_node(struct be_queue_info *q) | |
146 | { | |
147 | return q->dma_mem.va + q->head * q->entry_size; | |
148 | } | |
149 | ||
150 | static inline void *queue_tail_node(struct be_queue_info *q) | |
151 | { | |
152 | return q->dma_mem.va + q->tail * q->entry_size; | |
153 | } | |
154 | ||
3de09455 SK |
155 | static inline void *queue_index_node(struct be_queue_info *q, u16 index) |
156 | { | |
157 | return q->dma_mem.va + index * q->entry_size; | |
158 | } | |
159 | ||
5fb379ee SP |
160 | static inline void queue_head_inc(struct be_queue_info *q) |
161 | { | |
162 | index_inc(&q->head, q->len); | |
163 | } | |
164 | ||
165 | static inline void queue_tail_inc(struct be_queue_info *q) | |
166 | { | |
167 | index_inc(&q->tail, q->len); | |
168 | } | |
169 | ||
5fb379ee SP |
170 | struct be_eq_obj { |
171 | struct be_queue_info q; | |
172 | char desc[32]; | |
173 | ||
174 | /* Adaptive interrupt coalescing (AIC) info */ | |
175 | bool enable_aic; | |
10ef9ab4 SP |
176 | u32 min_eqd; /* in usecs */ |
177 | u32 max_eqd; /* in usecs */ | |
178 | u32 eqd; /* configured val when aic is off */ | |
179 | u32 cur_eqd; /* in usecs */ | |
5fb379ee | 180 | |
10ef9ab4 SP |
181 | u8 idx; /* array index */ |
182 | u16 tx_budget; | |
5fb379ee | 183 | struct napi_struct napi; |
10ef9ab4 SP |
184 | struct be_adapter *adapter; |
185 | } ____cacheline_aligned_in_smp; | |
5fb379ee SP |
186 | |
187 | struct be_mcc_obj { | |
188 | struct be_queue_info q; | |
189 | struct be_queue_info cq; | |
7a1e9b20 | 190 | bool rearm_cq; |
5fb379ee SP |
191 | }; |
192 | ||
3abcdeda | 193 | struct be_tx_stats { |
ac124ff9 SP |
194 | u64 tx_bytes; |
195 | u64 tx_pkts; | |
196 | u64 tx_reqs; | |
197 | u64 tx_wrbs; | |
198 | u64 tx_compl; | |
199 | ulong tx_jiffies; | |
200 | u32 tx_stops; | |
ab1594e9 SP |
201 | struct u64_stats_sync sync; |
202 | struct u64_stats_sync sync_compl; | |
6b7c5b94 SP |
203 | }; |
204 | ||
6b7c5b94 SP |
205 | struct be_tx_obj { |
206 | struct be_queue_info q; | |
207 | struct be_queue_info cq; | |
208 | /* Remember the skbs that were transmitted */ | |
209 | struct sk_buff *sent_skb_list[TX_Q_LEN]; | |
3c8def97 | 210 | struct be_tx_stats stats; |
10ef9ab4 | 211 | } ____cacheline_aligned_in_smp; |
6b7c5b94 SP |
212 | |
213 | /* Struct to remember the pages posted for rx frags */ | |
214 | struct be_rx_page_info { | |
215 | struct page *page; | |
fac6da5b | 216 | DEFINE_DMA_UNMAP_ADDR(bus); |
6b7c5b94 SP |
217 | u16 page_offset; |
218 | bool last_page_user; | |
219 | }; | |
220 | ||
3abcdeda | 221 | struct be_rx_stats { |
3abcdeda | 222 | u64 rx_bytes; |
3abcdeda | 223 | u64 rx_pkts; |
ac124ff9 SP |
224 | u64 rx_pkts_prev; |
225 | ulong rx_jiffies; | |
226 | u32 rx_drops_no_skbs; /* skb allocation errors */ | |
227 | u32 rx_drops_no_frags; /* HW has no fetched frags */ | |
228 | u32 rx_post_fail; /* page post alloc failures */ | |
ac124ff9 | 229 | u32 rx_compl; |
3abcdeda | 230 | u32 rx_mcast_pkts; |
ac124ff9 SP |
231 | u32 rx_compl_err; /* completions with err set */ |
232 | u32 rx_pps; /* pkts per second */ | |
ab1594e9 | 233 | struct u64_stats_sync sync; |
3abcdeda SP |
234 | }; |
235 | ||
2e588f84 SP |
236 | struct be_rx_compl_info { |
237 | u32 rss_hash; | |
6709d952 | 238 | u16 vlan_tag; |
2e588f84 SP |
239 | u16 pkt_size; |
240 | u16 rxq_idx; | |
12004ae9 | 241 | u16 port; |
2e588f84 SP |
242 | u8 vlanf; |
243 | u8 num_rcvd; | |
244 | u8 err; | |
245 | u8 ipf; | |
246 | u8 tcpf; | |
247 | u8 udpf; | |
248 | u8 ip_csum; | |
249 | u8 l4_csum; | |
250 | u8 ipv6; | |
251 | u8 vtm; | |
252 | u8 pkt_type; | |
253 | }; | |
254 | ||
6b7c5b94 | 255 | struct be_rx_obj { |
3abcdeda | 256 | struct be_adapter *adapter; |
6b7c5b94 SP |
257 | struct be_queue_info q; |
258 | struct be_queue_info cq; | |
2e588f84 | 259 | struct be_rx_compl_info rxcp; |
6b7c5b94 | 260 | struct be_rx_page_info page_info_tbl[RX_Q_LEN]; |
3abcdeda SP |
261 | struct be_rx_stats stats; |
262 | u8 rss_id; | |
263 | bool rx_post_starved; /* Zero rx frags have been posted to BE */ | |
10ef9ab4 | 264 | } ____cacheline_aligned_in_smp; |
6b7c5b94 | 265 | |
609ff3bb | 266 | struct be_drv_stats { |
9ae081c6 | 267 | u32 be_on_die_temperature; |
ac124ff9 SP |
268 | u32 eth_red_drops; |
269 | u32 rx_drops_no_pbuf; | |
270 | u32 rx_drops_no_txpb; | |
271 | u32 rx_drops_no_erx_descr; | |
272 | u32 rx_drops_no_tpre_descr; | |
273 | u32 rx_drops_too_many_frags; | |
ac124ff9 SP |
274 | u32 forwarded_packets; |
275 | u32 rx_drops_mtu; | |
276 | u32 rx_crc_errors; | |
277 | u32 rx_alignment_symbol_errors; | |
278 | u32 rx_pause_frames; | |
279 | u32 rx_priority_pause_frames; | |
280 | u32 rx_control_frames; | |
281 | u32 rx_in_range_errors; | |
282 | u32 rx_out_range_errors; | |
283 | u32 rx_frame_too_long; | |
d45b9d39 | 284 | u32 rx_address_mismatch_drops; |
ac124ff9 SP |
285 | u32 rx_dropped_too_small; |
286 | u32 rx_dropped_too_short; | |
287 | u32 rx_dropped_header_too_small; | |
288 | u32 rx_dropped_tcp_length; | |
289 | u32 rx_dropped_runt; | |
290 | u32 rx_ip_checksum_errs; | |
291 | u32 rx_tcp_checksum_errs; | |
292 | u32 rx_udp_checksum_errs; | |
293 | u32 tx_pauseframes; | |
294 | u32 tx_priority_pauseframes; | |
295 | u32 tx_controlframes; | |
296 | u32 rxpp_fifo_overflow_drop; | |
297 | u32 rx_input_fifo_overflow_drop; | |
298 | u32 pmem_fifo_overflow_drop; | |
299 | u32 jabber_events; | |
609ff3bb AK |
300 | }; |
301 | ||
64600ea5 | 302 | struct be_vf_cfg { |
11ac75ed SP |
303 | unsigned char mac_addr[ETH_ALEN]; |
304 | int if_handle; | |
305 | int pmac_id; | |
306 | u16 vlan_tag; | |
307 | u32 tx_rate; | |
64600ea5 AK |
308 | }; |
309 | ||
b236916a | 310 | #define BE_FLAGS_LINK_STATUS_INIT 1 |
191eb756 | 311 | #define BE_FLAGS_WORKER_SCHEDULED (1 << 3) |
b236916a | 312 | |
6b7c5b94 SP |
313 | struct be_adapter { |
314 | struct pci_dev *pdev; | |
315 | struct net_device *netdev; | |
316 | ||
8788fdc2 SP |
317 | u8 __iomem *csr; |
318 | u8 __iomem *db; /* Door Bell */ | |
8788fdc2 | 319 | |
2984961c | 320 | struct mutex mbox_lock; /* For serializing mbox cmds to BE card */ |
8788fdc2 SP |
321 | struct be_dma_mem mbox_mem; |
322 | /* Mbox mem is adjusted to align to 16 bytes. The allocated addr | |
323 | * is stored for freeing purpose */ | |
324 | struct be_dma_mem mbox_mem_alloced; | |
325 | ||
326 | struct be_mcc_obj mcc_obj; | |
327 | spinlock_t mcc_lock; /* For serializing mcc cmds to BE card */ | |
328 | spinlock_t mcc_cq_lock; | |
6b7c5b94 | 329 | |
ac6a0c4a | 330 | u32 num_msix_vec; |
10ef9ab4 SP |
331 | u32 num_evt_qs; |
332 | struct be_eq_obj eq_obj[MAX_MSIX_VECTORS]; | |
333 | struct msix_entry msix_entries[MAX_MSIX_VECTORS]; | |
6b7c5b94 SP |
334 | bool isr_registered; |
335 | ||
336 | /* TX Rings */ | |
10ef9ab4 | 337 | u32 num_tx_qs; |
3c8def97 | 338 | struct be_tx_obj tx_obj[MAX_TX_QS]; |
6b7c5b94 SP |
339 | |
340 | /* Rx rings */ | |
3abcdeda | 341 | u32 num_rx_qs; |
10ef9ab4 | 342 | struct be_rx_obj rx_obj[MAX_RX_QS]; |
6b7c5b94 SP |
343 | u32 big_page_size; /* Compounded page size shared by rx wrbs */ |
344 | ||
ecd62107 | 345 | u8 eq_next_idx; |
609ff3bb | 346 | struct be_drv_stats drv_stats; |
fe6d2a38 | 347 | |
82903e4b AK |
348 | u16 vlans_added; |
349 | u16 max_vlans; /* Number of vlans supported */ | |
b738127d | 350 | u8 vlan_tag[VLAN_N_VID]; |
cc4ce020 SK |
351 | u8 vlan_prio_bmap; /* Available Priority BitMap */ |
352 | u16 recommended_prio; /* Recommended Priority */ | |
5b8821b7 | 353 | struct be_dma_mem rx_filter; /* Cmd DMA mem for rx-filter */ |
6b7c5b94 | 354 | |
3abcdeda | 355 | struct be_dma_mem stats_cmd; |
6b7c5b94 SP |
356 | /* Work queue used to perform periodic tasks like getting statistics */ |
357 | struct delayed_work work; | |
609ff3bb | 358 | u16 work_counter; |
6b7c5b94 | 359 | |
b236916a | 360 | u32 flags; |
6b7c5b94 | 361 | /* Ethtool knobs and info */ |
6b7c5b94 | 362 | char fw_ver[FW_VER_LEN]; |
30128031 | 363 | int if_handle; /* Used to configure filtering */ |
6b7c5b94 | 364 | u32 pmac_id; /* MAC addr handle used by BE card */ |
1a642469 | 365 | u32 beacon_state; /* for set_phys_id */ |
6b7c5b94 | 366 | |
cf588477 | 367 | bool eeh_err; |
6589ade0 SP |
368 | bool ue_detected; |
369 | bool fw_timeout; | |
6b7c5b94 | 370 | u32 port_num; |
24307eef | 371 | bool promiscuous; |
3486be29 | 372 | u32 function_mode; |
3abcdeda | 373 | u32 function_caps; |
9e90c961 AK |
374 | u32 rx_fc; /* Rx flow control */ |
375 | u32 tx_fc; /* Tx flow control */ | |
b2aebe6d | 376 | bool stats_cmd_sent; |
0dffc83e AK |
377 | int link_speed; |
378 | u8 port_type; | |
16c02145 | 379 | u8 transceiver; |
ee3cb629 | 380 | u8 autoneg; |
7b139c83 | 381 | u8 generation; /* BladeEngine ASIC generation */ |
dd131e76 SB |
382 | u32 flash_status; |
383 | struct completion flash_compl; | |
ba343c77 | 384 | |
11ac75ed | 385 | u32 num_vfs; |
344dbf10 | 386 | u8 is_virtfn; |
11ac75ed SP |
387 | struct be_vf_cfg *vf_cfg; |
388 | bool be3_native; | |
fe6d2a38 | 389 | u32 sli_family; |
9e1453c5 | 390 | u8 hba_port_num; |
3968fa1e | 391 | u16 pvid; |
4762f6ce AK |
392 | u8 wol_cap; |
393 | bool wol; | |
6b7c5b94 SP |
394 | }; |
395 | ||
344dbf10 | 396 | #define be_physfn(adapter) (!adapter->is_virtfn) |
11ac75ed SP |
397 | #define sriov_enabled(adapter) (adapter->num_vfs > 0) |
398 | #define for_all_vfs(adapter, vf_cfg, i) \ | |
399 | for (i = 0, vf_cfg = &adapter->vf_cfg[i]; i < adapter->num_vfs; \ | |
400 | i++, vf_cfg++) | |
ba343c77 | 401 | |
7b139c83 AK |
402 | /* BladeEngine Generation numbers */ |
403 | #define BE_GEN2 2 | |
404 | #define BE_GEN3 3 | |
405 | ||
5b8821b7 SP |
406 | #define ON 1 |
407 | #define OFF 0 | |
12f4d0a8 ME |
408 | #define lancer_chip(adapter) ((adapter->pdev->device == OC_DEVICE_ID3) || \ |
409 | (adapter->pdev->device == OC_DEVICE_ID4)) | |
fe6d2a38 | 410 | |
0fc0b732 | 411 | extern const struct ethtool_ops be_ethtool_ops; |
6b7c5b94 | 412 | |
ac6a0c4a | 413 | #define msix_enabled(adapter) (adapter->num_msix_vec > 0) |
10ef9ab4 SP |
414 | #define num_irqs(adapter) (msix_enabled(adapter) ? \ |
415 | adapter->num_msix_vec : 1) | |
416 | #define tx_stats(txo) (&(txo)->stats) | |
417 | #define rx_stats(rxo) (&(rxo)->stats) | |
6b7c5b94 | 418 | |
10ef9ab4 SP |
419 | /* The default RXQ is the last RXQ */ |
420 | #define default_rxo(adpt) (&adpt->rx_obj[adpt->num_rx_qs - 1]) | |
6b7c5b94 | 421 | |
3abcdeda SP |
422 | #define for_all_rx_queues(adapter, rxo, i) \ |
423 | for (i = 0, rxo = &adapter->rx_obj[i]; i < adapter->num_rx_qs; \ | |
424 | i++, rxo++) | |
425 | ||
10ef9ab4 | 426 | /* Skip the default non-rss queue (last one)*/ |
3abcdeda | 427 | #define for_all_rss_queues(adapter, rxo, i) \ |
10ef9ab4 | 428 | for (i = 0, rxo = &adapter->rx_obj[i]; i < (adapter->num_rx_qs - 1);\ |
3abcdeda SP |
429 | i++, rxo++) |
430 | ||
3c8def97 SP |
431 | #define for_all_tx_queues(adapter, txo, i) \ |
432 | for (i = 0, txo = &adapter->tx_obj[i]; i < adapter->num_tx_qs; \ | |
433 | i++, txo++) | |
434 | ||
10ef9ab4 SP |
435 | #define for_all_evt_queues(adapter, eqo, i) \ |
436 | for (i = 0, eqo = &adapter->eq_obj[i]; i < adapter->num_evt_qs; \ | |
437 | i++, eqo++) | |
438 | ||
439 | #define is_mcc_eqo(eqo) (eqo->idx == 0) | |
440 | #define mcc_eqo(adapter) (&adapter->eq_obj[0]) | |
441 | ||
6b7c5b94 SP |
442 | #define PAGE_SHIFT_4K 12 |
443 | #define PAGE_SIZE_4K (1 << PAGE_SHIFT_4K) | |
444 | ||
445 | /* Returns number of pages spanned by the data starting at the given addr */ | |
446 | #define PAGES_4K_SPANNED(_address, size) \ | |
447 | ((u32)((((size_t)(_address) & (PAGE_SIZE_4K - 1)) + \ | |
448 | (size) + (PAGE_SIZE_4K - 1)) >> PAGE_SHIFT_4K)) | |
449 | ||
6b7c5b94 SP |
450 | /* Returns bit offset within a DWORD of a bitfield */ |
451 | #define AMAP_BIT_OFFSET(_struct, field) \ | |
452 | (((size_t)&(((_struct *)0)->field))%32) | |
453 | ||
454 | /* Returns the bit mask of the field that is NOT shifted into location. */ | |
455 | static inline u32 amap_mask(u32 bitsize) | |
456 | { | |
457 | return (bitsize == 32 ? 0xFFFFFFFF : (1 << bitsize) - 1); | |
458 | } | |
459 | ||
460 | static inline void | |
461 | amap_set(void *ptr, u32 dw_offset, u32 mask, u32 offset, u32 value) | |
462 | { | |
463 | u32 *dw = (u32 *) ptr + dw_offset; | |
464 | *dw &= ~(mask << offset); | |
465 | *dw |= (mask & value) << offset; | |
466 | } | |
467 | ||
468 | #define AMAP_SET_BITS(_struct, field, ptr, val) \ | |
469 | amap_set(ptr, \ | |
470 | offsetof(_struct, field)/32, \ | |
471 | amap_mask(sizeof(((_struct *)0)->field)), \ | |
472 | AMAP_BIT_OFFSET(_struct, field), \ | |
473 | val) | |
474 | ||
475 | static inline u32 amap_get(void *ptr, u32 dw_offset, u32 mask, u32 offset) | |
476 | { | |
477 | u32 *dw = (u32 *) ptr; | |
478 | return mask & (*(dw + dw_offset) >> offset); | |
479 | } | |
480 | ||
481 | #define AMAP_GET_BITS(_struct, field, ptr) \ | |
482 | amap_get(ptr, \ | |
483 | offsetof(_struct, field)/32, \ | |
484 | amap_mask(sizeof(((_struct *)0)->field)), \ | |
485 | AMAP_BIT_OFFSET(_struct, field)) | |
486 | ||
487 | #define be_dws_cpu_to_le(wrb, len) swap_dws(wrb, len) | |
488 | #define be_dws_le_to_cpu(wrb, len) swap_dws(wrb, len) | |
489 | static inline void swap_dws(void *wrb, int len) | |
490 | { | |
491 | #ifdef __BIG_ENDIAN | |
492 | u32 *dw = wrb; | |
493 | BUG_ON(len % 4); | |
494 | do { | |
495 | *dw = cpu_to_le32(*dw); | |
496 | dw++; | |
497 | len -= 4; | |
498 | } while (len); | |
499 | #endif /* __BIG_ENDIAN */ | |
500 | } | |
501 | ||
502 | static inline u8 is_tcp_pkt(struct sk_buff *skb) | |
503 | { | |
504 | u8 val = 0; | |
505 | ||
506 | if (ip_hdr(skb)->version == 4) | |
507 | val = (ip_hdr(skb)->protocol == IPPROTO_TCP); | |
508 | else if (ip_hdr(skb)->version == 6) | |
509 | val = (ipv6_hdr(skb)->nexthdr == NEXTHDR_TCP); | |
510 | ||
511 | return val; | |
512 | } | |
513 | ||
514 | static inline u8 is_udp_pkt(struct sk_buff *skb) | |
515 | { | |
516 | u8 val = 0; | |
517 | ||
518 | if (ip_hdr(skb)->version == 4) | |
519 | val = (ip_hdr(skb)->protocol == IPPROTO_UDP); | |
520 | else if (ip_hdr(skb)->version == 6) | |
521 | val = (ipv6_hdr(skb)->nexthdr == NEXTHDR_UDP); | |
522 | ||
523 | return val; | |
524 | } | |
525 | ||
344dbf10 SB |
526 | static inline void be_check_sriov_fn_type(struct be_adapter *adapter) |
527 | { | |
fe6d2a38 SP |
528 | u32 sli_intf; |
529 | ||
b0060586 AK |
530 | pci_read_config_dword(adapter->pdev, SLI_INTF_REG_OFFSET, &sli_intf); |
531 | adapter->is_virtfn = (sli_intf & SLI_INTF_FT_MASK) ? 1 : 0; | |
344dbf10 SB |
532 | } |
533 | ||
6d87f5c3 AK |
534 | static inline void be_vf_eth_addr_generate(struct be_adapter *adapter, u8 *mac) |
535 | { | |
536 | u32 addr; | |
537 | ||
538 | addr = jhash(adapter->netdev->dev_addr, ETH_ALEN, 0); | |
539 | ||
540 | mac[5] = (u8)(addr & 0xFF); | |
541 | mac[4] = (u8)((addr >> 8) & 0xFF); | |
542 | mac[3] = (u8)((addr >> 16) & 0xFF); | |
7a2414a5 AK |
543 | /* Use the OUI from the current MAC address */ |
544 | memcpy(mac, adapter->netdev->dev_addr, 3); | |
6d87f5c3 AK |
545 | } |
546 | ||
4b972914 AK |
547 | static inline bool be_multi_rxq(const struct be_adapter *adapter) |
548 | { | |
549 | return adapter->num_rx_qs > 1; | |
550 | } | |
551 | ||
6589ade0 SP |
552 | static inline bool be_error(struct be_adapter *adapter) |
553 | { | |
554 | return adapter->eeh_err || adapter->ue_detected || adapter->fw_timeout; | |
555 | } | |
556 | ||
4762f6ce AK |
557 | static inline bool be_is_wol_excluded(struct be_adapter *adapter) |
558 | { | |
559 | struct pci_dev *pdev = adapter->pdev; | |
560 | ||
561 | if (!be_physfn(adapter)) | |
562 | return true; | |
563 | ||
564 | switch (pdev->subsystem_device) { | |
565 | case OC_SUBSYS_DEVICE_ID1: | |
566 | case OC_SUBSYS_DEVICE_ID2: | |
567 | case OC_SUBSYS_DEVICE_ID3: | |
568 | case OC_SUBSYS_DEVICE_ID4: | |
569 | return true; | |
570 | default: | |
571 | return false; | |
572 | } | |
573 | } | |
574 | ||
8788fdc2 | 575 | extern void be_cq_notify(struct be_adapter *adapter, u16 qid, bool arm, |
5fb379ee | 576 | u16 num_popped); |
b236916a | 577 | extern void be_link_status_update(struct be_adapter *adapter, u8 link_status); |
89a88ab8 | 578 | extern void be_parse_stats(struct be_adapter *adapter); |
84517482 | 579 | extern int be_load_fw(struct be_adapter *adapter, u8 *func); |
4762f6ce | 580 | extern bool be_is_wol_supported(struct be_adapter *adapter); |
6b7c5b94 | 581 | #endif /* BE_H */ |