Commit | Line | Data |
---|---|---|
6b7c5b94 | 1 | /* |
40263820 | 2 | * Copyright (C) 2005 - 2014 Emulex |
6b7c5b94 SP |
3 | * All rights reserved. |
4 | * | |
5 | * This program is free software; you can redistribute it and/or | |
6 | * modify it under the terms of the GNU General Public License version 2 | |
7 | * as published by the Free Software Foundation. The full GNU General | |
8 | * Public License is included in this distribution in the file called COPYING. | |
9 | * | |
10 | * Contact Information: | |
d2145cde | 11 | * linux-drivers@emulex.com |
6b7c5b94 | 12 | * |
d2145cde AK |
13 | * Emulex |
14 | * 3333 Susan Street | |
15 | * Costa Mesa, CA 92626 | |
6b7c5b94 SP |
16 | */ |
17 | ||
18 | #ifndef BE_H | |
19 | #define BE_H | |
20 | ||
21 | #include <linux/pci.h> | |
22 | #include <linux/etherdevice.h> | |
6b7c5b94 SP |
23 | #include <linux/delay.h> |
24 | #include <net/tcp.h> | |
25 | #include <net/ip.h> | |
26 | #include <net/ipv6.h> | |
27 | #include <linux/if_vlan.h> | |
28 | #include <linux/workqueue.h> | |
29 | #include <linux/interrupt.h> | |
84517482 | 30 | #include <linux/firmware.h> |
5a0e3ad6 | 31 | #include <linux/slab.h> |
ab1594e9 | 32 | #include <linux/u64_stats_sync.h> |
6b7c5b94 SP |
33 | |
34 | #include "be_hw.h" | |
045508a8 | 35 | #include "be_roce.h" |
6b7c5b94 | 36 | |
c346e6e5 | 37 | #define DRV_VER "10.4u" |
6b7c5b94 | 38 | #define DRV_NAME "be2net" |
00d3d51e SB |
39 | #define BE_NAME "Emulex BladeEngine2" |
40 | #define BE3_NAME "Emulex BladeEngine3" | |
41 | #define OC_NAME "Emulex OneConnect" | |
fe6d2a38 SP |
42 | #define OC_NAME_BE OC_NAME "(be3)" |
43 | #define OC_NAME_LANCER OC_NAME "(Lancer)" | |
ecedb6ae | 44 | #define OC_NAME_SH OC_NAME "(Skyhawk)" |
f3effb45 | 45 | #define DRV_DESC "Emulex OneConnect NIC Driver" |
6b7c5b94 | 46 | |
c4ca2374 | 47 | #define BE_VENDOR_ID 0x19a2 |
fe6d2a38 | 48 | #define EMULEX_VENDOR_ID 0x10df |
c4ca2374 | 49 | #define BE_DEVICE_ID1 0x211 |
12d7ea2c | 50 | #define BE_DEVICE_ID2 0x221 |
fe6d2a38 SP |
51 | #define OC_DEVICE_ID1 0x700 /* Device Id for BE2 cards */ |
52 | #define OC_DEVICE_ID2 0x710 /* Device Id for BE3 cards */ | |
53 | #define OC_DEVICE_ID3 0xe220 /* Device id for Lancer cards */ | |
12f4d0a8 | 54 | #define OC_DEVICE_ID4 0xe228 /* Device id for VF in Lancer */ |
ecedb6ae | 55 | #define OC_DEVICE_ID5 0x720 /* Device Id for Skyhawk cards */ |
76b73530 | 56 | #define OC_DEVICE_ID6 0x728 /* Device id for VF in SkyHawk */ |
4762f6ce AK |
57 | #define OC_SUBSYS_DEVICE_ID1 0xE602 |
58 | #define OC_SUBSYS_DEVICE_ID2 0xE642 | |
59 | #define OC_SUBSYS_DEVICE_ID3 0xE612 | |
60 | #define OC_SUBSYS_DEVICE_ID4 0xE652 | |
c4ca2374 AK |
61 | |
62 | static inline char *nic_name(struct pci_dev *pdev) | |
63 | { | |
12d7ea2c AK |
64 | switch (pdev->device) { |
65 | case OC_DEVICE_ID1: | |
c4ca2374 | 66 | return OC_NAME; |
e254f6ec | 67 | case OC_DEVICE_ID2: |
fe6d2a38 SP |
68 | return OC_NAME_BE; |
69 | case OC_DEVICE_ID3: | |
12f4d0a8 | 70 | case OC_DEVICE_ID4: |
fe6d2a38 | 71 | return OC_NAME_LANCER; |
12d7ea2c AK |
72 | case BE_DEVICE_ID2: |
73 | return BE3_NAME; | |
ecedb6ae | 74 | case OC_DEVICE_ID5: |
76b73530 | 75 | case OC_DEVICE_ID6: |
ecedb6ae | 76 | return OC_NAME_SH; |
12d7ea2c | 77 | default: |
c4ca2374 | 78 | return BE_NAME; |
12d7ea2c | 79 | } |
c4ca2374 AK |
80 | } |
81 | ||
6b7c5b94 | 82 | /* Number of bytes of an RX frame that are copied to skb->data */ |
2e588f84 | 83 | #define BE_HDR_LEN ((u16) 64) |
bb349bb4 ED |
84 | /* allocate extra space to allow tunneling decapsulation without head reallocation */ |
85 | #define BE_RX_SKB_ALLOC_SIZE (BE_HDR_LEN + 64) | |
86 | ||
6b7c5b94 SP |
87 | #define BE_MAX_JUMBO_FRAME_SIZE 9018 |
88 | #define BE_MIN_MTU 256 | |
89 | ||
90 | #define BE_NUM_VLANS_SUPPORTED 64 | |
2632bafd | 91 | #define BE_MAX_EQD 128u |
6b7c5b94 SP |
92 | #define BE_MAX_TX_FRAG_COUNT 30 |
93 | ||
94 | #define EVNT_Q_LEN 1024 | |
95 | #define TX_Q_LEN 2048 | |
96 | #define TX_CQ_LEN 1024 | |
97 | #define RX_Q_LEN 1024 /* Does not support any other value */ | |
98 | #define RX_CQ_LEN 1024 | |
5fb379ee | 99 | #define MCC_Q_LEN 128 /* total size not to exceed 8 pages */ |
6b7c5b94 SP |
100 | #define MCC_CQ_LEN 256 |
101 | ||
10ef9ab4 | 102 | #define BE2_MAX_RSS_QS 4 |
68d7bdcb SP |
103 | #define BE3_MAX_RSS_QS 16 |
104 | #define BE3_MAX_TX_QS 16 | |
105 | #define BE3_MAX_EVT_QS 16 | |
e3dc867c | 106 | #define BE3_SRIOV_MAX_EVT_QS 8 |
68d7bdcb SP |
107 | |
108 | #define MAX_RX_QS 32 | |
109 | #define MAX_EVT_QS 32 | |
110 | #define MAX_TX_QS 32 | |
10ef9ab4 | 111 | |
045508a8 | 112 | #define MAX_ROCE_EQS 5 |
68d7bdcb | 113 | #define MAX_MSIX_VECTORS 32 |
92bf14ab | 114 | #define MIN_MSIX_VECTORS 1 |
10ef9ab4 | 115 | #define BE_TX_BUDGET 256 |
6b7c5b94 | 116 | #define BE_NAPI_WEIGHT 64 |
10ef9ab4 | 117 | #define MAX_RX_POST BE_NAPI_WEIGHT /* Frags posted at a time */ |
6b7c5b94 SP |
118 | #define RX_FRAGS_REFILL_WM (RX_Q_LEN - MAX_RX_POST) |
119 | ||
7c5a5242 | 120 | #define MAX_VFS 30 /* Max VFs supported by BE3 FW */ |
8788fdc2 SP |
121 | #define FW_VER_LEN 32 |
122 | ||
e2557877 VD |
123 | #define RSS_INDIR_TABLE_LEN 128 |
124 | #define RSS_HASH_KEY_LEN 40 | |
125 | ||
6b7c5b94 SP |
126 | struct be_dma_mem { |
127 | void *va; | |
128 | dma_addr_t dma; | |
129 | u32 size; | |
130 | }; | |
131 | ||
132 | struct be_queue_info { | |
133 | struct be_dma_mem dma_mem; | |
134 | u16 len; | |
135 | u16 entry_size; /* Size of an element in the queue */ | |
136 | u16 id; | |
137 | u16 tail, head; | |
138 | bool created; | |
139 | atomic_t used; /* Number of valid elements in the queue */ | |
140 | }; | |
141 | ||
5fb379ee SP |
142 | static inline u32 MODULO(u16 val, u16 limit) |
143 | { | |
144 | BUG_ON(limit & (limit - 1)); | |
145 | return val & (limit - 1); | |
146 | } | |
147 | ||
148 | static inline void index_adv(u16 *index, u16 val, u16 limit) | |
149 | { | |
150 | *index = MODULO((*index + val), limit); | |
151 | } | |
152 | ||
153 | static inline void index_inc(u16 *index, u16 limit) | |
154 | { | |
155 | *index = MODULO((*index + 1), limit); | |
156 | } | |
157 | ||
158 | static inline void *queue_head_node(struct be_queue_info *q) | |
159 | { | |
160 | return q->dma_mem.va + q->head * q->entry_size; | |
161 | } | |
162 | ||
163 | static inline void *queue_tail_node(struct be_queue_info *q) | |
164 | { | |
165 | return q->dma_mem.va + q->tail * q->entry_size; | |
166 | } | |
167 | ||
3de09455 SK |
168 | static inline void *queue_index_node(struct be_queue_info *q, u16 index) |
169 | { | |
170 | return q->dma_mem.va + index * q->entry_size; | |
171 | } | |
172 | ||
5fb379ee SP |
173 | static inline void queue_head_inc(struct be_queue_info *q) |
174 | { | |
175 | index_inc(&q->head, q->len); | |
176 | } | |
177 | ||
652bf646 PR |
178 | static inline void index_dec(u16 *index, u16 limit) |
179 | { | |
180 | *index = MODULO((*index - 1), limit); | |
181 | } | |
182 | ||
5fb379ee SP |
183 | static inline void queue_tail_inc(struct be_queue_info *q) |
184 | { | |
185 | index_inc(&q->tail, q->len); | |
186 | } | |
187 | ||
5fb379ee SP |
188 | struct be_eq_obj { |
189 | struct be_queue_info q; | |
190 | char desc[32]; | |
191 | ||
192 | /* Adaptive interrupt coalescing (AIC) info */ | |
193 | bool enable_aic; | |
10ef9ab4 SP |
194 | u32 min_eqd; /* in usecs */ |
195 | u32 max_eqd; /* in usecs */ | |
196 | u32 eqd; /* configured val when aic is off */ | |
197 | u32 cur_eqd; /* in usecs */ | |
5fb379ee | 198 | |
10ef9ab4 | 199 | u8 idx; /* array index */ |
f2f781a7 | 200 | u8 msix_idx; |
10ef9ab4 | 201 | u16 tx_budget; |
d0b9cec3 | 202 | u16 spurious_intr; |
5fb379ee | 203 | struct napi_struct napi; |
10ef9ab4 | 204 | struct be_adapter *adapter; |
6384a4d0 SP |
205 | |
206 | #ifdef CONFIG_NET_RX_BUSY_POLL | |
207 | #define BE_EQ_IDLE 0 | |
208 | #define BE_EQ_NAPI 1 /* napi owns this EQ */ | |
209 | #define BE_EQ_POLL 2 /* poll owns this EQ */ | |
210 | #define BE_EQ_LOCKED (BE_EQ_NAPI | BE_EQ_POLL) | |
211 | #define BE_EQ_NAPI_YIELD 4 /* napi yielded this EQ */ | |
212 | #define BE_EQ_POLL_YIELD 8 /* poll yielded this EQ */ | |
213 | #define BE_EQ_YIELD (BE_EQ_NAPI_YIELD | BE_EQ_POLL_YIELD) | |
214 | #define BE_EQ_USER_PEND (BE_EQ_POLL | BE_EQ_POLL_YIELD) | |
215 | unsigned int state; | |
216 | spinlock_t lock; /* lock to serialize napi and busy-poll */ | |
217 | #endif /* CONFIG_NET_RX_BUSY_POLL */ | |
10ef9ab4 | 218 | } ____cacheline_aligned_in_smp; |
5fb379ee | 219 | |
2632bafd SP |
220 | struct be_aic_obj { /* Adaptive interrupt coalescing (AIC) info */ |
221 | bool enable; | |
222 | u32 min_eqd; /* in usecs */ | |
223 | u32 max_eqd; /* in usecs */ | |
224 | u32 prev_eqd; /* in usecs */ | |
225 | u32 et_eqd; /* configured val when aic is off */ | |
226 | ulong jiffies; | |
227 | u64 rx_pkts_prev; /* Used to calculate RX pps */ | |
228 | u64 tx_reqs_prev; /* Used to calculate TX pps */ | |
229 | }; | |
230 | ||
6384a4d0 SP |
231 | enum { |
232 | NAPI_POLLING, | |
233 | BUSY_POLLING | |
234 | }; | |
235 | ||
5fb379ee SP |
236 | struct be_mcc_obj { |
237 | struct be_queue_info q; | |
238 | struct be_queue_info cq; | |
7a1e9b20 | 239 | bool rearm_cq; |
5fb379ee SP |
240 | }; |
241 | ||
3abcdeda | 242 | struct be_tx_stats { |
ac124ff9 SP |
243 | u64 tx_bytes; |
244 | u64 tx_pkts; | |
245 | u64 tx_reqs; | |
246 | u64 tx_wrbs; | |
247 | u64 tx_compl; | |
248 | ulong tx_jiffies; | |
249 | u32 tx_stops; | |
bc617526 | 250 | u32 tx_drv_drops; /* pkts dropped by driver */ |
512bb8a2 KA |
251 | /* the error counters are described in be_ethtool.c */ |
252 | u32 tx_hdr_parse_err; | |
253 | u32 tx_dma_err; | |
254 | u32 tx_tso_err; | |
255 | u32 tx_spoof_check_err; | |
256 | u32 tx_qinq_err; | |
257 | u32 tx_internal_parity_err; | |
ab1594e9 SP |
258 | struct u64_stats_sync sync; |
259 | struct u64_stats_sync sync_compl; | |
6b7c5b94 SP |
260 | }; |
261 | ||
6b7c5b94 | 262 | struct be_tx_obj { |
94d73aaa | 263 | u32 db_offset; |
6b7c5b94 SP |
264 | struct be_queue_info q; |
265 | struct be_queue_info cq; | |
266 | /* Remember the skbs that were transmitted */ | |
267 | struct sk_buff *sent_skb_list[TX_Q_LEN]; | |
3c8def97 | 268 | struct be_tx_stats stats; |
10ef9ab4 | 269 | } ____cacheline_aligned_in_smp; |
6b7c5b94 SP |
270 | |
271 | /* Struct to remember the pages posted for rx frags */ | |
272 | struct be_rx_page_info { | |
273 | struct page *page; | |
e50287be | 274 | /* set to page-addr for last frag of the page & frag-addr otherwise */ |
fac6da5b | 275 | DEFINE_DMA_UNMAP_ADDR(bus); |
6b7c5b94 | 276 | u16 page_offset; |
e50287be | 277 | bool last_frag; /* last frag of the page */ |
6b7c5b94 SP |
278 | }; |
279 | ||
3abcdeda | 280 | struct be_rx_stats { |
3abcdeda | 281 | u64 rx_bytes; |
3abcdeda | 282 | u64 rx_pkts; |
ac124ff9 SP |
283 | u32 rx_drops_no_skbs; /* skb allocation errors */ |
284 | u32 rx_drops_no_frags; /* HW has no fetched frags */ | |
285 | u32 rx_post_fail; /* page post alloc failures */ | |
ac124ff9 | 286 | u32 rx_compl; |
3abcdeda | 287 | u32 rx_mcast_pkts; |
ac124ff9 | 288 | u32 rx_compl_err; /* completions with err set */ |
ab1594e9 | 289 | struct u64_stats_sync sync; |
3abcdeda SP |
290 | }; |
291 | ||
2e588f84 SP |
292 | struct be_rx_compl_info { |
293 | u32 rss_hash; | |
6709d952 | 294 | u16 vlan_tag; |
2e588f84 | 295 | u16 pkt_size; |
12004ae9 | 296 | u16 port; |
2e588f84 SP |
297 | u8 vlanf; |
298 | u8 num_rcvd; | |
299 | u8 err; | |
300 | u8 ipf; | |
301 | u8 tcpf; | |
302 | u8 udpf; | |
303 | u8 ip_csum; | |
304 | u8 l4_csum; | |
305 | u8 ipv6; | |
f93f160b | 306 | u8 qnq; |
2e588f84 | 307 | u8 pkt_type; |
e38b1706 | 308 | u8 ip_frag; |
c9c47142 | 309 | u8 tunneled; |
2e588f84 SP |
310 | }; |
311 | ||
6b7c5b94 | 312 | struct be_rx_obj { |
3abcdeda | 313 | struct be_adapter *adapter; |
6b7c5b94 SP |
314 | struct be_queue_info q; |
315 | struct be_queue_info cq; | |
2e588f84 | 316 | struct be_rx_compl_info rxcp; |
6b7c5b94 | 317 | struct be_rx_page_info page_info_tbl[RX_Q_LEN]; |
3abcdeda SP |
318 | struct be_rx_stats stats; |
319 | u8 rss_id; | |
320 | bool rx_post_starved; /* Zero rx frags have been posted to BE */ | |
10ef9ab4 | 321 | } ____cacheline_aligned_in_smp; |
6b7c5b94 | 322 | |
609ff3bb | 323 | struct be_drv_stats { |
9ae081c6 | 324 | u32 be_on_die_temperature; |
ac124ff9 SP |
325 | u32 eth_red_drops; |
326 | u32 rx_drops_no_pbuf; | |
327 | u32 rx_drops_no_txpb; | |
328 | u32 rx_drops_no_erx_descr; | |
329 | u32 rx_drops_no_tpre_descr; | |
330 | u32 rx_drops_too_many_frags; | |
ac124ff9 SP |
331 | u32 forwarded_packets; |
332 | u32 rx_drops_mtu; | |
333 | u32 rx_crc_errors; | |
334 | u32 rx_alignment_symbol_errors; | |
335 | u32 rx_pause_frames; | |
336 | u32 rx_priority_pause_frames; | |
337 | u32 rx_control_frames; | |
338 | u32 rx_in_range_errors; | |
339 | u32 rx_out_range_errors; | |
340 | u32 rx_frame_too_long; | |
18fb06a1 | 341 | u32 rx_address_filtered; |
ac124ff9 SP |
342 | u32 rx_dropped_too_small; |
343 | u32 rx_dropped_too_short; | |
344 | u32 rx_dropped_header_too_small; | |
345 | u32 rx_dropped_tcp_length; | |
346 | u32 rx_dropped_runt; | |
347 | u32 rx_ip_checksum_errs; | |
348 | u32 rx_tcp_checksum_errs; | |
349 | u32 rx_udp_checksum_errs; | |
350 | u32 tx_pauseframes; | |
351 | u32 tx_priority_pauseframes; | |
352 | u32 tx_controlframes; | |
353 | u32 rxpp_fifo_overflow_drop; | |
354 | u32 rx_input_fifo_overflow_drop; | |
355 | u32 pmem_fifo_overflow_drop; | |
356 | u32 jabber_events; | |
461ae379 AK |
357 | u32 rx_roce_bytes_lsd; |
358 | u32 rx_roce_bytes_msd; | |
359 | u32 rx_roce_frames; | |
360 | u32 roce_drops_payload_len; | |
361 | u32 roce_drops_crc; | |
609ff3bb AK |
362 | }; |
363 | ||
c502224e SK |
364 | /* A vlan-id of 0xFFFF must be used to clear transparent vlan-tagging */ |
365 | #define BE_RESET_VLAN_TAG_ID 0xFFFF | |
366 | ||
64600ea5 | 367 | struct be_vf_cfg { |
11ac75ed SP |
368 | unsigned char mac_addr[ETH_ALEN]; |
369 | int if_handle; | |
370 | int pmac_id; | |
371 | u16 vlan_tag; | |
372 | u32 tx_rate; | |
bdce2ad7 | 373 | u32 plink_tracking; |
64600ea5 AK |
374 | }; |
375 | ||
39f1d94d SP |
376 | enum vf_state { |
377 | ENABLED = 0, | |
378 | ASSIGNED = 1 | |
379 | }; | |
380 | ||
b236916a | 381 | #define BE_FLAGS_LINK_STATUS_INIT 1 |
f174c7ec | 382 | #define BE_FLAGS_SRIOV_ENABLED (1 << 2) |
191eb756 | 383 | #define BE_FLAGS_WORKER_SCHEDULED (1 << 3) |
d9d604f8 | 384 | #define BE_FLAGS_VLAN_PROMISC (1 << 4) |
a0794885 | 385 | #define BE_FLAGS_MCAST_PROMISC (1 << 5) |
04d3d624 | 386 | #define BE_FLAGS_NAPI_ENABLED (1 << 9) |
bc0c3405 | 387 | #define BE_FLAGS_QNQ_ASYNC_EVT_RCVD (1 << 11) |
c9c47142 | 388 | #define BE_FLAGS_VXLAN_OFFLOADS (1 << 12) |
e1ad8e33 | 389 | #define BE_FLAGS_SETUP_DONE (1 << 13) |
b236916a | 390 | |
c9c47142 SP |
391 | #define BE_UC_PMAC_COUNT 30 |
392 | #define BE_VF_UC_PMAC_COUNT 2 | |
f0613380 | 393 | |
5c510811 SK |
394 | /* Ethtool set_dump flags */ |
395 | #define LANCER_INITIATE_FW_DUMP 0x1 | |
f0613380 | 396 | #define LANCER_DELETE_FW_DUMP 0x2 |
5c510811 | 397 | |
42f11cf2 AK |
398 | struct phy_info { |
399 | u8 transceiver; | |
400 | u8 autoneg; | |
401 | u8 fc_autoneg; | |
402 | u8 port_type; | |
403 | u16 phy_type; | |
404 | u16 interface_type; | |
405 | u32 misc_params; | |
406 | u16 auto_speeds_supported; | |
407 | u16 fixed_speeds_supported; | |
408 | int link_speed; | |
42f11cf2 AK |
409 | u32 dac_cable_len; |
410 | u32 advertising; | |
411 | u32 supported; | |
412 | }; | |
413 | ||
92bf14ab SP |
414 | struct be_resources { |
415 | u16 max_vfs; /* Total VFs "really" supported by FW/HW */ | |
416 | u16 max_mcast_mac; | |
417 | u16 max_tx_qs; | |
418 | u16 max_rss_qs; | |
419 | u16 max_rx_qs; | |
420 | u16 max_uc_mac; /* Max UC MACs programmable */ | |
421 | u16 max_vlans; /* Number of vlans supported */ | |
422 | u16 max_evt_qs; | |
423 | u32 if_cap_flags; | |
10cccf60 | 424 | u32 vf_if_cap_flags; /* VF if capability flags */ |
92bf14ab SP |
425 | }; |
426 | ||
e2557877 VD |
427 | struct rss_info { |
428 | u64 rss_flags; | |
429 | u8 rsstable[RSS_INDIR_TABLE_LEN]; | |
430 | u8 rss_queue[RSS_INDIR_TABLE_LEN]; | |
431 | u8 rss_hkey[RSS_HASH_KEY_LEN]; | |
432 | }; | |
433 | ||
6b7c5b94 SP |
434 | struct be_adapter { |
435 | struct pci_dev *pdev; | |
436 | struct net_device *netdev; | |
437 | ||
c5b3ad4c | 438 | u8 __iomem *csr; /* CSR BAR used only for BE2/3 */ |
8788fdc2 | 439 | u8 __iomem *db; /* Door Bell */ |
8788fdc2 | 440 | |
2984961c | 441 | struct mutex mbox_lock; /* For serializing mbox cmds to BE card */ |
8788fdc2 SP |
442 | struct be_dma_mem mbox_mem; |
443 | /* Mbox mem is adjusted to align to 16 bytes. The allocated addr | |
444 | * is stored for freeing purpose */ | |
445 | struct be_dma_mem mbox_mem_alloced; | |
446 | ||
447 | struct be_mcc_obj mcc_obj; | |
448 | spinlock_t mcc_lock; /* For serializing mcc cmds to BE card */ | |
449 | spinlock_t mcc_cq_lock; | |
6b7c5b94 | 450 | |
92bf14ab SP |
451 | u16 cfg_num_qs; /* configured via set-channels */ |
452 | u16 num_evt_qs; | |
453 | u16 num_msix_vec; | |
454 | struct be_eq_obj eq_obj[MAX_EVT_QS]; | |
10ef9ab4 | 455 | struct msix_entry msix_entries[MAX_MSIX_VECTORS]; |
6b7c5b94 SP |
456 | bool isr_registered; |
457 | ||
458 | /* TX Rings */ | |
92bf14ab | 459 | u16 num_tx_qs; |
3c8def97 | 460 | struct be_tx_obj tx_obj[MAX_TX_QS]; |
6b7c5b94 SP |
461 | |
462 | /* Rx rings */ | |
92bf14ab | 463 | u16 num_rx_qs; |
10ef9ab4 | 464 | struct be_rx_obj rx_obj[MAX_RX_QS]; |
6b7c5b94 SP |
465 | u32 big_page_size; /* Compounded page size shared by rx wrbs */ |
466 | ||
609ff3bb | 467 | struct be_drv_stats drv_stats; |
2632bafd | 468 | struct be_aic_obj aic_obj[MAX_EVT_QS]; |
82903e4b | 469 | u16 vlans_added; |
f6cbd364 | 470 | unsigned long vids[BITS_TO_LONGS(VLAN_N_VID)]; |
cc4ce020 SK |
471 | u8 vlan_prio_bmap; /* Available Priority BitMap */ |
472 | u16 recommended_prio; /* Recommended Priority */ | |
5b8821b7 | 473 | struct be_dma_mem rx_filter; /* Cmd DMA mem for rx-filter */ |
6b7c5b94 | 474 | |
3abcdeda | 475 | struct be_dma_mem stats_cmd; |
6b7c5b94 SP |
476 | /* Work queue used to perform periodic tasks like getting statistics */ |
477 | struct delayed_work work; | |
609ff3bb | 478 | u16 work_counter; |
6b7c5b94 | 479 | |
f67ef7ba | 480 | struct delayed_work func_recovery_work; |
b236916a | 481 | u32 flags; |
f25b119c | 482 | u32 cmd_privileges; |
6b7c5b94 | 483 | /* Ethtool knobs and info */ |
6b7c5b94 | 484 | char fw_ver[FW_VER_LEN]; |
eeb65ced | 485 | char fw_on_flash[FW_VER_LEN]; |
30128031 | 486 | int if_handle; /* Used to configure filtering */ |
fbc13f01 | 487 | u32 *pmac_id; /* MAC addr handle used by BE card */ |
1a642469 | 488 | u32 beacon_state; /* for set_phys_id */ |
6b7c5b94 | 489 | |
f67ef7ba | 490 | bool eeh_error; |
6589ade0 | 491 | bool fw_timeout; |
f67ef7ba PR |
492 | bool hw_error; |
493 | ||
6b7c5b94 | 494 | u32 port_num; |
24307eef | 495 | bool promiscuous; |
f93f160b | 496 | u8 mc_type; |
3486be29 | 497 | u32 function_mode; |
3abcdeda | 498 | u32 function_caps; |
9e90c961 AK |
499 | u32 rx_fc; /* Rx flow control */ |
500 | u32 tx_fc; /* Tx flow control */ | |
b2aebe6d | 501 | bool stats_cmd_sent; |
045508a8 | 502 | struct { |
045508a8 PP |
503 | u32 size; |
504 | u32 total_size; | |
505 | u64 io_addr; | |
506 | } roce_db; | |
507 | u32 num_msix_roce_vec; | |
508 | struct ocrdma_dev *ocrdma_dev; | |
509 | struct list_head entry; | |
510 | ||
dd131e76 | 511 | u32 flash_status; |
5eeff635 | 512 | struct completion et_cmd_compl; |
ba343c77 | 513 | |
bec84e6b | 514 | struct be_resources pool_res; /* resources available for the port */ |
92bf14ab SP |
515 | struct be_resources res; /* resources available for the func */ |
516 | u16 num_vfs; /* Number of VFs provisioned by PF */ | |
39f1d94d | 517 | u8 virtfn; |
11ac75ed SP |
518 | struct be_vf_cfg *vf_cfg; |
519 | bool be3_native; | |
fe6d2a38 | 520 | u32 sli_family; |
9e1453c5 | 521 | u8 hba_port_num; |
3968fa1e | 522 | u16 pvid; |
c9c47142 | 523 | __be16 vxlan_port; |
42f11cf2 | 524 | struct phy_info phy; |
4762f6ce | 525 | u8 wol_cap; |
76a9e08e | 526 | bool wol_en; |
fbc13f01 | 527 | u32 uc_macs; /* Count of secondary UC MAC programmed */ |
0ad3157e | 528 | u16 asic_rev; |
bc0c3405 | 529 | u16 qnq_vid; |
941a77d5 | 530 | u32 msg_enable; |
7aeb2156 | 531 | int be_get_temp_freq; |
d5c18473 | 532 | u8 pf_number; |
e2557877 | 533 | struct rss_info rss_info; |
6b7c5b94 SP |
534 | }; |
535 | ||
39f1d94d | 536 | #define be_physfn(adapter) (!adapter->virtfn) |
2c7a9dc1 | 537 | #define be_virtfn(adapter) (adapter->virtfn) |
f174c7ec VV |
538 | #define sriov_enabled(adapter) (adapter->flags & \ |
539 | BE_FLAGS_SRIOV_ENABLED) | |
bec84e6b | 540 | |
11ac75ed SP |
541 | #define for_all_vfs(adapter, vf_cfg, i) \ |
542 | for (i = 0, vf_cfg = &adapter->vf_cfg[i]; i < adapter->num_vfs; \ | |
543 | i++, vf_cfg++) | |
ba343c77 | 544 | |
5b8821b7 SP |
545 | #define ON 1 |
546 | #define OFF 0 | |
ca34fe38 | 547 | |
92bf14ab SP |
548 | #define be_max_vlans(adapter) (adapter->res.max_vlans) |
549 | #define be_max_uc(adapter) (adapter->res.max_uc_mac) | |
550 | #define be_max_mc(adapter) (adapter->res.max_mcast_mac) | |
bec84e6b | 551 | #define be_max_vfs(adapter) (adapter->pool_res.max_vfs) |
92bf14ab SP |
552 | #define be_max_rss(adapter) (adapter->res.max_rss_qs) |
553 | #define be_max_txqs(adapter) (adapter->res.max_tx_qs) | |
554 | #define be_max_prio_txqs(adapter) (adapter->res.max_prio_tx_qs) | |
555 | #define be_max_rxqs(adapter) (adapter->res.max_rx_qs) | |
556 | #define be_max_eqs(adapter) (adapter->res.max_evt_qs) | |
557 | #define be_if_cap_flags(adapter) (adapter->res.if_cap_flags) | |
558 | ||
559 | static inline u16 be_max_qs(struct be_adapter *adapter) | |
560 | { | |
561 | /* If no RSS, need atleast the one def RXQ */ | |
562 | u16 num = max_t(u16, be_max_rss(adapter), 1); | |
563 | ||
564 | num = min(num, be_max_eqs(adapter)); | |
565 | return min_t(u16, num, num_online_cpus()); | |
566 | } | |
567 | ||
f93f160b VV |
568 | /* Is BE in pvid_tagging mode */ |
569 | #define be_pvid_tagging_enabled(adapter) (adapter->pvid) | |
570 | ||
571 | /* Is BE in QNQ multi-channel mode */ | |
66064dbc | 572 | #define be_is_qnq_mode(adapter) (adapter->function_mode & QNQ_MODE) |
f93f160b | 573 | |
ca34fe38 SP |
574 | #define lancer_chip(adapter) (adapter->pdev->device == OC_DEVICE_ID3 || \ |
575 | adapter->pdev->device == OC_DEVICE_ID4) | |
fe6d2a38 | 576 | |
76b73530 PR |
577 | #define skyhawk_chip(adapter) (adapter->pdev->device == OC_DEVICE_ID5 || \ |
578 | adapter->pdev->device == OC_DEVICE_ID6) | |
d3bd3a5e | 579 | |
ca34fe38 SP |
580 | #define BE3_chip(adapter) (adapter->pdev->device == BE_DEVICE_ID2 || \ |
581 | adapter->pdev->device == OC_DEVICE_ID2) | |
582 | ||
583 | #define BE2_chip(adapter) (adapter->pdev->device == BE_DEVICE_ID1 || \ | |
584 | adapter->pdev->device == OC_DEVICE_ID1) | |
585 | ||
586 | #define BEx_chip(adapter) (BE3_chip(adapter) || BE2_chip(adapter)) | |
d3bd3a5e | 587 | |
dbf0f2a7 SP |
588 | #define be_roce_supported(adapter) (skyhawk_chip(adapter) && \ |
589 | (adapter->function_mode & RDMA_ENABLED)) | |
045508a8 | 590 | |
0fc0b732 | 591 | extern const struct ethtool_ops be_ethtool_ops; |
6b7c5b94 | 592 | |
ac6a0c4a | 593 | #define msix_enabled(adapter) (adapter->num_msix_vec > 0) |
10ef9ab4 SP |
594 | #define num_irqs(adapter) (msix_enabled(adapter) ? \ |
595 | adapter->num_msix_vec : 1) | |
596 | #define tx_stats(txo) (&(txo)->stats) | |
597 | #define rx_stats(rxo) (&(rxo)->stats) | |
6b7c5b94 | 598 | |
10ef9ab4 SP |
599 | /* The default RXQ is the last RXQ */ |
600 | #define default_rxo(adpt) (&adpt->rx_obj[adpt->num_rx_qs - 1]) | |
6b7c5b94 | 601 | |
3abcdeda SP |
602 | #define for_all_rx_queues(adapter, rxo, i) \ |
603 | for (i = 0, rxo = &adapter->rx_obj[i]; i < adapter->num_rx_qs; \ | |
604 | i++, rxo++) | |
605 | ||
10ef9ab4 | 606 | /* Skip the default non-rss queue (last one)*/ |
3abcdeda | 607 | #define for_all_rss_queues(adapter, rxo, i) \ |
10ef9ab4 | 608 | for (i = 0, rxo = &adapter->rx_obj[i]; i < (adapter->num_rx_qs - 1);\ |
3abcdeda SP |
609 | i++, rxo++) |
610 | ||
3c8def97 SP |
611 | #define for_all_tx_queues(adapter, txo, i) \ |
612 | for (i = 0, txo = &adapter->tx_obj[i]; i < adapter->num_tx_qs; \ | |
613 | i++, txo++) | |
614 | ||
10ef9ab4 SP |
615 | #define for_all_evt_queues(adapter, eqo, i) \ |
616 | for (i = 0, eqo = &adapter->eq_obj[i]; i < adapter->num_evt_qs; \ | |
617 | i++, eqo++) | |
618 | ||
6384a4d0 SP |
619 | #define for_all_rx_queues_on_eq(adapter, eqo, rxo, i) \ |
620 | for (i = eqo->idx, rxo = &adapter->rx_obj[i]; i < adapter->num_rx_qs;\ | |
621 | i += adapter->num_evt_qs, rxo += adapter->num_evt_qs) | |
622 | ||
10ef9ab4 SP |
623 | #define is_mcc_eqo(eqo) (eqo->idx == 0) |
624 | #define mcc_eqo(adapter) (&adapter->eq_obj[0]) | |
625 | ||
6b7c5b94 SP |
626 | #define PAGE_SHIFT_4K 12 |
627 | #define PAGE_SIZE_4K (1 << PAGE_SHIFT_4K) | |
628 | ||
629 | /* Returns number of pages spanned by the data starting at the given addr */ | |
630 | #define PAGES_4K_SPANNED(_address, size) \ | |
631 | ((u32)((((size_t)(_address) & (PAGE_SIZE_4K - 1)) + \ | |
632 | (size) + (PAGE_SIZE_4K - 1)) >> PAGE_SHIFT_4K)) | |
633 | ||
6b7c5b94 SP |
634 | /* Returns bit offset within a DWORD of a bitfield */ |
635 | #define AMAP_BIT_OFFSET(_struct, field) \ | |
636 | (((size_t)&(((_struct *)0)->field))%32) | |
637 | ||
638 | /* Returns the bit mask of the field that is NOT shifted into location. */ | |
639 | static inline u32 amap_mask(u32 bitsize) | |
640 | { | |
641 | return (bitsize == 32 ? 0xFFFFFFFF : (1 << bitsize) - 1); | |
642 | } | |
643 | ||
644 | static inline void | |
645 | amap_set(void *ptr, u32 dw_offset, u32 mask, u32 offset, u32 value) | |
646 | { | |
647 | u32 *dw = (u32 *) ptr + dw_offset; | |
648 | *dw &= ~(mask << offset); | |
649 | *dw |= (mask & value) << offset; | |
650 | } | |
651 | ||
652 | #define AMAP_SET_BITS(_struct, field, ptr, val) \ | |
653 | amap_set(ptr, \ | |
654 | offsetof(_struct, field)/32, \ | |
655 | amap_mask(sizeof(((_struct *)0)->field)), \ | |
656 | AMAP_BIT_OFFSET(_struct, field), \ | |
657 | val) | |
658 | ||
659 | static inline u32 amap_get(void *ptr, u32 dw_offset, u32 mask, u32 offset) | |
660 | { | |
661 | u32 *dw = (u32 *) ptr; | |
662 | return mask & (*(dw + dw_offset) >> offset); | |
663 | } | |
664 | ||
665 | #define AMAP_GET_BITS(_struct, field, ptr) \ | |
666 | amap_get(ptr, \ | |
667 | offsetof(_struct, field)/32, \ | |
668 | amap_mask(sizeof(((_struct *)0)->field)), \ | |
669 | AMAP_BIT_OFFSET(_struct, field)) | |
670 | ||
c3c18bc1 SP |
671 | #define GET_RX_COMPL_V0_BITS(field, ptr) \ |
672 | AMAP_GET_BITS(struct amap_eth_rx_compl_v0, field, ptr) | |
673 | ||
674 | #define GET_RX_COMPL_V1_BITS(field, ptr) \ | |
675 | AMAP_GET_BITS(struct amap_eth_rx_compl_v1, field, ptr) | |
676 | ||
677 | #define GET_TX_COMPL_BITS(field, ptr) \ | |
678 | AMAP_GET_BITS(struct amap_eth_tx_compl, field, ptr) | |
679 | ||
680 | #define SET_TX_WRB_HDR_BITS(field, ptr, val) \ | |
681 | AMAP_SET_BITS(struct amap_eth_hdr_wrb, field, ptr, val) | |
682 | ||
6b7c5b94 SP |
683 | #define be_dws_cpu_to_le(wrb, len) swap_dws(wrb, len) |
684 | #define be_dws_le_to_cpu(wrb, len) swap_dws(wrb, len) | |
685 | static inline void swap_dws(void *wrb, int len) | |
686 | { | |
687 | #ifdef __BIG_ENDIAN | |
688 | u32 *dw = wrb; | |
689 | BUG_ON(len % 4); | |
690 | do { | |
691 | *dw = cpu_to_le32(*dw); | |
692 | dw++; | |
693 | len -= 4; | |
694 | } while (len); | |
695 | #endif /* __BIG_ENDIAN */ | |
696 | } | |
697 | ||
0532d4e3 KA |
698 | #define be_cmd_status(status) (status > 0 ? -EIO : status) |
699 | ||
6b7c5b94 SP |
700 | static inline u8 is_tcp_pkt(struct sk_buff *skb) |
701 | { | |
702 | u8 val = 0; | |
703 | ||
704 | if (ip_hdr(skb)->version == 4) | |
705 | val = (ip_hdr(skb)->protocol == IPPROTO_TCP); | |
706 | else if (ip_hdr(skb)->version == 6) | |
707 | val = (ipv6_hdr(skb)->nexthdr == NEXTHDR_TCP); | |
708 | ||
709 | return val; | |
710 | } | |
711 | ||
712 | static inline u8 is_udp_pkt(struct sk_buff *skb) | |
713 | { | |
714 | u8 val = 0; | |
715 | ||
716 | if (ip_hdr(skb)->version == 4) | |
717 | val = (ip_hdr(skb)->protocol == IPPROTO_UDP); | |
718 | else if (ip_hdr(skb)->version == 6) | |
719 | val = (ipv6_hdr(skb)->nexthdr == NEXTHDR_UDP); | |
720 | ||
721 | return val; | |
722 | } | |
723 | ||
93040ae5 SK |
724 | static inline bool is_ipv4_pkt(struct sk_buff *skb) |
725 | { | |
e8efcec5 | 726 | return skb->protocol == htons(ETH_P_IP) && ip_hdr(skb)->version == 4; |
93040ae5 SK |
727 | } |
728 | ||
6d87f5c3 AK |
729 | static inline void be_vf_eth_addr_generate(struct be_adapter *adapter, u8 *mac) |
730 | { | |
731 | u32 addr; | |
732 | ||
733 | addr = jhash(adapter->netdev->dev_addr, ETH_ALEN, 0); | |
734 | ||
735 | mac[5] = (u8)(addr & 0xFF); | |
736 | mac[4] = (u8)((addr >> 8) & 0xFF); | |
737 | mac[3] = (u8)((addr >> 16) & 0xFF); | |
7a2414a5 AK |
738 | /* Use the OUI from the current MAC address */ |
739 | memcpy(mac, adapter->netdev->dev_addr, 3); | |
6d87f5c3 AK |
740 | } |
741 | ||
4b972914 AK |
742 | static inline bool be_multi_rxq(const struct be_adapter *adapter) |
743 | { | |
744 | return adapter->num_rx_qs > 1; | |
745 | } | |
746 | ||
6589ade0 SP |
747 | static inline bool be_error(struct be_adapter *adapter) |
748 | { | |
f67ef7ba PR |
749 | return adapter->eeh_error || adapter->hw_error || adapter->fw_timeout; |
750 | } | |
751 | ||
d23e946c | 752 | static inline bool be_hw_error(struct be_adapter *adapter) |
f67ef7ba PR |
753 | { |
754 | return adapter->eeh_error || adapter->hw_error; | |
755 | } | |
756 | ||
757 | static inline void be_clear_all_error(struct be_adapter *adapter) | |
758 | { | |
759 | adapter->eeh_error = false; | |
760 | adapter->hw_error = false; | |
761 | adapter->fw_timeout = false; | |
6589ade0 SP |
762 | } |
763 | ||
4762f6ce AK |
764 | static inline bool be_is_wol_excluded(struct be_adapter *adapter) |
765 | { | |
766 | struct pci_dev *pdev = adapter->pdev; | |
767 | ||
768 | if (!be_physfn(adapter)) | |
769 | return true; | |
770 | ||
771 | switch (pdev->subsystem_device) { | |
772 | case OC_SUBSYS_DEVICE_ID1: | |
773 | case OC_SUBSYS_DEVICE_ID2: | |
774 | case OC_SUBSYS_DEVICE_ID3: | |
775 | case OC_SUBSYS_DEVICE_ID4: | |
776 | return true; | |
777 | default: | |
778 | return false; | |
779 | } | |
780 | } | |
781 | ||
bc0c3405 AK |
782 | static inline int qnq_async_evt_rcvd(struct be_adapter *adapter) |
783 | { | |
784 | return adapter->flags & BE_FLAGS_QNQ_ASYNC_EVT_RCVD; | |
785 | } | |
786 | ||
6384a4d0 SP |
787 | #ifdef CONFIG_NET_RX_BUSY_POLL |
788 | static inline bool be_lock_napi(struct be_eq_obj *eqo) | |
789 | { | |
790 | bool status = true; | |
791 | ||
792 | spin_lock(&eqo->lock); /* BH is already disabled */ | |
793 | if (eqo->state & BE_EQ_LOCKED) { | |
794 | WARN_ON(eqo->state & BE_EQ_NAPI); | |
795 | eqo->state |= BE_EQ_NAPI_YIELD; | |
796 | status = false; | |
797 | } else { | |
798 | eqo->state = BE_EQ_NAPI; | |
799 | } | |
800 | spin_unlock(&eqo->lock); | |
801 | return status; | |
802 | } | |
803 | ||
804 | static inline void be_unlock_napi(struct be_eq_obj *eqo) | |
805 | { | |
806 | spin_lock(&eqo->lock); /* BH is already disabled */ | |
807 | ||
808 | WARN_ON(eqo->state & (BE_EQ_POLL | BE_EQ_NAPI_YIELD)); | |
809 | eqo->state = BE_EQ_IDLE; | |
810 | ||
811 | spin_unlock(&eqo->lock); | |
812 | } | |
813 | ||
814 | static inline bool be_lock_busy_poll(struct be_eq_obj *eqo) | |
815 | { | |
816 | bool status = true; | |
817 | ||
818 | spin_lock_bh(&eqo->lock); | |
819 | if (eqo->state & BE_EQ_LOCKED) { | |
820 | eqo->state |= BE_EQ_POLL_YIELD; | |
821 | status = false; | |
822 | } else { | |
823 | eqo->state |= BE_EQ_POLL; | |
824 | } | |
825 | spin_unlock_bh(&eqo->lock); | |
826 | return status; | |
827 | } | |
828 | ||
829 | static inline void be_unlock_busy_poll(struct be_eq_obj *eqo) | |
830 | { | |
831 | spin_lock_bh(&eqo->lock); | |
832 | ||
833 | WARN_ON(eqo->state & (BE_EQ_NAPI)); | |
834 | eqo->state = BE_EQ_IDLE; | |
835 | ||
836 | spin_unlock_bh(&eqo->lock); | |
837 | } | |
838 | ||
839 | static inline void be_enable_busy_poll(struct be_eq_obj *eqo) | |
840 | { | |
841 | spin_lock_init(&eqo->lock); | |
842 | eqo->state = BE_EQ_IDLE; | |
843 | } | |
844 | ||
845 | static inline void be_disable_busy_poll(struct be_eq_obj *eqo) | |
846 | { | |
847 | local_bh_disable(); | |
848 | ||
849 | /* It's enough to just acquire napi lock on the eqo to stop | |
850 | * be_busy_poll() from processing any queueus. | |
851 | */ | |
852 | while (!be_lock_napi(eqo)) | |
853 | mdelay(1); | |
854 | ||
855 | local_bh_enable(); | |
856 | } | |
857 | ||
858 | #else /* CONFIG_NET_RX_BUSY_POLL */ | |
859 | ||
860 | static inline bool be_lock_napi(struct be_eq_obj *eqo) | |
861 | { | |
862 | return true; | |
863 | } | |
864 | ||
865 | static inline void be_unlock_napi(struct be_eq_obj *eqo) | |
866 | { | |
867 | } | |
868 | ||
869 | static inline bool be_lock_busy_poll(struct be_eq_obj *eqo) | |
870 | { | |
871 | return false; | |
872 | } | |
873 | ||
874 | static inline void be_unlock_busy_poll(struct be_eq_obj *eqo) | |
875 | { | |
876 | } | |
877 | ||
878 | static inline void be_enable_busy_poll(struct be_eq_obj *eqo) | |
879 | { | |
880 | } | |
881 | ||
882 | static inline void be_disable_busy_poll(struct be_eq_obj *eqo) | |
883 | { | |
884 | } | |
885 | #endif /* CONFIG_NET_RX_BUSY_POLL */ | |
886 | ||
31886e87 JP |
887 | void be_cq_notify(struct be_adapter *adapter, u16 qid, bool arm, |
888 | u16 num_popped); | |
889 | void be_link_status_update(struct be_adapter *adapter, u8 link_status); | |
890 | void be_parse_stats(struct be_adapter *adapter); | |
891 | int be_load_fw(struct be_adapter *adapter, u8 *func); | |
892 | bool be_is_wol_supported(struct be_adapter *adapter); | |
893 | bool be_pause_supported(struct be_adapter *adapter); | |
894 | u32 be_get_fw_log_level(struct be_adapter *adapter); | |
394efd19 | 895 | |
e9e2a904 SK |
896 | static inline int fw_major_num(const char *fw_ver) |
897 | { | |
898 | int fw_major = 0; | |
899 | ||
900 | sscanf(fw_ver, "%d.", &fw_major); | |
901 | ||
902 | return fw_major; | |
903 | } | |
904 | ||
68d7bdcb SP |
905 | int be_update_queues(struct be_adapter *adapter); |
906 | int be_poll(struct napi_struct *napi, int budget); | |
941a77d5 | 907 | |
045508a8 PP |
908 | /* |
909 | * internal function to initialize-cleanup roce device. | |
910 | */ | |
31886e87 JP |
911 | void be_roce_dev_add(struct be_adapter *); |
912 | void be_roce_dev_remove(struct be_adapter *); | |
045508a8 PP |
913 | |
914 | /* | |
915 | * internal function to open-close roce device during ifup-ifdown. | |
916 | */ | |
31886e87 JP |
917 | void be_roce_dev_open(struct be_adapter *); |
918 | void be_roce_dev_close(struct be_adapter *); | |
d114f99a | 919 | void be_roce_dev_shutdown(struct be_adapter *); |
045508a8 | 920 | |
6b7c5b94 | 921 | #endif /* BE_H */ |