Commit | Line | Data |
---|---|---|
6b7c5b94 | 1 | /* |
c7bb15a6 | 2 | * Copyright (C) 2005 - 2013 Emulex |
6b7c5b94 SP |
3 | * All rights reserved. |
4 | * | |
5 | * This program is free software; you can redistribute it and/or | |
6 | * modify it under the terms of the GNU General Public License version 2 | |
7 | * as published by the Free Software Foundation. The full GNU General | |
8 | * Public License is included in this distribution in the file called COPYING. | |
9 | * | |
10 | * Contact Information: | |
d2145cde | 11 | * linux-drivers@emulex.com |
6b7c5b94 | 12 | * |
d2145cde AK |
13 | * Emulex |
14 | * 3333 Susan Street | |
15 | * Costa Mesa, CA 92626 | |
6b7c5b94 SP |
16 | */ |
17 | ||
18 | #ifndef BE_H | |
19 | #define BE_H | |
20 | ||
21 | #include <linux/pci.h> | |
22 | #include <linux/etherdevice.h> | |
6b7c5b94 SP |
23 | #include <linux/delay.h> |
24 | #include <net/tcp.h> | |
25 | #include <net/ip.h> | |
26 | #include <net/ipv6.h> | |
27 | #include <linux/if_vlan.h> | |
28 | #include <linux/workqueue.h> | |
29 | #include <linux/interrupt.h> | |
84517482 | 30 | #include <linux/firmware.h> |
5a0e3ad6 | 31 | #include <linux/slab.h> |
ab1594e9 | 32 | #include <linux/u64_stats_sync.h> |
6b7c5b94 SP |
33 | |
34 | #include "be_hw.h" | |
045508a8 | 35 | #include "be_roce.h" |
6b7c5b94 | 36 | |
5721f943 | 37 | #define DRV_VER "4.9.134.0u" |
6b7c5b94 | 38 | #define DRV_NAME "be2net" |
00d3d51e SB |
39 | #define BE_NAME "Emulex BladeEngine2" |
40 | #define BE3_NAME "Emulex BladeEngine3" | |
41 | #define OC_NAME "Emulex OneConnect" | |
fe6d2a38 SP |
42 | #define OC_NAME_BE OC_NAME "(be3)" |
43 | #define OC_NAME_LANCER OC_NAME "(Lancer)" | |
ecedb6ae | 44 | #define OC_NAME_SH OC_NAME "(Skyhawk)" |
00d3d51e | 45 | #define DRV_DESC "Emulex OneConnect 10Gbps NIC Driver" |
6b7c5b94 | 46 | |
c4ca2374 | 47 | #define BE_VENDOR_ID 0x19a2 |
fe6d2a38 | 48 | #define EMULEX_VENDOR_ID 0x10df |
c4ca2374 | 49 | #define BE_DEVICE_ID1 0x211 |
12d7ea2c | 50 | #define BE_DEVICE_ID2 0x221 |
fe6d2a38 SP |
51 | #define OC_DEVICE_ID1 0x700 /* Device Id for BE2 cards */ |
52 | #define OC_DEVICE_ID2 0x710 /* Device Id for BE3 cards */ | |
53 | #define OC_DEVICE_ID3 0xe220 /* Device id for Lancer cards */ | |
12f4d0a8 | 54 | #define OC_DEVICE_ID4 0xe228 /* Device id for VF in Lancer */ |
ecedb6ae | 55 | #define OC_DEVICE_ID5 0x720 /* Device Id for Skyhawk cards */ |
76b73530 | 56 | #define OC_DEVICE_ID6 0x728 /* Device id for VF in SkyHawk */ |
4762f6ce AK |
57 | #define OC_SUBSYS_DEVICE_ID1 0xE602 |
58 | #define OC_SUBSYS_DEVICE_ID2 0xE642 | |
59 | #define OC_SUBSYS_DEVICE_ID3 0xE612 | |
60 | #define OC_SUBSYS_DEVICE_ID4 0xE652 | |
c4ca2374 AK |
61 | |
62 | static inline char *nic_name(struct pci_dev *pdev) | |
63 | { | |
12d7ea2c AK |
64 | switch (pdev->device) { |
65 | case OC_DEVICE_ID1: | |
c4ca2374 | 66 | return OC_NAME; |
e254f6ec | 67 | case OC_DEVICE_ID2: |
fe6d2a38 SP |
68 | return OC_NAME_BE; |
69 | case OC_DEVICE_ID3: | |
12f4d0a8 | 70 | case OC_DEVICE_ID4: |
fe6d2a38 | 71 | return OC_NAME_LANCER; |
12d7ea2c AK |
72 | case BE_DEVICE_ID2: |
73 | return BE3_NAME; | |
ecedb6ae | 74 | case OC_DEVICE_ID5: |
76b73530 | 75 | case OC_DEVICE_ID6: |
ecedb6ae | 76 | return OC_NAME_SH; |
12d7ea2c | 77 | default: |
c4ca2374 | 78 | return BE_NAME; |
12d7ea2c | 79 | } |
c4ca2374 AK |
80 | } |
81 | ||
6b7c5b94 | 82 | /* Number of bytes of an RX frame that are copied to skb->data */ |
2e588f84 | 83 | #define BE_HDR_LEN ((u16) 64) |
bb349bb4 ED |
84 | /* allocate extra space to allow tunneling decapsulation without head reallocation */ |
85 | #define BE_RX_SKB_ALLOC_SIZE (BE_HDR_LEN + 64) | |
86 | ||
6b7c5b94 SP |
87 | #define BE_MAX_JUMBO_FRAME_SIZE 9018 |
88 | #define BE_MIN_MTU 256 | |
89 | ||
90 | #define BE_NUM_VLANS_SUPPORTED 64 | |
10ef9ab4 | 91 | #define BE_MAX_EQD 96u |
6b7c5b94 SP |
92 | #define BE_MAX_TX_FRAG_COUNT 30 |
93 | ||
94 | #define EVNT_Q_LEN 1024 | |
95 | #define TX_Q_LEN 2048 | |
96 | #define TX_CQ_LEN 1024 | |
97 | #define RX_Q_LEN 1024 /* Does not support any other value */ | |
98 | #define RX_CQ_LEN 1024 | |
5fb379ee | 99 | #define MCC_Q_LEN 128 /* total size not to exceed 8 pages */ |
6b7c5b94 SP |
100 | #define MCC_CQ_LEN 256 |
101 | ||
10ef9ab4 SP |
102 | #define BE3_MAX_RSS_QS 8 |
103 | #define BE2_MAX_RSS_QS 4 | |
92bf14ab | 104 | #define BE3_MAX_TX_QS 8 |
10ef9ab4 | 105 | #define MAX_RSS_QS BE3_MAX_RSS_QS |
ac6a0c4a | 106 | #define MAX_RX_QS (MAX_RSS_QS + 1) /* RSS qs + 1 def Rx */ |
92bf14ab | 107 | #define MAX_EVT_QS MAX_RSS_QS |
10ef9ab4 | 108 | |
3c8def97 | 109 | #define MAX_TX_QS 8 |
045508a8 PP |
110 | #define MAX_ROCE_EQS 5 |
111 | #define MAX_MSIX_VECTORS (MAX_RSS_QS + MAX_ROCE_EQS) /* RSS qs + RoCE */ | |
92bf14ab | 112 | #define MIN_MSIX_VECTORS 1 |
10ef9ab4 | 113 | #define BE_TX_BUDGET 256 |
6b7c5b94 | 114 | #define BE_NAPI_WEIGHT 64 |
10ef9ab4 | 115 | #define MAX_RX_POST BE_NAPI_WEIGHT /* Frags posted at a time */ |
6b7c5b94 SP |
116 | #define RX_FRAGS_REFILL_WM (RX_Q_LEN - MAX_RX_POST) |
117 | ||
7c5a5242 | 118 | #define MAX_VFS 30 /* Max VFs supported by BE3 FW */ |
8788fdc2 SP |
119 | #define FW_VER_LEN 32 |
120 | ||
6b7c5b94 SP |
121 | struct be_dma_mem { |
122 | void *va; | |
123 | dma_addr_t dma; | |
124 | u32 size; | |
125 | }; | |
126 | ||
127 | struct be_queue_info { | |
128 | struct be_dma_mem dma_mem; | |
129 | u16 len; | |
130 | u16 entry_size; /* Size of an element in the queue */ | |
131 | u16 id; | |
132 | u16 tail, head; | |
133 | bool created; | |
134 | atomic_t used; /* Number of valid elements in the queue */ | |
135 | }; | |
136 | ||
5fb379ee SP |
137 | static inline u32 MODULO(u16 val, u16 limit) |
138 | { | |
139 | BUG_ON(limit & (limit - 1)); | |
140 | return val & (limit - 1); | |
141 | } | |
142 | ||
143 | static inline void index_adv(u16 *index, u16 val, u16 limit) | |
144 | { | |
145 | *index = MODULO((*index + val), limit); | |
146 | } | |
147 | ||
148 | static inline void index_inc(u16 *index, u16 limit) | |
149 | { | |
150 | *index = MODULO((*index + 1), limit); | |
151 | } | |
152 | ||
153 | static inline void *queue_head_node(struct be_queue_info *q) | |
154 | { | |
155 | return q->dma_mem.va + q->head * q->entry_size; | |
156 | } | |
157 | ||
158 | static inline void *queue_tail_node(struct be_queue_info *q) | |
159 | { | |
160 | return q->dma_mem.va + q->tail * q->entry_size; | |
161 | } | |
162 | ||
3de09455 SK |
163 | static inline void *queue_index_node(struct be_queue_info *q, u16 index) |
164 | { | |
165 | return q->dma_mem.va + index * q->entry_size; | |
166 | } | |
167 | ||
5fb379ee SP |
168 | static inline void queue_head_inc(struct be_queue_info *q) |
169 | { | |
170 | index_inc(&q->head, q->len); | |
171 | } | |
172 | ||
652bf646 PR |
173 | static inline void index_dec(u16 *index, u16 limit) |
174 | { | |
175 | *index = MODULO((*index - 1), limit); | |
176 | } | |
177 | ||
5fb379ee SP |
178 | static inline void queue_tail_inc(struct be_queue_info *q) |
179 | { | |
180 | index_inc(&q->tail, q->len); | |
181 | } | |
182 | ||
5fb379ee SP |
183 | struct be_eq_obj { |
184 | struct be_queue_info q; | |
185 | char desc[32]; | |
186 | ||
187 | /* Adaptive interrupt coalescing (AIC) info */ | |
188 | bool enable_aic; | |
10ef9ab4 SP |
189 | u32 min_eqd; /* in usecs */ |
190 | u32 max_eqd; /* in usecs */ | |
191 | u32 eqd; /* configured val when aic is off */ | |
192 | u32 cur_eqd; /* in usecs */ | |
5fb379ee | 193 | |
10ef9ab4 | 194 | u8 idx; /* array index */ |
f2f781a7 | 195 | u8 msix_idx; |
10ef9ab4 | 196 | u16 tx_budget; |
d0b9cec3 | 197 | u16 spurious_intr; |
5fb379ee | 198 | struct napi_struct napi; |
10ef9ab4 SP |
199 | struct be_adapter *adapter; |
200 | } ____cacheline_aligned_in_smp; | |
5fb379ee SP |
201 | |
202 | struct be_mcc_obj { | |
203 | struct be_queue_info q; | |
204 | struct be_queue_info cq; | |
7a1e9b20 | 205 | bool rearm_cq; |
5fb379ee SP |
206 | }; |
207 | ||
3abcdeda | 208 | struct be_tx_stats { |
ac124ff9 SP |
209 | u64 tx_bytes; |
210 | u64 tx_pkts; | |
211 | u64 tx_reqs; | |
212 | u64 tx_wrbs; | |
213 | u64 tx_compl; | |
214 | ulong tx_jiffies; | |
215 | u32 tx_stops; | |
ab1594e9 SP |
216 | struct u64_stats_sync sync; |
217 | struct u64_stats_sync sync_compl; | |
6b7c5b94 SP |
218 | }; |
219 | ||
6b7c5b94 | 220 | struct be_tx_obj { |
94d73aaa | 221 | u32 db_offset; |
6b7c5b94 SP |
222 | struct be_queue_info q; |
223 | struct be_queue_info cq; | |
224 | /* Remember the skbs that were transmitted */ | |
225 | struct sk_buff *sent_skb_list[TX_Q_LEN]; | |
3c8def97 | 226 | struct be_tx_stats stats; |
10ef9ab4 | 227 | } ____cacheline_aligned_in_smp; |
6b7c5b94 SP |
228 | |
229 | /* Struct to remember the pages posted for rx frags */ | |
230 | struct be_rx_page_info { | |
231 | struct page *page; | |
fac6da5b | 232 | DEFINE_DMA_UNMAP_ADDR(bus); |
6b7c5b94 SP |
233 | u16 page_offset; |
234 | bool last_page_user; | |
235 | }; | |
236 | ||
3abcdeda | 237 | struct be_rx_stats { |
3abcdeda | 238 | u64 rx_bytes; |
3abcdeda | 239 | u64 rx_pkts; |
ac124ff9 SP |
240 | u64 rx_pkts_prev; |
241 | ulong rx_jiffies; | |
242 | u32 rx_drops_no_skbs; /* skb allocation errors */ | |
243 | u32 rx_drops_no_frags; /* HW has no fetched frags */ | |
244 | u32 rx_post_fail; /* page post alloc failures */ | |
ac124ff9 | 245 | u32 rx_compl; |
3abcdeda | 246 | u32 rx_mcast_pkts; |
ac124ff9 SP |
247 | u32 rx_compl_err; /* completions with err set */ |
248 | u32 rx_pps; /* pkts per second */ | |
ab1594e9 | 249 | struct u64_stats_sync sync; |
3abcdeda SP |
250 | }; |
251 | ||
2e588f84 SP |
252 | struct be_rx_compl_info { |
253 | u32 rss_hash; | |
6709d952 | 254 | u16 vlan_tag; |
2e588f84 SP |
255 | u16 pkt_size; |
256 | u16 rxq_idx; | |
12004ae9 | 257 | u16 port; |
2e588f84 SP |
258 | u8 vlanf; |
259 | u8 num_rcvd; | |
260 | u8 err; | |
261 | u8 ipf; | |
262 | u8 tcpf; | |
263 | u8 udpf; | |
264 | u8 ip_csum; | |
265 | u8 l4_csum; | |
266 | u8 ipv6; | |
267 | u8 vtm; | |
268 | u8 pkt_type; | |
e38b1706 | 269 | u8 ip_frag; |
2e588f84 SP |
270 | }; |
271 | ||
6b7c5b94 | 272 | struct be_rx_obj { |
3abcdeda | 273 | struct be_adapter *adapter; |
6b7c5b94 SP |
274 | struct be_queue_info q; |
275 | struct be_queue_info cq; | |
2e588f84 | 276 | struct be_rx_compl_info rxcp; |
6b7c5b94 | 277 | struct be_rx_page_info page_info_tbl[RX_Q_LEN]; |
3abcdeda SP |
278 | struct be_rx_stats stats; |
279 | u8 rss_id; | |
280 | bool rx_post_starved; /* Zero rx frags have been posted to BE */ | |
10ef9ab4 | 281 | } ____cacheline_aligned_in_smp; |
6b7c5b94 | 282 | |
609ff3bb | 283 | struct be_drv_stats { |
9ae081c6 | 284 | u32 be_on_die_temperature; |
ac124ff9 SP |
285 | u32 eth_red_drops; |
286 | u32 rx_drops_no_pbuf; | |
287 | u32 rx_drops_no_txpb; | |
288 | u32 rx_drops_no_erx_descr; | |
289 | u32 rx_drops_no_tpre_descr; | |
290 | u32 rx_drops_too_many_frags; | |
ac124ff9 SP |
291 | u32 forwarded_packets; |
292 | u32 rx_drops_mtu; | |
293 | u32 rx_crc_errors; | |
294 | u32 rx_alignment_symbol_errors; | |
295 | u32 rx_pause_frames; | |
296 | u32 rx_priority_pause_frames; | |
297 | u32 rx_control_frames; | |
298 | u32 rx_in_range_errors; | |
299 | u32 rx_out_range_errors; | |
300 | u32 rx_frame_too_long; | |
18fb06a1 | 301 | u32 rx_address_filtered; |
ac124ff9 SP |
302 | u32 rx_dropped_too_small; |
303 | u32 rx_dropped_too_short; | |
304 | u32 rx_dropped_header_too_small; | |
305 | u32 rx_dropped_tcp_length; | |
306 | u32 rx_dropped_runt; | |
307 | u32 rx_ip_checksum_errs; | |
308 | u32 rx_tcp_checksum_errs; | |
309 | u32 rx_udp_checksum_errs; | |
310 | u32 tx_pauseframes; | |
311 | u32 tx_priority_pauseframes; | |
312 | u32 tx_controlframes; | |
313 | u32 rxpp_fifo_overflow_drop; | |
314 | u32 rx_input_fifo_overflow_drop; | |
315 | u32 pmem_fifo_overflow_drop; | |
316 | u32 jabber_events; | |
609ff3bb AK |
317 | }; |
318 | ||
64600ea5 | 319 | struct be_vf_cfg { |
11ac75ed SP |
320 | unsigned char mac_addr[ETH_ALEN]; |
321 | int if_handle; | |
322 | int pmac_id; | |
f1f3ee1b | 323 | u16 def_vid; |
11ac75ed SP |
324 | u16 vlan_tag; |
325 | u32 tx_rate; | |
64600ea5 AK |
326 | }; |
327 | ||
39f1d94d SP |
328 | enum vf_state { |
329 | ENABLED = 0, | |
330 | ASSIGNED = 1 | |
331 | }; | |
332 | ||
b236916a | 333 | #define BE_FLAGS_LINK_STATUS_INIT 1 |
191eb756 | 334 | #define BE_FLAGS_WORKER_SCHEDULED (1 << 3) |
04d3d624 | 335 | #define BE_FLAGS_NAPI_ENABLED (1 << 9) |
fbc13f01 AK |
336 | #define BE_UC_PMAC_COUNT 30 |
337 | #define BE_VF_UC_PMAC_COUNT 2 | |
bc0c3405 | 338 | #define BE_FLAGS_QNQ_ASYNC_EVT_RCVD (1 << 11) |
b236916a | 339 | |
5c510811 SK |
340 | /* Ethtool set_dump flags */ |
341 | #define LANCER_INITIATE_FW_DUMP 0x1 | |
342 | ||
42f11cf2 AK |
343 | struct phy_info { |
344 | u8 transceiver; | |
345 | u8 autoneg; | |
346 | u8 fc_autoneg; | |
347 | u8 port_type; | |
348 | u16 phy_type; | |
349 | u16 interface_type; | |
350 | u32 misc_params; | |
351 | u16 auto_speeds_supported; | |
352 | u16 fixed_speeds_supported; | |
353 | int link_speed; | |
42f11cf2 AK |
354 | u32 dac_cable_len; |
355 | u32 advertising; | |
356 | u32 supported; | |
357 | }; | |
358 | ||
92bf14ab SP |
359 | struct be_resources { |
360 | u16 max_vfs; /* Total VFs "really" supported by FW/HW */ | |
361 | u16 max_mcast_mac; | |
362 | u16 max_tx_qs; | |
363 | u16 max_rss_qs; | |
364 | u16 max_rx_qs; | |
365 | u16 max_uc_mac; /* Max UC MACs programmable */ | |
366 | u16 max_vlans; /* Number of vlans supported */ | |
367 | u16 max_evt_qs; | |
368 | u32 if_cap_flags; | |
369 | }; | |
370 | ||
6b7c5b94 SP |
371 | struct be_adapter { |
372 | struct pci_dev *pdev; | |
373 | struct net_device *netdev; | |
374 | ||
c5b3ad4c | 375 | u8 __iomem *csr; /* CSR BAR used only for BE2/3 */ |
8788fdc2 | 376 | u8 __iomem *db; /* Door Bell */ |
8788fdc2 | 377 | |
2984961c | 378 | struct mutex mbox_lock; /* For serializing mbox cmds to BE card */ |
8788fdc2 SP |
379 | struct be_dma_mem mbox_mem; |
380 | /* Mbox mem is adjusted to align to 16 bytes. The allocated addr | |
381 | * is stored for freeing purpose */ | |
382 | struct be_dma_mem mbox_mem_alloced; | |
383 | ||
384 | struct be_mcc_obj mcc_obj; | |
385 | spinlock_t mcc_lock; /* For serializing mcc cmds to BE card */ | |
386 | spinlock_t mcc_cq_lock; | |
6b7c5b94 | 387 | |
92bf14ab SP |
388 | u16 cfg_num_qs; /* configured via set-channels */ |
389 | u16 num_evt_qs; | |
390 | u16 num_msix_vec; | |
391 | struct be_eq_obj eq_obj[MAX_EVT_QS]; | |
10ef9ab4 | 392 | struct msix_entry msix_entries[MAX_MSIX_VECTORS]; |
6b7c5b94 SP |
393 | bool isr_registered; |
394 | ||
395 | /* TX Rings */ | |
92bf14ab | 396 | u16 num_tx_qs; |
3c8def97 | 397 | struct be_tx_obj tx_obj[MAX_TX_QS]; |
6b7c5b94 SP |
398 | |
399 | /* Rx rings */ | |
92bf14ab | 400 | u16 num_rx_qs; |
10ef9ab4 | 401 | struct be_rx_obj rx_obj[MAX_RX_QS]; |
6b7c5b94 SP |
402 | u32 big_page_size; /* Compounded page size shared by rx wrbs */ |
403 | ||
609ff3bb | 404 | struct be_drv_stats drv_stats; |
82903e4b | 405 | u16 vlans_added; |
b738127d | 406 | u8 vlan_tag[VLAN_N_VID]; |
cc4ce020 SK |
407 | u8 vlan_prio_bmap; /* Available Priority BitMap */ |
408 | u16 recommended_prio; /* Recommended Priority */ | |
5b8821b7 | 409 | struct be_dma_mem rx_filter; /* Cmd DMA mem for rx-filter */ |
6b7c5b94 | 410 | |
3abcdeda | 411 | struct be_dma_mem stats_cmd; |
6b7c5b94 SP |
412 | /* Work queue used to perform periodic tasks like getting statistics */ |
413 | struct delayed_work work; | |
609ff3bb | 414 | u16 work_counter; |
6b7c5b94 | 415 | |
f67ef7ba | 416 | struct delayed_work func_recovery_work; |
b236916a | 417 | u32 flags; |
f25b119c | 418 | u32 cmd_privileges; |
6b7c5b94 | 419 | /* Ethtool knobs and info */ |
6b7c5b94 | 420 | char fw_ver[FW_VER_LEN]; |
eeb65ced | 421 | char fw_on_flash[FW_VER_LEN]; |
30128031 | 422 | int if_handle; /* Used to configure filtering */ |
fbc13f01 | 423 | u32 *pmac_id; /* MAC addr handle used by BE card */ |
1a642469 | 424 | u32 beacon_state; /* for set_phys_id */ |
6b7c5b94 | 425 | |
f67ef7ba | 426 | bool eeh_error; |
6589ade0 | 427 | bool fw_timeout; |
f67ef7ba PR |
428 | bool hw_error; |
429 | ||
6b7c5b94 | 430 | u32 port_num; |
24307eef | 431 | bool promiscuous; |
3486be29 | 432 | u32 function_mode; |
3abcdeda | 433 | u32 function_caps; |
9e90c961 AK |
434 | u32 rx_fc; /* Rx flow control */ |
435 | u32 tx_fc; /* Tx flow control */ | |
b2aebe6d | 436 | bool stats_cmd_sent; |
045508a8 PP |
437 | u32 if_type; |
438 | struct { | |
045508a8 PP |
439 | u32 size; |
440 | u32 total_size; | |
441 | u64 io_addr; | |
442 | } roce_db; | |
443 | u32 num_msix_roce_vec; | |
444 | struct ocrdma_dev *ocrdma_dev; | |
445 | struct list_head entry; | |
446 | ||
dd131e76 SB |
447 | u32 flash_status; |
448 | struct completion flash_compl; | |
ba343c77 | 449 | |
92bf14ab SP |
450 | struct be_resources res; /* resources available for the func */ |
451 | u16 num_vfs; /* Number of VFs provisioned by PF */ | |
39f1d94d | 452 | u8 virtfn; |
11ac75ed SP |
453 | struct be_vf_cfg *vf_cfg; |
454 | bool be3_native; | |
fe6d2a38 | 455 | u32 sli_family; |
9e1453c5 | 456 | u8 hba_port_num; |
3968fa1e | 457 | u16 pvid; |
42f11cf2 | 458 | struct phy_info phy; |
4762f6ce AK |
459 | u8 wol_cap; |
460 | bool wol; | |
fbc13f01 | 461 | u32 uc_macs; /* Count of secondary UC MAC programmed */ |
0ad3157e | 462 | u16 asic_rev; |
bc0c3405 | 463 | u16 qnq_vid; |
941a77d5 | 464 | u32 msg_enable; |
7aeb2156 | 465 | int be_get_temp_freq; |
d5c18473 | 466 | u8 pf_number; |
594ad54a | 467 | u64 rss_flags; |
6b7c5b94 SP |
468 | }; |
469 | ||
39f1d94d | 470 | #define be_physfn(adapter) (!adapter->virtfn) |
11ac75ed | 471 | #define sriov_enabled(adapter) (adapter->num_vfs > 0) |
92bf14ab | 472 | #define sriov_want(adapter) (be_max_vfs(adapter) && num_vfs && \ |
39f1d94d | 473 | be_physfn(adapter)) |
11ac75ed SP |
474 | #define for_all_vfs(adapter, vf_cfg, i) \ |
475 | for (i = 0, vf_cfg = &adapter->vf_cfg[i]; i < adapter->num_vfs; \ | |
476 | i++, vf_cfg++) | |
ba343c77 | 477 | |
5b8821b7 SP |
478 | #define ON 1 |
479 | #define OFF 0 | |
ca34fe38 | 480 | |
92bf14ab SP |
481 | #define be_max_vlans(adapter) (adapter->res.max_vlans) |
482 | #define be_max_uc(adapter) (adapter->res.max_uc_mac) | |
483 | #define be_max_mc(adapter) (adapter->res.max_mcast_mac) | |
484 | #define be_max_vfs(adapter) (adapter->res.max_vfs) | |
485 | #define be_max_rss(adapter) (adapter->res.max_rss_qs) | |
486 | #define be_max_txqs(adapter) (adapter->res.max_tx_qs) | |
487 | #define be_max_prio_txqs(adapter) (adapter->res.max_prio_tx_qs) | |
488 | #define be_max_rxqs(adapter) (adapter->res.max_rx_qs) | |
489 | #define be_max_eqs(adapter) (adapter->res.max_evt_qs) | |
490 | #define be_if_cap_flags(adapter) (adapter->res.if_cap_flags) | |
491 | ||
492 | static inline u16 be_max_qs(struct be_adapter *adapter) | |
493 | { | |
494 | /* If no RSS, need atleast the one def RXQ */ | |
495 | u16 num = max_t(u16, be_max_rss(adapter), 1); | |
496 | ||
497 | num = min(num, be_max_eqs(adapter)); | |
498 | return min_t(u16, num, num_online_cpus()); | |
499 | } | |
500 | ||
ca34fe38 SP |
501 | #define lancer_chip(adapter) (adapter->pdev->device == OC_DEVICE_ID3 || \ |
502 | adapter->pdev->device == OC_DEVICE_ID4) | |
fe6d2a38 | 503 | |
76b73530 PR |
504 | #define skyhawk_chip(adapter) (adapter->pdev->device == OC_DEVICE_ID5 || \ |
505 | adapter->pdev->device == OC_DEVICE_ID6) | |
d3bd3a5e | 506 | |
ca34fe38 SP |
507 | #define BE3_chip(adapter) (adapter->pdev->device == BE_DEVICE_ID2 || \ |
508 | adapter->pdev->device == OC_DEVICE_ID2) | |
509 | ||
510 | #define BE2_chip(adapter) (adapter->pdev->device == BE_DEVICE_ID1 || \ | |
511 | adapter->pdev->device == OC_DEVICE_ID1) | |
512 | ||
513 | #define BEx_chip(adapter) (BE3_chip(adapter) || BE2_chip(adapter)) | |
d3bd3a5e | 514 | |
dbf0f2a7 SP |
515 | #define be_roce_supported(adapter) (skyhawk_chip(adapter) && \ |
516 | (adapter->function_mode & RDMA_ENABLED)) | |
045508a8 | 517 | |
0fc0b732 | 518 | extern const struct ethtool_ops be_ethtool_ops; |
6b7c5b94 | 519 | |
ac6a0c4a | 520 | #define msix_enabled(adapter) (adapter->num_msix_vec > 0) |
10ef9ab4 SP |
521 | #define num_irqs(adapter) (msix_enabled(adapter) ? \ |
522 | adapter->num_msix_vec : 1) | |
523 | #define tx_stats(txo) (&(txo)->stats) | |
524 | #define rx_stats(rxo) (&(rxo)->stats) | |
6b7c5b94 | 525 | |
10ef9ab4 SP |
526 | /* The default RXQ is the last RXQ */ |
527 | #define default_rxo(adpt) (&adpt->rx_obj[adpt->num_rx_qs - 1]) | |
6b7c5b94 | 528 | |
3abcdeda SP |
529 | #define for_all_rx_queues(adapter, rxo, i) \ |
530 | for (i = 0, rxo = &adapter->rx_obj[i]; i < adapter->num_rx_qs; \ | |
531 | i++, rxo++) | |
532 | ||
10ef9ab4 | 533 | /* Skip the default non-rss queue (last one)*/ |
3abcdeda | 534 | #define for_all_rss_queues(adapter, rxo, i) \ |
10ef9ab4 | 535 | for (i = 0, rxo = &adapter->rx_obj[i]; i < (adapter->num_rx_qs - 1);\ |
3abcdeda SP |
536 | i++, rxo++) |
537 | ||
3c8def97 SP |
538 | #define for_all_tx_queues(adapter, txo, i) \ |
539 | for (i = 0, txo = &adapter->tx_obj[i]; i < adapter->num_tx_qs; \ | |
540 | i++, txo++) | |
541 | ||
10ef9ab4 SP |
542 | #define for_all_evt_queues(adapter, eqo, i) \ |
543 | for (i = 0, eqo = &adapter->eq_obj[i]; i < adapter->num_evt_qs; \ | |
544 | i++, eqo++) | |
545 | ||
546 | #define is_mcc_eqo(eqo) (eqo->idx == 0) | |
547 | #define mcc_eqo(adapter) (&adapter->eq_obj[0]) | |
548 | ||
6b7c5b94 SP |
549 | #define PAGE_SHIFT_4K 12 |
550 | #define PAGE_SIZE_4K (1 << PAGE_SHIFT_4K) | |
551 | ||
552 | /* Returns number of pages spanned by the data starting at the given addr */ | |
553 | #define PAGES_4K_SPANNED(_address, size) \ | |
554 | ((u32)((((size_t)(_address) & (PAGE_SIZE_4K - 1)) + \ | |
555 | (size) + (PAGE_SIZE_4K - 1)) >> PAGE_SHIFT_4K)) | |
556 | ||
6b7c5b94 SP |
557 | /* Returns bit offset within a DWORD of a bitfield */ |
558 | #define AMAP_BIT_OFFSET(_struct, field) \ | |
559 | (((size_t)&(((_struct *)0)->field))%32) | |
560 | ||
561 | /* Returns the bit mask of the field that is NOT shifted into location. */ | |
562 | static inline u32 amap_mask(u32 bitsize) | |
563 | { | |
564 | return (bitsize == 32 ? 0xFFFFFFFF : (1 << bitsize) - 1); | |
565 | } | |
566 | ||
567 | static inline void | |
568 | amap_set(void *ptr, u32 dw_offset, u32 mask, u32 offset, u32 value) | |
569 | { | |
570 | u32 *dw = (u32 *) ptr + dw_offset; | |
571 | *dw &= ~(mask << offset); | |
572 | *dw |= (mask & value) << offset; | |
573 | } | |
574 | ||
575 | #define AMAP_SET_BITS(_struct, field, ptr, val) \ | |
576 | amap_set(ptr, \ | |
577 | offsetof(_struct, field)/32, \ | |
578 | amap_mask(sizeof(((_struct *)0)->field)), \ | |
579 | AMAP_BIT_OFFSET(_struct, field), \ | |
580 | val) | |
581 | ||
582 | static inline u32 amap_get(void *ptr, u32 dw_offset, u32 mask, u32 offset) | |
583 | { | |
584 | u32 *dw = (u32 *) ptr; | |
585 | return mask & (*(dw + dw_offset) >> offset); | |
586 | } | |
587 | ||
588 | #define AMAP_GET_BITS(_struct, field, ptr) \ | |
589 | amap_get(ptr, \ | |
590 | offsetof(_struct, field)/32, \ | |
591 | amap_mask(sizeof(((_struct *)0)->field)), \ | |
592 | AMAP_BIT_OFFSET(_struct, field)) | |
593 | ||
594 | #define be_dws_cpu_to_le(wrb, len) swap_dws(wrb, len) | |
595 | #define be_dws_le_to_cpu(wrb, len) swap_dws(wrb, len) | |
596 | static inline void swap_dws(void *wrb, int len) | |
597 | { | |
598 | #ifdef __BIG_ENDIAN | |
599 | u32 *dw = wrb; | |
600 | BUG_ON(len % 4); | |
601 | do { | |
602 | *dw = cpu_to_le32(*dw); | |
603 | dw++; | |
604 | len -= 4; | |
605 | } while (len); | |
606 | #endif /* __BIG_ENDIAN */ | |
607 | } | |
608 | ||
609 | static inline u8 is_tcp_pkt(struct sk_buff *skb) | |
610 | { | |
611 | u8 val = 0; | |
612 | ||
613 | if (ip_hdr(skb)->version == 4) | |
614 | val = (ip_hdr(skb)->protocol == IPPROTO_TCP); | |
615 | else if (ip_hdr(skb)->version == 6) | |
616 | val = (ipv6_hdr(skb)->nexthdr == NEXTHDR_TCP); | |
617 | ||
618 | return val; | |
619 | } | |
620 | ||
621 | static inline u8 is_udp_pkt(struct sk_buff *skb) | |
622 | { | |
623 | u8 val = 0; | |
624 | ||
625 | if (ip_hdr(skb)->version == 4) | |
626 | val = (ip_hdr(skb)->protocol == IPPROTO_UDP); | |
627 | else if (ip_hdr(skb)->version == 6) | |
628 | val = (ipv6_hdr(skb)->nexthdr == NEXTHDR_UDP); | |
629 | ||
630 | return val; | |
631 | } | |
632 | ||
93040ae5 SK |
633 | static inline bool is_ipv4_pkt(struct sk_buff *skb) |
634 | { | |
e8efcec5 | 635 | return skb->protocol == htons(ETH_P_IP) && ip_hdr(skb)->version == 4; |
93040ae5 SK |
636 | } |
637 | ||
6d87f5c3 AK |
638 | static inline void be_vf_eth_addr_generate(struct be_adapter *adapter, u8 *mac) |
639 | { | |
640 | u32 addr; | |
641 | ||
642 | addr = jhash(adapter->netdev->dev_addr, ETH_ALEN, 0); | |
643 | ||
644 | mac[5] = (u8)(addr & 0xFF); | |
645 | mac[4] = (u8)((addr >> 8) & 0xFF); | |
646 | mac[3] = (u8)((addr >> 16) & 0xFF); | |
7a2414a5 AK |
647 | /* Use the OUI from the current MAC address */ |
648 | memcpy(mac, adapter->netdev->dev_addr, 3); | |
6d87f5c3 AK |
649 | } |
650 | ||
4b972914 AK |
651 | static inline bool be_multi_rxq(const struct be_adapter *adapter) |
652 | { | |
653 | return adapter->num_rx_qs > 1; | |
654 | } | |
655 | ||
6589ade0 SP |
656 | static inline bool be_error(struct be_adapter *adapter) |
657 | { | |
f67ef7ba PR |
658 | return adapter->eeh_error || adapter->hw_error || adapter->fw_timeout; |
659 | } | |
660 | ||
d23e946c | 661 | static inline bool be_hw_error(struct be_adapter *adapter) |
f67ef7ba PR |
662 | { |
663 | return adapter->eeh_error || adapter->hw_error; | |
664 | } | |
665 | ||
666 | static inline void be_clear_all_error(struct be_adapter *adapter) | |
667 | { | |
668 | adapter->eeh_error = false; | |
669 | adapter->hw_error = false; | |
670 | adapter->fw_timeout = false; | |
6589ade0 SP |
671 | } |
672 | ||
4762f6ce AK |
673 | static inline bool be_is_wol_excluded(struct be_adapter *adapter) |
674 | { | |
675 | struct pci_dev *pdev = adapter->pdev; | |
676 | ||
677 | if (!be_physfn(adapter)) | |
678 | return true; | |
679 | ||
680 | switch (pdev->subsystem_device) { | |
681 | case OC_SUBSYS_DEVICE_ID1: | |
682 | case OC_SUBSYS_DEVICE_ID2: | |
683 | case OC_SUBSYS_DEVICE_ID3: | |
684 | case OC_SUBSYS_DEVICE_ID4: | |
685 | return true; | |
686 | default: | |
687 | return false; | |
688 | } | |
689 | } | |
690 | ||
bc0c3405 AK |
691 | static inline int qnq_async_evt_rcvd(struct be_adapter *adapter) |
692 | { | |
693 | return adapter->flags & BE_FLAGS_QNQ_ASYNC_EVT_RCVD; | |
694 | } | |
695 | ||
8788fdc2 | 696 | extern void be_cq_notify(struct be_adapter *adapter, u16 qid, bool arm, |
5fb379ee | 697 | u16 num_popped); |
b236916a | 698 | extern void be_link_status_update(struct be_adapter *adapter, u8 link_status); |
89a88ab8 | 699 | extern void be_parse_stats(struct be_adapter *adapter); |
84517482 | 700 | extern int be_load_fw(struct be_adapter *adapter, u8 *func); |
4762f6ce | 701 | extern bool be_is_wol_supported(struct be_adapter *adapter); |
42f11cf2 | 702 | extern bool be_pause_supported(struct be_adapter *adapter); |
941a77d5 SK |
703 | extern u32 be_get_fw_log_level(struct be_adapter *adapter); |
704 | ||
045508a8 PP |
705 | /* |
706 | * internal function to initialize-cleanup roce device. | |
707 | */ | |
708 | extern void be_roce_dev_add(struct be_adapter *); | |
709 | extern void be_roce_dev_remove(struct be_adapter *); | |
710 | ||
711 | /* | |
712 | * internal function to open-close roce device during ifup-ifdown. | |
713 | */ | |
714 | extern void be_roce_dev_open(struct be_adapter *); | |
715 | extern void be_roce_dev_close(struct be_adapter *); | |
716 | ||
6b7c5b94 | 717 | #endif /* BE_H */ |