[deliverable/linux.git] / drivers / net / ethernet / emulex / benet / be.h

/*
 * Copyright (C) 2005 - 2011 Emulex
 * All rights reserved.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License version 2
 * as published by the Free Software Foundation.  The full GNU General
 * Public License is included in this distribution in the file called COPYING.
 *
 * Contact Information:
 * linux-drivers@emulex.com
 *
 * Emulex
 * 3333 Susan Street
 * Costa Mesa, CA 92626
 */

#ifndef BE_H
#define BE_H

#include <linux/pci.h>
#include <linux/etherdevice.h>
#include <linux/delay.h>
#include <net/tcp.h>
#include <net/ip.h>
#include <net/ipv6.h>
#include <linux/if_vlan.h>
#include <linux/workqueue.h>
#include <linux/interrupt.h>
#include <linux/firmware.h>
#include <linux/slab.h>
#include <linux/u64_stats_sync.h>

#include "be_hw.h"

#define DRV_VER			"4.2.220u"
#define DRV_NAME		"be2net"
#define BE_NAME			"ServerEngines BladeEngine2 10Gbps NIC"
#define BE3_NAME		"ServerEngines BladeEngine3 10Gbps NIC"
#define OC_NAME			"Emulex OneConnect 10Gbps NIC"
#define OC_NAME_BE		OC_NAME	"(be3)"
#define OC_NAME_LANCER		OC_NAME "(Lancer)"
#define OC_NAME_SH		OC_NAME "(Skyhawk)"
#define DRV_DESC		"ServerEngines BladeEngine 10Gbps NIC Driver"

#define BE_VENDOR_ID 		0x19a2
#define EMULEX_VENDOR_ID	0x10df
#define BE_DEVICE_ID1		0x211
#define BE_DEVICE_ID2		0x221
#define OC_DEVICE_ID1		0x700	/* Device Id for BE2 cards */
#define OC_DEVICE_ID2		0x710	/* Device Id for BE3 cards */
#define OC_DEVICE_ID3		0xe220	/* Device id for Lancer cards */
#define OC_DEVICE_ID4           0xe228   /* Device id for VF in Lancer */
#define OC_DEVICE_ID5		0x720	/* Device Id for Skyhawk cards */
#define OC_SUBSYS_DEVICE_ID1	0xE602
#define OC_SUBSYS_DEVICE_ID2	0xE642
#define OC_SUBSYS_DEVICE_ID3	0xE612
#define OC_SUBSYS_DEVICE_ID4	0xE652

static inline char *nic_name(struct pci_dev *pdev)
{
	switch (pdev->device) {
	case OC_DEVICE_ID1:
		return OC_NAME;
	case OC_DEVICE_ID2:
		return OC_NAME_BE;
	case OC_DEVICE_ID3:
	case OC_DEVICE_ID4:
		return OC_NAME_LANCER;
	case BE_DEVICE_ID2:
		return BE3_NAME;
	case OC_DEVICE_ID5:
		return OC_NAME_SH;
	default:
		return BE_NAME;
	}
}

/* Number of bytes of an RX frame that are copied to skb->data */
#define BE_HDR_LEN		((u16) 64)
/* allocate extra space to allow tunneling decapsulation without head reallocation */
#define BE_RX_SKB_ALLOC_SIZE (BE_HDR_LEN + 64)

#define BE_MAX_JUMBO_FRAME_SIZE	9018
#define BE_MIN_MTU		256

#define BE_NUM_VLANS_SUPPORTED	64
#define BE_MAX_EQD		96u
#define	BE_MAX_TX_FRAG_COUNT	30

#define EVNT_Q_LEN		1024
#define TX_Q_LEN		2048
#define TX_CQ_LEN		1024
#define RX_Q_LEN		1024	/* Does not support any other value */
#define RX_CQ_LEN		1024
#define MCC_Q_LEN		128	/* total size not to exceed 8 pages */
#define MCC_CQ_LEN		256

#define BE3_MAX_RSS_QS		8
#define BE2_MAX_RSS_QS		4
#define MAX_RSS_QS		BE3_MAX_RSS_QS
#define MAX_RX_QS		(MAX_RSS_QS + 1) /* RSS qs + 1 def Rx */

#define MAX_TX_QS		8
#define MAX_MSIX_VECTORS	MAX_RSS_QS
#define BE_TX_BUDGET		256
#define BE_NAPI_WEIGHT		64
#define MAX_RX_POST		BE_NAPI_WEIGHT /* Frags posted at a time */
#define RX_FRAGS_REFILL_WM	(RX_Q_LEN - MAX_RX_POST)

#define FW_VER_LEN		32

struct be_dma_mem {
	void *va;
	dma_addr_t dma;
	u32 size;
};

struct be_queue_info {
	struct be_dma_mem dma_mem;
	u16 len;
	u16 entry_size;	/* Size of an element in the queue */
	u16 id;
	u16 tail, head;
	bool created;
	atomic_t used;	/* Number of valid elements in the queue */
};

static inline u32 MODULO(u16 val, u16 limit)
{
	BUG_ON(limit & (limit - 1));
	return val & (limit - 1);
}

static inline void index_adv(u16 *index, u16 val, u16 limit)
{
	*index = MODULO((*index + val), limit);
}

static inline void index_inc(u16 *index, u16 limit)
{
	*index = MODULO((*index + 1), limit);
}

static inline void *queue_head_node(struct be_queue_info *q)
{
	return q->dma_mem.va + q->head * q->entry_size;
}

static inline void *queue_tail_node(struct be_queue_info *q)
{
	return q->dma_mem.va + q->tail * q->entry_size;
}

static inline void *queue_index_node(struct be_queue_info *q, u16 index)
{
	return q->dma_mem.va + index * q->entry_size;
}

static inline void queue_head_inc(struct be_queue_info *q)
{
	index_inc(&q->head, q->len);
}

static inline void index_dec(u16 *index, u16 limit)
{
	*index = MODULO((*index - 1), limit);
}

static inline void queue_tail_inc(struct be_queue_info *q)
{
	index_inc(&q->tail, q->len);
}

struct be_eq_obj {
	struct be_queue_info q;
	char desc[32];

	/* Adaptive interrupt coalescing (AIC) info */
	bool enable_aic;
	u32 min_eqd;		/* in usecs */
	u32 max_eqd;		/* in usecs */
	u32 eqd;		/* configured val when aic is off */
	u32 cur_eqd;		/* in usecs */

	u8 idx;			/* array index */
	u16 tx_budget;
	struct napi_struct napi;
	struct be_adapter *adapter;
} ____cacheline_aligned_in_smp;

struct be_mcc_obj {
	struct be_queue_info q;
	struct be_queue_info cq;
	bool rearm_cq;
};

struct be_tx_stats {
	u64 tx_bytes;
	u64 tx_pkts;
	u64 tx_reqs;
	u64 tx_wrbs;
	u64 tx_compl;
	ulong tx_jiffies;
	u32 tx_stops;
	struct u64_stats_sync sync;
	struct u64_stats_sync sync_compl;
};

struct be_tx_obj {
	struct be_queue_info q;
	struct be_queue_info cq;
	/* Remember the skbs that were transmitted */
	struct sk_buff *sent_skb_list[TX_Q_LEN];
	struct be_tx_stats stats;
} ____cacheline_aligned_in_smp;

/* Struct to remember the pages posted for rx frags */
struct be_rx_page_info {
	struct page *page;
	DEFINE_DMA_UNMAP_ADDR(bus);
	u16 page_offset;
	bool last_page_user;
};

struct be_rx_stats {
	u64 rx_bytes;
	u64 rx_pkts;
	u64 rx_pkts_prev;
	ulong rx_jiffies;
	u32 rx_drops_no_skbs;	/* skb allocation errors */
	u32 rx_drops_no_frags;	/* HW has no fetched frags */
	u32 rx_post_fail;	/* page post alloc failures */
	u32 rx_compl;
	u32 rx_mcast_pkts;
	u32 rx_compl_err;	/* completions with err set */
	u32 rx_pps;		/* pkts per second */
	struct u64_stats_sync sync;
};

struct be_rx_compl_info {
	u32 rss_hash;
	u16 vlan_tag;
	u16 pkt_size;
	u16 rxq_idx;
	u16 port;
	u8 vlanf;
	u8 num_rcvd;
	u8 err;
	u8 ipf;
	u8 tcpf;
	u8 udpf;
	u8 ip_csum;
	u8 l4_csum;
	u8 ipv6;
	u8 vtm;
	u8 pkt_type;
};

struct be_rx_obj {
	struct be_adapter *adapter;
	struct be_queue_info q;
	struct be_queue_info cq;
	struct be_rx_compl_info rxcp;
	struct be_rx_page_info page_info_tbl[RX_Q_LEN];
	struct be_rx_stats stats;
	u8 rss_id;
	bool rx_post_starved;	/* Zero rx frags have been posted to BE */
} ____cacheline_aligned_in_smp;

struct be_drv_stats {
	u32 be_on_die_temperature;
	u32 eth_red_drops;
	u32 rx_drops_no_pbuf;
	u32 rx_drops_no_txpb;
	u32 rx_drops_no_erx_descr;
	u32 rx_drops_no_tpre_descr;
	u32 rx_drops_too_many_frags;
	u32 forwarded_packets;
	u32 rx_drops_mtu;
	u32 rx_crc_errors;
	u32 rx_alignment_symbol_errors;
	u32 rx_pause_frames;
	u32 rx_priority_pause_frames;
	u32 rx_control_frames;
	u32 rx_in_range_errors;
	u32 rx_out_range_errors;
	u32 rx_frame_too_long;
	u32 rx_address_mismatch_drops;
	u32 rx_dropped_too_small;
	u32 rx_dropped_too_short;
	u32 rx_dropped_header_too_small;
	u32 rx_dropped_tcp_length;
	u32 rx_dropped_runt;
	u32 rx_ip_checksum_errs;
	u32 rx_tcp_checksum_errs;
	u32 rx_udp_checksum_errs;
	u32 tx_pauseframes;
	u32 tx_priority_pauseframes;
	u32 tx_controlframes;
	u32 rxpp_fifo_overflow_drop;
	u32 rx_input_fifo_overflow_drop;
	u32 pmem_fifo_overflow_drop;
	u32 jabber_events;
};

struct be_vf_cfg {
	unsigned char mac_addr[ETH_ALEN];
	int if_handle;
	int pmac_id;
	u16 def_vid;
	u16 vlan_tag;
	u32 tx_rate;
};

enum vf_state {
	ENABLED = 0,
	ASSIGNED = 1
};

#define BE_FLAGS_LINK_STATUS_INIT		1
#define BE_FLAGS_WORKER_SCHEDULED		(1 << 3)
#define BE_UC_PMAC_COUNT		30
#define BE_VF_UC_PMAC_COUNT		2

struct phy_info {
	u8 transceiver;
	u8 autoneg;
	u8 fc_autoneg;
	u8 port_type;
	u16 phy_type;
	u16 interface_type;
	u32 misc_params;
	u16 auto_speeds_supported;
	u16 fixed_speeds_supported;
	int link_speed;
	int forced_port_speed;
	u32 dac_cable_len;
	u32 advertising;
	u32 supported;
};

struct be_adapter {
	struct pci_dev *pdev;
	struct net_device *netdev;

	u8 __iomem *csr;
	u8 __iomem *db;		/* Door Bell */

	struct mutex mbox_lock; /* For serializing mbox cmds to BE card */
	struct be_dma_mem mbox_mem;
	/* Mbox mem is adjusted to align to 16 bytes. The allocated addr
	 * is stored for freeing purpose */
	struct be_dma_mem mbox_mem_alloced;

	struct be_mcc_obj mcc_obj;
	spinlock_t mcc_lock;	/* For serializing mcc cmds to BE card */
	spinlock_t mcc_cq_lock;

	u32 num_msix_vec;
	u32 num_evt_qs;
	struct be_eq_obj eq_obj[MAX_MSIX_VECTORS];
	struct msix_entry msix_entries[MAX_MSIX_VECTORS];
	bool isr_registered;

	/* TX Rings */
	u32 num_tx_qs;
	struct be_tx_obj tx_obj[MAX_TX_QS];

	/* Rx rings */
	u32 num_rx_qs;
	struct be_rx_obj rx_obj[MAX_RX_QS];
	u32 big_page_size;	/* Compounded page size shared by rx wrbs */

	u8 eq_next_idx;
	struct be_drv_stats drv_stats;

	u16 vlans_added;
	u16 max_vlans;	/* Number of vlans supported */
	u8 vlan_tag[VLAN_N_VID];
	u8 vlan_prio_bmap;	/* Available Priority BitMap */
	u16 recommended_prio;	/* Recommended Priority */
	struct be_dma_mem rx_filter; /* Cmd DMA mem for rx-filter */

	struct be_dma_mem stats_cmd;
	/* Work queue used to perform periodic tasks like getting statistics */
	struct delayed_work work;
	u16 work_counter;

	u32 flags;
	/* Ethtool knobs and info */
	char fw_ver[FW_VER_LEN];
	int if_handle;		/* Used to configure filtering */
	u32 *pmac_id;		/* MAC addr handle used by BE card */
	u32 beacon_state;	/* for set_phys_id */

	bool eeh_err;
	bool ue_detected;
	bool fw_timeout;
	u32 port_num;
	bool promiscuous;
	u32 function_mode;
	u32 function_caps;
	u32 rx_fc;		/* Rx flow control */
	u32 tx_fc;		/* Tx flow control */
	bool stats_cmd_sent;
	u8 generation;		/* BladeEngine ASIC generation */
	u32 flash_status;
	struct completion flash_compl;

	u32 num_vfs;		/* Number of VFs provisioned by PF driver */
	u32 dev_num_vfs;	/* Number of VFs supported by HW */
	u8 virtfn;
	struct be_vf_cfg *vf_cfg;
	bool be3_native;
	u32 sli_family;
	u8 hba_port_num;
	u16 pvid;
	struct phy_info phy;
	u8 wol_cap;
	bool wol;
	u32 max_pmac_cnt;	/* Max secondary UC MACs programmable */
	u32 uc_macs;		/* Count of secondary UC MAC programmed */
};

#define be_physfn(adapter)		(!adapter->virtfn)
#define	sriov_enabled(adapter)		(adapter->num_vfs > 0)
#define	sriov_want(adapter)		(adapter->dev_num_vfs && num_vfs && \
					 be_physfn(adapter))
#define for_all_vfs(adapter, vf_cfg, i)					\
	for (i = 0, vf_cfg = &adapter->vf_cfg[i]; i < adapter->num_vfs;	\
		i++, vf_cfg++)

/* BladeEngine Generation numbers */
#define BE_GEN2 2
#define BE_GEN3 3

#define ON				1
#define OFF				0
#define lancer_chip(adapter)	((adapter->pdev->device == OC_DEVICE_ID3) || \
				 (adapter->pdev->device == OC_DEVICE_ID4))

extern const struct ethtool_ops be_ethtool_ops;

#define msix_enabled(adapter)		(adapter->num_msix_vec > 0)
#define num_irqs(adapter)		(msix_enabled(adapter) ?	\
						adapter->num_msix_vec : 1)
#define tx_stats(txo)			(&(txo)->stats)
#define rx_stats(rxo)			(&(rxo)->stats)

/* The default RXQ is the last RXQ */
#define default_rxo(adpt)		(&adpt->rx_obj[adpt->num_rx_qs - 1])

#define for_all_rx_queues(adapter, rxo, i)				\
	for (i = 0, rxo = &adapter->rx_obj[i]; i < adapter->num_rx_qs;	\
		i++, rxo++)

/* Skip the default non-rss queue (last one)*/
#define for_all_rss_queues(adapter, rxo, i)				\
	for (i = 0, rxo = &adapter->rx_obj[i]; i < (adapter->num_rx_qs - 1);\
		i++, rxo++)

#define for_all_tx_queues(adapter, txo, i)				\
	for (i = 0, txo = &adapter->tx_obj[i]; i < adapter->num_tx_qs;	\
		i++, txo++)

#define for_all_evt_queues(adapter, eqo, i)				\
	for (i = 0, eqo = &adapter->eq_obj[i]; i < adapter->num_evt_qs; \
		i++, eqo++)

#define is_mcc_eqo(eqo)			(eqo->idx == 0)
#define mcc_eqo(adapter)		(&adapter->eq_obj[0])

#define PAGE_SHIFT_4K		12
#define PAGE_SIZE_4K		(1 << PAGE_SHIFT_4K)

/* Returns number of pages spanned by the data starting at the given addr */
#define PAGES_4K_SPANNED(_address, size) 				\
		((u32)((((size_t)(_address) & (PAGE_SIZE_4K - 1)) + 	\
			(size) + (PAGE_SIZE_4K - 1)) >> PAGE_SHIFT_4K))

/* Returns bit offset within a DWORD of a bitfield */
#define AMAP_BIT_OFFSET(_struct, field)  				\
		(((size_t)&(((_struct *)0)->field))%32)

/* Returns the bit mask of the field that is NOT shifted into location. */
static inline u32 amap_mask(u32 bitsize)
{
	return (bitsize == 32 ? 0xFFFFFFFF : (1 << bitsize) - 1);
}

static inline void
amap_set(void *ptr, u32 dw_offset, u32 mask, u32 offset, u32 value)
{
	u32 *dw = (u32 *) ptr + dw_offset;
	*dw &= ~(mask << offset);
	*dw |= (mask & value) << offset;
}

#define AMAP_SET_BITS(_struct, field, ptr, val)				\
		amap_set(ptr,						\
			offsetof(_struct, field)/32,			\
			amap_mask(sizeof(((_struct *)0)->field)),	\
			AMAP_BIT_OFFSET(_struct, field),		\
			val)

static inline u32 amap_get(void *ptr, u32 dw_offset, u32 mask, u32 offset)
{
	u32 *dw = (u32 *) ptr;
	return mask & (*(dw + dw_offset) >> offset);
}

#define AMAP_GET_BITS(_struct, field, ptr)				\
		amap_get(ptr,						\
			offsetof(_struct, field)/32,			\
			amap_mask(sizeof(((_struct *)0)->field)),	\
			AMAP_BIT_OFFSET(_struct, field))

#define be_dws_cpu_to_le(wrb, len)	swap_dws(wrb, len)
#define be_dws_le_to_cpu(wrb, len)	swap_dws(wrb, len)
static inline void swap_dws(void *wrb, int len)
{
#ifdef __BIG_ENDIAN
	u32 *dw = wrb;
	BUG_ON(len % 4);
	do {
		*dw = cpu_to_le32(*dw);
		dw++;
		len -= 4;
	} while (len);
#endif				/* __BIG_ENDIAN */
}

static inline u8 is_tcp_pkt(struct sk_buff *skb)
{
	u8 val = 0;

	if (ip_hdr(skb)->version == 4)
		val = (ip_hdr(skb)->protocol == IPPROTO_TCP);
	else if (ip_hdr(skb)->version == 6)
		val = (ipv6_hdr(skb)->nexthdr == NEXTHDR_TCP);

	return val;
}

static inline u8 is_udp_pkt(struct sk_buff *skb)
{
	u8 val = 0;

	if (ip_hdr(skb)->version == 4)
		val = (ip_hdr(skb)->protocol == IPPROTO_UDP);
	else if (ip_hdr(skb)->version == 6)
		val = (ipv6_hdr(skb)->nexthdr == NEXTHDR_UDP);

	return val;
}

static inline void be_vf_eth_addr_generate(struct be_adapter *adapter, u8 *mac)
{
	u32 addr;

	addr = jhash(adapter->netdev->dev_addr, ETH_ALEN, 0);

	mac[5] = (u8)(addr & 0xFF);
	mac[4] = (u8)((addr >> 8) & 0xFF);
	mac[3] = (u8)((addr >> 16) & 0xFF);
	/* Use the OUI from the current MAC address */
	memcpy(mac, adapter->netdev->dev_addr, 3);
}

static inline bool be_multi_rxq(const struct be_adapter *adapter)
{
	return adapter->num_rx_qs > 1;
}

static inline bool be_error(struct be_adapter *adapter)
{
	return adapter->eeh_err || adapter->ue_detected || adapter->fw_timeout;
}

static inline bool be_is_wol_excluded(struct be_adapter *adapter)
{
	struct pci_dev *pdev = adapter->pdev;

	if (!be_physfn(adapter))
		return true;

	switch (pdev->subsystem_device) {
	case OC_SUBSYS_DEVICE_ID1:
	case OC_SUBSYS_DEVICE_ID2:
	case OC_SUBSYS_DEVICE_ID3:
	case OC_SUBSYS_DEVICE_ID4:
		return true;
	default:
		return false;
	}
}

extern void be_cq_notify(struct be_adapter *adapter, u16 qid, bool arm,
		u16 num_popped);
extern void be_link_status_update(struct be_adapter *adapter, u8 link_status);
extern void be_parse_stats(struct be_adapter *adapter);
extern int be_load_fw(struct be_adapter *adapter, u8 *func);
extern bool be_is_wol_supported(struct be_adapter *adapter);
extern bool be_pause_supported(struct be_adapter *adapter);
#endif				/* BE_H */
Commit	Line	Data
6b7c5b94	1	/*
d2145cde	2	* Copyright (C) 2005 - 2011 Emulex
6b7c5b94 SP	3	* All rights reserved.
	4	*
	5	* This program is free software; you can redistribute it and/or
	6	* modify it under the terms of the GNU General Public License version 2
	7	* as published by the Free Software Foundation. The full GNU General
	8	* Public License is included in this distribution in the file called COPYING.
	9	*
	10	* Contact Information:
d2145cde	11	* linux-drivers@emulex.com
6b7c5b94	12	*
d2145cde AK	13	* Emulex
	14	* 3333 Susan Street
	15	* Costa Mesa, CA 92626
6b7c5b94 SP	16	*/
	17
	18	#ifndef BE_H
	19	#define BE_H
	20
	21	#include <linux/pci.h>
	22	#include <linux/etherdevice.h>
6b7c5b94 SP	23	#include <linux/delay.h>
	24	#include <net/tcp.h>
	25	#include <net/ip.h>
	26	#include <net/ipv6.h>
	27	#include <linux/if_vlan.h>
	28	#include <linux/workqueue.h>
	29	#include <linux/interrupt.h>
84517482	30	#include <linux/firmware.h>
5a0e3ad6	31	#include <linux/slab.h>
ab1594e9	32	#include <linux/u64_stats_sync.h>
6b7c5b94 SP	33
	34	#include "be_hw.h"
	35
06b0ab37	36	#define DRV_VER "4.2.220u"
6b7c5b94 SP	37	#define DRV_NAME "be2net"
6b7c5b94 SP	38	#define BE_NAME "ServerEngines BladeEngine2 10Gbps NIC"
12d7ea2c	39	#define BE3_NAME "ServerEngines BladeEngine3 10Gbps NIC"
c4ca2374	40	#define OC_NAME "Emulex OneConnect 10Gbps NIC"
fe6d2a38 SP	41	#define OC_NAME_BE OC_NAME "(be3)"
fe6d2a38 SP	42	#define OC_NAME_LANCER OC_NAME "(Lancer)"
ecedb6ae	43	#define OC_NAME_SH OC_NAME "(Skyhawk)"
35ecf03c	44	#define DRV_DESC "ServerEngines BladeEngine 10Gbps NIC Driver"
6b7c5b94	45
c4ca2374	46	#define BE_VENDOR_ID 0x19a2
fe6d2a38	47	#define EMULEX_VENDOR_ID 0x10df
c4ca2374	48	#define BE_DEVICE_ID1 0x211
12d7ea2c	49	#define BE_DEVICE_ID2 0x221
fe6d2a38 SP	50	#define OC_DEVICE_ID1 0x700 /* Device Id for BE2 cards */
	51	#define OC_DEVICE_ID2 0x710 /* Device Id for BE3 cards */
	52	#define OC_DEVICE_ID3 0xe220 /* Device id for Lancer cards */
12f4d0a8	53	#define OC_DEVICE_ID4 0xe228 /* Device id for VF in Lancer */
ecedb6ae	54	#define OC_DEVICE_ID5 0x720 /* Device Id for Skyhawk cards */
4762f6ce AK	55	#define OC_SUBSYS_DEVICE_ID1 0xE602
	56	#define OC_SUBSYS_DEVICE_ID2 0xE642
	57	#define OC_SUBSYS_DEVICE_ID3 0xE612
	58	#define OC_SUBSYS_DEVICE_ID4 0xE652
c4ca2374 AK	59
	60	static inline char nic_name(struct pci_dev pdev)
	61	{
12d7ea2c AK	62	switch (pdev->device) {
12d7ea2c AK	63	case OC_DEVICE_ID1:
c4ca2374	64	return OC_NAME;
e254f6ec	65	case OC_DEVICE_ID2:
fe6d2a38 SP	66	return OC_NAME_BE;
fe6d2a38 SP	67	case OC_DEVICE_ID3:
12f4d0a8	68	case OC_DEVICE_ID4:
fe6d2a38	69	return OC_NAME_LANCER;
12d7ea2c AK	70	case BE_DEVICE_ID2:
12d7ea2c AK	71	return BE3_NAME;
ecedb6ae AK	72	case OC_DEVICE_ID5:
ecedb6ae AK	73	return OC_NAME_SH;
12d7ea2c	74	default:
c4ca2374	75	return BE_NAME;
12d7ea2c	76	}
c4ca2374 AK	77	}
c4ca2374 AK	78
6b7c5b94	79	/* Number of bytes of an RX frame that are copied to skb->data */
2e588f84	80	#define BE_HDR_LEN ((u16) 64)
bb349bb4 ED	81	/* allocate extra space to allow tunneling decapsulation without head reallocation */
	82	#define BE_RX_SKB_ALLOC_SIZE (BE_HDR_LEN + 64)
	83
6b7c5b94 SP	84	#define BE_MAX_JUMBO_FRAME_SIZE 9018
	85	#define BE_MIN_MTU 256
	86
	87	#define BE_NUM_VLANS_SUPPORTED 64
10ef9ab4	88	#define BE_MAX_EQD 96u
6b7c5b94 SP	89	#define BE_MAX_TX_FRAG_COUNT 30
	90
	91	#define EVNT_Q_LEN 1024
	92	#define TX_Q_LEN 2048
	93	#define TX_CQ_LEN 1024
	94	#define RX_Q_LEN 1024 /* Does not support any other value */
	95	#define RX_CQ_LEN 1024
5fb379ee	96	#define MCC_Q_LEN 128 /* total size not to exceed 8 pages */
6b7c5b94 SP	97	#define MCC_CQ_LEN 256
6b7c5b94 SP	98
10ef9ab4 SP	99	#define BE3_MAX_RSS_QS 8
	100	#define BE2_MAX_RSS_QS 4
	101	#define MAX_RSS_QS BE3_MAX_RSS_QS
ac6a0c4a	102	#define MAX_RX_QS (MAX_RSS_QS + 1) /* RSS qs + 1 def Rx */
10ef9ab4	103
3c8def97	104	#define MAX_TX_QS 8
10ef9ab4 SP	105	#define MAX_MSIX_VECTORS MAX_RSS_QS
10ef9ab4 SP	106	#define BE_TX_BUDGET 256
6b7c5b94	107	#define BE_NAPI_WEIGHT 64
10ef9ab4	108	#define MAX_RX_POST BE_NAPI_WEIGHT /* Frags posted at a time */
6b7c5b94 SP	109	#define RX_FRAGS_REFILL_WM (RX_Q_LEN - MAX_RX_POST)
6b7c5b94 SP	110
8788fdc2 SP	111	#define FW_VER_LEN 32
8788fdc2 SP	112
6b7c5b94 SP	113	struct be_dma_mem {
	114	void *va;
	115	dma_addr_t dma;
	116	u32 size;
	117	};
	118
	119	struct be_queue_info {
	120	struct be_dma_mem dma_mem;
	121	u16 len;
	122	u16 entry_size; /* Size of an element in the queue */
	123	u16 id;
	124	u16 tail, head;
	125	bool created;
	126	atomic_t used; /* Number of valid elements in the queue */
	127	};
	128
5fb379ee SP	129	static inline u32 MODULO(u16 val, u16 limit)
	130	{
	131	BUG_ON(limit & (limit - 1));
	132	return val & (limit - 1);
	133	}
	134
	135	static inline void index_adv(u16 *index, u16 val, u16 limit)
	136	{
	137	index = MODULO((index + val), limit);
	138	}
	139
	140	static inline void index_inc(u16 *index, u16 limit)
	141	{
	142	index = MODULO((index + 1), limit);
	143	}
	144
	145	static inline void queue_head_node(struct be_queue_info q)
	146	{
	147	return q->dma_mem.va + q->head * q->entry_size;
	148	}
	149
	150	static inline void queue_tail_node(struct be_queue_info q)
	151	{
	152	return q->dma_mem.va + q->tail * q->entry_size;
	153	}
	154
3de09455 SK	155	static inline void queue_index_node(struct be_queue_info q, u16 index)
	156	{
	157	return q->dma_mem.va + index * q->entry_size;
	158	}
	159
5fb379ee SP	160	static inline void queue_head_inc(struct be_queue_info *q)
	161	{
	162	index_inc(&q->head, q->len);
	163	}
	164
652bf646 PR	165	static inline void index_dec(u16 *index, u16 limit)
	166	{
	167	index = MODULO((index - 1), limit);
	168	}
	169
5fb379ee SP	170	static inline void queue_tail_inc(struct be_queue_info *q)
	171	{
	172	index_inc(&q->tail, q->len);
	173	}
	174
5fb379ee SP	175	struct be_eq_obj {
	176	struct be_queue_info q;
	177	char desc[32];
	178
	179	/* Adaptive interrupt coalescing (AIC) info */
	180	bool enable_aic;
10ef9ab4 SP	181	u32 min_eqd; /* in usecs */
	182	u32 max_eqd; /* in usecs */
	183	u32 eqd; /* configured val when aic is off */
	184	u32 cur_eqd; /* in usecs */
5fb379ee	185
10ef9ab4 SP	186	u8 idx; /* array index */
10ef9ab4 SP	187	u16 tx_budget;
5fb379ee	188	struct napi_struct napi;
10ef9ab4 SP	189	struct be_adapter *adapter;
10ef9ab4 SP	190	} ____cacheline_aligned_in_smp;
5fb379ee SP	191
	192	struct be_mcc_obj {
	193	struct be_queue_info q;
	194	struct be_queue_info cq;
7a1e9b20	195	bool rearm_cq;
5fb379ee SP	196	};
5fb379ee SP	197
3abcdeda	198	struct be_tx_stats {
ac124ff9 SP	199	u64 tx_bytes;
	200	u64 tx_pkts;
	201	u64 tx_reqs;
	202	u64 tx_wrbs;
	203	u64 tx_compl;
	204	ulong tx_jiffies;
	205	u32 tx_stops;
ab1594e9 SP	206	struct u64_stats_sync sync;
ab1594e9 SP	207	struct u64_stats_sync sync_compl;
6b7c5b94 SP	208	};
6b7c5b94 SP	209
6b7c5b94 SP	210	struct be_tx_obj {
	211	struct be_queue_info q;
	212	struct be_queue_info cq;
	213	/* Remember the skbs that were transmitted */
	214	struct sk_buff *sent_skb_list[TX_Q_LEN];
3c8def97	215	struct be_tx_stats stats;
10ef9ab4	216	} ____cacheline_aligned_in_smp;
6b7c5b94 SP	217
	218	/* Struct to remember the pages posted for rx frags */
	219	struct be_rx_page_info {
	220	struct page *page;
fac6da5b	221	DEFINE_DMA_UNMAP_ADDR(bus);
6b7c5b94 SP	222	u16 page_offset;
	223	bool last_page_user;
	224	};
	225
3abcdeda	226	struct be_rx_stats {
3abcdeda	227	u64 rx_bytes;
3abcdeda	228	u64 rx_pkts;
ac124ff9 SP	229	u64 rx_pkts_prev;
	230	ulong rx_jiffies;
	231	u32 rx_drops_no_skbs; /* skb allocation errors */
	232	u32 rx_drops_no_frags; /* HW has no fetched frags */
	233	u32 rx_post_fail; /* page post alloc failures */
ac124ff9	234	u32 rx_compl;
3abcdeda	235	u32 rx_mcast_pkts;
ac124ff9 SP	236	u32 rx_compl_err; /* completions with err set */
ac124ff9 SP	237	u32 rx_pps; /* pkts per second */
ab1594e9	238	struct u64_stats_sync sync;
3abcdeda SP	239	};
3abcdeda SP	240
2e588f84 SP	241	struct be_rx_compl_info {
2e588f84 SP	242	u32 rss_hash;
6709d952	243	u16 vlan_tag;
2e588f84 SP	244	u16 pkt_size;
2e588f84 SP	245	u16 rxq_idx;
12004ae9	246	u16 port;
2e588f84 SP	247	u8 vlanf;
	248	u8 num_rcvd;
	249	u8 err;
	250	u8 ipf;
	251	u8 tcpf;
	252	u8 udpf;
	253	u8 ip_csum;
	254	u8 l4_csum;
	255	u8 ipv6;
	256	u8 vtm;
	257	u8 pkt_type;
	258	};
	259
6b7c5b94	260	struct be_rx_obj {
3abcdeda	261	struct be_adapter *adapter;
6b7c5b94 SP	262	struct be_queue_info q;
6b7c5b94 SP	263	struct be_queue_info cq;
2e588f84	264	struct be_rx_compl_info rxcp;
6b7c5b94	265	struct be_rx_page_info page_info_tbl[RX_Q_LEN];
3abcdeda SP	266	struct be_rx_stats stats;
	267	u8 rss_id;
	268	bool rx_post_starved; /* Zero rx frags have been posted to BE */
10ef9ab4	269	} ____cacheline_aligned_in_smp;
6b7c5b94	270
609ff3bb	271	struct be_drv_stats {
9ae081c6	272	u32 be_on_die_temperature;
ac124ff9 SP	273	u32 eth_red_drops;
	274	u32 rx_drops_no_pbuf;
	275	u32 rx_drops_no_txpb;
	276	u32 rx_drops_no_erx_descr;
	277	u32 rx_drops_no_tpre_descr;
	278	u32 rx_drops_too_many_frags;
ac124ff9 SP	279	u32 forwarded_packets;
	280	u32 rx_drops_mtu;
	281	u32 rx_crc_errors;
	282	u32 rx_alignment_symbol_errors;
	283	u32 rx_pause_frames;
	284	u32 rx_priority_pause_frames;
	285	u32 rx_control_frames;
	286	u32 rx_in_range_errors;
	287	u32 rx_out_range_errors;
	288	u32 rx_frame_too_long;
d45b9d39	289	u32 rx_address_mismatch_drops;
ac124ff9 SP	290	u32 rx_dropped_too_small;
	291	u32 rx_dropped_too_short;
	292	u32 rx_dropped_header_too_small;
	293	u32 rx_dropped_tcp_length;
	294	u32 rx_dropped_runt;
	295	u32 rx_ip_checksum_errs;
	296	u32 rx_tcp_checksum_errs;
	297	u32 rx_udp_checksum_errs;
	298	u32 tx_pauseframes;
	299	u32 tx_priority_pauseframes;
	300	u32 tx_controlframes;
	301	u32 rxpp_fifo_overflow_drop;
	302	u32 rx_input_fifo_overflow_drop;
	303	u32 pmem_fifo_overflow_drop;
	304	u32 jabber_events;
609ff3bb AK	305	};
609ff3bb AK	306
64600ea5	307	struct be_vf_cfg {
11ac75ed SP	308	unsigned char mac_addr[ETH_ALEN];
	309	int if_handle;
	310	int pmac_id;
f1f3ee1b	311	u16 def_vid;
11ac75ed SP	312	u16 vlan_tag;
11ac75ed SP	313	u32 tx_rate;
64600ea5 AK	314	};
64600ea5 AK	315
39f1d94d SP	316	enum vf_state {
	317	ENABLED = 0,
	318	ASSIGNED = 1
	319	};
	320
b236916a	321	#define BE_FLAGS_LINK_STATUS_INIT 1
191eb756	322	#define BE_FLAGS_WORKER_SCHEDULED (1 << 3)
fbc13f01 AK	323	#define BE_UC_PMAC_COUNT 30
fbc13f01 AK	324	#define BE_VF_UC_PMAC_COUNT 2
b236916a	325
42f11cf2 AK	326	struct phy_info {
	327	u8 transceiver;
	328	u8 autoneg;
	329	u8 fc_autoneg;
	330	u8 port_type;
	331	u16 phy_type;
	332	u16 interface_type;
	333	u32 misc_params;
	334	u16 auto_speeds_supported;
	335	u16 fixed_speeds_supported;
	336	int link_speed;
	337	int forced_port_speed;
	338	u32 dac_cable_len;
	339	u32 advertising;
	340	u32 supported;
	341	};
	342
6b7c5b94 SP	343	struct be_adapter {
	344	struct pci_dev *pdev;
	345	struct net_device *netdev;
	346
8788fdc2 SP	347	u8 __iomem *csr;
8788fdc2 SP	348	u8 __iomem db; / Door Bell */
8788fdc2	349
2984961c	350	struct mutex mbox_lock; /* For serializing mbox cmds to BE card */
8788fdc2 SP	351	struct be_dma_mem mbox_mem;
	352	/* Mbox mem is adjusted to align to 16 bytes. The allocated addr
	353	* is stored for freeing purpose */
	354	struct be_dma_mem mbox_mem_alloced;
	355
	356	struct be_mcc_obj mcc_obj;
	357	spinlock_t mcc_lock; /* For serializing mcc cmds to BE card */
	358	spinlock_t mcc_cq_lock;
6b7c5b94	359
ac6a0c4a	360	u32 num_msix_vec;
10ef9ab4 SP	361	u32 num_evt_qs;
	362	struct be_eq_obj eq_obj[MAX_MSIX_VECTORS];
	363	struct msix_entry msix_entries[MAX_MSIX_VECTORS];
6b7c5b94 SP	364	bool isr_registered;
	365
	366	/* TX Rings */
10ef9ab4	367	u32 num_tx_qs;
3c8def97	368	struct be_tx_obj tx_obj[MAX_TX_QS];
6b7c5b94 SP	369
6b7c5b94 SP	370	/* Rx rings */
3abcdeda	371	u32 num_rx_qs;
10ef9ab4	372	struct be_rx_obj rx_obj[MAX_RX_QS];
6b7c5b94 SP	373	u32 big_page_size; /* Compounded page size shared by rx wrbs */
6b7c5b94 SP	374
ecd62107	375	u8 eq_next_idx;
609ff3bb	376	struct be_drv_stats drv_stats;
fe6d2a38	377
82903e4b AK	378	u16 vlans_added;
82903e4b AK	379	u16 max_vlans; /* Number of vlans supported */
b738127d	380	u8 vlan_tag[VLAN_N_VID];
cc4ce020 SK	381	u8 vlan_prio_bmap; /* Available Priority BitMap */
cc4ce020 SK	382	u16 recommended_prio; /* Recommended Priority */
5b8821b7	383	struct be_dma_mem rx_filter; /* Cmd DMA mem for rx-filter */
6b7c5b94	384
3abcdeda	385	struct be_dma_mem stats_cmd;
6b7c5b94 SP	386	/* Work queue used to perform periodic tasks like getting statistics */
6b7c5b94 SP	387	struct delayed_work work;
609ff3bb	388	u16 work_counter;
6b7c5b94	389
b236916a	390	u32 flags;
6b7c5b94	391	/* Ethtool knobs and info */
6b7c5b94	392	char fw_ver[FW_VER_LEN];
30128031	393	int if_handle; /* Used to configure filtering */
fbc13f01	394	u32 pmac_id; / MAC addr handle used by BE card */
1a642469	395	u32 beacon_state; /* for set_phys_id */
6b7c5b94	396
cf588477	397	bool eeh_err;
6589ade0 SP	398	bool ue_detected;
6589ade0 SP	399	bool fw_timeout;
6b7c5b94	400	u32 port_num;
24307eef	401	bool promiscuous;
3486be29	402	u32 function_mode;
3abcdeda	403	u32 function_caps;
9e90c961 AK	404	u32 rx_fc; /* Rx flow control */
9e90c961 AK	405	u32 tx_fc; /* Tx flow control */
b2aebe6d	406	bool stats_cmd_sent;
7b139c83	407	u8 generation; /* BladeEngine ASIC generation */
dd131e76 SB	408	u32 flash_status;
dd131e76 SB	409	struct completion flash_compl;
ba343c77	410
39f1d94d SP	411	u32 num_vfs; /* Number of VFs provisioned by PF driver */
	412	u32 dev_num_vfs; /* Number of VFs supported by HW */
	413	u8 virtfn;
11ac75ed SP	414	struct be_vf_cfg *vf_cfg;
11ac75ed SP	415	bool be3_native;
fe6d2a38	416	u32 sli_family;
9e1453c5	417	u8 hba_port_num;
3968fa1e	418	u16 pvid;
42f11cf2	419	struct phy_info phy;
4762f6ce AK	420	u8 wol_cap;
4762f6ce AK	421	bool wol;
fbc13f01 AK	422	u32 max_pmac_cnt; /* Max secondary UC MACs programmable */
fbc13f01 AK	423	u32 uc_macs; /* Count of secondary UC MAC programmed */
6b7c5b94 SP	424	};
6b7c5b94 SP	425
39f1d94d	426	#define be_physfn(adapter) (!adapter->virtfn)
11ac75ed	427	#define sriov_enabled(adapter) (adapter->num_vfs > 0)
39f1d94d SP	428	#define sriov_want(adapter) (adapter->dev_num_vfs && num_vfs && \
39f1d94d SP	429	be_physfn(adapter))
11ac75ed SP	430	#define for_all_vfs(adapter, vf_cfg, i) \
	431	for (i = 0, vf_cfg = &adapter->vf_cfg[i]; i < adapter->num_vfs; \
	432	i++, vf_cfg++)
ba343c77	433
7b139c83 AK	434	/* BladeEngine Generation numbers */
	435	#define BE_GEN2 2
	436	#define BE_GEN3 3
	437
5b8821b7 SP	438	#define ON 1
5b8821b7 SP	439	#define OFF 0
12f4d0a8 ME	440	#define lancer_chip(adapter) ((adapter->pdev->device == OC_DEVICE_ID3) \|\| \
12f4d0a8 ME	441	(adapter->pdev->device == OC_DEVICE_ID4))
fe6d2a38	442
0fc0b732	443	extern const struct ethtool_ops be_ethtool_ops;
6b7c5b94	444
ac6a0c4a	445	#define msix_enabled(adapter) (adapter->num_msix_vec > 0)
10ef9ab4 SP	446	#define num_irqs(adapter) (msix_enabled(adapter) ? \
	447	adapter->num_msix_vec : 1)
	448	#define tx_stats(txo) (&(txo)->stats)
	449	#define rx_stats(rxo) (&(rxo)->stats)
6b7c5b94	450
10ef9ab4 SP	451	/* The default RXQ is the last RXQ */
10ef9ab4 SP	452	#define default_rxo(adpt) (&adpt->rx_obj[adpt->num_rx_qs - 1])
6b7c5b94	453
3abcdeda SP	454	#define for_all_rx_queues(adapter, rxo, i) \
	455	for (i = 0, rxo = &adapter->rx_obj[i]; i < adapter->num_rx_qs; \
	456	i++, rxo++)
	457
10ef9ab4	458	/* Skip the default non-rss queue (last one)*/
3abcdeda	459	#define for_all_rss_queues(adapter, rxo, i) \
10ef9ab4	460	for (i = 0, rxo = &adapter->rx_obj[i]; i < (adapter->num_rx_qs - 1);\
3abcdeda SP	461	i++, rxo++)
3abcdeda SP	462
3c8def97 SP	463	#define for_all_tx_queues(adapter, txo, i) \
	464	for (i = 0, txo = &adapter->tx_obj[i]; i < adapter->num_tx_qs; \
	465	i++, txo++)
	466
10ef9ab4 SP	467	#define for_all_evt_queues(adapter, eqo, i) \
	468	for (i = 0, eqo = &adapter->eq_obj[i]; i < adapter->num_evt_qs; \
	469	i++, eqo++)
	470
	471	#define is_mcc_eqo(eqo) (eqo->idx == 0)
	472	#define mcc_eqo(adapter) (&adapter->eq_obj[0])
	473
6b7c5b94 SP	474	#define PAGE_SHIFT_4K 12
	475	#define PAGE_SIZE_4K (1 << PAGE_SHIFT_4K)
	476
	477	/* Returns number of pages spanned by the data starting at the given addr */
	478	#define PAGES_4K_SPANNED(_address, size) \
	479	((u32)((((size_t)(_address) & (PAGE_SIZE_4K - 1)) + \
	480	(size) + (PAGE_SIZE_4K - 1)) >> PAGE_SHIFT_4K))
	481
6b7c5b94 SP	482	/* Returns bit offset within a DWORD of a bitfield */
	483	#define AMAP_BIT_OFFSET(_struct, field) \
	484	(((size_t)&(((_struct *)0)->field))%32)
	485
	486	/* Returns the bit mask of the field that is NOT shifted into location. */
	487	static inline u32 amap_mask(u32 bitsize)
	488	{
	489	return (bitsize == 32 ? 0xFFFFFFFF : (1 << bitsize) - 1);
	490	}
	491
	492	static inline void
	493	amap_set(void *ptr, u32 dw_offset, u32 mask, u32 offset, u32 value)
	494	{
	495	u32 dw = (u32 ) ptr + dw_offset;
	496	*dw &= ~(mask << offset);
	497	*dw \|= (mask & value) << offset;
	498	}
	499
	500	#define AMAP_SET_BITS(_struct, field, ptr, val) \
	501	amap_set(ptr, \
	502	offsetof(_struct, field)/32, \
	503	amap_mask(sizeof(((_struct *)0)->field)), \
	504	AMAP_BIT_OFFSET(_struct, field), \
	505	val)
	506
	507	static inline u32 amap_get(void *ptr, u32 dw_offset, u32 mask, u32 offset)
	508	{
	509	u32 dw = (u32 ) ptr;
	510	return mask & (*(dw + dw_offset) >> offset);
	511	}
	512
	513	#define AMAP_GET_BITS(_struct, field, ptr) \
	514	amap_get(ptr, \
	515	offsetof(_struct, field)/32, \
	516	amap_mask(sizeof(((_struct *)0)->field)), \
	517	AMAP_BIT_OFFSET(_struct, field))
	518
	519	#define be_dws_cpu_to_le(wrb, len) swap_dws(wrb, len)
	520	#define be_dws_le_to_cpu(wrb, len) swap_dws(wrb, len)
	521	static inline void swap_dws(void *wrb, int len)
	522	{
	523	#ifdef __BIG_ENDIAN
	524	u32 *dw = wrb;
	525	BUG_ON(len % 4);
	526	do {
	527	dw = cpu_to_le32(dw);
	528	dw++;
	529	len -= 4;
	530	} while (len);
	531	#endif /* __BIG_ENDIAN */
	532	}
	533
	534	static inline u8 is_tcp_pkt(struct sk_buff *skb)
	535	{
	536	u8 val = 0;
	537
	538	if (ip_hdr(skb)->version == 4)
	539	val = (ip_hdr(skb)->protocol == IPPROTO_TCP);
	540	else if (ip_hdr(skb)->version == 6)
	541	val = (ipv6_hdr(skb)->nexthdr == NEXTHDR_TCP);
	542
	543	return val;
	544	}
	545
546	static inline u8 is_udp_pkt(struct sk_buff *skb)
547	{
548	u8 val = 0;
549
550	if (ip_hdr(skb)->version == 4)
551	val = (ip_hdr(skb)->protocol == IPPROTO_UDP);
552	else if (ip_hdr(skb)->version == 6)
553	val = (ipv6_hdr(skb)->nexthdr == NEXTHDR_UDP);
554
555	return val;
556	}
557
6d87f5c3 AK	558	static inline void be_vf_eth_addr_generate(struct be_adapter adapter, u8 mac)
	559	{
	560	u32 addr;
	561
	562	addr = jhash(adapter->netdev->dev_addr, ETH_ALEN, 0);
	563
	564	mac[5] = (u8)(addr & 0xFF);
	565	mac[4] = (u8)((addr >> 8) & 0xFF);
	566	mac[3] = (u8)((addr >> 16) & 0xFF);
7a2414a5 AK	567	/* Use the OUI from the current MAC address */
7a2414a5 AK	568	memcpy(mac, adapter->netdev->dev_addr, 3);
6d87f5c3 AK	569	}
6d87f5c3 AK	570
4b972914 AK	571	static inline bool be_multi_rxq(const struct be_adapter *adapter)
	572	{
	573	return adapter->num_rx_qs > 1;
	574	}
	575
6589ade0 SP	576	static inline bool be_error(struct be_adapter *adapter)
	577	{
	578	return adapter->eeh_err \|\| adapter->ue_detected \|\| adapter->fw_timeout;
	579	}
	580
4762f6ce AK	581	static inline bool be_is_wol_excluded(struct be_adapter *adapter)
	582	{
	583	struct pci_dev *pdev = adapter->pdev;
	584
	585	if (!be_physfn(adapter))
	586	return true;
	587
	588	switch (pdev->subsystem_device) {
	589	case OC_SUBSYS_DEVICE_ID1:
	590	case OC_SUBSYS_DEVICE_ID2:
	591	case OC_SUBSYS_DEVICE_ID3:
	592	case OC_SUBSYS_DEVICE_ID4:
	593	return true;
	594	default:
	595	return false;
	596	}
	597	}
	598
8788fdc2	599	extern void be_cq_notify(struct be_adapter *adapter, u16 qid, bool arm,
5fb379ee	600	u16 num_popped);
b236916a	601	extern void be_link_status_update(struct be_adapter *adapter, u8 link_status);
89a88ab8	602	extern void be_parse_stats(struct be_adapter *adapter);
84517482	603	extern int be_load_fw(struct be_adapter adapter, u8 func);
4762f6ce	604	extern bool be_is_wol_supported(struct be_adapter *adapter);
42f11cf2	605	extern bool be_pause_supported(struct be_adapter *adapter);
6b7c5b94	606	#endif /* BE_H */