be2net: refactor be_set_rx_mode() and be_vid_config() for readability
[deliverable/linux.git] / drivers / net / ethernet / emulex / benet / be.h
CommitLineData
6b7c5b94 1/*
40263820 2 * Copyright (C) 2005 - 2014 Emulex
6b7c5b94
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3 * All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License version 2
7 * as published by the Free Software Foundation. The full GNU General
8 * Public License is included in this distribution in the file called COPYING.
9 *
10 * Contact Information:
d2145cde 11 * linux-drivers@emulex.com
6b7c5b94 12 *
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13 * Emulex
14 * 3333 Susan Street
15 * Costa Mesa, CA 92626
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16 */
17
18#ifndef BE_H
19#define BE_H
20
21#include <linux/pci.h>
22#include <linux/etherdevice.h>
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23#include <linux/delay.h>
24#include <net/tcp.h>
25#include <net/ip.h>
26#include <net/ipv6.h>
27#include <linux/if_vlan.h>
28#include <linux/workqueue.h>
29#include <linux/interrupt.h>
84517482 30#include <linux/firmware.h>
5a0e3ad6 31#include <linux/slab.h>
ab1594e9 32#include <linux/u64_stats_sync.h>
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33
34#include "be_hw.h"
045508a8 35#include "be_roce.h"
6b7c5b94 36
c346e6e5 37#define DRV_VER "10.4u"
6b7c5b94 38#define DRV_NAME "be2net"
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39#define BE_NAME "Emulex BladeEngine2"
40#define BE3_NAME "Emulex BladeEngine3"
41#define OC_NAME "Emulex OneConnect"
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42#define OC_NAME_BE OC_NAME "(be3)"
43#define OC_NAME_LANCER OC_NAME "(Lancer)"
ecedb6ae 44#define OC_NAME_SH OC_NAME "(Skyhawk)"
f3effb45 45#define DRV_DESC "Emulex OneConnect NIC Driver"
6b7c5b94 46
c4ca2374 47#define BE_VENDOR_ID 0x19a2
fe6d2a38 48#define EMULEX_VENDOR_ID 0x10df
c4ca2374 49#define BE_DEVICE_ID1 0x211
12d7ea2c 50#define BE_DEVICE_ID2 0x221
fe6d2a38
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51#define OC_DEVICE_ID1 0x700 /* Device Id for BE2 cards */
52#define OC_DEVICE_ID2 0x710 /* Device Id for BE3 cards */
53#define OC_DEVICE_ID3 0xe220 /* Device id for Lancer cards */
12f4d0a8 54#define OC_DEVICE_ID4 0xe228 /* Device id for VF in Lancer */
ecedb6ae 55#define OC_DEVICE_ID5 0x720 /* Device Id for Skyhawk cards */
76b73530 56#define OC_DEVICE_ID6 0x728 /* Device id for VF in SkyHawk */
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57#define OC_SUBSYS_DEVICE_ID1 0xE602
58#define OC_SUBSYS_DEVICE_ID2 0xE642
59#define OC_SUBSYS_DEVICE_ID3 0xE612
60#define OC_SUBSYS_DEVICE_ID4 0xE652
c4ca2374 61
6b7c5b94 62/* Number of bytes of an RX frame that are copied to skb->data */
2e588f84 63#define BE_HDR_LEN ((u16) 64)
bb349bb4
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64/* allocate extra space to allow tunneling decapsulation without head reallocation */
65#define BE_RX_SKB_ALLOC_SIZE (BE_HDR_LEN + 64)
66
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67#define BE_MAX_JUMBO_FRAME_SIZE 9018
68#define BE_MIN_MTU 256
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69#define BE_MAX_MTU (BE_MAX_JUMBO_FRAME_SIZE - \
70 (ETH_HLEN + ETH_FCS_LEN))
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71
72#define BE_NUM_VLANS_SUPPORTED 64
2632bafd 73#define BE_MAX_EQD 128u
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74#define BE_MAX_TX_FRAG_COUNT 30
75
76#define EVNT_Q_LEN 1024
77#define TX_Q_LEN 2048
78#define TX_CQ_LEN 1024
79#define RX_Q_LEN 1024 /* Does not support any other value */
80#define RX_CQ_LEN 1024
5fb379ee 81#define MCC_Q_LEN 128 /* total size not to exceed 8 pages */
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82#define MCC_CQ_LEN 256
83
10ef9ab4 84#define BE2_MAX_RSS_QS 4
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85#define BE3_MAX_RSS_QS 16
86#define BE3_MAX_TX_QS 16
87#define BE3_MAX_EVT_QS 16
e3dc867c 88#define BE3_SRIOV_MAX_EVT_QS 8
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89
90#define MAX_RX_QS 32
91#define MAX_EVT_QS 32
92#define MAX_TX_QS 32
10ef9ab4 93
045508a8 94#define MAX_ROCE_EQS 5
68d7bdcb 95#define MAX_MSIX_VECTORS 32
92bf14ab 96#define MIN_MSIX_VECTORS 1
6b7c5b94 97#define BE_NAPI_WEIGHT 64
10ef9ab4 98#define MAX_RX_POST BE_NAPI_WEIGHT /* Frags posted at a time */
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99#define RX_FRAGS_REFILL_WM (RX_Q_LEN - MAX_RX_POST)
100
7c5a5242 101#define MAX_VFS 30 /* Max VFs supported by BE3 FW */
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102#define FW_VER_LEN 32
103
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104#define RSS_INDIR_TABLE_LEN 128
105#define RSS_HASH_KEY_LEN 40
106
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107struct be_dma_mem {
108 void *va;
109 dma_addr_t dma;
110 u32 size;
111};
112
113struct be_queue_info {
114 struct be_dma_mem dma_mem;
115 u16 len;
116 u16 entry_size; /* Size of an element in the queue */
117 u16 id;
118 u16 tail, head;
119 bool created;
120 atomic_t used; /* Number of valid elements in the queue */
121};
122
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123static inline u32 MODULO(u16 val, u16 limit)
124{
125 BUG_ON(limit & (limit - 1));
126 return val & (limit - 1);
127}
128
129static inline void index_adv(u16 *index, u16 val, u16 limit)
130{
131 *index = MODULO((*index + val), limit);
132}
133
134static inline void index_inc(u16 *index, u16 limit)
135{
136 *index = MODULO((*index + 1), limit);
137}
138
139static inline void *queue_head_node(struct be_queue_info *q)
140{
141 return q->dma_mem.va + q->head * q->entry_size;
142}
143
144static inline void *queue_tail_node(struct be_queue_info *q)
145{
146 return q->dma_mem.va + q->tail * q->entry_size;
147}
148
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149static inline void *queue_index_node(struct be_queue_info *q, u16 index)
150{
151 return q->dma_mem.va + index * q->entry_size;
152}
153
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154static inline void queue_head_inc(struct be_queue_info *q)
155{
156 index_inc(&q->head, q->len);
157}
158
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159static inline void index_dec(u16 *index, u16 limit)
160{
161 *index = MODULO((*index - 1), limit);
162}
163
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164static inline void queue_tail_inc(struct be_queue_info *q)
165{
166 index_inc(&q->tail, q->len);
167}
168
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169struct be_eq_obj {
170 struct be_queue_info q;
171 char desc[32];
172
173 /* Adaptive interrupt coalescing (AIC) info */
174 bool enable_aic;
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175 u32 min_eqd; /* in usecs */
176 u32 max_eqd; /* in usecs */
177 u32 eqd; /* configured val when aic is off */
178 u32 cur_eqd; /* in usecs */
5fb379ee 179
10ef9ab4 180 u8 idx; /* array index */
f2f781a7 181 u8 msix_idx;
d0b9cec3 182 u16 spurious_intr;
5fb379ee 183 struct napi_struct napi;
10ef9ab4 184 struct be_adapter *adapter;
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185
186#ifdef CONFIG_NET_RX_BUSY_POLL
187#define BE_EQ_IDLE 0
188#define BE_EQ_NAPI 1 /* napi owns this EQ */
189#define BE_EQ_POLL 2 /* poll owns this EQ */
190#define BE_EQ_LOCKED (BE_EQ_NAPI | BE_EQ_POLL)
191#define BE_EQ_NAPI_YIELD 4 /* napi yielded this EQ */
192#define BE_EQ_POLL_YIELD 8 /* poll yielded this EQ */
193#define BE_EQ_YIELD (BE_EQ_NAPI_YIELD | BE_EQ_POLL_YIELD)
194#define BE_EQ_USER_PEND (BE_EQ_POLL | BE_EQ_POLL_YIELD)
195 unsigned int state;
196 spinlock_t lock; /* lock to serialize napi and busy-poll */
197#endif /* CONFIG_NET_RX_BUSY_POLL */
10ef9ab4 198} ____cacheline_aligned_in_smp;
5fb379ee 199
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200struct be_aic_obj { /* Adaptive interrupt coalescing (AIC) info */
201 bool enable;
202 u32 min_eqd; /* in usecs */
203 u32 max_eqd; /* in usecs */
204 u32 prev_eqd; /* in usecs */
205 u32 et_eqd; /* configured val when aic is off */
206 ulong jiffies;
207 u64 rx_pkts_prev; /* Used to calculate RX pps */
208 u64 tx_reqs_prev; /* Used to calculate TX pps */
209};
210
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211enum {
212 NAPI_POLLING,
213 BUSY_POLLING
214};
215
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216struct be_mcc_obj {
217 struct be_queue_info q;
218 struct be_queue_info cq;
7a1e9b20 219 bool rearm_cq;
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220};
221
3abcdeda 222struct be_tx_stats {
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223 u64 tx_bytes;
224 u64 tx_pkts;
225 u64 tx_reqs;
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226 u64 tx_compl;
227 ulong tx_jiffies;
228 u32 tx_stops;
bc617526 229 u32 tx_drv_drops; /* pkts dropped by driver */
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230 /* the error counters are described in be_ethtool.c */
231 u32 tx_hdr_parse_err;
232 u32 tx_dma_err;
233 u32 tx_tso_err;
234 u32 tx_spoof_check_err;
235 u32 tx_qinq_err;
236 u32 tx_internal_parity_err;
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237 struct u64_stats_sync sync;
238 struct u64_stats_sync sync_compl;
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239};
240
6b7c5b94 241struct be_tx_obj {
94d73aaa 242 u32 db_offset;
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243 struct be_queue_info q;
244 struct be_queue_info cq;
245 /* Remember the skbs that were transmitted */
246 struct sk_buff *sent_skb_list[TX_Q_LEN];
3c8def97 247 struct be_tx_stats stats;
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248 u16 pend_wrb_cnt; /* Number of WRBs yet to be given to HW */
249 u16 last_req_wrb_cnt; /* wrb cnt of the last req in the Q */
250 u16 last_req_hdr; /* index of the last req's hdr-wrb */
10ef9ab4 251} ____cacheline_aligned_in_smp;
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252
253/* Struct to remember the pages posted for rx frags */
254struct be_rx_page_info {
255 struct page *page;
e50287be 256 /* set to page-addr for last frag of the page & frag-addr otherwise */
fac6da5b 257 DEFINE_DMA_UNMAP_ADDR(bus);
6b7c5b94 258 u16 page_offset;
e50287be 259 bool last_frag; /* last frag of the page */
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260};
261
3abcdeda 262struct be_rx_stats {
3abcdeda 263 u64 rx_bytes;
3abcdeda 264 u64 rx_pkts;
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265 u32 rx_drops_no_skbs; /* skb allocation errors */
266 u32 rx_drops_no_frags; /* HW has no fetched frags */
267 u32 rx_post_fail; /* page post alloc failures */
ac124ff9 268 u32 rx_compl;
3abcdeda 269 u32 rx_mcast_pkts;
ac124ff9 270 u32 rx_compl_err; /* completions with err set */
ab1594e9 271 struct u64_stats_sync sync;
3abcdeda
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272};
273
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274struct be_rx_compl_info {
275 u32 rss_hash;
6709d952 276 u16 vlan_tag;
2e588f84 277 u16 pkt_size;
12004ae9 278 u16 port;
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279 u8 vlanf;
280 u8 num_rcvd;
281 u8 err;
282 u8 ipf;
283 u8 tcpf;
284 u8 udpf;
285 u8 ip_csum;
286 u8 l4_csum;
287 u8 ipv6;
f93f160b 288 u8 qnq;
2e588f84 289 u8 pkt_type;
e38b1706 290 u8 ip_frag;
c9c47142 291 u8 tunneled;
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292};
293
6b7c5b94 294struct be_rx_obj {
3abcdeda 295 struct be_adapter *adapter;
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296 struct be_queue_info q;
297 struct be_queue_info cq;
2e588f84 298 struct be_rx_compl_info rxcp;
6b7c5b94 299 struct be_rx_page_info page_info_tbl[RX_Q_LEN];
3abcdeda
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300 struct be_rx_stats stats;
301 u8 rss_id;
302 bool rx_post_starved; /* Zero rx frags have been posted to BE */
10ef9ab4 303} ____cacheline_aligned_in_smp;
6b7c5b94 304
609ff3bb 305struct be_drv_stats {
9ae081c6 306 u32 be_on_die_temperature;
ac124ff9 307 u32 eth_red_drops;
d3de1540 308 u32 dma_map_errors;
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309 u32 rx_drops_no_pbuf;
310 u32 rx_drops_no_txpb;
311 u32 rx_drops_no_erx_descr;
312 u32 rx_drops_no_tpre_descr;
313 u32 rx_drops_too_many_frags;
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314 u32 forwarded_packets;
315 u32 rx_drops_mtu;
316 u32 rx_crc_errors;
317 u32 rx_alignment_symbol_errors;
318 u32 rx_pause_frames;
319 u32 rx_priority_pause_frames;
320 u32 rx_control_frames;
321 u32 rx_in_range_errors;
322 u32 rx_out_range_errors;
323 u32 rx_frame_too_long;
18fb06a1 324 u32 rx_address_filtered;
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325 u32 rx_dropped_too_small;
326 u32 rx_dropped_too_short;
327 u32 rx_dropped_header_too_small;
328 u32 rx_dropped_tcp_length;
329 u32 rx_dropped_runt;
330 u32 rx_ip_checksum_errs;
331 u32 rx_tcp_checksum_errs;
332 u32 rx_udp_checksum_errs;
333 u32 tx_pauseframes;
334 u32 tx_priority_pauseframes;
335 u32 tx_controlframes;
336 u32 rxpp_fifo_overflow_drop;
337 u32 rx_input_fifo_overflow_drop;
338 u32 pmem_fifo_overflow_drop;
339 u32 jabber_events;
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340 u32 rx_roce_bytes_lsd;
341 u32 rx_roce_bytes_msd;
342 u32 rx_roce_frames;
343 u32 roce_drops_payload_len;
344 u32 roce_drops_crc;
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345};
346
c502224e
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347/* A vlan-id of 0xFFFF must be used to clear transparent vlan-tagging */
348#define BE_RESET_VLAN_TAG_ID 0xFFFF
349
64600ea5 350struct be_vf_cfg {
11ac75ed
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351 unsigned char mac_addr[ETH_ALEN];
352 int if_handle;
353 int pmac_id;
354 u16 vlan_tag;
355 u32 tx_rate;
bdce2ad7 356 u32 plink_tracking;
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357};
358
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359enum vf_state {
360 ENABLED = 0,
361 ASSIGNED = 1
362};
363
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364#define BE_FLAGS_LINK_STATUS_INIT BIT(1)
365#define BE_FLAGS_SRIOV_ENABLED BIT(2)
366#define BE_FLAGS_WORKER_SCHEDULED BIT(3)
83b06116
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367#define BE_FLAGS_NAPI_ENABLED BIT(6)
368#define BE_FLAGS_QNQ_ASYNC_EVT_RCVD BIT(7)
369#define BE_FLAGS_VXLAN_OFFLOADS BIT(8)
370#define BE_FLAGS_SETUP_DONE BIT(9)
b236916a 371
c9c47142
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372#define BE_UC_PMAC_COUNT 30
373#define BE_VF_UC_PMAC_COUNT 2
f0613380 374
5c510811
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375/* Ethtool set_dump flags */
376#define LANCER_INITIATE_FW_DUMP 0x1
f0613380 377#define LANCER_DELETE_FW_DUMP 0x2
5c510811 378
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379struct phy_info {
380 u8 transceiver;
381 u8 autoneg;
382 u8 fc_autoneg;
383 u8 port_type;
384 u16 phy_type;
385 u16 interface_type;
386 u32 misc_params;
387 u16 auto_speeds_supported;
388 u16 fixed_speeds_supported;
389 int link_speed;
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390 u32 advertising;
391 u32 supported;
6809cee0 392 u8 cable_type;
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393};
394
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395struct be_resources {
396 u16 max_vfs; /* Total VFs "really" supported by FW/HW */
397 u16 max_mcast_mac;
398 u16 max_tx_qs;
399 u16 max_rss_qs;
400 u16 max_rx_qs;
401 u16 max_uc_mac; /* Max UC MACs programmable */
402 u16 max_vlans; /* Number of vlans supported */
403 u16 max_evt_qs;
404 u32 if_cap_flags;
10cccf60 405 u32 vf_if_cap_flags; /* VF if capability flags */
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406};
407
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408struct rss_info {
409 u64 rss_flags;
410 u8 rsstable[RSS_INDIR_TABLE_LEN];
411 u8 rss_queue[RSS_INDIR_TABLE_LEN];
412 u8 rss_hkey[RSS_HASH_KEY_LEN];
413};
414
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415struct be_adapter {
416 struct pci_dev *pdev;
417 struct net_device *netdev;
418
c5b3ad4c 419 u8 __iomem *csr; /* CSR BAR used only for BE2/3 */
8788fdc2 420 u8 __iomem *db; /* Door Bell */
8788fdc2 421
2984961c 422 struct mutex mbox_lock; /* For serializing mbox cmds to BE card */
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423 struct be_dma_mem mbox_mem;
424 /* Mbox mem is adjusted to align to 16 bytes. The allocated addr
425 * is stored for freeing purpose */
426 struct be_dma_mem mbox_mem_alloced;
427
428 struct be_mcc_obj mcc_obj;
429 spinlock_t mcc_lock; /* For serializing mcc cmds to BE card */
430 spinlock_t mcc_cq_lock;
6b7c5b94 431
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432 u16 cfg_num_qs; /* configured via set-channels */
433 u16 num_evt_qs;
434 u16 num_msix_vec;
435 struct be_eq_obj eq_obj[MAX_EVT_QS];
10ef9ab4 436 struct msix_entry msix_entries[MAX_MSIX_VECTORS];
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437 bool isr_registered;
438
439 /* TX Rings */
92bf14ab 440 u16 num_tx_qs;
3c8def97 441 struct be_tx_obj tx_obj[MAX_TX_QS];
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442
443 /* Rx rings */
92bf14ab 444 u16 num_rx_qs;
10ef9ab4 445 struct be_rx_obj rx_obj[MAX_RX_QS];
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446 u32 big_page_size; /* Compounded page size shared by rx wrbs */
447
609ff3bb 448 struct be_drv_stats drv_stats;
2632bafd 449 struct be_aic_obj aic_obj[MAX_EVT_QS];
cc4ce020
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450 u8 vlan_prio_bmap; /* Available Priority BitMap */
451 u16 recommended_prio; /* Recommended Priority */
5b8821b7 452 struct be_dma_mem rx_filter; /* Cmd DMA mem for rx-filter */
6b7c5b94 453
3abcdeda 454 struct be_dma_mem stats_cmd;
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455 /* Work queue used to perform periodic tasks like getting statistics */
456 struct delayed_work work;
609ff3bb 457 u16 work_counter;
6b7c5b94 458
f67ef7ba 459 struct delayed_work func_recovery_work;
b236916a 460 u32 flags;
f25b119c 461 u32 cmd_privileges;
6b7c5b94 462 /* Ethtool knobs and info */
6b7c5b94 463 char fw_ver[FW_VER_LEN];
eeb65ced 464 char fw_on_flash[FW_VER_LEN];
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465
466 /* IFACE filtering fields */
30128031 467 int if_handle; /* Used to configure filtering */
f66b7cfd 468 u32 if_flags; /* Interface filtering flags */
fbc13f01 469 u32 *pmac_id; /* MAC addr handle used by BE card */
f66b7cfd
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470 u32 uc_macs; /* Count of secondary UC MAC programmed */
471 unsigned long vids[BITS_TO_LONGS(VLAN_N_VID)];
472 u16 vlans_added;
473
1a642469 474 u32 beacon_state; /* for set_phys_id */
6b7c5b94 475
f67ef7ba 476 bool eeh_error;
6589ade0 477 bool fw_timeout;
f67ef7ba
PR
478 bool hw_error;
479
6b7c5b94 480 u32 port_num;
f93f160b 481 u8 mc_type;
3486be29 482 u32 function_mode;
3abcdeda 483 u32 function_caps;
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484 u32 rx_fc; /* Rx flow control */
485 u32 tx_fc; /* Tx flow control */
b2aebe6d 486 bool stats_cmd_sent;
045508a8 487 struct {
045508a8
PP
488 u32 size;
489 u32 total_size;
490 u64 io_addr;
491 } roce_db;
492 u32 num_msix_roce_vec;
493 struct ocrdma_dev *ocrdma_dev;
494 struct list_head entry;
495
dd131e76 496 u32 flash_status;
5eeff635 497 struct completion et_cmd_compl;
ba343c77 498
bec84e6b 499 struct be_resources pool_res; /* resources available for the port */
92bf14ab
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500 struct be_resources res; /* resources available for the func */
501 u16 num_vfs; /* Number of VFs provisioned by PF */
39f1d94d 502 u8 virtfn;
11ac75ed
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503 struct be_vf_cfg *vf_cfg;
504 bool be3_native;
fe6d2a38 505 u32 sli_family;
9e1453c5 506 u8 hba_port_num;
3968fa1e 507 u16 pvid;
c9c47142 508 __be16 vxlan_port;
630f4b70 509 int vxlan_port_count;
42f11cf2 510 struct phy_info phy;
4762f6ce 511 u8 wol_cap;
76a9e08e 512 bool wol_en;
0ad3157e 513 u16 asic_rev;
bc0c3405 514 u16 qnq_vid;
941a77d5 515 u32 msg_enable;
7aeb2156 516 int be_get_temp_freq;
d5c18473 517 u8 pf_number;
e2557877 518 struct rss_info rss_info;
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519};
520
39f1d94d 521#define be_physfn(adapter) (!adapter->virtfn)
2c7a9dc1 522#define be_virtfn(adapter) (adapter->virtfn)
f174c7ec
VV
523#define sriov_enabled(adapter) (adapter->flags & \
524 BE_FLAGS_SRIOV_ENABLED)
bec84e6b 525
11ac75ed
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526#define for_all_vfs(adapter, vf_cfg, i) \
527 for (i = 0, vf_cfg = &adapter->vf_cfg[i]; i < adapter->num_vfs; \
528 i++, vf_cfg++)
ba343c77 529
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530#define ON 1
531#define OFF 0
ca34fe38 532
92bf14ab
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533#define be_max_vlans(adapter) (adapter->res.max_vlans)
534#define be_max_uc(adapter) (adapter->res.max_uc_mac)
535#define be_max_mc(adapter) (adapter->res.max_mcast_mac)
bec84e6b 536#define be_max_vfs(adapter) (adapter->pool_res.max_vfs)
92bf14ab
SP
537#define be_max_rss(adapter) (adapter->res.max_rss_qs)
538#define be_max_txqs(adapter) (adapter->res.max_tx_qs)
539#define be_max_prio_txqs(adapter) (adapter->res.max_prio_tx_qs)
540#define be_max_rxqs(adapter) (adapter->res.max_rx_qs)
541#define be_max_eqs(adapter) (adapter->res.max_evt_qs)
542#define be_if_cap_flags(adapter) (adapter->res.if_cap_flags)
543
544static inline u16 be_max_qs(struct be_adapter *adapter)
545{
546 /* If no RSS, need atleast the one def RXQ */
547 u16 num = max_t(u16, be_max_rss(adapter), 1);
548
549 num = min(num, be_max_eqs(adapter));
550 return min_t(u16, num, num_online_cpus());
551}
552
f93f160b
VV
553/* Is BE in pvid_tagging mode */
554#define be_pvid_tagging_enabled(adapter) (adapter->pvid)
555
556/* Is BE in QNQ multi-channel mode */
66064dbc 557#define be_is_qnq_mode(adapter) (adapter->function_mode & QNQ_MODE)
f93f160b 558
ca34fe38
SP
559#define lancer_chip(adapter) (adapter->pdev->device == OC_DEVICE_ID3 || \
560 adapter->pdev->device == OC_DEVICE_ID4)
fe6d2a38 561
76b73530
PR
562#define skyhawk_chip(adapter) (adapter->pdev->device == OC_DEVICE_ID5 || \
563 adapter->pdev->device == OC_DEVICE_ID6)
d3bd3a5e 564
ca34fe38
SP
565#define BE3_chip(adapter) (adapter->pdev->device == BE_DEVICE_ID2 || \
566 adapter->pdev->device == OC_DEVICE_ID2)
567
568#define BE2_chip(adapter) (adapter->pdev->device == BE_DEVICE_ID1 || \
569 adapter->pdev->device == OC_DEVICE_ID1)
570
571#define BEx_chip(adapter) (BE3_chip(adapter) || BE2_chip(adapter))
d3bd3a5e 572
dbf0f2a7
SP
573#define be_roce_supported(adapter) (skyhawk_chip(adapter) && \
574 (adapter->function_mode & RDMA_ENABLED))
045508a8 575
0fc0b732 576extern const struct ethtool_ops be_ethtool_ops;
6b7c5b94 577
ac6a0c4a 578#define msix_enabled(adapter) (adapter->num_msix_vec > 0)
10ef9ab4
SP
579#define num_irqs(adapter) (msix_enabled(adapter) ? \
580 adapter->num_msix_vec : 1)
581#define tx_stats(txo) (&(txo)->stats)
582#define rx_stats(rxo) (&(rxo)->stats)
6b7c5b94 583
10ef9ab4
SP
584/* The default RXQ is the last RXQ */
585#define default_rxo(adpt) (&adpt->rx_obj[adpt->num_rx_qs - 1])
6b7c5b94 586
3abcdeda
SP
587#define for_all_rx_queues(adapter, rxo, i) \
588 for (i = 0, rxo = &adapter->rx_obj[i]; i < adapter->num_rx_qs; \
589 i++, rxo++)
590
10ef9ab4 591/* Skip the default non-rss queue (last one)*/
3abcdeda 592#define for_all_rss_queues(adapter, rxo, i) \
10ef9ab4 593 for (i = 0, rxo = &adapter->rx_obj[i]; i < (adapter->num_rx_qs - 1);\
3abcdeda
SP
594 i++, rxo++)
595
3c8def97
SP
596#define for_all_tx_queues(adapter, txo, i) \
597 for (i = 0, txo = &adapter->tx_obj[i]; i < adapter->num_tx_qs; \
598 i++, txo++)
599
10ef9ab4
SP
600#define for_all_evt_queues(adapter, eqo, i) \
601 for (i = 0, eqo = &adapter->eq_obj[i]; i < adapter->num_evt_qs; \
602 i++, eqo++)
603
6384a4d0
SP
604#define for_all_rx_queues_on_eq(adapter, eqo, rxo, i) \
605 for (i = eqo->idx, rxo = &adapter->rx_obj[i]; i < adapter->num_rx_qs;\
606 i += adapter->num_evt_qs, rxo += adapter->num_evt_qs)
607
a4906ea0
SP
608#define for_all_tx_queues_on_eq(adapter, eqo, txo, i) \
609 for (i = eqo->idx, txo = &adapter->tx_obj[i]; i < adapter->num_tx_qs;\
610 i += adapter->num_evt_qs, txo += adapter->num_evt_qs)
611
10ef9ab4
SP
612#define is_mcc_eqo(eqo) (eqo->idx == 0)
613#define mcc_eqo(adapter) (&adapter->eq_obj[0])
614
6b7c5b94
SP
615#define PAGE_SHIFT_4K 12
616#define PAGE_SIZE_4K (1 << PAGE_SHIFT_4K)
617
618/* Returns number of pages spanned by the data starting at the given addr */
619#define PAGES_4K_SPANNED(_address, size) \
620 ((u32)((((size_t)(_address) & (PAGE_SIZE_4K - 1)) + \
621 (size) + (PAGE_SIZE_4K - 1)) >> PAGE_SHIFT_4K))
622
6b7c5b94
SP
623/* Returns bit offset within a DWORD of a bitfield */
624#define AMAP_BIT_OFFSET(_struct, field) \
625 (((size_t)&(((_struct *)0)->field))%32)
626
627/* Returns the bit mask of the field that is NOT shifted into location. */
628static inline u32 amap_mask(u32 bitsize)
629{
630 return (bitsize == 32 ? 0xFFFFFFFF : (1 << bitsize) - 1);
631}
632
633static inline void
634amap_set(void *ptr, u32 dw_offset, u32 mask, u32 offset, u32 value)
635{
636 u32 *dw = (u32 *) ptr + dw_offset;
637 *dw &= ~(mask << offset);
638 *dw |= (mask & value) << offset;
639}
640
641#define AMAP_SET_BITS(_struct, field, ptr, val) \
642 amap_set(ptr, \
643 offsetof(_struct, field)/32, \
644 amap_mask(sizeof(((_struct *)0)->field)), \
645 AMAP_BIT_OFFSET(_struct, field), \
646 val)
647
648static inline u32 amap_get(void *ptr, u32 dw_offset, u32 mask, u32 offset)
649{
650 u32 *dw = (u32 *) ptr;
651 return mask & (*(dw + dw_offset) >> offset);
652}
653
654#define AMAP_GET_BITS(_struct, field, ptr) \
655 amap_get(ptr, \
656 offsetof(_struct, field)/32, \
657 amap_mask(sizeof(((_struct *)0)->field)), \
658 AMAP_BIT_OFFSET(_struct, field))
659
c3c18bc1
SP
660#define GET_RX_COMPL_V0_BITS(field, ptr) \
661 AMAP_GET_BITS(struct amap_eth_rx_compl_v0, field, ptr)
662
663#define GET_RX_COMPL_V1_BITS(field, ptr) \
664 AMAP_GET_BITS(struct amap_eth_rx_compl_v1, field, ptr)
665
666#define GET_TX_COMPL_BITS(field, ptr) \
667 AMAP_GET_BITS(struct amap_eth_tx_compl, field, ptr)
668
669#define SET_TX_WRB_HDR_BITS(field, ptr, val) \
670 AMAP_SET_BITS(struct amap_eth_hdr_wrb, field, ptr, val)
671
6b7c5b94
SP
672#define be_dws_cpu_to_le(wrb, len) swap_dws(wrb, len)
673#define be_dws_le_to_cpu(wrb, len) swap_dws(wrb, len)
674static inline void swap_dws(void *wrb, int len)
675{
676#ifdef __BIG_ENDIAN
677 u32 *dw = wrb;
678 BUG_ON(len % 4);
679 do {
680 *dw = cpu_to_le32(*dw);
681 dw++;
682 len -= 4;
683 } while (len);
684#endif /* __BIG_ENDIAN */
685}
686
0532d4e3
KA
687#define be_cmd_status(status) (status > 0 ? -EIO : status)
688
6b7c5b94
SP
689static inline u8 is_tcp_pkt(struct sk_buff *skb)
690{
691 u8 val = 0;
692
693 if (ip_hdr(skb)->version == 4)
694 val = (ip_hdr(skb)->protocol == IPPROTO_TCP);
695 else if (ip_hdr(skb)->version == 6)
696 val = (ipv6_hdr(skb)->nexthdr == NEXTHDR_TCP);
697
698 return val;
699}
700
701static inline u8 is_udp_pkt(struct sk_buff *skb)
702{
703 u8 val = 0;
704
705 if (ip_hdr(skb)->version == 4)
706 val = (ip_hdr(skb)->protocol == IPPROTO_UDP);
707 else if (ip_hdr(skb)->version == 6)
708 val = (ipv6_hdr(skb)->nexthdr == NEXTHDR_UDP);
709
710 return val;
711}
712
93040ae5
SK
713static inline bool is_ipv4_pkt(struct sk_buff *skb)
714{
e8efcec5 715 return skb->protocol == htons(ETH_P_IP) && ip_hdr(skb)->version == 4;
93040ae5
SK
716}
717
4b972914
AK
718static inline bool be_multi_rxq(const struct be_adapter *adapter)
719{
720 return adapter->num_rx_qs > 1;
721}
722
6589ade0
SP
723static inline bool be_error(struct be_adapter *adapter)
724{
f67ef7ba
PR
725 return adapter->eeh_error || adapter->hw_error || adapter->fw_timeout;
726}
727
d23e946c 728static inline bool be_hw_error(struct be_adapter *adapter)
f67ef7ba
PR
729{
730 return adapter->eeh_error || adapter->hw_error;
731}
732
733static inline void be_clear_all_error(struct be_adapter *adapter)
734{
735 adapter->eeh_error = false;
736 adapter->hw_error = false;
737 adapter->fw_timeout = false;
6589ade0
SP
738}
739
31886e87
JP
740void be_cq_notify(struct be_adapter *adapter, u16 qid, bool arm,
741 u16 num_popped);
742void be_link_status_update(struct be_adapter *adapter, u8 link_status);
743void be_parse_stats(struct be_adapter *adapter);
744int be_load_fw(struct be_adapter *adapter, u8 *func);
745bool be_is_wol_supported(struct be_adapter *adapter);
746bool be_pause_supported(struct be_adapter *adapter);
747u32 be_get_fw_log_level(struct be_adapter *adapter);
68d7bdcb
SP
748int be_update_queues(struct be_adapter *adapter);
749int be_poll(struct napi_struct *napi, int budget);
941a77d5 750
045508a8
PP
751/*
752 * internal function to initialize-cleanup roce device.
753 */
31886e87
JP
754void be_roce_dev_add(struct be_adapter *);
755void be_roce_dev_remove(struct be_adapter *);
045508a8
PP
756
757/*
758 * internal function to open-close roce device during ifup-ifdown.
759 */
31886e87
JP
760void be_roce_dev_open(struct be_adapter *);
761void be_roce_dev_close(struct be_adapter *);
d114f99a 762void be_roce_dev_shutdown(struct be_adapter *);
045508a8 763
6b7c5b94 764#endif /* BE_H */
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