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netpoll: revert 6bdb7fe3104 and fix be_poll() instead
[deliverable/linux.git] / drivers / net / ethernet / emulex / benet / be_cmds.c
CommitLineData
6b7c5b94 1/*
d2145cde 2 * Copyright (C) 2005 - 2011 Emulex
6b7c5b94
SP		 3 * All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License version 2
7 * as published by the Free Software Foundation. The full GNU General
8 * Public License is included in this distribution in the file called COPYING.
9 *
10 * Contact Information:
d2145cde 11 * linux-drivers@emulex.com
6b7c5b94 12 *
d2145cde
AK		 13 * Emulex
14 * 3333 Susan Street
15 * Costa Mesa, CA 92626
6b7c5b94
SP		 16 */
17
6a4ab669 18#include <linux/module.h>
6b7c5b94 19#include "be.h"
8788fdc2 20#include "be_cmds.h"
6b7c5b94 21
3de09455
SK		 22static inline void *embedded_payload(struct be_mcc_wrb *wrb)
23{
24 return wrb->payload.embedded_payload;
25}
609ff3bb 26
8788fdc2 27static void be_mcc_notify(struct be_adapter *adapter)
5fb379ee 28{
8788fdc2 29 struct be_queue_info *mccq = &adapter->mcc_obj.q;
5fb379ee
SP		 30 u32 val = 0;
31
6589ade0 32 if (be_error(adapter))
7acc2087 33 return;
7acc2087 34
5fb379ee
SP		 35 val |= mccq->id & DB_MCCQ_RING_ID_MASK;
36 val |= 1 << DB_MCCQ_NUM_POSTED_SHIFT;
f3eb62d2
SP		 37
38 wmb();
8788fdc2 39 iowrite32(val, adapter->db + DB_MCCQ_OFFSET);
5fb379ee
SP		 40}
41
42/* To check if valid bit is set, check the entire word as we don't know
43 * the endianness of the data (old entry is host endian while a new entry is
44 * little endian) */
efd2e40a 45static inline bool be_mcc_compl_is_new(struct be_mcc_compl *compl)
5fb379ee
SP		 46{
47 if (compl->flags != 0) {
48 compl->flags = le32_to_cpu(compl->flags);
49 BUG_ON((compl->flags & CQE_FLAGS_VALID_MASK) == 0);
50 return true;
51 } else {
52 return false;
53 }
54}
55
56/* Need to reset the entire word that houses the valid bit */
efd2e40a 57static inline void be_mcc_compl_use(struct be_mcc_compl *compl)
5fb379ee
SP		 58{
59 compl->flags = 0;
60}
61
652bf646
PR		 62static struct be_cmd_resp_hdr *be_decode_resp_hdr(u32 tag0, u32 tag1)
63{
64 unsigned long addr;
65
66 addr = tag1;
67 addr = ((addr << 16) << 16) | tag0;
68 return (void *)addr;
69}
70
8788fdc2 71static int be_mcc_compl_process(struct be_adapter *adapter,
652bf646 72 struct be_mcc_compl *compl)
5fb379ee
SP		 73{
74 u16 compl_status, extd_status;
652bf646
PR		 75 struct be_cmd_resp_hdr *resp_hdr;
76 u8 opcode = 0, subsystem = 0;
5fb379ee
SP		 77
78 /* Just swap the status to host endian; mcc tag is opaquely copied
79 * from mcc_wrb */
80 be_dws_le_to_cpu(compl, 4);
81
82 compl_status = (compl->status >> CQE_STATUS_COMPL_SHIFT) &
83 CQE_STATUS_COMPL_MASK;
dd131e76 84
652bf646
PR		 85 resp_hdr = be_decode_resp_hdr(compl->tag0, compl->tag1);
86
87 if (resp_hdr) {
88 opcode = resp_hdr->opcode;
89 subsystem = resp_hdr->subsystem;
90 }
91
92 if (((opcode == OPCODE_COMMON_WRITE_FLASHROM) ||
93 (opcode == OPCODE_COMMON_WRITE_OBJECT)) &&
94 (subsystem == CMD_SUBSYSTEM_COMMON)) {
dd131e76
SB		 95 adapter->flash_status = compl_status;
96 complete(&adapter->flash_compl);
97 }
98
b31c50a7 99 if (compl_status == MCC_STATUS_SUCCESS) {
652bf646
PR		 100 if (((opcode == OPCODE_ETH_GET_STATISTICS) ||
101 (opcode == OPCODE_ETH_GET_PPORT_STATS)) &&
102 (subsystem == CMD_SUBSYSTEM_ETH)) {
89a88ab8 103 be_parse_stats(adapter);
b2aebe6d 104 adapter->stats_cmd_sent = false;
b31c50a7 105 }
652bf646
PR		 106 if (opcode == OPCODE_COMMON_GET_CNTL_ADDITIONAL_ATTRIBUTES &&
107 subsystem == CMD_SUBSYSTEM_COMMON) {
3de09455 108 struct be_cmd_resp_get_cntl_addnl_attribs *resp =
652bf646 109 (void *)resp_hdr;
3de09455
SK		 110 adapter->drv_stats.be_on_die_temperature =
111 resp->on_die_temperature;
112 }
2b3f291b 113 } else {
652bf646 114 if (opcode == OPCODE_COMMON_GET_CNTL_ADDITIONAL_ATTRIBUTES)
7aeb2156 115 adapter->be_get_temp_freq = 0;
3de09455 116
2b3f291b
SP		 117 if (compl_status == MCC_STATUS_NOT_SUPPORTED ||
118 compl_status == MCC_STATUS_ILLEGAL_REQUEST)
119 goto done;
120
121 if (compl_status == MCC_STATUS_UNAUTHORIZED_REQUEST) {
97f1d8cd
VV		 122 dev_warn(&adapter->pdev->dev,
123 "opcode %d-%d is not permitted\n",
124 opcode, subsystem);
2b3f291b
SP		 125 } else {
126 extd_status = (compl->status >> CQE_STATUS_EXTD_SHIFT) &
127 CQE_STATUS_EXTD_MASK;
97f1d8cd
VV		 128 dev_err(&adapter->pdev->dev,
129 "opcode %d-%d failed:status %d-%d\n",
130 opcode, subsystem, compl_status, extd_status);
2b3f291b 131 }
5fb379ee 132 }
2b3f291b 133done:
b31c50a7 134 return compl_status;
5fb379ee
SP		 135}
136
a8f447bd 137/* Link state evt is a string of bytes; no need for endian swapping */
8788fdc2 138static void be_async_link_state_process(struct be_adapter *adapter,
a8f447bd
SP		 139 struct be_async_event_link_state *evt)
140{
b236916a 141 /* When link status changes, link speed must be re-queried from FW */
42f11cf2 142 adapter->phy.link_speed = -1;
b236916a 143
2e177a5c
PR		 144 /* Ignore physical link event */
145 if (lancer_chip(adapter) &&
146 !(evt->port_link_status & LOGICAL_LINK_STATUS_MASK))
147 return;
148
b236916a
AK		 149 /* For the initial link status do not rely on the ASYNC event as
150 * it may not be received in some cases.
151 */
152 if (adapter->flags & BE_FLAGS_LINK_STATUS_INIT)
153 be_link_status_update(adapter, evt->port_link_status);
a8f447bd
SP		 154}
155
cc4ce020
SK		 156/* Grp5 CoS Priority evt */
157static void be_async_grp5_cos_priority_process(struct be_adapter *adapter,
158 struct be_async_event_grp5_cos_priority *evt)
159{
160 if (evt->valid) {
161 adapter->vlan_prio_bmap = evt->available_priority_bmap;
60964dd7 162 adapter->recommended_prio &= ~VLAN_PRIO_MASK;
cc4ce020
SK		 163 adapter->recommended_prio =
164 evt->reco_default_priority << VLAN_PRIO_SHIFT;
165 }
166}
167
168/* Grp5 QOS Speed evt */
169static void be_async_grp5_qos_speed_process(struct be_adapter *adapter,
170 struct be_async_event_grp5_qos_link_speed *evt)
171{
172 if (evt->physical_port == adapter->port_num) {
173 /* qos_link_speed is in units of 10 Mbps */
42f11cf2 174 adapter->phy.link_speed = evt->qos_link_speed * 10;
cc4ce020
SK		 175 }
176}
177
3968fa1e
AK		 178/*Grp5 PVID evt*/
179static void be_async_grp5_pvid_state_process(struct be_adapter *adapter,
180 struct be_async_event_grp5_pvid_state *evt)
181{
182 if (evt->enabled)
939cf306 183 adapter->pvid = le16_to_cpu(evt->tag) & VLAN_VID_MASK;
3968fa1e
AK		 184 else
185 adapter->pvid = 0;
186}
187
cc4ce020
SK		 188static void be_async_grp5_evt_process(struct be_adapter *adapter,
189 u32 trailer, struct be_mcc_compl *evt)
190{
191 u8 event_type = 0;
192
193 event_type = (trailer >> ASYNC_TRAILER_EVENT_TYPE_SHIFT) &
194 ASYNC_TRAILER_EVENT_TYPE_MASK;
195
196 switch (event_type) {
197 case ASYNC_EVENT_COS_PRIORITY:
198 be_async_grp5_cos_priority_process(adapter,
199 (struct be_async_event_grp5_cos_priority *)evt);
200 break;
201 case ASYNC_EVENT_QOS_SPEED:
202 be_async_grp5_qos_speed_process(adapter,
203 (struct be_async_event_grp5_qos_link_speed *)evt);
204 break;
3968fa1e
AK		 205 case ASYNC_EVENT_PVID_STATE:
206 be_async_grp5_pvid_state_process(adapter,
207 (struct be_async_event_grp5_pvid_state *)evt);
208 break;
cc4ce020
SK		 209 default:
210 dev_warn(&adapter->pdev->dev, "Unknown grp5 event!\n");
211 break;
212 }
213}
214
a8f447bd
SP		 215static inline bool is_link_state_evt(u32 trailer)
216{
807540ba 217 return ((trailer >> ASYNC_TRAILER_EVENT_CODE_SHIFT) &
a8f447bd 218 ASYNC_TRAILER_EVENT_CODE_MASK) ==
807540ba 219 ASYNC_EVENT_CODE_LINK_STATE;
a8f447bd 220}
5fb379ee 221
cc4ce020
SK		 222static inline bool is_grp5_evt(u32 trailer)
223{
224 return (((trailer >> ASYNC_TRAILER_EVENT_CODE_SHIFT) &
225 ASYNC_TRAILER_EVENT_CODE_MASK) ==
226 ASYNC_EVENT_CODE_GRP_5);
227}
228
efd2e40a 229static struct be_mcc_compl *be_mcc_compl_get(struct be_adapter *adapter)
5fb379ee 230{
8788fdc2 231 struct be_queue_info *mcc_cq = &adapter->mcc_obj.cq;
efd2e40a 232 struct be_mcc_compl *compl = queue_tail_node(mcc_cq);
5fb379ee
SP		 233
234 if (be_mcc_compl_is_new(compl)) {
235 queue_tail_inc(mcc_cq);
236 return compl;
237 }
238 return NULL;
239}
240
7a1e9b20
SP		 241void be_async_mcc_enable(struct be_adapter *adapter)
242{
243 spin_lock_bh(&adapter->mcc_cq_lock);
244
245 be_cq_notify(adapter, adapter->mcc_obj.cq.id, true, 0);
246 adapter->mcc_obj.rearm_cq = true;
247
248 spin_unlock_bh(&adapter->mcc_cq_lock);
249}
250
251void be_async_mcc_disable(struct be_adapter *adapter)
252{
253 adapter->mcc_obj.rearm_cq = false;
254}
255
10ef9ab4 256int be_process_mcc(struct be_adapter *adapter)
5fb379ee 257{
efd2e40a 258 struct be_mcc_compl *compl;
10ef9ab4 259 int num = 0, status = 0;
7a1e9b20 260 struct be_mcc_obj *mcc_obj = &adapter->mcc_obj;
5fb379ee 261
072a9c48 262 spin_lock(&adapter->mcc_cq_lock);
8788fdc2 263 while ((compl = be_mcc_compl_get(adapter))) {
a8f447bd
SP		 264 if (compl->flags & CQE_FLAGS_ASYNC_MASK) {
265 /* Interpret flags as an async trailer */
323f30b3
AK		 266 if (is_link_state_evt(compl->flags))
267 be_async_link_state_process(adapter,
a8f447bd 268 (struct be_async_event_link_state *) compl);
cc4ce020
SK		 269 else if (is_grp5_evt(compl->flags))
270 be_async_grp5_evt_process(adapter,
271 compl->flags, compl);
b31c50a7 272 } else if (compl->flags & CQE_FLAGS_COMPLETED_MASK) {
10ef9ab4 273 status = be_mcc_compl_process(adapter, compl);
7a1e9b20 274 atomic_dec(&mcc_obj->q.used);
5fb379ee
SP		 275 }
276 be_mcc_compl_use(compl);
277 num++;
278 }
b31c50a7 279
10ef9ab4
SP		 280 if (num)
281 be_cq_notify(adapter, mcc_obj->cq.id, mcc_obj->rearm_cq, num);
282
072a9c48 283 spin_unlock(&adapter->mcc_cq_lock);
10ef9ab4 284 return status;
5fb379ee
SP		 285}
286
6ac7b687 287/* Wait till no more pending mcc requests are present */
b31c50a7 288static int be_mcc_wait_compl(struct be_adapter *adapter)
6ac7b687 289{
b31c50a7 290#define mcc_timeout 120000 /* 12s timeout */
10ef9ab4 291 int i, status = 0;
f31e50a8
SP		 292 struct be_mcc_obj *mcc_obj = &adapter->mcc_obj;
293
6ac7b687 294 for (i = 0; i < mcc_timeout; i++) {
6589ade0
SP		 295 if (be_error(adapter))
296 return -EIO;
297
072a9c48 298 local_bh_disable();
10ef9ab4 299 status = be_process_mcc(adapter);
072a9c48 300 local_bh_enable();
b31c50a7 301
f31e50a8 302 if (atomic_read(&mcc_obj->q.used) == 0)
6ac7b687
SP		 303 break;
304 udelay(100);
305 }
b31c50a7 306 if (i == mcc_timeout) {
6589ade0
SP		 307 dev_err(&adapter->pdev->dev, "FW not responding\n");
308 adapter->fw_timeout = true;
652bf646 309 return -EIO;
b31c50a7 310 }
f31e50a8 311 return status;
6ac7b687
SP		 312}
313
314/* Notify MCC requests and wait for completion */
b31c50a7 315static int be_mcc_notify_wait(struct be_adapter *adapter)
6ac7b687 316{
652bf646
PR		 317 int status;
318 struct be_mcc_wrb *wrb;
319 struct be_mcc_obj *mcc_obj = &adapter->mcc_obj;
320 u16 index = mcc_obj->q.head;
321 struct be_cmd_resp_hdr *resp;
322
323 index_dec(&index, mcc_obj->q.len);
324 wrb = queue_index_node(&mcc_obj->q, index);
325
326 resp = be_decode_resp_hdr(wrb->tag0, wrb->tag1);
327
8788fdc2 328 be_mcc_notify(adapter);
652bf646
PR		 329
330 status = be_mcc_wait_compl(adapter);
331 if (status == -EIO)
332 goto out;
333
334 status = resp->status;
335out:
336 return status;
6ac7b687
SP		 337}
338
5f0b849e 339static int be_mbox_db_ready_wait(struct be_adapter *adapter, void __iomem *db)
6b7c5b94 340{
f25b03a7 341 int msecs = 0;
6b7c5b94
SP		 342 u32 ready;
343
344 do {
6589ade0
SP		 345 if (be_error(adapter))
346 return -EIO;
347
cf588477 348 ready = ioread32(db);
434b3648 349 if (ready == 0xffffffff)
cf588477 350 return -1;
cf588477
SP		 351
352 ready &= MPU_MAILBOX_DB_RDY_MASK;
6b7c5b94
SP		 353 if (ready)
354 break;
355
f25b03a7 356 if (msecs > 4000) {
6589ade0
SP		 357 dev_err(&adapter->pdev->dev, "FW not responding\n");
358 adapter->fw_timeout = true;
f67ef7ba 359 be_detect_error(adapter);
6b7c5b94
SP		 360 return -1;
361 }
362
1dbf53a2 363 msleep(1);
f25b03a7 364 msecs++;
6b7c5b94
SP		 365 } while (true);
366
367 return 0;
368}
369
370/*
371 * Insert the mailbox address into the doorbell in two steps
5fb379ee 372 * Polls on the mbox doorbell till a command completion (or a timeout) occurs
6b7c5b94 373 */
b31c50a7 374static int be_mbox_notify_wait(struct be_adapter *adapter)
6b7c5b94
SP		 375{
376 int status;
6b7c5b94 377 u32 val = 0;
8788fdc2
SP		 378 void __iomem *db = adapter->db + MPU_MAILBOX_DB_OFFSET;
379 struct be_dma_mem *mbox_mem = &adapter->mbox_mem;
6b7c5b94 380 struct be_mcc_mailbox *mbox = mbox_mem->va;
efd2e40a 381 struct be_mcc_compl *compl = &mbox->compl;
6b7c5b94 382
cf588477
SP		 383 /* wait for ready to be set */
384 status = be_mbox_db_ready_wait(adapter, db);
385 if (status != 0)
386 return status;
387
6b7c5b94
SP		 388 val |= MPU_MAILBOX_DB_HI_MASK;
389 /* at bits 2 - 31 place mbox dma addr msb bits 34 - 63 */
390 val |= (upper_32_bits(mbox_mem->dma) >> 2) << 2;
391 iowrite32(val, db);
392
393 /* wait for ready to be set */
5f0b849e 394 status = be_mbox_db_ready_wait(adapter, db);
6b7c5b94
SP		 395 if (status != 0)
396 return status;
397
398 val = 0;
6b7c5b94
SP		 399 /* at bits 2 - 31 place mbox dma addr lsb bits 4 - 33 */
400 val |= (u32)(mbox_mem->dma >> 4) << 2;
401 iowrite32(val, db);
402
5f0b849e 403 status = be_mbox_db_ready_wait(adapter, db);
6b7c5b94
SP		 404 if (status != 0)
405 return status;
406
5fb379ee 407 /* A cq entry has been made now */
efd2e40a
SP		 408 if (be_mcc_compl_is_new(compl)) {
409 status = be_mcc_compl_process(adapter, &mbox->compl);
410 be_mcc_compl_use(compl);
5fb379ee
SP		 411 if (status)
412 return status;
413 } else {
5f0b849e 414 dev_err(&adapter->pdev->dev, "invalid mailbox completion\n");
6b7c5b94
SP		 415 return -1;
416 }
5fb379ee 417 return 0;
6b7c5b94
SP		 418}
419
8788fdc2 420static int be_POST_stage_get(struct be_adapter *adapter, u16 *stage)
6b7c5b94 421{
fe6d2a38
SP		 422 u32 sem;
423
424 if (lancer_chip(adapter))
425 sem = ioread32(adapter->db + MPU_EP_SEMAPHORE_IF_TYPE2_OFFSET);
426 else
427 sem = ioread32(adapter->csr + MPU_EP_SEMAPHORE_OFFSET);
6b7c5b94
SP		 428
429 *stage = sem & EP_SEMAPHORE_POST_STAGE_MASK;
430 if ((sem >> EP_SEMAPHORE_POST_ERR_SHIFT) & EP_SEMAPHORE_POST_ERR_MASK)
431 return -1;
432 else
433 return 0;
434}
435
bf99e50d
PR		 436int lancer_wait_ready(struct be_adapter *adapter)
437{
438#define SLIPORT_READY_TIMEOUT 30
439 u32 sliport_status;
440 int status = 0, i;
441
442 for (i = 0; i < SLIPORT_READY_TIMEOUT; i++) {
443 sliport_status = ioread32(adapter->db + SLIPORT_STATUS_OFFSET);
444 if (sliport_status & SLIPORT_STATUS_RDY_MASK)
445 break;
446
447 msleep(1000);
448 }
449
450 if (i == SLIPORT_READY_TIMEOUT)
451 status = -1;
452
453 return status;
454}
455
456int lancer_test_and_set_rdy_state(struct be_adapter *adapter)
457{
458 int status;
459 u32 sliport_status, err, reset_needed;
460 status = lancer_wait_ready(adapter);
461 if (!status) {
462 sliport_status = ioread32(adapter->db + SLIPORT_STATUS_OFFSET);
463 err = sliport_status & SLIPORT_STATUS_ERR_MASK;
464 reset_needed = sliport_status & SLIPORT_STATUS_RN_MASK;
465 if (err && reset_needed) {
466 iowrite32(SLI_PORT_CONTROL_IP_MASK,
467 adapter->db + SLIPORT_CONTROL_OFFSET);
468
469 /* check adapter has corrected the error */
470 status = lancer_wait_ready(adapter);
471 sliport_status = ioread32(adapter->db +
472 SLIPORT_STATUS_OFFSET);
473 sliport_status &= (SLIPORT_STATUS_ERR_MASK |
474 SLIPORT_STATUS_RN_MASK);
475 if (status || sliport_status)
476 status = -1;
477 } else if (err || reset_needed) {
478 status = -1;
479 }
480 }
481 return status;
482}
483
484int be_fw_wait_ready(struct be_adapter *adapter)
6b7c5b94 485{
43a04fdc
SP		 486 u16 stage;
487 int status, timeout = 0;
6ed35eea 488 struct device *dev = &adapter->pdev->dev;
6b7c5b94 489
bf99e50d
PR		 490 if (lancer_chip(adapter)) {
491 status = lancer_wait_ready(adapter);
492 return status;
493 }
494
43a04fdc
SP		 495 do {
496 status = be_POST_stage_get(adapter, &stage);
497 if (status) {
6ed35eea 498 dev_err(dev, "POST error; stage=0x%x\n", stage);
43a04fdc
SP		 499 return -1;
500 } else if (stage != POST_STAGE_ARMFW_RDY) {
6ed35eea
SP		 501 if (msleep_interruptible(2000)) {
502 dev_err(dev, "Waiting for POST aborted\n");
503 return -EINTR;
504 }
43a04fdc
SP		 505 timeout += 2;
506 } else {
507 return 0;
508 }
3ab81b5f 509 } while (timeout < 60);
6b7c5b94 510
6ed35eea 511 dev_err(dev, "POST timeout; stage=0x%x\n", stage);
43a04fdc 512 return -1;
6b7c5b94
SP		 513}
514
6b7c5b94
SP		 515
516static inline struct be_sge *nonembedded_sgl(struct be_mcc_wrb *wrb)
517{
518 return &wrb->payload.sgl[0];
519}
520
6b7c5b94
SP		 521
522/* Don't touch the hdr after it's prepared */
106df1e3
SK		 523/* mem will be NULL for embedded commands */
524static void be_wrb_cmd_hdr_prepare(struct be_cmd_req_hdr *req_hdr,
525 u8 subsystem, u8 opcode, int cmd_len,
526 struct be_mcc_wrb *wrb, struct be_dma_mem *mem)
6b7c5b94 527{
106df1e3 528 struct be_sge *sge;
652bf646
PR		 529 unsigned long addr = (unsigned long)req_hdr;
530 u64 req_addr = addr;
106df1e3 531
6b7c5b94
SP		 532 req_hdr->opcode = opcode;
533 req_hdr->subsystem = subsystem;
534 req_hdr->request_length = cpu_to_le32(cmd_len - sizeof(*req_hdr));
07793d33 535 req_hdr->version = 0;
106df1e3 536
652bf646
PR		 537 wrb->tag0 = req_addr & 0xFFFFFFFF;
538 wrb->tag1 = upper_32_bits(req_addr);
539
106df1e3
SK		 540 wrb->payload_length = cmd_len;
541 if (mem) {
542 wrb->embedded |= (1 & MCC_WRB_SGE_CNT_MASK) <<
543 MCC_WRB_SGE_CNT_SHIFT;
544 sge = nonembedded_sgl(wrb);
545 sge->pa_hi = cpu_to_le32(upper_32_bits(mem->dma));
546 sge->pa_lo = cpu_to_le32(mem->dma & 0xFFFFFFFF);
547 sge->len = cpu_to_le32(mem->size);
548 } else
549 wrb->embedded |= MCC_WRB_EMBEDDED_MASK;
550 be_dws_cpu_to_le(wrb, 8);
6b7c5b94
SP		 551}
552
553static void be_cmd_page_addrs_prepare(struct phys_addr *pages, u32 max_pages,
554 struct be_dma_mem *mem)
555{
556 int i, buf_pages = min(PAGES_4K_SPANNED(mem->va, mem->size), max_pages);
557 u64 dma = (u64)mem->dma;
558
559 for (i = 0; i < buf_pages; i++) {
560 pages[i].lo = cpu_to_le32(dma & 0xFFFFFFFF);
561 pages[i].hi = cpu_to_le32(upper_32_bits(dma));
562 dma += PAGE_SIZE_4K;
563 }
564}
565
566/* Converts interrupt delay in microseconds to multiplier value */
567static u32 eq_delay_to_mult(u32 usec_delay)
568{
569#define MAX_INTR_RATE 651042
570 const u32 round = 10;
571 u32 multiplier;
572
573 if (usec_delay == 0)
574 multiplier = 0;
575 else {
576 u32 interrupt_rate = 1000000 / usec_delay;
577 /* Max delay, corresponding to the lowest interrupt rate */
578 if (interrupt_rate == 0)
579 multiplier = 1023;
580 else {
581 multiplier = (MAX_INTR_RATE - interrupt_rate) * round;
582 multiplier /= interrupt_rate;
583 /* Round the multiplier to the closest value.*/
584 multiplier = (multiplier + round/2) / round;
585 multiplier = min(multiplier, (u32)1023);
586 }
587 }
588 return multiplier;
589}
590
b31c50a7 591static inline struct be_mcc_wrb *wrb_from_mbox(struct be_adapter *adapter)
6b7c5b94 592{
b31c50a7
SP		 593 struct be_dma_mem *mbox_mem = &adapter->mbox_mem;
594 struct be_mcc_wrb *wrb
595 = &((struct be_mcc_mailbox *)(mbox_mem->va))->wrb;
596 memset(wrb, 0, sizeof(*wrb));
597 return wrb;
6b7c5b94
SP		 598}
599
b31c50a7 600static struct be_mcc_wrb *wrb_from_mccq(struct be_adapter *adapter)
5fb379ee 601{
b31c50a7
SP		 602 struct be_queue_info *mccq = &adapter->mcc_obj.q;
603 struct be_mcc_wrb *wrb;
604
713d0394
SP		 605 if (atomic_read(&mccq->used) >= mccq->len) {
606 dev_err(&adapter->pdev->dev, "Out of MCCQ wrbs\n");
607 return NULL;
608 }
609
b31c50a7
SP		 610 wrb = queue_head_node(mccq);
611 queue_head_inc(mccq);
612 atomic_inc(&mccq->used);
613 memset(wrb, 0, sizeof(*wrb));
5fb379ee
SP		 614 return wrb;
615}
616
2243e2e9
SP		 617/* Tell fw we're about to start firing cmds by writing a
618 * special pattern across the wrb hdr; uses mbox
619 */
620int be_cmd_fw_init(struct be_adapter *adapter)
621{
622 u8 *wrb;
623 int status;
624
bf99e50d
PR		 625 if (lancer_chip(adapter))
626 return 0;
627
2984961c
IV		 628 if (mutex_lock_interruptible(&adapter->mbox_lock))
629 return -1;
2243e2e9
SP		 630
631 wrb = (u8 *)wrb_from_mbox(adapter);
359a972f
SP		 632 *wrb++ = 0xFF;
633 *wrb++ = 0x12;
634 *wrb++ = 0x34;
635 *wrb++ = 0xFF;
636 *wrb++ = 0xFF;
637 *wrb++ = 0x56;
638 *wrb++ = 0x78;
639 *wrb = 0xFF;
2243e2e9
SP		 640
641 status = be_mbox_notify_wait(adapter);
642
2984961c 643 mutex_unlock(&adapter->mbox_lock);
2243e2e9
SP		 644 return status;
645}
646
647/* Tell fw we're done with firing cmds by writing a
648 * special pattern across the wrb hdr; uses mbox
649 */
650int be_cmd_fw_clean(struct be_adapter *adapter)
651{
652 u8 *wrb;
653 int status;
654
bf99e50d
PR		 655 if (lancer_chip(adapter))
656 return 0;
657
2984961c
IV		 658 if (mutex_lock_interruptible(&adapter->mbox_lock))
659 return -1;
2243e2e9
SP		 660
661 wrb = (u8 *)wrb_from_mbox(adapter);
662 *wrb++ = 0xFF;
663 *wrb++ = 0xAA;
664 *wrb++ = 0xBB;
665 *wrb++ = 0xFF;
666 *wrb++ = 0xFF;
667 *wrb++ = 0xCC;
668 *wrb++ = 0xDD;
669 *wrb = 0xFF;
670
671 status = be_mbox_notify_wait(adapter);
672
2984961c 673 mutex_unlock(&adapter->mbox_lock);
2243e2e9
SP		 674 return status;
675}
bf99e50d 676
8788fdc2 677int be_cmd_eq_create(struct be_adapter *adapter,
6b7c5b94
SP		 678 struct be_queue_info *eq, int eq_delay)
679{
b31c50a7
SP		 680 struct be_mcc_wrb *wrb;
681 struct be_cmd_req_eq_create *req;
6b7c5b94
SP		 682 struct be_dma_mem *q_mem = &eq->dma_mem;
683 int status;
684
2984961c
IV		 685 if (mutex_lock_interruptible(&adapter->mbox_lock))
686 return -1;
b31c50a7
SP		 687
688 wrb = wrb_from_mbox(adapter);
689 req = embedded_payload(wrb);
6b7c5b94 690
106df1e3
SK		 691 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
692 OPCODE_COMMON_EQ_CREATE, sizeof(*req), wrb, NULL);
6b7c5b94
SP		 693
694 req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
695
6b7c5b94
SP		 696 AMAP_SET_BITS(struct amap_eq_context, valid, req->context, 1);
697 /* 4byte eqe*/
698 AMAP_SET_BITS(struct amap_eq_context, size, req->context, 0);
699 AMAP_SET_BITS(struct amap_eq_context, count, req->context,
700 __ilog2_u32(eq->len/256));
701 AMAP_SET_BITS(struct amap_eq_context, delaymult, req->context,
702 eq_delay_to_mult(eq_delay));
703 be_dws_cpu_to_le(req->context, sizeof(req->context));
704
705 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
706
b31c50a7 707 status = be_mbox_notify_wait(adapter);
6b7c5b94 708 if (!status) {
b31c50a7 709 struct be_cmd_resp_eq_create *resp = embedded_payload(wrb);
6b7c5b94
SP		 710 eq->id = le16_to_cpu(resp->eq_id);
711 eq->created = true;
712 }
b31c50a7 713
2984961c 714 mutex_unlock(&adapter->mbox_lock);
6b7c5b94
SP		 715 return status;
716}
717
f9449ab7 718/* Use MCC */
8788fdc2 719int be_cmd_mac_addr_query(struct be_adapter *adapter, u8 *mac_addr,
590c391d 720 u8 type, bool permanent, u32 if_handle, u32 pmac_id)
6b7c5b94 721{
b31c50a7
SP		 722 struct be_mcc_wrb *wrb;
723 struct be_cmd_req_mac_query *req;
6b7c5b94
SP		 724 int status;
725
f9449ab7 726 spin_lock_bh(&adapter->mcc_lock);
b31c50a7 727
f9449ab7
SP		 728 wrb = wrb_from_mccq(adapter);
729 if (!wrb) {
730 status = -EBUSY;
731 goto err;
732 }
b31c50a7 733 req = embedded_payload(wrb);
6b7c5b94 734
106df1e3
SK		 735 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
736 OPCODE_COMMON_NTWK_MAC_QUERY, sizeof(*req), wrb, NULL);
6b7c5b94
SP		 737 req->type = type;
738 if (permanent) {
739 req->permanent = 1;
740 } else {
b31c50a7 741 req->if_id = cpu_to_le16((u16) if_handle);
590c391d 742 req->pmac_id = cpu_to_le32(pmac_id);
6b7c5b94
SP		 743 req->permanent = 0;
744 }
745
f9449ab7 746 status = be_mcc_notify_wait(adapter);
b31c50a7
SP		 747 if (!status) {
748 struct be_cmd_resp_mac_query *resp = embedded_payload(wrb);
6b7c5b94 749 memcpy(mac_addr, resp->mac.addr, ETH_ALEN);
b31c50a7 750 }
6b7c5b94 751
f9449ab7
SP		 752err:
753 spin_unlock_bh(&adapter->mcc_lock);
6b7c5b94
SP		 754 return status;
755}
756
b31c50a7 757/* Uses synchronous MCCQ */
8788fdc2 758int be_cmd_pmac_add(struct be_adapter *adapter, u8 *mac_addr,
f8617e08 759 u32 if_id, u32 *pmac_id, u32 domain)
6b7c5b94 760{
b31c50a7
SP		 761 struct be_mcc_wrb *wrb;
762 struct be_cmd_req_pmac_add *req;
6b7c5b94
SP		 763 int status;
764
b31c50a7
SP		 765 spin_lock_bh(&adapter->mcc_lock);
766
767 wrb = wrb_from_mccq(adapter);
713d0394
SP		 768 if (!wrb) {
769 status = -EBUSY;
770 goto err;
771 }
b31c50a7 772 req = embedded_payload(wrb);
6b7c5b94 773
106df1e3
SK		 774 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
775 OPCODE_COMMON_NTWK_PMAC_ADD, sizeof(*req), wrb, NULL);
6b7c5b94 776
f8617e08 777 req->hdr.domain = domain;
6b7c5b94
SP		 778 req->if_id = cpu_to_le32(if_id);
779 memcpy(req->mac_address, mac_addr, ETH_ALEN);
780
b31c50a7 781 status = be_mcc_notify_wait(adapter);
6b7c5b94
SP		 782 if (!status) {
783 struct be_cmd_resp_pmac_add *resp = embedded_payload(wrb);
784 *pmac_id = le32_to_cpu(resp->pmac_id);
785 }
786
713d0394 787err:
b31c50a7 788 spin_unlock_bh(&adapter->mcc_lock);
e3a7ae2c
SK		 789
790 if (status == MCC_STATUS_UNAUTHORIZED_REQUEST)
791 status = -EPERM;
792
6b7c5b94
SP		 793 return status;
794}
795
b31c50a7 796/* Uses synchronous MCCQ */
30128031 797int be_cmd_pmac_del(struct be_adapter *adapter, u32 if_id, int pmac_id, u32 dom)
6b7c5b94 798{
b31c50a7
SP		 799 struct be_mcc_wrb *wrb;
800 struct be_cmd_req_pmac_del *req;
6b7c5b94
SP		 801 int status;
802
30128031
SP		 803 if (pmac_id == -1)
804 return 0;
805
b31c50a7
SP		 806 spin_lock_bh(&adapter->mcc_lock);
807
808 wrb = wrb_from_mccq(adapter);
713d0394
SP		 809 if (!wrb) {
810 status = -EBUSY;
811 goto err;
812 }
b31c50a7 813 req = embedded_payload(wrb);
6b7c5b94 814
106df1e3
SK		 815 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
816 OPCODE_COMMON_NTWK_PMAC_DEL, sizeof(*req), wrb, NULL);
6b7c5b94 817
f8617e08 818 req->hdr.domain = dom;
6b7c5b94
SP		 819 req->if_id = cpu_to_le32(if_id);
820 req->pmac_id = cpu_to_le32(pmac_id);
821
b31c50a7
SP		 822 status = be_mcc_notify_wait(adapter);
823
713d0394 824err:
b31c50a7 825 spin_unlock_bh(&adapter->mcc_lock);
6b7c5b94
SP		 826 return status;
827}
828
b31c50a7 829/* Uses Mbox */
10ef9ab4
SP		 830int be_cmd_cq_create(struct be_adapter *adapter, struct be_queue_info *cq,
831 struct be_queue_info *eq, bool no_delay, int coalesce_wm)
6b7c5b94 832{
b31c50a7
SP		 833 struct be_mcc_wrb *wrb;
834 struct be_cmd_req_cq_create *req;
6b7c5b94 835 struct be_dma_mem *q_mem = &cq->dma_mem;
b31c50a7 836 void *ctxt;
6b7c5b94
SP		 837 int status;
838
2984961c
IV		 839 if (mutex_lock_interruptible(&adapter->mbox_lock))
840 return -1;
b31c50a7
SP		 841
842 wrb = wrb_from_mbox(adapter);
843 req = embedded_payload(wrb);
844 ctxt = &req->context;
6b7c5b94 845
106df1e3
SK		 846 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
847 OPCODE_COMMON_CQ_CREATE, sizeof(*req), wrb, NULL);
6b7c5b94
SP		 848
849 req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
fe6d2a38 850 if (lancer_chip(adapter)) {
8b7756ca 851 req->hdr.version = 2;
fe6d2a38 852 req->page_size = 1; /* 1 for 4K */
fe6d2a38
SP		 853 AMAP_SET_BITS(struct amap_cq_context_lancer, nodelay, ctxt,
854 no_delay);
855 AMAP_SET_BITS(struct amap_cq_context_lancer, count, ctxt,
856 __ilog2_u32(cq->len/256));
857 AMAP_SET_BITS(struct amap_cq_context_lancer, valid, ctxt, 1);
858 AMAP_SET_BITS(struct amap_cq_context_lancer, eventable,
859 ctxt, 1);
860 AMAP_SET_BITS(struct amap_cq_context_lancer, eqid,
861 ctxt, eq->id);
fe6d2a38
SP		 862 } else {
863 AMAP_SET_BITS(struct amap_cq_context_be, coalescwm, ctxt,
864 coalesce_wm);
865 AMAP_SET_BITS(struct amap_cq_context_be, nodelay,
866 ctxt, no_delay);
867 AMAP_SET_BITS(struct amap_cq_context_be, count, ctxt,
868 __ilog2_u32(cq->len/256));
869 AMAP_SET_BITS(struct amap_cq_context_be, valid, ctxt, 1);
fe6d2a38
SP		 870 AMAP_SET_BITS(struct amap_cq_context_be, eventable, ctxt, 1);
871 AMAP_SET_BITS(struct amap_cq_context_be, eqid, ctxt, eq->id);
fe6d2a38 872 }
6b7c5b94 873
6b7c5b94
SP		 874 be_dws_cpu_to_le(ctxt, sizeof(req->context));
875
876 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
877
b31c50a7 878 status = be_mbox_notify_wait(adapter);
6b7c5b94 879 if (!status) {
b31c50a7 880 struct be_cmd_resp_cq_create *resp = embedded_payload(wrb);
6b7c5b94
SP		 881 cq->id = le16_to_cpu(resp->cq_id);
882 cq->created = true;
883 }
b31c50a7 884
2984961c 885 mutex_unlock(&adapter->mbox_lock);
5fb379ee
SP		 886
887 return status;
888}
889
890static u32 be_encoded_q_len(int q_len)
891{
892 u32 len_encoded = fls(q_len); /* log2(len) + 1 */
893 if (len_encoded == 16)
894 len_encoded = 0;
895 return len_encoded;
896}
897
34b1ef04 898int be_cmd_mccq_ext_create(struct be_adapter *adapter,
5fb379ee
SP		 899 struct be_queue_info *mccq,
900 struct be_queue_info *cq)
901{
b31c50a7 902 struct be_mcc_wrb *wrb;
34b1ef04 903 struct be_cmd_req_mcc_ext_create *req;
5fb379ee 904 struct be_dma_mem *q_mem = &mccq->dma_mem;
b31c50a7 905 void *ctxt;
5fb379ee
SP		 906 int status;
907
2984961c
IV		 908 if (mutex_lock_interruptible(&adapter->mbox_lock))
909 return -1;
b31c50a7
SP		 910
911 wrb = wrb_from_mbox(adapter);
912 req = embedded_payload(wrb);
913 ctxt = &req->context;
5fb379ee 914
106df1e3
SK		 915 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
916 OPCODE_COMMON_MCC_CREATE_EXT, sizeof(*req), wrb, NULL);
5fb379ee 917
d4a2ac3e 918 req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
fe6d2a38
SP		 919 if (lancer_chip(adapter)) {
920 req->hdr.version = 1;
921 req->cq_id = cpu_to_le16(cq->id);
922
923 AMAP_SET_BITS(struct amap_mcc_context_lancer, ring_size, ctxt,
924 be_encoded_q_len(mccq->len));
925 AMAP_SET_BITS(struct amap_mcc_context_lancer, valid, ctxt, 1);
926 AMAP_SET_BITS(struct amap_mcc_context_lancer, async_cq_id,
927 ctxt, cq->id);
928 AMAP_SET_BITS(struct amap_mcc_context_lancer, async_cq_valid,
929 ctxt, 1);
930
931 } else {
932 AMAP_SET_BITS(struct amap_mcc_context_be, valid, ctxt, 1);
933 AMAP_SET_BITS(struct amap_mcc_context_be, ring_size, ctxt,
934 be_encoded_q_len(mccq->len));
935 AMAP_SET_BITS(struct amap_mcc_context_be, cq_id, ctxt, cq->id);
936 }
5fb379ee 937
cc4ce020 938 /* Subscribe to Link State and Group 5 Events(bits 1 and 5 set) */
fe6d2a38 939 req->async_event_bitmap[0] = cpu_to_le32(0x00000022);
5fb379ee
SP		 940 be_dws_cpu_to_le(ctxt, sizeof(req->context));
941
942 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
943
b31c50a7 944 status = be_mbox_notify_wait(adapter);
5fb379ee
SP		 945 if (!status) {
946 struct be_cmd_resp_mcc_create *resp = embedded_payload(wrb);
947 mccq->id = le16_to_cpu(resp->id);
948 mccq->created = true;
949 }
2984961c 950 mutex_unlock(&adapter->mbox_lock);
6b7c5b94
SP		 951
952 return status;
953}
954
34b1ef04
SK		 955int be_cmd_mccq_org_create(struct be_adapter *adapter,
956 struct be_queue_info *mccq,
957 struct be_queue_info *cq)
958{
959 struct be_mcc_wrb *wrb;
960 struct be_cmd_req_mcc_create *req;
961 struct be_dma_mem *q_mem = &mccq->dma_mem;
962 void *ctxt;
963 int status;
964
965 if (mutex_lock_interruptible(&adapter->mbox_lock))
966 return -1;
967
968 wrb = wrb_from_mbox(adapter);
969 req = embedded_payload(wrb);
970 ctxt = &req->context;
971
106df1e3
SK		 972 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
973 OPCODE_COMMON_MCC_CREATE, sizeof(*req), wrb, NULL);
34b1ef04
SK		 974
975 req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
976
977 AMAP_SET_BITS(struct amap_mcc_context_be, valid, ctxt, 1);
978 AMAP_SET_BITS(struct amap_mcc_context_be, ring_size, ctxt,
979 be_encoded_q_len(mccq->len));
980 AMAP_SET_BITS(struct amap_mcc_context_be, cq_id, ctxt, cq->id);
981
982 be_dws_cpu_to_le(ctxt, sizeof(req->context));
983
984 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
985
986 status = be_mbox_notify_wait(adapter);
987 if (!status) {
988 struct be_cmd_resp_mcc_create *resp = embedded_payload(wrb);
989 mccq->id = le16_to_cpu(resp->id);
990 mccq->created = true;
991 }
992
993 mutex_unlock(&adapter->mbox_lock);
994 return status;
995}
996
997int be_cmd_mccq_create(struct be_adapter *adapter,
998 struct be_queue_info *mccq,
999 struct be_queue_info *cq)
1000{
1001 int status;
1002
1003 status = be_cmd_mccq_ext_create(adapter, mccq, cq);
1004 if (status && !lancer_chip(adapter)) {
1005 dev_warn(&adapter->pdev->dev, "Upgrade to F/W ver 2.102.235.0 "
1006 "or newer to avoid conflicting priorities between NIC "
1007 "and FCoE traffic");
1008 status = be_cmd_mccq_org_create(adapter, mccq, cq);
1009 }
1010 return status;
1011}
1012
8788fdc2 1013int be_cmd_txq_create(struct be_adapter *adapter,
6b7c5b94
SP		 1014 struct be_queue_info *txq,
1015 struct be_queue_info *cq)
1016{
b31c50a7
SP		 1017 struct be_mcc_wrb *wrb;
1018 struct be_cmd_req_eth_tx_create *req;
6b7c5b94 1019 struct be_dma_mem *q_mem = &txq->dma_mem;
b31c50a7 1020 void *ctxt;
6b7c5b94 1021 int status;
6b7c5b94 1022
293c4a7d
PR		 1023 spin_lock_bh(&adapter->mcc_lock);
1024
1025 wrb = wrb_from_mccq(adapter);
1026 if (!wrb) {
1027 status = -EBUSY;
1028 goto err;
1029 }
b31c50a7 1030
b31c50a7
SP		 1031 req = embedded_payload(wrb);
1032 ctxt = &req->context;
6b7c5b94 1033
106df1e3
SK		 1034 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1035 OPCODE_ETH_TX_CREATE, sizeof(*req), wrb, NULL);
6b7c5b94 1036
8b7756ca
PR		 1037 if (lancer_chip(adapter)) {
1038 req->hdr.version = 1;
1039 AMAP_SET_BITS(struct amap_tx_context, if_id, ctxt,
1040 adapter->if_handle);
1041 }
1042
6b7c5b94
SP		 1043 req->num_pages = PAGES_4K_SPANNED(q_mem->va, q_mem->size);
1044 req->ulp_num = BE_ULP1_NUM;
1045 req->type = BE_ETH_TX_RING_TYPE_STANDARD;
1046
b31c50a7
SP		 1047 AMAP_SET_BITS(struct amap_tx_context, tx_ring_size, ctxt,
1048 be_encoded_q_len(txq->len));
6b7c5b94
SP		 1049 AMAP_SET_BITS(struct amap_tx_context, ctx_valid, ctxt, 1);
1050 AMAP_SET_BITS(struct amap_tx_context, cq_id_send, ctxt, cq->id);
1051
1052 be_dws_cpu_to_le(ctxt, sizeof(req->context));
1053
1054 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
1055
293c4a7d 1056 status = be_mcc_notify_wait(adapter);
6b7c5b94
SP		 1057 if (!status) {
1058 struct be_cmd_resp_eth_tx_create *resp = embedded_payload(wrb);
1059 txq->id = le16_to_cpu(resp->cid);
1060 txq->created = true;
1061 }
b31c50a7 1062
293c4a7d
PR		 1063err:
1064 spin_unlock_bh(&adapter->mcc_lock);
6b7c5b94
SP		 1065
1066 return status;
1067}
1068
482c9e79 1069/* Uses MCC */
8788fdc2 1070int be_cmd_rxq_create(struct be_adapter *adapter,
6b7c5b94 1071 struct be_queue_info *rxq, u16 cq_id, u16 frag_size,
10ef9ab4 1072 u32 if_id, u32 rss, u8 *rss_id)
6b7c5b94 1073{
b31c50a7
SP		 1074 struct be_mcc_wrb *wrb;
1075 struct be_cmd_req_eth_rx_create *req;
6b7c5b94
SP		 1076 struct be_dma_mem *q_mem = &rxq->dma_mem;
1077 int status;
1078
482c9e79 1079 spin_lock_bh(&adapter->mcc_lock);
b31c50a7 1080
482c9e79
SP		 1081 wrb = wrb_from_mccq(adapter);
1082 if (!wrb) {
1083 status = -EBUSY;
1084 goto err;
1085 }
b31c50a7 1086 req = embedded_payload(wrb);
6b7c5b94 1087
106df1e3
SK		 1088 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1089 OPCODE_ETH_RX_CREATE, sizeof(*req), wrb, NULL);
6b7c5b94
SP		 1090
1091 req->cq_id = cpu_to_le16(cq_id);
1092 req->frag_size = fls(frag_size) - 1;
1093 req->num_pages = 2;
1094 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
1095 req->interface_id = cpu_to_le32(if_id);
10ef9ab4 1096 req->max_frame_size = cpu_to_le16(BE_MAX_JUMBO_FRAME_SIZE);
6b7c5b94
SP		 1097 req->rss_queue = cpu_to_le32(rss);
1098
482c9e79 1099 status = be_mcc_notify_wait(adapter);
6b7c5b94
SP		 1100 if (!status) {
1101 struct be_cmd_resp_eth_rx_create *resp = embedded_payload(wrb);
1102 rxq->id = le16_to_cpu(resp->id);
1103 rxq->created = true;
3abcdeda 1104 *rss_id = resp->rss_id;
6b7c5b94 1105 }
b31c50a7 1106
482c9e79
SP		 1107err:
1108 spin_unlock_bh(&adapter->mcc_lock);
6b7c5b94
SP		 1109 return status;
1110}
1111
b31c50a7
SP		 1112/* Generic destroyer function for all types of queues
1113 * Uses Mbox
1114 */
8788fdc2 1115int be_cmd_q_destroy(struct be_adapter *adapter, struct be_queue_info *q,
6b7c5b94
SP		 1116 int queue_type)
1117{
b31c50a7
SP		 1118 struct be_mcc_wrb *wrb;
1119 struct be_cmd_req_q_destroy *req;
6b7c5b94
SP		 1120 u8 subsys = 0, opcode = 0;
1121 int status;
1122
2984961c
IV		 1123 if (mutex_lock_interruptible(&adapter->mbox_lock))
1124 return -1;
6b7c5b94 1125
b31c50a7
SP		 1126 wrb = wrb_from_mbox(adapter);
1127 req = embedded_payload(wrb);
1128
6b7c5b94
SP		 1129 switch (queue_type) {
1130 case QTYPE_EQ:
1131 subsys = CMD_SUBSYSTEM_COMMON;
1132 opcode = OPCODE_COMMON_EQ_DESTROY;
1133 break;
1134 case QTYPE_CQ:
1135 subsys = CMD_SUBSYSTEM_COMMON;
1136 opcode = OPCODE_COMMON_CQ_DESTROY;
1137 break;
1138 case QTYPE_TXQ:
1139 subsys = CMD_SUBSYSTEM_ETH;
1140 opcode = OPCODE_ETH_TX_DESTROY;
1141 break;
1142 case QTYPE_RXQ:
1143 subsys = CMD_SUBSYSTEM_ETH;
1144 opcode = OPCODE_ETH_RX_DESTROY;
1145 break;
5fb379ee
SP		 1146 case QTYPE_MCCQ:
1147 subsys = CMD_SUBSYSTEM_COMMON;
1148 opcode = OPCODE_COMMON_MCC_DESTROY;
1149 break;
6b7c5b94 1150 default:
5f0b849e 1151 BUG();
6b7c5b94 1152 }
d744b44e 1153
106df1e3
SK		 1154 be_wrb_cmd_hdr_prepare(&req->hdr, subsys, opcode, sizeof(*req), wrb,
1155 NULL);
6b7c5b94
SP		 1156 req->id = cpu_to_le16(q->id);
1157
b31c50a7 1158 status = be_mbox_notify_wait(adapter);
482c9e79
SP		 1159 if (!status)
1160 q->created = false;
5f0b849e 1161
2984961c 1162 mutex_unlock(&adapter->mbox_lock);
482c9e79
SP		 1163 return status;
1164}
6b7c5b94 1165
482c9e79
SP		 1166/* Uses MCC */
1167int be_cmd_rxq_destroy(struct be_adapter *adapter, struct be_queue_info *q)
1168{
1169 struct be_mcc_wrb *wrb;
1170 struct be_cmd_req_q_destroy *req;
1171 int status;
1172
1173 spin_lock_bh(&adapter->mcc_lock);
1174
1175 wrb = wrb_from_mccq(adapter);
1176 if (!wrb) {
1177 status = -EBUSY;
1178 goto err;
1179 }
1180 req = embedded_payload(wrb);
1181
106df1e3
SK		 1182 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1183 OPCODE_ETH_RX_DESTROY, sizeof(*req), wrb, NULL);
482c9e79
SP		 1184 req->id = cpu_to_le16(q->id);
1185
1186 status = be_mcc_notify_wait(adapter);
1187 if (!status)
1188 q->created = false;
1189
1190err:
1191 spin_unlock_bh(&adapter->mcc_lock);
6b7c5b94
SP		 1192 return status;
1193}
1194
b31c50a7 1195/* Create an rx filtering policy configuration on an i/f
f9449ab7 1196 * Uses MCCQ
b31c50a7 1197 */
73d540f2 1198int be_cmd_if_create(struct be_adapter *adapter, u32 cap_flags, u32 en_flags,
1578e777 1199 u32 *if_handle, u32 domain)
6b7c5b94 1200{
b31c50a7
SP		 1201 struct be_mcc_wrb *wrb;
1202 struct be_cmd_req_if_create *req;
6b7c5b94
SP		 1203 int status;
1204
f9449ab7 1205 spin_lock_bh(&adapter->mcc_lock);
b31c50a7 1206
f9449ab7
SP		 1207 wrb = wrb_from_mccq(adapter);
1208 if (!wrb) {
1209 status = -EBUSY;
1210 goto err;
1211 }
b31c50a7 1212 req = embedded_payload(wrb);
6b7c5b94 1213
106df1e3
SK		 1214 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1215 OPCODE_COMMON_NTWK_INTERFACE_CREATE, sizeof(*req), wrb, NULL);
ba343c77 1216 req->hdr.domain = domain;
73d540f2
SP		 1217 req->capability_flags = cpu_to_le32(cap_flags);
1218 req->enable_flags = cpu_to_le32(en_flags);
1578e777
PR		 1219
1220 req->pmac_invalid = true;
6b7c5b94 1221
f9449ab7 1222 status = be_mcc_notify_wait(adapter);
6b7c5b94
SP		 1223 if (!status) {
1224 struct be_cmd_resp_if_create *resp = embedded_payload(wrb);
1225 *if_handle = le32_to_cpu(resp->interface_id);
6b7c5b94
SP		 1226 }
1227
f9449ab7
SP		 1228err:
1229 spin_unlock_bh(&adapter->mcc_lock);
6b7c5b94
SP		 1230 return status;
1231}
1232
f9449ab7 1233/* Uses MCCQ */
30128031 1234int be_cmd_if_destroy(struct be_adapter *adapter, int interface_id, u32 domain)
6b7c5b94 1235{
b31c50a7
SP		 1236 struct be_mcc_wrb *wrb;
1237 struct be_cmd_req_if_destroy *req;
6b7c5b94
SP		 1238 int status;
1239
30128031 1240 if (interface_id == -1)
f9449ab7 1241 return 0;
b31c50a7 1242
f9449ab7
SP		 1243 spin_lock_bh(&adapter->mcc_lock);
1244
1245 wrb = wrb_from_mccq(adapter);
1246 if (!wrb) {
1247 status = -EBUSY;
1248 goto err;
1249 }
b31c50a7 1250 req = embedded_payload(wrb);
6b7c5b94 1251
106df1e3
SK		 1252 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1253 OPCODE_COMMON_NTWK_INTERFACE_DESTROY, sizeof(*req), wrb, NULL);
658681f7 1254 req->hdr.domain = domain;
6b7c5b94 1255 req->interface_id = cpu_to_le32(interface_id);
b31c50a7 1256
f9449ab7
SP		 1257 status = be_mcc_notify_wait(adapter);
1258err:
1259 spin_unlock_bh(&adapter->mcc_lock);
6b7c5b94
SP		 1260 return status;
1261}
1262
1263/* Get stats is a non embedded command: the request is not embedded inside
1264 * WRB but is a separate dma memory block
b31c50a7 1265 * Uses asynchronous MCC
6b7c5b94 1266 */
8788fdc2 1267int be_cmd_get_stats(struct be_adapter *adapter, struct be_dma_mem *nonemb_cmd)
6b7c5b94 1268{
b31c50a7 1269 struct be_mcc_wrb *wrb;
89a88ab8 1270 struct be_cmd_req_hdr *hdr;
713d0394 1271 int status = 0;
6b7c5b94 1272
b31c50a7 1273 spin_lock_bh(&adapter->mcc_lock);
6b7c5b94 1274
b31c50a7 1275 wrb = wrb_from_mccq(adapter);
713d0394
SP		 1276 if (!wrb) {
1277 status = -EBUSY;
1278 goto err;
1279 }
89a88ab8 1280 hdr = nonemb_cmd->va;
6b7c5b94 1281
106df1e3
SK		 1282 be_wrb_cmd_hdr_prepare(hdr, CMD_SUBSYSTEM_ETH,
1283 OPCODE_ETH_GET_STATISTICS, nonemb_cmd->size, wrb, nonemb_cmd);
89a88ab8
AK		 1284
1285 if (adapter->generation == BE_GEN3)
1286 hdr->version = 1;
1287
b31c50a7 1288 be_mcc_notify(adapter);
b2aebe6d 1289 adapter->stats_cmd_sent = true;
6b7c5b94 1290
713d0394 1291err:
b31c50a7 1292 spin_unlock_bh(&adapter->mcc_lock);
713d0394 1293 return status;
6b7c5b94
SP		 1294}
1295
005d5696
SX		 1296/* Lancer Stats */
1297int lancer_cmd_get_pport_stats(struct be_adapter *adapter,
1298 struct be_dma_mem *nonemb_cmd)
1299{
1300
1301 struct be_mcc_wrb *wrb;
1302 struct lancer_cmd_req_pport_stats *req;
005d5696
SX		 1303 int status = 0;
1304
1305 spin_lock_bh(&adapter->mcc_lock);
1306
1307 wrb = wrb_from_mccq(adapter);
1308 if (!wrb) {
1309 status = -EBUSY;
1310 goto err;
1311 }
1312 req = nonemb_cmd->va;
005d5696 1313
106df1e3
SK		 1314 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1315 OPCODE_ETH_GET_PPORT_STATS, nonemb_cmd->size, wrb,
1316 nonemb_cmd);
005d5696 1317
d51ebd33 1318 req->cmd_params.params.pport_num = cpu_to_le16(adapter->hba_port_num);
005d5696
SX		 1319 req->cmd_params.params.reset_stats = 0;
1320
005d5696
SX		 1321 be_mcc_notify(adapter);
1322 adapter->stats_cmd_sent = true;
1323
1324err:
1325 spin_unlock_bh(&adapter->mcc_lock);
1326 return status;
1327}
1328
b31c50a7 1329/* Uses synchronous mcc */
ea172a01 1330int be_cmd_link_status_query(struct be_adapter *adapter, u8 *mac_speed,
b236916a 1331 u16 *link_speed, u8 *link_status, u32 dom)
6b7c5b94 1332{
b31c50a7
SP		 1333 struct be_mcc_wrb *wrb;
1334 struct be_cmd_req_link_status *req;
6b7c5b94
SP		 1335 int status;
1336
b31c50a7
SP		 1337 spin_lock_bh(&adapter->mcc_lock);
1338
b236916a
AK		 1339 if (link_status)
1340 *link_status = LINK_DOWN;
1341
b31c50a7 1342 wrb = wrb_from_mccq(adapter);
713d0394
SP		 1343 if (!wrb) {
1344 status = -EBUSY;
1345 goto err;
1346 }
b31c50a7 1347 req = embedded_payload(wrb);
a8f447bd 1348
57cd80d4
PR		 1349 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1350 OPCODE_COMMON_NTWK_LINK_STATUS_QUERY, sizeof(*req), wrb, NULL);
1351
b236916a 1352 if (adapter->generation == BE_GEN3 || lancer_chip(adapter))
daad6167
PR		 1353 req->hdr.version = 1;
1354
57cd80d4 1355 req->hdr.domain = dom;
6b7c5b94 1356
b31c50a7 1357 status = be_mcc_notify_wait(adapter);
6b7c5b94
SP		 1358 if (!status) {
1359 struct be_cmd_resp_link_status *resp = embedded_payload(wrb);
0388f251 1360 if (resp->mac_speed != PHY_LINK_SPEED_ZERO) {
b236916a
AK		 1361 if (link_speed)
1362 *link_speed = le16_to_cpu(resp->link_speed);
f9449ab7
SP		 1363 if (mac_speed)
1364 *mac_speed = resp->mac_speed;
0388f251 1365 }
b236916a
AK		 1366 if (link_status)
1367 *link_status = resp->logical_link_status;
6b7c5b94
SP		 1368 }
1369
713d0394 1370err:
b31c50a7 1371 spin_unlock_bh(&adapter->mcc_lock);
6b7c5b94
SP		 1372 return status;
1373}
1374
609ff3bb
AK		 1375/* Uses synchronous mcc */
1376int be_cmd_get_die_temperature(struct be_adapter *adapter)
1377{
1378 struct be_mcc_wrb *wrb;
1379 struct be_cmd_req_get_cntl_addnl_attribs *req;
1380 int status;
1381
1382 spin_lock_bh(&adapter->mcc_lock);
1383
1384 wrb = wrb_from_mccq(adapter);
1385 if (!wrb) {
1386 status = -EBUSY;
1387 goto err;
1388 }
1389 req = embedded_payload(wrb);
1390
106df1e3
SK		 1391 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1392 OPCODE_COMMON_GET_CNTL_ADDITIONAL_ATTRIBUTES, sizeof(*req),
1393 wrb, NULL);
609ff3bb 1394
3de09455 1395 be_mcc_notify(adapter);
609ff3bb
AK		 1396
1397err:
1398 spin_unlock_bh(&adapter->mcc_lock);
1399 return status;
1400}
1401
311fddc7
SK		 1402/* Uses synchronous mcc */
1403int be_cmd_get_reg_len(struct be_adapter *adapter, u32 *log_size)
1404{
1405 struct be_mcc_wrb *wrb;
1406 struct be_cmd_req_get_fat *req;
1407 int status;
1408
1409 spin_lock_bh(&adapter->mcc_lock);
1410
1411 wrb = wrb_from_mccq(adapter);
1412 if (!wrb) {
1413 status = -EBUSY;
1414 goto err;
1415 }
1416 req = embedded_payload(wrb);
1417
106df1e3
SK		 1418 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1419 OPCODE_COMMON_MANAGE_FAT, sizeof(*req), wrb, NULL);
311fddc7
SK		 1420 req->fat_operation = cpu_to_le32(QUERY_FAT);
1421 status = be_mcc_notify_wait(adapter);
1422 if (!status) {
1423 struct be_cmd_resp_get_fat *resp = embedded_payload(wrb);
1424 if (log_size && resp->log_size)
fe2a70ee
SK		 1425 *log_size = le32_to_cpu(resp->log_size) -
1426 sizeof(u32);
311fddc7
SK		 1427 }
1428err:
1429 spin_unlock_bh(&adapter->mcc_lock);
1430 return status;
1431}
1432
1433void be_cmd_get_regs(struct be_adapter *adapter, u32 buf_len, void *buf)
1434{
1435 struct be_dma_mem get_fat_cmd;
1436 struct be_mcc_wrb *wrb;
1437 struct be_cmd_req_get_fat *req;
fe2a70ee
SK		 1438 u32 offset = 0, total_size, buf_size,
1439 log_offset = sizeof(u32), payload_len;
311fddc7
SK		 1440 int status;
1441
1442 if (buf_len == 0)
1443 return;
1444
1445 total_size = buf_len;
1446
fe2a70ee
SK		 1447 get_fat_cmd.size = sizeof(struct be_cmd_req_get_fat) + 60*1024;
1448 get_fat_cmd.va = pci_alloc_consistent(adapter->pdev,
1449 get_fat_cmd.size,
1450 &get_fat_cmd.dma);
1451 if (!get_fat_cmd.va) {
1452 status = -ENOMEM;
1453 dev_err(&adapter->pdev->dev,
1454 "Memory allocation failure while retrieving FAT data\n");
1455 return;
1456 }
1457
311fddc7
SK		 1458 spin_lock_bh(&adapter->mcc_lock);
1459
311fddc7
SK		 1460 while (total_size) {
1461 buf_size = min(total_size, (u32)60*1024);
1462 total_size -= buf_size;
1463
fe2a70ee
SK		 1464 wrb = wrb_from_mccq(adapter);
1465 if (!wrb) {
1466 status = -EBUSY;
311fddc7
SK		 1467 goto err;
1468 }
1469 req = get_fat_cmd.va;
311fddc7 1470
fe2a70ee 1471 payload_len = sizeof(struct be_cmd_req_get_fat) + buf_size;
106df1e3
SK		 1472 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1473 OPCODE_COMMON_MANAGE_FAT, payload_len, wrb,
1474 &get_fat_cmd);
311fddc7
SK		 1475
1476 req->fat_operation = cpu_to_le32(RETRIEVE_FAT);
1477 req->read_log_offset = cpu_to_le32(log_offset);
1478 req->read_log_length = cpu_to_le32(buf_size);
1479 req->data_buffer_size = cpu_to_le32(buf_size);
1480
1481 status = be_mcc_notify_wait(adapter);
1482 if (!status) {
1483 struct be_cmd_resp_get_fat *resp = get_fat_cmd.va;
1484 memcpy(buf + offset,
1485 resp->data_buffer,
92aa9214 1486 le32_to_cpu(resp->read_log_length));
fe2a70ee 1487 } else {
311fddc7 1488 dev_err(&adapter->pdev->dev, "FAT Table Retrieve error\n");
fe2a70ee
SK		 1489 goto err;
1490 }
311fddc7
SK		 1491 offset += buf_size;
1492 log_offset += buf_size;
1493 }
1494err:
fe2a70ee
SK		 1495 pci_free_consistent(adapter->pdev, get_fat_cmd.size,
1496 get_fat_cmd.va,
1497 get_fat_cmd.dma);
311fddc7
SK		 1498 spin_unlock_bh(&adapter->mcc_lock);
1499}
1500
04b71175
SP		 1501/* Uses synchronous mcc */
1502int be_cmd_get_fw_ver(struct be_adapter *adapter, char *fw_ver,
1503 char *fw_on_flash)
6b7c5b94 1504{
b31c50a7
SP		 1505 struct be_mcc_wrb *wrb;
1506 struct be_cmd_req_get_fw_version *req;
6b7c5b94
SP		 1507 int status;
1508
04b71175 1509 spin_lock_bh(&adapter->mcc_lock);
b31c50a7 1510
04b71175
SP		 1511 wrb = wrb_from_mccq(adapter);
1512 if (!wrb) {
1513 status = -EBUSY;
1514 goto err;
1515 }
6b7c5b94 1516
04b71175 1517 req = embedded_payload(wrb);
6b7c5b94 1518
106df1e3
SK		 1519 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1520 OPCODE_COMMON_GET_FW_VERSION, sizeof(*req), wrb, NULL);
04b71175 1521 status = be_mcc_notify_wait(adapter);
6b7c5b94
SP		 1522 if (!status) {
1523 struct be_cmd_resp_get_fw_version *resp = embedded_payload(wrb);
04b71175
SP		 1524 strcpy(fw_ver, resp->firmware_version_string);
1525 if (fw_on_flash)
1526 strcpy(fw_on_flash, resp->fw_on_flash_version_string);
6b7c5b94 1527 }
04b71175
SP		 1528err:
1529 spin_unlock_bh(&adapter->mcc_lock);
6b7c5b94
SP		 1530 return status;
1531}
1532
b31c50a7
SP		 1533/* set the EQ delay interval of an EQ to specified value
1534 * Uses async mcc
1535 */
8788fdc2 1536int be_cmd_modify_eqd(struct be_adapter *adapter, u32 eq_id, u32 eqd)
6b7c5b94 1537{
b31c50a7
SP		 1538 struct be_mcc_wrb *wrb;
1539 struct be_cmd_req_modify_eq_delay *req;
713d0394 1540 int status = 0;
6b7c5b94 1541
b31c50a7
SP		 1542 spin_lock_bh(&adapter->mcc_lock);
1543
1544 wrb = wrb_from_mccq(adapter);
713d0394
SP		 1545 if (!wrb) {
1546 status = -EBUSY;
1547 goto err;
1548 }
b31c50a7 1549 req = embedded_payload(wrb);
6b7c5b94 1550
106df1e3
SK		 1551 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1552 OPCODE_COMMON_MODIFY_EQ_DELAY, sizeof(*req), wrb, NULL);
6b7c5b94
SP		 1553
1554 req->num_eq = cpu_to_le32(1);
1555 req->delay[0].eq_id = cpu_to_le32(eq_id);
1556 req->delay[0].phase = 0;
1557 req->delay[0].delay_multiplier = cpu_to_le32(eqd);
1558
b31c50a7 1559 be_mcc_notify(adapter);
6b7c5b94 1560
713d0394 1561err:
b31c50a7 1562 spin_unlock_bh(&adapter->mcc_lock);
713d0394 1563 return status;
6b7c5b94
SP		 1564}
1565
b31c50a7 1566/* Uses sycnhronous mcc */
8788fdc2 1567int be_cmd_vlan_config(struct be_adapter *adapter, u32 if_id, u16 *vtag_array,
6b7c5b94
SP		 1568 u32 num, bool untagged, bool promiscuous)
1569{
b31c50a7
SP		 1570 struct be_mcc_wrb *wrb;
1571 struct be_cmd_req_vlan_config *req;
6b7c5b94
SP		 1572 int status;
1573
b31c50a7
SP		 1574 spin_lock_bh(&adapter->mcc_lock);
1575
1576 wrb = wrb_from_mccq(adapter);
713d0394
SP		 1577 if (!wrb) {
1578 status = -EBUSY;
1579 goto err;
1580 }
b31c50a7 1581 req = embedded_payload(wrb);
6b7c5b94 1582
106df1e3
SK		 1583 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1584 OPCODE_COMMON_NTWK_VLAN_CONFIG, sizeof(*req), wrb, NULL);
6b7c5b94
SP		 1585
1586 req->interface_id = if_id;
1587 req->promiscuous = promiscuous;
1588 req->untagged = untagged;
1589 req->num_vlan = num;
1590 if (!promiscuous) {
1591 memcpy(req->normal_vlan, vtag_array,
1592 req->num_vlan * sizeof(vtag_array[0]));
1593 }
1594
b31c50a7 1595 status = be_mcc_notify_wait(adapter);
6b7c5b94 1596
713d0394 1597err:
b31c50a7 1598 spin_unlock_bh(&adapter->mcc_lock);
6b7c5b94
SP		 1599 return status;
1600}
1601
5b8821b7 1602int be_cmd_rx_filter(struct be_adapter *adapter, u32 flags, u32 value)
6b7c5b94 1603{
6ac7b687 1604 struct be_mcc_wrb *wrb;
5b8821b7
SP		 1605 struct be_dma_mem *mem = &adapter->rx_filter;
1606 struct be_cmd_req_rx_filter *req = mem->va;
e7b909a6 1607 int status;
6b7c5b94 1608
8788fdc2 1609 spin_lock_bh(&adapter->mcc_lock);
6ac7b687 1610
b31c50a7 1611 wrb = wrb_from_mccq(adapter);
713d0394
SP		 1612 if (!wrb) {
1613 status = -EBUSY;
1614 goto err;
1615 }
5b8821b7 1616 memset(req, 0, sizeof(*req));
106df1e3
SK		 1617 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1618 OPCODE_COMMON_NTWK_RX_FILTER, sizeof(*req),
1619 wrb, mem);
6b7c5b94 1620
5b8821b7
SP		 1621 req->if_id = cpu_to_le32(adapter->if_handle);
1622 if (flags & IFF_PROMISC) {
1623 req->if_flags_mask = cpu_to_le32(BE_IF_FLAGS_PROMISCUOUS |
1624 BE_IF_FLAGS_VLAN_PROMISCUOUS);
1625 if (value == ON)
1626 req->if_flags = cpu_to_le32(BE_IF_FLAGS_PROMISCUOUS |
8e7d3f68 1627 BE_IF_FLAGS_VLAN_PROMISCUOUS);
5b8821b7
SP		 1628 } else if (flags & IFF_ALLMULTI) {
1629 req->if_flags_mask = req->if_flags =
8e7d3f68 1630 cpu_to_le32(BE_IF_FLAGS_MCAST_PROMISCUOUS);
5b8821b7 1631 } else {
22bedad3 1632 struct netdev_hw_addr *ha;
5b8821b7 1633 int i = 0;
24307eef 1634
8e7d3f68
SP		 1635 req->if_flags_mask = req->if_flags =
1636 cpu_to_le32(BE_IF_FLAGS_MULTICAST);
1610c79f
PR		 1637
1638 /* Reset mcast promisc mode if already set by setting mask
1639 * and not setting flags field
1640 */
0b13fb45
PR		 1641 if (!lancer_chip(adapter) || be_physfn(adapter))
1642 req->if_flags_mask |=
1610c79f
PR		 1643 cpu_to_le32(BE_IF_FLAGS_MCAST_PROMISCUOUS);
1644
016f97b1 1645 req->mcast_num = cpu_to_le32(netdev_mc_count(adapter->netdev));
5b8821b7
SP		 1646 netdev_for_each_mc_addr(ha, adapter->netdev)
1647 memcpy(req->mcast_mac[i++].byte, ha->addr, ETH_ALEN);
6b7c5b94
SP		 1648 }
1649
0d1d5875 1650 status = be_mcc_notify_wait(adapter);
713d0394 1651err:
8788fdc2 1652 spin_unlock_bh(&adapter->mcc_lock);
e7b909a6 1653 return status;
6b7c5b94
SP		 1654}
1655
b31c50a7 1656/* Uses synchrounous mcc */
8788fdc2 1657int be_cmd_set_flow_control(struct be_adapter *adapter, u32 tx_fc, u32 rx_fc)
6b7c5b94 1658{
b31c50a7
SP		 1659 struct be_mcc_wrb *wrb;
1660 struct be_cmd_req_set_flow_control *req;
6b7c5b94
SP		 1661 int status;
1662
b31c50a7 1663 spin_lock_bh(&adapter->mcc_lock);
6b7c5b94 1664
b31c50a7 1665 wrb = wrb_from_mccq(adapter);
713d0394
SP		 1666 if (!wrb) {
1667 status = -EBUSY;
1668 goto err;
1669 }
b31c50a7 1670 req = embedded_payload(wrb);
6b7c5b94 1671
106df1e3
SK		 1672 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1673 OPCODE_COMMON_SET_FLOW_CONTROL, sizeof(*req), wrb, NULL);
6b7c5b94
SP		 1674
1675 req->tx_flow_control = cpu_to_le16((u16)tx_fc);
1676 req->rx_flow_control = cpu_to_le16((u16)rx_fc);
1677
b31c50a7 1678 status = be_mcc_notify_wait(adapter);
6b7c5b94 1679
713d0394 1680err:
b31c50a7 1681 spin_unlock_bh(&adapter->mcc_lock);
6b7c5b94
SP		 1682 return status;
1683}
1684
b31c50a7 1685/* Uses sycn mcc */
8788fdc2 1686int be_cmd_get_flow_control(struct be_adapter *adapter, u32 *tx_fc, u32 *rx_fc)
6b7c5b94 1687{
b31c50a7
SP		 1688 struct be_mcc_wrb *wrb;
1689 struct be_cmd_req_get_flow_control *req;
6b7c5b94
SP		 1690 int status;
1691
b31c50a7 1692 spin_lock_bh(&adapter->mcc_lock);
6b7c5b94 1693
b31c50a7 1694 wrb = wrb_from_mccq(adapter);
713d0394
SP		 1695 if (!wrb) {
1696 status = -EBUSY;
1697 goto err;
1698 }
b31c50a7 1699 req = embedded_payload(wrb);
6b7c5b94 1700
106df1e3
SK		 1701 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1702 OPCODE_COMMON_GET_FLOW_CONTROL, sizeof(*req), wrb, NULL);
6b7c5b94 1703
b31c50a7 1704 status = be_mcc_notify_wait(adapter);
6b7c5b94
SP		 1705 if (!status) {
1706 struct be_cmd_resp_get_flow_control *resp =
1707 embedded_payload(wrb);
1708 *tx_fc = le16_to_cpu(resp->tx_flow_control);
1709 *rx_fc = le16_to_cpu(resp->rx_flow_control);
1710 }
1711
713d0394 1712err:
b31c50a7 1713 spin_unlock_bh(&adapter->mcc_lock);
6b7c5b94
SP		 1714 return status;
1715}
1716
b31c50a7 1717/* Uses mbox */
3abcdeda
SP		 1718int be_cmd_query_fw_cfg(struct be_adapter *adapter, u32 *port_num,
1719 u32 *mode, u32 *caps)
6b7c5b94 1720{
b31c50a7
SP		 1721 struct be_mcc_wrb *wrb;
1722 struct be_cmd_req_query_fw_cfg *req;
6b7c5b94
SP		 1723 int status;
1724
2984961c
IV		 1725 if (mutex_lock_interruptible(&adapter->mbox_lock))
1726 return -1;
6b7c5b94 1727
b31c50a7
SP		 1728 wrb = wrb_from_mbox(adapter);
1729 req = embedded_payload(wrb);
6b7c5b94 1730
106df1e3
SK		 1731 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1732 OPCODE_COMMON_QUERY_FIRMWARE_CONFIG, sizeof(*req), wrb, NULL);
6b7c5b94 1733
b31c50a7 1734 status = be_mbox_notify_wait(adapter);
6b7c5b94
SP		 1735 if (!status) {
1736 struct be_cmd_resp_query_fw_cfg *resp = embedded_payload(wrb);
1737 *port_num = le32_to_cpu(resp->phys_port);
3486be29 1738 *mode = le32_to_cpu(resp->function_mode);
3abcdeda 1739 *caps = le32_to_cpu(resp->function_caps);
6b7c5b94
SP		 1740 }
1741
2984961c 1742 mutex_unlock(&adapter->mbox_lock);
6b7c5b94
SP		 1743 return status;
1744}
14074eab 1745
b31c50a7 1746/* Uses mbox */
14074eab 1747int be_cmd_reset_function(struct be_adapter *adapter)
1748{
b31c50a7
SP		 1749 struct be_mcc_wrb *wrb;
1750 struct be_cmd_req_hdr *req;
14074eab 1751 int status;
1752
bf99e50d
PR		 1753 if (lancer_chip(adapter)) {
1754 status = lancer_wait_ready(adapter);
1755 if (!status) {
1756 iowrite32(SLI_PORT_CONTROL_IP_MASK,
1757 adapter->db + SLIPORT_CONTROL_OFFSET);
1758 status = lancer_test_and_set_rdy_state(adapter);
1759 }
1760 if (status) {
1761 dev_err(&adapter->pdev->dev,
1762 "Adapter in non recoverable error\n");
1763 }
1764 return status;
1765 }
1766
2984961c
IV		 1767 if (mutex_lock_interruptible(&adapter->mbox_lock))
1768 return -1;
14074eab 1769
b31c50a7
SP		 1770 wrb = wrb_from_mbox(adapter);
1771 req = embedded_payload(wrb);
14074eab 1772
106df1e3
SK		 1773 be_wrb_cmd_hdr_prepare(req, CMD_SUBSYSTEM_COMMON,
1774 OPCODE_COMMON_FUNCTION_RESET, sizeof(*req), wrb, NULL);
14074eab 1775
b31c50a7 1776 status = be_mbox_notify_wait(adapter);
14074eab 1777
2984961c 1778 mutex_unlock(&adapter->mbox_lock);
14074eab 1779 return status;
1780}
84517482 1781
3abcdeda
SP		 1782int be_cmd_rss_config(struct be_adapter *adapter, u8 *rsstable, u16 table_size)
1783{
1784 struct be_mcc_wrb *wrb;
1785 struct be_cmd_req_rss_config *req;
65f8584e
PR		 1786 u32 myhash[10] = {0x15d43fa5, 0x2534685a, 0x5f87693a, 0x5668494e,
1787 0x33cf6a53, 0x383334c6, 0x76ac4257, 0x59b242b2,
1788 0x3ea83c02, 0x4a110304};
3abcdeda
SP		 1789 int status;
1790
2984961c
IV		 1791 if (mutex_lock_interruptible(&adapter->mbox_lock))
1792 return -1;
3abcdeda
SP		 1793
1794 wrb = wrb_from_mbox(adapter);
1795 req = embedded_payload(wrb);
1796
106df1e3
SK		 1797 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1798 OPCODE_ETH_RSS_CONFIG, sizeof(*req), wrb, NULL);
3abcdeda
SP		 1799
1800 req->if_id = cpu_to_le32(adapter->if_handle);
1ca7ba92
SP		 1801 req->enable_rss = cpu_to_le16(RSS_ENABLE_TCP_IPV4 | RSS_ENABLE_IPV4 |
1802 RSS_ENABLE_TCP_IPV6 | RSS_ENABLE_IPV6);
d3bd3a5e
PR		 1803
1804 if (lancer_chip(adapter) || skyhawk_chip(adapter)) {
1805 req->hdr.version = 1;
1806 req->enable_rss |= cpu_to_le16(RSS_ENABLE_UDP_IPV4 |
1807 RSS_ENABLE_UDP_IPV6);
1808 }
1809
3abcdeda
SP		 1810 req->cpu_table_size_log2 = cpu_to_le16(fls(table_size) - 1);
1811 memcpy(req->cpu_table, rsstable, table_size);
1812 memcpy(req->hash, myhash, sizeof(myhash));
1813 be_dws_cpu_to_le(req->hash, sizeof(req->hash));
1814
1815 status = be_mbox_notify_wait(adapter);
1816
2984961c 1817 mutex_unlock(&adapter->mbox_lock);
3abcdeda
SP		 1818 return status;
1819}
1820
fad9ab2c
SB		 1821/* Uses sync mcc */
1822int be_cmd_set_beacon_state(struct be_adapter *adapter, u8 port_num,
1823 u8 bcn, u8 sts, u8 state)
1824{
1825 struct be_mcc_wrb *wrb;
1826 struct be_cmd_req_enable_disable_beacon *req;
1827 int status;
1828
1829 spin_lock_bh(&adapter->mcc_lock);
1830
1831 wrb = wrb_from_mccq(adapter);
713d0394
SP		 1832 if (!wrb) {
1833 status = -EBUSY;
1834 goto err;
1835 }
fad9ab2c
SB		 1836 req = embedded_payload(wrb);
1837
106df1e3
SK		 1838 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1839 OPCODE_COMMON_ENABLE_DISABLE_BEACON, sizeof(*req), wrb, NULL);
fad9ab2c
SB		 1840
1841 req->port_num = port_num;
1842 req->beacon_state = state;
1843 req->beacon_duration = bcn;
1844 req->status_duration = sts;
1845
1846 status = be_mcc_notify_wait(adapter);
1847
713d0394 1848err:
fad9ab2c
SB		 1849 spin_unlock_bh(&adapter->mcc_lock);
1850 return status;
1851}
1852
1853/* Uses sync mcc */
1854int be_cmd_get_beacon_state(struct be_adapter *adapter, u8 port_num, u32 *state)
1855{
1856 struct be_mcc_wrb *wrb;
1857 struct be_cmd_req_get_beacon_state *req;
1858 int status;
1859
1860 spin_lock_bh(&adapter->mcc_lock);
1861
1862 wrb = wrb_from_mccq(adapter);
713d0394
SP		 1863 if (!wrb) {
1864 status = -EBUSY;
1865 goto err;
1866 }
fad9ab2c
SB		 1867 req = embedded_payload(wrb);
1868
106df1e3
SK		 1869 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1870 OPCODE_COMMON_GET_BEACON_STATE, sizeof(*req), wrb, NULL);
fad9ab2c
SB		 1871
1872 req->port_num = port_num;
1873
1874 status = be_mcc_notify_wait(adapter);
1875 if (!status) {
1876 struct be_cmd_resp_get_beacon_state *resp =
1877 embedded_payload(wrb);
1878 *state = resp->beacon_state;
1879 }
1880
713d0394 1881err:
fad9ab2c
SB		 1882 spin_unlock_bh(&adapter->mcc_lock);
1883 return status;
1884}
1885
485bf569 1886int lancer_cmd_write_object(struct be_adapter *adapter, struct be_dma_mem *cmd,
f67ef7ba
PR		 1887 u32 data_size, u32 data_offset,
1888 const char *obj_name, u32 *data_written,
1889 u8 *change_status, u8 *addn_status)
485bf569
SN		 1890{
1891 struct be_mcc_wrb *wrb;
1892 struct lancer_cmd_req_write_object *req;
1893 struct lancer_cmd_resp_write_object *resp;
1894 void *ctxt = NULL;
1895 int status;
1896
1897 spin_lock_bh(&adapter->mcc_lock);
1898 adapter->flash_status = 0;
1899
1900 wrb = wrb_from_mccq(adapter);
1901 if (!wrb) {
1902 status = -EBUSY;
1903 goto err_unlock;
1904 }
1905
1906 req = embedded_payload(wrb);
1907
106df1e3 1908 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
485bf569 1909 OPCODE_COMMON_WRITE_OBJECT,
106df1e3
SK		 1910 sizeof(struct lancer_cmd_req_write_object), wrb,
1911 NULL);
485bf569
SN		 1912
1913 ctxt = &req->context;
1914 AMAP_SET_BITS(struct amap_lancer_write_obj_context,
1915 write_length, ctxt, data_size);
1916
1917 if (data_size == 0)
1918 AMAP_SET_BITS(struct amap_lancer_write_obj_context,
1919 eof, ctxt, 1);
1920 else
1921 AMAP_SET_BITS(struct amap_lancer_write_obj_context,
1922 eof, ctxt, 0);
1923
1924 be_dws_cpu_to_le(ctxt, sizeof(req->context));
1925 req->write_offset = cpu_to_le32(data_offset);
1926 strcpy(req->object_name, obj_name);
1927 req->descriptor_count = cpu_to_le32(1);
1928 req->buf_len = cpu_to_le32(data_size);
1929 req->addr_low = cpu_to_le32((cmd->dma +
1930 sizeof(struct lancer_cmd_req_write_object))
1931 & 0xFFFFFFFF);
1932 req->addr_high = cpu_to_le32(upper_32_bits(cmd->dma +
1933 sizeof(struct lancer_cmd_req_write_object)));
1934
1935 be_mcc_notify(adapter);
1936 spin_unlock_bh(&adapter->mcc_lock);
1937
1938 if (!wait_for_completion_timeout(&adapter->flash_compl,
804c7515 1939 msecs_to_jiffies(30000)))
485bf569
SN		 1940 status = -1;
1941 else
1942 status = adapter->flash_status;
1943
1944 resp = embedded_payload(wrb);
f67ef7ba 1945 if (!status) {
485bf569 1946 *data_written = le32_to_cpu(resp->actual_write_len);
f67ef7ba
PR		 1947 *change_status = resp->change_status;
1948 } else {
485bf569 1949 *addn_status = resp->additional_status;
f67ef7ba 1950 }
485bf569
SN		 1951
1952 return status;
1953
1954err_unlock:
1955 spin_unlock_bh(&adapter->mcc_lock);
1956 return status;
1957}
1958
de49bd5a
PR		 1959int lancer_cmd_read_object(struct be_adapter *adapter, struct be_dma_mem *cmd,
1960 u32 data_size, u32 data_offset, const char *obj_name,
1961 u32 *data_read, u32 *eof, u8 *addn_status)
1962{
1963 struct be_mcc_wrb *wrb;
1964 struct lancer_cmd_req_read_object *req;
1965 struct lancer_cmd_resp_read_object *resp;
1966 int status;
1967
1968 spin_lock_bh(&adapter->mcc_lock);
1969
1970 wrb = wrb_from_mccq(adapter);
1971 if (!wrb) {
1972 status = -EBUSY;
1973 goto err_unlock;
1974 }
1975
1976 req = embedded_payload(wrb);
1977
1978 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1979 OPCODE_COMMON_READ_OBJECT,
1980 sizeof(struct lancer_cmd_req_read_object), wrb,
1981 NULL);
1982
1983 req->desired_read_len = cpu_to_le32(data_size);
1984 req->read_offset = cpu_to_le32(data_offset);
1985 strcpy(req->object_name, obj_name);
1986 req->descriptor_count = cpu_to_le32(1);
1987 req->buf_len = cpu_to_le32(data_size);
1988 req->addr_low = cpu_to_le32((cmd->dma & 0xFFFFFFFF));
1989 req->addr_high = cpu_to_le32(upper_32_bits(cmd->dma));
1990
1991 status = be_mcc_notify_wait(adapter);
1992
1993 resp = embedded_payload(wrb);
1994 if (!status) {
1995 *data_read = le32_to_cpu(resp->actual_read_len);
1996 *eof = le32_to_cpu(resp->eof);
1997 } else {
1998 *addn_status = resp->additional_status;
1999 }
2000
2001err_unlock:
2002 spin_unlock_bh(&adapter->mcc_lock);
2003 return status;
2004}
2005
84517482
AK		 2006int be_cmd_write_flashrom(struct be_adapter *adapter, struct be_dma_mem *cmd,
2007 u32 flash_type, u32 flash_opcode, u32 buf_size)
2008{
b31c50a7 2009 struct be_mcc_wrb *wrb;
3f0d4560 2010 struct be_cmd_write_flashrom *req;
84517482
AK		 2011 int status;
2012
b31c50a7 2013 spin_lock_bh(&adapter->mcc_lock);
dd131e76 2014 adapter->flash_status = 0;
b31c50a7
SP		 2015
2016 wrb = wrb_from_mccq(adapter);
713d0394
SP		 2017 if (!wrb) {
2018 status = -EBUSY;
2892d9c2 2019 goto err_unlock;
713d0394
SP		 2020 }
2021 req = cmd->va;
84517482 2022
106df1e3
SK		 2023 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2024 OPCODE_COMMON_WRITE_FLASHROM, cmd->size, wrb, cmd);
84517482
AK		 2025
2026 req->params.op_type = cpu_to_le32(flash_type);
2027 req->params.op_code = cpu_to_le32(flash_opcode);
2028 req->params.data_buf_size = cpu_to_le32(buf_size);
2029
dd131e76
SB		 2030 be_mcc_notify(adapter);
2031 spin_unlock_bh(&adapter->mcc_lock);
2032
2033 if (!wait_for_completion_timeout(&adapter->flash_compl,
e2edb7d5 2034 msecs_to_jiffies(40000)))
dd131e76
SB		 2035 status = -1;
2036 else
2037 status = adapter->flash_status;
84517482 2038
2892d9c2
DC		 2039 return status;
2040
2041err_unlock:
2042 spin_unlock_bh(&adapter->mcc_lock);
84517482
AK		 2043 return status;
2044}
fa9a6fed 2045
3f0d4560
AK		 2046int be_cmd_get_flash_crc(struct be_adapter *adapter, u8 *flashed_crc,
2047 int offset)
fa9a6fed
SB		 2048{
2049 struct be_mcc_wrb *wrb;
2050 struct be_cmd_write_flashrom *req;
2051 int status;
2052
2053 spin_lock_bh(&adapter->mcc_lock);
2054
2055 wrb = wrb_from_mccq(adapter);
713d0394
SP		 2056 if (!wrb) {
2057 status = -EBUSY;
2058 goto err;
2059 }
fa9a6fed
SB		 2060 req = embedded_payload(wrb);
2061
106df1e3
SK		 2062 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2063 OPCODE_COMMON_READ_FLASHROM, sizeof(*req)+4, wrb, NULL);
fa9a6fed 2064
c165541e 2065 req->params.op_type = cpu_to_le32(OPTYPE_REDBOOT);
fa9a6fed 2066 req->params.op_code = cpu_to_le32(FLASHROM_OPER_REPORT);
8b93b710
AK		 2067 req->params.offset = cpu_to_le32(offset);
2068 req->params.data_buf_size = cpu_to_le32(0x4);
fa9a6fed
SB		 2069
2070 status = be_mcc_notify_wait(adapter);
2071 if (!status)
2072 memcpy(flashed_crc, req->params.data_buf, 4);
2073
713d0394 2074err:
fa9a6fed
SB		 2075 spin_unlock_bh(&adapter->mcc_lock);
2076 return status;
2077}
71d8d1b5 2078
c196b02c 2079int be_cmd_enable_magic_wol(struct be_adapter *adapter, u8 *mac,
71d8d1b5
AK		 2080 struct be_dma_mem *nonemb_cmd)
2081{
2082 struct be_mcc_wrb *wrb;
2083 struct be_cmd_req_acpi_wol_magic_config *req;
71d8d1b5
AK		 2084 int status;
2085
2086 spin_lock_bh(&adapter->mcc_lock);
2087
2088 wrb = wrb_from_mccq(adapter);
2089 if (!wrb) {
2090 status = -EBUSY;
2091 goto err;
2092 }
2093 req = nonemb_cmd->va;
71d8d1b5 2094
106df1e3
SK		 2095 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
2096 OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG, sizeof(*req), wrb,
2097 nonemb_cmd);
71d8d1b5
AK		 2098 memcpy(req->magic_mac, mac, ETH_ALEN);
2099
71d8d1b5
AK		 2100 status = be_mcc_notify_wait(adapter);
2101
2102err:
2103 spin_unlock_bh(&adapter->mcc_lock);
2104 return status;
2105}
ff33a6e2 2106
fced9999
SB		 2107int be_cmd_set_loopback(struct be_adapter *adapter, u8 port_num,
2108 u8 loopback_type, u8 enable)
2109{
2110 struct be_mcc_wrb *wrb;
2111 struct be_cmd_req_set_lmode *req;
2112 int status;
2113
2114 spin_lock_bh(&adapter->mcc_lock);
2115
2116 wrb = wrb_from_mccq(adapter);
2117 if (!wrb) {
2118 status = -EBUSY;
2119 goto err;
2120 }
2121
2122 req = embedded_payload(wrb);
2123
106df1e3
SK		 2124 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
2125 OPCODE_LOWLEVEL_SET_LOOPBACK_MODE, sizeof(*req), wrb,
2126 NULL);
fced9999
SB		 2127
2128 req->src_port = port_num;
2129 req->dest_port = port_num;
2130 req->loopback_type = loopback_type;
2131 req->loopback_state = enable;
2132
2133 status = be_mcc_notify_wait(adapter);
2134err:
2135 spin_unlock_bh(&adapter->mcc_lock);
2136 return status;
2137}
2138
ff33a6e2
S		 2139int be_cmd_loopback_test(struct be_adapter *adapter, u32 port_num,
2140 u32 loopback_type, u32 pkt_size, u32 num_pkts, u64 pattern)
2141{
2142 struct be_mcc_wrb *wrb;
2143 struct be_cmd_req_loopback_test *req;
2144 int status;
2145
2146 spin_lock_bh(&adapter->mcc_lock);
2147
2148 wrb = wrb_from_mccq(adapter);
2149 if (!wrb) {
2150 status = -EBUSY;
2151 goto err;
2152 }
2153
2154 req = embedded_payload(wrb);
2155
106df1e3
SK		 2156 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
2157 OPCODE_LOWLEVEL_LOOPBACK_TEST, sizeof(*req), wrb, NULL);
3ffd0515 2158 req->hdr.timeout = cpu_to_le32(4);
ff33a6e2
S		 2159
2160 req->pattern = cpu_to_le64(pattern);
2161 req->src_port = cpu_to_le32(port_num);
2162 req->dest_port = cpu_to_le32(port_num);
2163 req->pkt_size = cpu_to_le32(pkt_size);
2164 req->num_pkts = cpu_to_le32(num_pkts);
2165 req->loopback_type = cpu_to_le32(loopback_type);
2166
2167 status = be_mcc_notify_wait(adapter);
2168 if (!status) {
2169 struct be_cmd_resp_loopback_test *resp = embedded_payload(wrb);
2170 status = le32_to_cpu(resp->status);
2171 }
2172
2173err:
2174 spin_unlock_bh(&adapter->mcc_lock);
2175 return status;
2176}
2177
2178int be_cmd_ddr_dma_test(struct be_adapter *adapter, u64 pattern,
2179 u32 byte_cnt, struct be_dma_mem *cmd)
2180{
2181 struct be_mcc_wrb *wrb;
2182 struct be_cmd_req_ddrdma_test *req;
ff33a6e2
S		 2183 int status;
2184 int i, j = 0;
2185
2186 spin_lock_bh(&adapter->mcc_lock);
2187
2188 wrb = wrb_from_mccq(adapter);
2189 if (!wrb) {
2190 status = -EBUSY;
2191 goto err;
2192 }
2193 req = cmd->va;
106df1e3
SK		 2194 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
2195 OPCODE_LOWLEVEL_HOST_DDR_DMA, cmd->size, wrb, cmd);
ff33a6e2
S		 2196
2197 req->pattern = cpu_to_le64(pattern);
2198 req->byte_count = cpu_to_le32(byte_cnt);
2199 for (i = 0; i < byte_cnt; i++) {
2200 req->snd_buff[i] = (u8)(pattern >> (j*8));
2201 j++;
2202 if (j > 7)
2203 j = 0;
2204 }
2205
2206 status = be_mcc_notify_wait(adapter);
2207
2208 if (!status) {
2209 struct be_cmd_resp_ddrdma_test *resp;
2210 resp = cmd->va;
2211 if ((memcmp(resp->rcv_buff, req->snd_buff, byte_cnt) != 0) ||
2212 resp->snd_err) {
2213 status = -1;
2214 }
2215 }
2216
2217err:
2218 spin_unlock_bh(&adapter->mcc_lock);
2219 return status;
2220}
368c0ca2 2221
c196b02c 2222int be_cmd_get_seeprom_data(struct be_adapter *adapter,
368c0ca2
SB		 2223 struct be_dma_mem *nonemb_cmd)
2224{
2225 struct be_mcc_wrb *wrb;
2226 struct be_cmd_req_seeprom_read *req;
2227 struct be_sge *sge;
2228 int status;
2229
2230 spin_lock_bh(&adapter->mcc_lock);
2231
2232 wrb = wrb_from_mccq(adapter);
e45ff01d
AK		 2233 if (!wrb) {
2234 status = -EBUSY;
2235 goto err;
2236 }
368c0ca2
SB		 2237 req = nonemb_cmd->va;
2238 sge = nonembedded_sgl(wrb);
2239
106df1e3
SK		 2240 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2241 OPCODE_COMMON_SEEPROM_READ, sizeof(*req), wrb,
2242 nonemb_cmd);
368c0ca2
SB		 2243
2244 status = be_mcc_notify_wait(adapter);
2245
e45ff01d 2246err:
368c0ca2
SB		 2247 spin_unlock_bh(&adapter->mcc_lock);
2248 return status;
2249}
ee3cb629 2250
42f11cf2 2251int be_cmd_get_phy_info(struct be_adapter *adapter)
ee3cb629
AK		 2252{
2253 struct be_mcc_wrb *wrb;
2254 struct be_cmd_req_get_phy_info *req;
306f1348 2255 struct be_dma_mem cmd;
ee3cb629
AK		 2256 int status;
2257
2258 spin_lock_bh(&adapter->mcc_lock);
2259
2260 wrb = wrb_from_mccq(adapter);
2261 if (!wrb) {
2262 status = -EBUSY;
2263 goto err;
2264 }
306f1348
SP		 2265 cmd.size = sizeof(struct be_cmd_req_get_phy_info);
2266 cmd.va = pci_alloc_consistent(adapter->pdev, cmd.size,
2267 &cmd.dma);
2268 if (!cmd.va) {
2269 dev_err(&adapter->pdev->dev, "Memory alloc failure\n");
2270 status = -ENOMEM;
2271 goto err;
2272 }
ee3cb629 2273
306f1348 2274 req = cmd.va;
ee3cb629 2275
106df1e3
SK		 2276 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2277 OPCODE_COMMON_GET_PHY_DETAILS, sizeof(*req),
2278 wrb, &cmd);
ee3cb629
AK		 2279
2280 status = be_mcc_notify_wait(adapter);
306f1348
SP		 2281 if (!status) {
2282 struct be_phy_info *resp_phy_info =
2283 cmd.va + sizeof(struct be_cmd_req_hdr);
42f11cf2
AK		 2284 adapter->phy.phy_type = le16_to_cpu(resp_phy_info->phy_type);
2285 adapter->phy.interface_type =
306f1348 2286 le16_to_cpu(resp_phy_info->interface_type);
42f11cf2
AK		 2287 adapter->phy.auto_speeds_supported =
2288 le16_to_cpu(resp_phy_info->auto_speeds_supported);
2289 adapter->phy.fixed_speeds_supported =
2290 le16_to_cpu(resp_phy_info->fixed_speeds_supported);
2291 adapter->phy.misc_params =
2292 le32_to_cpu(resp_phy_info->misc_params);
306f1348
SP		 2293 }
2294 pci_free_consistent(adapter->pdev, cmd.size,
2295 cmd.va, cmd.dma);
ee3cb629
AK		 2296err:
2297 spin_unlock_bh(&adapter->mcc_lock);
2298 return status;
2299}
e1d18735
AK		 2300
2301int be_cmd_set_qos(struct be_adapter *adapter, u32 bps, u32 domain)
2302{
2303 struct be_mcc_wrb *wrb;
2304 struct be_cmd_req_set_qos *req;
2305 int status;
2306
2307 spin_lock_bh(&adapter->mcc_lock);
2308
2309 wrb = wrb_from_mccq(adapter);
2310 if (!wrb) {
2311 status = -EBUSY;
2312 goto err;
2313 }
2314
2315 req = embedded_payload(wrb);
2316
106df1e3
SK		 2317 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2318 OPCODE_COMMON_SET_QOS, sizeof(*req), wrb, NULL);
e1d18735
AK		 2319
2320 req->hdr.domain = domain;
6bff57a7
AK		 2321 req->valid_bits = cpu_to_le32(BE_QOS_BITS_NIC);
2322 req->max_bps_nic = cpu_to_le32(bps);
e1d18735
AK		 2323
2324 status = be_mcc_notify_wait(adapter);
2325
2326err:
2327 spin_unlock_bh(&adapter->mcc_lock);
2328 return status;
2329}
9e1453c5
AK		 2330
2331int be_cmd_get_cntl_attributes(struct be_adapter *adapter)
2332{
2333 struct be_mcc_wrb *wrb;
2334 struct be_cmd_req_cntl_attribs *req;
2335 struct be_cmd_resp_cntl_attribs *resp;
9e1453c5
AK		 2336 int status;
2337 int payload_len = max(sizeof(*req), sizeof(*resp));
2338 struct mgmt_controller_attrib *attribs;
2339 struct be_dma_mem attribs_cmd;
2340
2341 memset(&attribs_cmd, 0, sizeof(struct be_dma_mem));
2342 attribs_cmd.size = sizeof(struct be_cmd_resp_cntl_attribs);
2343 attribs_cmd.va = pci_alloc_consistent(adapter->pdev, attribs_cmd.size,
2344 &attribs_cmd.dma);
2345 if (!attribs_cmd.va) {
2346 dev_err(&adapter->pdev->dev,
2347 "Memory allocation failure\n");
2348 return -ENOMEM;
2349 }
2350
2351 if (mutex_lock_interruptible(&adapter->mbox_lock))
2352 return -1;
2353
2354 wrb = wrb_from_mbox(adapter);
2355 if (!wrb) {
2356 status = -EBUSY;
2357 goto err;
2358 }
2359 req = attribs_cmd.va;
9e1453c5 2360
106df1e3
SK		 2361 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2362 OPCODE_COMMON_GET_CNTL_ATTRIBUTES, payload_len, wrb,
2363 &attribs_cmd);
9e1453c5
AK		 2364
2365 status = be_mbox_notify_wait(adapter);
2366 if (!status) {
43d620c8 2367 attribs = attribs_cmd.va + sizeof(struct be_cmd_resp_hdr);
9e1453c5
AK		 2368 adapter->hba_port_num = attribs->hba_attribs.phy_port;
2369 }
2370
2371err:
2372 mutex_unlock(&adapter->mbox_lock);
2373 pci_free_consistent(adapter->pdev, attribs_cmd.size, attribs_cmd.va,
2374 attribs_cmd.dma);
2375 return status;
2376}
2e588f84
SP		 2377
2378/* Uses mbox */
2dc1deb6 2379int be_cmd_req_native_mode(struct be_adapter *adapter)
2e588f84
SP		 2380{
2381 struct be_mcc_wrb *wrb;
2382 struct be_cmd_req_set_func_cap *req;
2383 int status;
2384
2385 if (mutex_lock_interruptible(&adapter->mbox_lock))
2386 return -1;
2387
2388 wrb = wrb_from_mbox(adapter);
2389 if (!wrb) {
2390 status = -EBUSY;
2391 goto err;
2392 }
2393
2394 req = embedded_payload(wrb);
2395
106df1e3
SK		 2396 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2397 OPCODE_COMMON_SET_DRIVER_FUNCTION_CAP, sizeof(*req), wrb, NULL);
2e588f84
SP		 2398
2399 req->valid_cap_flags = cpu_to_le32(CAPABILITY_SW_TIMESTAMPS |
2400 CAPABILITY_BE3_NATIVE_ERX_API);
2401 req->cap_flags = cpu_to_le32(CAPABILITY_BE3_NATIVE_ERX_API);
2402
2403 status = be_mbox_notify_wait(adapter);
2404 if (!status) {
2405 struct be_cmd_resp_set_func_cap *resp = embedded_payload(wrb);
2406 adapter->be3_native = le32_to_cpu(resp->cap_flags) &
2407 CAPABILITY_BE3_NATIVE_ERX_API;
2408 }
2409err:
2410 mutex_unlock(&adapter->mbox_lock);
2411 return status;
2412}
590c391d
PR		 2413
2414/* Uses synchronous MCCQ */
1578e777
PR		 2415int be_cmd_get_mac_from_list(struct be_adapter *adapter, u8 *mac,
2416 bool *pmac_id_active, u32 *pmac_id, u8 domain)
590c391d
PR		 2417{
2418 struct be_mcc_wrb *wrb;
2419 struct be_cmd_req_get_mac_list *req;
2420 int status;
2421 int mac_count;
e5e1ee89
PR		 2422 struct be_dma_mem get_mac_list_cmd;
2423 int i;
2424
2425 memset(&get_mac_list_cmd, 0, sizeof(struct be_dma_mem));
2426 get_mac_list_cmd.size = sizeof(struct be_cmd_resp_get_mac_list);
2427 get_mac_list_cmd.va = pci_alloc_consistent(adapter->pdev,
2428 get_mac_list_cmd.size,
2429 &get_mac_list_cmd.dma);
2430
2431 if (!get_mac_list_cmd.va) {
2432 dev_err(&adapter->pdev->dev,
2433 "Memory allocation failure during GET_MAC_LIST\n");
2434 return -ENOMEM;
2435 }
590c391d
PR		 2436
2437 spin_lock_bh(&adapter->mcc_lock);
2438
2439 wrb = wrb_from_mccq(adapter);
2440 if (!wrb) {
2441 status = -EBUSY;
e5e1ee89 2442 goto out;
590c391d 2443 }
e5e1ee89
PR		 2444
2445 req = get_mac_list_cmd.va;
590c391d
PR		 2446
2447 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2448 OPCODE_COMMON_GET_MAC_LIST, sizeof(*req),
e5e1ee89 2449 wrb, &get_mac_list_cmd);
590c391d
PR		 2450
2451 req->hdr.domain = domain;
e5e1ee89
PR		 2452 req->mac_type = MAC_ADDRESS_TYPE_NETWORK;
2453 req->perm_override = 1;
590c391d
PR		 2454
2455 status = be_mcc_notify_wait(adapter);
2456 if (!status) {
2457 struct be_cmd_resp_get_mac_list *resp =
e5e1ee89
PR		 2458 get_mac_list_cmd.va;
2459 mac_count = resp->true_mac_count + resp->pseudo_mac_count;
2460 /* Mac list returned could contain one or more active mac_ids
1578e777
PR		 2461 * or one or more true or pseudo permanant mac addresses.
2462 * If an active mac_id is present, return first active mac_id
2463 * found.
e5e1ee89 2464 */
590c391d 2465 for (i = 0; i < mac_count; i++) {
e5e1ee89
PR		 2466 struct get_list_macaddr *mac_entry;
2467 u16 mac_addr_size;
2468 u32 mac_id;
2469
2470 mac_entry = &resp->macaddr_list[i];
2471 mac_addr_size = le16_to_cpu(mac_entry->mac_addr_size);
2472 /* mac_id is a 32 bit value and mac_addr size
2473 * is 6 bytes
2474 */
2475 if (mac_addr_size == sizeof(u32)) {
2476 *pmac_id_active = true;
2477 mac_id = mac_entry->mac_addr_id.s_mac_id.mac_id;
2478 *pmac_id = le32_to_cpu(mac_id);
2479 goto out;
590c391d 2480 }
590c391d 2481 }
1578e777 2482 /* If no active mac_id found, return first mac addr */
e5e1ee89
PR		 2483 *pmac_id_active = false;
2484 memcpy(mac, resp->macaddr_list[0].mac_addr_id.macaddr,
2485 ETH_ALEN);
590c391d
PR		 2486 }
2487
e5e1ee89 2488out:
590c391d 2489 spin_unlock_bh(&adapter->mcc_lock);
e5e1ee89
PR		 2490 pci_free_consistent(adapter->pdev, get_mac_list_cmd.size,
2491 get_mac_list_cmd.va, get_mac_list_cmd.dma);
590c391d
PR		 2492 return status;
2493}
2494
2495/* Uses synchronous MCCQ */
2496int be_cmd_set_mac_list(struct be_adapter *adapter, u8 *mac_array,
2497 u8 mac_count, u32 domain)
2498{
2499 struct be_mcc_wrb *wrb;
2500 struct be_cmd_req_set_mac_list *req;
2501 int status;
2502 struct be_dma_mem cmd;
2503
2504 memset(&cmd, 0, sizeof(struct be_dma_mem));
2505 cmd.size = sizeof(struct be_cmd_req_set_mac_list);
2506 cmd.va = dma_alloc_coherent(&adapter->pdev->dev, cmd.size,
2507 &cmd.dma, GFP_KERNEL);
2508 if (!cmd.va) {
2509 dev_err(&adapter->pdev->dev, "Memory alloc failure\n");
2510 return -ENOMEM;
2511 }
2512
2513 spin_lock_bh(&adapter->mcc_lock);
2514
2515 wrb = wrb_from_mccq(adapter);
2516 if (!wrb) {
2517 status = -EBUSY;
2518 goto err;
2519 }
2520
2521 req = cmd.va;
2522 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2523 OPCODE_COMMON_SET_MAC_LIST, sizeof(*req),
2524 wrb, &cmd);
2525
2526 req->hdr.domain = domain;
2527 req->mac_count = mac_count;
2528 if (mac_count)
2529 memcpy(req->mac, mac_array, ETH_ALEN*mac_count);
2530
2531 status = be_mcc_notify_wait(adapter);
2532
2533err:
2534 dma_free_coherent(&adapter->pdev->dev, cmd.size,
2535 cmd.va, cmd.dma);
2536 spin_unlock_bh(&adapter->mcc_lock);
2537 return status;
2538}
4762f6ce 2539
f1f3ee1b
AK		 2540int be_cmd_set_hsw_config(struct be_adapter *adapter, u16 pvid,
2541 u32 domain, u16 intf_id)
2542{
2543 struct be_mcc_wrb *wrb;
2544 struct be_cmd_req_set_hsw_config *req;
2545 void *ctxt;
2546 int status;
2547
2548 spin_lock_bh(&adapter->mcc_lock);
2549
2550 wrb = wrb_from_mccq(adapter);
2551 if (!wrb) {
2552 status = -EBUSY;
2553 goto err;
2554 }
2555
2556 req = embedded_payload(wrb);
2557 ctxt = &req->context;
2558
2559 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2560 OPCODE_COMMON_SET_HSW_CONFIG, sizeof(*req), wrb, NULL);
2561
2562 req->hdr.domain = domain;
2563 AMAP_SET_BITS(struct amap_set_hsw_context, interface_id, ctxt, intf_id);
2564 if (pvid) {
2565 AMAP_SET_BITS(struct amap_set_hsw_context, pvid_valid, ctxt, 1);
2566 AMAP_SET_BITS(struct amap_set_hsw_context, pvid, ctxt, pvid);
2567 }
2568
2569 be_dws_cpu_to_le(req->context, sizeof(req->context));
2570 status = be_mcc_notify_wait(adapter);
2571
2572err:
2573 spin_unlock_bh(&adapter->mcc_lock);
2574 return status;
2575}
2576
2577/* Get Hyper switch config */
2578int be_cmd_get_hsw_config(struct be_adapter *adapter, u16 *pvid,
2579 u32 domain, u16 intf_id)
2580{
2581 struct be_mcc_wrb *wrb;
2582 struct be_cmd_req_get_hsw_config *req;
2583 void *ctxt;
2584 int status;
2585 u16 vid;
2586
2587 spin_lock_bh(&adapter->mcc_lock);
2588
2589 wrb = wrb_from_mccq(adapter);
2590 if (!wrb) {
2591 status = -EBUSY;
2592 goto err;
2593 }
2594
2595 req = embedded_payload(wrb);
2596 ctxt = &req->context;
2597
2598 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2599 OPCODE_COMMON_GET_HSW_CONFIG, sizeof(*req), wrb, NULL);
2600
2601 req->hdr.domain = domain;
2602 AMAP_SET_BITS(struct amap_get_hsw_req_context, interface_id, ctxt,
2603 intf_id);
2604 AMAP_SET_BITS(struct amap_get_hsw_req_context, pvid_valid, ctxt, 1);
2605 be_dws_cpu_to_le(req->context, sizeof(req->context));
2606
2607 status = be_mcc_notify_wait(adapter);
2608 if (!status) {
2609 struct be_cmd_resp_get_hsw_config *resp =
2610 embedded_payload(wrb);
2611 be_dws_le_to_cpu(&resp->context,
2612 sizeof(resp->context));
2613 vid = AMAP_GET_BITS(struct amap_get_hsw_resp_context,
2614 pvid, &resp->context);
2615 *pvid = le16_to_cpu(vid);
2616 }
2617
2618err:
2619 spin_unlock_bh(&adapter->mcc_lock);
2620 return status;
2621}
2622
4762f6ce
AK		 2623int be_cmd_get_acpi_wol_cap(struct be_adapter *adapter)
2624{
2625 struct be_mcc_wrb *wrb;
2626 struct be_cmd_req_acpi_wol_magic_config_v1 *req;
2627 int status;
2628 int payload_len = sizeof(*req);
2629 struct be_dma_mem cmd;
2630
2631 memset(&cmd, 0, sizeof(struct be_dma_mem));
2632 cmd.size = sizeof(struct be_cmd_resp_acpi_wol_magic_config_v1);
2633 cmd.va = pci_alloc_consistent(adapter->pdev, cmd.size,
2634 &cmd.dma);
2635 if (!cmd.va) {
2636 dev_err(&adapter->pdev->dev,
2637 "Memory allocation failure\n");
2638 return -ENOMEM;
2639 }
2640
2641 if (mutex_lock_interruptible(&adapter->mbox_lock))
2642 return -1;
2643
2644 wrb = wrb_from_mbox(adapter);
2645 if (!wrb) {
2646 status = -EBUSY;
2647 goto err;
2648 }
2649
2650 req = cmd.va;
2651
2652 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
2653 OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG,
2654 payload_len, wrb, &cmd);
2655
2656 req->hdr.version = 1;
2657 req->query_options = BE_GET_WOL_CAP;
2658
2659 status = be_mbox_notify_wait(adapter);
2660 if (!status) {
2661 struct be_cmd_resp_acpi_wol_magic_config_v1 *resp;
2662 resp = (struct be_cmd_resp_acpi_wol_magic_config_v1 *) cmd.va;
2663
2664 /* the command could succeed misleadingly on old f/w
2665 * which is not aware of the V1 version. fake an error. */
2666 if (resp->hdr.response_length < payload_len) {
2667 status = -1;
2668 goto err;
2669 }
2670 adapter->wol_cap = resp->wol_settings;
2671 }
2672err:
2673 mutex_unlock(&adapter->mbox_lock);
2674 pci_free_consistent(adapter->pdev, cmd.size, cmd.va, cmd.dma);
2675 return status;
941a77d5
SK		 2676
2677}
2678int be_cmd_get_ext_fat_capabilites(struct be_adapter *adapter,
2679 struct be_dma_mem *cmd)
2680{
2681 struct be_mcc_wrb *wrb;
2682 struct be_cmd_req_get_ext_fat_caps *req;
2683 int status;
2684
2685 if (mutex_lock_interruptible(&adapter->mbox_lock))
2686 return -1;
2687
2688 wrb = wrb_from_mbox(adapter);
2689 if (!wrb) {
2690 status = -EBUSY;
2691 goto err;
2692 }
2693
2694 req = cmd->va;
2695 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2696 OPCODE_COMMON_GET_EXT_FAT_CAPABILITES,
2697 cmd->size, wrb, cmd);
2698 req->parameter_type = cpu_to_le32(1);
2699
2700 status = be_mbox_notify_wait(adapter);
2701err:
2702 mutex_unlock(&adapter->mbox_lock);
2703 return status;
2704}
2705
2706int be_cmd_set_ext_fat_capabilites(struct be_adapter *adapter,
2707 struct be_dma_mem *cmd,
2708 struct be_fat_conf_params *configs)
2709{
2710 struct be_mcc_wrb *wrb;
2711 struct be_cmd_req_set_ext_fat_caps *req;
2712 int status;
2713
2714 spin_lock_bh(&adapter->mcc_lock);
2715
2716 wrb = wrb_from_mccq(adapter);
2717 if (!wrb) {
2718 status = -EBUSY;
2719 goto err;
2720 }
2721
2722 req = cmd->va;
2723 memcpy(&req->set_params, configs, sizeof(struct be_fat_conf_params));
2724 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2725 OPCODE_COMMON_SET_EXT_FAT_CAPABILITES,
2726 cmd->size, wrb, cmd);
2727
2728 status = be_mcc_notify_wait(adapter);
2729err:
2730 spin_unlock_bh(&adapter->mcc_lock);
2731 return status;
4762f6ce 2732}
6a4ab669 2733
b4e32a71
PR		 2734int be_cmd_query_port_name(struct be_adapter *adapter, u8 *port_name)
2735{
2736 struct be_mcc_wrb *wrb;
2737 struct be_cmd_req_get_port_name *req;
2738 int status;
2739
2740 if (!lancer_chip(adapter)) {
2741 *port_name = adapter->hba_port_num + '0';
2742 return 0;
2743 }
2744
2745 spin_lock_bh(&adapter->mcc_lock);
2746
2747 wrb = wrb_from_mccq(adapter);
2748 if (!wrb) {
2749 status = -EBUSY;
2750 goto err;
2751 }
2752
2753 req = embedded_payload(wrb);
2754
2755 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2756 OPCODE_COMMON_GET_PORT_NAME, sizeof(*req), wrb,
2757 NULL);
2758 req->hdr.version = 1;
2759
2760 status = be_mcc_notify_wait(adapter);
2761 if (!status) {
2762 struct be_cmd_resp_get_port_name *resp = embedded_payload(wrb);
2763 *port_name = resp->port_name[adapter->hba_port_num];
2764 } else {
2765 *port_name = adapter->hba_port_num + '0';
2766 }
2767err:
2768 spin_unlock_bh(&adapter->mcc_lock);
2769 return status;
2770}
2771
6a4ab669
PP		 2772int be_roce_mcc_cmd(void *netdev_handle, void *wrb_payload,
2773 int wrb_payload_size, u16 *cmd_status, u16 *ext_status)
2774{
2775 struct be_adapter *adapter = netdev_priv(netdev_handle);
2776 struct be_mcc_wrb *wrb;
2777 struct be_cmd_req_hdr *hdr = (struct be_cmd_req_hdr *) wrb_payload;
2778 struct be_cmd_req_hdr *req;
2779 struct be_cmd_resp_hdr *resp;
2780 int status;
2781
2782 spin_lock_bh(&adapter->mcc_lock);
2783
2784 wrb = wrb_from_mccq(adapter);
2785 if (!wrb) {
2786 status = -EBUSY;
2787 goto err;
2788 }
2789 req = embedded_payload(wrb);
2790 resp = embedded_payload(wrb);
2791
2792 be_wrb_cmd_hdr_prepare(req, hdr->subsystem,
2793 hdr->opcode, wrb_payload_size, wrb, NULL);
2794 memcpy(req, wrb_payload, wrb_payload_size);
2795 be_dws_cpu_to_le(req, wrb_payload_size);
2796
2797 status = be_mcc_notify_wait(adapter);
2798 if (cmd_status)
2799 *cmd_status = (status & 0xffff);
2800 if (ext_status)
2801 *ext_status = 0;
2802 memcpy(wrb_payload, resp, sizeof(*resp) + resp->response_length);
2803 be_dws_le_to_cpu(wrb_payload, sizeof(*resp) + resp->response_length);
2804err:
2805 spin_unlock_bh(&adapter->mcc_lock);
2806 return status;
2807}
2808EXPORT_SYMBOL(be_roce_mcc_cmd);
Linux kernel - Deliverables
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