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Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/net
[deliverable/linux.git] / drivers / net / ethernet / emulex / benet / be_cmds.c
CommitLineData
6b7c5b94 1/*
40263820 2 * Copyright (C) 2005 - 2014 Emulex
6b7c5b94
SP		 3 * All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License version 2
7 * as published by the Free Software Foundation. The full GNU General
8 * Public License is included in this distribution in the file called COPYING.
9 *
10 * Contact Information:
d2145cde 11 * linux-drivers@emulex.com
6b7c5b94 12 *
d2145cde
AK		 13 * Emulex
14 * 3333 Susan Street
15 * Costa Mesa, CA 92626
6b7c5b94
SP		 16 */
17
6a4ab669 18#include <linux/module.h>
6b7c5b94 19#include "be.h"
8788fdc2 20#include "be_cmds.h"
6b7c5b94 21
f25b119c
PR		 22static struct be_cmd_priv_map cmd_priv_map[] = {
23 {
24 OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG,
25 CMD_SUBSYSTEM_ETH,
26 BE_PRIV_LNKMGMT | BE_PRIV_VHADM |
27 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC
28 },
29 {
30 OPCODE_COMMON_GET_FLOW_CONTROL,
31 CMD_SUBSYSTEM_COMMON,
32 BE_PRIV_LNKQUERY | BE_PRIV_VHADM |
33 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC
34 },
35 {
36 OPCODE_COMMON_SET_FLOW_CONTROL,
37 CMD_SUBSYSTEM_COMMON,
38 BE_PRIV_LNKMGMT | BE_PRIV_VHADM |
39 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC
40 },
41 {
42 OPCODE_ETH_GET_PPORT_STATS,
43 CMD_SUBSYSTEM_ETH,
44 BE_PRIV_LNKMGMT | BE_PRIV_VHADM |
45 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC
46 },
47 {
48 OPCODE_COMMON_GET_PHY_DETAILS,
49 CMD_SUBSYSTEM_COMMON,
50 BE_PRIV_LNKMGMT | BE_PRIV_VHADM |
51 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC
52 }
53};
54
55static bool be_cmd_allowed(struct be_adapter *adapter, u8 opcode,
56 u8 subsystem)
57{
58 int i;
59 int num_entries = sizeof(cmd_priv_map)/sizeof(struct be_cmd_priv_map);
60 u32 cmd_privileges = adapter->cmd_privileges;
61
62 for (i = 0; i < num_entries; i++)
63 if (opcode == cmd_priv_map[i].opcode &&
64 subsystem == cmd_priv_map[i].subsystem)
65 if (!(cmd_privileges & cmd_priv_map[i].priv_mask))
66 return false;
67
68 return true;
69}
70
3de09455
SK		 71static inline void *embedded_payload(struct be_mcc_wrb *wrb)
72{
73 return wrb->payload.embedded_payload;
74}
609ff3bb 75
8788fdc2 76static void be_mcc_notify(struct be_adapter *adapter)
5fb379ee 77{
8788fdc2 78 struct be_queue_info *mccq = &adapter->mcc_obj.q;
5fb379ee
SP		 79 u32 val = 0;
80
6589ade0 81 if (be_error(adapter))
7acc2087 82 return;
7acc2087 83
5fb379ee
SP		 84 val |= mccq->id & DB_MCCQ_RING_ID_MASK;
85 val |= 1 << DB_MCCQ_NUM_POSTED_SHIFT;
f3eb62d2
SP		 86
87 wmb();
8788fdc2 88 iowrite32(val, adapter->db + DB_MCCQ_OFFSET);
5fb379ee
SP		 89}
90
91/* To check if valid bit is set, check the entire word as we don't know
92 * the endianness of the data (old entry is host endian while a new entry is
93 * little endian) */
efd2e40a 94static inline bool be_mcc_compl_is_new(struct be_mcc_compl *compl)
5fb379ee 95{
9e9ff4b7
SP		 96 u32 flags;
97
5fb379ee 98 if (compl->flags != 0) {
9e9ff4b7
SP		 99 flags = le32_to_cpu(compl->flags);
100 if (flags & CQE_FLAGS_VALID_MASK) {
101 compl->flags = flags;
102 return true;
103 }
5fb379ee 104 }
9e9ff4b7 105 return false;
5fb379ee
SP		 106}
107
108/* Need to reset the entire word that houses the valid bit */
efd2e40a 109static inline void be_mcc_compl_use(struct be_mcc_compl *compl)
5fb379ee
SP		 110{
111 compl->flags = 0;
112}
113
652bf646
PR		 114static struct be_cmd_resp_hdr *be_decode_resp_hdr(u32 tag0, u32 tag1)
115{
116 unsigned long addr;
117
118 addr = tag1;
119 addr = ((addr << 16) << 16) | tag0;
120 return (void *)addr;
121}
122
8788fdc2 123static int be_mcc_compl_process(struct be_adapter *adapter,
652bf646 124 struct be_mcc_compl *compl)
5fb379ee
SP		 125{
126 u16 compl_status, extd_status;
652bf646
PR		 127 struct be_cmd_resp_hdr *resp_hdr;
128 u8 opcode = 0, subsystem = 0;
5fb379ee
SP		 129
130 /* Just swap the status to host endian; mcc tag is opaquely copied
131 * from mcc_wrb */
132 be_dws_le_to_cpu(compl, 4);
133
134 compl_status = (compl->status >> CQE_STATUS_COMPL_SHIFT) &
135 CQE_STATUS_COMPL_MASK;
dd131e76 136
652bf646
PR		 137 resp_hdr = be_decode_resp_hdr(compl->tag0, compl->tag1);
138
139 if (resp_hdr) {
140 opcode = resp_hdr->opcode;
141 subsystem = resp_hdr->subsystem;
142 }
143
5eeff635
SR		 144 if (opcode == OPCODE_LOWLEVEL_LOOPBACK_TEST &&
145 subsystem == CMD_SUBSYSTEM_LOWLEVEL) {
146 complete(&adapter->et_cmd_compl);
147 return 0;
148 }
149
652bf646
PR		 150 if (((opcode == OPCODE_COMMON_WRITE_FLASHROM) ||
151 (opcode == OPCODE_COMMON_WRITE_OBJECT)) &&
152 (subsystem == CMD_SUBSYSTEM_COMMON)) {
dd131e76 153 adapter->flash_status = compl_status;
5eeff635 154 complete(&adapter->et_cmd_compl);
dd131e76
SB		 155 }
156
b31c50a7 157 if (compl_status == MCC_STATUS_SUCCESS) {
652bf646
PR		 158 if (((opcode == OPCODE_ETH_GET_STATISTICS) ||
159 (opcode == OPCODE_ETH_GET_PPORT_STATS)) &&
160 (subsystem == CMD_SUBSYSTEM_ETH)) {
89a88ab8 161 be_parse_stats(adapter);
b2aebe6d 162 adapter->stats_cmd_sent = false;
b31c50a7 163 }
652bf646
PR		 164 if (opcode == OPCODE_COMMON_GET_CNTL_ADDITIONAL_ATTRIBUTES &&
165 subsystem == CMD_SUBSYSTEM_COMMON) {
3de09455 166 struct be_cmd_resp_get_cntl_addnl_attribs *resp =
652bf646 167 (void *)resp_hdr;
3de09455
SK		 168 adapter->drv_stats.be_on_die_temperature =
169 resp->on_die_temperature;
170 }
2b3f291b 171 } else {
652bf646 172 if (opcode == OPCODE_COMMON_GET_CNTL_ADDITIONAL_ATTRIBUTES)
7aeb2156 173 adapter->be_get_temp_freq = 0;
3de09455 174
2b3f291b
SP		 175 if (compl_status == MCC_STATUS_NOT_SUPPORTED ||
176 compl_status == MCC_STATUS_ILLEGAL_REQUEST)
177 goto done;
178
179 if (compl_status == MCC_STATUS_UNAUTHORIZED_REQUEST) {
97f1d8cd 180 dev_warn(&adapter->pdev->dev,
522609f2 181 "VF is not privileged to issue opcode %d-%d\n",
97f1d8cd 182 opcode, subsystem);
2b3f291b
SP		 183 } else {
184 extd_status = (compl->status >> CQE_STATUS_EXTD_SHIFT) &
185 CQE_STATUS_EXTD_MASK;
97f1d8cd
VV		 186 dev_err(&adapter->pdev->dev,
187 "opcode %d-%d failed:status %d-%d\n",
188 opcode, subsystem, compl_status, extd_status);
d9d604f8
AK		 189
190 if (extd_status == MCC_ADDL_STS_INSUFFICIENT_RESOURCES)
191 return extd_status;
2b3f291b 192 }
5fb379ee 193 }
2b3f291b 194done:
b31c50a7 195 return compl_status;
5fb379ee
SP		 196}
197
a8f447bd 198/* Link state evt is a string of bytes; no need for endian swapping */
8788fdc2 199static void be_async_link_state_process(struct be_adapter *adapter,
a8f447bd
SP		 200 struct be_async_event_link_state *evt)
201{
b236916a 202 /* When link status changes, link speed must be re-queried from FW */
42f11cf2 203 adapter->phy.link_speed = -1;
b236916a 204
bdce2ad7
SR		 205 /* On BEx the FW does not send a separate link status
206 * notification for physical and logical link.
207 * On other chips just process the logical link
208 * status notification
209 */
210 if (!BEx_chip(adapter) &&
2e177a5c
PR		 211 !(evt->port_link_status & LOGICAL_LINK_STATUS_MASK))
212 return;
213
b236916a
AK		 214 /* For the initial link status do not rely on the ASYNC event as
215 * it may not be received in some cases.
216 */
217 if (adapter->flags & BE_FLAGS_LINK_STATUS_INIT)
bdce2ad7
SR		 218 be_link_status_update(adapter,
219 evt->port_link_status & LINK_STATUS_MASK);
a8f447bd
SP		 220}
221
cc4ce020
SK		 222/* Grp5 CoS Priority evt */
223static void be_async_grp5_cos_priority_process(struct be_adapter *adapter,
224 struct be_async_event_grp5_cos_priority *evt)
225{
226 if (evt->valid) {
227 adapter->vlan_prio_bmap = evt->available_priority_bmap;
60964dd7 228 adapter->recommended_prio &= ~VLAN_PRIO_MASK;
cc4ce020
SK		 229 adapter->recommended_prio =
230 evt->reco_default_priority << VLAN_PRIO_SHIFT;
231 }
232}
233
323ff71e 234/* Grp5 QOS Speed evt: qos_link_speed is in units of 10 Mbps */
cc4ce020
SK		 235static void be_async_grp5_qos_speed_process(struct be_adapter *adapter,
236 struct be_async_event_grp5_qos_link_speed *evt)
237{
323ff71e
SP		 238 if (adapter->phy.link_speed >= 0 &&
239 evt->physical_port == adapter->port_num)
240 adapter->phy.link_speed = le16_to_cpu(evt->qos_link_speed) * 10;
cc4ce020
SK		 241}
242
3968fa1e
AK		 243/*Grp5 PVID evt*/
244static void be_async_grp5_pvid_state_process(struct be_adapter *adapter,
245 struct be_async_event_grp5_pvid_state *evt)
246{
bdac85b5 247 if (evt->enabled) {
939cf306 248 adapter->pvid = le16_to_cpu(evt->tag) & VLAN_VID_MASK;
bdac85b5
RN		 249 dev_info(&adapter->pdev->dev, "LPVID: %d\n", adapter->pvid);
250 } else {
3968fa1e 251 adapter->pvid = 0;
bdac85b5 252 }
3968fa1e
AK		 253}
254
cc4ce020
SK		 255static void be_async_grp5_evt_process(struct be_adapter *adapter,
256 u32 trailer, struct be_mcc_compl *evt)
257{
258 u8 event_type = 0;
259
260 event_type = (trailer >> ASYNC_TRAILER_EVENT_TYPE_SHIFT) &
261 ASYNC_TRAILER_EVENT_TYPE_MASK;
262
263 switch (event_type) {
264 case ASYNC_EVENT_COS_PRIORITY:
265 be_async_grp5_cos_priority_process(adapter,
266 (struct be_async_event_grp5_cos_priority *)evt);
267 break;
268 case ASYNC_EVENT_QOS_SPEED:
269 be_async_grp5_qos_speed_process(adapter,
270 (struct be_async_event_grp5_qos_link_speed *)evt);
271 break;
3968fa1e
AK		 272 case ASYNC_EVENT_PVID_STATE:
273 be_async_grp5_pvid_state_process(adapter,
274 (struct be_async_event_grp5_pvid_state *)evt);
275 break;
cc4ce020 276 default:
05ccaa2b
VV		 277 dev_warn(&adapter->pdev->dev, "Unknown grp5 event 0x%x!\n",
278 event_type);
cc4ce020
SK		 279 break;
280 }
281}
282
bc0c3405
AK		 283static void be_async_dbg_evt_process(struct be_adapter *adapter,
284 u32 trailer, struct be_mcc_compl *cmp)
285{
286 u8 event_type = 0;
287 struct be_async_event_qnq *evt = (struct be_async_event_qnq *) cmp;
288
289 event_type = (trailer >> ASYNC_TRAILER_EVENT_TYPE_SHIFT) &
290 ASYNC_TRAILER_EVENT_TYPE_MASK;
291
292 switch (event_type) {
293 case ASYNC_DEBUG_EVENT_TYPE_QNQ:
294 if (evt->valid)
295 adapter->qnq_vid = le16_to_cpu(evt->vlan_tag);
296 adapter->flags |= BE_FLAGS_QNQ_ASYNC_EVT_RCVD;
297 break;
298 default:
05ccaa2b
VV		 299 dev_warn(&adapter->pdev->dev, "Unknown debug event 0x%x!\n",
300 event_type);
bc0c3405
AK		 301 break;
302 }
303}
304
a8f447bd
SP		 305static inline bool is_link_state_evt(u32 trailer)
306{
807540ba 307 return ((trailer >> ASYNC_TRAILER_EVENT_CODE_SHIFT) &
a8f447bd 308 ASYNC_TRAILER_EVENT_CODE_MASK) ==
807540ba 309 ASYNC_EVENT_CODE_LINK_STATE;
a8f447bd 310}
5fb379ee 311
cc4ce020
SK		 312static inline bool is_grp5_evt(u32 trailer)
313{
314 return (((trailer >> ASYNC_TRAILER_EVENT_CODE_SHIFT) &
315 ASYNC_TRAILER_EVENT_CODE_MASK) ==
316 ASYNC_EVENT_CODE_GRP_5);
317}
318
bc0c3405
AK		 319static inline bool is_dbg_evt(u32 trailer)
320{
321 return (((trailer >> ASYNC_TRAILER_EVENT_CODE_SHIFT) &
322 ASYNC_TRAILER_EVENT_CODE_MASK) ==
323 ASYNC_EVENT_CODE_QNQ);
324}
325
efd2e40a 326static struct be_mcc_compl *be_mcc_compl_get(struct be_adapter *adapter)
5fb379ee 327{
8788fdc2 328 struct be_queue_info *mcc_cq = &adapter->mcc_obj.cq;
efd2e40a 329 struct be_mcc_compl *compl = queue_tail_node(mcc_cq);
5fb379ee
SP		 330
331 if (be_mcc_compl_is_new(compl)) {
332 queue_tail_inc(mcc_cq);
333 return compl;
334 }
335 return NULL;
336}
337
7a1e9b20
SP		 338void be_async_mcc_enable(struct be_adapter *adapter)
339{
340 spin_lock_bh(&adapter->mcc_cq_lock);
341
342 be_cq_notify(adapter, adapter->mcc_obj.cq.id, true, 0);
343 adapter->mcc_obj.rearm_cq = true;
344
345 spin_unlock_bh(&adapter->mcc_cq_lock);
346}
347
348void be_async_mcc_disable(struct be_adapter *adapter)
349{
a323d9bf
SP		 350 spin_lock_bh(&adapter->mcc_cq_lock);
351
7a1e9b20 352 adapter->mcc_obj.rearm_cq = false;
a323d9bf
SP		 353 be_cq_notify(adapter, adapter->mcc_obj.cq.id, false, 0);
354
355 spin_unlock_bh(&adapter->mcc_cq_lock);
7a1e9b20
SP		 356}
357
10ef9ab4 358int be_process_mcc(struct be_adapter *adapter)
5fb379ee 359{
efd2e40a 360 struct be_mcc_compl *compl;
10ef9ab4 361 int num = 0, status = 0;
7a1e9b20 362 struct be_mcc_obj *mcc_obj = &adapter->mcc_obj;
5fb379ee 363
072a9c48 364 spin_lock(&adapter->mcc_cq_lock);
8788fdc2 365 while ((compl = be_mcc_compl_get(adapter))) {
a8f447bd
SP		 366 if (compl->flags & CQE_FLAGS_ASYNC_MASK) {
367 /* Interpret flags as an async trailer */
323f30b3
AK		 368 if (is_link_state_evt(compl->flags))
369 be_async_link_state_process(adapter,
a8f447bd 370 (struct be_async_event_link_state *) compl);
cc4ce020
SK		 371 else if (is_grp5_evt(compl->flags))
372 be_async_grp5_evt_process(adapter,
373 compl->flags, compl);
bc0c3405
AK		 374 else if (is_dbg_evt(compl->flags))
375 be_async_dbg_evt_process(adapter,
376 compl->flags, compl);
b31c50a7 377 } else if (compl->flags & CQE_FLAGS_COMPLETED_MASK) {
10ef9ab4 378 status = be_mcc_compl_process(adapter, compl);
7a1e9b20 379 atomic_dec(&mcc_obj->q.used);
5fb379ee
SP		 380 }
381 be_mcc_compl_use(compl);
382 num++;
383 }
b31c50a7 384
10ef9ab4
SP		 385 if (num)
386 be_cq_notify(adapter, mcc_obj->cq.id, mcc_obj->rearm_cq, num);
387
072a9c48 388 spin_unlock(&adapter->mcc_cq_lock);
10ef9ab4 389 return status;
5fb379ee
SP		 390}
391
6ac7b687 392/* Wait till no more pending mcc requests are present */
b31c50a7 393static int be_mcc_wait_compl(struct be_adapter *adapter)
6ac7b687 394{
b31c50a7 395#define mcc_timeout 120000 /* 12s timeout */
10ef9ab4 396 int i, status = 0;
f31e50a8
SP		 397 struct be_mcc_obj *mcc_obj = &adapter->mcc_obj;
398
6ac7b687 399 for (i = 0; i < mcc_timeout; i++) {
6589ade0
SP		 400 if (be_error(adapter))
401 return -EIO;
402
072a9c48 403 local_bh_disable();
10ef9ab4 404 status = be_process_mcc(adapter);
072a9c48 405 local_bh_enable();
b31c50a7 406
f31e50a8 407 if (atomic_read(&mcc_obj->q.used) == 0)
6ac7b687
SP		 408 break;
409 udelay(100);
410 }
b31c50a7 411 if (i == mcc_timeout) {
6589ade0
SP		 412 dev_err(&adapter->pdev->dev, "FW not responding\n");
413 adapter->fw_timeout = true;
652bf646 414 return -EIO;
b31c50a7 415 }
f31e50a8 416 return status;
6ac7b687
SP		 417}
418
419/* Notify MCC requests and wait for completion */
b31c50a7 420static int be_mcc_notify_wait(struct be_adapter *adapter)
6ac7b687 421{
652bf646
PR		 422 int status;
423 struct be_mcc_wrb *wrb;
424 struct be_mcc_obj *mcc_obj = &adapter->mcc_obj;
425 u16 index = mcc_obj->q.head;
426 struct be_cmd_resp_hdr *resp;
427
428 index_dec(&index, mcc_obj->q.len);
429 wrb = queue_index_node(&mcc_obj->q, index);
430
431 resp = be_decode_resp_hdr(wrb->tag0, wrb->tag1);
432
8788fdc2 433 be_mcc_notify(adapter);
652bf646
PR		 434
435 status = be_mcc_wait_compl(adapter);
436 if (status == -EIO)
437 goto out;
438
439 status = resp->status;
440out:
441 return status;
6ac7b687
SP		 442}
443
5f0b849e 444static int be_mbox_db_ready_wait(struct be_adapter *adapter, void __iomem *db)
6b7c5b94 445{
f25b03a7 446 int msecs = 0;
6b7c5b94
SP		 447 u32 ready;
448
449 do {
6589ade0
SP		 450 if (be_error(adapter))
451 return -EIO;
452
cf588477 453 ready = ioread32(db);
434b3648 454 if (ready == 0xffffffff)
cf588477 455 return -1;
cf588477
SP		 456
457 ready &= MPU_MAILBOX_DB_RDY_MASK;
6b7c5b94
SP		 458 if (ready)
459 break;
460
f25b03a7 461 if (msecs > 4000) {
6589ade0
SP		 462 dev_err(&adapter->pdev->dev, "FW not responding\n");
463 adapter->fw_timeout = true;
f67ef7ba 464 be_detect_error(adapter);
6b7c5b94
SP		 465 return -1;
466 }
467
1dbf53a2 468 msleep(1);
f25b03a7 469 msecs++;
6b7c5b94
SP		 470 } while (true);
471
472 return 0;
473}
474
475/*
476 * Insert the mailbox address into the doorbell in two steps
5fb379ee 477 * Polls on the mbox doorbell till a command completion (or a timeout) occurs
6b7c5b94 478 */
b31c50a7 479static int be_mbox_notify_wait(struct be_adapter *adapter)
6b7c5b94
SP		 480{
481 int status;
6b7c5b94 482 u32 val = 0;
8788fdc2
SP		 483 void __iomem *db = adapter->db + MPU_MAILBOX_DB_OFFSET;
484 struct be_dma_mem *mbox_mem = &adapter->mbox_mem;
6b7c5b94 485 struct be_mcc_mailbox *mbox = mbox_mem->va;
efd2e40a 486 struct be_mcc_compl *compl = &mbox->compl;
6b7c5b94 487
cf588477
SP		 488 /* wait for ready to be set */
489 status = be_mbox_db_ready_wait(adapter, db);
490 if (status != 0)
491 return status;
492
6b7c5b94
SP		 493 val |= MPU_MAILBOX_DB_HI_MASK;
494 /* at bits 2 - 31 place mbox dma addr msb bits 34 - 63 */
495 val |= (upper_32_bits(mbox_mem->dma) >> 2) << 2;
496 iowrite32(val, db);
497
498 /* wait for ready to be set */
5f0b849e 499 status = be_mbox_db_ready_wait(adapter, db);
6b7c5b94
SP		 500 if (status != 0)
501 return status;
502
503 val = 0;
6b7c5b94
SP		 504 /* at bits 2 - 31 place mbox dma addr lsb bits 4 - 33 */
505 val |= (u32)(mbox_mem->dma >> 4) << 2;
506 iowrite32(val, db);
507
5f0b849e 508 status = be_mbox_db_ready_wait(adapter, db);
6b7c5b94
SP		 509 if (status != 0)
510 return status;
511
5fb379ee 512 /* A cq entry has been made now */
efd2e40a
SP		 513 if (be_mcc_compl_is_new(compl)) {
514 status = be_mcc_compl_process(adapter, &mbox->compl);
515 be_mcc_compl_use(compl);
5fb379ee
SP		 516 if (status)
517 return status;
518 } else {
5f0b849e 519 dev_err(&adapter->pdev->dev, "invalid mailbox completion\n");
6b7c5b94
SP		 520 return -1;
521 }
5fb379ee 522 return 0;
6b7c5b94
SP		 523}
524
c5b3ad4c 525static u16 be_POST_stage_get(struct be_adapter *adapter)
6b7c5b94 526{
fe6d2a38
SP		 527 u32 sem;
528
c5b3ad4c
SP		 529 if (BEx_chip(adapter))
530 sem = ioread32(adapter->csr + SLIPORT_SEMAPHORE_OFFSET_BEx);
6b7c5b94 531 else
c5b3ad4c
SP		 532 pci_read_config_dword(adapter->pdev,
533 SLIPORT_SEMAPHORE_OFFSET_SH, &sem);
534
535 return sem & POST_STAGE_MASK;
6b7c5b94
SP		 536}
537
87f20c26 538static int lancer_wait_ready(struct be_adapter *adapter)
bf99e50d
PR		 539{
540#define SLIPORT_READY_TIMEOUT 30
541 u32 sliport_status;
542 int status = 0, i;
543
544 for (i = 0; i < SLIPORT_READY_TIMEOUT; i++) {
545 sliport_status = ioread32(adapter->db + SLIPORT_STATUS_OFFSET);
546 if (sliport_status & SLIPORT_STATUS_RDY_MASK)
547 break;
548
549 msleep(1000);
550 }
551
552 if (i == SLIPORT_READY_TIMEOUT)
553 status = -1;
554
555 return status;
556}
557
67297ad8
PR		 558static bool lancer_provisioning_error(struct be_adapter *adapter)
559{
560 u32 sliport_status = 0, sliport_err1 = 0, sliport_err2 = 0;
561 sliport_status = ioread32(adapter->db + SLIPORT_STATUS_OFFSET);
562 if (sliport_status & SLIPORT_STATUS_ERR_MASK) {
563 sliport_err1 = ioread32(adapter->db +
564 SLIPORT_ERROR1_OFFSET);
565 sliport_err2 = ioread32(adapter->db +
566 SLIPORT_ERROR2_OFFSET);
567
568 if (sliport_err1 == SLIPORT_ERROR_NO_RESOURCE1 &&
569 sliport_err2 == SLIPORT_ERROR_NO_RESOURCE2)
570 return true;
571 }
572 return false;
573}
574
bf99e50d
PR		 575int lancer_test_and_set_rdy_state(struct be_adapter *adapter)
576{
577 int status;
578 u32 sliport_status, err, reset_needed;
67297ad8
PR		 579 bool resource_error;
580
581 resource_error = lancer_provisioning_error(adapter);
582 if (resource_error)
01e5b2c4 583 return -EAGAIN;
67297ad8 584
bf99e50d
PR		 585 status = lancer_wait_ready(adapter);
586 if (!status) {
587 sliport_status = ioread32(adapter->db + SLIPORT_STATUS_OFFSET);
588 err = sliport_status & SLIPORT_STATUS_ERR_MASK;
589 reset_needed = sliport_status & SLIPORT_STATUS_RN_MASK;
590 if (err && reset_needed) {
591 iowrite32(SLI_PORT_CONTROL_IP_MASK,
592 adapter->db + SLIPORT_CONTROL_OFFSET);
593
594 /* check adapter has corrected the error */
595 status = lancer_wait_ready(adapter);
596 sliport_status = ioread32(adapter->db +
597 SLIPORT_STATUS_OFFSET);
598 sliport_status &= (SLIPORT_STATUS_ERR_MASK |
599 SLIPORT_STATUS_RN_MASK);
600 if (status || sliport_status)
601 status = -1;
602 } else if (err || reset_needed) {
603 status = -1;
604 }
605 }
67297ad8
PR		 606 /* Stop error recovery if error is not recoverable.
607 * No resource error is temporary errors and will go away
608 * when PF provisions resources.
609 */
610 resource_error = lancer_provisioning_error(adapter);
01e5b2c4
SK		 611 if (resource_error)
612 status = -EAGAIN;
67297ad8 613
bf99e50d
PR		 614 return status;
615}
616
617int be_fw_wait_ready(struct be_adapter *adapter)
6b7c5b94 618{
43a04fdc
SP		 619 u16 stage;
620 int status, timeout = 0;
6ed35eea 621 struct device *dev = &adapter->pdev->dev;
6b7c5b94 622
bf99e50d
PR		 623 if (lancer_chip(adapter)) {
624 status = lancer_wait_ready(adapter);
625 return status;
626 }
627
43a04fdc 628 do {
c5b3ad4c 629 stage = be_POST_stage_get(adapter);
66d29cbc 630 if (stage == POST_STAGE_ARMFW_RDY)
43a04fdc 631 return 0;
66d29cbc
GS		 632
633 dev_info(dev, "Waiting for POST, %ds elapsed\n",
634 timeout);
635 if (msleep_interruptible(2000)) {
636 dev_err(dev, "Waiting for POST aborted\n");
637 return -EINTR;
43a04fdc 638 }
66d29cbc 639 timeout += 2;
3ab81b5f 640 } while (timeout < 60);
6b7c5b94 641
6ed35eea 642 dev_err(dev, "POST timeout; stage=0x%x\n", stage);
43a04fdc 643 return -1;
6b7c5b94
SP		 644}
645
6b7c5b94
SP		 646
647static inline struct be_sge *nonembedded_sgl(struct be_mcc_wrb *wrb)
648{
649 return &wrb->payload.sgl[0];
650}
651
bea50988
SP		 652static inline void fill_wrb_tags(struct be_mcc_wrb *wrb,
653 unsigned long addr)
654{
655 wrb->tag0 = addr & 0xFFFFFFFF;
656 wrb->tag1 = upper_32_bits(addr);
657}
6b7c5b94
SP		 658
659/* Don't touch the hdr after it's prepared */
106df1e3
SK		 660/* mem will be NULL for embedded commands */
661static void be_wrb_cmd_hdr_prepare(struct be_cmd_req_hdr *req_hdr,
662 u8 subsystem, u8 opcode, int cmd_len,
663 struct be_mcc_wrb *wrb, struct be_dma_mem *mem)
6b7c5b94 664{
106df1e3
SK		 665 struct be_sge *sge;
666
6b7c5b94
SP		 667 req_hdr->opcode = opcode;
668 req_hdr->subsystem = subsystem;
669 req_hdr->request_length = cpu_to_le32(cmd_len - sizeof(*req_hdr));
07793d33 670 req_hdr->version = 0;
bea50988 671 fill_wrb_tags(wrb, (ulong) req_hdr);
106df1e3
SK		 672 wrb->payload_length = cmd_len;
673 if (mem) {
674 wrb->embedded |= (1 & MCC_WRB_SGE_CNT_MASK) <<
675 MCC_WRB_SGE_CNT_SHIFT;
676 sge = nonembedded_sgl(wrb);
677 sge->pa_hi = cpu_to_le32(upper_32_bits(mem->dma));
678 sge->pa_lo = cpu_to_le32(mem->dma & 0xFFFFFFFF);
679 sge->len = cpu_to_le32(mem->size);
680 } else
681 wrb->embedded |= MCC_WRB_EMBEDDED_MASK;
682 be_dws_cpu_to_le(wrb, 8);
6b7c5b94
SP		 683}
684
685static void be_cmd_page_addrs_prepare(struct phys_addr *pages, u32 max_pages,
686 struct be_dma_mem *mem)
687{
688 int i, buf_pages = min(PAGES_4K_SPANNED(mem->va, mem->size), max_pages);
689 u64 dma = (u64)mem->dma;
690
691 for (i = 0; i < buf_pages; i++) {
692 pages[i].lo = cpu_to_le32(dma & 0xFFFFFFFF);
693 pages[i].hi = cpu_to_le32(upper_32_bits(dma));
694 dma += PAGE_SIZE_4K;
695 }
696}
697
b31c50a7 698static inline struct be_mcc_wrb *wrb_from_mbox(struct be_adapter *adapter)
6b7c5b94 699{
b31c50a7
SP		 700 struct be_dma_mem *mbox_mem = &adapter->mbox_mem;
701 struct be_mcc_wrb *wrb
702 = &((struct be_mcc_mailbox *)(mbox_mem->va))->wrb;
703 memset(wrb, 0, sizeof(*wrb));
704 return wrb;
6b7c5b94
SP		 705}
706
b31c50a7 707static struct be_mcc_wrb *wrb_from_mccq(struct be_adapter *adapter)
5fb379ee 708{
b31c50a7
SP		 709 struct be_queue_info *mccq = &adapter->mcc_obj.q;
710 struct be_mcc_wrb *wrb;
711
aa790db9
PR		 712 if (!mccq->created)
713 return NULL;
714
4d277125 715 if (atomic_read(&mccq->used) >= mccq->len)
713d0394 716 return NULL;
713d0394 717
b31c50a7
SP		 718 wrb = queue_head_node(mccq);
719 queue_head_inc(mccq);
720 atomic_inc(&mccq->used);
721 memset(wrb, 0, sizeof(*wrb));
5fb379ee
SP		 722 return wrb;
723}
724
bea50988
SP		 725static bool use_mcc(struct be_adapter *adapter)
726{
727 return adapter->mcc_obj.q.created;
728}
729
730/* Must be used only in process context */
731static int be_cmd_lock(struct be_adapter *adapter)
732{
733 if (use_mcc(adapter)) {
734 spin_lock_bh(&adapter->mcc_lock);
735 return 0;
736 } else {
737 return mutex_lock_interruptible(&adapter->mbox_lock);
738 }
739}
740
741/* Must be used only in process context */
742static void be_cmd_unlock(struct be_adapter *adapter)
743{
744 if (use_mcc(adapter))
745 spin_unlock_bh(&adapter->mcc_lock);
746 else
747 return mutex_unlock(&adapter->mbox_lock);
748}
749
750static struct be_mcc_wrb *be_cmd_copy(struct be_adapter *adapter,
751 struct be_mcc_wrb *wrb)
752{
753 struct be_mcc_wrb *dest_wrb;
754
755 if (use_mcc(adapter)) {
756 dest_wrb = wrb_from_mccq(adapter);
757 if (!dest_wrb)
758 return NULL;
759 } else {
760 dest_wrb = wrb_from_mbox(adapter);
761 }
762
763 memcpy(dest_wrb, wrb, sizeof(*wrb));
764 if (wrb->embedded & cpu_to_le32(MCC_WRB_EMBEDDED_MASK))
765 fill_wrb_tags(dest_wrb, (ulong) embedded_payload(wrb));
766
767 return dest_wrb;
768}
769
770/* Must be used only in process context */
771static int be_cmd_notify_wait(struct be_adapter *adapter,
772 struct be_mcc_wrb *wrb)
773{
774 struct be_mcc_wrb *dest_wrb;
775 int status;
776
777 status = be_cmd_lock(adapter);
778 if (status)
779 return status;
780
781 dest_wrb = be_cmd_copy(adapter, wrb);
782 if (!dest_wrb)
783 return -EBUSY;
784
785 if (use_mcc(adapter))
786 status = be_mcc_notify_wait(adapter);
787 else
788 status = be_mbox_notify_wait(adapter);
789
790 if (!status)
791 memcpy(wrb, dest_wrb, sizeof(*wrb));
792
793 be_cmd_unlock(adapter);
794 return status;
795}
796
2243e2e9
SP		 797/* Tell fw we're about to start firing cmds by writing a
798 * special pattern across the wrb hdr; uses mbox
799 */
800int be_cmd_fw_init(struct be_adapter *adapter)
801{
802 u8 *wrb;
803 int status;
804
bf99e50d
PR		 805 if (lancer_chip(adapter))
806 return 0;
807
2984961c
IV		 808 if (mutex_lock_interruptible(&adapter->mbox_lock))
809 return -1;
2243e2e9
SP		 810
811 wrb = (u8 *)wrb_from_mbox(adapter);
359a972f
SP		 812 *wrb++ = 0xFF;
813 *wrb++ = 0x12;
814 *wrb++ = 0x34;
815 *wrb++ = 0xFF;
816 *wrb++ = 0xFF;
817 *wrb++ = 0x56;
818 *wrb++ = 0x78;
819 *wrb = 0xFF;
2243e2e9
SP		 820
821 status = be_mbox_notify_wait(adapter);
822
2984961c 823 mutex_unlock(&adapter->mbox_lock);
2243e2e9
SP		 824 return status;
825}
826
827/* Tell fw we're done with firing cmds by writing a
828 * special pattern across the wrb hdr; uses mbox
829 */
830int be_cmd_fw_clean(struct be_adapter *adapter)
831{
832 u8 *wrb;
833 int status;
834
bf99e50d
PR		 835 if (lancer_chip(adapter))
836 return 0;
837
2984961c
IV		 838 if (mutex_lock_interruptible(&adapter->mbox_lock))
839 return -1;
2243e2e9
SP		 840
841 wrb = (u8 *)wrb_from_mbox(adapter);
842 *wrb++ = 0xFF;
843 *wrb++ = 0xAA;
844 *wrb++ = 0xBB;
845 *wrb++ = 0xFF;
846 *wrb++ = 0xFF;
847 *wrb++ = 0xCC;
848 *wrb++ = 0xDD;
849 *wrb = 0xFF;
850
851 status = be_mbox_notify_wait(adapter);
852
2984961c 853 mutex_unlock(&adapter->mbox_lock);
2243e2e9
SP		 854 return status;
855}
bf99e50d 856
f2f781a7 857int be_cmd_eq_create(struct be_adapter *adapter, struct be_eq_obj *eqo)
6b7c5b94 858{
b31c50a7
SP		 859 struct be_mcc_wrb *wrb;
860 struct be_cmd_req_eq_create *req;
f2f781a7
SP		 861 struct be_dma_mem *q_mem = &eqo->q.dma_mem;
862 int status, ver = 0;
6b7c5b94 863
2984961c
IV		 864 if (mutex_lock_interruptible(&adapter->mbox_lock))
865 return -1;
b31c50a7
SP		 866
867 wrb = wrb_from_mbox(adapter);
868 req = embedded_payload(wrb);
6b7c5b94 869
106df1e3
SK		 870 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
871 OPCODE_COMMON_EQ_CREATE, sizeof(*req), wrb, NULL);
6b7c5b94 872
f2f781a7
SP		 873 /* Support for EQ_CREATEv2 available only SH-R onwards */
874 if (!(BEx_chip(adapter) || lancer_chip(adapter)))
875 ver = 2;
876
877 req->hdr.version = ver;
6b7c5b94
SP		 878 req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
879
6b7c5b94
SP		 880 AMAP_SET_BITS(struct amap_eq_context, valid, req->context, 1);
881 /* 4byte eqe*/
882 AMAP_SET_BITS(struct amap_eq_context, size, req->context, 0);
883 AMAP_SET_BITS(struct amap_eq_context, count, req->context,
f2f781a7 884 __ilog2_u32(eqo->q.len / 256));
6b7c5b94
SP		 885 be_dws_cpu_to_le(req->context, sizeof(req->context));
886
887 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
888
b31c50a7 889 status = be_mbox_notify_wait(adapter);
6b7c5b94 890 if (!status) {
b31c50a7 891 struct be_cmd_resp_eq_create *resp = embedded_payload(wrb);
f2f781a7
SP		 892 eqo->q.id = le16_to_cpu(resp->eq_id);
893 eqo->msix_idx =
894 (ver == 2) ? le16_to_cpu(resp->msix_idx) : eqo->idx;
895 eqo->q.created = true;
6b7c5b94 896 }
b31c50a7 897
2984961c 898 mutex_unlock(&adapter->mbox_lock);
6b7c5b94
SP		 899 return status;
900}
901
f9449ab7 902/* Use MCC */
8788fdc2 903int be_cmd_mac_addr_query(struct be_adapter *adapter, u8 *mac_addr,
5ee4979b 904 bool permanent, u32 if_handle, u32 pmac_id)
6b7c5b94 905{
b31c50a7
SP		 906 struct be_mcc_wrb *wrb;
907 struct be_cmd_req_mac_query *req;
6b7c5b94
SP		 908 int status;
909
f9449ab7 910 spin_lock_bh(&adapter->mcc_lock);
b31c50a7 911
f9449ab7
SP		 912 wrb = wrb_from_mccq(adapter);
913 if (!wrb) {
914 status = -EBUSY;
915 goto err;
916 }
b31c50a7 917 req = embedded_payload(wrb);
6b7c5b94 918
106df1e3
SK		 919 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
920 OPCODE_COMMON_NTWK_MAC_QUERY, sizeof(*req), wrb, NULL);
5ee4979b 921 req->type = MAC_ADDRESS_TYPE_NETWORK;
6b7c5b94
SP		 922 if (permanent) {
923 req->permanent = 1;
924 } else {
b31c50a7 925 req->if_id = cpu_to_le16((u16) if_handle);
590c391d 926 req->pmac_id = cpu_to_le32(pmac_id);
6b7c5b94
SP		 927 req->permanent = 0;
928 }
929
f9449ab7 930 status = be_mcc_notify_wait(adapter);
b31c50a7
SP		 931 if (!status) {
932 struct be_cmd_resp_mac_query *resp = embedded_payload(wrb);
6b7c5b94 933 memcpy(mac_addr, resp->mac.addr, ETH_ALEN);
b31c50a7 934 }
6b7c5b94 935
f9449ab7
SP		 936err:
937 spin_unlock_bh(&adapter->mcc_lock);
6b7c5b94
SP		 938 return status;
939}
940
b31c50a7 941/* Uses synchronous MCCQ */
8788fdc2 942int be_cmd_pmac_add(struct be_adapter *adapter, u8 *mac_addr,
f8617e08 943 u32 if_id, u32 *pmac_id, u32 domain)
6b7c5b94 944{
b31c50a7
SP		 945 struct be_mcc_wrb *wrb;
946 struct be_cmd_req_pmac_add *req;
6b7c5b94
SP		 947 int status;
948
b31c50a7
SP		 949 spin_lock_bh(&adapter->mcc_lock);
950
951 wrb = wrb_from_mccq(adapter);
713d0394
SP		 952 if (!wrb) {
953 status = -EBUSY;
954 goto err;
955 }
b31c50a7 956 req = embedded_payload(wrb);
6b7c5b94 957
106df1e3
SK		 958 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
959 OPCODE_COMMON_NTWK_PMAC_ADD, sizeof(*req), wrb, NULL);
6b7c5b94 960
f8617e08 961 req->hdr.domain = domain;
6b7c5b94
SP		 962 req->if_id = cpu_to_le32(if_id);
963 memcpy(req->mac_address, mac_addr, ETH_ALEN);
964
b31c50a7 965 status = be_mcc_notify_wait(adapter);
6b7c5b94
SP		 966 if (!status) {
967 struct be_cmd_resp_pmac_add *resp = embedded_payload(wrb);
968 *pmac_id = le32_to_cpu(resp->pmac_id);
969 }
970
713d0394 971err:
b31c50a7 972 spin_unlock_bh(&adapter->mcc_lock);
e3a7ae2c
SK		 973
974 if (status == MCC_STATUS_UNAUTHORIZED_REQUEST)
975 status = -EPERM;
976
6b7c5b94
SP		 977 return status;
978}
979
b31c50a7 980/* Uses synchronous MCCQ */
30128031 981int be_cmd_pmac_del(struct be_adapter *adapter, u32 if_id, int pmac_id, u32 dom)
6b7c5b94 982{
b31c50a7
SP		 983 struct be_mcc_wrb *wrb;
984 struct be_cmd_req_pmac_del *req;
6b7c5b94
SP		 985 int status;
986
30128031
SP		 987 if (pmac_id == -1)
988 return 0;
989
b31c50a7
SP		 990 spin_lock_bh(&adapter->mcc_lock);
991
992 wrb = wrb_from_mccq(adapter);
713d0394
SP		 993 if (!wrb) {
994 status = -EBUSY;
995 goto err;
996 }
b31c50a7 997 req = embedded_payload(wrb);
6b7c5b94 998
106df1e3
SK		 999 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1000 OPCODE_COMMON_NTWK_PMAC_DEL, sizeof(*req), wrb, NULL);
6b7c5b94 1001
f8617e08 1002 req->hdr.domain = dom;
6b7c5b94
SP		 1003 req->if_id = cpu_to_le32(if_id);
1004 req->pmac_id = cpu_to_le32(pmac_id);
1005
b31c50a7
SP		 1006 status = be_mcc_notify_wait(adapter);
1007
713d0394 1008err:
b31c50a7 1009 spin_unlock_bh(&adapter->mcc_lock);
6b7c5b94
SP		 1010 return status;
1011}
1012
b31c50a7 1013/* Uses Mbox */
10ef9ab4
SP		 1014int be_cmd_cq_create(struct be_adapter *adapter, struct be_queue_info *cq,
1015 struct be_queue_info *eq, bool no_delay, int coalesce_wm)
6b7c5b94 1016{
b31c50a7
SP		 1017 struct be_mcc_wrb *wrb;
1018 struct be_cmd_req_cq_create *req;
6b7c5b94 1019 struct be_dma_mem *q_mem = &cq->dma_mem;
b31c50a7 1020 void *ctxt;
6b7c5b94
SP		 1021 int status;
1022
2984961c
IV		 1023 if (mutex_lock_interruptible(&adapter->mbox_lock))
1024 return -1;
b31c50a7
SP		 1025
1026 wrb = wrb_from_mbox(adapter);
1027 req = embedded_payload(wrb);
1028 ctxt = &req->context;
6b7c5b94 1029
106df1e3
SK		 1030 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1031 OPCODE_COMMON_CQ_CREATE, sizeof(*req), wrb, NULL);
6b7c5b94
SP		 1032
1033 req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
bbdc42f8
AK		 1034
1035 if (BEx_chip(adapter)) {
fe6d2a38
SP		 1036 AMAP_SET_BITS(struct amap_cq_context_be, coalescwm, ctxt,
1037 coalesce_wm);
1038 AMAP_SET_BITS(struct amap_cq_context_be, nodelay,
1039 ctxt, no_delay);
1040 AMAP_SET_BITS(struct amap_cq_context_be, count, ctxt,
1041 __ilog2_u32(cq->len/256));
1042 AMAP_SET_BITS(struct amap_cq_context_be, valid, ctxt, 1);
fe6d2a38
SP		 1043 AMAP_SET_BITS(struct amap_cq_context_be, eventable, ctxt, 1);
1044 AMAP_SET_BITS(struct amap_cq_context_be, eqid, ctxt, eq->id);
bbdc42f8
AK		 1045 } else {
1046 req->hdr.version = 2;
1047 req->page_size = 1; /* 1 for 4K */
09e83a9d
AK		 1048
1049 /* coalesce-wm field in this cmd is not relevant to Lancer.
1050 * Lancer uses COMMON_MODIFY_CQ to set this field
1051 */
1052 if (!lancer_chip(adapter))
1053 AMAP_SET_BITS(struct amap_cq_context_v2, coalescwm,
1054 ctxt, coalesce_wm);
bbdc42f8
AK		 1055 AMAP_SET_BITS(struct amap_cq_context_v2, nodelay, ctxt,
1056 no_delay);
1057 AMAP_SET_BITS(struct amap_cq_context_v2, count, ctxt,
1058 __ilog2_u32(cq->len/256));
1059 AMAP_SET_BITS(struct amap_cq_context_v2, valid, ctxt, 1);
1060 AMAP_SET_BITS(struct amap_cq_context_v2, eventable,
1061 ctxt, 1);
1062 AMAP_SET_BITS(struct amap_cq_context_v2, eqid,
1063 ctxt, eq->id);
fe6d2a38 1064 }
6b7c5b94 1065
6b7c5b94
SP		 1066 be_dws_cpu_to_le(ctxt, sizeof(req->context));
1067
1068 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
1069
b31c50a7 1070 status = be_mbox_notify_wait(adapter);
6b7c5b94 1071 if (!status) {
b31c50a7 1072 struct be_cmd_resp_cq_create *resp = embedded_payload(wrb);
6b7c5b94
SP		 1073 cq->id = le16_to_cpu(resp->cq_id);
1074 cq->created = true;
1075 }
b31c50a7 1076
2984961c 1077 mutex_unlock(&adapter->mbox_lock);
5fb379ee
SP		 1078
1079 return status;
1080}
1081
1082static u32 be_encoded_q_len(int q_len)
1083{
1084 u32 len_encoded = fls(q_len); /* log2(len) + 1 */
1085 if (len_encoded == 16)
1086 len_encoded = 0;
1087 return len_encoded;
1088}
1089
4188e7df
JH		 1090static int be_cmd_mccq_ext_create(struct be_adapter *adapter,
1091 struct be_queue_info *mccq,
1092 struct be_queue_info *cq)
5fb379ee 1093{
b31c50a7 1094 struct be_mcc_wrb *wrb;
34b1ef04 1095 struct be_cmd_req_mcc_ext_create *req;
5fb379ee 1096 struct be_dma_mem *q_mem = &mccq->dma_mem;
b31c50a7 1097 void *ctxt;
5fb379ee
SP		 1098 int status;
1099
2984961c
IV		 1100 if (mutex_lock_interruptible(&adapter->mbox_lock))
1101 return -1;
b31c50a7
SP		 1102
1103 wrb = wrb_from_mbox(adapter);
1104 req = embedded_payload(wrb);
1105 ctxt = &req->context;
5fb379ee 1106
106df1e3
SK		 1107 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1108 OPCODE_COMMON_MCC_CREATE_EXT, sizeof(*req), wrb, NULL);
5fb379ee 1109
d4a2ac3e 1110 req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
666d39c7 1111 if (BEx_chip(adapter)) {
fe6d2a38
SP		 1112 AMAP_SET_BITS(struct amap_mcc_context_be, valid, ctxt, 1);
1113 AMAP_SET_BITS(struct amap_mcc_context_be, ring_size, ctxt,
1114 be_encoded_q_len(mccq->len));
1115 AMAP_SET_BITS(struct amap_mcc_context_be, cq_id, ctxt, cq->id);
666d39c7
VV		 1116 } else {
1117 req->hdr.version = 1;
1118 req->cq_id = cpu_to_le16(cq->id);
1119
1120 AMAP_SET_BITS(struct amap_mcc_context_v1, ring_size, ctxt,
1121 be_encoded_q_len(mccq->len));
1122 AMAP_SET_BITS(struct amap_mcc_context_v1, valid, ctxt, 1);
1123 AMAP_SET_BITS(struct amap_mcc_context_v1, async_cq_id,
1124 ctxt, cq->id);
1125 AMAP_SET_BITS(struct amap_mcc_context_v1, async_cq_valid,
1126 ctxt, 1);
fe6d2a38 1127 }
5fb379ee 1128
cc4ce020 1129 /* Subscribe to Link State and Group 5 Events(bits 1 and 5 set) */
fe6d2a38 1130 req->async_event_bitmap[0] = cpu_to_le32(0x00000022);
bc0c3405 1131 req->async_event_bitmap[0] |= cpu_to_le32(1 << ASYNC_EVENT_CODE_QNQ);
5fb379ee
SP		 1132 be_dws_cpu_to_le(ctxt, sizeof(req->context));
1133
1134 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
1135
b31c50a7 1136 status = be_mbox_notify_wait(adapter);
5fb379ee
SP		 1137 if (!status) {
1138 struct be_cmd_resp_mcc_create *resp = embedded_payload(wrb);
1139 mccq->id = le16_to_cpu(resp->id);
1140 mccq->created = true;
1141 }
2984961c 1142 mutex_unlock(&adapter->mbox_lock);
6b7c5b94
SP		 1143
1144 return status;
1145}
1146
4188e7df
JH		 1147static int be_cmd_mccq_org_create(struct be_adapter *adapter,
1148 struct be_queue_info *mccq,
1149 struct be_queue_info *cq)
34b1ef04
SK		 1150{
1151 struct be_mcc_wrb *wrb;
1152 struct be_cmd_req_mcc_create *req;
1153 struct be_dma_mem *q_mem = &mccq->dma_mem;
1154 void *ctxt;
1155 int status;
1156
1157 if (mutex_lock_interruptible(&adapter->mbox_lock))
1158 return -1;
1159
1160 wrb = wrb_from_mbox(adapter);
1161 req = embedded_payload(wrb);
1162 ctxt = &req->context;
1163
106df1e3
SK		 1164 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1165 OPCODE_COMMON_MCC_CREATE, sizeof(*req), wrb, NULL);
34b1ef04
SK		 1166
1167 req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
1168
1169 AMAP_SET_BITS(struct amap_mcc_context_be, valid, ctxt, 1);
1170 AMAP_SET_BITS(struct amap_mcc_context_be, ring_size, ctxt,
1171 be_encoded_q_len(mccq->len));
1172 AMAP_SET_BITS(struct amap_mcc_context_be, cq_id, ctxt, cq->id);
1173
1174 be_dws_cpu_to_le(ctxt, sizeof(req->context));
1175
1176 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
1177
1178 status = be_mbox_notify_wait(adapter);
1179 if (!status) {
1180 struct be_cmd_resp_mcc_create *resp = embedded_payload(wrb);
1181 mccq->id = le16_to_cpu(resp->id);
1182 mccq->created = true;
1183 }
1184
1185 mutex_unlock(&adapter->mbox_lock);
1186 return status;
1187}
1188
1189int be_cmd_mccq_create(struct be_adapter *adapter,
1190 struct be_queue_info *mccq,
1191 struct be_queue_info *cq)
1192{
1193 int status;
1194
1195 status = be_cmd_mccq_ext_create(adapter, mccq, cq);
666d39c7 1196 if (status && BEx_chip(adapter)) {
34b1ef04
SK		 1197 dev_warn(&adapter->pdev->dev, "Upgrade to F/W ver 2.102.235.0 "
1198 "or newer to avoid conflicting priorities between NIC "
1199 "and FCoE traffic");
1200 status = be_cmd_mccq_org_create(adapter, mccq, cq);
1201 }
1202 return status;
1203}
1204
94d73aaa 1205int be_cmd_txq_create(struct be_adapter *adapter, struct be_tx_obj *txo)
6b7c5b94 1206{
7707133c 1207 struct be_mcc_wrb wrb = {0};
b31c50a7 1208 struct be_cmd_req_eth_tx_create *req;
94d73aaa
VV		 1209 struct be_queue_info *txq = &txo->q;
1210 struct be_queue_info *cq = &txo->cq;
6b7c5b94 1211 struct be_dma_mem *q_mem = &txq->dma_mem;
94d73aaa 1212 int status, ver = 0;
6b7c5b94 1213
7707133c 1214 req = embedded_payload(&wrb);
106df1e3 1215 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
7707133c 1216 OPCODE_ETH_TX_CREATE, sizeof(*req), &wrb, NULL);
6b7c5b94 1217
8b7756ca
PR		 1218 if (lancer_chip(adapter)) {
1219 req->hdr.version = 1;
94d73aaa
VV		 1220 } else if (BEx_chip(adapter)) {
1221 if (adapter->function_caps & BE_FUNCTION_CAPS_SUPER_NIC)
1222 req->hdr.version = 2;
1223 } else { /* For SH */
1224 req->hdr.version = 2;
8b7756ca
PR		 1225 }
1226
81b02655
VV		 1227 if (req->hdr.version > 0)
1228 req->if_id = cpu_to_le16(adapter->if_handle);
6b7c5b94
SP		 1229 req->num_pages = PAGES_4K_SPANNED(q_mem->va, q_mem->size);
1230 req->ulp_num = BE_ULP1_NUM;
1231 req->type = BE_ETH_TX_RING_TYPE_STANDARD;
94d73aaa
VV		 1232 req->cq_id = cpu_to_le16(cq->id);
1233 req->queue_size = be_encoded_q_len(txq->len);
6b7c5b94 1234 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
94d73aaa
VV		 1235 ver = req->hdr.version;
1236
7707133c 1237 status = be_cmd_notify_wait(adapter, &wrb);
6b7c5b94 1238 if (!status) {
7707133c 1239 struct be_cmd_resp_eth_tx_create *resp = embedded_payload(&wrb);
6b7c5b94 1240 txq->id = le16_to_cpu(resp->cid);
94d73aaa
VV		 1241 if (ver == 2)
1242 txo->db_offset = le32_to_cpu(resp->db_offset);
1243 else
1244 txo->db_offset = DB_TXULP1_OFFSET;
6b7c5b94
SP		 1245 txq->created = true;
1246 }
b31c50a7 1247
6b7c5b94
SP		 1248 return status;
1249}
1250
482c9e79 1251/* Uses MCC */
8788fdc2 1252int be_cmd_rxq_create(struct be_adapter *adapter,
6b7c5b94 1253 struct be_queue_info *rxq, u16 cq_id, u16 frag_size,
10ef9ab4 1254 u32 if_id, u32 rss, u8 *rss_id)
6b7c5b94 1255{
b31c50a7
SP		 1256 struct be_mcc_wrb *wrb;
1257 struct be_cmd_req_eth_rx_create *req;
6b7c5b94
SP		 1258 struct be_dma_mem *q_mem = &rxq->dma_mem;
1259 int status;
1260
482c9e79 1261 spin_lock_bh(&adapter->mcc_lock);
b31c50a7 1262
482c9e79
SP		 1263 wrb = wrb_from_mccq(adapter);
1264 if (!wrb) {
1265 status = -EBUSY;
1266 goto err;
1267 }
b31c50a7 1268 req = embedded_payload(wrb);
6b7c5b94 1269
106df1e3
SK		 1270 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1271 OPCODE_ETH_RX_CREATE, sizeof(*req), wrb, NULL);
6b7c5b94
SP		 1272
1273 req->cq_id = cpu_to_le16(cq_id);
1274 req->frag_size = fls(frag_size) - 1;
1275 req->num_pages = 2;
1276 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
1277 req->interface_id = cpu_to_le32(if_id);
10ef9ab4 1278 req->max_frame_size = cpu_to_le16(BE_MAX_JUMBO_FRAME_SIZE);
6b7c5b94
SP		 1279 req->rss_queue = cpu_to_le32(rss);
1280
482c9e79 1281 status = be_mcc_notify_wait(adapter);
6b7c5b94
SP		 1282 if (!status) {
1283 struct be_cmd_resp_eth_rx_create *resp = embedded_payload(wrb);
1284 rxq->id = le16_to_cpu(resp->id);
1285 rxq->created = true;
3abcdeda 1286 *rss_id = resp->rss_id;
6b7c5b94 1287 }
b31c50a7 1288
482c9e79
SP		 1289err:
1290 spin_unlock_bh(&adapter->mcc_lock);
6b7c5b94
SP		 1291 return status;
1292}
1293
b31c50a7
SP		 1294/* Generic destroyer function for all types of queues
1295 * Uses Mbox
1296 */
8788fdc2 1297int be_cmd_q_destroy(struct be_adapter *adapter, struct be_queue_info *q,
6b7c5b94
SP		 1298 int queue_type)
1299{
b31c50a7
SP		 1300 struct be_mcc_wrb *wrb;
1301 struct be_cmd_req_q_destroy *req;
6b7c5b94
SP		 1302 u8 subsys = 0, opcode = 0;
1303 int status;
1304
2984961c
IV		 1305 if (mutex_lock_interruptible(&adapter->mbox_lock))
1306 return -1;
6b7c5b94 1307
b31c50a7
SP		 1308 wrb = wrb_from_mbox(adapter);
1309 req = embedded_payload(wrb);
1310
6b7c5b94
SP		 1311 switch (queue_type) {
1312 case QTYPE_EQ:
1313 subsys = CMD_SUBSYSTEM_COMMON;
1314 opcode = OPCODE_COMMON_EQ_DESTROY;
1315 break;
1316 case QTYPE_CQ:
1317 subsys = CMD_SUBSYSTEM_COMMON;
1318 opcode = OPCODE_COMMON_CQ_DESTROY;
1319 break;
1320 case QTYPE_TXQ:
1321 subsys = CMD_SUBSYSTEM_ETH;
1322 opcode = OPCODE_ETH_TX_DESTROY;
1323 break;
1324 case QTYPE_RXQ:
1325 subsys = CMD_SUBSYSTEM_ETH;
1326 opcode = OPCODE_ETH_RX_DESTROY;
1327 break;
5fb379ee
SP		 1328 case QTYPE_MCCQ:
1329 subsys = CMD_SUBSYSTEM_COMMON;
1330 opcode = OPCODE_COMMON_MCC_DESTROY;
1331 break;
6b7c5b94 1332 default:
5f0b849e 1333 BUG();
6b7c5b94 1334 }
d744b44e 1335
106df1e3
SK		 1336 be_wrb_cmd_hdr_prepare(&req->hdr, subsys, opcode, sizeof(*req), wrb,
1337 NULL);
6b7c5b94
SP		 1338 req->id = cpu_to_le16(q->id);
1339
b31c50a7 1340 status = be_mbox_notify_wait(adapter);
aa790db9 1341 q->created = false;
5f0b849e 1342
2984961c 1343 mutex_unlock(&adapter->mbox_lock);
482c9e79
SP		 1344 return status;
1345}
6b7c5b94 1346
482c9e79
SP		 1347/* Uses MCC */
1348int be_cmd_rxq_destroy(struct be_adapter *adapter, struct be_queue_info *q)
1349{
1350 struct be_mcc_wrb *wrb;
1351 struct be_cmd_req_q_destroy *req;
1352 int status;
1353
1354 spin_lock_bh(&adapter->mcc_lock);
1355
1356 wrb = wrb_from_mccq(adapter);
1357 if (!wrb) {
1358 status = -EBUSY;
1359 goto err;
1360 }
1361 req = embedded_payload(wrb);
1362
106df1e3
SK		 1363 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1364 OPCODE_ETH_RX_DESTROY, sizeof(*req), wrb, NULL);
482c9e79
SP		 1365 req->id = cpu_to_le16(q->id);
1366
1367 status = be_mcc_notify_wait(adapter);
aa790db9 1368 q->created = false;
482c9e79
SP		 1369
1370err:
1371 spin_unlock_bh(&adapter->mcc_lock);
6b7c5b94
SP		 1372 return status;
1373}
1374
b31c50a7 1375/* Create an rx filtering policy configuration on an i/f
bea50988 1376 * Will use MBOX only if MCCQ has not been created.
b31c50a7 1377 */
73d540f2 1378int be_cmd_if_create(struct be_adapter *adapter, u32 cap_flags, u32 en_flags,
1578e777 1379 u32 *if_handle, u32 domain)
6b7c5b94 1380{
bea50988 1381 struct be_mcc_wrb wrb = {0};
b31c50a7 1382 struct be_cmd_req_if_create *req;
6b7c5b94
SP		 1383 int status;
1384
bea50988 1385 req = embedded_payload(&wrb);
106df1e3 1386 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
bea50988 1387 OPCODE_COMMON_NTWK_INTERFACE_CREATE, sizeof(*req), &wrb, NULL);
ba343c77 1388 req->hdr.domain = domain;
73d540f2
SP		 1389 req->capability_flags = cpu_to_le32(cap_flags);
1390 req->enable_flags = cpu_to_le32(en_flags);
1578e777 1391 req->pmac_invalid = true;
6b7c5b94 1392
bea50988 1393 status = be_cmd_notify_wait(adapter, &wrb);
6b7c5b94 1394 if (!status) {
bea50988 1395 struct be_cmd_resp_if_create *resp = embedded_payload(&wrb);
6b7c5b94 1396 *if_handle = le32_to_cpu(resp->interface_id);
b5bb9776
SP		 1397
1398 /* Hack to retrieve VF's pmac-id on BE3 */
1399 if (BE3_chip(adapter) && !be_physfn(adapter))
1400 adapter->pmac_id[0] = le32_to_cpu(resp->pmac_id);
6b7c5b94 1401 }
6b7c5b94
SP		 1402 return status;
1403}
1404
f9449ab7 1405/* Uses MCCQ */
30128031 1406int be_cmd_if_destroy(struct be_adapter *adapter, int interface_id, u32 domain)
6b7c5b94 1407{
b31c50a7
SP		 1408 struct be_mcc_wrb *wrb;
1409 struct be_cmd_req_if_destroy *req;
6b7c5b94
SP		 1410 int status;
1411
30128031 1412 if (interface_id == -1)
f9449ab7 1413 return 0;
b31c50a7 1414
f9449ab7
SP		 1415 spin_lock_bh(&adapter->mcc_lock);
1416
1417 wrb = wrb_from_mccq(adapter);
1418 if (!wrb) {
1419 status = -EBUSY;
1420 goto err;
1421 }
b31c50a7 1422 req = embedded_payload(wrb);
6b7c5b94 1423
106df1e3
SK		 1424 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1425 OPCODE_COMMON_NTWK_INTERFACE_DESTROY, sizeof(*req), wrb, NULL);
658681f7 1426 req->hdr.domain = domain;
6b7c5b94 1427 req->interface_id = cpu_to_le32(interface_id);
b31c50a7 1428
f9449ab7
SP		 1429 status = be_mcc_notify_wait(adapter);
1430err:
1431 spin_unlock_bh(&adapter->mcc_lock);
6b7c5b94
SP		 1432 return status;
1433}
1434
1435/* Get stats is a non embedded command: the request is not embedded inside
1436 * WRB but is a separate dma memory block
b31c50a7 1437 * Uses asynchronous MCC
6b7c5b94 1438 */
8788fdc2 1439int be_cmd_get_stats(struct be_adapter *adapter, struct be_dma_mem *nonemb_cmd)
6b7c5b94 1440{
b31c50a7 1441 struct be_mcc_wrb *wrb;
89a88ab8 1442 struct be_cmd_req_hdr *hdr;
713d0394 1443 int status = 0;
6b7c5b94 1444
b31c50a7 1445 spin_lock_bh(&adapter->mcc_lock);
6b7c5b94 1446
b31c50a7 1447 wrb = wrb_from_mccq(adapter);
713d0394
SP		 1448 if (!wrb) {
1449 status = -EBUSY;
1450 goto err;
1451 }
89a88ab8 1452 hdr = nonemb_cmd->va;
6b7c5b94 1453
106df1e3
SK		 1454 be_wrb_cmd_hdr_prepare(hdr, CMD_SUBSYSTEM_ETH,
1455 OPCODE_ETH_GET_STATISTICS, nonemb_cmd->size, wrb, nonemb_cmd);
89a88ab8 1456
ca34fe38 1457 /* version 1 of the cmd is not supported only by BE2 */
61000861
AK		 1458 if (BE2_chip(adapter))
1459 hdr->version = 0;
1460 if (BE3_chip(adapter) || lancer_chip(adapter))
89a88ab8 1461 hdr->version = 1;
61000861
AK		 1462 else
1463 hdr->version = 2;
89a88ab8 1464
b31c50a7 1465 be_mcc_notify(adapter);
b2aebe6d 1466 adapter->stats_cmd_sent = true;
6b7c5b94 1467
713d0394 1468err:
b31c50a7 1469 spin_unlock_bh(&adapter->mcc_lock);
713d0394 1470 return status;
6b7c5b94
SP		 1471}
1472
005d5696
SX		 1473/* Lancer Stats */
1474int lancer_cmd_get_pport_stats(struct be_adapter *adapter,
1475 struct be_dma_mem *nonemb_cmd)
1476{
1477
1478 struct be_mcc_wrb *wrb;
1479 struct lancer_cmd_req_pport_stats *req;
005d5696
SX		 1480 int status = 0;
1481
f25b119c
PR		 1482 if (!be_cmd_allowed(adapter, OPCODE_ETH_GET_PPORT_STATS,
1483 CMD_SUBSYSTEM_ETH))
1484 return -EPERM;
1485
005d5696
SX		 1486 spin_lock_bh(&adapter->mcc_lock);
1487
1488 wrb = wrb_from_mccq(adapter);
1489 if (!wrb) {
1490 status = -EBUSY;
1491 goto err;
1492 }
1493 req = nonemb_cmd->va;
005d5696 1494
106df1e3
SK		 1495 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1496 OPCODE_ETH_GET_PPORT_STATS, nonemb_cmd->size, wrb,
1497 nonemb_cmd);
005d5696 1498
d51ebd33 1499 req->cmd_params.params.pport_num = cpu_to_le16(adapter->hba_port_num);
005d5696
SX		 1500 req->cmd_params.params.reset_stats = 0;
1501
005d5696
SX		 1502 be_mcc_notify(adapter);
1503 adapter->stats_cmd_sent = true;
1504
1505err:
1506 spin_unlock_bh(&adapter->mcc_lock);
1507 return status;
1508}
1509
323ff71e
SP		 1510static int be_mac_to_link_speed(int mac_speed)
1511{
1512 switch (mac_speed) {
1513 case PHY_LINK_SPEED_ZERO:
1514 return 0;
1515 case PHY_LINK_SPEED_10MBPS:
1516 return 10;
1517 case PHY_LINK_SPEED_100MBPS:
1518 return 100;
1519 case PHY_LINK_SPEED_1GBPS:
1520 return 1000;
1521 case PHY_LINK_SPEED_10GBPS:
1522 return 10000;
b971f847
VV		 1523 case PHY_LINK_SPEED_20GBPS:
1524 return 20000;
1525 case PHY_LINK_SPEED_25GBPS:
1526 return 25000;
1527 case PHY_LINK_SPEED_40GBPS:
1528 return 40000;
323ff71e
SP		 1529 }
1530 return 0;
1531}
1532
1533/* Uses synchronous mcc
1534 * Returns link_speed in Mbps
1535 */
1536int be_cmd_link_status_query(struct be_adapter *adapter, u16 *link_speed,
1537 u8 *link_status, u32 dom)
6b7c5b94 1538{
b31c50a7
SP		 1539 struct be_mcc_wrb *wrb;
1540 struct be_cmd_req_link_status *req;
6b7c5b94
SP		 1541 int status;
1542
b31c50a7
SP		 1543 spin_lock_bh(&adapter->mcc_lock);
1544
b236916a
AK		 1545 if (link_status)
1546 *link_status = LINK_DOWN;
1547
b31c50a7 1548 wrb = wrb_from_mccq(adapter);
713d0394
SP		 1549 if (!wrb) {
1550 status = -EBUSY;
1551 goto err;
1552 }
b31c50a7 1553 req = embedded_payload(wrb);
a8f447bd 1554
57cd80d4
PR		 1555 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1556 OPCODE_COMMON_NTWK_LINK_STATUS_QUERY, sizeof(*req), wrb, NULL);
1557
ca34fe38
SP		 1558 /* version 1 of the cmd is not supported only by BE2 */
1559 if (!BE2_chip(adapter))
daad6167
PR		 1560 req->hdr.version = 1;
1561
57cd80d4 1562 req->hdr.domain = dom;
6b7c5b94 1563
b31c50a7 1564 status = be_mcc_notify_wait(adapter);
6b7c5b94
SP		 1565 if (!status) {
1566 struct be_cmd_resp_link_status *resp = embedded_payload(wrb);
323ff71e
SP		 1567 if (link_speed) {
1568 *link_speed = resp->link_speed ?
1569 le16_to_cpu(resp->link_speed) * 10 :
1570 be_mac_to_link_speed(resp->mac_speed);
1571
1572 if (!resp->logical_link_status)
1573 *link_speed = 0;
0388f251 1574 }
b236916a
AK		 1575 if (link_status)
1576 *link_status = resp->logical_link_status;
6b7c5b94
SP		 1577 }
1578
713d0394 1579err:
b31c50a7 1580 spin_unlock_bh(&adapter->mcc_lock);
6b7c5b94
SP		 1581 return status;
1582}
1583
609ff3bb
AK		 1584/* Uses synchronous mcc */
1585int be_cmd_get_die_temperature(struct be_adapter *adapter)
1586{
1587 struct be_mcc_wrb *wrb;
1588 struct be_cmd_req_get_cntl_addnl_attribs *req;
117affe3 1589 int status = 0;
609ff3bb
AK		 1590
1591 spin_lock_bh(&adapter->mcc_lock);
1592
1593 wrb = wrb_from_mccq(adapter);
1594 if (!wrb) {
1595 status = -EBUSY;
1596 goto err;
1597 }
1598 req = embedded_payload(wrb);
1599
106df1e3
SK		 1600 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1601 OPCODE_COMMON_GET_CNTL_ADDITIONAL_ATTRIBUTES, sizeof(*req),
1602 wrb, NULL);
609ff3bb 1603
3de09455 1604 be_mcc_notify(adapter);
609ff3bb
AK		 1605
1606err:
1607 spin_unlock_bh(&adapter->mcc_lock);
1608 return status;
1609}
1610
311fddc7
SK		 1611/* Uses synchronous mcc */
1612int be_cmd_get_reg_len(struct be_adapter *adapter, u32 *log_size)
1613{
1614 struct be_mcc_wrb *wrb;
1615 struct be_cmd_req_get_fat *req;
1616 int status;
1617
1618 spin_lock_bh(&adapter->mcc_lock);
1619
1620 wrb = wrb_from_mccq(adapter);
1621 if (!wrb) {
1622 status = -EBUSY;
1623 goto err;
1624 }
1625 req = embedded_payload(wrb);
1626
106df1e3
SK		 1627 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1628 OPCODE_COMMON_MANAGE_FAT, sizeof(*req), wrb, NULL);
311fddc7
SK		 1629 req->fat_operation = cpu_to_le32(QUERY_FAT);
1630 status = be_mcc_notify_wait(adapter);
1631 if (!status) {
1632 struct be_cmd_resp_get_fat *resp = embedded_payload(wrb);
1633 if (log_size && resp->log_size)
fe2a70ee
SK		 1634 *log_size = le32_to_cpu(resp->log_size) -
1635 sizeof(u32);
311fddc7
SK		 1636 }
1637err:
1638 spin_unlock_bh(&adapter->mcc_lock);
1639 return status;
1640}
1641
1642void be_cmd_get_regs(struct be_adapter *adapter, u32 buf_len, void *buf)
1643{
1644 struct be_dma_mem get_fat_cmd;
1645 struct be_mcc_wrb *wrb;
1646 struct be_cmd_req_get_fat *req;
fe2a70ee
SK		 1647 u32 offset = 0, total_size, buf_size,
1648 log_offset = sizeof(u32), payload_len;
311fddc7
SK		 1649 int status;
1650
1651 if (buf_len == 0)
1652 return;
1653
1654 total_size = buf_len;
1655
fe2a70ee
SK		 1656 get_fat_cmd.size = sizeof(struct be_cmd_req_get_fat) + 60*1024;
1657 get_fat_cmd.va = pci_alloc_consistent(adapter->pdev,
1658 get_fat_cmd.size,
1659 &get_fat_cmd.dma);
1660 if (!get_fat_cmd.va) {
1661 status = -ENOMEM;
1662 dev_err(&adapter->pdev->dev,
1663 "Memory allocation failure while retrieving FAT data\n");
1664 return;
1665 }
1666
311fddc7
SK		 1667 spin_lock_bh(&adapter->mcc_lock);
1668
311fddc7
SK		 1669 while (total_size) {
1670 buf_size = min(total_size, (u32)60*1024);
1671 total_size -= buf_size;
1672
fe2a70ee
SK		 1673 wrb = wrb_from_mccq(adapter);
1674 if (!wrb) {
1675 status = -EBUSY;
311fddc7
SK		 1676 goto err;
1677 }
1678 req = get_fat_cmd.va;
311fddc7 1679
fe2a70ee 1680 payload_len = sizeof(struct be_cmd_req_get_fat) + buf_size;
106df1e3
SK		 1681 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1682 OPCODE_COMMON_MANAGE_FAT, payload_len, wrb,
1683 &get_fat_cmd);
311fddc7
SK		 1684
1685 req->fat_operation = cpu_to_le32(RETRIEVE_FAT);
1686 req->read_log_offset = cpu_to_le32(log_offset);
1687 req->read_log_length = cpu_to_le32(buf_size);
1688 req->data_buffer_size = cpu_to_le32(buf_size);
1689
1690 status = be_mcc_notify_wait(adapter);
1691 if (!status) {
1692 struct be_cmd_resp_get_fat *resp = get_fat_cmd.va;
1693 memcpy(buf + offset,
1694 resp->data_buffer,
92aa9214 1695 le32_to_cpu(resp->read_log_length));
fe2a70ee 1696 } else {
311fddc7 1697 dev_err(&adapter->pdev->dev, "FAT Table Retrieve error\n");
fe2a70ee
SK		 1698 goto err;
1699 }
311fddc7
SK		 1700 offset += buf_size;
1701 log_offset += buf_size;
1702 }
1703err:
fe2a70ee
SK		 1704 pci_free_consistent(adapter->pdev, get_fat_cmd.size,
1705 get_fat_cmd.va,
1706 get_fat_cmd.dma);
311fddc7
SK		 1707 spin_unlock_bh(&adapter->mcc_lock);
1708}
1709
04b71175
SP		 1710/* Uses synchronous mcc */
1711int be_cmd_get_fw_ver(struct be_adapter *adapter, char *fw_ver,
1712 char *fw_on_flash)
6b7c5b94 1713{
b31c50a7
SP		 1714 struct be_mcc_wrb *wrb;
1715 struct be_cmd_req_get_fw_version *req;
6b7c5b94
SP		 1716 int status;
1717
04b71175 1718 spin_lock_bh(&adapter->mcc_lock);
b31c50a7 1719
04b71175
SP		 1720 wrb = wrb_from_mccq(adapter);
1721 if (!wrb) {
1722 status = -EBUSY;
1723 goto err;
1724 }
6b7c5b94 1725
04b71175 1726 req = embedded_payload(wrb);
6b7c5b94 1727
106df1e3
SK		 1728 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1729 OPCODE_COMMON_GET_FW_VERSION, sizeof(*req), wrb, NULL);
04b71175 1730 status = be_mcc_notify_wait(adapter);
6b7c5b94
SP		 1731 if (!status) {
1732 struct be_cmd_resp_get_fw_version *resp = embedded_payload(wrb);
04b71175
SP		 1733 strcpy(fw_ver, resp->firmware_version_string);
1734 if (fw_on_flash)
1735 strcpy(fw_on_flash, resp->fw_on_flash_version_string);
6b7c5b94 1736 }
04b71175
SP		 1737err:
1738 spin_unlock_bh(&adapter->mcc_lock);
6b7c5b94
SP		 1739 return status;
1740}
1741
b31c50a7
SP		 1742/* set the EQ delay interval of an EQ to specified value
1743 * Uses async mcc
1744 */
2632bafd
SP		 1745int be_cmd_modify_eqd(struct be_adapter *adapter, struct be_set_eqd *set_eqd,
1746 int num)
6b7c5b94 1747{
b31c50a7
SP		 1748 struct be_mcc_wrb *wrb;
1749 struct be_cmd_req_modify_eq_delay *req;
2632bafd 1750 int status = 0, i;
6b7c5b94 1751
b31c50a7
SP		 1752 spin_lock_bh(&adapter->mcc_lock);
1753
1754 wrb = wrb_from_mccq(adapter);
713d0394
SP		 1755 if (!wrb) {
1756 status = -EBUSY;
1757 goto err;
1758 }
b31c50a7 1759 req = embedded_payload(wrb);
6b7c5b94 1760
106df1e3
SK		 1761 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1762 OPCODE_COMMON_MODIFY_EQ_DELAY, sizeof(*req), wrb, NULL);
6b7c5b94 1763
2632bafd
SP		 1764 req->num_eq = cpu_to_le32(num);
1765 for (i = 0; i < num; i++) {
1766 req->set_eqd[i].eq_id = cpu_to_le32(set_eqd[i].eq_id);
1767 req->set_eqd[i].phase = 0;
1768 req->set_eqd[i].delay_multiplier =
1769 cpu_to_le32(set_eqd[i].delay_multiplier);
1770 }
6b7c5b94 1771
b31c50a7 1772 be_mcc_notify(adapter);
713d0394 1773err:
b31c50a7 1774 spin_unlock_bh(&adapter->mcc_lock);
713d0394 1775 return status;
6b7c5b94
SP		 1776}
1777
b31c50a7 1778/* Uses sycnhronous mcc */
8788fdc2 1779int be_cmd_vlan_config(struct be_adapter *adapter, u32 if_id, u16 *vtag_array,
012bd387 1780 u32 num, bool promiscuous)
6b7c5b94 1781{
b31c50a7
SP		 1782 struct be_mcc_wrb *wrb;
1783 struct be_cmd_req_vlan_config *req;
6b7c5b94
SP		 1784 int status;
1785
b31c50a7
SP		 1786 spin_lock_bh(&adapter->mcc_lock);
1787
1788 wrb = wrb_from_mccq(adapter);
713d0394
SP		 1789 if (!wrb) {
1790 status = -EBUSY;
1791 goto err;
1792 }
b31c50a7 1793 req = embedded_payload(wrb);
6b7c5b94 1794
106df1e3
SK		 1795 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1796 OPCODE_COMMON_NTWK_VLAN_CONFIG, sizeof(*req), wrb, NULL);
6b7c5b94
SP		 1797
1798 req->interface_id = if_id;
1799 req->promiscuous = promiscuous;
012bd387 1800 req->untagged = BE_IF_FLAGS_UNTAGGED & be_if_cap_flags(adapter) ? 1 : 0;
6b7c5b94
SP		 1801 req->num_vlan = num;
1802 if (!promiscuous) {
1803 memcpy(req->normal_vlan, vtag_array,
1804 req->num_vlan * sizeof(vtag_array[0]));
1805 }
1806
b31c50a7 1807 status = be_mcc_notify_wait(adapter);
6b7c5b94 1808
713d0394 1809err:
b31c50a7 1810 spin_unlock_bh(&adapter->mcc_lock);
6b7c5b94
SP		 1811 return status;
1812}
1813
5b8821b7 1814int be_cmd_rx_filter(struct be_adapter *adapter, u32 flags, u32 value)
6b7c5b94 1815{
6ac7b687 1816 struct be_mcc_wrb *wrb;
5b8821b7
SP		 1817 struct be_dma_mem *mem = &adapter->rx_filter;
1818 struct be_cmd_req_rx_filter *req = mem->va;
e7b909a6 1819 int status;
6b7c5b94 1820
8788fdc2 1821 spin_lock_bh(&adapter->mcc_lock);
6ac7b687 1822
b31c50a7 1823 wrb = wrb_from_mccq(adapter);
713d0394
SP		 1824 if (!wrb) {
1825 status = -EBUSY;
1826 goto err;
1827 }
5b8821b7 1828 memset(req, 0, sizeof(*req));
106df1e3
SK		 1829 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1830 OPCODE_COMMON_NTWK_RX_FILTER, sizeof(*req),
1831 wrb, mem);
6b7c5b94 1832
5b8821b7
SP		 1833 req->if_id = cpu_to_le32(adapter->if_handle);
1834 if (flags & IFF_PROMISC) {
1835 req->if_flags_mask = cpu_to_le32(BE_IF_FLAGS_PROMISCUOUS |
c5dae588
AK		 1836 BE_IF_FLAGS_VLAN_PROMISCUOUS |
1837 BE_IF_FLAGS_MCAST_PROMISCUOUS);
5b8821b7
SP		 1838 if (value == ON)
1839 req->if_flags = cpu_to_le32(BE_IF_FLAGS_PROMISCUOUS |
c5dae588
AK		 1840 BE_IF_FLAGS_VLAN_PROMISCUOUS |
1841 BE_IF_FLAGS_MCAST_PROMISCUOUS);
5b8821b7
SP		 1842 } else if (flags & IFF_ALLMULTI) {
1843 req->if_flags_mask = req->if_flags =
8e7d3f68 1844 cpu_to_le32(BE_IF_FLAGS_MCAST_PROMISCUOUS);
d9d604f8
AK		 1845 } else if (flags & BE_FLAGS_VLAN_PROMISC) {
1846 req->if_flags_mask = cpu_to_le32(BE_IF_FLAGS_VLAN_PROMISCUOUS);
1847
1848 if (value == ON)
1849 req->if_flags =
1850 cpu_to_le32(BE_IF_FLAGS_VLAN_PROMISCUOUS);
5b8821b7 1851 } else {
22bedad3 1852 struct netdev_hw_addr *ha;
5b8821b7 1853 int i = 0;
24307eef 1854
8e7d3f68
SP		 1855 req->if_flags_mask = req->if_flags =
1856 cpu_to_le32(BE_IF_FLAGS_MULTICAST);
1610c79f
PR		 1857
1858 /* Reset mcast promisc mode if already set by setting mask
1859 * and not setting flags field
1860 */
abb93951
PR		 1861 req->if_flags_mask |=
1862 cpu_to_le32(BE_IF_FLAGS_MCAST_PROMISCUOUS &
92bf14ab 1863 be_if_cap_flags(adapter));
016f97b1 1864 req->mcast_num = cpu_to_le32(netdev_mc_count(adapter->netdev));
5b8821b7
SP		 1865 netdev_for_each_mc_addr(ha, adapter->netdev)
1866 memcpy(req->mcast_mac[i++].byte, ha->addr, ETH_ALEN);
6b7c5b94
SP		 1867 }
1868
012bd387
AK		 1869 if ((req->if_flags_mask & cpu_to_le32(be_if_cap_flags(adapter))) !=
1870 req->if_flags_mask) {
1871 dev_warn(&adapter->pdev->dev,
1872 "Cannot set rx filter flags 0x%x\n",
1873 req->if_flags_mask);
1874 dev_warn(&adapter->pdev->dev,
1875 "Interface is capable of 0x%x flags only\n",
1876 be_if_cap_flags(adapter));
1877 }
1878 req->if_flags_mask &= cpu_to_le32(be_if_cap_flags(adapter));
1879
0d1d5875 1880 status = be_mcc_notify_wait(adapter);
012bd387 1881
713d0394 1882err:
8788fdc2 1883 spin_unlock_bh(&adapter->mcc_lock);
e7b909a6 1884 return status;
6b7c5b94
SP		 1885}
1886
b31c50a7 1887/* Uses synchrounous mcc */
8788fdc2 1888int be_cmd_set_flow_control(struct be_adapter *adapter, u32 tx_fc, u32 rx_fc)
6b7c5b94 1889{
b31c50a7
SP		 1890 struct be_mcc_wrb *wrb;
1891 struct be_cmd_req_set_flow_control *req;
6b7c5b94
SP		 1892 int status;
1893
f25b119c
PR		 1894 if (!be_cmd_allowed(adapter, OPCODE_COMMON_SET_FLOW_CONTROL,
1895 CMD_SUBSYSTEM_COMMON))
1896 return -EPERM;
1897
b31c50a7 1898 spin_lock_bh(&adapter->mcc_lock);
6b7c5b94 1899
b31c50a7 1900 wrb = wrb_from_mccq(adapter);
713d0394
SP		 1901 if (!wrb) {
1902 status = -EBUSY;
1903 goto err;
1904 }
b31c50a7 1905 req = embedded_payload(wrb);
6b7c5b94 1906
106df1e3
SK		 1907 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1908 OPCODE_COMMON_SET_FLOW_CONTROL, sizeof(*req), wrb, NULL);
6b7c5b94
SP		 1909
1910 req->tx_flow_control = cpu_to_le16((u16)tx_fc);
1911 req->rx_flow_control = cpu_to_le16((u16)rx_fc);
1912
b31c50a7 1913 status = be_mcc_notify_wait(adapter);
6b7c5b94 1914
713d0394 1915err:
b31c50a7 1916 spin_unlock_bh(&adapter->mcc_lock);
6b7c5b94
SP		 1917 return status;
1918}
1919
b31c50a7 1920/* Uses sycn mcc */
8788fdc2 1921int be_cmd_get_flow_control(struct be_adapter *adapter, u32 *tx_fc, u32 *rx_fc)
6b7c5b94 1922{
b31c50a7
SP		 1923 struct be_mcc_wrb *wrb;
1924 struct be_cmd_req_get_flow_control *req;
6b7c5b94
SP		 1925 int status;
1926
f25b119c
PR		 1927 if (!be_cmd_allowed(adapter, OPCODE_COMMON_GET_FLOW_CONTROL,
1928 CMD_SUBSYSTEM_COMMON))
1929 return -EPERM;
1930
b31c50a7 1931 spin_lock_bh(&adapter->mcc_lock);
6b7c5b94 1932
b31c50a7 1933 wrb = wrb_from_mccq(adapter);
713d0394
SP		 1934 if (!wrb) {
1935 status = -EBUSY;
1936 goto err;
1937 }
b31c50a7 1938 req = embedded_payload(wrb);
6b7c5b94 1939
106df1e3
SK		 1940 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1941 OPCODE_COMMON_GET_FLOW_CONTROL, sizeof(*req), wrb, NULL);
6b7c5b94 1942
b31c50a7 1943 status = be_mcc_notify_wait(adapter);
6b7c5b94
SP		 1944 if (!status) {
1945 struct be_cmd_resp_get_flow_control *resp =
1946 embedded_payload(wrb);
1947 *tx_fc = le16_to_cpu(resp->tx_flow_control);
1948 *rx_fc = le16_to_cpu(resp->rx_flow_control);
1949 }
1950
713d0394 1951err:
b31c50a7 1952 spin_unlock_bh(&adapter->mcc_lock);
6b7c5b94
SP		 1953 return status;
1954}
1955
b31c50a7 1956/* Uses mbox */
3abcdeda 1957int be_cmd_query_fw_cfg(struct be_adapter *adapter, u32 *port_num,
0ad3157e 1958 u32 *mode, u32 *caps, u16 *asic_rev)
6b7c5b94 1959{
b31c50a7
SP		 1960 struct be_mcc_wrb *wrb;
1961 struct be_cmd_req_query_fw_cfg *req;
6b7c5b94
SP		 1962 int status;
1963
2984961c
IV		 1964 if (mutex_lock_interruptible(&adapter->mbox_lock))
1965 return -1;
6b7c5b94 1966
b31c50a7
SP		 1967 wrb = wrb_from_mbox(adapter);
1968 req = embedded_payload(wrb);
6b7c5b94 1969
106df1e3
SK		 1970 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1971 OPCODE_COMMON_QUERY_FIRMWARE_CONFIG, sizeof(*req), wrb, NULL);
6b7c5b94 1972
b31c50a7 1973 status = be_mbox_notify_wait(adapter);
6b7c5b94
SP		 1974 if (!status) {
1975 struct be_cmd_resp_query_fw_cfg *resp = embedded_payload(wrb);
1976 *port_num = le32_to_cpu(resp->phys_port);
3486be29 1977 *mode = le32_to_cpu(resp->function_mode);
3abcdeda 1978 *caps = le32_to_cpu(resp->function_caps);
0ad3157e 1979 *asic_rev = le32_to_cpu(resp->asic_revision) & 0xFF;
6b7c5b94
SP		 1980 }
1981
2984961c 1982 mutex_unlock(&adapter->mbox_lock);
6b7c5b94
SP		 1983 return status;
1984}
14074eab 1985
b31c50a7 1986/* Uses mbox */
14074eab 1987int be_cmd_reset_function(struct be_adapter *adapter)
1988{
b31c50a7
SP		 1989 struct be_mcc_wrb *wrb;
1990 struct be_cmd_req_hdr *req;
14074eab 1991 int status;
1992
bf99e50d
PR		 1993 if (lancer_chip(adapter)) {
1994 status = lancer_wait_ready(adapter);
1995 if (!status) {
1996 iowrite32(SLI_PORT_CONTROL_IP_MASK,
1997 adapter->db + SLIPORT_CONTROL_OFFSET);
1998 status = lancer_test_and_set_rdy_state(adapter);
1999 }
2000 if (status) {
2001 dev_err(&adapter->pdev->dev,
2002 "Adapter in non recoverable error\n");
2003 }
2004 return status;
2005 }
2006
2984961c
IV		 2007 if (mutex_lock_interruptible(&adapter->mbox_lock))
2008 return -1;
14074eab 2009
b31c50a7
SP		 2010 wrb = wrb_from_mbox(adapter);
2011 req = embedded_payload(wrb);
14074eab 2012
106df1e3
SK		 2013 be_wrb_cmd_hdr_prepare(req, CMD_SUBSYSTEM_COMMON,
2014 OPCODE_COMMON_FUNCTION_RESET, sizeof(*req), wrb, NULL);
14074eab 2015
b31c50a7 2016 status = be_mbox_notify_wait(adapter);
14074eab 2017
2984961c 2018 mutex_unlock(&adapter->mbox_lock);
14074eab 2019 return status;
2020}
84517482 2021
594ad54a
SR		 2022int be_cmd_rss_config(struct be_adapter *adapter, u8 *rsstable,
2023 u32 rss_hash_opts, u16 table_size)
3abcdeda
SP		 2024{
2025 struct be_mcc_wrb *wrb;
2026 struct be_cmd_req_rss_config *req;
65f8584e
PR		 2027 u32 myhash[10] = {0x15d43fa5, 0x2534685a, 0x5f87693a, 0x5668494e,
2028 0x33cf6a53, 0x383334c6, 0x76ac4257, 0x59b242b2,
2029 0x3ea83c02, 0x4a110304};
3abcdeda
SP		 2030 int status;
2031
da1388d6
VV		 2032 if (!(be_if_cap_flags(adapter) & BE_IF_FLAGS_RSS))
2033 return 0;
2034
2984961c
IV		 2035 if (mutex_lock_interruptible(&adapter->mbox_lock))
2036 return -1;
3abcdeda
SP		 2037
2038 wrb = wrb_from_mbox(adapter);
2039 req = embedded_payload(wrb);
2040
106df1e3
SK		 2041 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
2042 OPCODE_ETH_RSS_CONFIG, sizeof(*req), wrb, NULL);
3abcdeda
SP		 2043
2044 req->if_id = cpu_to_le32(adapter->if_handle);
594ad54a
SR		 2045 req->enable_rss = cpu_to_le16(rss_hash_opts);
2046 req->cpu_table_size_log2 = cpu_to_le16(fls(table_size) - 1);
d3bd3a5e 2047
594ad54a 2048 if (lancer_chip(adapter) || skyhawk_chip(adapter))
d3bd3a5e 2049 req->hdr.version = 1;
d3bd3a5e 2050
3abcdeda
SP		 2051 memcpy(req->cpu_table, rsstable, table_size);
2052 memcpy(req->hash, myhash, sizeof(myhash));
2053 be_dws_cpu_to_le(req->hash, sizeof(req->hash));
2054
2055 status = be_mbox_notify_wait(adapter);
2056
2984961c 2057 mutex_unlock(&adapter->mbox_lock);
3abcdeda
SP		 2058 return status;
2059}
2060
fad9ab2c
SB		 2061/* Uses sync mcc */
2062int be_cmd_set_beacon_state(struct be_adapter *adapter, u8 port_num,
2063 u8 bcn, u8 sts, u8 state)
2064{
2065 struct be_mcc_wrb *wrb;
2066 struct be_cmd_req_enable_disable_beacon *req;
2067 int status;
2068
2069 spin_lock_bh(&adapter->mcc_lock);
2070
2071 wrb = wrb_from_mccq(adapter);
713d0394
SP		 2072 if (!wrb) {
2073 status = -EBUSY;
2074 goto err;
2075 }
fad9ab2c
SB		 2076 req = embedded_payload(wrb);
2077
106df1e3
SK		 2078 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2079 OPCODE_COMMON_ENABLE_DISABLE_BEACON, sizeof(*req), wrb, NULL);
fad9ab2c
SB		 2080
2081 req->port_num = port_num;
2082 req->beacon_state = state;
2083 req->beacon_duration = bcn;
2084 req->status_duration = sts;
2085
2086 status = be_mcc_notify_wait(adapter);
2087
713d0394 2088err:
fad9ab2c
SB		 2089 spin_unlock_bh(&adapter->mcc_lock);
2090 return status;
2091}
2092
2093/* Uses sync mcc */
2094int be_cmd_get_beacon_state(struct be_adapter *adapter, u8 port_num, u32 *state)
2095{
2096 struct be_mcc_wrb *wrb;
2097 struct be_cmd_req_get_beacon_state *req;
2098 int status;
2099
2100 spin_lock_bh(&adapter->mcc_lock);
2101
2102 wrb = wrb_from_mccq(adapter);
713d0394
SP		 2103 if (!wrb) {
2104 status = -EBUSY;
2105 goto err;
2106 }
fad9ab2c
SB		 2107 req = embedded_payload(wrb);
2108
106df1e3
SK		 2109 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2110 OPCODE_COMMON_GET_BEACON_STATE, sizeof(*req), wrb, NULL);
fad9ab2c
SB		 2111
2112 req->port_num = port_num;
2113
2114 status = be_mcc_notify_wait(adapter);
2115 if (!status) {
2116 struct be_cmd_resp_get_beacon_state *resp =
2117 embedded_payload(wrb);
2118 *state = resp->beacon_state;
2119 }
2120
713d0394 2121err:
fad9ab2c
SB		 2122 spin_unlock_bh(&adapter->mcc_lock);
2123 return status;
2124}
2125
485bf569 2126int lancer_cmd_write_object(struct be_adapter *adapter, struct be_dma_mem *cmd,
f67ef7ba
PR		 2127 u32 data_size, u32 data_offset,
2128 const char *obj_name, u32 *data_written,
2129 u8 *change_status, u8 *addn_status)
485bf569
SN		 2130{
2131 struct be_mcc_wrb *wrb;
2132 struct lancer_cmd_req_write_object *req;
2133 struct lancer_cmd_resp_write_object *resp;
2134 void *ctxt = NULL;
2135 int status;
2136
2137 spin_lock_bh(&adapter->mcc_lock);
2138 adapter->flash_status = 0;
2139
2140 wrb = wrb_from_mccq(adapter);
2141 if (!wrb) {
2142 status = -EBUSY;
2143 goto err_unlock;
2144 }
2145
2146 req = embedded_payload(wrb);
2147
106df1e3 2148 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
485bf569 2149 OPCODE_COMMON_WRITE_OBJECT,
106df1e3
SK		 2150 sizeof(struct lancer_cmd_req_write_object), wrb,
2151 NULL);
485bf569
SN		 2152
2153 ctxt = &req->context;
2154 AMAP_SET_BITS(struct amap_lancer_write_obj_context,
2155 write_length, ctxt, data_size);
2156
2157 if (data_size == 0)
2158 AMAP_SET_BITS(struct amap_lancer_write_obj_context,
2159 eof, ctxt, 1);
2160 else
2161 AMAP_SET_BITS(struct amap_lancer_write_obj_context,
2162 eof, ctxt, 0);
2163
2164 be_dws_cpu_to_le(ctxt, sizeof(req->context));
2165 req->write_offset = cpu_to_le32(data_offset);
2166 strcpy(req->object_name, obj_name);
2167 req->descriptor_count = cpu_to_le32(1);
2168 req->buf_len = cpu_to_le32(data_size);
2169 req->addr_low = cpu_to_le32((cmd->dma +
2170 sizeof(struct lancer_cmd_req_write_object))
2171 & 0xFFFFFFFF);
2172 req->addr_high = cpu_to_le32(upper_32_bits(cmd->dma +
2173 sizeof(struct lancer_cmd_req_write_object)));
2174
2175 be_mcc_notify(adapter);
2176 spin_unlock_bh(&adapter->mcc_lock);
2177
5eeff635 2178 if (!wait_for_completion_timeout(&adapter->et_cmd_compl,
701962d0 2179 msecs_to_jiffies(60000)))
485bf569
SN		 2180 status = -1;
2181 else
2182 status = adapter->flash_status;
2183
2184 resp = embedded_payload(wrb);
f67ef7ba 2185 if (!status) {
485bf569 2186 *data_written = le32_to_cpu(resp->actual_write_len);
f67ef7ba
PR		 2187 *change_status = resp->change_status;
2188 } else {
485bf569 2189 *addn_status = resp->additional_status;
f67ef7ba 2190 }
485bf569
SN		 2191
2192 return status;
2193
2194err_unlock:
2195 spin_unlock_bh(&adapter->mcc_lock);
2196 return status;
2197}
2198
de49bd5a
PR		 2199int lancer_cmd_read_object(struct be_adapter *adapter, struct be_dma_mem *cmd,
2200 u32 data_size, u32 data_offset, const char *obj_name,
2201 u32 *data_read, u32 *eof, u8 *addn_status)
2202{
2203 struct be_mcc_wrb *wrb;
2204 struct lancer_cmd_req_read_object *req;
2205 struct lancer_cmd_resp_read_object *resp;
2206 int status;
2207
2208 spin_lock_bh(&adapter->mcc_lock);
2209
2210 wrb = wrb_from_mccq(adapter);
2211 if (!wrb) {
2212 status = -EBUSY;
2213 goto err_unlock;
2214 }
2215
2216 req = embedded_payload(wrb);
2217
2218 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2219 OPCODE_COMMON_READ_OBJECT,
2220 sizeof(struct lancer_cmd_req_read_object), wrb,
2221 NULL);
2222
2223 req->desired_read_len = cpu_to_le32(data_size);
2224 req->read_offset = cpu_to_le32(data_offset);
2225 strcpy(req->object_name, obj_name);
2226 req->descriptor_count = cpu_to_le32(1);
2227 req->buf_len = cpu_to_le32(data_size);
2228 req->addr_low = cpu_to_le32((cmd->dma & 0xFFFFFFFF));
2229 req->addr_high = cpu_to_le32(upper_32_bits(cmd->dma));
2230
2231 status = be_mcc_notify_wait(adapter);
2232
2233 resp = embedded_payload(wrb);
2234 if (!status) {
2235 *data_read = le32_to_cpu(resp->actual_read_len);
2236 *eof = le32_to_cpu(resp->eof);
2237 } else {
2238 *addn_status = resp->additional_status;
2239 }
2240
2241err_unlock:
2242 spin_unlock_bh(&adapter->mcc_lock);
2243 return status;
2244}
2245
84517482
AK		 2246int be_cmd_write_flashrom(struct be_adapter *adapter, struct be_dma_mem *cmd,
2247 u32 flash_type, u32 flash_opcode, u32 buf_size)
2248{
b31c50a7 2249 struct be_mcc_wrb *wrb;
3f0d4560 2250 struct be_cmd_write_flashrom *req;
84517482
AK		 2251 int status;
2252
b31c50a7 2253 spin_lock_bh(&adapter->mcc_lock);
dd131e76 2254 adapter->flash_status = 0;
b31c50a7
SP		 2255
2256 wrb = wrb_from_mccq(adapter);
713d0394
SP		 2257 if (!wrb) {
2258 status = -EBUSY;
2892d9c2 2259 goto err_unlock;
713d0394
SP		 2260 }
2261 req = cmd->va;
84517482 2262
106df1e3
SK		 2263 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2264 OPCODE_COMMON_WRITE_FLASHROM, cmd->size, wrb, cmd);
84517482
AK		 2265
2266 req->params.op_type = cpu_to_le32(flash_type);
2267 req->params.op_code = cpu_to_le32(flash_opcode);
2268 req->params.data_buf_size = cpu_to_le32(buf_size);
2269
dd131e76
SB		 2270 be_mcc_notify(adapter);
2271 spin_unlock_bh(&adapter->mcc_lock);
2272
5eeff635
SR		 2273 if (!wait_for_completion_timeout(&adapter->et_cmd_compl,
2274 msecs_to_jiffies(40000)))
dd131e76
SB		 2275 status = -1;
2276 else
2277 status = adapter->flash_status;
84517482 2278
2892d9c2
DC		 2279 return status;
2280
2281err_unlock:
2282 spin_unlock_bh(&adapter->mcc_lock);
84517482
AK		 2283 return status;
2284}
fa9a6fed 2285
3f0d4560
AK		 2286int be_cmd_get_flash_crc(struct be_adapter *adapter, u8 *flashed_crc,
2287 int offset)
fa9a6fed
SB		 2288{
2289 struct be_mcc_wrb *wrb;
be716446 2290 struct be_cmd_read_flash_crc *req;
fa9a6fed
SB		 2291 int status;
2292
2293 spin_lock_bh(&adapter->mcc_lock);
2294
2295 wrb = wrb_from_mccq(adapter);
713d0394
SP		 2296 if (!wrb) {
2297 status = -EBUSY;
2298 goto err;
2299 }
fa9a6fed
SB		 2300 req = embedded_payload(wrb);
2301
106df1e3 2302 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
be716446
PR		 2303 OPCODE_COMMON_READ_FLASHROM, sizeof(*req),
2304 wrb, NULL);
fa9a6fed 2305
c165541e 2306 req->params.op_type = cpu_to_le32(OPTYPE_REDBOOT);
fa9a6fed 2307 req->params.op_code = cpu_to_le32(FLASHROM_OPER_REPORT);
8b93b710
AK		 2308 req->params.offset = cpu_to_le32(offset);
2309 req->params.data_buf_size = cpu_to_le32(0x4);
fa9a6fed
SB		 2310
2311 status = be_mcc_notify_wait(adapter);
2312 if (!status)
be716446 2313 memcpy(flashed_crc, req->crc, 4);
fa9a6fed 2314
713d0394 2315err:
fa9a6fed
SB		 2316 spin_unlock_bh(&adapter->mcc_lock);
2317 return status;
2318}
71d8d1b5 2319
c196b02c 2320int be_cmd_enable_magic_wol(struct be_adapter *adapter, u8 *mac,
71d8d1b5
AK		 2321 struct be_dma_mem *nonemb_cmd)
2322{
2323 struct be_mcc_wrb *wrb;
2324 struct be_cmd_req_acpi_wol_magic_config *req;
71d8d1b5
AK		 2325 int status;
2326
2327 spin_lock_bh(&adapter->mcc_lock);
2328
2329 wrb = wrb_from_mccq(adapter);
2330 if (!wrb) {
2331 status = -EBUSY;
2332 goto err;
2333 }
2334 req = nonemb_cmd->va;
71d8d1b5 2335
106df1e3
SK		 2336 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
2337 OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG, sizeof(*req), wrb,
2338 nonemb_cmd);
71d8d1b5
AK		 2339 memcpy(req->magic_mac, mac, ETH_ALEN);
2340
71d8d1b5
AK		 2341 status = be_mcc_notify_wait(adapter);
2342
2343err:
2344 spin_unlock_bh(&adapter->mcc_lock);
2345 return status;
2346}
ff33a6e2 2347
fced9999
SB		 2348int be_cmd_set_loopback(struct be_adapter *adapter, u8 port_num,
2349 u8 loopback_type, u8 enable)
2350{
2351 struct be_mcc_wrb *wrb;
2352 struct be_cmd_req_set_lmode *req;
2353 int status;
2354
2355 spin_lock_bh(&adapter->mcc_lock);
2356
2357 wrb = wrb_from_mccq(adapter);
2358 if (!wrb) {
2359 status = -EBUSY;
2360 goto err;
2361 }
2362
2363 req = embedded_payload(wrb);
2364
106df1e3
SK		 2365 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
2366 OPCODE_LOWLEVEL_SET_LOOPBACK_MODE, sizeof(*req), wrb,
2367 NULL);
fced9999
SB		 2368
2369 req->src_port = port_num;
2370 req->dest_port = port_num;
2371 req->loopback_type = loopback_type;
2372 req->loopback_state = enable;
2373
2374 status = be_mcc_notify_wait(adapter);
2375err:
2376 spin_unlock_bh(&adapter->mcc_lock);
2377 return status;
2378}
2379
ff33a6e2
S		 2380int be_cmd_loopback_test(struct be_adapter *adapter, u32 port_num,
2381 u32 loopback_type, u32 pkt_size, u32 num_pkts, u64 pattern)
2382{
2383 struct be_mcc_wrb *wrb;
2384 struct be_cmd_req_loopback_test *req;
5eeff635 2385 struct be_cmd_resp_loopback_test *resp;
ff33a6e2
S		 2386 int status;
2387
2388 spin_lock_bh(&adapter->mcc_lock);
2389
2390 wrb = wrb_from_mccq(adapter);
2391 if (!wrb) {
2392 status = -EBUSY;
2393 goto err;
2394 }
2395
2396 req = embedded_payload(wrb);
2397
106df1e3
SK		 2398 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
2399 OPCODE_LOWLEVEL_LOOPBACK_TEST, sizeof(*req), wrb, NULL);
ff33a6e2 2400
5eeff635 2401 req->hdr.timeout = cpu_to_le32(15);
ff33a6e2
S		 2402 req->pattern = cpu_to_le64(pattern);
2403 req->src_port = cpu_to_le32(port_num);
2404 req->dest_port = cpu_to_le32(port_num);
2405 req->pkt_size = cpu_to_le32(pkt_size);
2406 req->num_pkts = cpu_to_le32(num_pkts);
2407 req->loopback_type = cpu_to_le32(loopback_type);
2408
5eeff635
SR		 2409 be_mcc_notify(adapter);
2410
2411 spin_unlock_bh(&adapter->mcc_lock);
ff33a6e2 2412
5eeff635
SR		 2413 wait_for_completion(&adapter->et_cmd_compl);
2414 resp = embedded_payload(wrb);
2415 status = le32_to_cpu(resp->status);
2416
2417 return status;
ff33a6e2
S		 2418err:
2419 spin_unlock_bh(&adapter->mcc_lock);
2420 return status;
2421}
2422
2423int be_cmd_ddr_dma_test(struct be_adapter *adapter, u64 pattern,
2424 u32 byte_cnt, struct be_dma_mem *cmd)
2425{
2426 struct be_mcc_wrb *wrb;
2427 struct be_cmd_req_ddrdma_test *req;
ff33a6e2
S		 2428 int status;
2429 int i, j = 0;
2430
2431 spin_lock_bh(&adapter->mcc_lock);
2432
2433 wrb = wrb_from_mccq(adapter);
2434 if (!wrb) {
2435 status = -EBUSY;
2436 goto err;
2437 }
2438 req = cmd->va;
106df1e3
SK		 2439 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
2440 OPCODE_LOWLEVEL_HOST_DDR_DMA, cmd->size, wrb, cmd);
ff33a6e2
S		 2441
2442 req->pattern = cpu_to_le64(pattern);
2443 req->byte_count = cpu_to_le32(byte_cnt);
2444 for (i = 0; i < byte_cnt; i++) {
2445 req->snd_buff[i] = (u8)(pattern >> (j*8));
2446 j++;
2447 if (j > 7)
2448 j = 0;
2449 }
2450
2451 status = be_mcc_notify_wait(adapter);
2452
2453 if (!status) {
2454 struct be_cmd_resp_ddrdma_test *resp;
2455 resp = cmd->va;
2456 if ((memcmp(resp->rcv_buff, req->snd_buff, byte_cnt) != 0) ||
2457 resp->snd_err) {
2458 status = -1;
2459 }
2460 }
2461
2462err:
2463 spin_unlock_bh(&adapter->mcc_lock);
2464 return status;
2465}
368c0ca2 2466
c196b02c 2467int be_cmd_get_seeprom_data(struct be_adapter *adapter,
368c0ca2
SB		 2468 struct be_dma_mem *nonemb_cmd)
2469{
2470 struct be_mcc_wrb *wrb;
2471 struct be_cmd_req_seeprom_read *req;
368c0ca2
SB		 2472 int status;
2473
2474 spin_lock_bh(&adapter->mcc_lock);
2475
2476 wrb = wrb_from_mccq(adapter);
e45ff01d
AK		 2477 if (!wrb) {
2478 status = -EBUSY;
2479 goto err;
2480 }
368c0ca2 2481 req = nonemb_cmd->va;
368c0ca2 2482
106df1e3
SK		 2483 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2484 OPCODE_COMMON_SEEPROM_READ, sizeof(*req), wrb,
2485 nonemb_cmd);
368c0ca2
SB		 2486
2487 status = be_mcc_notify_wait(adapter);
2488
e45ff01d 2489err:
368c0ca2
SB		 2490 spin_unlock_bh(&adapter->mcc_lock);
2491 return status;
2492}
ee3cb629 2493
42f11cf2 2494int be_cmd_get_phy_info(struct be_adapter *adapter)
ee3cb629
AK		 2495{
2496 struct be_mcc_wrb *wrb;
2497 struct be_cmd_req_get_phy_info *req;
306f1348 2498 struct be_dma_mem cmd;
ee3cb629
AK		 2499 int status;
2500
f25b119c
PR		 2501 if (!be_cmd_allowed(adapter, OPCODE_COMMON_GET_PHY_DETAILS,
2502 CMD_SUBSYSTEM_COMMON))
2503 return -EPERM;
2504
ee3cb629
AK		 2505 spin_lock_bh(&adapter->mcc_lock);
2506
2507 wrb = wrb_from_mccq(adapter);
2508 if (!wrb) {
2509 status = -EBUSY;
2510 goto err;
2511 }
306f1348
SP		 2512 cmd.size = sizeof(struct be_cmd_req_get_phy_info);
2513 cmd.va = pci_alloc_consistent(adapter->pdev, cmd.size,
2514 &cmd.dma);
2515 if (!cmd.va) {
2516 dev_err(&adapter->pdev->dev, "Memory alloc failure\n");
2517 status = -ENOMEM;
2518 goto err;
2519 }
ee3cb629 2520
306f1348 2521 req = cmd.va;
ee3cb629 2522
106df1e3
SK		 2523 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2524 OPCODE_COMMON_GET_PHY_DETAILS, sizeof(*req),
2525 wrb, &cmd);
ee3cb629
AK		 2526
2527 status = be_mcc_notify_wait(adapter);
306f1348
SP		 2528 if (!status) {
2529 struct be_phy_info *resp_phy_info =
2530 cmd.va + sizeof(struct be_cmd_req_hdr);
42f11cf2
AK		 2531 adapter->phy.phy_type = le16_to_cpu(resp_phy_info->phy_type);
2532 adapter->phy.interface_type =
306f1348 2533 le16_to_cpu(resp_phy_info->interface_type);
42f11cf2
AK		 2534 adapter->phy.auto_speeds_supported =
2535 le16_to_cpu(resp_phy_info->auto_speeds_supported);
2536 adapter->phy.fixed_speeds_supported =
2537 le16_to_cpu(resp_phy_info->fixed_speeds_supported);
2538 adapter->phy.misc_params =
2539 le32_to_cpu(resp_phy_info->misc_params);
68cb7e47
VV		 2540
2541 if (BE2_chip(adapter)) {
2542 adapter->phy.fixed_speeds_supported =
2543 BE_SUPPORTED_SPEED_10GBPS |
2544 BE_SUPPORTED_SPEED_1GBPS;
2545 }
306f1348
SP		 2546 }
2547 pci_free_consistent(adapter->pdev, cmd.size,
2548 cmd.va, cmd.dma);
ee3cb629
AK		 2549err:
2550 spin_unlock_bh(&adapter->mcc_lock);
2551 return status;
2552}
e1d18735
AK		 2553
2554int be_cmd_set_qos(struct be_adapter *adapter, u32 bps, u32 domain)
2555{
2556 struct be_mcc_wrb *wrb;
2557 struct be_cmd_req_set_qos *req;
2558 int status;
2559
2560 spin_lock_bh(&adapter->mcc_lock);
2561
2562 wrb = wrb_from_mccq(adapter);
2563 if (!wrb) {
2564 status = -EBUSY;
2565 goto err;
2566 }
2567
2568 req = embedded_payload(wrb);
2569
106df1e3
SK		 2570 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2571 OPCODE_COMMON_SET_QOS, sizeof(*req), wrb, NULL);
e1d18735
AK		 2572
2573 req->hdr.domain = domain;
6bff57a7
AK		 2574 req->valid_bits = cpu_to_le32(BE_QOS_BITS_NIC);
2575 req->max_bps_nic = cpu_to_le32(bps);
e1d18735
AK		 2576
2577 status = be_mcc_notify_wait(adapter);
2578
2579err:
2580 spin_unlock_bh(&adapter->mcc_lock);
2581 return status;
2582}
9e1453c5
AK		 2583
2584int be_cmd_get_cntl_attributes(struct be_adapter *adapter)
2585{
2586 struct be_mcc_wrb *wrb;
2587 struct be_cmd_req_cntl_attribs *req;
2588 struct be_cmd_resp_cntl_attribs *resp;
9e1453c5
AK		 2589 int status;
2590 int payload_len = max(sizeof(*req), sizeof(*resp));
2591 struct mgmt_controller_attrib *attribs;
2592 struct be_dma_mem attribs_cmd;
2593
d98ef50f
SR		 2594 if (mutex_lock_interruptible(&adapter->mbox_lock))
2595 return -1;
2596
9e1453c5
AK		 2597 memset(&attribs_cmd, 0, sizeof(struct be_dma_mem));
2598 attribs_cmd.size = sizeof(struct be_cmd_resp_cntl_attribs);
2599 attribs_cmd.va = pci_alloc_consistent(adapter->pdev, attribs_cmd.size,
2600 &attribs_cmd.dma);
2601 if (!attribs_cmd.va) {
2602 dev_err(&adapter->pdev->dev,
2603 "Memory allocation failure\n");
d98ef50f
SR		 2604 status = -ENOMEM;
2605 goto err;
9e1453c5
AK		 2606 }
2607
9e1453c5
AK		 2608 wrb = wrb_from_mbox(adapter);
2609 if (!wrb) {
2610 status = -EBUSY;
2611 goto err;
2612 }
2613 req = attribs_cmd.va;
9e1453c5 2614
106df1e3
SK		 2615 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2616 OPCODE_COMMON_GET_CNTL_ATTRIBUTES, payload_len, wrb,
2617 &attribs_cmd);
9e1453c5
AK		 2618
2619 status = be_mbox_notify_wait(adapter);
2620 if (!status) {
43d620c8 2621 attribs = attribs_cmd.va + sizeof(struct be_cmd_resp_hdr);
9e1453c5
AK		 2622 adapter->hba_port_num = attribs->hba_attribs.phy_port;
2623 }
2624
2625err:
2626 mutex_unlock(&adapter->mbox_lock);
d98ef50f
SR		 2627 if (attribs_cmd.va)
2628 pci_free_consistent(adapter->pdev, attribs_cmd.size,
2629 attribs_cmd.va, attribs_cmd.dma);
9e1453c5
AK		 2630 return status;
2631}
2e588f84
SP		 2632
2633/* Uses mbox */
2dc1deb6 2634int be_cmd_req_native_mode(struct be_adapter *adapter)
2e588f84
SP		 2635{
2636 struct be_mcc_wrb *wrb;
2637 struct be_cmd_req_set_func_cap *req;
2638 int status;
2639
2640 if (mutex_lock_interruptible(&adapter->mbox_lock))
2641 return -1;
2642
2643 wrb = wrb_from_mbox(adapter);
2644 if (!wrb) {
2645 status = -EBUSY;
2646 goto err;
2647 }
2648
2649 req = embedded_payload(wrb);
2650
106df1e3
SK		 2651 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2652 OPCODE_COMMON_SET_DRIVER_FUNCTION_CAP, sizeof(*req), wrb, NULL);
2e588f84
SP		 2653
2654 req->valid_cap_flags = cpu_to_le32(CAPABILITY_SW_TIMESTAMPS |
2655 CAPABILITY_BE3_NATIVE_ERX_API);
2656 req->cap_flags = cpu_to_le32(CAPABILITY_BE3_NATIVE_ERX_API);
2657
2658 status = be_mbox_notify_wait(adapter);
2659 if (!status) {
2660 struct be_cmd_resp_set_func_cap *resp = embedded_payload(wrb);
2661 adapter->be3_native = le32_to_cpu(resp->cap_flags) &
2662 CAPABILITY_BE3_NATIVE_ERX_API;
d379142b
SP		 2663 if (!adapter->be3_native)
2664 dev_warn(&adapter->pdev->dev,
2665 "adapter not in advanced mode\n");
2e588f84
SP		 2666 }
2667err:
2668 mutex_unlock(&adapter->mbox_lock);
2669 return status;
2670}
590c391d 2671
f25b119c
PR		 2672/* Get privilege(s) for a function */
2673int be_cmd_get_fn_privileges(struct be_adapter *adapter, u32 *privilege,
2674 u32 domain)
2675{
2676 struct be_mcc_wrb *wrb;
2677 struct be_cmd_req_get_fn_privileges *req;
2678 int status;
2679
2680 spin_lock_bh(&adapter->mcc_lock);
2681
2682 wrb = wrb_from_mccq(adapter);
2683 if (!wrb) {
2684 status = -EBUSY;
2685 goto err;
2686 }
2687
2688 req = embedded_payload(wrb);
2689
2690 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2691 OPCODE_COMMON_GET_FN_PRIVILEGES, sizeof(*req),
2692 wrb, NULL);
2693
2694 req->hdr.domain = domain;
2695
2696 status = be_mcc_notify_wait(adapter);
2697 if (!status) {
2698 struct be_cmd_resp_get_fn_privileges *resp =
2699 embedded_payload(wrb);
2700 *privilege = le32_to_cpu(resp->privilege_mask);
02308d74
SR		 2701
2702 /* In UMC mode FW does not return right privileges.
2703 * Override with correct privilege equivalent to PF.
2704 */
2705 if (BEx_chip(adapter) && be_is_mc(adapter) &&
2706 be_physfn(adapter))
2707 *privilege = MAX_PRIVILEGES;
f25b119c
PR		 2708 }
2709
2710err:
2711 spin_unlock_bh(&adapter->mcc_lock);
2712 return status;
2713}
2714
04a06028
SP		 2715/* Set privilege(s) for a function */
2716int be_cmd_set_fn_privileges(struct be_adapter *adapter, u32 privileges,
2717 u32 domain)
2718{
2719 struct be_mcc_wrb *wrb;
2720 struct be_cmd_req_set_fn_privileges *req;
2721 int status;
2722
2723 spin_lock_bh(&adapter->mcc_lock);
2724
2725 wrb = wrb_from_mccq(adapter);
2726 if (!wrb) {
2727 status = -EBUSY;
2728 goto err;
2729 }
2730
2731 req = embedded_payload(wrb);
2732 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2733 OPCODE_COMMON_SET_FN_PRIVILEGES, sizeof(*req),
2734 wrb, NULL);
2735 req->hdr.domain = domain;
2736 if (lancer_chip(adapter))
2737 req->privileges_lancer = cpu_to_le32(privileges);
2738 else
2739 req->privileges = cpu_to_le32(privileges);
2740
2741 status = be_mcc_notify_wait(adapter);
2742err:
2743 spin_unlock_bh(&adapter->mcc_lock);
2744 return status;
2745}
2746
5a712c13
SP		 2747/* pmac_id_valid: true => pmac_id is supplied and MAC address is requested.
2748 * pmac_id_valid: false => pmac_id or MAC address is requested.
2749 * If pmac_id is returned, pmac_id_valid is returned as true
2750 */
1578e777 2751int be_cmd_get_mac_from_list(struct be_adapter *adapter, u8 *mac,
b188f090
SR		 2752 bool *pmac_id_valid, u32 *pmac_id, u32 if_handle,
2753 u8 domain)
590c391d
PR		 2754{
2755 struct be_mcc_wrb *wrb;
2756 struct be_cmd_req_get_mac_list *req;
2757 int status;
2758 int mac_count;
e5e1ee89
PR		 2759 struct be_dma_mem get_mac_list_cmd;
2760 int i;
2761
2762 memset(&get_mac_list_cmd, 0, sizeof(struct be_dma_mem));
2763 get_mac_list_cmd.size = sizeof(struct be_cmd_resp_get_mac_list);
2764 get_mac_list_cmd.va = pci_alloc_consistent(adapter->pdev,
2765 get_mac_list_cmd.size,
2766 &get_mac_list_cmd.dma);
2767
2768 if (!get_mac_list_cmd.va) {
2769 dev_err(&adapter->pdev->dev,
2770 "Memory allocation failure during GET_MAC_LIST\n");
2771 return -ENOMEM;
2772 }
590c391d
PR		 2773
2774 spin_lock_bh(&adapter->mcc_lock);
2775
2776 wrb = wrb_from_mccq(adapter);
2777 if (!wrb) {
2778 status = -EBUSY;
e5e1ee89 2779 goto out;
590c391d 2780 }
e5e1ee89
PR		 2781
2782 req = get_mac_list_cmd.va;
590c391d
PR		 2783
2784 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
bf591f51
SP		 2785 OPCODE_COMMON_GET_MAC_LIST,
2786 get_mac_list_cmd.size, wrb, &get_mac_list_cmd);
590c391d 2787 req->hdr.domain = domain;
e5e1ee89 2788 req->mac_type = MAC_ADDRESS_TYPE_NETWORK;
5a712c13
SP		 2789 if (*pmac_id_valid) {
2790 req->mac_id = cpu_to_le32(*pmac_id);
b188f090 2791 req->iface_id = cpu_to_le16(if_handle);
5a712c13
SP		 2792 req->perm_override = 0;
2793 } else {
2794 req->perm_override = 1;
2795 }
590c391d
PR		 2796
2797 status = be_mcc_notify_wait(adapter);
2798 if (!status) {
2799 struct be_cmd_resp_get_mac_list *resp =
e5e1ee89 2800 get_mac_list_cmd.va;
5a712c13
SP		 2801
2802 if (*pmac_id_valid) {
2803 memcpy(mac, resp->macid_macaddr.mac_addr_id.macaddr,
2804 ETH_ALEN);
2805 goto out;
2806 }
2807
e5e1ee89
PR		 2808 mac_count = resp->true_mac_count + resp->pseudo_mac_count;
2809 /* Mac list returned could contain one or more active mac_ids
1578e777
PR		 2810 * or one or more true or pseudo permanant mac addresses.
2811 * If an active mac_id is present, return first active mac_id
2812 * found.
e5e1ee89 2813 */
590c391d 2814 for (i = 0; i < mac_count; i++) {
e5e1ee89
PR		 2815 struct get_list_macaddr *mac_entry;
2816 u16 mac_addr_size;
2817 u32 mac_id;
2818
2819 mac_entry = &resp->macaddr_list[i];
2820 mac_addr_size = le16_to_cpu(mac_entry->mac_addr_size);
2821 /* mac_id is a 32 bit value and mac_addr size
2822 * is 6 bytes
2823 */
2824 if (mac_addr_size == sizeof(u32)) {
5a712c13 2825 *pmac_id_valid = true;
e5e1ee89
PR		 2826 mac_id = mac_entry->mac_addr_id.s_mac_id.mac_id;
2827 *pmac_id = le32_to_cpu(mac_id);
2828 goto out;
590c391d 2829 }
590c391d 2830 }
1578e777 2831 /* If no active mac_id found, return first mac addr */
5a712c13 2832 *pmac_id_valid = false;
e5e1ee89
PR		 2833 memcpy(mac, resp->macaddr_list[0].mac_addr_id.macaddr,
2834 ETH_ALEN);
590c391d
PR		 2835 }
2836
e5e1ee89 2837out:
590c391d 2838 spin_unlock_bh(&adapter->mcc_lock);
e5e1ee89
PR		 2839 pci_free_consistent(adapter->pdev, get_mac_list_cmd.size,
2840 get_mac_list_cmd.va, get_mac_list_cmd.dma);
590c391d
PR		 2841 return status;
2842}
2843
b188f090
SR		 2844int be_cmd_get_active_mac(struct be_adapter *adapter, u32 curr_pmac_id, u8 *mac,
2845 u32 if_handle, bool active, u32 domain)
5a712c13 2846{
5a712c13 2847
b188f090
SR		 2848 if (!active)
2849 be_cmd_get_mac_from_list(adapter, mac, &active, &curr_pmac_id,
2850 if_handle, domain);
3175d8c2 2851 if (BEx_chip(adapter))
5a712c13 2852 return be_cmd_mac_addr_query(adapter, mac, false,
b188f090 2853 if_handle, curr_pmac_id);
3175d8c2
SP		 2854 else
2855 /* Fetch the MAC address using pmac_id */
2856 return be_cmd_get_mac_from_list(adapter, mac, &active,
b188f090
SR		 2857 &curr_pmac_id,
2858 if_handle, domain);
5a712c13
SP		 2859}
2860
95046b92
SP		 2861int be_cmd_get_perm_mac(struct be_adapter *adapter, u8 *mac)
2862{
2863 int status;
2864 bool pmac_valid = false;
2865
2866 memset(mac, 0, ETH_ALEN);
2867
3175d8c2
SP		 2868 if (BEx_chip(adapter)) {
2869 if (be_physfn(adapter))
2870 status = be_cmd_mac_addr_query(adapter, mac, true, 0,
2871 0);
2872 else
2873 status = be_cmd_mac_addr_query(adapter, mac, false,
2874 adapter->if_handle, 0);
2875 } else {
95046b92 2876 status = be_cmd_get_mac_from_list(adapter, mac, &pmac_valid,
b188f090 2877 NULL, adapter->if_handle, 0);
3175d8c2
SP		 2878 }
2879
95046b92
SP		 2880 return status;
2881}
2882
590c391d
PR		 2883/* Uses synchronous MCCQ */
2884int be_cmd_set_mac_list(struct be_adapter *adapter, u8 *mac_array,
2885 u8 mac_count, u32 domain)
2886{
2887 struct be_mcc_wrb *wrb;
2888 struct be_cmd_req_set_mac_list *req;
2889 int status;
2890 struct be_dma_mem cmd;
2891
2892 memset(&cmd, 0, sizeof(struct be_dma_mem));
2893 cmd.size = sizeof(struct be_cmd_req_set_mac_list);
2894 cmd.va = dma_alloc_coherent(&adapter->pdev->dev, cmd.size,
2895 &cmd.dma, GFP_KERNEL);
d0320f75 2896 if (!cmd.va)
590c391d 2897 return -ENOMEM;
590c391d
PR		 2898
2899 spin_lock_bh(&adapter->mcc_lock);
2900
2901 wrb = wrb_from_mccq(adapter);
2902 if (!wrb) {
2903 status = -EBUSY;
2904 goto err;
2905 }
2906
2907 req = cmd.va;
2908 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2909 OPCODE_COMMON_SET_MAC_LIST, sizeof(*req),
2910 wrb, &cmd);
2911
2912 req->hdr.domain = domain;
2913 req->mac_count = mac_count;
2914 if (mac_count)
2915 memcpy(req->mac, mac_array, ETH_ALEN*mac_count);
2916
2917 status = be_mcc_notify_wait(adapter);
2918
2919err:
2920 dma_free_coherent(&adapter->pdev->dev, cmd.size,
2921 cmd.va, cmd.dma);
2922 spin_unlock_bh(&adapter->mcc_lock);
2923 return status;
2924}
4762f6ce 2925
3175d8c2
SP		 2926/* Wrapper to delete any active MACs and provision the new mac.
2927 * Changes to MAC_LIST are allowed iff none of the MAC addresses in the
2928 * current list are active.
2929 */
2930int be_cmd_set_mac(struct be_adapter *adapter, u8 *mac, int if_id, u32 dom)
2931{
2932 bool active_mac = false;
2933 u8 old_mac[ETH_ALEN];
2934 u32 pmac_id;
2935 int status;
2936
2937 status = be_cmd_get_mac_from_list(adapter, old_mac, &active_mac,
b188f090
SR		 2938 &pmac_id, if_id, dom);
2939
3175d8c2
SP		 2940 if (!status && active_mac)
2941 be_cmd_pmac_del(adapter, if_id, pmac_id, dom);
2942
2943 return be_cmd_set_mac_list(adapter, mac, mac ? 1 : 0, dom);
2944}
2945
f1f3ee1b 2946int be_cmd_set_hsw_config(struct be_adapter *adapter, u16 pvid,
a77dcb8c 2947 u32 domain, u16 intf_id, u16 hsw_mode)
f1f3ee1b
AK		 2948{
2949 struct be_mcc_wrb *wrb;
2950 struct be_cmd_req_set_hsw_config *req;
2951 void *ctxt;
2952 int status;
2953
2954 spin_lock_bh(&adapter->mcc_lock);
2955
2956 wrb = wrb_from_mccq(adapter);
2957 if (!wrb) {
2958 status = -EBUSY;
2959 goto err;
2960 }
2961
2962 req = embedded_payload(wrb);
2963 ctxt = &req->context;
2964
2965 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2966 OPCODE_COMMON_SET_HSW_CONFIG, sizeof(*req), wrb, NULL);
2967
2968 req->hdr.domain = domain;
2969 AMAP_SET_BITS(struct amap_set_hsw_context, interface_id, ctxt, intf_id);
2970 if (pvid) {
2971 AMAP_SET_BITS(struct amap_set_hsw_context, pvid_valid, ctxt, 1);
2972 AMAP_SET_BITS(struct amap_set_hsw_context, pvid, ctxt, pvid);
2973 }
a77dcb8c
AK		 2974 if (!BEx_chip(adapter) && hsw_mode) {
2975 AMAP_SET_BITS(struct amap_set_hsw_context, interface_id,
2976 ctxt, adapter->hba_port_num);
2977 AMAP_SET_BITS(struct amap_set_hsw_context, pport, ctxt, 1);
2978 AMAP_SET_BITS(struct amap_set_hsw_context, port_fwd_type,
2979 ctxt, hsw_mode);
2980 }
f1f3ee1b
AK		 2981
2982 be_dws_cpu_to_le(req->context, sizeof(req->context));
2983 status = be_mcc_notify_wait(adapter);
2984
2985err:
2986 spin_unlock_bh(&adapter->mcc_lock);
2987 return status;
2988}
2989
2990/* Get Hyper switch config */
2991int be_cmd_get_hsw_config(struct be_adapter *adapter, u16 *pvid,
a77dcb8c 2992 u32 domain, u16 intf_id, u8 *mode)
f1f3ee1b
AK		 2993{
2994 struct be_mcc_wrb *wrb;
2995 struct be_cmd_req_get_hsw_config *req;
2996 void *ctxt;
2997 int status;
2998 u16 vid;
2999
3000 spin_lock_bh(&adapter->mcc_lock);
3001
3002 wrb = wrb_from_mccq(adapter);
3003 if (!wrb) {
3004 status = -EBUSY;
3005 goto err;
3006 }
3007
3008 req = embedded_payload(wrb);
3009 ctxt = &req->context;
3010
3011 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3012 OPCODE_COMMON_GET_HSW_CONFIG, sizeof(*req), wrb, NULL);
3013
3014 req->hdr.domain = domain;
a77dcb8c
AK		 3015 AMAP_SET_BITS(struct amap_get_hsw_req_context, interface_id,
3016 ctxt, intf_id);
f1f3ee1b 3017 AMAP_SET_BITS(struct amap_get_hsw_req_context, pvid_valid, ctxt, 1);
a77dcb8c 3018
2c07c1d7 3019 if (!BEx_chip(adapter) && mode) {
a77dcb8c
AK		 3020 AMAP_SET_BITS(struct amap_get_hsw_req_context, interface_id,
3021 ctxt, adapter->hba_port_num);
3022 AMAP_SET_BITS(struct amap_get_hsw_req_context, pport, ctxt, 1);
3023 }
f1f3ee1b
AK		 3024 be_dws_cpu_to_le(req->context, sizeof(req->context));
3025
3026 status = be_mcc_notify_wait(adapter);
3027 if (!status) {
3028 struct be_cmd_resp_get_hsw_config *resp =
3029 embedded_payload(wrb);
3030 be_dws_le_to_cpu(&resp->context,
3031 sizeof(resp->context));
3032 vid = AMAP_GET_BITS(struct amap_get_hsw_resp_context,
3033 pvid, &resp->context);
a77dcb8c
AK		 3034 if (pvid)
3035 *pvid = le16_to_cpu(vid);
3036 if (mode)
3037 *mode = AMAP_GET_BITS(struct amap_get_hsw_resp_context,
3038 port_fwd_type, &resp->context);
f1f3ee1b
AK		 3039 }
3040
3041err:
3042 spin_unlock_bh(&adapter->mcc_lock);
3043 return status;
3044}
3045
4762f6ce
AK		 3046int be_cmd_get_acpi_wol_cap(struct be_adapter *adapter)
3047{
3048 struct be_mcc_wrb *wrb;
3049 struct be_cmd_req_acpi_wol_magic_config_v1 *req;
76a9e08e 3050 int status = 0;
4762f6ce
AK		 3051 struct be_dma_mem cmd;
3052
f25b119c
PR		 3053 if (!be_cmd_allowed(adapter, OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG,
3054 CMD_SUBSYSTEM_ETH))
3055 return -EPERM;
3056
76a9e08e
SR		 3057 if (be_is_wol_excluded(adapter))
3058 return status;
3059
d98ef50f
SR		 3060 if (mutex_lock_interruptible(&adapter->mbox_lock))
3061 return -1;
3062
4762f6ce
AK		 3063 memset(&cmd, 0, sizeof(struct be_dma_mem));
3064 cmd.size = sizeof(struct be_cmd_resp_acpi_wol_magic_config_v1);
3065 cmd.va = pci_alloc_consistent(adapter->pdev, cmd.size,
3066 &cmd.dma);
3067 if (!cmd.va) {
3068 dev_err(&adapter->pdev->dev,
3069 "Memory allocation failure\n");
d98ef50f
SR		 3070 status = -ENOMEM;
3071 goto err;
4762f6ce
AK		 3072 }
3073
4762f6ce
AK		 3074 wrb = wrb_from_mbox(adapter);
3075 if (!wrb) {
3076 status = -EBUSY;
3077 goto err;
3078 }
3079
3080 req = cmd.va;
3081
3082 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
3083 OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG,
76a9e08e 3084 sizeof(*req), wrb, &cmd);
4762f6ce
AK		 3085
3086 req->hdr.version = 1;
3087 req->query_options = BE_GET_WOL_CAP;
3088
3089 status = be_mbox_notify_wait(adapter);
3090 if (!status) {
3091 struct be_cmd_resp_acpi_wol_magic_config_v1 *resp;
3092 resp = (struct be_cmd_resp_acpi_wol_magic_config_v1 *) cmd.va;
3093
4762f6ce 3094 adapter->wol_cap = resp->wol_settings;
76a9e08e
SR		 3095 if (adapter->wol_cap & BE_WOL_CAP)
3096 adapter->wol_en = true;
4762f6ce
AK		 3097 }
3098err:
3099 mutex_unlock(&adapter->mbox_lock);
d98ef50f
SR		 3100 if (cmd.va)
3101 pci_free_consistent(adapter->pdev, cmd.size, cmd.va, cmd.dma);
4762f6ce 3102 return status;
941a77d5
SK		 3103
3104}
baaa08d1
VV		 3105
3106int be_cmd_set_fw_log_level(struct be_adapter *adapter, u32 level)
3107{
3108 struct be_dma_mem extfat_cmd;
3109 struct be_fat_conf_params *cfgs;
3110 int status;
3111 int i, j;
3112
3113 memset(&extfat_cmd, 0, sizeof(struct be_dma_mem));
3114 extfat_cmd.size = sizeof(struct be_cmd_resp_get_ext_fat_caps);
3115 extfat_cmd.va = pci_alloc_consistent(adapter->pdev, extfat_cmd.size,
3116 &extfat_cmd.dma);
3117 if (!extfat_cmd.va)
3118 return -ENOMEM;
3119
3120 status = be_cmd_get_ext_fat_capabilites(adapter, &extfat_cmd);
3121 if (status)
3122 goto err;
3123
3124 cfgs = (struct be_fat_conf_params *)
3125 (extfat_cmd.va + sizeof(struct be_cmd_resp_hdr));
3126 for (i = 0; i < le32_to_cpu(cfgs->num_modules); i++) {
3127 u32 num_modes = le32_to_cpu(cfgs->module[i].num_modes);
3128 for (j = 0; j < num_modes; j++) {
3129 if (cfgs->module[i].trace_lvl[j].mode == MODE_UART)
3130 cfgs->module[i].trace_lvl[j].dbg_lvl =
3131 cpu_to_le32(level);
3132 }
3133 }
3134
3135 status = be_cmd_set_ext_fat_capabilites(adapter, &extfat_cmd, cfgs);
3136err:
3137 pci_free_consistent(adapter->pdev, extfat_cmd.size, extfat_cmd.va,
3138 extfat_cmd.dma);
3139 return status;
3140}
3141
3142int be_cmd_get_fw_log_level(struct be_adapter *adapter)
3143{
3144 struct be_dma_mem extfat_cmd;
3145 struct be_fat_conf_params *cfgs;
3146 int status, j;
3147 int level = 0;
3148
3149 memset(&extfat_cmd, 0, sizeof(struct be_dma_mem));
3150 extfat_cmd.size = sizeof(struct be_cmd_resp_get_ext_fat_caps);
3151 extfat_cmd.va = pci_alloc_consistent(adapter->pdev, extfat_cmd.size,
3152 &extfat_cmd.dma);
3153
3154 if (!extfat_cmd.va) {
3155 dev_err(&adapter->pdev->dev, "%s: Memory allocation failure\n",
3156 __func__);
3157 goto err;
3158 }
3159
3160 status = be_cmd_get_ext_fat_capabilites(adapter, &extfat_cmd);
3161 if (!status) {
3162 cfgs = (struct be_fat_conf_params *)(extfat_cmd.va +
3163 sizeof(struct be_cmd_resp_hdr));
3164 for (j = 0; j < le32_to_cpu(cfgs->module[0].num_modes); j++) {
3165 if (cfgs->module[0].trace_lvl[j].mode == MODE_UART)
3166 level = cfgs->module[0].trace_lvl[j].dbg_lvl;
3167 }
3168 }
3169 pci_free_consistent(adapter->pdev, extfat_cmd.size, extfat_cmd.va,
3170 extfat_cmd.dma);
3171err:
3172 return level;
3173}
3174
941a77d5
SK		 3175int be_cmd_get_ext_fat_capabilites(struct be_adapter *adapter,
3176 struct be_dma_mem *cmd)
3177{
3178 struct be_mcc_wrb *wrb;
3179 struct be_cmd_req_get_ext_fat_caps *req;
3180 int status;
3181
3182 if (mutex_lock_interruptible(&adapter->mbox_lock))
3183 return -1;
3184
3185 wrb = wrb_from_mbox(adapter);
3186 if (!wrb) {
3187 status = -EBUSY;
3188 goto err;
3189 }
3190
3191 req = cmd->va;
3192 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3193 OPCODE_COMMON_GET_EXT_FAT_CAPABILITES,
3194 cmd->size, wrb, cmd);
3195 req->parameter_type = cpu_to_le32(1);
3196
3197 status = be_mbox_notify_wait(adapter);
3198err:
3199 mutex_unlock(&adapter->mbox_lock);
3200 return status;
3201}
3202
3203int be_cmd_set_ext_fat_capabilites(struct be_adapter *adapter,
3204 struct be_dma_mem *cmd,
3205 struct be_fat_conf_params *configs)
3206{
3207 struct be_mcc_wrb *wrb;
3208 struct be_cmd_req_set_ext_fat_caps *req;
3209 int status;
3210
3211 spin_lock_bh(&adapter->mcc_lock);
3212
3213 wrb = wrb_from_mccq(adapter);
3214 if (!wrb) {
3215 status = -EBUSY;
3216 goto err;
3217 }
3218
3219 req = cmd->va;
3220 memcpy(&req->set_params, configs, sizeof(struct be_fat_conf_params));
3221 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3222 OPCODE_COMMON_SET_EXT_FAT_CAPABILITES,
3223 cmd->size, wrb, cmd);
3224
3225 status = be_mcc_notify_wait(adapter);
3226err:
3227 spin_unlock_bh(&adapter->mcc_lock);
3228 return status;
4762f6ce 3229}
6a4ab669 3230
b4e32a71
PR		 3231int be_cmd_query_port_name(struct be_adapter *adapter, u8 *port_name)
3232{
3233 struct be_mcc_wrb *wrb;
3234 struct be_cmd_req_get_port_name *req;
3235 int status;
3236
3237 if (!lancer_chip(adapter)) {
3238 *port_name = adapter->hba_port_num + '0';
3239 return 0;
3240 }
3241
3242 spin_lock_bh(&adapter->mcc_lock);
3243
3244 wrb = wrb_from_mccq(adapter);
3245 if (!wrb) {
3246 status = -EBUSY;
3247 goto err;
3248 }
3249
3250 req = embedded_payload(wrb);
3251
3252 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3253 OPCODE_COMMON_GET_PORT_NAME, sizeof(*req), wrb,
3254 NULL);
3255 req->hdr.version = 1;
3256
3257 status = be_mcc_notify_wait(adapter);
3258 if (!status) {
3259 struct be_cmd_resp_get_port_name *resp = embedded_payload(wrb);
3260 *port_name = resp->port_name[adapter->hba_port_num];
3261 } else {
3262 *port_name = adapter->hba_port_num + '0';
3263 }
3264err:
3265 spin_unlock_bh(&adapter->mcc_lock);
3266 return status;
3267}
3268
150d58c7 3269static struct be_nic_res_desc *be_get_nic_desc(u8 *buf, u32 desc_count)
abb93951 3270{
150d58c7 3271 struct be_res_desc_hdr *hdr = (struct be_res_desc_hdr *)buf;
abb93951
PR		 3272 int i;
3273
3274 for (i = 0; i < desc_count; i++) {
150d58c7
VV		 3275 if (hdr->desc_type == NIC_RESOURCE_DESC_TYPE_V0 ||
3276 hdr->desc_type == NIC_RESOURCE_DESC_TYPE_V1)
3277 return (struct be_nic_res_desc *)hdr;
abb93951 3278
150d58c7
VV		 3279 hdr->desc_len = hdr->desc_len ? : RESOURCE_DESC_SIZE_V0;
3280 hdr = (void *)hdr + hdr->desc_len;
abb93951 3281 }
150d58c7
VV		 3282 return NULL;
3283}
3284
3285static struct be_pcie_res_desc *be_get_pcie_desc(u8 devfn, u8 *buf,
3286 u32 desc_count)
3287{
3288 struct be_res_desc_hdr *hdr = (struct be_res_desc_hdr *)buf;
3289 struct be_pcie_res_desc *pcie;
3290 int i;
3291
3292 for (i = 0; i < desc_count; i++) {
3293 if ((hdr->desc_type == PCIE_RESOURCE_DESC_TYPE_V0 ||
3294 hdr->desc_type == PCIE_RESOURCE_DESC_TYPE_V1)) {
3295 pcie = (struct be_pcie_res_desc *)hdr;
3296 if (pcie->pf_num == devfn)
3297 return pcie;
3298 }
abb93951 3299
150d58c7
VV		 3300 hdr->desc_len = hdr->desc_len ? : RESOURCE_DESC_SIZE_V0;
3301 hdr = (void *)hdr + hdr->desc_len;
3302 }
950e2958 3303 return NULL;
abb93951
PR		 3304}
3305
f93f160b
VV		 3306static struct be_port_res_desc *be_get_port_desc(u8 *buf, u32 desc_count)
3307{
3308 struct be_res_desc_hdr *hdr = (struct be_res_desc_hdr *)buf;
3309 int i;
3310
3311 for (i = 0; i < desc_count; i++) {
3312 if (hdr->desc_type == PORT_RESOURCE_DESC_TYPE_V1)
3313 return (struct be_port_res_desc *)hdr;
3314
3315 hdr->desc_len = hdr->desc_len ? : RESOURCE_DESC_SIZE_V0;
3316 hdr = (void *)hdr + hdr->desc_len;
3317 }
3318 return NULL;
3319}
3320
92bf14ab
SP		 3321static void be_copy_nic_desc(struct be_resources *res,
3322 struct be_nic_res_desc *desc)
3323{
3324 res->max_uc_mac = le16_to_cpu(desc->unicast_mac_count);
3325 res->max_vlans = le16_to_cpu(desc->vlan_count);
3326 res->max_mcast_mac = le16_to_cpu(desc->mcast_mac_count);
3327 res->max_tx_qs = le16_to_cpu(desc->txq_count);
3328 res->max_rss_qs = le16_to_cpu(desc->rssq_count);
3329 res->max_rx_qs = le16_to_cpu(desc->rq_count);
3330 res->max_evt_qs = le16_to_cpu(desc->eq_count);
3331 /* Clear flags that driver is not interested in */
3332 res->if_cap_flags = le32_to_cpu(desc->cap_flags) &
3333 BE_IF_CAP_FLAGS_WANT;
3334 /* Need 1 RXQ as the default RXQ */
3335 if (res->max_rss_qs && res->max_rss_qs == res->max_rx_qs)
3336 res->max_rss_qs -= 1;
3337}
3338
abb93951 3339/* Uses Mbox */
92bf14ab 3340int be_cmd_get_func_config(struct be_adapter *adapter, struct be_resources *res)
abb93951
PR		 3341{
3342 struct be_mcc_wrb *wrb;
3343 struct be_cmd_req_get_func_config *req;
3344 int status;
3345 struct be_dma_mem cmd;
3346
d98ef50f
SR		 3347 if (mutex_lock_interruptible(&adapter->mbox_lock))
3348 return -1;
3349
abb93951
PR		 3350 memset(&cmd, 0, sizeof(struct be_dma_mem));
3351 cmd.size = sizeof(struct be_cmd_resp_get_func_config);
3352 cmd.va = pci_alloc_consistent(adapter->pdev, cmd.size,
3353 &cmd.dma);
3354 if (!cmd.va) {
3355 dev_err(&adapter->pdev->dev, "Memory alloc failure\n");
d98ef50f
SR		 3356 status = -ENOMEM;
3357 goto err;
abb93951 3358 }
abb93951
PR		 3359
3360 wrb = wrb_from_mbox(adapter);
3361 if (!wrb) {
3362 status = -EBUSY;
3363 goto err;
3364 }
3365
3366 req = cmd.va;
3367
3368 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3369 OPCODE_COMMON_GET_FUNC_CONFIG,
3370 cmd.size, wrb, &cmd);
3371
28710c55
KA		 3372 if (skyhawk_chip(adapter))
3373 req->hdr.version = 1;
3374
abb93951
PR		 3375 status = be_mbox_notify_wait(adapter);
3376 if (!status) {
3377 struct be_cmd_resp_get_func_config *resp = cmd.va;
3378 u32 desc_count = le32_to_cpu(resp->desc_count);
150d58c7 3379 struct be_nic_res_desc *desc;
abb93951 3380
150d58c7 3381 desc = be_get_nic_desc(resp->func_param, desc_count);
abb93951
PR		 3382 if (!desc) {
3383 status = -EINVAL;
3384 goto err;
3385 }
3386
d5c18473 3387 adapter->pf_number = desc->pf_num;
92bf14ab 3388 be_copy_nic_desc(res, desc);
abb93951
PR		 3389 }
3390err:
3391 mutex_unlock(&adapter->mbox_lock);
d98ef50f
SR		 3392 if (cmd.va)
3393 pci_free_consistent(adapter->pdev, cmd.size, cmd.va, cmd.dma);
abb93951
PR		 3394 return status;
3395}
3396
a05f99db 3397/* Uses mbox */
4188e7df
JH		 3398static int be_cmd_get_profile_config_mbox(struct be_adapter *adapter,
3399 u8 domain, struct be_dma_mem *cmd)
abb93951
PR		 3400{
3401 struct be_mcc_wrb *wrb;
3402 struct be_cmd_req_get_profile_config *req;
3403 int status;
abb93951 3404
a05f99db
VV		 3405 if (mutex_lock_interruptible(&adapter->mbox_lock))
3406 return -1;
3407 wrb = wrb_from_mbox(adapter);
3408
3409 req = cmd->va;
3410 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3411 OPCODE_COMMON_GET_PROFILE_CONFIG,
3412 cmd->size, wrb, cmd);
3413
3414 req->type = ACTIVE_PROFILE_TYPE;
3415 req->hdr.domain = domain;
3416 if (!lancer_chip(adapter))
3417 req->hdr.version = 1;
3418
3419 status = be_mbox_notify_wait(adapter);
3420
3421 mutex_unlock(&adapter->mbox_lock);
3422 return status;
3423}
3424
3425/* Uses sync mcc */
4188e7df
JH		 3426static int be_cmd_get_profile_config_mccq(struct be_adapter *adapter,
3427 u8 domain, struct be_dma_mem *cmd)
a05f99db
VV		 3428{
3429 struct be_mcc_wrb *wrb;
3430 struct be_cmd_req_get_profile_config *req;
3431 int status;
abb93951
PR		 3432
3433 spin_lock_bh(&adapter->mcc_lock);
3434
3435 wrb = wrb_from_mccq(adapter);
3436 if (!wrb) {
3437 status = -EBUSY;
3438 goto err;
3439 }
3440
a05f99db 3441 req = cmd->va;
abb93951
PR		 3442 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3443 OPCODE_COMMON_GET_PROFILE_CONFIG,
a05f99db 3444 cmd->size, wrb, cmd);
abb93951
PR		 3445
3446 req->type = ACTIVE_PROFILE_TYPE;
3447 req->hdr.domain = domain;
a05f99db
VV		 3448 if (!lancer_chip(adapter))
3449 req->hdr.version = 1;
abb93951
PR		 3450
3451 status = be_mcc_notify_wait(adapter);
a05f99db
VV		 3452
3453err:
3454 spin_unlock_bh(&adapter->mcc_lock);
3455 return status;
3456}
3457
3458/* Uses sync mcc, if MCCQ is already created otherwise mbox */
92bf14ab
SP		 3459int be_cmd_get_profile_config(struct be_adapter *adapter,
3460 struct be_resources *res, u8 domain)
a05f99db 3461{
150d58c7
VV		 3462 struct be_cmd_resp_get_profile_config *resp;
3463 struct be_pcie_res_desc *pcie;
f93f160b 3464 struct be_port_res_desc *port;
150d58c7 3465 struct be_nic_res_desc *nic;
a05f99db
VV		 3466 struct be_queue_info *mccq = &adapter->mcc_obj.q;
3467 struct be_dma_mem cmd;
150d58c7 3468 u32 desc_count;
a05f99db
VV		 3469 int status;
3470
3471 memset(&cmd, 0, sizeof(struct be_dma_mem));
150d58c7
VV		 3472 cmd.size = sizeof(struct be_cmd_resp_get_profile_config);
3473 cmd.va = pci_alloc_consistent(adapter->pdev, cmd.size, &cmd.dma);
3474 if (!cmd.va)
a05f99db 3475 return -ENOMEM;
a05f99db
VV		 3476
3477 if (!mccq->created)
3478 status = be_cmd_get_profile_config_mbox(adapter, domain, &cmd);
3479 else
3480 status = be_cmd_get_profile_config_mccq(adapter, domain, &cmd);
150d58c7
VV		 3481 if (status)
3482 goto err;
abb93951 3483
150d58c7
VV		 3484 resp = cmd.va;
3485 desc_count = le32_to_cpu(resp->desc_count);
abb93951 3486
150d58c7
VV		 3487 pcie = be_get_pcie_desc(adapter->pdev->devfn, resp->func_param,
3488 desc_count);
3489 if (pcie)
92bf14ab 3490 res->max_vfs = le16_to_cpu(pcie->num_vfs);
150d58c7 3491
f93f160b
VV		 3492 port = be_get_port_desc(resp->func_param, desc_count);
3493 if (port)
3494 adapter->mc_type = port->mc_type;
3495
150d58c7 3496 nic = be_get_nic_desc(resp->func_param, desc_count);
92bf14ab
SP		 3497 if (nic)
3498 be_copy_nic_desc(res, nic);
3499
abb93951 3500err:
a05f99db 3501 if (cmd.va)
150d58c7 3502 pci_free_consistent(adapter->pdev, cmd.size, cmd.va, cmd.dma);
abb93951
PR		 3503 return status;
3504}
3505
a401801c
SP		 3506int be_cmd_set_profile_config(struct be_adapter *adapter, void *desc,
3507 int size, u8 version, u8 domain)
d5c18473 3508{
d5c18473 3509 struct be_cmd_req_set_profile_config *req;
a401801c 3510 struct be_mcc_wrb *wrb;
d5c18473
PR		 3511 int status;
3512
3513 spin_lock_bh(&adapter->mcc_lock);
3514
3515 wrb = wrb_from_mccq(adapter);
3516 if (!wrb) {
3517 status = -EBUSY;
3518 goto err;
3519 }
3520
3521 req = embedded_payload(wrb);
d5c18473
PR		 3522 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3523 OPCODE_COMMON_SET_PROFILE_CONFIG, sizeof(*req),
3524 wrb, NULL);
a401801c 3525 req->hdr.version = version;
d5c18473
PR		 3526 req->hdr.domain = domain;
3527 req->desc_count = cpu_to_le32(1);
a401801c
SP		 3528 memcpy(req->desc, desc, size);
3529
d5c18473
PR		 3530 status = be_mcc_notify_wait(adapter);
3531err:
3532 spin_unlock_bh(&adapter->mcc_lock);
3533 return status;
3534}
3535
a401801c
SP		 3536/* Mark all fields invalid */
3537void be_reset_nic_desc(struct be_nic_res_desc *nic)
3538{
3539 memset(nic, 0, sizeof(*nic));
3540 nic->unicast_mac_count = 0xFFFF;
3541 nic->mcc_count = 0xFFFF;
3542 nic->vlan_count = 0xFFFF;
3543 nic->mcast_mac_count = 0xFFFF;
3544 nic->txq_count = 0xFFFF;
3545 nic->rq_count = 0xFFFF;
3546 nic->rssq_count = 0xFFFF;
3547 nic->lro_count = 0xFFFF;
3548 nic->cq_count = 0xFFFF;
3549 nic->toe_conn_count = 0xFFFF;
3550 nic->eq_count = 0xFFFF;
3551 nic->link_param = 0xFF;
3552 nic->acpi_params = 0xFF;
3553 nic->wol_param = 0x0F;
3554 nic->bw_min = 0xFFFFFFFF;
3555 nic->bw_max = 0xFFFFFFFF;
3556}
3557
3558int be_cmd_config_qos(struct be_adapter *adapter, u32 bps, u8 domain)
3559{
3560 if (lancer_chip(adapter)) {
3561 struct be_nic_res_desc nic_desc;
3562
3563 be_reset_nic_desc(&nic_desc);
3564 nic_desc.hdr.desc_type = NIC_RESOURCE_DESC_TYPE_V0;
3565 nic_desc.hdr.desc_len = RESOURCE_DESC_SIZE_V0;
3566 nic_desc.flags = (1 << QUN_SHIFT) | (1 << IMM_SHIFT) |
3567 (1 << NOSV_SHIFT);
3568 nic_desc.pf_num = adapter->pf_number;
3569 nic_desc.vf_num = domain;
3570 nic_desc.bw_max = cpu_to_le32(bps);
3571
3572 return be_cmd_set_profile_config(adapter, &nic_desc,
3573 RESOURCE_DESC_SIZE_V0,
3574 0, domain);
3575 } else {
3576 return be_cmd_set_qos(adapter, bps, domain);
3577 }
3578}
3579
3580int be_cmd_manage_iface(struct be_adapter *adapter, u32 iface, u8 op)
3581{
3582 struct be_mcc_wrb *wrb;
3583 struct be_cmd_req_manage_iface_filters *req;
3584 int status;
3585
3586 if (iface == 0xFFFFFFFF)
3587 return -1;
3588
3589 spin_lock_bh(&adapter->mcc_lock);
3590
3591 wrb = wrb_from_mccq(adapter);
3592 if (!wrb) {
3593 status = -EBUSY;
3594 goto err;
3595 }
3596 req = embedded_payload(wrb);
3597
3598 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3599 OPCODE_COMMON_MANAGE_IFACE_FILTERS, sizeof(*req),
3600 wrb, NULL);
3601 req->op = op;
3602 req->target_iface_id = cpu_to_le32(iface);
3603
3604 status = be_mcc_notify_wait(adapter);
3605err:
3606 spin_unlock_bh(&adapter->mcc_lock);
3607 return status;
3608}
3609
3610int be_cmd_set_vxlan_port(struct be_adapter *adapter, __be16 port)
3611{
3612 struct be_port_res_desc port_desc;
3613
3614 memset(&port_desc, 0, sizeof(port_desc));
3615 port_desc.hdr.desc_type = PORT_RESOURCE_DESC_TYPE_V1;
3616 port_desc.hdr.desc_len = RESOURCE_DESC_SIZE_V1;
3617 port_desc.flags = (1 << IMM_SHIFT) | (1 << NOSV_SHIFT);
3618 port_desc.link_num = adapter->hba_port_num;
3619 if (port) {
3620 port_desc.nv_flags = NV_TYPE_VXLAN | (1 << SOCVID_SHIFT) |
3621 (1 << RCVID_SHIFT);
3622 port_desc.nv_port = swab16(port);
3623 } else {
3624 port_desc.nv_flags = NV_TYPE_DISABLED;
3625 port_desc.nv_port = 0;
3626 }
3627
3628 return be_cmd_set_profile_config(adapter, &port_desc,
3629 RESOURCE_DESC_SIZE_V1, 1, 0);
3630}
3631
4c876616
SP		 3632int be_cmd_get_if_id(struct be_adapter *adapter, struct be_vf_cfg *vf_cfg,
3633 int vf_num)
3634{
3635 struct be_mcc_wrb *wrb;
3636 struct be_cmd_req_get_iface_list *req;
3637 struct be_cmd_resp_get_iface_list *resp;
3638 int status;
3639
3640 spin_lock_bh(&adapter->mcc_lock);
3641
3642 wrb = wrb_from_mccq(adapter);
3643 if (!wrb) {
3644 status = -EBUSY;
3645 goto err;
3646 }
3647 req = embedded_payload(wrb);
3648
3649 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3650 OPCODE_COMMON_GET_IFACE_LIST, sizeof(*resp),
3651 wrb, NULL);
3652 req->hdr.domain = vf_num + 1;
3653
3654 status = be_mcc_notify_wait(adapter);
3655 if (!status) {
3656 resp = (struct be_cmd_resp_get_iface_list *)req;
3657 vf_cfg->if_handle = le32_to_cpu(resp->if_desc.if_id);
3658 }
3659
3660err:
3661 spin_unlock_bh(&adapter->mcc_lock);
3662 return status;
3663}
3664
5c510811
SK		 3665static int lancer_wait_idle(struct be_adapter *adapter)
3666{
3667#define SLIPORT_IDLE_TIMEOUT 30
3668 u32 reg_val;
3669 int status = 0, i;
3670
3671 for (i = 0; i < SLIPORT_IDLE_TIMEOUT; i++) {
3672 reg_val = ioread32(adapter->db + PHYSDEV_CONTROL_OFFSET);
3673 if ((reg_val & PHYSDEV_CONTROL_INP_MASK) == 0)
3674 break;
3675
3676 ssleep(1);
3677 }
3678
3679 if (i == SLIPORT_IDLE_TIMEOUT)
3680 status = -1;
3681
3682 return status;
3683}
3684
3685int lancer_physdev_ctrl(struct be_adapter *adapter, u32 mask)
3686{
3687 int status = 0;
3688
3689 status = lancer_wait_idle(adapter);
3690 if (status)
3691 return status;
3692
3693 iowrite32(mask, adapter->db + PHYSDEV_CONTROL_OFFSET);
3694
3695 return status;
3696}
3697
3698/* Routine to check whether dump image is present or not */
3699bool dump_present(struct be_adapter *adapter)
3700{
3701 u32 sliport_status = 0;
3702
3703 sliport_status = ioread32(adapter->db + SLIPORT_STATUS_OFFSET);
3704 return !!(sliport_status & SLIPORT_STATUS_DIP_MASK);
3705}
3706
3707int lancer_initiate_dump(struct be_adapter *adapter)
3708{
3709 int status;
3710
3711 /* give firmware reset and diagnostic dump */
3712 status = lancer_physdev_ctrl(adapter, PHYSDEV_CONTROL_FW_RESET_MASK |
3713 PHYSDEV_CONTROL_DD_MASK);
3714 if (status < 0) {
3715 dev_err(&adapter->pdev->dev, "Firmware reset failed\n");
3716 return status;
3717 }
3718
3719 status = lancer_wait_idle(adapter);
3720 if (status)
3721 return status;
3722
3723 if (!dump_present(adapter)) {
3724 dev_err(&adapter->pdev->dev, "Dump image not present\n");
3725 return -1;
3726 }
3727
3728 return 0;
3729}
3730
dcf7ebba
PR		 3731/* Uses sync mcc */
3732int be_cmd_enable_vf(struct be_adapter *adapter, u8 domain)
3733{
3734 struct be_mcc_wrb *wrb;
3735 struct be_cmd_enable_disable_vf *req;
3736 int status;
3737
0599863d 3738 if (BEx_chip(adapter))
dcf7ebba
PR		 3739 return 0;
3740
3741 spin_lock_bh(&adapter->mcc_lock);
3742
3743 wrb = wrb_from_mccq(adapter);
3744 if (!wrb) {
3745 status = -EBUSY;
3746 goto err;
3747 }
3748
3749 req = embedded_payload(wrb);
3750
3751 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3752 OPCODE_COMMON_ENABLE_DISABLE_VF, sizeof(*req),
3753 wrb, NULL);
3754
3755 req->hdr.domain = domain;
3756 req->enable = 1;
3757 status = be_mcc_notify_wait(adapter);
3758err:
3759 spin_unlock_bh(&adapter->mcc_lock);
3760 return status;
3761}
3762
68c45a2d
SK		 3763int be_cmd_intr_set(struct be_adapter *adapter, bool intr_enable)
3764{
3765 struct be_mcc_wrb *wrb;
3766 struct be_cmd_req_intr_set *req;
3767 int status;
3768
3769 if (mutex_lock_interruptible(&adapter->mbox_lock))
3770 return -1;
3771
3772 wrb = wrb_from_mbox(adapter);
3773
3774 req = embedded_payload(wrb);
3775
3776 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3777 OPCODE_COMMON_SET_INTERRUPT_ENABLE, sizeof(*req),
3778 wrb, NULL);
3779
3780 req->intr_enabled = intr_enable;
3781
3782 status = be_mbox_notify_wait(adapter);
3783
3784 mutex_unlock(&adapter->mbox_lock);
3785 return status;
3786}
3787
542963b7
VV		 3788/* Uses MBOX */
3789int be_cmd_get_active_profile(struct be_adapter *adapter, u16 *profile_id)
3790{
3791 struct be_cmd_req_get_active_profile *req;
3792 struct be_mcc_wrb *wrb;
3793 int status;
3794
3795 if (mutex_lock_interruptible(&adapter->mbox_lock))
3796 return -1;
3797
3798 wrb = wrb_from_mbox(adapter);
3799 if (!wrb) {
3800 status = -EBUSY;
3801 goto err;
3802 }
3803
3804 req = embedded_payload(wrb);
3805
3806 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3807 OPCODE_COMMON_GET_ACTIVE_PROFILE, sizeof(*req),
3808 wrb, NULL);
3809
3810 status = be_mbox_notify_wait(adapter);
3811 if (!status) {
3812 struct be_cmd_resp_get_active_profile *resp =
3813 embedded_payload(wrb);
3814 *profile_id = le16_to_cpu(resp->active_profile_id);
3815 }
3816
3817err:
3818 mutex_unlock(&adapter->mbox_lock);
3819 return status;
3820}
3821
bdce2ad7
SR		 3822int be_cmd_set_logical_link_config(struct be_adapter *adapter,
3823 int link_state, u8 domain)
3824{
3825 struct be_mcc_wrb *wrb;
3826 struct be_cmd_req_set_ll_link *req;
3827 int status;
3828
3829 if (BEx_chip(adapter) || lancer_chip(adapter))
3830 return 0;
3831
3832 spin_lock_bh(&adapter->mcc_lock);
3833
3834 wrb = wrb_from_mccq(adapter);
3835 if (!wrb) {
3836 status = -EBUSY;
3837 goto err;
3838 }
3839
3840 req = embedded_payload(wrb);
3841
3842 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3843 OPCODE_COMMON_SET_LOGICAL_LINK_CONFIG,
3844 sizeof(*req), wrb, NULL);
3845
3846 req->hdr.version = 1;
3847 req->hdr.domain = domain;
3848
3849 if (link_state == IFLA_VF_LINK_STATE_ENABLE)
3850 req->link_config |= 1;
3851
3852 if (link_state == IFLA_VF_LINK_STATE_AUTO)
3853 req->link_config |= 1 << PLINK_TRACK_SHIFT;
3854
3855 status = be_mcc_notify_wait(adapter);
3856err:
3857 spin_unlock_bh(&adapter->mcc_lock);
3858 return status;
3859}
3860
6a4ab669
PP		 3861int be_roce_mcc_cmd(void *netdev_handle, void *wrb_payload,
3862 int wrb_payload_size, u16 *cmd_status, u16 *ext_status)
3863{
3864 struct be_adapter *adapter = netdev_priv(netdev_handle);
3865 struct be_mcc_wrb *wrb;
3866 struct be_cmd_req_hdr *hdr = (struct be_cmd_req_hdr *) wrb_payload;
3867 struct be_cmd_req_hdr *req;
3868 struct be_cmd_resp_hdr *resp;
3869 int status;
3870
3871 spin_lock_bh(&adapter->mcc_lock);
3872
3873 wrb = wrb_from_mccq(adapter);
3874 if (!wrb) {
3875 status = -EBUSY;
3876 goto err;
3877 }
3878 req = embedded_payload(wrb);
3879 resp = embedded_payload(wrb);
3880
3881 be_wrb_cmd_hdr_prepare(req, hdr->subsystem,
3882 hdr->opcode, wrb_payload_size, wrb, NULL);
3883 memcpy(req, wrb_payload, wrb_payload_size);
3884 be_dws_cpu_to_le(req, wrb_payload_size);
3885
3886 status = be_mcc_notify_wait(adapter);
3887 if (cmd_status)
3888 *cmd_status = (status & 0xffff);
3889 if (ext_status)
3890 *ext_status = 0;
3891 memcpy(wrb_payload, resp, sizeof(*resp) + resp->response_length);
3892 be_dws_le_to_cpu(wrb_payload, sizeof(*resp) + resp->response_length);
3893err:
3894 spin_unlock_bh(&adapter->mcc_lock);
3895 return status;
3896}
3897EXPORT_SYMBOL(be_roce_mcc_cmd);
Linux kernel - Deliverables
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