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Merge tag 'for-4.1' of git://git.kernel.org/pub/scm/linux/kernel/git/kishon/linux...
[deliverable/linux.git] / drivers / net / ethernet / emulex / benet / be_cmds.c
CommitLineData
6b7c5b94 1/*
40263820 2 * Copyright (C) 2005 - 2014 Emulex
6b7c5b94
SP		 3 * All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License version 2
7 * as published by the Free Software Foundation. The full GNU General
8 * Public License is included in this distribution in the file called COPYING.
9 *
10 * Contact Information:
d2145cde 11 * linux-drivers@emulex.com
6b7c5b94 12 *
d2145cde
AK		 13 * Emulex
14 * 3333 Susan Street
15 * Costa Mesa, CA 92626
6b7c5b94
SP		 16 */
17
6a4ab669 18#include <linux/module.h>
6b7c5b94 19#include "be.h"
8788fdc2 20#include "be_cmds.h"
6b7c5b94 21
21252377
VV		 22static char *be_port_misconfig_evt_desc[] = {
23 "A valid SFP module detected",
24 "Optics faulted/ incorrectly installed/ not installed.",
25 "Optics of two types installed.",
26 "Incompatible optics.",
27 "Unknown port SFP status"
28};
29
30static char *be_port_misconfig_remedy_desc[] = {
31 "",
32 "Reseat optics. If issue not resolved, replace",
33 "Remove one optic or install matching pair of optics",
34 "Replace with compatible optics for card to function",
35 ""
36};
37
f25b119c
PR		 38static struct be_cmd_priv_map cmd_priv_map[] = {
39 {
40 OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG,
41 CMD_SUBSYSTEM_ETH,
42 BE_PRIV_LNKMGMT | BE_PRIV_VHADM |
43 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC
44 },
45 {
46 OPCODE_COMMON_GET_FLOW_CONTROL,
47 CMD_SUBSYSTEM_COMMON,
48 BE_PRIV_LNKQUERY | BE_PRIV_VHADM |
49 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC
50 },
51 {
52 OPCODE_COMMON_SET_FLOW_CONTROL,
53 CMD_SUBSYSTEM_COMMON,
54 BE_PRIV_LNKMGMT | BE_PRIV_VHADM |
55 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC
56 },
57 {
58 OPCODE_ETH_GET_PPORT_STATS,
59 CMD_SUBSYSTEM_ETH,
60 BE_PRIV_LNKMGMT | BE_PRIV_VHADM |
61 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC
62 },
63 {
64 OPCODE_COMMON_GET_PHY_DETAILS,
65 CMD_SUBSYSTEM_COMMON,
66 BE_PRIV_LNKMGMT | BE_PRIV_VHADM |
67 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC
68 }
69};
70
a2cc4e0b 71static bool be_cmd_allowed(struct be_adapter *adapter, u8 opcode, u8 subsystem)
f25b119c
PR		 72{
73 int i;
74 int num_entries = sizeof(cmd_priv_map)/sizeof(struct be_cmd_priv_map);
75 u32 cmd_privileges = adapter->cmd_privileges;
76
77 for (i = 0; i < num_entries; i++)
78 if (opcode == cmd_priv_map[i].opcode &&
79 subsystem == cmd_priv_map[i].subsystem)
80 if (!(cmd_privileges & cmd_priv_map[i].priv_mask))
81 return false;
82
83 return true;
84}
85
3de09455
SK		 86static inline void *embedded_payload(struct be_mcc_wrb *wrb)
87{
88 return wrb->payload.embedded_payload;
89}
609ff3bb 90
8788fdc2 91static void be_mcc_notify(struct be_adapter *adapter)
5fb379ee 92{
8788fdc2 93 struct be_queue_info *mccq = &adapter->mcc_obj.q;
5fb379ee
SP		 94 u32 val = 0;
95
6589ade0 96 if (be_error(adapter))
7acc2087 97 return;
7acc2087 98
5fb379ee
SP		 99 val |= mccq->id & DB_MCCQ_RING_ID_MASK;
100 val |= 1 << DB_MCCQ_NUM_POSTED_SHIFT;
f3eb62d2
SP		 101
102 wmb();
8788fdc2 103 iowrite32(val, adapter->db + DB_MCCQ_OFFSET);
5fb379ee
SP		 104}
105
106/* To check if valid bit is set, check the entire word as we don't know
107 * the endianness of the data (old entry is host endian while a new entry is
108 * little endian) */
efd2e40a 109static inline bool be_mcc_compl_is_new(struct be_mcc_compl *compl)
5fb379ee 110{
9e9ff4b7
SP		 111 u32 flags;
112
5fb379ee 113 if (compl->flags != 0) {
9e9ff4b7
SP		 114 flags = le32_to_cpu(compl->flags);
115 if (flags & CQE_FLAGS_VALID_MASK) {
116 compl->flags = flags;
117 return true;
118 }
5fb379ee 119 }
9e9ff4b7 120 return false;
5fb379ee
SP		 121}
122
123/* Need to reset the entire word that houses the valid bit */
efd2e40a 124static inline void be_mcc_compl_use(struct be_mcc_compl *compl)
5fb379ee
SP		 125{
126 compl->flags = 0;
127}
128
652bf646
PR		 129static struct be_cmd_resp_hdr *be_decode_resp_hdr(u32 tag0, u32 tag1)
130{
131 unsigned long addr;
132
133 addr = tag1;
134 addr = ((addr << 16) << 16) | tag0;
135 return (void *)addr;
136}
137
4c60005f
KA		 138static bool be_skip_err_log(u8 opcode, u16 base_status, u16 addl_status)
139{
140 if (base_status == MCC_STATUS_NOT_SUPPORTED ||
141 base_status == MCC_STATUS_ILLEGAL_REQUEST ||
142 addl_status == MCC_ADDL_STATUS_TOO_MANY_INTERFACES ||
143 (opcode == OPCODE_COMMON_WRITE_FLASHROM &&
144 (base_status == MCC_STATUS_ILLEGAL_FIELD ||
145 addl_status == MCC_ADDL_STATUS_FLASH_IMAGE_CRC_MISMATCH)))
146 return true;
147 else
148 return false;
149}
150
559b633f
SP		 151/* Place holder for all the async MCC cmds wherein the caller is not in a busy
152 * loop (has not issued be_mcc_notify_wait())
153 */
154static void be_async_cmd_process(struct be_adapter *adapter,
155 struct be_mcc_compl *compl,
156 struct be_cmd_resp_hdr *resp_hdr)
157{
158 enum mcc_base_status base_status = base_status(compl->status);
159 u8 opcode = 0, subsystem = 0;
160
161 if (resp_hdr) {
162 opcode = resp_hdr->opcode;
163 subsystem = resp_hdr->subsystem;
164 }
165
166 if (opcode == OPCODE_LOWLEVEL_LOOPBACK_TEST &&
167 subsystem == CMD_SUBSYSTEM_LOWLEVEL) {
168 complete(&adapter->et_cmd_compl);
169 return;
170 }
171
172 if ((opcode == OPCODE_COMMON_WRITE_FLASHROM ||
173 opcode == OPCODE_COMMON_WRITE_OBJECT) &&
174 subsystem == CMD_SUBSYSTEM_COMMON) {
175 adapter->flash_status = compl->status;
176 complete(&adapter->et_cmd_compl);
177 return;
178 }
179
180 if ((opcode == OPCODE_ETH_GET_STATISTICS ||
181 opcode == OPCODE_ETH_GET_PPORT_STATS) &&
182 subsystem == CMD_SUBSYSTEM_ETH &&
183 base_status == MCC_STATUS_SUCCESS) {
184 be_parse_stats(adapter);
185 adapter->stats_cmd_sent = false;
186 return;
187 }
188
189 if (opcode == OPCODE_COMMON_GET_CNTL_ADDITIONAL_ATTRIBUTES &&
190 subsystem == CMD_SUBSYSTEM_COMMON) {
191 if (base_status == MCC_STATUS_SUCCESS) {
192 struct be_cmd_resp_get_cntl_addnl_attribs *resp =
193 (void *)resp_hdr;
194 adapter->drv_stats.be_on_die_temperature =
195 resp->on_die_temperature;
196 } else {
197 adapter->be_get_temp_freq = 0;
198 }
199 return;
200 }
201}
202
8788fdc2 203static int be_mcc_compl_process(struct be_adapter *adapter,
652bf646 204 struct be_mcc_compl *compl)
5fb379ee 205{
4c60005f
KA		 206 enum mcc_base_status base_status;
207 enum mcc_addl_status addl_status;
652bf646
PR		 208 struct be_cmd_resp_hdr *resp_hdr;
209 u8 opcode = 0, subsystem = 0;
5fb379ee
SP		 210
211 /* Just swap the status to host endian; mcc tag is opaquely copied
212 * from mcc_wrb */
213 be_dws_le_to_cpu(compl, 4);
214
4c60005f
KA		 215 base_status = base_status(compl->status);
216 addl_status = addl_status(compl->status);
96c9b2e4 217
652bf646 218 resp_hdr = be_decode_resp_hdr(compl->tag0, compl->tag1);
652bf646
PR		 219 if (resp_hdr) {
220 opcode = resp_hdr->opcode;
221 subsystem = resp_hdr->subsystem;
222 }
223
559b633f 224 be_async_cmd_process(adapter, compl, resp_hdr);
3de09455 225
559b633f
SP		 226 if (base_status != MCC_STATUS_SUCCESS &&
227 !be_skip_err_log(opcode, base_status, addl_status)) {
4c60005f 228 if (base_status == MCC_STATUS_UNAUTHORIZED_REQUEST) {
97f1d8cd 229 dev_warn(&adapter->pdev->dev,
522609f2 230 "VF is not privileged to issue opcode %d-%d\n",
97f1d8cd 231 opcode, subsystem);
2b3f291b 232 } else {
97f1d8cd
VV		 233 dev_err(&adapter->pdev->dev,
234 "opcode %d-%d failed:status %d-%d\n",
4c60005f 235 opcode, subsystem, base_status, addl_status);
2b3f291b 236 }
5fb379ee 237 }
4c60005f 238 return compl->status;
5fb379ee
SP		 239}
240
a8f447bd 241/* Link state evt is a string of bytes; no need for endian swapping */
8788fdc2 242static void be_async_link_state_process(struct be_adapter *adapter,
3acf19d9 243 struct be_mcc_compl *compl)
a8f447bd 244{
3acf19d9
SP		 245 struct be_async_event_link_state *evt =
246 (struct be_async_event_link_state *)compl;
247
b236916a 248 /* When link status changes, link speed must be re-queried from FW */
42f11cf2 249 adapter->phy.link_speed = -1;
b236916a 250
bdce2ad7
SR		 251 /* On BEx the FW does not send a separate link status
252 * notification for physical and logical link.
253 * On other chips just process the logical link
254 * status notification
255 */
256 if (!BEx_chip(adapter) &&
2e177a5c
PR		 257 !(evt->port_link_status & LOGICAL_LINK_STATUS_MASK))
258 return;
259
b236916a
AK		 260 /* For the initial link status do not rely on the ASYNC event as
261 * it may not be received in some cases.
262 */
263 if (adapter->flags & BE_FLAGS_LINK_STATUS_INIT)
bdce2ad7
SR		 264 be_link_status_update(adapter,
265 evt->port_link_status & LINK_STATUS_MASK);
a8f447bd
SP		 266}
267
21252377
VV		 268static void be_async_port_misconfig_event_process(struct be_adapter *adapter,
269 struct be_mcc_compl *compl)
270{
271 struct be_async_event_misconfig_port *evt =
272 (struct be_async_event_misconfig_port *)compl;
273 u32 sfp_mismatch_evt = le32_to_cpu(evt->event_data_word1);
274 struct device *dev = &adapter->pdev->dev;
275 u8 port_misconfig_evt;
276
277 port_misconfig_evt =
278 ((sfp_mismatch_evt >> (adapter->hba_port_num * 8)) & 0xff);
279
280 /* Log an error message that would allow a user to determine
281 * whether the SFPs have an issue
282 */
283 dev_info(dev, "Port %c: %s %s", adapter->port_name,
284 be_port_misconfig_evt_desc[port_misconfig_evt],
285 be_port_misconfig_remedy_desc[port_misconfig_evt]);
286
287 if (port_misconfig_evt == INCOMPATIBLE_SFP)
288 adapter->flags |= BE_FLAGS_EVT_INCOMPATIBLE_SFP;
289}
290
cc4ce020
SK		 291/* Grp5 CoS Priority evt */
292static void be_async_grp5_cos_priority_process(struct be_adapter *adapter,
3acf19d9 293 struct be_mcc_compl *compl)
cc4ce020 294{
3acf19d9
SP		 295 struct be_async_event_grp5_cos_priority *evt =
296 (struct be_async_event_grp5_cos_priority *)compl;
297
cc4ce020
SK		 298 if (evt->valid) {
299 adapter->vlan_prio_bmap = evt->available_priority_bmap;
60964dd7 300 adapter->recommended_prio &= ~VLAN_PRIO_MASK;
cc4ce020
SK		 301 adapter->recommended_prio =
302 evt->reco_default_priority << VLAN_PRIO_SHIFT;
303 }
304}
305
323ff71e 306/* Grp5 QOS Speed evt: qos_link_speed is in units of 10 Mbps */
cc4ce020 307static void be_async_grp5_qos_speed_process(struct be_adapter *adapter,
3acf19d9 308 struct be_mcc_compl *compl)
cc4ce020 309{
3acf19d9
SP		 310 struct be_async_event_grp5_qos_link_speed *evt =
311 (struct be_async_event_grp5_qos_link_speed *)compl;
312
323ff71e
SP		 313 if (adapter->phy.link_speed >= 0 &&
314 evt->physical_port == adapter->port_num)
315 adapter->phy.link_speed = le16_to_cpu(evt->qos_link_speed) * 10;
cc4ce020
SK		 316}
317
3968fa1e
AK		 318/*Grp5 PVID evt*/
319static void be_async_grp5_pvid_state_process(struct be_adapter *adapter,
3acf19d9 320 struct be_mcc_compl *compl)
3968fa1e 321{
3acf19d9
SP		 322 struct be_async_event_grp5_pvid_state *evt =
323 (struct be_async_event_grp5_pvid_state *)compl;
324
bdac85b5 325 if (evt->enabled) {
939cf306 326 adapter->pvid = le16_to_cpu(evt->tag) & VLAN_VID_MASK;
bdac85b5
RN		 327 dev_info(&adapter->pdev->dev, "LPVID: %d\n", adapter->pvid);
328 } else {
3968fa1e 329 adapter->pvid = 0;
bdac85b5 330 }
3968fa1e
AK		 331}
332
cc4ce020 333static void be_async_grp5_evt_process(struct be_adapter *adapter,
3acf19d9 334 struct be_mcc_compl *compl)
cc4ce020 335{
3acf19d9
SP		 336 u8 event_type = (compl->flags >> ASYNC_EVENT_TYPE_SHIFT) &
337 ASYNC_EVENT_TYPE_MASK;
cc4ce020
SK		 338
339 switch (event_type) {
340 case ASYNC_EVENT_COS_PRIORITY:
3acf19d9
SP		 341 be_async_grp5_cos_priority_process(adapter, compl);
342 break;
cc4ce020 343 case ASYNC_EVENT_QOS_SPEED:
3acf19d9
SP		 344 be_async_grp5_qos_speed_process(adapter, compl);
345 break;
3968fa1e 346 case ASYNC_EVENT_PVID_STATE:
3acf19d9
SP		 347 be_async_grp5_pvid_state_process(adapter, compl);
348 break;
cc4ce020 349 default:
cc4ce020
SK		 350 break;
351 }
352}
353
bc0c3405 354static void be_async_dbg_evt_process(struct be_adapter *adapter,
3acf19d9 355 struct be_mcc_compl *cmp)
bc0c3405
AK		 356{
357 u8 event_type = 0;
504fbf1e 358 struct be_async_event_qnq *evt = (struct be_async_event_qnq *)cmp;
bc0c3405 359
3acf19d9
SP		 360 event_type = (cmp->flags >> ASYNC_EVENT_TYPE_SHIFT) &
361 ASYNC_EVENT_TYPE_MASK;
bc0c3405
AK		 362
363 switch (event_type) {
364 case ASYNC_DEBUG_EVENT_TYPE_QNQ:
365 if (evt->valid)
366 adapter->qnq_vid = le16_to_cpu(evt->vlan_tag);
367 adapter->flags |= BE_FLAGS_QNQ_ASYNC_EVT_RCVD;
368 break;
369 default:
05ccaa2b
VV		 370 dev_warn(&adapter->pdev->dev, "Unknown debug event 0x%x!\n",
371 event_type);
bc0c3405
AK		 372 break;
373 }
374}
375
21252377
VV		 376static void be_async_sliport_evt_process(struct be_adapter *adapter,
377 struct be_mcc_compl *cmp)
378{
379 u8 event_type = (cmp->flags >> ASYNC_EVENT_TYPE_SHIFT) &
380 ASYNC_EVENT_TYPE_MASK;
381
382 if (event_type == ASYNC_EVENT_PORT_MISCONFIG)
383 be_async_port_misconfig_event_process(adapter, cmp);
384}
385
3acf19d9 386static inline bool is_link_state_evt(u32 flags)
a8f447bd 387{
3acf19d9
SP		 388 return ((flags >> ASYNC_EVENT_CODE_SHIFT) & ASYNC_EVENT_CODE_MASK) ==
389 ASYNC_EVENT_CODE_LINK_STATE;
a8f447bd 390}
5fb379ee 391
3acf19d9 392static inline bool is_grp5_evt(u32 flags)
cc4ce020 393{
3acf19d9
SP		 394 return ((flags >> ASYNC_EVENT_CODE_SHIFT) & ASYNC_EVENT_CODE_MASK) ==
395 ASYNC_EVENT_CODE_GRP_5;
cc4ce020
SK		 396}
397
3acf19d9 398static inline bool is_dbg_evt(u32 flags)
bc0c3405 399{
3acf19d9
SP		 400 return ((flags >> ASYNC_EVENT_CODE_SHIFT) & ASYNC_EVENT_CODE_MASK) ==
401 ASYNC_EVENT_CODE_QNQ;
402}
403
21252377
VV		 404static inline bool is_sliport_evt(u32 flags)
405{
406 return ((flags >> ASYNC_EVENT_CODE_SHIFT) & ASYNC_EVENT_CODE_MASK) ==
407 ASYNC_EVENT_CODE_SLIPORT;
408}
409
3acf19d9
SP		 410static void be_mcc_event_process(struct be_adapter *adapter,
411 struct be_mcc_compl *compl)
412{
413 if (is_link_state_evt(compl->flags))
414 be_async_link_state_process(adapter, compl);
415 else if (is_grp5_evt(compl->flags))
416 be_async_grp5_evt_process(adapter, compl);
417 else if (is_dbg_evt(compl->flags))
418 be_async_dbg_evt_process(adapter, compl);
21252377
VV		 419 else if (is_sliport_evt(compl->flags))
420 be_async_sliport_evt_process(adapter, compl);
bc0c3405
AK		 421}
422
efd2e40a 423static struct be_mcc_compl *be_mcc_compl_get(struct be_adapter *adapter)
5fb379ee 424{
8788fdc2 425 struct be_queue_info *mcc_cq = &adapter->mcc_obj.cq;
efd2e40a 426 struct be_mcc_compl *compl = queue_tail_node(mcc_cq);
5fb379ee
SP		 427
428 if (be_mcc_compl_is_new(compl)) {
429 queue_tail_inc(mcc_cq);
430 return compl;
431 }
432 return NULL;
433}
434
7a1e9b20
SP		 435void be_async_mcc_enable(struct be_adapter *adapter)
436{
437 spin_lock_bh(&adapter->mcc_cq_lock);
438
439 be_cq_notify(adapter, adapter->mcc_obj.cq.id, true, 0);
440 adapter->mcc_obj.rearm_cq = true;
441
442 spin_unlock_bh(&adapter->mcc_cq_lock);
443}
444
445void be_async_mcc_disable(struct be_adapter *adapter)
446{
a323d9bf
SP		 447 spin_lock_bh(&adapter->mcc_cq_lock);
448
7a1e9b20 449 adapter->mcc_obj.rearm_cq = false;
a323d9bf
SP		 450 be_cq_notify(adapter, adapter->mcc_obj.cq.id, false, 0);
451
452 spin_unlock_bh(&adapter->mcc_cq_lock);
7a1e9b20
SP		 453}
454
10ef9ab4 455int be_process_mcc(struct be_adapter *adapter)
5fb379ee 456{
efd2e40a 457 struct be_mcc_compl *compl;
10ef9ab4 458 int num = 0, status = 0;
7a1e9b20 459 struct be_mcc_obj *mcc_obj = &adapter->mcc_obj;
5fb379ee 460
072a9c48 461 spin_lock(&adapter->mcc_cq_lock);
3acf19d9 462
8788fdc2 463 while ((compl = be_mcc_compl_get(adapter))) {
a8f447bd 464 if (compl->flags & CQE_FLAGS_ASYNC_MASK) {
3acf19d9 465 be_mcc_event_process(adapter, compl);
b31c50a7 466 } else if (compl->flags & CQE_FLAGS_COMPLETED_MASK) {
3acf19d9
SP		 467 status = be_mcc_compl_process(adapter, compl);
468 atomic_dec(&mcc_obj->q.used);
5fb379ee
SP		 469 }
470 be_mcc_compl_use(compl);
471 num++;
472 }
b31c50a7 473
10ef9ab4
SP		 474 if (num)
475 be_cq_notify(adapter, mcc_obj->cq.id, mcc_obj->rearm_cq, num);
476
072a9c48 477 spin_unlock(&adapter->mcc_cq_lock);
10ef9ab4 478 return status;
5fb379ee
SP		 479}
480
6ac7b687 481/* Wait till no more pending mcc requests are present */
b31c50a7 482static int be_mcc_wait_compl(struct be_adapter *adapter)
6ac7b687 483{
b31c50a7 484#define mcc_timeout 120000 /* 12s timeout */
10ef9ab4 485 int i, status = 0;
f31e50a8
SP		 486 struct be_mcc_obj *mcc_obj = &adapter->mcc_obj;
487
6ac7b687 488 for (i = 0; i < mcc_timeout; i++) {
6589ade0
SP		 489 if (be_error(adapter))
490 return -EIO;
491
072a9c48 492 local_bh_disable();
10ef9ab4 493 status = be_process_mcc(adapter);
072a9c48 494 local_bh_enable();
b31c50a7 495
f31e50a8 496 if (atomic_read(&mcc_obj->q.used) == 0)
6ac7b687
SP		 497 break;
498 udelay(100);
499 }
b31c50a7 500 if (i == mcc_timeout) {
6589ade0
SP		 501 dev_err(&adapter->pdev->dev, "FW not responding\n");
502 adapter->fw_timeout = true;
652bf646 503 return -EIO;
b31c50a7 504 }
f31e50a8 505 return status;
6ac7b687
SP		 506}
507
508/* Notify MCC requests and wait for completion */
b31c50a7 509static int be_mcc_notify_wait(struct be_adapter *adapter)
6ac7b687 510{
652bf646
PR		 511 int status;
512 struct be_mcc_wrb *wrb;
513 struct be_mcc_obj *mcc_obj = &adapter->mcc_obj;
514 u16 index = mcc_obj->q.head;
515 struct be_cmd_resp_hdr *resp;
516
517 index_dec(&index, mcc_obj->q.len);
518 wrb = queue_index_node(&mcc_obj->q, index);
519
520 resp = be_decode_resp_hdr(wrb->tag0, wrb->tag1);
521
8788fdc2 522 be_mcc_notify(adapter);
652bf646
PR		 523
524 status = be_mcc_wait_compl(adapter);
525 if (status == -EIO)
526 goto out;
527
4c60005f
KA		 528 status = (resp->base_status |
529 ((resp->addl_status & CQE_ADDL_STATUS_MASK) <<
530 CQE_ADDL_STATUS_SHIFT));
652bf646
PR		 531out:
532 return status;
6ac7b687
SP		 533}
534
5f0b849e 535static int be_mbox_db_ready_wait(struct be_adapter *adapter, void __iomem *db)
6b7c5b94 536{
f25b03a7 537 int msecs = 0;
6b7c5b94
SP		 538 u32 ready;
539
540 do {
6589ade0
SP		 541 if (be_error(adapter))
542 return -EIO;
543
cf588477 544 ready = ioread32(db);
434b3648 545 if (ready == 0xffffffff)
cf588477 546 return -1;
cf588477
SP		 547
548 ready &= MPU_MAILBOX_DB_RDY_MASK;
6b7c5b94
SP		 549 if (ready)
550 break;
551
f25b03a7 552 if (msecs > 4000) {
6589ade0
SP		 553 dev_err(&adapter->pdev->dev, "FW not responding\n");
554 adapter->fw_timeout = true;
f67ef7ba 555 be_detect_error(adapter);
6b7c5b94
SP		 556 return -1;
557 }
558
1dbf53a2 559 msleep(1);
f25b03a7 560 msecs++;
6b7c5b94
SP		 561 } while (true);
562
563 return 0;
564}
565
566/*
567 * Insert the mailbox address into the doorbell in two steps
5fb379ee 568 * Polls on the mbox doorbell till a command completion (or a timeout) occurs
6b7c5b94 569 */
b31c50a7 570static int be_mbox_notify_wait(struct be_adapter *adapter)
6b7c5b94
SP		 571{
572 int status;
6b7c5b94 573 u32 val = 0;
8788fdc2
SP		 574 void __iomem *db = adapter->db + MPU_MAILBOX_DB_OFFSET;
575 struct be_dma_mem *mbox_mem = &adapter->mbox_mem;
6b7c5b94 576 struct be_mcc_mailbox *mbox = mbox_mem->va;
efd2e40a 577 struct be_mcc_compl *compl = &mbox->compl;
6b7c5b94 578
cf588477
SP		 579 /* wait for ready to be set */
580 status = be_mbox_db_ready_wait(adapter, db);
581 if (status != 0)
582 return status;
583
6b7c5b94
SP		 584 val |= MPU_MAILBOX_DB_HI_MASK;
585 /* at bits 2 - 31 place mbox dma addr msb bits 34 - 63 */
586 val |= (upper_32_bits(mbox_mem->dma) >> 2) << 2;
587 iowrite32(val, db);
588
589 /* wait for ready to be set */
5f0b849e 590 status = be_mbox_db_ready_wait(adapter, db);
6b7c5b94
SP		 591 if (status != 0)
592 return status;
593
594 val = 0;
6b7c5b94
SP		 595 /* at bits 2 - 31 place mbox dma addr lsb bits 4 - 33 */
596 val |= (u32)(mbox_mem->dma >> 4) << 2;
597 iowrite32(val, db);
598
5f0b849e 599 status = be_mbox_db_ready_wait(adapter, db);
6b7c5b94
SP		 600 if (status != 0)
601 return status;
602
5fb379ee 603 /* A cq entry has been made now */
efd2e40a
SP		 604 if (be_mcc_compl_is_new(compl)) {
605 status = be_mcc_compl_process(adapter, &mbox->compl);
606 be_mcc_compl_use(compl);
5fb379ee
SP		 607 if (status)
608 return status;
609 } else {
5f0b849e 610 dev_err(&adapter->pdev->dev, "invalid mailbox completion\n");
6b7c5b94
SP		 611 return -1;
612 }
5fb379ee 613 return 0;
6b7c5b94
SP		 614}
615
c5b3ad4c 616static u16 be_POST_stage_get(struct be_adapter *adapter)
6b7c5b94 617{
fe6d2a38
SP		 618 u32 sem;
619
c5b3ad4c
SP		 620 if (BEx_chip(adapter))
621 sem = ioread32(adapter->csr + SLIPORT_SEMAPHORE_OFFSET_BEx);
6b7c5b94 622 else
c5b3ad4c
SP		 623 pci_read_config_dword(adapter->pdev,
624 SLIPORT_SEMAPHORE_OFFSET_SH, &sem);
625
626 return sem & POST_STAGE_MASK;
6b7c5b94
SP		 627}
628
87f20c26 629static int lancer_wait_ready(struct be_adapter *adapter)
bf99e50d
PR		 630{
631#define SLIPORT_READY_TIMEOUT 30
632 u32 sliport_status;
e673244a 633 int i;
bf99e50d
PR		 634
635 for (i = 0; i < SLIPORT_READY_TIMEOUT; i++) {
636 sliport_status = ioread32(adapter->db + SLIPORT_STATUS_OFFSET);
637 if (sliport_status & SLIPORT_STATUS_RDY_MASK)
638 break;
639
640 msleep(1000);
641 }
642
643 if (i == SLIPORT_READY_TIMEOUT)
e673244a 644 return sliport_status ? : -1;
bf99e50d 645
e673244a 646 return 0;
bf99e50d
PR		 647}
648
67297ad8
PR		 649static bool lancer_provisioning_error(struct be_adapter *adapter)
650{
651 u32 sliport_status = 0, sliport_err1 = 0, sliport_err2 = 0;
03d28ffe 652
67297ad8
PR		 653 sliport_status = ioread32(adapter->db + SLIPORT_STATUS_OFFSET);
654 if (sliport_status & SLIPORT_STATUS_ERR_MASK) {
a2cc4e0b
SP		 655 sliport_err1 = ioread32(adapter->db + SLIPORT_ERROR1_OFFSET);
656 sliport_err2 = ioread32(adapter->db + SLIPORT_ERROR2_OFFSET);
67297ad8
PR		 657
658 if (sliport_err1 == SLIPORT_ERROR_NO_RESOURCE1 &&
659 sliport_err2 == SLIPORT_ERROR_NO_RESOURCE2)
660 return true;
661 }
662 return false;
663}
664
bf99e50d
PR		 665int lancer_test_and_set_rdy_state(struct be_adapter *adapter)
666{
667 int status;
668 u32 sliport_status, err, reset_needed;
67297ad8
PR		 669 bool resource_error;
670
671 resource_error = lancer_provisioning_error(adapter);
672 if (resource_error)
01e5b2c4 673 return -EAGAIN;
67297ad8 674
bf99e50d
PR		 675 status = lancer_wait_ready(adapter);
676 if (!status) {
677 sliport_status = ioread32(adapter->db + SLIPORT_STATUS_OFFSET);
678 err = sliport_status & SLIPORT_STATUS_ERR_MASK;
679 reset_needed = sliport_status & SLIPORT_STATUS_RN_MASK;
680 if (err && reset_needed) {
681 iowrite32(SLI_PORT_CONTROL_IP_MASK,
682 adapter->db + SLIPORT_CONTROL_OFFSET);
683
e673244a 684 /* check if adapter has corrected the error */
bf99e50d
PR		 685 status = lancer_wait_ready(adapter);
686 sliport_status = ioread32(adapter->db +
687 SLIPORT_STATUS_OFFSET);
688 sliport_status &= (SLIPORT_STATUS_ERR_MASK |
689 SLIPORT_STATUS_RN_MASK);
690 if (status || sliport_status)
691 status = -1;
692 } else if (err || reset_needed) {
693 status = -1;
694 }
695 }
67297ad8
PR		 696 /* Stop error recovery if error is not recoverable.
697 * No resource error is temporary errors and will go away
698 * when PF provisions resources.
699 */
700 resource_error = lancer_provisioning_error(adapter);
01e5b2c4
SK		 701 if (resource_error)
702 status = -EAGAIN;
67297ad8 703
bf99e50d
PR		 704 return status;
705}
706
707int be_fw_wait_ready(struct be_adapter *adapter)
6b7c5b94 708{
43a04fdc
SP		 709 u16 stage;
710 int status, timeout = 0;
6ed35eea 711 struct device *dev = &adapter->pdev->dev;
6b7c5b94 712
bf99e50d
PR		 713 if (lancer_chip(adapter)) {
714 status = lancer_wait_ready(adapter);
e673244a
KA		 715 if (status) {
716 stage = status;
717 goto err;
718 }
719 return 0;
bf99e50d
PR		 720 }
721
43a04fdc 722 do {
c5b3ad4c 723 stage = be_POST_stage_get(adapter);
66d29cbc 724 if (stage == POST_STAGE_ARMFW_RDY)
43a04fdc 725 return 0;
66d29cbc 726
a2cc4e0b 727 dev_info(dev, "Waiting for POST, %ds elapsed\n", timeout);
66d29cbc
GS		 728 if (msleep_interruptible(2000)) {
729 dev_err(dev, "Waiting for POST aborted\n");
730 return -EINTR;
43a04fdc 731 }
66d29cbc 732 timeout += 2;
3ab81b5f 733 } while (timeout < 60);
6b7c5b94 734
e673244a
KA		 735err:
736 dev_err(dev, "POST timeout; stage=%#x\n", stage);
43a04fdc 737 return -1;
6b7c5b94
SP		 738}
739
6b7c5b94
SP		 740static inline struct be_sge *nonembedded_sgl(struct be_mcc_wrb *wrb)
741{
742 return &wrb->payload.sgl[0];
743}
744
a2cc4e0b 745static inline void fill_wrb_tags(struct be_mcc_wrb *wrb, unsigned long addr)
bea50988
SP		 746{
747 wrb->tag0 = addr & 0xFFFFFFFF;
748 wrb->tag1 = upper_32_bits(addr);
749}
6b7c5b94
SP		 750
751/* Don't touch the hdr after it's prepared */
106df1e3
SK		 752/* mem will be NULL for embedded commands */
753static void be_wrb_cmd_hdr_prepare(struct be_cmd_req_hdr *req_hdr,
a2cc4e0b
SP		 754 u8 subsystem, u8 opcode, int cmd_len,
755 struct be_mcc_wrb *wrb,
756 struct be_dma_mem *mem)
6b7c5b94 757{
106df1e3
SK		 758 struct be_sge *sge;
759
6b7c5b94
SP		 760 req_hdr->opcode = opcode;
761 req_hdr->subsystem = subsystem;
762 req_hdr->request_length = cpu_to_le32(cmd_len - sizeof(*req_hdr));
07793d33 763 req_hdr->version = 0;
bea50988 764 fill_wrb_tags(wrb, (ulong) req_hdr);
106df1e3
SK		 765 wrb->payload_length = cmd_len;
766 if (mem) {
767 wrb->embedded |= (1 & MCC_WRB_SGE_CNT_MASK) <<
768 MCC_WRB_SGE_CNT_SHIFT;
769 sge = nonembedded_sgl(wrb);
770 sge->pa_hi = cpu_to_le32(upper_32_bits(mem->dma));
771 sge->pa_lo = cpu_to_le32(mem->dma & 0xFFFFFFFF);
772 sge->len = cpu_to_le32(mem->size);
773 } else
774 wrb->embedded |= MCC_WRB_EMBEDDED_MASK;
775 be_dws_cpu_to_le(wrb, 8);
6b7c5b94
SP		 776}
777
778static void be_cmd_page_addrs_prepare(struct phys_addr *pages, u32 max_pages,
a2cc4e0b 779 struct be_dma_mem *mem)
6b7c5b94
SP		 780{
781 int i, buf_pages = min(PAGES_4K_SPANNED(mem->va, mem->size), max_pages);
782 u64 dma = (u64)mem->dma;
783
784 for (i = 0; i < buf_pages; i++) {
785 pages[i].lo = cpu_to_le32(dma & 0xFFFFFFFF);
786 pages[i].hi = cpu_to_le32(upper_32_bits(dma));
787 dma += PAGE_SIZE_4K;
788 }
789}
790
b31c50a7 791static inline struct be_mcc_wrb *wrb_from_mbox(struct be_adapter *adapter)
6b7c5b94 792{
b31c50a7
SP		 793 struct be_dma_mem *mbox_mem = &adapter->mbox_mem;
794 struct be_mcc_wrb *wrb
795 = &((struct be_mcc_mailbox *)(mbox_mem->va))->wrb;
796 memset(wrb, 0, sizeof(*wrb));
797 return wrb;
6b7c5b94
SP		 798}
799
b31c50a7 800static struct be_mcc_wrb *wrb_from_mccq(struct be_adapter *adapter)
5fb379ee 801{
b31c50a7
SP		 802 struct be_queue_info *mccq = &adapter->mcc_obj.q;
803 struct be_mcc_wrb *wrb;
804
aa790db9
PR		 805 if (!mccq->created)
806 return NULL;
807
4d277125 808 if (atomic_read(&mccq->used) >= mccq->len)
713d0394 809 return NULL;
713d0394 810
b31c50a7
SP		 811 wrb = queue_head_node(mccq);
812 queue_head_inc(mccq);
813 atomic_inc(&mccq->used);
814 memset(wrb, 0, sizeof(*wrb));
5fb379ee
SP		 815 return wrb;
816}
817
bea50988
SP		 818static bool use_mcc(struct be_adapter *adapter)
819{
820 return adapter->mcc_obj.q.created;
821}
822
823/* Must be used only in process context */
824static int be_cmd_lock(struct be_adapter *adapter)
825{
826 if (use_mcc(adapter)) {
827 spin_lock_bh(&adapter->mcc_lock);
828 return 0;
829 } else {
830 return mutex_lock_interruptible(&adapter->mbox_lock);
831 }
832}
833
834/* Must be used only in process context */
835static void be_cmd_unlock(struct be_adapter *adapter)
836{
837 if (use_mcc(adapter))
838 spin_unlock_bh(&adapter->mcc_lock);
839 else
840 return mutex_unlock(&adapter->mbox_lock);
841}
842
843static struct be_mcc_wrb *be_cmd_copy(struct be_adapter *adapter,
844 struct be_mcc_wrb *wrb)
845{
846 struct be_mcc_wrb *dest_wrb;
847
848 if (use_mcc(adapter)) {
849 dest_wrb = wrb_from_mccq(adapter);
850 if (!dest_wrb)
851 return NULL;
852 } else {
853 dest_wrb = wrb_from_mbox(adapter);
854 }
855
856 memcpy(dest_wrb, wrb, sizeof(*wrb));
857 if (wrb->embedded & cpu_to_le32(MCC_WRB_EMBEDDED_MASK))
858 fill_wrb_tags(dest_wrb, (ulong) embedded_payload(wrb));
859
860 return dest_wrb;
861}
862
863/* Must be used only in process context */
864static int be_cmd_notify_wait(struct be_adapter *adapter,
865 struct be_mcc_wrb *wrb)
866{
867 struct be_mcc_wrb *dest_wrb;
868 int status;
869
870 status = be_cmd_lock(adapter);
871 if (status)
872 return status;
873
874 dest_wrb = be_cmd_copy(adapter, wrb);
875 if (!dest_wrb)
876 return -EBUSY;
877
878 if (use_mcc(adapter))
879 status = be_mcc_notify_wait(adapter);
880 else
881 status = be_mbox_notify_wait(adapter);
882
883 if (!status)
884 memcpy(wrb, dest_wrb, sizeof(*wrb));
885
886 be_cmd_unlock(adapter);
887 return status;
888}
889
2243e2e9
SP		 890/* Tell fw we're about to start firing cmds by writing a
891 * special pattern across the wrb hdr; uses mbox
892 */
893int be_cmd_fw_init(struct be_adapter *adapter)
894{
895 u8 *wrb;
896 int status;
897
bf99e50d
PR		 898 if (lancer_chip(adapter))
899 return 0;
900
2984961c
IV		 901 if (mutex_lock_interruptible(&adapter->mbox_lock))
902 return -1;
2243e2e9
SP		 903
904 wrb = (u8 *)wrb_from_mbox(adapter);
359a972f
SP		 905 *wrb++ = 0xFF;
906 *wrb++ = 0x12;
907 *wrb++ = 0x34;
908 *wrb++ = 0xFF;
909 *wrb++ = 0xFF;
910 *wrb++ = 0x56;
911 *wrb++ = 0x78;
912 *wrb = 0xFF;
2243e2e9
SP		 913
914 status = be_mbox_notify_wait(adapter);
915
2984961c 916 mutex_unlock(&adapter->mbox_lock);
2243e2e9
SP		 917 return status;
918}
919
920/* Tell fw we're done with firing cmds by writing a
921 * special pattern across the wrb hdr; uses mbox
922 */
923int be_cmd_fw_clean(struct be_adapter *adapter)
924{
925 u8 *wrb;
926 int status;
927
bf99e50d
PR		 928 if (lancer_chip(adapter))
929 return 0;
930
2984961c
IV		 931 if (mutex_lock_interruptible(&adapter->mbox_lock))
932 return -1;
2243e2e9
SP		 933
934 wrb = (u8 *)wrb_from_mbox(adapter);
935 *wrb++ = 0xFF;
936 *wrb++ = 0xAA;
937 *wrb++ = 0xBB;
938 *wrb++ = 0xFF;
939 *wrb++ = 0xFF;
940 *wrb++ = 0xCC;
941 *wrb++ = 0xDD;
942 *wrb = 0xFF;
943
944 status = be_mbox_notify_wait(adapter);
945
2984961c 946 mutex_unlock(&adapter->mbox_lock);
2243e2e9
SP		 947 return status;
948}
bf99e50d 949
f2f781a7 950int be_cmd_eq_create(struct be_adapter *adapter, struct be_eq_obj *eqo)
6b7c5b94 951{
b31c50a7
SP		 952 struct be_mcc_wrb *wrb;
953 struct be_cmd_req_eq_create *req;
f2f781a7
SP		 954 struct be_dma_mem *q_mem = &eqo->q.dma_mem;
955 int status, ver = 0;
6b7c5b94 956
2984961c
IV		 957 if (mutex_lock_interruptible(&adapter->mbox_lock))
958 return -1;
b31c50a7
SP		 959
960 wrb = wrb_from_mbox(adapter);
961 req = embedded_payload(wrb);
6b7c5b94 962
106df1e3 963 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 964 OPCODE_COMMON_EQ_CREATE, sizeof(*req), wrb,
965 NULL);
6b7c5b94 966
f2f781a7
SP		 967 /* Support for EQ_CREATEv2 available only SH-R onwards */
968 if (!(BEx_chip(adapter) || lancer_chip(adapter)))
969 ver = 2;
970
971 req->hdr.version = ver;
6b7c5b94
SP		 972 req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
973
6b7c5b94
SP		 974 AMAP_SET_BITS(struct amap_eq_context, valid, req->context, 1);
975 /* 4byte eqe*/
976 AMAP_SET_BITS(struct amap_eq_context, size, req->context, 0);
977 AMAP_SET_BITS(struct amap_eq_context, count, req->context,
f2f781a7 978 __ilog2_u32(eqo->q.len / 256));
6b7c5b94
SP		 979 be_dws_cpu_to_le(req->context, sizeof(req->context));
980
981 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
982
b31c50a7 983 status = be_mbox_notify_wait(adapter);
6b7c5b94 984 if (!status) {
b31c50a7 985 struct be_cmd_resp_eq_create *resp = embedded_payload(wrb);
03d28ffe 986
f2f781a7
SP		 987 eqo->q.id = le16_to_cpu(resp->eq_id);
988 eqo->msix_idx =
989 (ver == 2) ? le16_to_cpu(resp->msix_idx) : eqo->idx;
990 eqo->q.created = true;
6b7c5b94 991 }
b31c50a7 992
2984961c 993 mutex_unlock(&adapter->mbox_lock);
6b7c5b94
SP		 994 return status;
995}
996
f9449ab7 997/* Use MCC */
8788fdc2 998int be_cmd_mac_addr_query(struct be_adapter *adapter, u8 *mac_addr,
5ee4979b 999 bool permanent, u32 if_handle, u32 pmac_id)
6b7c5b94 1000{
b31c50a7
SP		 1001 struct be_mcc_wrb *wrb;
1002 struct be_cmd_req_mac_query *req;
6b7c5b94
SP		 1003 int status;
1004
f9449ab7 1005 spin_lock_bh(&adapter->mcc_lock);
b31c50a7 1006
f9449ab7
SP		 1007 wrb = wrb_from_mccq(adapter);
1008 if (!wrb) {
1009 status = -EBUSY;
1010 goto err;
1011 }
b31c50a7 1012 req = embedded_payload(wrb);
6b7c5b94 1013
106df1e3 1014 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 1015 OPCODE_COMMON_NTWK_MAC_QUERY, sizeof(*req), wrb,
1016 NULL);
5ee4979b 1017 req->type = MAC_ADDRESS_TYPE_NETWORK;
6b7c5b94
SP		 1018 if (permanent) {
1019 req->permanent = 1;
1020 } else {
504fbf1e 1021 req->if_id = cpu_to_le16((u16)if_handle);
590c391d 1022 req->pmac_id = cpu_to_le32(pmac_id);
6b7c5b94
SP		 1023 req->permanent = 0;
1024 }
1025
f9449ab7 1026 status = be_mcc_notify_wait(adapter);
b31c50a7
SP		 1027 if (!status) {
1028 struct be_cmd_resp_mac_query *resp = embedded_payload(wrb);
03d28ffe 1029
6b7c5b94 1030 memcpy(mac_addr, resp->mac.addr, ETH_ALEN);
b31c50a7 1031 }
6b7c5b94 1032
f9449ab7
SP		 1033err:
1034 spin_unlock_bh(&adapter->mcc_lock);
6b7c5b94
SP		 1035 return status;
1036}
1037
b31c50a7 1038/* Uses synchronous MCCQ */
8788fdc2 1039int be_cmd_pmac_add(struct be_adapter *adapter, u8 *mac_addr,
a2cc4e0b 1040 u32 if_id, u32 *pmac_id, u32 domain)
6b7c5b94 1041{
b31c50a7
SP		 1042 struct be_mcc_wrb *wrb;
1043 struct be_cmd_req_pmac_add *req;
6b7c5b94
SP		 1044 int status;
1045
b31c50a7
SP		 1046 spin_lock_bh(&adapter->mcc_lock);
1047
1048 wrb = wrb_from_mccq(adapter);
713d0394
SP		 1049 if (!wrb) {
1050 status = -EBUSY;
1051 goto err;
1052 }
b31c50a7 1053 req = embedded_payload(wrb);
6b7c5b94 1054
106df1e3 1055 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 1056 OPCODE_COMMON_NTWK_PMAC_ADD, sizeof(*req), wrb,
1057 NULL);
6b7c5b94 1058
f8617e08 1059 req->hdr.domain = domain;
6b7c5b94
SP		 1060 req->if_id = cpu_to_le32(if_id);
1061 memcpy(req->mac_address, mac_addr, ETH_ALEN);
1062
b31c50a7 1063 status = be_mcc_notify_wait(adapter);
6b7c5b94
SP		 1064 if (!status) {
1065 struct be_cmd_resp_pmac_add *resp = embedded_payload(wrb);
03d28ffe 1066
6b7c5b94
SP		 1067 *pmac_id = le32_to_cpu(resp->pmac_id);
1068 }
1069
713d0394 1070err:
b31c50a7 1071 spin_unlock_bh(&adapter->mcc_lock);
e3a7ae2c
SK		 1072
1073 if (status == MCC_STATUS_UNAUTHORIZED_REQUEST)
1074 status = -EPERM;
1075
6b7c5b94
SP		 1076 return status;
1077}
1078
b31c50a7 1079/* Uses synchronous MCCQ */
30128031 1080int be_cmd_pmac_del(struct be_adapter *adapter, u32 if_id, int pmac_id, u32 dom)
6b7c5b94 1081{
b31c50a7
SP		 1082 struct be_mcc_wrb *wrb;
1083 struct be_cmd_req_pmac_del *req;
6b7c5b94
SP		 1084 int status;
1085
30128031
SP		 1086 if (pmac_id == -1)
1087 return 0;
1088
b31c50a7
SP		 1089 spin_lock_bh(&adapter->mcc_lock);
1090
1091 wrb = wrb_from_mccq(adapter);
713d0394
SP		 1092 if (!wrb) {
1093 status = -EBUSY;
1094 goto err;
1095 }
b31c50a7 1096 req = embedded_payload(wrb);
6b7c5b94 1097
106df1e3 1098 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
cd3307aa
KA		 1099 OPCODE_COMMON_NTWK_PMAC_DEL, sizeof(*req),
1100 wrb, NULL);
6b7c5b94 1101
f8617e08 1102 req->hdr.domain = dom;
6b7c5b94
SP		 1103 req->if_id = cpu_to_le32(if_id);
1104 req->pmac_id = cpu_to_le32(pmac_id);
1105
b31c50a7
SP		 1106 status = be_mcc_notify_wait(adapter);
1107
713d0394 1108err:
b31c50a7 1109 spin_unlock_bh(&adapter->mcc_lock);
6b7c5b94
SP		 1110 return status;
1111}
1112
b31c50a7 1113/* Uses Mbox */
10ef9ab4 1114int be_cmd_cq_create(struct be_adapter *adapter, struct be_queue_info *cq,
a2cc4e0b 1115 struct be_queue_info *eq, bool no_delay, int coalesce_wm)
6b7c5b94 1116{
b31c50a7
SP		 1117 struct be_mcc_wrb *wrb;
1118 struct be_cmd_req_cq_create *req;
6b7c5b94 1119 struct be_dma_mem *q_mem = &cq->dma_mem;
b31c50a7 1120 void *ctxt;
6b7c5b94
SP		 1121 int status;
1122
2984961c
IV		 1123 if (mutex_lock_interruptible(&adapter->mbox_lock))
1124 return -1;
b31c50a7
SP		 1125
1126 wrb = wrb_from_mbox(adapter);
1127 req = embedded_payload(wrb);
1128 ctxt = &req->context;
6b7c5b94 1129
106df1e3 1130 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 1131 OPCODE_COMMON_CQ_CREATE, sizeof(*req), wrb,
1132 NULL);
6b7c5b94
SP		 1133
1134 req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
bbdc42f8
AK		 1135
1136 if (BEx_chip(adapter)) {
fe6d2a38 1137 AMAP_SET_BITS(struct amap_cq_context_be, coalescwm, ctxt,
a2cc4e0b 1138 coalesce_wm);
fe6d2a38 1139 AMAP_SET_BITS(struct amap_cq_context_be, nodelay,
a2cc4e0b 1140 ctxt, no_delay);
fe6d2a38 1141 AMAP_SET_BITS(struct amap_cq_context_be, count, ctxt,
a2cc4e0b 1142 __ilog2_u32(cq->len / 256));
fe6d2a38 1143 AMAP_SET_BITS(struct amap_cq_context_be, valid, ctxt, 1);
fe6d2a38
SP		 1144 AMAP_SET_BITS(struct amap_cq_context_be, eventable, ctxt, 1);
1145 AMAP_SET_BITS(struct amap_cq_context_be, eqid, ctxt, eq->id);
bbdc42f8
AK		 1146 } else {
1147 req->hdr.version = 2;
1148 req->page_size = 1; /* 1 for 4K */
09e83a9d
AK		 1149
1150 /* coalesce-wm field in this cmd is not relevant to Lancer.
1151 * Lancer uses COMMON_MODIFY_CQ to set this field
1152 */
1153 if (!lancer_chip(adapter))
1154 AMAP_SET_BITS(struct amap_cq_context_v2, coalescwm,
1155 ctxt, coalesce_wm);
bbdc42f8 1156 AMAP_SET_BITS(struct amap_cq_context_v2, nodelay, ctxt,
a2cc4e0b 1157 no_delay);
bbdc42f8 1158 AMAP_SET_BITS(struct amap_cq_context_v2, count, ctxt,
a2cc4e0b 1159 __ilog2_u32(cq->len / 256));
bbdc42f8 1160 AMAP_SET_BITS(struct amap_cq_context_v2, valid, ctxt, 1);
a2cc4e0b
SP		 1161 AMAP_SET_BITS(struct amap_cq_context_v2, eventable, ctxt, 1);
1162 AMAP_SET_BITS(struct amap_cq_context_v2, eqid, ctxt, eq->id);
fe6d2a38 1163 }
6b7c5b94 1164
6b7c5b94
SP		 1165 be_dws_cpu_to_le(ctxt, sizeof(req->context));
1166
1167 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
1168
b31c50a7 1169 status = be_mbox_notify_wait(adapter);
6b7c5b94 1170 if (!status) {
b31c50a7 1171 struct be_cmd_resp_cq_create *resp = embedded_payload(wrb);
03d28ffe 1172
6b7c5b94
SP		 1173 cq->id = le16_to_cpu(resp->cq_id);
1174 cq->created = true;
1175 }
b31c50a7 1176
2984961c 1177 mutex_unlock(&adapter->mbox_lock);
5fb379ee
SP		 1178
1179 return status;
1180}
1181
1182static u32 be_encoded_q_len(int q_len)
1183{
1184 u32 len_encoded = fls(q_len); /* log2(len) + 1 */
03d28ffe 1185
5fb379ee
SP		 1186 if (len_encoded == 16)
1187 len_encoded = 0;
1188 return len_encoded;
1189}
1190
4188e7df 1191static int be_cmd_mccq_ext_create(struct be_adapter *adapter,
a2cc4e0b
SP		 1192 struct be_queue_info *mccq,
1193 struct be_queue_info *cq)
5fb379ee 1194{
b31c50a7 1195 struct be_mcc_wrb *wrb;
34b1ef04 1196 struct be_cmd_req_mcc_ext_create *req;
5fb379ee 1197 struct be_dma_mem *q_mem = &mccq->dma_mem;
b31c50a7 1198 void *ctxt;
5fb379ee
SP		 1199 int status;
1200
2984961c
IV		 1201 if (mutex_lock_interruptible(&adapter->mbox_lock))
1202 return -1;
b31c50a7
SP		 1203
1204 wrb = wrb_from_mbox(adapter);
1205 req = embedded_payload(wrb);
1206 ctxt = &req->context;
5fb379ee 1207
106df1e3 1208 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 1209 OPCODE_COMMON_MCC_CREATE_EXT, sizeof(*req), wrb,
1210 NULL);
5fb379ee 1211
d4a2ac3e 1212 req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
666d39c7 1213 if (BEx_chip(adapter)) {
fe6d2a38
SP		 1214 AMAP_SET_BITS(struct amap_mcc_context_be, valid, ctxt, 1);
1215 AMAP_SET_BITS(struct amap_mcc_context_be, ring_size, ctxt,
a2cc4e0b 1216 be_encoded_q_len(mccq->len));
fe6d2a38 1217 AMAP_SET_BITS(struct amap_mcc_context_be, cq_id, ctxt, cq->id);
666d39c7
VV		 1218 } else {
1219 req->hdr.version = 1;
1220 req->cq_id = cpu_to_le16(cq->id);
1221
1222 AMAP_SET_BITS(struct amap_mcc_context_v1, ring_size, ctxt,
1223 be_encoded_q_len(mccq->len));
1224 AMAP_SET_BITS(struct amap_mcc_context_v1, valid, ctxt, 1);
1225 AMAP_SET_BITS(struct amap_mcc_context_v1, async_cq_id,
1226 ctxt, cq->id);
1227 AMAP_SET_BITS(struct amap_mcc_context_v1, async_cq_valid,
1228 ctxt, 1);
fe6d2a38 1229 }
5fb379ee 1230
21252377
VV		 1231 /* Subscribe to Link State, Sliport Event and Group 5 Events
1232 * (bits 1, 5 and 17 set)
1233 */
1234 req->async_event_bitmap[0] =
1235 cpu_to_le32(BIT(ASYNC_EVENT_CODE_LINK_STATE) |
1236 BIT(ASYNC_EVENT_CODE_GRP_5) |
1237 BIT(ASYNC_EVENT_CODE_QNQ) |
1238 BIT(ASYNC_EVENT_CODE_SLIPORT));
1239
5fb379ee
SP		 1240 be_dws_cpu_to_le(ctxt, sizeof(req->context));
1241
1242 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
1243
b31c50a7 1244 status = be_mbox_notify_wait(adapter);
5fb379ee
SP		 1245 if (!status) {
1246 struct be_cmd_resp_mcc_create *resp = embedded_payload(wrb);
03d28ffe 1247
5fb379ee
SP		 1248 mccq->id = le16_to_cpu(resp->id);
1249 mccq->created = true;
1250 }
2984961c 1251 mutex_unlock(&adapter->mbox_lock);
6b7c5b94
SP		 1252
1253 return status;
1254}
1255
4188e7df 1256static int be_cmd_mccq_org_create(struct be_adapter *adapter,
a2cc4e0b
SP		 1257 struct be_queue_info *mccq,
1258 struct be_queue_info *cq)
34b1ef04
SK		 1259{
1260 struct be_mcc_wrb *wrb;
1261 struct be_cmd_req_mcc_create *req;
1262 struct be_dma_mem *q_mem = &mccq->dma_mem;
1263 void *ctxt;
1264 int status;
1265
1266 if (mutex_lock_interruptible(&adapter->mbox_lock))
1267 return -1;
1268
1269 wrb = wrb_from_mbox(adapter);
1270 req = embedded_payload(wrb);
1271 ctxt = &req->context;
1272
106df1e3 1273 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 1274 OPCODE_COMMON_MCC_CREATE, sizeof(*req), wrb,
1275 NULL);
34b1ef04
SK		 1276
1277 req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
1278
1279 AMAP_SET_BITS(struct amap_mcc_context_be, valid, ctxt, 1);
1280 AMAP_SET_BITS(struct amap_mcc_context_be, ring_size, ctxt,
a2cc4e0b 1281 be_encoded_q_len(mccq->len));
34b1ef04
SK		 1282 AMAP_SET_BITS(struct amap_mcc_context_be, cq_id, ctxt, cq->id);
1283
1284 be_dws_cpu_to_le(ctxt, sizeof(req->context));
1285
1286 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
1287
1288 status = be_mbox_notify_wait(adapter);
1289 if (!status) {
1290 struct be_cmd_resp_mcc_create *resp = embedded_payload(wrb);
03d28ffe 1291
34b1ef04
SK		 1292 mccq->id = le16_to_cpu(resp->id);
1293 mccq->created = true;
1294 }
1295
1296 mutex_unlock(&adapter->mbox_lock);
1297 return status;
1298}
1299
1300int be_cmd_mccq_create(struct be_adapter *adapter,
a2cc4e0b 1301 struct be_queue_info *mccq, struct be_queue_info *cq)
34b1ef04
SK		 1302{
1303 int status;
1304
1305 status = be_cmd_mccq_ext_create(adapter, mccq, cq);
666d39c7 1306 if (status && BEx_chip(adapter)) {
34b1ef04
SK		 1307 dev_warn(&adapter->pdev->dev, "Upgrade to F/W ver 2.102.235.0 "
1308 "or newer to avoid conflicting priorities between NIC "
1309 "and FCoE traffic");
1310 status = be_cmd_mccq_org_create(adapter, mccq, cq);
1311 }
1312 return status;
1313}
1314
94d73aaa 1315int be_cmd_txq_create(struct be_adapter *adapter, struct be_tx_obj *txo)
6b7c5b94 1316{
7707133c 1317 struct be_mcc_wrb wrb = {0};
b31c50a7 1318 struct be_cmd_req_eth_tx_create *req;
94d73aaa
VV		 1319 struct be_queue_info *txq = &txo->q;
1320 struct be_queue_info *cq = &txo->cq;
6b7c5b94 1321 struct be_dma_mem *q_mem = &txq->dma_mem;
94d73aaa 1322 int status, ver = 0;
6b7c5b94 1323
7707133c 1324 req = embedded_payload(&wrb);
106df1e3 1325 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
a2cc4e0b 1326 OPCODE_ETH_TX_CREATE, sizeof(*req), &wrb, NULL);
6b7c5b94 1327
8b7756ca
PR		 1328 if (lancer_chip(adapter)) {
1329 req->hdr.version = 1;
94d73aaa
VV		 1330 } else if (BEx_chip(adapter)) {
1331 if (adapter->function_caps & BE_FUNCTION_CAPS_SUPER_NIC)
1332 req->hdr.version = 2;
1333 } else { /* For SH */
1334 req->hdr.version = 2;
8b7756ca
PR		 1335 }
1336
81b02655
VV		 1337 if (req->hdr.version > 0)
1338 req->if_id = cpu_to_le16(adapter->if_handle);
6b7c5b94
SP		 1339 req->num_pages = PAGES_4K_SPANNED(q_mem->va, q_mem->size);
1340 req->ulp_num = BE_ULP1_NUM;
1341 req->type = BE_ETH_TX_RING_TYPE_STANDARD;
94d73aaa
VV		 1342 req->cq_id = cpu_to_le16(cq->id);
1343 req->queue_size = be_encoded_q_len(txq->len);
6b7c5b94 1344 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
94d73aaa
VV		 1345 ver = req->hdr.version;
1346
7707133c 1347 status = be_cmd_notify_wait(adapter, &wrb);
6b7c5b94 1348 if (!status) {
7707133c 1349 struct be_cmd_resp_eth_tx_create *resp = embedded_payload(&wrb);
03d28ffe 1350
6b7c5b94 1351 txq->id = le16_to_cpu(resp->cid);
94d73aaa
VV		 1352 if (ver == 2)
1353 txo->db_offset = le32_to_cpu(resp->db_offset);
1354 else
1355 txo->db_offset = DB_TXULP1_OFFSET;
6b7c5b94
SP		 1356 txq->created = true;
1357 }
b31c50a7 1358
6b7c5b94
SP		 1359 return status;
1360}
1361
482c9e79 1362/* Uses MCC */
8788fdc2 1363int be_cmd_rxq_create(struct be_adapter *adapter,
a2cc4e0b
SP		 1364 struct be_queue_info *rxq, u16 cq_id, u16 frag_size,
1365 u32 if_id, u32 rss, u8 *rss_id)
6b7c5b94 1366{
b31c50a7
SP		 1367 struct be_mcc_wrb *wrb;
1368 struct be_cmd_req_eth_rx_create *req;
6b7c5b94
SP		 1369 struct be_dma_mem *q_mem = &rxq->dma_mem;
1370 int status;
1371
482c9e79 1372 spin_lock_bh(&adapter->mcc_lock);
b31c50a7 1373
482c9e79
SP		 1374 wrb = wrb_from_mccq(adapter);
1375 if (!wrb) {
1376 status = -EBUSY;
1377 goto err;
1378 }
b31c50a7 1379 req = embedded_payload(wrb);
6b7c5b94 1380
106df1e3 1381 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
a2cc4e0b 1382 OPCODE_ETH_RX_CREATE, sizeof(*req), wrb, NULL);
6b7c5b94
SP		 1383
1384 req->cq_id = cpu_to_le16(cq_id);
1385 req->frag_size = fls(frag_size) - 1;
1386 req->num_pages = 2;
1387 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
1388 req->interface_id = cpu_to_le32(if_id);
10ef9ab4 1389 req->max_frame_size = cpu_to_le16(BE_MAX_JUMBO_FRAME_SIZE);
6b7c5b94
SP		 1390 req->rss_queue = cpu_to_le32(rss);
1391
482c9e79 1392 status = be_mcc_notify_wait(adapter);
6b7c5b94
SP		 1393 if (!status) {
1394 struct be_cmd_resp_eth_rx_create *resp = embedded_payload(wrb);
03d28ffe 1395
6b7c5b94
SP		 1396 rxq->id = le16_to_cpu(resp->id);
1397 rxq->created = true;
3abcdeda 1398 *rss_id = resp->rss_id;
6b7c5b94 1399 }
b31c50a7 1400
482c9e79
SP		 1401err:
1402 spin_unlock_bh(&adapter->mcc_lock);
6b7c5b94
SP		 1403 return status;
1404}
1405
b31c50a7
SP		 1406/* Generic destroyer function for all types of queues
1407 * Uses Mbox
1408 */
8788fdc2 1409int be_cmd_q_destroy(struct be_adapter *adapter, struct be_queue_info *q,
a2cc4e0b 1410 int queue_type)
6b7c5b94 1411{
b31c50a7
SP		 1412 struct be_mcc_wrb *wrb;
1413 struct be_cmd_req_q_destroy *req;
6b7c5b94
SP		 1414 u8 subsys = 0, opcode = 0;
1415 int status;
1416
2984961c
IV		 1417 if (mutex_lock_interruptible(&adapter->mbox_lock))
1418 return -1;
6b7c5b94 1419
b31c50a7
SP		 1420 wrb = wrb_from_mbox(adapter);
1421 req = embedded_payload(wrb);
1422
6b7c5b94
SP		 1423 switch (queue_type) {
1424 case QTYPE_EQ:
1425 subsys = CMD_SUBSYSTEM_COMMON;
1426 opcode = OPCODE_COMMON_EQ_DESTROY;
1427 break;
1428 case QTYPE_CQ:
1429 subsys = CMD_SUBSYSTEM_COMMON;
1430 opcode = OPCODE_COMMON_CQ_DESTROY;
1431 break;
1432 case QTYPE_TXQ:
1433 subsys = CMD_SUBSYSTEM_ETH;
1434 opcode = OPCODE_ETH_TX_DESTROY;
1435 break;
1436 case QTYPE_RXQ:
1437 subsys = CMD_SUBSYSTEM_ETH;
1438 opcode = OPCODE_ETH_RX_DESTROY;
1439 break;
5fb379ee
SP		 1440 case QTYPE_MCCQ:
1441 subsys = CMD_SUBSYSTEM_COMMON;
1442 opcode = OPCODE_COMMON_MCC_DESTROY;
1443 break;
6b7c5b94 1444 default:
5f0b849e 1445 BUG();
6b7c5b94 1446 }
d744b44e 1447
106df1e3 1448 be_wrb_cmd_hdr_prepare(&req->hdr, subsys, opcode, sizeof(*req), wrb,
a2cc4e0b 1449 NULL);
6b7c5b94
SP		 1450 req->id = cpu_to_le16(q->id);
1451
b31c50a7 1452 status = be_mbox_notify_wait(adapter);
aa790db9 1453 q->created = false;
5f0b849e 1454
2984961c 1455 mutex_unlock(&adapter->mbox_lock);
482c9e79
SP		 1456 return status;
1457}
6b7c5b94 1458
482c9e79
SP		 1459/* Uses MCC */
1460int be_cmd_rxq_destroy(struct be_adapter *adapter, struct be_queue_info *q)
1461{
1462 struct be_mcc_wrb *wrb;
1463 struct be_cmd_req_q_destroy *req;
1464 int status;
1465
1466 spin_lock_bh(&adapter->mcc_lock);
1467
1468 wrb = wrb_from_mccq(adapter);
1469 if (!wrb) {
1470 status = -EBUSY;
1471 goto err;
1472 }
1473 req = embedded_payload(wrb);
1474
106df1e3 1475 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
a2cc4e0b 1476 OPCODE_ETH_RX_DESTROY, sizeof(*req), wrb, NULL);
482c9e79
SP		 1477 req->id = cpu_to_le16(q->id);
1478
1479 status = be_mcc_notify_wait(adapter);
aa790db9 1480 q->created = false;
482c9e79
SP		 1481
1482err:
1483 spin_unlock_bh(&adapter->mcc_lock);
6b7c5b94
SP		 1484 return status;
1485}
1486
b31c50a7 1487/* Create an rx filtering policy configuration on an i/f
bea50988 1488 * Will use MBOX only if MCCQ has not been created.
b31c50a7 1489 */
73d540f2 1490int be_cmd_if_create(struct be_adapter *adapter, u32 cap_flags, u32 en_flags,
1578e777 1491 u32 *if_handle, u32 domain)
6b7c5b94 1492{
bea50988 1493 struct be_mcc_wrb wrb = {0};
b31c50a7 1494 struct be_cmd_req_if_create *req;
6b7c5b94
SP		 1495 int status;
1496
bea50988 1497 req = embedded_payload(&wrb);
106df1e3 1498 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 1499 OPCODE_COMMON_NTWK_INTERFACE_CREATE,
1500 sizeof(*req), &wrb, NULL);
ba343c77 1501 req->hdr.domain = domain;
73d540f2
SP		 1502 req->capability_flags = cpu_to_le32(cap_flags);
1503 req->enable_flags = cpu_to_le32(en_flags);
1578e777 1504 req->pmac_invalid = true;
6b7c5b94 1505
bea50988 1506 status = be_cmd_notify_wait(adapter, &wrb);
6b7c5b94 1507 if (!status) {
bea50988 1508 struct be_cmd_resp_if_create *resp = embedded_payload(&wrb);
03d28ffe 1509
6b7c5b94 1510 *if_handle = le32_to_cpu(resp->interface_id);
b5bb9776
SP		 1511
1512 /* Hack to retrieve VF's pmac-id on BE3 */
1513 if (BE3_chip(adapter) && !be_physfn(adapter))
1514 adapter->pmac_id[0] = le32_to_cpu(resp->pmac_id);
6b7c5b94 1515 }
6b7c5b94
SP		 1516 return status;
1517}
1518
f9449ab7 1519/* Uses MCCQ */
30128031 1520int be_cmd_if_destroy(struct be_adapter *adapter, int interface_id, u32 domain)
6b7c5b94 1521{
b31c50a7
SP		 1522 struct be_mcc_wrb *wrb;
1523 struct be_cmd_req_if_destroy *req;
6b7c5b94
SP		 1524 int status;
1525
30128031 1526 if (interface_id == -1)
f9449ab7 1527 return 0;
b31c50a7 1528
f9449ab7
SP		 1529 spin_lock_bh(&adapter->mcc_lock);
1530
1531 wrb = wrb_from_mccq(adapter);
1532 if (!wrb) {
1533 status = -EBUSY;
1534 goto err;
1535 }
b31c50a7 1536 req = embedded_payload(wrb);
6b7c5b94 1537
106df1e3 1538 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 1539 OPCODE_COMMON_NTWK_INTERFACE_DESTROY,
1540 sizeof(*req), wrb, NULL);
658681f7 1541 req->hdr.domain = domain;
6b7c5b94 1542 req->interface_id = cpu_to_le32(interface_id);
b31c50a7 1543
f9449ab7
SP		 1544 status = be_mcc_notify_wait(adapter);
1545err:
1546 spin_unlock_bh(&adapter->mcc_lock);
6b7c5b94
SP		 1547 return status;
1548}
1549
1550/* Get stats is a non embedded command: the request is not embedded inside
1551 * WRB but is a separate dma memory block
b31c50a7 1552 * Uses asynchronous MCC
6b7c5b94 1553 */
8788fdc2 1554int be_cmd_get_stats(struct be_adapter *adapter, struct be_dma_mem *nonemb_cmd)
6b7c5b94 1555{
b31c50a7 1556 struct be_mcc_wrb *wrb;
89a88ab8 1557 struct be_cmd_req_hdr *hdr;
713d0394 1558 int status = 0;
6b7c5b94 1559
b31c50a7 1560 spin_lock_bh(&adapter->mcc_lock);
6b7c5b94 1561
b31c50a7 1562 wrb = wrb_from_mccq(adapter);
713d0394
SP		 1563 if (!wrb) {
1564 status = -EBUSY;
1565 goto err;
1566 }
89a88ab8 1567 hdr = nonemb_cmd->va;
6b7c5b94 1568
106df1e3 1569 be_wrb_cmd_hdr_prepare(hdr, CMD_SUBSYSTEM_ETH,
a2cc4e0b
SP		 1570 OPCODE_ETH_GET_STATISTICS, nonemb_cmd->size, wrb,
1571 nonemb_cmd);
89a88ab8 1572
ca34fe38 1573 /* version 1 of the cmd is not supported only by BE2 */
61000861
AK		 1574 if (BE2_chip(adapter))
1575 hdr->version = 0;
1576 if (BE3_chip(adapter) || lancer_chip(adapter))
89a88ab8 1577 hdr->version = 1;
61000861
AK		 1578 else
1579 hdr->version = 2;
89a88ab8 1580
b31c50a7 1581 be_mcc_notify(adapter);
b2aebe6d 1582 adapter->stats_cmd_sent = true;
6b7c5b94 1583
713d0394 1584err:
b31c50a7 1585 spin_unlock_bh(&adapter->mcc_lock);
713d0394 1586 return status;
6b7c5b94
SP		 1587}
1588
005d5696
SX		 1589/* Lancer Stats */
1590int lancer_cmd_get_pport_stats(struct be_adapter *adapter,
a2cc4e0b 1591 struct be_dma_mem *nonemb_cmd)
005d5696 1592{
005d5696
SX		 1593 struct be_mcc_wrb *wrb;
1594 struct lancer_cmd_req_pport_stats *req;
005d5696
SX		 1595 int status = 0;
1596
f25b119c
PR		 1597 if (!be_cmd_allowed(adapter, OPCODE_ETH_GET_PPORT_STATS,
1598 CMD_SUBSYSTEM_ETH))
1599 return -EPERM;
1600
005d5696
SX		 1601 spin_lock_bh(&adapter->mcc_lock);
1602
1603 wrb = wrb_from_mccq(adapter);
1604 if (!wrb) {
1605 status = -EBUSY;
1606 goto err;
1607 }
1608 req = nonemb_cmd->va;
005d5696 1609
106df1e3 1610 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
a2cc4e0b
SP		 1611 OPCODE_ETH_GET_PPORT_STATS, nonemb_cmd->size,
1612 wrb, nonemb_cmd);
005d5696 1613
d51ebd33 1614 req->cmd_params.params.pport_num = cpu_to_le16(adapter->hba_port_num);
005d5696
SX		 1615 req->cmd_params.params.reset_stats = 0;
1616
005d5696
SX		 1617 be_mcc_notify(adapter);
1618 adapter->stats_cmd_sent = true;
1619
1620err:
1621 spin_unlock_bh(&adapter->mcc_lock);
1622 return status;
1623}
1624
323ff71e
SP		 1625static int be_mac_to_link_speed(int mac_speed)
1626{
1627 switch (mac_speed) {
1628 case PHY_LINK_SPEED_ZERO:
1629 return 0;
1630 case PHY_LINK_SPEED_10MBPS:
1631 return 10;
1632 case PHY_LINK_SPEED_100MBPS:
1633 return 100;
1634 case PHY_LINK_SPEED_1GBPS:
1635 return 1000;
1636 case PHY_LINK_SPEED_10GBPS:
1637 return 10000;
b971f847
VV		 1638 case PHY_LINK_SPEED_20GBPS:
1639 return 20000;
1640 case PHY_LINK_SPEED_25GBPS:
1641 return 25000;
1642 case PHY_LINK_SPEED_40GBPS:
1643 return 40000;
323ff71e
SP		 1644 }
1645 return 0;
1646}
1647
1648/* Uses synchronous mcc
1649 * Returns link_speed in Mbps
1650 */
1651int be_cmd_link_status_query(struct be_adapter *adapter, u16 *link_speed,
1652 u8 *link_status, u32 dom)
6b7c5b94 1653{
b31c50a7
SP		 1654 struct be_mcc_wrb *wrb;
1655 struct be_cmd_req_link_status *req;
6b7c5b94
SP		 1656 int status;
1657
b31c50a7
SP		 1658 spin_lock_bh(&adapter->mcc_lock);
1659
b236916a
AK		 1660 if (link_status)
1661 *link_status = LINK_DOWN;
1662
b31c50a7 1663 wrb = wrb_from_mccq(adapter);
713d0394
SP		 1664 if (!wrb) {
1665 status = -EBUSY;
1666 goto err;
1667 }
b31c50a7 1668 req = embedded_payload(wrb);
a8f447bd 1669
57cd80d4 1670 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 1671 OPCODE_COMMON_NTWK_LINK_STATUS_QUERY,
1672 sizeof(*req), wrb, NULL);
57cd80d4 1673
ca34fe38
SP		 1674 /* version 1 of the cmd is not supported only by BE2 */
1675 if (!BE2_chip(adapter))
daad6167
PR		 1676 req->hdr.version = 1;
1677
57cd80d4 1678 req->hdr.domain = dom;
6b7c5b94 1679
b31c50a7 1680 status = be_mcc_notify_wait(adapter);
6b7c5b94
SP		 1681 if (!status) {
1682 struct be_cmd_resp_link_status *resp = embedded_payload(wrb);
03d28ffe 1683
323ff71e
SP		 1684 if (link_speed) {
1685 *link_speed = resp->link_speed ?
1686 le16_to_cpu(resp->link_speed) * 10 :
1687 be_mac_to_link_speed(resp->mac_speed);
1688
1689 if (!resp->logical_link_status)
1690 *link_speed = 0;
0388f251 1691 }
b236916a
AK		 1692 if (link_status)
1693 *link_status = resp->logical_link_status;
6b7c5b94
SP		 1694 }
1695
713d0394 1696err:
b31c50a7 1697 spin_unlock_bh(&adapter->mcc_lock);
6b7c5b94
SP		 1698 return status;
1699}
1700
609ff3bb
AK		 1701/* Uses synchronous mcc */
1702int be_cmd_get_die_temperature(struct be_adapter *adapter)
1703{
1704 struct be_mcc_wrb *wrb;
1705 struct be_cmd_req_get_cntl_addnl_attribs *req;
117affe3 1706 int status = 0;
609ff3bb
AK		 1707
1708 spin_lock_bh(&adapter->mcc_lock);
1709
1710 wrb = wrb_from_mccq(adapter);
1711 if (!wrb) {
1712 status = -EBUSY;
1713 goto err;
1714 }
1715 req = embedded_payload(wrb);
1716
106df1e3 1717 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 1718 OPCODE_COMMON_GET_CNTL_ADDITIONAL_ATTRIBUTES,
1719 sizeof(*req), wrb, NULL);
609ff3bb 1720
3de09455 1721 be_mcc_notify(adapter);
609ff3bb
AK		 1722
1723err:
1724 spin_unlock_bh(&adapter->mcc_lock);
1725 return status;
1726}
1727
311fddc7
SK		 1728/* Uses synchronous mcc */
1729int be_cmd_get_reg_len(struct be_adapter *adapter, u32 *log_size)
1730{
1731 struct be_mcc_wrb *wrb;
1732 struct be_cmd_req_get_fat *req;
1733 int status;
1734
1735 spin_lock_bh(&adapter->mcc_lock);
1736
1737 wrb = wrb_from_mccq(adapter);
1738 if (!wrb) {
1739 status = -EBUSY;
1740 goto err;
1741 }
1742 req = embedded_payload(wrb);
1743
106df1e3 1744 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 1745 OPCODE_COMMON_MANAGE_FAT, sizeof(*req), wrb,
1746 NULL);
311fddc7
SK		 1747 req->fat_operation = cpu_to_le32(QUERY_FAT);
1748 status = be_mcc_notify_wait(adapter);
1749 if (!status) {
1750 struct be_cmd_resp_get_fat *resp = embedded_payload(wrb);
03d28ffe 1751
311fddc7 1752 if (log_size && resp->log_size)
fe2a70ee
SK		 1753 *log_size = le32_to_cpu(resp->log_size) -
1754 sizeof(u32);
311fddc7
SK		 1755 }
1756err:
1757 spin_unlock_bh(&adapter->mcc_lock);
1758 return status;
1759}
1760
c5f156de 1761int be_cmd_get_regs(struct be_adapter *adapter, u32 buf_len, void *buf)
311fddc7
SK		 1762{
1763 struct be_dma_mem get_fat_cmd;
1764 struct be_mcc_wrb *wrb;
1765 struct be_cmd_req_get_fat *req;
fe2a70ee
SK		 1766 u32 offset = 0, total_size, buf_size,
1767 log_offset = sizeof(u32), payload_len;
c5f156de 1768 int status = 0;
311fddc7
SK		 1769
1770 if (buf_len == 0)
c5f156de 1771 return -EIO;
311fddc7
SK		 1772
1773 total_size = buf_len;
1774
fe2a70ee
SK		 1775 get_fat_cmd.size = sizeof(struct be_cmd_req_get_fat) + 60*1024;
1776 get_fat_cmd.va = pci_alloc_consistent(adapter->pdev,
a2cc4e0b
SP		 1777 get_fat_cmd.size,
1778 &get_fat_cmd.dma);
fe2a70ee 1779 if (!get_fat_cmd.va) {
fe2a70ee 1780 dev_err(&adapter->pdev->dev,
cd3307aa 1781 "Memory allocation failure while reading FAT data\n");
c5f156de 1782 return -ENOMEM;
fe2a70ee
SK		 1783 }
1784
311fddc7
SK		 1785 spin_lock_bh(&adapter->mcc_lock);
1786
311fddc7
SK		 1787 while (total_size) {
1788 buf_size = min(total_size, (u32)60*1024);
1789 total_size -= buf_size;
1790
fe2a70ee
SK		 1791 wrb = wrb_from_mccq(adapter);
1792 if (!wrb) {
1793 status = -EBUSY;
311fddc7
SK		 1794 goto err;
1795 }
1796 req = get_fat_cmd.va;
311fddc7 1797
fe2a70ee 1798 payload_len = sizeof(struct be_cmd_req_get_fat) + buf_size;
106df1e3 1799 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 1800 OPCODE_COMMON_MANAGE_FAT, payload_len,
1801 wrb, &get_fat_cmd);
311fddc7
SK		 1802
1803 req->fat_operation = cpu_to_le32(RETRIEVE_FAT);
1804 req->read_log_offset = cpu_to_le32(log_offset);
1805 req->read_log_length = cpu_to_le32(buf_size);
1806 req->data_buffer_size = cpu_to_le32(buf_size);
1807
1808 status = be_mcc_notify_wait(adapter);
1809 if (!status) {
1810 struct be_cmd_resp_get_fat *resp = get_fat_cmd.va;
03d28ffe 1811
311fddc7 1812 memcpy(buf + offset,
a2cc4e0b
SP		 1813 resp->data_buffer,
1814 le32_to_cpu(resp->read_log_length));
fe2a70ee 1815 } else {
311fddc7 1816 dev_err(&adapter->pdev->dev, "FAT Table Retrieve error\n");
fe2a70ee
SK		 1817 goto err;
1818 }
311fddc7
SK		 1819 offset += buf_size;
1820 log_offset += buf_size;
1821 }
1822err:
fe2a70ee 1823 pci_free_consistent(adapter->pdev, get_fat_cmd.size,
a2cc4e0b 1824 get_fat_cmd.va, get_fat_cmd.dma);
311fddc7 1825 spin_unlock_bh(&adapter->mcc_lock);
c5f156de 1826 return status;
311fddc7
SK		 1827}
1828
04b71175 1829/* Uses synchronous mcc */
e97e3cda 1830int be_cmd_get_fw_ver(struct be_adapter *adapter)
6b7c5b94 1831{
b31c50a7
SP		 1832 struct be_mcc_wrb *wrb;
1833 struct be_cmd_req_get_fw_version *req;
6b7c5b94
SP		 1834 int status;
1835
04b71175 1836 spin_lock_bh(&adapter->mcc_lock);
b31c50a7 1837
04b71175
SP		 1838 wrb = wrb_from_mccq(adapter);
1839 if (!wrb) {
1840 status = -EBUSY;
1841 goto err;
1842 }
6b7c5b94 1843
04b71175 1844 req = embedded_payload(wrb);
6b7c5b94 1845
106df1e3 1846 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 1847 OPCODE_COMMON_GET_FW_VERSION, sizeof(*req), wrb,
1848 NULL);
04b71175 1849 status = be_mcc_notify_wait(adapter);
6b7c5b94
SP		 1850 if (!status) {
1851 struct be_cmd_resp_get_fw_version *resp = embedded_payload(wrb);
acbafeb1 1852
242eb470
VV		 1853 strlcpy(adapter->fw_ver, resp->firmware_version_string,
1854 sizeof(adapter->fw_ver));
1855 strlcpy(adapter->fw_on_flash, resp->fw_on_flash_version_string,
1856 sizeof(adapter->fw_on_flash));
6b7c5b94 1857 }
04b71175
SP		 1858err:
1859 spin_unlock_bh(&adapter->mcc_lock);
6b7c5b94
SP		 1860 return status;
1861}
1862
b31c50a7
SP		 1863/* set the EQ delay interval of an EQ to specified value
1864 * Uses async mcc
1865 */
b502ae8d
KA		 1866static int __be_cmd_modify_eqd(struct be_adapter *adapter,
1867 struct be_set_eqd *set_eqd, int num)
6b7c5b94 1868{
b31c50a7
SP		 1869 struct be_mcc_wrb *wrb;
1870 struct be_cmd_req_modify_eq_delay *req;
2632bafd 1871 int status = 0, i;
6b7c5b94 1872
b31c50a7
SP		 1873 spin_lock_bh(&adapter->mcc_lock);
1874
1875 wrb = wrb_from_mccq(adapter);
713d0394
SP		 1876 if (!wrb) {
1877 status = -EBUSY;
1878 goto err;
1879 }
b31c50a7 1880 req = embedded_payload(wrb);
6b7c5b94 1881
106df1e3 1882 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 1883 OPCODE_COMMON_MODIFY_EQ_DELAY, sizeof(*req), wrb,
1884 NULL);
6b7c5b94 1885
2632bafd
SP		 1886 req->num_eq = cpu_to_le32(num);
1887 for (i = 0; i < num; i++) {
1888 req->set_eqd[i].eq_id = cpu_to_le32(set_eqd[i].eq_id);
1889 req->set_eqd[i].phase = 0;
1890 req->set_eqd[i].delay_multiplier =
1891 cpu_to_le32(set_eqd[i].delay_multiplier);
1892 }
6b7c5b94 1893
b31c50a7 1894 be_mcc_notify(adapter);
713d0394 1895err:
b31c50a7 1896 spin_unlock_bh(&adapter->mcc_lock);
713d0394 1897 return status;
6b7c5b94
SP		 1898}
1899
93676703
KA		 1900int be_cmd_modify_eqd(struct be_adapter *adapter, struct be_set_eqd *set_eqd,
1901 int num)
1902{
1903 int num_eqs, i = 0;
1904
c8ba4ad0
SR		 1905 while (num) {
1906 num_eqs = min(num, 8);
1907 __be_cmd_modify_eqd(adapter, &set_eqd[i], num_eqs);
1908 i += num_eqs;
1909 num -= num_eqs;
93676703
KA		 1910 }
1911
1912 return 0;
1913}
1914
b31c50a7 1915/* Uses sycnhronous mcc */
8788fdc2 1916int be_cmd_vlan_config(struct be_adapter *adapter, u32 if_id, u16 *vtag_array,
435452aa 1917 u32 num, u32 domain)
6b7c5b94 1918{
b31c50a7
SP		 1919 struct be_mcc_wrb *wrb;
1920 struct be_cmd_req_vlan_config *req;
6b7c5b94
SP		 1921 int status;
1922
b31c50a7
SP		 1923 spin_lock_bh(&adapter->mcc_lock);
1924
1925 wrb = wrb_from_mccq(adapter);
713d0394
SP		 1926 if (!wrb) {
1927 status = -EBUSY;
1928 goto err;
1929 }
b31c50a7 1930 req = embedded_payload(wrb);
6b7c5b94 1931
106df1e3 1932 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 1933 OPCODE_COMMON_NTWK_VLAN_CONFIG, sizeof(*req),
1934 wrb, NULL);
435452aa 1935 req->hdr.domain = domain;
6b7c5b94
SP		 1936
1937 req->interface_id = if_id;
012bd387 1938 req->untagged = BE_IF_FLAGS_UNTAGGED & be_if_cap_flags(adapter) ? 1 : 0;
6b7c5b94 1939 req->num_vlan = num;
4d567d97
KA		 1940 memcpy(req->normal_vlan, vtag_array,
1941 req->num_vlan * sizeof(vtag_array[0]));
6b7c5b94 1942
b31c50a7 1943 status = be_mcc_notify_wait(adapter);
713d0394 1944err:
b31c50a7 1945 spin_unlock_bh(&adapter->mcc_lock);
6b7c5b94
SP		 1946 return status;
1947}
1948
ac34b743 1949static int __be_cmd_rx_filter(struct be_adapter *adapter, u32 flags, u32 value)
6b7c5b94 1950{
6ac7b687 1951 struct be_mcc_wrb *wrb;
5b8821b7
SP		 1952 struct be_dma_mem *mem = &adapter->rx_filter;
1953 struct be_cmd_req_rx_filter *req = mem->va;
e7b909a6 1954 int status;
6b7c5b94 1955
8788fdc2 1956 spin_lock_bh(&adapter->mcc_lock);
6ac7b687 1957
b31c50a7 1958 wrb = wrb_from_mccq(adapter);
713d0394
SP		 1959 if (!wrb) {
1960 status = -EBUSY;
1961 goto err;
1962 }
5b8821b7 1963 memset(req, 0, sizeof(*req));
106df1e3 1964 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 1965 OPCODE_COMMON_NTWK_RX_FILTER, sizeof(*req),
1966 wrb, mem);
6b7c5b94 1967
5b8821b7 1968 req->if_id = cpu_to_le32(adapter->if_handle);
ac34b743
SP		 1969 req->if_flags_mask = cpu_to_le32(flags);
1970 req->if_flags = (value == ON) ? req->if_flags_mask : 0;
1971
1972 if (flags & BE_IF_FLAGS_MULTICAST) {
22bedad3 1973 struct netdev_hw_addr *ha;
5b8821b7 1974 int i = 0;
24307eef 1975
1610c79f
PR		 1976 /* Reset mcast promisc mode if already set by setting mask
1977 * and not setting flags field
1978 */
abb93951
PR		 1979 req->if_flags_mask |=
1980 cpu_to_le32(BE_IF_FLAGS_MCAST_PROMISCUOUS &
92bf14ab 1981 be_if_cap_flags(adapter));
016f97b1 1982 req->mcast_num = cpu_to_le32(netdev_mc_count(adapter->netdev));
5b8821b7
SP		 1983 netdev_for_each_mc_addr(ha, adapter->netdev)
1984 memcpy(req->mcast_mac[i++].byte, ha->addr, ETH_ALEN);
6b7c5b94
SP		 1985 }
1986
0d1d5875 1987 status = be_mcc_notify_wait(adapter);
713d0394 1988err:
8788fdc2 1989 spin_unlock_bh(&adapter->mcc_lock);
e7b909a6 1990 return status;
6b7c5b94
SP		 1991}
1992
ac34b743
SP		 1993int be_cmd_rx_filter(struct be_adapter *adapter, u32 flags, u32 value)
1994{
1995 struct device *dev = &adapter->pdev->dev;
1996
1997 if ((flags & be_if_cap_flags(adapter)) != flags) {
1998 dev_warn(dev, "Cannot set rx filter flags 0x%x\n", flags);
1999 dev_warn(dev, "Interface is capable of 0x%x flags only\n",
2000 be_if_cap_flags(adapter));
2001 }
2002 flags &= be_if_cap_flags(adapter);
2003
2004 return __be_cmd_rx_filter(adapter, flags, value);
2005}
2006
b31c50a7 2007/* Uses synchrounous mcc */
8788fdc2 2008int be_cmd_set_flow_control(struct be_adapter *adapter, u32 tx_fc, u32 rx_fc)
6b7c5b94 2009{
b31c50a7
SP		 2010 struct be_mcc_wrb *wrb;
2011 struct be_cmd_req_set_flow_control *req;
6b7c5b94
SP		 2012 int status;
2013
f25b119c
PR		 2014 if (!be_cmd_allowed(adapter, OPCODE_COMMON_SET_FLOW_CONTROL,
2015 CMD_SUBSYSTEM_COMMON))
2016 return -EPERM;
2017
b31c50a7 2018 spin_lock_bh(&adapter->mcc_lock);
6b7c5b94 2019
b31c50a7 2020 wrb = wrb_from_mccq(adapter);
713d0394
SP		 2021 if (!wrb) {
2022 status = -EBUSY;
2023 goto err;
2024 }
b31c50a7 2025 req = embedded_payload(wrb);
6b7c5b94 2026
106df1e3 2027 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 2028 OPCODE_COMMON_SET_FLOW_CONTROL, sizeof(*req),
2029 wrb, NULL);
6b7c5b94 2030
b29812c1 2031 req->hdr.version = 1;
6b7c5b94
SP		 2032 req->tx_flow_control = cpu_to_le16((u16)tx_fc);
2033 req->rx_flow_control = cpu_to_le16((u16)rx_fc);
2034
b31c50a7 2035 status = be_mcc_notify_wait(adapter);
6b7c5b94 2036
713d0394 2037err:
b31c50a7 2038 spin_unlock_bh(&adapter->mcc_lock);
b29812c1
SR		 2039
2040 if (base_status(status) == MCC_STATUS_FEATURE_NOT_SUPPORTED)
2041 return -EOPNOTSUPP;
2042
6b7c5b94
SP		 2043 return status;
2044}
2045
b31c50a7 2046/* Uses sycn mcc */
8788fdc2 2047int be_cmd_get_flow_control(struct be_adapter *adapter, u32 *tx_fc, u32 *rx_fc)
6b7c5b94 2048{
b31c50a7
SP		 2049 struct be_mcc_wrb *wrb;
2050 struct be_cmd_req_get_flow_control *req;
6b7c5b94
SP		 2051 int status;
2052
f25b119c
PR		 2053 if (!be_cmd_allowed(adapter, OPCODE_COMMON_GET_FLOW_CONTROL,
2054 CMD_SUBSYSTEM_COMMON))
2055 return -EPERM;
2056
b31c50a7 2057 spin_lock_bh(&adapter->mcc_lock);
6b7c5b94 2058
b31c50a7 2059 wrb = wrb_from_mccq(adapter);
713d0394
SP		 2060 if (!wrb) {
2061 status = -EBUSY;
2062 goto err;
2063 }
b31c50a7 2064 req = embedded_payload(wrb);
6b7c5b94 2065
106df1e3 2066 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 2067 OPCODE_COMMON_GET_FLOW_CONTROL, sizeof(*req),
2068 wrb, NULL);
6b7c5b94 2069
b31c50a7 2070 status = be_mcc_notify_wait(adapter);
6b7c5b94
SP		 2071 if (!status) {
2072 struct be_cmd_resp_get_flow_control *resp =
2073 embedded_payload(wrb);
03d28ffe 2074
6b7c5b94
SP		 2075 *tx_fc = le16_to_cpu(resp->tx_flow_control);
2076 *rx_fc = le16_to_cpu(resp->rx_flow_control);
2077 }
2078
713d0394 2079err:
b31c50a7 2080 spin_unlock_bh(&adapter->mcc_lock);
6b7c5b94
SP		 2081 return status;
2082}
2083
b31c50a7 2084/* Uses mbox */
e97e3cda 2085int be_cmd_query_fw_cfg(struct be_adapter *adapter)
6b7c5b94 2086{
b31c50a7
SP		 2087 struct be_mcc_wrb *wrb;
2088 struct be_cmd_req_query_fw_cfg *req;
6b7c5b94
SP		 2089 int status;
2090
2984961c
IV		 2091 if (mutex_lock_interruptible(&adapter->mbox_lock))
2092 return -1;
6b7c5b94 2093
b31c50a7
SP		 2094 wrb = wrb_from_mbox(adapter);
2095 req = embedded_payload(wrb);
6b7c5b94 2096
106df1e3 2097 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 2098 OPCODE_COMMON_QUERY_FIRMWARE_CONFIG,
2099 sizeof(*req), wrb, NULL);
6b7c5b94 2100
b31c50a7 2101 status = be_mbox_notify_wait(adapter);
6b7c5b94
SP		 2102 if (!status) {
2103 struct be_cmd_resp_query_fw_cfg *resp = embedded_payload(wrb);
03d28ffe 2104
e97e3cda
KA		 2105 adapter->port_num = le32_to_cpu(resp->phys_port);
2106 adapter->function_mode = le32_to_cpu(resp->function_mode);
2107 adapter->function_caps = le32_to_cpu(resp->function_caps);
2108 adapter->asic_rev = le32_to_cpu(resp->asic_revision) & 0xFF;
acbafeb1
SP		 2109 dev_info(&adapter->pdev->dev,
2110 "FW config: function_mode=0x%x, function_caps=0x%x\n",
2111 adapter->function_mode, adapter->function_caps);
6b7c5b94
SP		 2112 }
2113
2984961c 2114 mutex_unlock(&adapter->mbox_lock);
6b7c5b94
SP		 2115 return status;
2116}
14074eab 2117
b31c50a7 2118/* Uses mbox */
14074eab 2119int be_cmd_reset_function(struct be_adapter *adapter)
2120{
b31c50a7
SP		 2121 struct be_mcc_wrb *wrb;
2122 struct be_cmd_req_hdr *req;
14074eab 2123 int status;
2124
bf99e50d
PR		 2125 if (lancer_chip(adapter)) {
2126 status = lancer_wait_ready(adapter);
2127 if (!status) {
2128 iowrite32(SLI_PORT_CONTROL_IP_MASK,
2129 adapter->db + SLIPORT_CONTROL_OFFSET);
2130 status = lancer_test_and_set_rdy_state(adapter);
2131 }
2132 if (status) {
2133 dev_err(&adapter->pdev->dev,
2134 "Adapter in non recoverable error\n");
2135 }
2136 return status;
2137 }
2138
2984961c
IV		 2139 if (mutex_lock_interruptible(&adapter->mbox_lock))
2140 return -1;
14074eab 2141
b31c50a7
SP		 2142 wrb = wrb_from_mbox(adapter);
2143 req = embedded_payload(wrb);
14074eab 2144
106df1e3 2145 be_wrb_cmd_hdr_prepare(req, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 2146 OPCODE_COMMON_FUNCTION_RESET, sizeof(*req), wrb,
2147 NULL);
14074eab 2148
b31c50a7 2149 status = be_mbox_notify_wait(adapter);
14074eab 2150
2984961c 2151 mutex_unlock(&adapter->mbox_lock);
14074eab 2152 return status;
2153}
84517482 2154
594ad54a 2155int be_cmd_rss_config(struct be_adapter *adapter, u8 *rsstable,
33cb0fa7 2156 u32 rss_hash_opts, u16 table_size, const u8 *rss_hkey)
3abcdeda
SP		 2157{
2158 struct be_mcc_wrb *wrb;
2159 struct be_cmd_req_rss_config *req;
3abcdeda
SP		 2160 int status;
2161
da1388d6
VV		 2162 if (!(be_if_cap_flags(adapter) & BE_IF_FLAGS_RSS))
2163 return 0;
2164
b51aa367 2165 spin_lock_bh(&adapter->mcc_lock);
3abcdeda 2166
b51aa367
KA		 2167 wrb = wrb_from_mccq(adapter);
2168 if (!wrb) {
2169 status = -EBUSY;
2170 goto err;
2171 }
3abcdeda
SP		 2172 req = embedded_payload(wrb);
2173
106df1e3 2174 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
a2cc4e0b 2175 OPCODE_ETH_RSS_CONFIG, sizeof(*req), wrb, NULL);
3abcdeda
SP		 2176
2177 req->if_id = cpu_to_le32(adapter->if_handle);
594ad54a
SR		 2178 req->enable_rss = cpu_to_le16(rss_hash_opts);
2179 req->cpu_table_size_log2 = cpu_to_le16(fls(table_size) - 1);
d3bd3a5e 2180
b51aa367 2181 if (!BEx_chip(adapter))
d3bd3a5e 2182 req->hdr.version = 1;
d3bd3a5e 2183
3abcdeda 2184 memcpy(req->cpu_table, rsstable, table_size);
e2557877 2185 memcpy(req->hash, rss_hkey, RSS_HASH_KEY_LEN);
3abcdeda
SP		 2186 be_dws_cpu_to_le(req->hash, sizeof(req->hash));
2187
b51aa367
KA		 2188 status = be_mcc_notify_wait(adapter);
2189err:
2190 spin_unlock_bh(&adapter->mcc_lock);
3abcdeda
SP		 2191 return status;
2192}
2193
fad9ab2c
SB		 2194/* Uses sync mcc */
2195int be_cmd_set_beacon_state(struct be_adapter *adapter, u8 port_num,
a2cc4e0b 2196 u8 bcn, u8 sts, u8 state)
fad9ab2c
SB		 2197{
2198 struct be_mcc_wrb *wrb;
2199 struct be_cmd_req_enable_disable_beacon *req;
2200 int status;
2201
2202 spin_lock_bh(&adapter->mcc_lock);
2203
2204 wrb = wrb_from_mccq(adapter);
713d0394
SP		 2205 if (!wrb) {
2206 status = -EBUSY;
2207 goto err;
2208 }
fad9ab2c
SB		 2209 req = embedded_payload(wrb);
2210
106df1e3 2211 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 2212 OPCODE_COMMON_ENABLE_DISABLE_BEACON,
2213 sizeof(*req), wrb, NULL);
fad9ab2c
SB		 2214
2215 req->port_num = port_num;
2216 req->beacon_state = state;
2217 req->beacon_duration = bcn;
2218 req->status_duration = sts;
2219
2220 status = be_mcc_notify_wait(adapter);
2221
713d0394 2222err:
fad9ab2c
SB		 2223 spin_unlock_bh(&adapter->mcc_lock);
2224 return status;
2225}
2226
2227/* Uses sync mcc */
2228int be_cmd_get_beacon_state(struct be_adapter *adapter, u8 port_num, u32 *state)
2229{
2230 struct be_mcc_wrb *wrb;
2231 struct be_cmd_req_get_beacon_state *req;
2232 int status;
2233
2234 spin_lock_bh(&adapter->mcc_lock);
2235
2236 wrb = wrb_from_mccq(adapter);
713d0394
SP		 2237 if (!wrb) {
2238 status = -EBUSY;
2239 goto err;
2240 }
fad9ab2c
SB		 2241 req = embedded_payload(wrb);
2242
106df1e3 2243 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 2244 OPCODE_COMMON_GET_BEACON_STATE, sizeof(*req),
2245 wrb, NULL);
fad9ab2c
SB		 2246
2247 req->port_num = port_num;
2248
2249 status = be_mcc_notify_wait(adapter);
2250 if (!status) {
2251 struct be_cmd_resp_get_beacon_state *resp =
2252 embedded_payload(wrb);
03d28ffe 2253
fad9ab2c
SB		 2254 *state = resp->beacon_state;
2255 }
2256
713d0394 2257err:
fad9ab2c
SB		 2258 spin_unlock_bh(&adapter->mcc_lock);
2259 return status;
2260}
2261
e36edd9d
ML		 2262/* Uses sync mcc */
2263int be_cmd_read_port_transceiver_data(struct be_adapter *adapter,
2264 u8 page_num, u8 *data)
2265{
2266 struct be_dma_mem cmd;
2267 struct be_mcc_wrb *wrb;
2268 struct be_cmd_req_port_type *req;
2269 int status;
2270
2271 if (page_num > TR_PAGE_A2)
2272 return -EINVAL;
2273
2274 cmd.size = sizeof(struct be_cmd_resp_port_type);
2275 cmd.va = pci_alloc_consistent(adapter->pdev, cmd.size, &cmd.dma);
2276 if (!cmd.va) {
2277 dev_err(&adapter->pdev->dev, "Memory allocation failed\n");
2278 return -ENOMEM;
2279 }
2280 memset(cmd.va, 0, cmd.size);
2281
2282 spin_lock_bh(&adapter->mcc_lock);
2283
2284 wrb = wrb_from_mccq(adapter);
2285 if (!wrb) {
2286 status = -EBUSY;
2287 goto err;
2288 }
2289 req = cmd.va;
2290
2291 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2292 OPCODE_COMMON_READ_TRANSRECV_DATA,
2293 cmd.size, wrb, &cmd);
2294
2295 req->port = cpu_to_le32(adapter->hba_port_num);
2296 req->page_num = cpu_to_le32(page_num);
2297 status = be_mcc_notify_wait(adapter);
2298 if (!status) {
2299 struct be_cmd_resp_port_type *resp = cmd.va;
2300
2301 memcpy(data, resp->page_data, PAGE_DATA_LEN);
2302 }
2303err:
2304 spin_unlock_bh(&adapter->mcc_lock);
2305 pci_free_consistent(adapter->pdev, cmd.size, cmd.va, cmd.dma);
2306 return status;
2307}
2308
485bf569 2309int lancer_cmd_write_object(struct be_adapter *adapter, struct be_dma_mem *cmd,
f67ef7ba
PR		 2310 u32 data_size, u32 data_offset,
2311 const char *obj_name, u32 *data_written,
2312 u8 *change_status, u8 *addn_status)
485bf569
SN		 2313{
2314 struct be_mcc_wrb *wrb;
2315 struct lancer_cmd_req_write_object *req;
2316 struct lancer_cmd_resp_write_object *resp;
2317 void *ctxt = NULL;
2318 int status;
2319
2320 spin_lock_bh(&adapter->mcc_lock);
2321 adapter->flash_status = 0;
2322
2323 wrb = wrb_from_mccq(adapter);
2324 if (!wrb) {
2325 status = -EBUSY;
2326 goto err_unlock;
2327 }
2328
2329 req = embedded_payload(wrb);
2330
106df1e3 2331 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 2332 OPCODE_COMMON_WRITE_OBJECT,
2333 sizeof(struct lancer_cmd_req_write_object), wrb,
2334 NULL);
485bf569
SN		 2335
2336 ctxt = &req->context;
2337 AMAP_SET_BITS(struct amap_lancer_write_obj_context,
a2cc4e0b 2338 write_length, ctxt, data_size);
485bf569
SN		 2339
2340 if (data_size == 0)
2341 AMAP_SET_BITS(struct amap_lancer_write_obj_context,
a2cc4e0b 2342 eof, ctxt, 1);
485bf569
SN		 2343 else
2344 AMAP_SET_BITS(struct amap_lancer_write_obj_context,
a2cc4e0b 2345 eof, ctxt, 0);
485bf569
SN		 2346
2347 be_dws_cpu_to_le(ctxt, sizeof(req->context));
2348 req->write_offset = cpu_to_le32(data_offset);
242eb470 2349 strlcpy(req->object_name, obj_name, sizeof(req->object_name));
485bf569
SN		 2350 req->descriptor_count = cpu_to_le32(1);
2351 req->buf_len = cpu_to_le32(data_size);
2352 req->addr_low = cpu_to_le32((cmd->dma +
a2cc4e0b
SP		 2353 sizeof(struct lancer_cmd_req_write_object))
2354 & 0xFFFFFFFF);
485bf569
SN		 2355 req->addr_high = cpu_to_le32(upper_32_bits(cmd->dma +
2356 sizeof(struct lancer_cmd_req_write_object)));
2357
2358 be_mcc_notify(adapter);
2359 spin_unlock_bh(&adapter->mcc_lock);
2360
5eeff635 2361 if (!wait_for_completion_timeout(&adapter->et_cmd_compl,
701962d0 2362 msecs_to_jiffies(60000)))
fd45160c 2363 status = -ETIMEDOUT;
485bf569
SN		 2364 else
2365 status = adapter->flash_status;
2366
2367 resp = embedded_payload(wrb);
f67ef7ba 2368 if (!status) {
485bf569 2369 *data_written = le32_to_cpu(resp->actual_write_len);
f67ef7ba
PR		 2370 *change_status = resp->change_status;
2371 } else {
485bf569 2372 *addn_status = resp->additional_status;
f67ef7ba 2373 }
485bf569
SN		 2374
2375 return status;
2376
2377err_unlock:
2378 spin_unlock_bh(&adapter->mcc_lock);
2379 return status;
2380}
2381
6809cee0
RN		 2382int be_cmd_query_cable_type(struct be_adapter *adapter)
2383{
2384 u8 page_data[PAGE_DATA_LEN];
2385 int status;
2386
2387 status = be_cmd_read_port_transceiver_data(adapter, TR_PAGE_A0,
2388 page_data);
2389 if (!status) {
2390 switch (adapter->phy.interface_type) {
2391 case PHY_TYPE_QSFP:
2392 adapter->phy.cable_type =
2393 page_data[QSFP_PLUS_CABLE_TYPE_OFFSET];
2394 break;
2395 case PHY_TYPE_SFP_PLUS_10GB:
2396 adapter->phy.cable_type =
2397 page_data[SFP_PLUS_CABLE_TYPE_OFFSET];
2398 break;
2399 default:
2400 adapter->phy.cable_type = 0;
2401 break;
2402 }
2403 }
2404 return status;
2405}
2406
21252377
VV		 2407int be_cmd_query_sfp_info(struct be_adapter *adapter)
2408{
2409 u8 page_data[PAGE_DATA_LEN];
2410 int status;
2411
2412 status = be_cmd_read_port_transceiver_data(adapter, TR_PAGE_A0,
2413 page_data);
2414 if (!status) {
2415 strlcpy(adapter->phy.vendor_name, page_data +
2416 SFP_VENDOR_NAME_OFFSET, SFP_VENDOR_NAME_LEN - 1);
2417 strlcpy(adapter->phy.vendor_pn,
2418 page_data + SFP_VENDOR_PN_OFFSET,
2419 SFP_VENDOR_NAME_LEN - 1);
2420 }
2421
2422 return status;
2423}
2424
f0613380
KA		 2425int lancer_cmd_delete_object(struct be_adapter *adapter, const char *obj_name)
2426{
2427 struct lancer_cmd_req_delete_object *req;
2428 struct be_mcc_wrb *wrb;
2429 int status;
2430
2431 spin_lock_bh(&adapter->mcc_lock);
2432
2433 wrb = wrb_from_mccq(adapter);
2434 if (!wrb) {
2435 status = -EBUSY;
2436 goto err;
2437 }
2438
2439 req = embedded_payload(wrb);
2440
2441 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2442 OPCODE_COMMON_DELETE_OBJECT,
2443 sizeof(*req), wrb, NULL);
2444
242eb470 2445 strlcpy(req->object_name, obj_name, sizeof(req->object_name));
f0613380
KA		 2446
2447 status = be_mcc_notify_wait(adapter);
2448err:
2449 spin_unlock_bh(&adapter->mcc_lock);
2450 return status;
2451}
2452
de49bd5a 2453int lancer_cmd_read_object(struct be_adapter *adapter, struct be_dma_mem *cmd,
a2cc4e0b
SP		 2454 u32 data_size, u32 data_offset, const char *obj_name,
2455 u32 *data_read, u32 *eof, u8 *addn_status)
de49bd5a
PR		 2456{
2457 struct be_mcc_wrb *wrb;
2458 struct lancer_cmd_req_read_object *req;
2459 struct lancer_cmd_resp_read_object *resp;
2460 int status;
2461
2462 spin_lock_bh(&adapter->mcc_lock);
2463
2464 wrb = wrb_from_mccq(adapter);
2465 if (!wrb) {
2466 status = -EBUSY;
2467 goto err_unlock;
2468 }
2469
2470 req = embedded_payload(wrb);
2471
2472 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 2473 OPCODE_COMMON_READ_OBJECT,
2474 sizeof(struct lancer_cmd_req_read_object), wrb,
2475 NULL);
de49bd5a
PR		 2476
2477 req->desired_read_len = cpu_to_le32(data_size);
2478 req->read_offset = cpu_to_le32(data_offset);
2479 strcpy(req->object_name, obj_name);
2480 req->descriptor_count = cpu_to_le32(1);
2481 req->buf_len = cpu_to_le32(data_size);
2482 req->addr_low = cpu_to_le32((cmd->dma & 0xFFFFFFFF));
2483 req->addr_high = cpu_to_le32(upper_32_bits(cmd->dma));
2484
2485 status = be_mcc_notify_wait(adapter);
2486
2487 resp = embedded_payload(wrb);
2488 if (!status) {
2489 *data_read = le32_to_cpu(resp->actual_read_len);
2490 *eof = le32_to_cpu(resp->eof);
2491 } else {
2492 *addn_status = resp->additional_status;
2493 }
2494
2495err_unlock:
2496 spin_unlock_bh(&adapter->mcc_lock);
2497 return status;
2498}
2499
84517482 2500int be_cmd_write_flashrom(struct be_adapter *adapter, struct be_dma_mem *cmd,
70a7b525
VV		 2501 u32 flash_type, u32 flash_opcode, u32 img_offset,
2502 u32 buf_size)
84517482 2503{
b31c50a7 2504 struct be_mcc_wrb *wrb;
3f0d4560 2505 struct be_cmd_write_flashrom *req;
84517482
AK		 2506 int status;
2507
b31c50a7 2508 spin_lock_bh(&adapter->mcc_lock);
dd131e76 2509 adapter->flash_status = 0;
b31c50a7
SP		 2510
2511 wrb = wrb_from_mccq(adapter);
713d0394
SP		 2512 if (!wrb) {
2513 status = -EBUSY;
2892d9c2 2514 goto err_unlock;
713d0394
SP		 2515 }
2516 req = cmd->va;
84517482 2517
106df1e3 2518 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 2519 OPCODE_COMMON_WRITE_FLASHROM, cmd->size, wrb,
2520 cmd);
84517482
AK		 2521
2522 req->params.op_type = cpu_to_le32(flash_type);
70a7b525
VV		 2523 if (flash_type == OPTYPE_OFFSET_SPECIFIED)
2524 req->params.offset = cpu_to_le32(img_offset);
2525
84517482
AK		 2526 req->params.op_code = cpu_to_le32(flash_opcode);
2527 req->params.data_buf_size = cpu_to_le32(buf_size);
2528
dd131e76
SB		 2529 be_mcc_notify(adapter);
2530 spin_unlock_bh(&adapter->mcc_lock);
2531
5eeff635
SR		 2532 if (!wait_for_completion_timeout(&adapter->et_cmd_compl,
2533 msecs_to_jiffies(40000)))
fd45160c 2534 status = -ETIMEDOUT;
dd131e76
SB		 2535 else
2536 status = adapter->flash_status;
84517482 2537
2892d9c2
DC		 2538 return status;
2539
2540err_unlock:
2541 spin_unlock_bh(&adapter->mcc_lock);
84517482
AK		 2542 return status;
2543}
fa9a6fed 2544
3f0d4560 2545int be_cmd_get_flash_crc(struct be_adapter *adapter, u8 *flashed_crc,
70a7b525 2546 u16 img_optype, u32 img_offset, u32 crc_offset)
fa9a6fed 2547{
be716446 2548 struct be_cmd_read_flash_crc *req;
70a7b525 2549 struct be_mcc_wrb *wrb;
fa9a6fed
SB		 2550 int status;
2551
2552 spin_lock_bh(&adapter->mcc_lock);
2553
2554 wrb = wrb_from_mccq(adapter);
713d0394
SP		 2555 if (!wrb) {
2556 status = -EBUSY;
2557 goto err;
2558 }
fa9a6fed
SB		 2559 req = embedded_payload(wrb);
2560
106df1e3 2561 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
be716446
PR		 2562 OPCODE_COMMON_READ_FLASHROM, sizeof(*req),
2563 wrb, NULL);
fa9a6fed 2564
70a7b525
VV		 2565 req->params.op_type = cpu_to_le32(img_optype);
2566 if (img_optype == OPTYPE_OFFSET_SPECIFIED)
2567 req->params.offset = cpu_to_le32(img_offset + crc_offset);
2568 else
2569 req->params.offset = cpu_to_le32(crc_offset);
2570
fa9a6fed 2571 req->params.op_code = cpu_to_le32(FLASHROM_OPER_REPORT);
8b93b710 2572 req->params.data_buf_size = cpu_to_le32(0x4);
fa9a6fed
SB		 2573
2574 status = be_mcc_notify_wait(adapter);
2575 if (!status)
be716446 2576 memcpy(flashed_crc, req->crc, 4);
fa9a6fed 2577
713d0394 2578err:
fa9a6fed
SB		 2579 spin_unlock_bh(&adapter->mcc_lock);
2580 return status;
2581}
71d8d1b5 2582
c196b02c 2583int be_cmd_enable_magic_wol(struct be_adapter *adapter, u8 *mac,
a2cc4e0b 2584 struct be_dma_mem *nonemb_cmd)
71d8d1b5
AK		 2585{
2586 struct be_mcc_wrb *wrb;
2587 struct be_cmd_req_acpi_wol_magic_config *req;
71d8d1b5
AK		 2588 int status;
2589
2590 spin_lock_bh(&adapter->mcc_lock);
2591
2592 wrb = wrb_from_mccq(adapter);
2593 if (!wrb) {
2594 status = -EBUSY;
2595 goto err;
2596 }
2597 req = nonemb_cmd->va;
71d8d1b5 2598
106df1e3 2599 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
a2cc4e0b
SP		 2600 OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG, sizeof(*req),
2601 wrb, nonemb_cmd);
71d8d1b5
AK		 2602 memcpy(req->magic_mac, mac, ETH_ALEN);
2603
71d8d1b5
AK		 2604 status = be_mcc_notify_wait(adapter);
2605
2606err:
2607 spin_unlock_bh(&adapter->mcc_lock);
2608 return status;
2609}
ff33a6e2 2610
fced9999
SB		 2611int be_cmd_set_loopback(struct be_adapter *adapter, u8 port_num,
2612 u8 loopback_type, u8 enable)
2613{
2614 struct be_mcc_wrb *wrb;
2615 struct be_cmd_req_set_lmode *req;
2616 int status;
2617
2618 spin_lock_bh(&adapter->mcc_lock);
2619
2620 wrb = wrb_from_mccq(adapter);
2621 if (!wrb) {
2622 status = -EBUSY;
2623 goto err;
2624 }
2625
2626 req = embedded_payload(wrb);
2627
106df1e3 2628 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
a2cc4e0b
SP		 2629 OPCODE_LOWLEVEL_SET_LOOPBACK_MODE, sizeof(*req),
2630 wrb, NULL);
fced9999
SB		 2631
2632 req->src_port = port_num;
2633 req->dest_port = port_num;
2634 req->loopback_type = loopback_type;
2635 req->loopback_state = enable;
2636
2637 status = be_mcc_notify_wait(adapter);
2638err:
2639 spin_unlock_bh(&adapter->mcc_lock);
2640 return status;
2641}
2642
ff33a6e2 2643int be_cmd_loopback_test(struct be_adapter *adapter, u32 port_num,
a2cc4e0b
SP		 2644 u32 loopback_type, u32 pkt_size, u32 num_pkts,
2645 u64 pattern)
ff33a6e2
S		 2646{
2647 struct be_mcc_wrb *wrb;
2648 struct be_cmd_req_loopback_test *req;
5eeff635 2649 struct be_cmd_resp_loopback_test *resp;
ff33a6e2
S		 2650 int status;
2651
2652 spin_lock_bh(&adapter->mcc_lock);
2653
2654 wrb = wrb_from_mccq(adapter);
2655 if (!wrb) {
2656 status = -EBUSY;
2657 goto err;
2658 }
2659
2660 req = embedded_payload(wrb);
2661
106df1e3 2662 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
a2cc4e0b
SP		 2663 OPCODE_LOWLEVEL_LOOPBACK_TEST, sizeof(*req), wrb,
2664 NULL);
ff33a6e2 2665
5eeff635 2666 req->hdr.timeout = cpu_to_le32(15);
ff33a6e2
S		 2667 req->pattern = cpu_to_le64(pattern);
2668 req->src_port = cpu_to_le32(port_num);
2669 req->dest_port = cpu_to_le32(port_num);
2670 req->pkt_size = cpu_to_le32(pkt_size);
2671 req->num_pkts = cpu_to_le32(num_pkts);
2672 req->loopback_type = cpu_to_le32(loopback_type);
2673
5eeff635
SR		 2674 be_mcc_notify(adapter);
2675
2676 spin_unlock_bh(&adapter->mcc_lock);
ff33a6e2 2677
5eeff635
SR		 2678 wait_for_completion(&adapter->et_cmd_compl);
2679 resp = embedded_payload(wrb);
2680 status = le32_to_cpu(resp->status);
2681
2682 return status;
ff33a6e2
S		 2683err:
2684 spin_unlock_bh(&adapter->mcc_lock);
2685 return status;
2686}
2687
2688int be_cmd_ddr_dma_test(struct be_adapter *adapter, u64 pattern,
a2cc4e0b 2689 u32 byte_cnt, struct be_dma_mem *cmd)
ff33a6e2
S		 2690{
2691 struct be_mcc_wrb *wrb;
2692 struct be_cmd_req_ddrdma_test *req;
ff33a6e2
S		 2693 int status;
2694 int i, j = 0;
2695
2696 spin_lock_bh(&adapter->mcc_lock);
2697
2698 wrb = wrb_from_mccq(adapter);
2699 if (!wrb) {
2700 status = -EBUSY;
2701 goto err;
2702 }
2703 req = cmd->va;
106df1e3 2704 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
a2cc4e0b
SP		 2705 OPCODE_LOWLEVEL_HOST_DDR_DMA, cmd->size, wrb,
2706 cmd);
ff33a6e2
S		 2707
2708 req->pattern = cpu_to_le64(pattern);
2709 req->byte_count = cpu_to_le32(byte_cnt);
2710 for (i = 0; i < byte_cnt; i++) {
2711 req->snd_buff[i] = (u8)(pattern >> (j*8));
2712 j++;
2713 if (j > 7)
2714 j = 0;
2715 }
2716
2717 status = be_mcc_notify_wait(adapter);
2718
2719 if (!status) {
2720 struct be_cmd_resp_ddrdma_test *resp;
03d28ffe 2721
ff33a6e2
S		 2722 resp = cmd->va;
2723 if ((memcmp(resp->rcv_buff, req->snd_buff, byte_cnt) != 0) ||
cd3307aa 2724 resp->snd_err) {
ff33a6e2
S		 2725 status = -1;
2726 }
2727 }
2728
2729err:
2730 spin_unlock_bh(&adapter->mcc_lock);
2731 return status;
2732}
368c0ca2 2733
c196b02c 2734int be_cmd_get_seeprom_data(struct be_adapter *adapter,
a2cc4e0b 2735 struct be_dma_mem *nonemb_cmd)
368c0ca2
SB		 2736{
2737 struct be_mcc_wrb *wrb;
2738 struct be_cmd_req_seeprom_read *req;
368c0ca2
SB		 2739 int status;
2740
2741 spin_lock_bh(&adapter->mcc_lock);
2742
2743 wrb = wrb_from_mccq(adapter);
e45ff01d
AK		 2744 if (!wrb) {
2745 status = -EBUSY;
2746 goto err;
2747 }
368c0ca2 2748 req = nonemb_cmd->va;
368c0ca2 2749
106df1e3 2750 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 2751 OPCODE_COMMON_SEEPROM_READ, sizeof(*req), wrb,
2752 nonemb_cmd);
368c0ca2
SB		 2753
2754 status = be_mcc_notify_wait(adapter);
2755
e45ff01d 2756err:
368c0ca2
SB		 2757 spin_unlock_bh(&adapter->mcc_lock);
2758 return status;
2759}
ee3cb629 2760
42f11cf2 2761int be_cmd_get_phy_info(struct be_adapter *adapter)
ee3cb629
AK		 2762{
2763 struct be_mcc_wrb *wrb;
2764 struct be_cmd_req_get_phy_info *req;
306f1348 2765 struct be_dma_mem cmd;
ee3cb629
AK		 2766 int status;
2767
f25b119c
PR		 2768 if (!be_cmd_allowed(adapter, OPCODE_COMMON_GET_PHY_DETAILS,
2769 CMD_SUBSYSTEM_COMMON))
2770 return -EPERM;
2771
ee3cb629
AK		 2772 spin_lock_bh(&adapter->mcc_lock);
2773
2774 wrb = wrb_from_mccq(adapter);
2775 if (!wrb) {
2776 status = -EBUSY;
2777 goto err;
2778 }
306f1348 2779 cmd.size = sizeof(struct be_cmd_req_get_phy_info);
a2cc4e0b 2780 cmd.va = pci_alloc_consistent(adapter->pdev, cmd.size, &cmd.dma);
306f1348
SP		 2781 if (!cmd.va) {
2782 dev_err(&adapter->pdev->dev, "Memory alloc failure\n");
2783 status = -ENOMEM;
2784 goto err;
2785 }
ee3cb629 2786
306f1348 2787 req = cmd.va;
ee3cb629 2788
106df1e3 2789 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 2790 OPCODE_COMMON_GET_PHY_DETAILS, sizeof(*req),
2791 wrb, &cmd);
ee3cb629
AK		 2792
2793 status = be_mcc_notify_wait(adapter);
306f1348
SP		 2794 if (!status) {
2795 struct be_phy_info *resp_phy_info =
2796 cmd.va + sizeof(struct be_cmd_req_hdr);
03d28ffe 2797
42f11cf2
AK		 2798 adapter->phy.phy_type = le16_to_cpu(resp_phy_info->phy_type);
2799 adapter->phy.interface_type =
306f1348 2800 le16_to_cpu(resp_phy_info->interface_type);
42f11cf2
AK		 2801 adapter->phy.auto_speeds_supported =
2802 le16_to_cpu(resp_phy_info->auto_speeds_supported);
2803 adapter->phy.fixed_speeds_supported =
2804 le16_to_cpu(resp_phy_info->fixed_speeds_supported);
2805 adapter->phy.misc_params =
2806 le32_to_cpu(resp_phy_info->misc_params);
68cb7e47
VV		 2807
2808 if (BE2_chip(adapter)) {
2809 adapter->phy.fixed_speeds_supported =
2810 BE_SUPPORTED_SPEED_10GBPS |
2811 BE_SUPPORTED_SPEED_1GBPS;
2812 }
306f1348 2813 }
a2cc4e0b 2814 pci_free_consistent(adapter->pdev, cmd.size, cmd.va, cmd.dma);
ee3cb629
AK		 2815err:
2816 spin_unlock_bh(&adapter->mcc_lock);
2817 return status;
2818}
e1d18735 2819
bc0ee163 2820static int be_cmd_set_qos(struct be_adapter *adapter, u32 bps, u32 domain)
e1d18735
AK		 2821{
2822 struct be_mcc_wrb *wrb;
2823 struct be_cmd_req_set_qos *req;
2824 int status;
2825
2826 spin_lock_bh(&adapter->mcc_lock);
2827
2828 wrb = wrb_from_mccq(adapter);
2829 if (!wrb) {
2830 status = -EBUSY;
2831 goto err;
2832 }
2833
2834 req = embedded_payload(wrb);
2835
106df1e3 2836 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b 2837 OPCODE_COMMON_SET_QOS, sizeof(*req), wrb, NULL);
e1d18735
AK		 2838
2839 req->hdr.domain = domain;
6bff57a7
AK		 2840 req->valid_bits = cpu_to_le32(BE_QOS_BITS_NIC);
2841 req->max_bps_nic = cpu_to_le32(bps);
e1d18735
AK		 2842
2843 status = be_mcc_notify_wait(adapter);
2844
2845err:
2846 spin_unlock_bh(&adapter->mcc_lock);
2847 return status;
2848}
9e1453c5
AK		 2849
2850int be_cmd_get_cntl_attributes(struct be_adapter *adapter)
2851{
2852 struct be_mcc_wrb *wrb;
2853 struct be_cmd_req_cntl_attribs *req;
2854 struct be_cmd_resp_cntl_attribs *resp;
9e1453c5
AK		 2855 int status;
2856 int payload_len = max(sizeof(*req), sizeof(*resp));
2857 struct mgmt_controller_attrib *attribs;
2858 struct be_dma_mem attribs_cmd;
2859
d98ef50f
SR		 2860 if (mutex_lock_interruptible(&adapter->mbox_lock))
2861 return -1;
2862
9e1453c5
AK		 2863 memset(&attribs_cmd, 0, sizeof(struct be_dma_mem));
2864 attribs_cmd.size = sizeof(struct be_cmd_resp_cntl_attribs);
2865 attribs_cmd.va = pci_alloc_consistent(adapter->pdev, attribs_cmd.size,
a2cc4e0b 2866 &attribs_cmd.dma);
9e1453c5 2867 if (!attribs_cmd.va) {
a2cc4e0b 2868 dev_err(&adapter->pdev->dev, "Memory allocation failure\n");
d98ef50f
SR		 2869 status = -ENOMEM;
2870 goto err;
9e1453c5
AK		 2871 }
2872
9e1453c5
AK		 2873 wrb = wrb_from_mbox(adapter);
2874 if (!wrb) {
2875 status = -EBUSY;
2876 goto err;
2877 }
2878 req = attribs_cmd.va;
9e1453c5 2879
106df1e3 2880 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 2881 OPCODE_COMMON_GET_CNTL_ATTRIBUTES, payload_len,
2882 wrb, &attribs_cmd);
9e1453c5
AK		 2883
2884 status = be_mbox_notify_wait(adapter);
2885 if (!status) {
43d620c8 2886 attribs = attribs_cmd.va + sizeof(struct be_cmd_resp_hdr);
9e1453c5
AK		 2887 adapter->hba_port_num = attribs->hba_attribs.phy_port;
2888 }
2889
2890err:
2891 mutex_unlock(&adapter->mbox_lock);
d98ef50f
SR		 2892 if (attribs_cmd.va)
2893 pci_free_consistent(adapter->pdev, attribs_cmd.size,
2894 attribs_cmd.va, attribs_cmd.dma);
9e1453c5
AK		 2895 return status;
2896}
2e588f84
SP		 2897
2898/* Uses mbox */
2dc1deb6 2899int be_cmd_req_native_mode(struct be_adapter *adapter)
2e588f84
SP		 2900{
2901 struct be_mcc_wrb *wrb;
2902 struct be_cmd_req_set_func_cap *req;
2903 int status;
2904
2905 if (mutex_lock_interruptible(&adapter->mbox_lock))
2906 return -1;
2907
2908 wrb = wrb_from_mbox(adapter);
2909 if (!wrb) {
2910 status = -EBUSY;
2911 goto err;
2912 }
2913
2914 req = embedded_payload(wrb);
2915
106df1e3 2916 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 2917 OPCODE_COMMON_SET_DRIVER_FUNCTION_CAP,
2918 sizeof(*req), wrb, NULL);
2e588f84
SP		 2919
2920 req->valid_cap_flags = cpu_to_le32(CAPABILITY_SW_TIMESTAMPS |
2921 CAPABILITY_BE3_NATIVE_ERX_API);
2922 req->cap_flags = cpu_to_le32(CAPABILITY_BE3_NATIVE_ERX_API);
2923
2924 status = be_mbox_notify_wait(adapter);
2925 if (!status) {
2926 struct be_cmd_resp_set_func_cap *resp = embedded_payload(wrb);
03d28ffe 2927
2e588f84
SP		 2928 adapter->be3_native = le32_to_cpu(resp->cap_flags) &
2929 CAPABILITY_BE3_NATIVE_ERX_API;
d379142b
SP		 2930 if (!adapter->be3_native)
2931 dev_warn(&adapter->pdev->dev,
2932 "adapter not in advanced mode\n");
2e588f84
SP		 2933 }
2934err:
2935 mutex_unlock(&adapter->mbox_lock);
2936 return status;
2937}
590c391d 2938
f25b119c
PR		 2939/* Get privilege(s) for a function */
2940int be_cmd_get_fn_privileges(struct be_adapter *adapter, u32 *privilege,
2941 u32 domain)
2942{
2943 struct be_mcc_wrb *wrb;
2944 struct be_cmd_req_get_fn_privileges *req;
2945 int status;
2946
2947 spin_lock_bh(&adapter->mcc_lock);
2948
2949 wrb = wrb_from_mccq(adapter);
2950 if (!wrb) {
2951 status = -EBUSY;
2952 goto err;
2953 }
2954
2955 req = embedded_payload(wrb);
2956
2957 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2958 OPCODE_COMMON_GET_FN_PRIVILEGES, sizeof(*req),
2959 wrb, NULL);
2960
2961 req->hdr.domain = domain;
2962
2963 status = be_mcc_notify_wait(adapter);
2964 if (!status) {
2965 struct be_cmd_resp_get_fn_privileges *resp =
2966 embedded_payload(wrb);
03d28ffe 2967
f25b119c 2968 *privilege = le32_to_cpu(resp->privilege_mask);
02308d74
SR		 2969
2970 /* In UMC mode FW does not return right privileges.
2971 * Override with correct privilege equivalent to PF.
2972 */
2973 if (BEx_chip(adapter) && be_is_mc(adapter) &&
2974 be_physfn(adapter))
2975 *privilege = MAX_PRIVILEGES;
f25b119c
PR		 2976 }
2977
2978err:
2979 spin_unlock_bh(&adapter->mcc_lock);
2980 return status;
2981}
2982
04a06028
SP		 2983/* Set privilege(s) for a function */
2984int be_cmd_set_fn_privileges(struct be_adapter *adapter, u32 privileges,
2985 u32 domain)
2986{
2987 struct be_mcc_wrb *wrb;
2988 struct be_cmd_req_set_fn_privileges *req;
2989 int status;
2990
2991 spin_lock_bh(&adapter->mcc_lock);
2992
2993 wrb = wrb_from_mccq(adapter);
2994 if (!wrb) {
2995 status = -EBUSY;
2996 goto err;
2997 }
2998
2999 req = embedded_payload(wrb);
3000 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3001 OPCODE_COMMON_SET_FN_PRIVILEGES, sizeof(*req),
3002 wrb, NULL);
3003 req->hdr.domain = domain;
3004 if (lancer_chip(adapter))
3005 req->privileges_lancer = cpu_to_le32(privileges);
3006 else
3007 req->privileges = cpu_to_le32(privileges);
3008
3009 status = be_mcc_notify_wait(adapter);
3010err:
3011 spin_unlock_bh(&adapter->mcc_lock);
3012 return status;
3013}
3014
5a712c13
SP		 3015/* pmac_id_valid: true => pmac_id is supplied and MAC address is requested.
3016 * pmac_id_valid: false => pmac_id or MAC address is requested.
3017 * If pmac_id is returned, pmac_id_valid is returned as true
3018 */
1578e777 3019int be_cmd_get_mac_from_list(struct be_adapter *adapter, u8 *mac,
b188f090
SR		 3020 bool *pmac_id_valid, u32 *pmac_id, u32 if_handle,
3021 u8 domain)
590c391d
PR		 3022{
3023 struct be_mcc_wrb *wrb;
3024 struct be_cmd_req_get_mac_list *req;
3025 int status;
3026 int mac_count;
e5e1ee89
PR		 3027 struct be_dma_mem get_mac_list_cmd;
3028 int i;
3029
3030 memset(&get_mac_list_cmd, 0, sizeof(struct be_dma_mem));
3031 get_mac_list_cmd.size = sizeof(struct be_cmd_resp_get_mac_list);
3032 get_mac_list_cmd.va = pci_alloc_consistent(adapter->pdev,
a2cc4e0b
SP		 3033 get_mac_list_cmd.size,
3034 &get_mac_list_cmd.dma);
e5e1ee89
PR		 3035
3036 if (!get_mac_list_cmd.va) {
3037 dev_err(&adapter->pdev->dev,
a2cc4e0b 3038 "Memory allocation failure during GET_MAC_LIST\n");
e5e1ee89
PR		 3039 return -ENOMEM;
3040 }
590c391d
PR		 3041
3042 spin_lock_bh(&adapter->mcc_lock);
3043
3044 wrb = wrb_from_mccq(adapter);
3045 if (!wrb) {
3046 status = -EBUSY;
e5e1ee89 3047 goto out;
590c391d 3048 }
e5e1ee89
PR		 3049
3050 req = get_mac_list_cmd.va;
590c391d
PR		 3051
3052 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
bf591f51
SP		 3053 OPCODE_COMMON_GET_MAC_LIST,
3054 get_mac_list_cmd.size, wrb, &get_mac_list_cmd);
590c391d 3055 req->hdr.domain = domain;
e5e1ee89 3056 req->mac_type = MAC_ADDRESS_TYPE_NETWORK;
5a712c13
SP		 3057 if (*pmac_id_valid) {
3058 req->mac_id = cpu_to_le32(*pmac_id);
b188f090 3059 req->iface_id = cpu_to_le16(if_handle);
5a712c13
SP		 3060 req->perm_override = 0;
3061 } else {
3062 req->perm_override = 1;
3063 }
590c391d
PR		 3064
3065 status = be_mcc_notify_wait(adapter);
3066 if (!status) {
3067 struct be_cmd_resp_get_mac_list *resp =
e5e1ee89 3068 get_mac_list_cmd.va;
5a712c13
SP		 3069
3070 if (*pmac_id_valid) {
3071 memcpy(mac, resp->macid_macaddr.mac_addr_id.macaddr,
3072 ETH_ALEN);
3073 goto out;
3074 }
3075
e5e1ee89
PR		 3076 mac_count = resp->true_mac_count + resp->pseudo_mac_count;
3077 /* Mac list returned could contain one or more active mac_ids
1578e777
PR		 3078 * or one or more true or pseudo permanant mac addresses.
3079 * If an active mac_id is present, return first active mac_id
3080 * found.
e5e1ee89 3081 */
590c391d 3082 for (i = 0; i < mac_count; i++) {
e5e1ee89
PR		 3083 struct get_list_macaddr *mac_entry;
3084 u16 mac_addr_size;
3085 u32 mac_id;
3086
3087 mac_entry = &resp->macaddr_list[i];
3088 mac_addr_size = le16_to_cpu(mac_entry->mac_addr_size);
3089 /* mac_id is a 32 bit value and mac_addr size
3090 * is 6 bytes
3091 */
3092 if (mac_addr_size == sizeof(u32)) {
5a712c13 3093 *pmac_id_valid = true;
e5e1ee89
PR		 3094 mac_id = mac_entry->mac_addr_id.s_mac_id.mac_id;
3095 *pmac_id = le32_to_cpu(mac_id);
3096 goto out;
590c391d 3097 }
590c391d 3098 }
1578e777 3099 /* If no active mac_id found, return first mac addr */
5a712c13 3100 *pmac_id_valid = false;
e5e1ee89 3101 memcpy(mac, resp->macaddr_list[0].mac_addr_id.macaddr,
a2cc4e0b 3102 ETH_ALEN);
590c391d
PR		 3103 }
3104
e5e1ee89 3105out:
590c391d 3106 spin_unlock_bh(&adapter->mcc_lock);
e5e1ee89 3107 pci_free_consistent(adapter->pdev, get_mac_list_cmd.size,
a2cc4e0b 3108 get_mac_list_cmd.va, get_mac_list_cmd.dma);
590c391d
PR		 3109 return status;
3110}
3111
a2cc4e0b
SP		 3112int be_cmd_get_active_mac(struct be_adapter *adapter, u32 curr_pmac_id,
3113 u8 *mac, u32 if_handle, bool active, u32 domain)
5a712c13 3114{
b188f090
SR		 3115 if (!active)
3116 be_cmd_get_mac_from_list(adapter, mac, &active, &curr_pmac_id,
3117 if_handle, domain);
3175d8c2 3118 if (BEx_chip(adapter))
5a712c13 3119 return be_cmd_mac_addr_query(adapter, mac, false,
b188f090 3120 if_handle, curr_pmac_id);
3175d8c2
SP		 3121 else
3122 /* Fetch the MAC address using pmac_id */
3123 return be_cmd_get_mac_from_list(adapter, mac, &active,
b188f090
SR		 3124 &curr_pmac_id,
3125 if_handle, domain);
5a712c13
SP		 3126}
3127
95046b92
SP		 3128int be_cmd_get_perm_mac(struct be_adapter *adapter, u8 *mac)
3129{
3130 int status;
3131 bool pmac_valid = false;
3132
3133 memset(mac, 0, ETH_ALEN);
3134
3175d8c2
SP		 3135 if (BEx_chip(adapter)) {
3136 if (be_physfn(adapter))
3137 status = be_cmd_mac_addr_query(adapter, mac, true, 0,
3138 0);
3139 else
3140 status = be_cmd_mac_addr_query(adapter, mac, false,
3141 adapter->if_handle, 0);
3142 } else {
95046b92 3143 status = be_cmd_get_mac_from_list(adapter, mac, &pmac_valid,
b188f090 3144 NULL, adapter->if_handle, 0);
3175d8c2
SP		 3145 }
3146
95046b92
SP		 3147 return status;
3148}
3149
590c391d
PR		 3150/* Uses synchronous MCCQ */
3151int be_cmd_set_mac_list(struct be_adapter *adapter, u8 *mac_array,
3152 u8 mac_count, u32 domain)
3153{
3154 struct be_mcc_wrb *wrb;
3155 struct be_cmd_req_set_mac_list *req;
3156 int status;
3157 struct be_dma_mem cmd;
3158
3159 memset(&cmd, 0, sizeof(struct be_dma_mem));
3160 cmd.size = sizeof(struct be_cmd_req_set_mac_list);
3161 cmd.va = dma_alloc_coherent(&adapter->pdev->dev, cmd.size,
a2cc4e0b 3162 &cmd.dma, GFP_KERNEL);
d0320f75 3163 if (!cmd.va)
590c391d 3164 return -ENOMEM;
590c391d
PR		 3165
3166 spin_lock_bh(&adapter->mcc_lock);
3167
3168 wrb = wrb_from_mccq(adapter);
3169 if (!wrb) {
3170 status = -EBUSY;
3171 goto err;
3172 }
3173
3174 req = cmd.va;
3175 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 3176 OPCODE_COMMON_SET_MAC_LIST, sizeof(*req),
3177 wrb, &cmd);
590c391d
PR		 3178
3179 req->hdr.domain = domain;
3180 req->mac_count = mac_count;
3181 if (mac_count)
3182 memcpy(req->mac, mac_array, ETH_ALEN*mac_count);
3183
3184 status = be_mcc_notify_wait(adapter);
3185
3186err:
a2cc4e0b 3187 dma_free_coherent(&adapter->pdev->dev, cmd.size, cmd.va, cmd.dma);
590c391d
PR		 3188 spin_unlock_bh(&adapter->mcc_lock);
3189 return status;
3190}
4762f6ce 3191
3175d8c2
SP		 3192/* Wrapper to delete any active MACs and provision the new mac.
3193 * Changes to MAC_LIST are allowed iff none of the MAC addresses in the
3194 * current list are active.
3195 */
3196int be_cmd_set_mac(struct be_adapter *adapter, u8 *mac, int if_id, u32 dom)
3197{
3198 bool active_mac = false;
3199 u8 old_mac[ETH_ALEN];
3200 u32 pmac_id;
3201 int status;
3202
3203 status = be_cmd_get_mac_from_list(adapter, old_mac, &active_mac,
b188f090
SR		 3204 &pmac_id, if_id, dom);
3205
3175d8c2
SP		 3206 if (!status && active_mac)
3207 be_cmd_pmac_del(adapter, if_id, pmac_id, dom);
3208
3209 return be_cmd_set_mac_list(adapter, mac, mac ? 1 : 0, dom);
3210}
3211
f1f3ee1b 3212int be_cmd_set_hsw_config(struct be_adapter *adapter, u16 pvid,
a77dcb8c 3213 u32 domain, u16 intf_id, u16 hsw_mode)
f1f3ee1b
AK		 3214{
3215 struct be_mcc_wrb *wrb;
3216 struct be_cmd_req_set_hsw_config *req;
3217 void *ctxt;
3218 int status;
3219
3220 spin_lock_bh(&adapter->mcc_lock);
3221
3222 wrb = wrb_from_mccq(adapter);
3223 if (!wrb) {
3224 status = -EBUSY;
3225 goto err;
3226 }
3227
3228 req = embedded_payload(wrb);
3229 ctxt = &req->context;
3230
3231 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 3232 OPCODE_COMMON_SET_HSW_CONFIG, sizeof(*req), wrb,
3233 NULL);
f1f3ee1b
AK		 3234
3235 req->hdr.domain = domain;
3236 AMAP_SET_BITS(struct amap_set_hsw_context, interface_id, ctxt, intf_id);
3237 if (pvid) {
3238 AMAP_SET_BITS(struct amap_set_hsw_context, pvid_valid, ctxt, 1);
3239 AMAP_SET_BITS(struct amap_set_hsw_context, pvid, ctxt, pvid);
3240 }
a77dcb8c
AK		 3241 if (!BEx_chip(adapter) && hsw_mode) {
3242 AMAP_SET_BITS(struct amap_set_hsw_context, interface_id,
3243 ctxt, adapter->hba_port_num);
3244 AMAP_SET_BITS(struct amap_set_hsw_context, pport, ctxt, 1);
3245 AMAP_SET_BITS(struct amap_set_hsw_context, port_fwd_type,
3246 ctxt, hsw_mode);
3247 }
f1f3ee1b
AK		 3248
3249 be_dws_cpu_to_le(req->context, sizeof(req->context));
3250 status = be_mcc_notify_wait(adapter);
3251
3252err:
3253 spin_unlock_bh(&adapter->mcc_lock);
3254 return status;
3255}
3256
3257/* Get Hyper switch config */
3258int be_cmd_get_hsw_config(struct be_adapter *adapter, u16 *pvid,
a77dcb8c 3259 u32 domain, u16 intf_id, u8 *mode)
f1f3ee1b
AK		 3260{
3261 struct be_mcc_wrb *wrb;
3262 struct be_cmd_req_get_hsw_config *req;
3263 void *ctxt;
3264 int status;
3265 u16 vid;
3266
3267 spin_lock_bh(&adapter->mcc_lock);
3268
3269 wrb = wrb_from_mccq(adapter);
3270 if (!wrb) {
3271 status = -EBUSY;
3272 goto err;
3273 }
3274
3275 req = embedded_payload(wrb);
3276 ctxt = &req->context;
3277
3278 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 3279 OPCODE_COMMON_GET_HSW_CONFIG, sizeof(*req), wrb,
3280 NULL);
f1f3ee1b
AK		 3281
3282 req->hdr.domain = domain;
a77dcb8c
AK		 3283 AMAP_SET_BITS(struct amap_get_hsw_req_context, interface_id,
3284 ctxt, intf_id);
f1f3ee1b 3285 AMAP_SET_BITS(struct amap_get_hsw_req_context, pvid_valid, ctxt, 1);
a77dcb8c 3286
2c07c1d7 3287 if (!BEx_chip(adapter) && mode) {
a77dcb8c
AK		 3288 AMAP_SET_BITS(struct amap_get_hsw_req_context, interface_id,
3289 ctxt, adapter->hba_port_num);
3290 AMAP_SET_BITS(struct amap_get_hsw_req_context, pport, ctxt, 1);
3291 }
f1f3ee1b
AK		 3292 be_dws_cpu_to_le(req->context, sizeof(req->context));
3293
3294 status = be_mcc_notify_wait(adapter);
3295 if (!status) {
3296 struct be_cmd_resp_get_hsw_config *resp =
3297 embedded_payload(wrb);
03d28ffe 3298
a2cc4e0b 3299 be_dws_le_to_cpu(&resp->context, sizeof(resp->context));
f1f3ee1b 3300 vid = AMAP_GET_BITS(struct amap_get_hsw_resp_context,
a2cc4e0b 3301 pvid, &resp->context);
a77dcb8c
AK		 3302 if (pvid)
3303 *pvid = le16_to_cpu(vid);
3304 if (mode)
3305 *mode = AMAP_GET_BITS(struct amap_get_hsw_resp_context,
3306 port_fwd_type, &resp->context);
f1f3ee1b
AK		 3307 }
3308
3309err:
3310 spin_unlock_bh(&adapter->mcc_lock);
3311 return status;
3312}
3313
f7062ee5
SP		 3314static bool be_is_wol_excluded(struct be_adapter *adapter)
3315{
3316 struct pci_dev *pdev = adapter->pdev;
3317
3318 if (!be_physfn(adapter))
3319 return true;
3320
3321 switch (pdev->subsystem_device) {
3322 case OC_SUBSYS_DEVICE_ID1:
3323 case OC_SUBSYS_DEVICE_ID2:
3324 case OC_SUBSYS_DEVICE_ID3:
3325 case OC_SUBSYS_DEVICE_ID4:
3326 return true;
3327 default:
3328 return false;
3329 }
3330}
3331
4762f6ce
AK		 3332int be_cmd_get_acpi_wol_cap(struct be_adapter *adapter)
3333{
3334 struct be_mcc_wrb *wrb;
3335 struct be_cmd_req_acpi_wol_magic_config_v1 *req;
76a9e08e 3336 int status = 0;
4762f6ce
AK		 3337 struct be_dma_mem cmd;
3338
f25b119c
PR		 3339 if (!be_cmd_allowed(adapter, OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG,
3340 CMD_SUBSYSTEM_ETH))
3341 return -EPERM;
3342
76a9e08e
SR		 3343 if (be_is_wol_excluded(adapter))
3344 return status;
3345
d98ef50f
SR		 3346 if (mutex_lock_interruptible(&adapter->mbox_lock))
3347 return -1;
3348
4762f6ce
AK		 3349 memset(&cmd, 0, sizeof(struct be_dma_mem));
3350 cmd.size = sizeof(struct be_cmd_resp_acpi_wol_magic_config_v1);
a2cc4e0b 3351 cmd.va = pci_alloc_consistent(adapter->pdev, cmd.size, &cmd.dma);
4762f6ce 3352 if (!cmd.va) {
a2cc4e0b 3353 dev_err(&adapter->pdev->dev, "Memory allocation failure\n");
d98ef50f
SR		 3354 status = -ENOMEM;
3355 goto err;
4762f6ce
AK		 3356 }
3357
4762f6ce
AK		 3358 wrb = wrb_from_mbox(adapter);
3359 if (!wrb) {
3360 status = -EBUSY;
3361 goto err;
3362 }
3363
3364 req = cmd.va;
3365
3366 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
3367 OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG,
76a9e08e 3368 sizeof(*req), wrb, &cmd);
4762f6ce
AK		 3369
3370 req->hdr.version = 1;
3371 req->query_options = BE_GET_WOL_CAP;
3372
3373 status = be_mbox_notify_wait(adapter);
3374 if (!status) {
3375 struct be_cmd_resp_acpi_wol_magic_config_v1 *resp;
03d28ffe 3376
504fbf1e 3377 resp = (struct be_cmd_resp_acpi_wol_magic_config_v1 *)cmd.va;
4762f6ce 3378
4762f6ce 3379 adapter->wol_cap = resp->wol_settings;
76a9e08e
SR		 3380 if (adapter->wol_cap & BE_WOL_CAP)
3381 adapter->wol_en = true;
4762f6ce
AK		 3382 }
3383err:
3384 mutex_unlock(&adapter->mbox_lock);
d98ef50f
SR		 3385 if (cmd.va)
3386 pci_free_consistent(adapter->pdev, cmd.size, cmd.va, cmd.dma);
4762f6ce 3387 return status;
941a77d5
SK		 3388
3389}
baaa08d1
VV		 3390
3391int be_cmd_set_fw_log_level(struct be_adapter *adapter, u32 level)
3392{
3393 struct be_dma_mem extfat_cmd;
3394 struct be_fat_conf_params *cfgs;
3395 int status;
3396 int i, j;
3397
3398 memset(&extfat_cmd, 0, sizeof(struct be_dma_mem));
3399 extfat_cmd.size = sizeof(struct be_cmd_resp_get_ext_fat_caps);
3400 extfat_cmd.va = pci_alloc_consistent(adapter->pdev, extfat_cmd.size,
3401 &extfat_cmd.dma);
3402 if (!extfat_cmd.va)
3403 return -ENOMEM;
3404
3405 status = be_cmd_get_ext_fat_capabilites(adapter, &extfat_cmd);
3406 if (status)
3407 goto err;
3408
3409 cfgs = (struct be_fat_conf_params *)
3410 (extfat_cmd.va + sizeof(struct be_cmd_resp_hdr));
3411 for (i = 0; i < le32_to_cpu(cfgs->num_modules); i++) {
3412 u32 num_modes = le32_to_cpu(cfgs->module[i].num_modes);
03d28ffe 3413
baaa08d1
VV		 3414 for (j = 0; j < num_modes; j++) {
3415 if (cfgs->module[i].trace_lvl[j].mode == MODE_UART)
3416 cfgs->module[i].trace_lvl[j].dbg_lvl =
3417 cpu_to_le32(level);
3418 }
3419 }
3420
3421 status = be_cmd_set_ext_fat_capabilites(adapter, &extfat_cmd, cfgs);
3422err:
3423 pci_free_consistent(adapter->pdev, extfat_cmd.size, extfat_cmd.va,
3424 extfat_cmd.dma);
3425 return status;
3426}
3427
3428int be_cmd_get_fw_log_level(struct be_adapter *adapter)
3429{
3430 struct be_dma_mem extfat_cmd;
3431 struct be_fat_conf_params *cfgs;
3432 int status, j;
3433 int level = 0;
3434
3435 memset(&extfat_cmd, 0, sizeof(struct be_dma_mem));
3436 extfat_cmd.size = sizeof(struct be_cmd_resp_get_ext_fat_caps);
3437 extfat_cmd.va = pci_alloc_consistent(adapter->pdev, extfat_cmd.size,
3438 &extfat_cmd.dma);
3439
3440 if (!extfat_cmd.va) {
3441 dev_err(&adapter->pdev->dev, "%s: Memory allocation failure\n",
3442 __func__);
3443 goto err;
3444 }
3445
3446 status = be_cmd_get_ext_fat_capabilites(adapter, &extfat_cmd);
3447 if (!status) {
3448 cfgs = (struct be_fat_conf_params *)(extfat_cmd.va +
3449 sizeof(struct be_cmd_resp_hdr));
03d28ffe 3450
baaa08d1
VV		 3451 for (j = 0; j < le32_to_cpu(cfgs->module[0].num_modes); j++) {
3452 if (cfgs->module[0].trace_lvl[j].mode == MODE_UART)
3453 level = cfgs->module[0].trace_lvl[j].dbg_lvl;
3454 }
3455 }
3456 pci_free_consistent(adapter->pdev, extfat_cmd.size, extfat_cmd.va,
3457 extfat_cmd.dma);
3458err:
3459 return level;
3460}
3461
941a77d5
SK		 3462int be_cmd_get_ext_fat_capabilites(struct be_adapter *adapter,
3463 struct be_dma_mem *cmd)
3464{
3465 struct be_mcc_wrb *wrb;
3466 struct be_cmd_req_get_ext_fat_caps *req;
3467 int status;
3468
3469 if (mutex_lock_interruptible(&adapter->mbox_lock))
3470 return -1;
3471
3472 wrb = wrb_from_mbox(adapter);
3473 if (!wrb) {
3474 status = -EBUSY;
3475 goto err;
3476 }
3477
3478 req = cmd->va;
3479 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3480 OPCODE_COMMON_GET_EXT_FAT_CAPABILITES,
3481 cmd->size, wrb, cmd);
3482 req->parameter_type = cpu_to_le32(1);
3483
3484 status = be_mbox_notify_wait(adapter);
3485err:
3486 mutex_unlock(&adapter->mbox_lock);
3487 return status;
3488}
3489
3490int be_cmd_set_ext_fat_capabilites(struct be_adapter *adapter,
3491 struct be_dma_mem *cmd,
3492 struct be_fat_conf_params *configs)
3493{
3494 struct be_mcc_wrb *wrb;
3495 struct be_cmd_req_set_ext_fat_caps *req;
3496 int status;
3497
3498 spin_lock_bh(&adapter->mcc_lock);
3499
3500 wrb = wrb_from_mccq(adapter);
3501 if (!wrb) {
3502 status = -EBUSY;
3503 goto err;
3504 }
3505
3506 req = cmd->va;
3507 memcpy(&req->set_params, configs, sizeof(struct be_fat_conf_params));
3508 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3509 OPCODE_COMMON_SET_EXT_FAT_CAPABILITES,
3510 cmd->size, wrb, cmd);
3511
3512 status = be_mcc_notify_wait(adapter);
3513err:
3514 spin_unlock_bh(&adapter->mcc_lock);
3515 return status;
4762f6ce 3516}
6a4ab669 3517
21252377 3518int be_cmd_query_port_name(struct be_adapter *adapter)
b4e32a71 3519{
b4e32a71 3520 struct be_cmd_req_get_port_name *req;
21252377 3521 struct be_mcc_wrb *wrb;
b4e32a71
PR		 3522 int status;
3523
21252377
VV		 3524 if (mutex_lock_interruptible(&adapter->mbox_lock))
3525 return -1;
b4e32a71 3526
21252377 3527 wrb = wrb_from_mbox(adapter);
b4e32a71
PR		 3528 req = embedded_payload(wrb);
3529
3530 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3531 OPCODE_COMMON_GET_PORT_NAME, sizeof(*req), wrb,
3532 NULL);
21252377
VV		 3533 if (!BEx_chip(adapter))
3534 req->hdr.version = 1;
b4e32a71 3535
21252377 3536 status = be_mbox_notify_wait(adapter);
b4e32a71
PR		 3537 if (!status) {
3538 struct be_cmd_resp_get_port_name *resp = embedded_payload(wrb);
03d28ffe 3539
21252377 3540 adapter->port_name = resp->port_name[adapter->hba_port_num];
b4e32a71 3541 } else {
21252377 3542 adapter->port_name = adapter->hba_port_num + '0';
b4e32a71 3543 }
21252377
VV		 3544
3545 mutex_unlock(&adapter->mbox_lock);
b4e32a71
PR		 3546 return status;
3547}
3548
10cccf60
VV		 3549/* Descriptor type */
3550enum {
3551 FUNC_DESC = 1,
3552 VFT_DESC = 2
3553};
3554
3555static struct be_nic_res_desc *be_get_nic_desc(u8 *buf, u32 desc_count,
3556 int desc_type)
abb93951 3557{
150d58c7 3558 struct be_res_desc_hdr *hdr = (struct be_res_desc_hdr *)buf;
10cccf60 3559 struct be_nic_res_desc *nic;
abb93951
PR		 3560 int i;
3561
3562 for (i = 0; i < desc_count; i++) {
150d58c7 3563 if (hdr->desc_type == NIC_RESOURCE_DESC_TYPE_V0 ||
10cccf60
VV		 3564 hdr->desc_type == NIC_RESOURCE_DESC_TYPE_V1) {
3565 nic = (struct be_nic_res_desc *)hdr;
3566 if (desc_type == FUNC_DESC ||
3567 (desc_type == VFT_DESC &&
3568 nic->flags & (1 << VFT_SHIFT)))
3569 return nic;
3570 }
abb93951 3571
150d58c7
VV		 3572 hdr->desc_len = hdr->desc_len ? : RESOURCE_DESC_SIZE_V0;
3573 hdr = (void *)hdr + hdr->desc_len;
abb93951 3574 }
150d58c7
VV		 3575 return NULL;
3576}
3577
10cccf60
VV		 3578static struct be_nic_res_desc *be_get_vft_desc(u8 *buf, u32 desc_count)
3579{
3580 return be_get_nic_desc(buf, desc_count, VFT_DESC);
3581}
3582
3583static struct be_nic_res_desc *be_get_func_nic_desc(u8 *buf, u32 desc_count)
3584{
3585 return be_get_nic_desc(buf, desc_count, FUNC_DESC);
3586}
3587
150d58c7
VV		 3588static struct be_pcie_res_desc *be_get_pcie_desc(u8 devfn, u8 *buf,
3589 u32 desc_count)
3590{
3591 struct be_res_desc_hdr *hdr = (struct be_res_desc_hdr *)buf;
3592 struct be_pcie_res_desc *pcie;
3593 int i;
3594
3595 for (i = 0; i < desc_count; i++) {
3596 if ((hdr->desc_type == PCIE_RESOURCE_DESC_TYPE_V0 ||
3597 hdr->desc_type == PCIE_RESOURCE_DESC_TYPE_V1)) {
3598 pcie = (struct be_pcie_res_desc *)hdr;
3599 if (pcie->pf_num == devfn)
3600 return pcie;
3601 }
abb93951 3602
150d58c7
VV		 3603 hdr->desc_len = hdr->desc_len ? : RESOURCE_DESC_SIZE_V0;
3604 hdr = (void *)hdr + hdr->desc_len;
3605 }
950e2958 3606 return NULL;
abb93951
PR		 3607}
3608
f93f160b
VV		 3609static struct be_port_res_desc *be_get_port_desc(u8 *buf, u32 desc_count)
3610{
3611 struct be_res_desc_hdr *hdr = (struct be_res_desc_hdr *)buf;
3612 int i;
3613
3614 for (i = 0; i < desc_count; i++) {
3615 if (hdr->desc_type == PORT_RESOURCE_DESC_TYPE_V1)
3616 return (struct be_port_res_desc *)hdr;
3617
3618 hdr->desc_len = hdr->desc_len ? : RESOURCE_DESC_SIZE_V0;
3619 hdr = (void *)hdr + hdr->desc_len;
3620 }
3621 return NULL;
3622}
3623
92bf14ab
SP		 3624static void be_copy_nic_desc(struct be_resources *res,
3625 struct be_nic_res_desc *desc)
3626{
3627 res->max_uc_mac = le16_to_cpu(desc->unicast_mac_count);
3628 res->max_vlans = le16_to_cpu(desc->vlan_count);
3629 res->max_mcast_mac = le16_to_cpu(desc->mcast_mac_count);
3630 res->max_tx_qs = le16_to_cpu(desc->txq_count);
3631 res->max_rss_qs = le16_to_cpu(desc->rssq_count);
3632 res->max_rx_qs = le16_to_cpu(desc->rq_count);
3633 res->max_evt_qs = le16_to_cpu(desc->eq_count);
3634 /* Clear flags that driver is not interested in */
3635 res->if_cap_flags = le32_to_cpu(desc->cap_flags) &
3636 BE_IF_CAP_FLAGS_WANT;
3637 /* Need 1 RXQ as the default RXQ */
3638 if (res->max_rss_qs && res->max_rss_qs == res->max_rx_qs)
3639 res->max_rss_qs -= 1;
3640}
3641
abb93951 3642/* Uses Mbox */
92bf14ab 3643int be_cmd_get_func_config(struct be_adapter *adapter, struct be_resources *res)
abb93951
PR		 3644{
3645 struct be_mcc_wrb *wrb;
3646 struct be_cmd_req_get_func_config *req;
3647 int status;
3648 struct be_dma_mem cmd;
3649
d98ef50f
SR		 3650 if (mutex_lock_interruptible(&adapter->mbox_lock))
3651 return -1;
3652
abb93951
PR		 3653 memset(&cmd, 0, sizeof(struct be_dma_mem));
3654 cmd.size = sizeof(struct be_cmd_resp_get_func_config);
a2cc4e0b 3655 cmd.va = pci_alloc_consistent(adapter->pdev, cmd.size, &cmd.dma);
abb93951
PR		 3656 if (!cmd.va) {
3657 dev_err(&adapter->pdev->dev, "Memory alloc failure\n");
d98ef50f
SR		 3658 status = -ENOMEM;
3659 goto err;
abb93951 3660 }
abb93951
PR		 3661
3662 wrb = wrb_from_mbox(adapter);
3663 if (!wrb) {
3664 status = -EBUSY;
3665 goto err;
3666 }
3667
3668 req = cmd.va;
3669
3670 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3671 OPCODE_COMMON_GET_FUNC_CONFIG,
3672 cmd.size, wrb, &cmd);
3673
28710c55
KA		 3674 if (skyhawk_chip(adapter))
3675 req->hdr.version = 1;
3676
abb93951
PR		 3677 status = be_mbox_notify_wait(adapter);
3678 if (!status) {
3679 struct be_cmd_resp_get_func_config *resp = cmd.va;
3680 u32 desc_count = le32_to_cpu(resp->desc_count);
150d58c7 3681 struct be_nic_res_desc *desc;
abb93951 3682
10cccf60 3683 desc = be_get_func_nic_desc(resp->func_param, desc_count);
abb93951
PR		 3684 if (!desc) {
3685 status = -EINVAL;
3686 goto err;
3687 }
3688
d5c18473 3689 adapter->pf_number = desc->pf_num;
92bf14ab 3690 be_copy_nic_desc(res, desc);
abb93951
PR		 3691 }
3692err:
3693 mutex_unlock(&adapter->mbox_lock);
d98ef50f
SR		 3694 if (cmd.va)
3695 pci_free_consistent(adapter->pdev, cmd.size, cmd.va, cmd.dma);
abb93951
PR		 3696 return status;
3697}
3698
ba48c0c9 3699/* Will use MBOX only if MCCQ has not been created */
92bf14ab
SP		 3700int be_cmd_get_profile_config(struct be_adapter *adapter,
3701 struct be_resources *res, u8 domain)
a05f99db 3702{
150d58c7 3703 struct be_cmd_resp_get_profile_config *resp;
ba48c0c9 3704 struct be_cmd_req_get_profile_config *req;
10cccf60 3705 struct be_nic_res_desc *vf_res;
150d58c7 3706 struct be_pcie_res_desc *pcie;
f93f160b 3707 struct be_port_res_desc *port;
150d58c7 3708 struct be_nic_res_desc *nic;
ba48c0c9 3709 struct be_mcc_wrb wrb = {0};
a05f99db 3710 struct be_dma_mem cmd;
150d58c7 3711 u32 desc_count;
a05f99db
VV		 3712 int status;
3713
3714 memset(&cmd, 0, sizeof(struct be_dma_mem));
150d58c7
VV		 3715 cmd.size = sizeof(struct be_cmd_resp_get_profile_config);
3716 cmd.va = pci_alloc_consistent(adapter->pdev, cmd.size, &cmd.dma);
3717 if (!cmd.va)
a05f99db 3718 return -ENOMEM;
a05f99db 3719
ba48c0c9
VV		 3720 req = cmd.va;
3721 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3722 OPCODE_COMMON_GET_PROFILE_CONFIG,
3723 cmd.size, &wrb, &cmd);
3724
3725 req->hdr.domain = domain;
3726 if (!lancer_chip(adapter))
3727 req->hdr.version = 1;
3728 req->type = ACTIVE_PROFILE_TYPE;
3729
3730 status = be_cmd_notify_wait(adapter, &wrb);
150d58c7
VV		 3731 if (status)
3732 goto err;
abb93951 3733
150d58c7
VV		 3734 resp = cmd.va;
3735 desc_count = le32_to_cpu(resp->desc_count);
abb93951 3736
a2cc4e0b
SP		 3737 pcie = be_get_pcie_desc(adapter->pdev->devfn, resp->func_param,
3738 desc_count);
150d58c7 3739 if (pcie)
92bf14ab 3740 res->max_vfs = le16_to_cpu(pcie->num_vfs);
150d58c7 3741
f93f160b
VV		 3742 port = be_get_port_desc(resp->func_param, desc_count);
3743 if (port)
3744 adapter->mc_type = port->mc_type;
3745
10cccf60 3746 nic = be_get_func_nic_desc(resp->func_param, desc_count);
92bf14ab
SP		 3747 if (nic)
3748 be_copy_nic_desc(res, nic);
3749
10cccf60
VV		 3750 vf_res = be_get_vft_desc(resp->func_param, desc_count);
3751 if (vf_res)
3752 res->vf_if_cap_flags = vf_res->cap_flags;
abb93951 3753err:
a05f99db 3754 if (cmd.va)
150d58c7 3755 pci_free_consistent(adapter->pdev, cmd.size, cmd.va, cmd.dma);
abb93951
PR		 3756 return status;
3757}
3758
bec84e6b
VV		 3759/* Will use MBOX only if MCCQ has not been created */
3760static int be_cmd_set_profile_config(struct be_adapter *adapter, void *desc,
3761 int size, int count, u8 version, u8 domain)
d5c18473 3762{
d5c18473 3763 struct be_cmd_req_set_profile_config *req;
bec84e6b
VV		 3764 struct be_mcc_wrb wrb = {0};
3765 struct be_dma_mem cmd;
d5c18473
PR		 3766 int status;
3767
bec84e6b
VV		 3768 memset(&cmd, 0, sizeof(struct be_dma_mem));
3769 cmd.size = sizeof(struct be_cmd_req_set_profile_config);
3770 cmd.va = pci_alloc_consistent(adapter->pdev, cmd.size, &cmd.dma);
3771 if (!cmd.va)
3772 return -ENOMEM;
d5c18473 3773
bec84e6b 3774 req = cmd.va;
d5c18473 3775 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
bec84e6b
VV		 3776 OPCODE_COMMON_SET_PROFILE_CONFIG, cmd.size,
3777 &wrb, &cmd);
a401801c 3778 req->hdr.version = version;
d5c18473 3779 req->hdr.domain = domain;
bec84e6b 3780 req->desc_count = cpu_to_le32(count);
a401801c
SP		 3781 memcpy(req->desc, desc, size);
3782
bec84e6b
VV		 3783 status = be_cmd_notify_wait(adapter, &wrb);
3784
3785 if (cmd.va)
3786 pci_free_consistent(adapter->pdev, cmd.size, cmd.va, cmd.dma);
d5c18473
PR		 3787 return status;
3788}
3789
a401801c 3790/* Mark all fields invalid */
bec84e6b 3791static void be_reset_nic_desc(struct be_nic_res_desc *nic)
a401801c
SP		 3792{
3793 memset(nic, 0, sizeof(*nic));
3794 nic->unicast_mac_count = 0xFFFF;
3795 nic->mcc_count = 0xFFFF;
3796 nic->vlan_count = 0xFFFF;
3797 nic->mcast_mac_count = 0xFFFF;
3798 nic->txq_count = 0xFFFF;
3799 nic->rq_count = 0xFFFF;
3800 nic->rssq_count = 0xFFFF;
3801 nic->lro_count = 0xFFFF;
3802 nic->cq_count = 0xFFFF;
3803 nic->toe_conn_count = 0xFFFF;
3804 nic->eq_count = 0xFFFF;
0f77ba73 3805 nic->iface_count = 0xFFFF;
a401801c 3806 nic->link_param = 0xFF;
0f77ba73 3807 nic->channel_id_param = cpu_to_le16(0xF000);
a401801c
SP		 3808 nic->acpi_params = 0xFF;
3809 nic->wol_param = 0x0F;
0f77ba73
RN		 3810 nic->tunnel_iface_count = 0xFFFF;
3811 nic->direct_tenant_iface_count = 0xFFFF;
bec84e6b 3812 nic->bw_min = 0xFFFFFFFF;
a401801c
SP		 3813 nic->bw_max = 0xFFFFFFFF;
3814}
3815
bec84e6b
VV		 3816/* Mark all fields invalid */
3817static void be_reset_pcie_desc(struct be_pcie_res_desc *pcie)
3818{
3819 memset(pcie, 0, sizeof(*pcie));
3820 pcie->sriov_state = 0xFF;
3821 pcie->pf_state = 0xFF;
3822 pcie->pf_type = 0xFF;
3823 pcie->num_vfs = 0xFFFF;
3824}
3825
0f77ba73
RN		 3826int be_cmd_config_qos(struct be_adapter *adapter, u32 max_rate, u16 link_speed,
3827 u8 domain)
a401801c 3828{
0f77ba73
RN		 3829 struct be_nic_res_desc nic_desc;
3830 u32 bw_percent;
3831 u16 version = 0;
3832
3833 if (BE3_chip(adapter))
3834 return be_cmd_set_qos(adapter, max_rate / 10, domain);
a401801c 3835
0f77ba73
RN		 3836 be_reset_nic_desc(&nic_desc);
3837 nic_desc.pf_num = adapter->pf_number;
3838 nic_desc.vf_num = domain;
58bdeaa6 3839 nic_desc.bw_min = 0;
0f77ba73 3840 if (lancer_chip(adapter)) {
a401801c
SP		 3841 nic_desc.hdr.desc_type = NIC_RESOURCE_DESC_TYPE_V0;
3842 nic_desc.hdr.desc_len = RESOURCE_DESC_SIZE_V0;
3843 nic_desc.flags = (1 << QUN_SHIFT) | (1 << IMM_SHIFT) |
3844 (1 << NOSV_SHIFT);
0f77ba73 3845 nic_desc.bw_max = cpu_to_le32(max_rate / 10);
a401801c 3846 } else {
0f77ba73
RN		 3847 version = 1;
3848 nic_desc.hdr.desc_type = NIC_RESOURCE_DESC_TYPE_V1;
3849 nic_desc.hdr.desc_len = RESOURCE_DESC_SIZE_V1;
3850 nic_desc.flags = (1 << IMM_SHIFT) | (1 << NOSV_SHIFT);
3851 bw_percent = max_rate ? (max_rate * 100) / link_speed : 100;
3852 nic_desc.bw_max = cpu_to_le32(bw_percent);
a401801c 3853 }
0f77ba73
RN		 3854
3855 return be_cmd_set_profile_config(adapter, &nic_desc,
3856 nic_desc.hdr.desc_len,
bec84e6b
VV		 3857 1, version, domain);
3858}
3859
3860int be_cmd_set_sriov_config(struct be_adapter *adapter,
3861 struct be_resources res, u16 num_vfs)
3862{
3863 struct {
3864 struct be_pcie_res_desc pcie;
3865 struct be_nic_res_desc nic_vft;
3866 } __packed desc;
3867 u16 vf_q_count;
3868
3869 if (BEx_chip(adapter) || lancer_chip(adapter))
3870 return 0;
3871
3872 /* PF PCIE descriptor */
3873 be_reset_pcie_desc(&desc.pcie);
3874 desc.pcie.hdr.desc_type = PCIE_RESOURCE_DESC_TYPE_V1;
3875 desc.pcie.hdr.desc_len = RESOURCE_DESC_SIZE_V1;
3876 desc.pcie.flags = (1 << IMM_SHIFT) | (1 << NOSV_SHIFT);
3877 desc.pcie.pf_num = adapter->pdev->devfn;
3878 desc.pcie.sriov_state = num_vfs ? 1 : 0;
3879 desc.pcie.num_vfs = cpu_to_le16(num_vfs);
3880
3881 /* VF NIC Template descriptor */
3882 be_reset_nic_desc(&desc.nic_vft);
3883 desc.nic_vft.hdr.desc_type = NIC_RESOURCE_DESC_TYPE_V1;
3884 desc.nic_vft.hdr.desc_len = RESOURCE_DESC_SIZE_V1;
3885 desc.nic_vft.flags = (1 << VFT_SHIFT) | (1 << IMM_SHIFT) |
3886 (1 << NOSV_SHIFT);
3887 desc.nic_vft.pf_num = adapter->pdev->devfn;
3888 desc.nic_vft.vf_num = 0;
3889
3890 if (num_vfs && res.vf_if_cap_flags & BE_IF_FLAGS_RSS) {
3891 /* If number of VFs requested is 8 less than max supported,
3892 * assign 8 queue pairs to the PF and divide the remaining
3893 * resources evenly among the VFs
3894 */
3895 if (num_vfs < (be_max_vfs(adapter) - 8))
3896 vf_q_count = (res.max_rss_qs - 8) / num_vfs;
3897 else
3898 vf_q_count = res.max_rss_qs / num_vfs;
3899
3900 desc.nic_vft.rq_count = cpu_to_le16(vf_q_count);
3901 desc.nic_vft.txq_count = cpu_to_le16(vf_q_count);
3902 desc.nic_vft.rssq_count = cpu_to_le16(vf_q_count - 1);
3903 desc.nic_vft.cq_count = cpu_to_le16(3 * vf_q_count);
3904 } else {
3905 desc.nic_vft.txq_count = cpu_to_le16(1);
3906 desc.nic_vft.rq_count = cpu_to_le16(1);
3907 desc.nic_vft.rssq_count = cpu_to_le16(0);
3908 /* One CQ for each TX, RX and MCCQ */
3909 desc.nic_vft.cq_count = cpu_to_le16(3);
3910 }
3911
3912 return be_cmd_set_profile_config(adapter, &desc,
3913 2 * RESOURCE_DESC_SIZE_V1, 2, 1, 0);
a401801c
SP		 3914}
3915
3916int be_cmd_manage_iface(struct be_adapter *adapter, u32 iface, u8 op)
3917{
3918 struct be_mcc_wrb *wrb;
3919 struct be_cmd_req_manage_iface_filters *req;
3920 int status;
3921
3922 if (iface == 0xFFFFFFFF)
3923 return -1;
3924
3925 spin_lock_bh(&adapter->mcc_lock);
3926
3927 wrb = wrb_from_mccq(adapter);
3928 if (!wrb) {
3929 status = -EBUSY;
3930 goto err;
3931 }
3932 req = embedded_payload(wrb);
3933
3934 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3935 OPCODE_COMMON_MANAGE_IFACE_FILTERS, sizeof(*req),
3936 wrb, NULL);
3937 req->op = op;
3938 req->target_iface_id = cpu_to_le32(iface);
3939
3940 status = be_mcc_notify_wait(adapter);
3941err:
3942 spin_unlock_bh(&adapter->mcc_lock);
3943 return status;
3944}
3945
3946int be_cmd_set_vxlan_port(struct be_adapter *adapter, __be16 port)
3947{
3948 struct be_port_res_desc port_desc;
3949
3950 memset(&port_desc, 0, sizeof(port_desc));
3951 port_desc.hdr.desc_type = PORT_RESOURCE_DESC_TYPE_V1;
3952 port_desc.hdr.desc_len = RESOURCE_DESC_SIZE_V1;
3953 port_desc.flags = (1 << IMM_SHIFT) | (1 << NOSV_SHIFT);
3954 port_desc.link_num = adapter->hba_port_num;
3955 if (port) {
3956 port_desc.nv_flags = NV_TYPE_VXLAN | (1 << SOCVID_SHIFT) |
3957 (1 << RCVID_SHIFT);
3958 port_desc.nv_port = swab16(port);
3959 } else {
3960 port_desc.nv_flags = NV_TYPE_DISABLED;
3961 port_desc.nv_port = 0;
3962 }
3963
3964 return be_cmd_set_profile_config(adapter, &port_desc,
bec84e6b 3965 RESOURCE_DESC_SIZE_V1, 1, 1, 0);
a401801c
SP		 3966}
3967
4c876616
SP		 3968int be_cmd_get_if_id(struct be_adapter *adapter, struct be_vf_cfg *vf_cfg,
3969 int vf_num)
3970{
3971 struct be_mcc_wrb *wrb;
3972 struct be_cmd_req_get_iface_list *req;
3973 struct be_cmd_resp_get_iface_list *resp;
3974 int status;
3975
3976 spin_lock_bh(&adapter->mcc_lock);
3977
3978 wrb = wrb_from_mccq(adapter);
3979 if (!wrb) {
3980 status = -EBUSY;
3981 goto err;
3982 }
3983 req = embedded_payload(wrb);
3984
3985 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3986 OPCODE_COMMON_GET_IFACE_LIST, sizeof(*resp),
3987 wrb, NULL);
3988 req->hdr.domain = vf_num + 1;
3989
3990 status = be_mcc_notify_wait(adapter);
3991 if (!status) {
3992 resp = (struct be_cmd_resp_get_iface_list *)req;
3993 vf_cfg->if_handle = le32_to_cpu(resp->if_desc.if_id);
3994 }
3995
3996err:
3997 spin_unlock_bh(&adapter->mcc_lock);
3998 return status;
3999}
4000
5c510811
SK		 4001static int lancer_wait_idle(struct be_adapter *adapter)
4002{
4003#define SLIPORT_IDLE_TIMEOUT 30
4004 u32 reg_val;
4005 int status = 0, i;
4006
4007 for (i = 0; i < SLIPORT_IDLE_TIMEOUT; i++) {
4008 reg_val = ioread32(adapter->db + PHYSDEV_CONTROL_OFFSET);
4009 if ((reg_val & PHYSDEV_CONTROL_INP_MASK) == 0)
4010 break;
4011
4012 ssleep(1);
4013 }
4014
4015 if (i == SLIPORT_IDLE_TIMEOUT)
4016 status = -1;
4017
4018 return status;
4019}
4020
4021int lancer_physdev_ctrl(struct be_adapter *adapter, u32 mask)
4022{
4023 int status = 0;
4024
4025 status = lancer_wait_idle(adapter);
4026 if (status)
4027 return status;
4028
4029 iowrite32(mask, adapter->db + PHYSDEV_CONTROL_OFFSET);
4030
4031 return status;
4032}
4033
4034/* Routine to check whether dump image is present or not */
4035bool dump_present(struct be_adapter *adapter)
4036{
4037 u32 sliport_status = 0;
4038
4039 sliport_status = ioread32(adapter->db + SLIPORT_STATUS_OFFSET);
4040 return !!(sliport_status & SLIPORT_STATUS_DIP_MASK);
4041}
4042
4043int lancer_initiate_dump(struct be_adapter *adapter)
4044{
f0613380 4045 struct device *dev = &adapter->pdev->dev;
5c510811
SK		 4046 int status;
4047
f0613380
KA		 4048 if (dump_present(adapter)) {
4049 dev_info(dev, "Previous dump not cleared, not forcing dump\n");
4050 return -EEXIST;
4051 }
4052
5c510811
SK		 4053 /* give firmware reset and diagnostic dump */
4054 status = lancer_physdev_ctrl(adapter, PHYSDEV_CONTROL_FW_RESET_MASK |
4055 PHYSDEV_CONTROL_DD_MASK);
4056 if (status < 0) {
f0613380 4057 dev_err(dev, "FW reset failed\n");
5c510811
SK		 4058 return status;
4059 }
4060
4061 status = lancer_wait_idle(adapter);
4062 if (status)
4063 return status;
4064
4065 if (!dump_present(adapter)) {
f0613380
KA		 4066 dev_err(dev, "FW dump not generated\n");
4067 return -EIO;
5c510811
SK		 4068 }
4069
4070 return 0;
4071}
4072
f0613380
KA		 4073int lancer_delete_dump(struct be_adapter *adapter)
4074{
4075 int status;
4076
4077 status = lancer_cmd_delete_object(adapter, LANCER_FW_DUMP_FILE);
4078 return be_cmd_status(status);
4079}
4080
dcf7ebba
PR		 4081/* Uses sync mcc */
4082int be_cmd_enable_vf(struct be_adapter *adapter, u8 domain)
4083{
4084 struct be_mcc_wrb *wrb;
4085 struct be_cmd_enable_disable_vf *req;
4086 int status;
4087
0599863d 4088 if (BEx_chip(adapter))
dcf7ebba
PR		 4089 return 0;
4090
4091 spin_lock_bh(&adapter->mcc_lock);
4092
4093 wrb = wrb_from_mccq(adapter);
4094 if (!wrb) {
4095 status = -EBUSY;
4096 goto err;
4097 }
4098
4099 req = embedded_payload(wrb);
4100
4101 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
4102 OPCODE_COMMON_ENABLE_DISABLE_VF, sizeof(*req),
4103 wrb, NULL);
4104
4105 req->hdr.domain = domain;
4106 req->enable = 1;
4107 status = be_mcc_notify_wait(adapter);
4108err:
4109 spin_unlock_bh(&adapter->mcc_lock);
4110 return status;
4111}
4112
68c45a2d
SK		 4113int be_cmd_intr_set(struct be_adapter *adapter, bool intr_enable)
4114{
4115 struct be_mcc_wrb *wrb;
4116 struct be_cmd_req_intr_set *req;
4117 int status;
4118
4119 if (mutex_lock_interruptible(&adapter->mbox_lock))
4120 return -1;
4121
4122 wrb = wrb_from_mbox(adapter);
4123
4124 req = embedded_payload(wrb);
4125
4126 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
4127 OPCODE_COMMON_SET_INTERRUPT_ENABLE, sizeof(*req),
4128 wrb, NULL);
4129
4130 req->intr_enabled = intr_enable;
4131
4132 status = be_mbox_notify_wait(adapter);
4133
4134 mutex_unlock(&adapter->mbox_lock);
4135 return status;
4136}
4137
542963b7
VV		 4138/* Uses MBOX */
4139int be_cmd_get_active_profile(struct be_adapter *adapter, u16 *profile_id)
4140{
4141 struct be_cmd_req_get_active_profile *req;
4142 struct be_mcc_wrb *wrb;
4143 int status;
4144
4145 if (mutex_lock_interruptible(&adapter->mbox_lock))
4146 return -1;
4147
4148 wrb = wrb_from_mbox(adapter);
4149 if (!wrb) {
4150 status = -EBUSY;
4151 goto err;
4152 }
4153
4154 req = embedded_payload(wrb);
4155
4156 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
4157 OPCODE_COMMON_GET_ACTIVE_PROFILE, sizeof(*req),
4158 wrb, NULL);
4159
4160 status = be_mbox_notify_wait(adapter);
4161 if (!status) {
4162 struct be_cmd_resp_get_active_profile *resp =
4163 embedded_payload(wrb);
03d28ffe 4164
542963b7
VV		 4165 *profile_id = le16_to_cpu(resp->active_profile_id);
4166 }
4167
4168err:
4169 mutex_unlock(&adapter->mbox_lock);
4170 return status;
4171}
4172
bdce2ad7
SR		 4173int be_cmd_set_logical_link_config(struct be_adapter *adapter,
4174 int link_state, u8 domain)
4175{
4176 struct be_mcc_wrb *wrb;
4177 struct be_cmd_req_set_ll_link *req;
4178 int status;
4179
4180 if (BEx_chip(adapter) || lancer_chip(adapter))
18fd6025 4181 return -EOPNOTSUPP;
bdce2ad7
SR		 4182
4183 spin_lock_bh(&adapter->mcc_lock);
4184
4185 wrb = wrb_from_mccq(adapter);
4186 if (!wrb) {
4187 status = -EBUSY;
4188 goto err;
4189 }
4190
4191 req = embedded_payload(wrb);
4192
4193 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
4194 OPCODE_COMMON_SET_LOGICAL_LINK_CONFIG,
4195 sizeof(*req), wrb, NULL);
4196
4197 req->hdr.version = 1;
4198 req->hdr.domain = domain;
4199
4200 if (link_state == IFLA_VF_LINK_STATE_ENABLE)
4201 req->link_config |= 1;
4202
4203 if (link_state == IFLA_VF_LINK_STATE_AUTO)
4204 req->link_config |= 1 << PLINK_TRACK_SHIFT;
4205
4206 status = be_mcc_notify_wait(adapter);
4207err:
4208 spin_unlock_bh(&adapter->mcc_lock);
4209 return status;
4210}
4211
6a4ab669 4212int be_roce_mcc_cmd(void *netdev_handle, void *wrb_payload,
a2cc4e0b 4213 int wrb_payload_size, u16 *cmd_status, u16 *ext_status)
6a4ab669
PP		 4214{
4215 struct be_adapter *adapter = netdev_priv(netdev_handle);
4216 struct be_mcc_wrb *wrb;
504fbf1e 4217 struct be_cmd_req_hdr *hdr = (struct be_cmd_req_hdr *)wrb_payload;
6a4ab669
PP		 4218 struct be_cmd_req_hdr *req;
4219 struct be_cmd_resp_hdr *resp;
4220 int status;
4221
4222 spin_lock_bh(&adapter->mcc_lock);
4223
4224 wrb = wrb_from_mccq(adapter);
4225 if (!wrb) {
4226 status = -EBUSY;
4227 goto err;
4228 }
4229 req = embedded_payload(wrb);
4230 resp = embedded_payload(wrb);
4231
4232 be_wrb_cmd_hdr_prepare(req, hdr->subsystem,
4233 hdr->opcode, wrb_payload_size, wrb, NULL);
4234 memcpy(req, wrb_payload, wrb_payload_size);
4235 be_dws_cpu_to_le(req, wrb_payload_size);
4236
4237 status = be_mcc_notify_wait(adapter);
4238 if (cmd_status)
4239 *cmd_status = (status & 0xffff);
4240 if (ext_status)
4241 *ext_status = 0;
4242 memcpy(wrb_payload, resp, sizeof(*resp) + resp->response_length);
4243 be_dws_le_to_cpu(wrb_payload, sizeof(*resp) + resp->response_length);
4244err:
4245 spin_unlock_bh(&adapter->mcc_lock);
4246 return status;
4247}
4248EXPORT_SYMBOL(be_roce_mcc_cmd);
Linux kernel - Deliverables
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