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be2net: modify log msg for lack of privilege error
[deliverable/linux.git] / drivers / net / ethernet / emulex / benet / be_cmds.c
CommitLineData
6b7c5b94 1/*
d2145cde 2 * Copyright (C) 2005 - 2011 Emulex
6b7c5b94
SP		 3 * All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License version 2
7 * as published by the Free Software Foundation. The full GNU General
8 * Public License is included in this distribution in the file called COPYING.
9 *
10 * Contact Information:
d2145cde 11 * linux-drivers@emulex.com
6b7c5b94 12 *
d2145cde
AK		 13 * Emulex
14 * 3333 Susan Street
15 * Costa Mesa, CA 92626
6b7c5b94
SP		 16 */
17
6a4ab669 18#include <linux/module.h>
6b7c5b94 19#include "be.h"
8788fdc2 20#include "be_cmds.h"
6b7c5b94 21
3de09455
SK		 22static inline void *embedded_payload(struct be_mcc_wrb *wrb)
23{
24 return wrb->payload.embedded_payload;
25}
609ff3bb 26
8788fdc2 27static void be_mcc_notify(struct be_adapter *adapter)
5fb379ee 28{
8788fdc2 29 struct be_queue_info *mccq = &adapter->mcc_obj.q;
5fb379ee
SP		 30 u32 val = 0;
31
6589ade0 32 if (be_error(adapter))
7acc2087 33 return;
7acc2087 34
5fb379ee
SP		 35 val |= mccq->id & DB_MCCQ_RING_ID_MASK;
36 val |= 1 << DB_MCCQ_NUM_POSTED_SHIFT;
f3eb62d2
SP		 37
38 wmb();
8788fdc2 39 iowrite32(val, adapter->db + DB_MCCQ_OFFSET);
5fb379ee
SP		 40}
41
42/* To check if valid bit is set, check the entire word as we don't know
43 * the endianness of the data (old entry is host endian while a new entry is
44 * little endian) */
efd2e40a 45static inline bool be_mcc_compl_is_new(struct be_mcc_compl *compl)
5fb379ee
SP		 46{
47 if (compl->flags != 0) {
48 compl->flags = le32_to_cpu(compl->flags);
49 BUG_ON((compl->flags & CQE_FLAGS_VALID_MASK) == 0);
50 return true;
51 } else {
52 return false;
53 }
54}
55
56/* Need to reset the entire word that houses the valid bit */
efd2e40a 57static inline void be_mcc_compl_use(struct be_mcc_compl *compl)
5fb379ee
SP		 58{
59 compl->flags = 0;
60}
61
652bf646
PR		 62static struct be_cmd_resp_hdr *be_decode_resp_hdr(u32 tag0, u32 tag1)
63{
64 unsigned long addr;
65
66 addr = tag1;
67 addr = ((addr << 16) << 16) | tag0;
68 return (void *)addr;
69}
70
8788fdc2 71static int be_mcc_compl_process(struct be_adapter *adapter,
652bf646 72 struct be_mcc_compl *compl)
5fb379ee
SP		 73{
74 u16 compl_status, extd_status;
652bf646
PR		 75 struct be_cmd_resp_hdr *resp_hdr;
76 u8 opcode = 0, subsystem = 0;
5fb379ee
SP		 77
78 /* Just swap the status to host endian; mcc tag is opaquely copied
79 * from mcc_wrb */
80 be_dws_le_to_cpu(compl, 4);
81
82 compl_status = (compl->status >> CQE_STATUS_COMPL_SHIFT) &
83 CQE_STATUS_COMPL_MASK;
dd131e76 84
652bf646
PR		 85 resp_hdr = be_decode_resp_hdr(compl->tag0, compl->tag1);
86
87 if (resp_hdr) {
88 opcode = resp_hdr->opcode;
89 subsystem = resp_hdr->subsystem;
90 }
91
92 if (((opcode == OPCODE_COMMON_WRITE_FLASHROM) ||
93 (opcode == OPCODE_COMMON_WRITE_OBJECT)) &&
94 (subsystem == CMD_SUBSYSTEM_COMMON)) {
dd131e76
SB		 95 adapter->flash_status = compl_status;
96 complete(&adapter->flash_compl);
97 }
98
b31c50a7 99 if (compl_status == MCC_STATUS_SUCCESS) {
652bf646
PR		 100 if (((opcode == OPCODE_ETH_GET_STATISTICS) ||
101 (opcode == OPCODE_ETH_GET_PPORT_STATS)) &&
102 (subsystem == CMD_SUBSYSTEM_ETH)) {
89a88ab8 103 be_parse_stats(adapter);
b2aebe6d 104 adapter->stats_cmd_sent = false;
b31c50a7 105 }
652bf646
PR		 106 if (opcode == OPCODE_COMMON_GET_CNTL_ADDITIONAL_ATTRIBUTES &&
107 subsystem == CMD_SUBSYSTEM_COMMON) {
3de09455 108 struct be_cmd_resp_get_cntl_addnl_attribs *resp =
652bf646 109 (void *)resp_hdr;
3de09455
SK		 110 adapter->drv_stats.be_on_die_temperature =
111 resp->on_die_temperature;
112 }
2b3f291b 113 } else {
652bf646 114 if (opcode == OPCODE_COMMON_GET_CNTL_ADDITIONAL_ATTRIBUTES)
7aeb2156 115 adapter->be_get_temp_freq = 0;
3de09455 116
2b3f291b
SP		 117 if (compl_status == MCC_STATUS_NOT_SUPPORTED ||
118 compl_status == MCC_STATUS_ILLEGAL_REQUEST)
119 goto done;
120
121 if (compl_status == MCC_STATUS_UNAUTHORIZED_REQUEST) {
97f1d8cd 122 dev_warn(&adapter->pdev->dev,
522609f2 123 "VF is not privileged to issue opcode %d-%d\n",
97f1d8cd 124 opcode, subsystem);
2b3f291b
SP		 125 } else {
126 extd_status = (compl->status >> CQE_STATUS_EXTD_SHIFT) &
127 CQE_STATUS_EXTD_MASK;
97f1d8cd
VV		 128 dev_err(&adapter->pdev->dev,
129 "opcode %d-%d failed:status %d-%d\n",
130 opcode, subsystem, compl_status, extd_status);
2b3f291b 131 }
5fb379ee 132 }
2b3f291b 133done:
b31c50a7 134 return compl_status;
5fb379ee
SP		 135}
136
a8f447bd 137/* Link state evt is a string of bytes; no need for endian swapping */
8788fdc2 138static void be_async_link_state_process(struct be_adapter *adapter,
a8f447bd
SP		 139 struct be_async_event_link_state *evt)
140{
b236916a 141 /* When link status changes, link speed must be re-queried from FW */
42f11cf2 142 adapter->phy.link_speed = -1;
b236916a 143
2e177a5c
PR		 144 /* Ignore physical link event */
145 if (lancer_chip(adapter) &&
146 !(evt->port_link_status & LOGICAL_LINK_STATUS_MASK))
147 return;
148
b236916a
AK		 149 /* For the initial link status do not rely on the ASYNC event as
150 * it may not be received in some cases.
151 */
152 if (adapter->flags & BE_FLAGS_LINK_STATUS_INIT)
153 be_link_status_update(adapter, evt->port_link_status);
a8f447bd
SP		 154}
155
cc4ce020
SK		 156/* Grp5 CoS Priority evt */
157static void be_async_grp5_cos_priority_process(struct be_adapter *adapter,
158 struct be_async_event_grp5_cos_priority *evt)
159{
160 if (evt->valid) {
161 adapter->vlan_prio_bmap = evt->available_priority_bmap;
60964dd7 162 adapter->recommended_prio &= ~VLAN_PRIO_MASK;
cc4ce020
SK		 163 adapter->recommended_prio =
164 evt->reco_default_priority << VLAN_PRIO_SHIFT;
165 }
166}
167
168/* Grp5 QOS Speed evt */
169static void be_async_grp5_qos_speed_process(struct be_adapter *adapter,
170 struct be_async_event_grp5_qos_link_speed *evt)
171{
172 if (evt->physical_port == adapter->port_num) {
173 /* qos_link_speed is in units of 10 Mbps */
42f11cf2 174 adapter->phy.link_speed = evt->qos_link_speed * 10;
cc4ce020
SK		 175 }
176}
177
3968fa1e
AK		 178/*Grp5 PVID evt*/
179static void be_async_grp5_pvid_state_process(struct be_adapter *adapter,
180 struct be_async_event_grp5_pvid_state *evt)
181{
182 if (evt->enabled)
939cf306 183 adapter->pvid = le16_to_cpu(evt->tag) & VLAN_VID_MASK;
3968fa1e
AK		 184 else
185 adapter->pvid = 0;
186}
187
cc4ce020
SK		 188static void be_async_grp5_evt_process(struct be_adapter *adapter,
189 u32 trailer, struct be_mcc_compl *evt)
190{
191 u8 event_type = 0;
192
193 event_type = (trailer >> ASYNC_TRAILER_EVENT_TYPE_SHIFT) &
194 ASYNC_TRAILER_EVENT_TYPE_MASK;
195
196 switch (event_type) {
197 case ASYNC_EVENT_COS_PRIORITY:
198 be_async_grp5_cos_priority_process(adapter,
199 (struct be_async_event_grp5_cos_priority *)evt);
200 break;
201 case ASYNC_EVENT_QOS_SPEED:
202 be_async_grp5_qos_speed_process(adapter,
203 (struct be_async_event_grp5_qos_link_speed *)evt);
204 break;
3968fa1e
AK		 205 case ASYNC_EVENT_PVID_STATE:
206 be_async_grp5_pvid_state_process(adapter,
207 (struct be_async_event_grp5_pvid_state *)evt);
208 break;
cc4ce020
SK		 209 default:
210 dev_warn(&adapter->pdev->dev, "Unknown grp5 event!\n");
211 break;
212 }
213}
214
a8f447bd
SP		 215static inline bool is_link_state_evt(u32 trailer)
216{
807540ba 217 return ((trailer >> ASYNC_TRAILER_EVENT_CODE_SHIFT) &
a8f447bd 218 ASYNC_TRAILER_EVENT_CODE_MASK) ==
807540ba 219 ASYNC_EVENT_CODE_LINK_STATE;
a8f447bd 220}
5fb379ee 221
cc4ce020
SK		 222static inline bool is_grp5_evt(u32 trailer)
223{
224 return (((trailer >> ASYNC_TRAILER_EVENT_CODE_SHIFT) &
225 ASYNC_TRAILER_EVENT_CODE_MASK) ==
226 ASYNC_EVENT_CODE_GRP_5);
227}
228
efd2e40a 229static struct be_mcc_compl *be_mcc_compl_get(struct be_adapter *adapter)
5fb379ee 230{
8788fdc2 231 struct be_queue_info *mcc_cq = &adapter->mcc_obj.cq;
efd2e40a 232 struct be_mcc_compl *compl = queue_tail_node(mcc_cq);
5fb379ee
SP		 233
234 if (be_mcc_compl_is_new(compl)) {
235 queue_tail_inc(mcc_cq);
236 return compl;
237 }
238 return NULL;
239}
240
7a1e9b20
SP		 241void be_async_mcc_enable(struct be_adapter *adapter)
242{
243 spin_lock_bh(&adapter->mcc_cq_lock);
244
245 be_cq_notify(adapter, adapter->mcc_obj.cq.id, true, 0);
246 adapter->mcc_obj.rearm_cq = true;
247
248 spin_unlock_bh(&adapter->mcc_cq_lock);
249}
250
251void be_async_mcc_disable(struct be_adapter *adapter)
252{
253 adapter->mcc_obj.rearm_cq = false;
254}
255
10ef9ab4 256int be_process_mcc(struct be_adapter *adapter)
5fb379ee 257{
efd2e40a 258 struct be_mcc_compl *compl;
10ef9ab4 259 int num = 0, status = 0;
7a1e9b20 260 struct be_mcc_obj *mcc_obj = &adapter->mcc_obj;
5fb379ee 261
8788fdc2
SP		 262 spin_lock_bh(&adapter->mcc_cq_lock);
263 while ((compl = be_mcc_compl_get(adapter))) {
a8f447bd
SP		 264 if (compl->flags & CQE_FLAGS_ASYNC_MASK) {
265 /* Interpret flags as an async trailer */
323f30b3
AK		 266 if (is_link_state_evt(compl->flags))
267 be_async_link_state_process(adapter,
a8f447bd 268 (struct be_async_event_link_state *) compl);
cc4ce020
SK		 269 else if (is_grp5_evt(compl->flags))
270 be_async_grp5_evt_process(adapter,
271 compl->flags, compl);
b31c50a7 272 } else if (compl->flags & CQE_FLAGS_COMPLETED_MASK) {
10ef9ab4 273 status = be_mcc_compl_process(adapter, compl);
7a1e9b20 274 atomic_dec(&mcc_obj->q.used);
5fb379ee
SP		 275 }
276 be_mcc_compl_use(compl);
277 num++;
278 }
b31c50a7 279
10ef9ab4
SP		 280 if (num)
281 be_cq_notify(adapter, mcc_obj->cq.id, mcc_obj->rearm_cq, num);
282
8788fdc2 283 spin_unlock_bh(&adapter->mcc_cq_lock);
10ef9ab4 284 return status;
5fb379ee
SP		 285}
286
6ac7b687 287/* Wait till no more pending mcc requests are present */
b31c50a7 288static int be_mcc_wait_compl(struct be_adapter *adapter)
6ac7b687 289{
b31c50a7 290#define mcc_timeout 120000 /* 12s timeout */
10ef9ab4 291 int i, status = 0;
f31e50a8
SP		 292 struct be_mcc_obj *mcc_obj = &adapter->mcc_obj;
293
6ac7b687 294 for (i = 0; i < mcc_timeout; i++) {
6589ade0
SP		 295 if (be_error(adapter))
296 return -EIO;
297
10ef9ab4 298 status = be_process_mcc(adapter);
b31c50a7 299
f31e50a8 300 if (atomic_read(&mcc_obj->q.used) == 0)
6ac7b687
SP		 301 break;
302 udelay(100);
303 }
b31c50a7 304 if (i == mcc_timeout) {
6589ade0
SP		 305 dev_err(&adapter->pdev->dev, "FW not responding\n");
306 adapter->fw_timeout = true;
652bf646 307 return -EIO;
b31c50a7 308 }
f31e50a8 309 return status;
6ac7b687
SP		 310}
311
312/* Notify MCC requests and wait for completion */
b31c50a7 313static int be_mcc_notify_wait(struct be_adapter *adapter)
6ac7b687 314{
652bf646
PR		 315 int status;
316 struct be_mcc_wrb *wrb;
317 struct be_mcc_obj *mcc_obj = &adapter->mcc_obj;
318 u16 index = mcc_obj->q.head;
319 struct be_cmd_resp_hdr *resp;
320
321 index_dec(&index, mcc_obj->q.len);
322 wrb = queue_index_node(&mcc_obj->q, index);
323
324 resp = be_decode_resp_hdr(wrb->tag0, wrb->tag1);
325
8788fdc2 326 be_mcc_notify(adapter);
652bf646
PR		 327
328 status = be_mcc_wait_compl(adapter);
329 if (status == -EIO)
330 goto out;
331
332 status = resp->status;
333out:
334 return status;
6ac7b687
SP		 335}
336
5f0b849e 337static int be_mbox_db_ready_wait(struct be_adapter *adapter, void __iomem *db)
6b7c5b94 338{
f25b03a7 339 int msecs = 0;
6b7c5b94
SP		 340 u32 ready;
341
342 do {
6589ade0
SP		 343 if (be_error(adapter))
344 return -EIO;
345
cf588477 346 ready = ioread32(db);
434b3648 347 if (ready == 0xffffffff)
cf588477 348 return -1;
cf588477
SP		 349
350 ready &= MPU_MAILBOX_DB_RDY_MASK;
6b7c5b94
SP		 351 if (ready)
352 break;
353
f25b03a7 354 if (msecs > 4000) {
6589ade0
SP		 355 dev_err(&adapter->pdev->dev, "FW not responding\n");
356 adapter->fw_timeout = true;
f67ef7ba 357 be_detect_error(adapter);
6b7c5b94
SP		 358 return -1;
359 }
360
1dbf53a2 361 msleep(1);
f25b03a7 362 msecs++;
6b7c5b94
SP		 363 } while (true);
364
365 return 0;
366}
367
368/*
369 * Insert the mailbox address into the doorbell in two steps
5fb379ee 370 * Polls on the mbox doorbell till a command completion (or a timeout) occurs
6b7c5b94 371 */
b31c50a7 372static int be_mbox_notify_wait(struct be_adapter *adapter)
6b7c5b94
SP		 373{
374 int status;
6b7c5b94 375 u32 val = 0;
8788fdc2
SP		 376 void __iomem *db = adapter->db + MPU_MAILBOX_DB_OFFSET;
377 struct be_dma_mem *mbox_mem = &adapter->mbox_mem;
6b7c5b94 378 struct be_mcc_mailbox *mbox = mbox_mem->va;
efd2e40a 379 struct be_mcc_compl *compl = &mbox->compl;
6b7c5b94 380
cf588477
SP		 381 /* wait for ready to be set */
382 status = be_mbox_db_ready_wait(adapter, db);
383 if (status != 0)
384 return status;
385
6b7c5b94
SP		 386 val |= MPU_MAILBOX_DB_HI_MASK;
387 /* at bits 2 - 31 place mbox dma addr msb bits 34 - 63 */
388 val |= (upper_32_bits(mbox_mem->dma) >> 2) << 2;
389 iowrite32(val, db);
390
391 /* wait for ready to be set */
5f0b849e 392 status = be_mbox_db_ready_wait(adapter, db);
6b7c5b94
SP		 393 if (status != 0)
394 return status;
395
396 val = 0;
6b7c5b94
SP		 397 /* at bits 2 - 31 place mbox dma addr lsb bits 4 - 33 */
398 val |= (u32)(mbox_mem->dma >> 4) << 2;
399 iowrite32(val, db);
400
5f0b849e 401 status = be_mbox_db_ready_wait(adapter, db);
6b7c5b94
SP		 402 if (status != 0)
403 return status;
404
5fb379ee 405 /* A cq entry has been made now */
efd2e40a
SP		 406 if (be_mcc_compl_is_new(compl)) {
407 status = be_mcc_compl_process(adapter, &mbox->compl);
408 be_mcc_compl_use(compl);
5fb379ee
SP		 409 if (status)
410 return status;
411 } else {
5f0b849e 412 dev_err(&adapter->pdev->dev, "invalid mailbox completion\n");
6b7c5b94
SP		 413 return -1;
414 }
5fb379ee 415 return 0;
6b7c5b94
SP		 416}
417
8788fdc2 418static int be_POST_stage_get(struct be_adapter *adapter, u16 *stage)
6b7c5b94 419{
fe6d2a38
SP		 420 u32 sem;
421
422 if (lancer_chip(adapter))
423 sem = ioread32(adapter->db + MPU_EP_SEMAPHORE_IF_TYPE2_OFFSET);
424 else
425 sem = ioread32(adapter->csr + MPU_EP_SEMAPHORE_OFFSET);
6b7c5b94
SP		 426
427 *stage = sem & EP_SEMAPHORE_POST_STAGE_MASK;
428 if ((sem >> EP_SEMAPHORE_POST_ERR_SHIFT) & EP_SEMAPHORE_POST_ERR_MASK)
429 return -1;
430 else
431 return 0;
432}
433
bf99e50d
PR		 434int lancer_wait_ready(struct be_adapter *adapter)
435{
436#define SLIPORT_READY_TIMEOUT 30
437 u32 sliport_status;
438 int status = 0, i;
439
440 for (i = 0; i < SLIPORT_READY_TIMEOUT; i++) {
441 sliport_status = ioread32(adapter->db + SLIPORT_STATUS_OFFSET);
442 if (sliport_status & SLIPORT_STATUS_RDY_MASK)
443 break;
444
445 msleep(1000);
446 }
447
448 if (i == SLIPORT_READY_TIMEOUT)
449 status = -1;
450
451 return status;
452}
453
454int lancer_test_and_set_rdy_state(struct be_adapter *adapter)
455{
456 int status;
457 u32 sliport_status, err, reset_needed;
458 status = lancer_wait_ready(adapter);
459 if (!status) {
460 sliport_status = ioread32(adapter->db + SLIPORT_STATUS_OFFSET);
461 err = sliport_status & SLIPORT_STATUS_ERR_MASK;
462 reset_needed = sliport_status & SLIPORT_STATUS_RN_MASK;
463 if (err && reset_needed) {
464 iowrite32(SLI_PORT_CONTROL_IP_MASK,
465 adapter->db + SLIPORT_CONTROL_OFFSET);
466
467 /* check adapter has corrected the error */
468 status = lancer_wait_ready(adapter);
469 sliport_status = ioread32(adapter->db +
470 SLIPORT_STATUS_OFFSET);
471 sliport_status &= (SLIPORT_STATUS_ERR_MASK |
472 SLIPORT_STATUS_RN_MASK);
473 if (status || sliport_status)
474 status = -1;
475 } else if (err || reset_needed) {
476 status = -1;
477 }
478 }
479 return status;
480}
481
482int be_fw_wait_ready(struct be_adapter *adapter)
6b7c5b94 483{
43a04fdc
SP		 484 u16 stage;
485 int status, timeout = 0;
6ed35eea 486 struct device *dev = &adapter->pdev->dev;
6b7c5b94 487
bf99e50d
PR		 488 if (lancer_chip(adapter)) {
489 status = lancer_wait_ready(adapter);
490 return status;
491 }
492
43a04fdc
SP		 493 do {
494 status = be_POST_stage_get(adapter, &stage);
495 if (status) {
6ed35eea 496 dev_err(dev, "POST error; stage=0x%x\n", stage);
43a04fdc
SP		 497 return -1;
498 } else if (stage != POST_STAGE_ARMFW_RDY) {
6ed35eea
SP		 499 if (msleep_interruptible(2000)) {
500 dev_err(dev, "Waiting for POST aborted\n");
501 return -EINTR;
502 }
43a04fdc
SP		 503 timeout += 2;
504 } else {
505 return 0;
506 }
3ab81b5f 507 } while (timeout < 60);
6b7c5b94 508
6ed35eea 509 dev_err(dev, "POST timeout; stage=0x%x\n", stage);
43a04fdc 510 return -1;
6b7c5b94
SP		 511}
512
6b7c5b94
SP		 513
514static inline struct be_sge *nonembedded_sgl(struct be_mcc_wrb *wrb)
515{
516 return &wrb->payload.sgl[0];
517}
518
6b7c5b94
SP		 519
520/* Don't touch the hdr after it's prepared */
106df1e3
SK		 521/* mem will be NULL for embedded commands */
522static void be_wrb_cmd_hdr_prepare(struct be_cmd_req_hdr *req_hdr,
523 u8 subsystem, u8 opcode, int cmd_len,
524 struct be_mcc_wrb *wrb, struct be_dma_mem *mem)
6b7c5b94 525{
106df1e3 526 struct be_sge *sge;
652bf646
PR		 527 unsigned long addr = (unsigned long)req_hdr;
528 u64 req_addr = addr;
106df1e3 529
6b7c5b94
SP		 530 req_hdr->opcode = opcode;
531 req_hdr->subsystem = subsystem;
532 req_hdr->request_length = cpu_to_le32(cmd_len - sizeof(*req_hdr));
07793d33 533 req_hdr->version = 0;
106df1e3 534
652bf646
PR		 535 wrb->tag0 = req_addr & 0xFFFFFFFF;
536 wrb->tag1 = upper_32_bits(req_addr);
537
106df1e3
SK		 538 wrb->payload_length = cmd_len;
539 if (mem) {
540 wrb->embedded |= (1 & MCC_WRB_SGE_CNT_MASK) <<
541 MCC_WRB_SGE_CNT_SHIFT;
542 sge = nonembedded_sgl(wrb);
543 sge->pa_hi = cpu_to_le32(upper_32_bits(mem->dma));
544 sge->pa_lo = cpu_to_le32(mem->dma & 0xFFFFFFFF);
545 sge->len = cpu_to_le32(mem->size);
546 } else
547 wrb->embedded |= MCC_WRB_EMBEDDED_MASK;
548 be_dws_cpu_to_le(wrb, 8);
6b7c5b94
SP		 549}
550
551static void be_cmd_page_addrs_prepare(struct phys_addr *pages, u32 max_pages,
552 struct be_dma_mem *mem)
553{
554 int i, buf_pages = min(PAGES_4K_SPANNED(mem->va, mem->size), max_pages);
555 u64 dma = (u64)mem->dma;
556
557 for (i = 0; i < buf_pages; i++) {
558 pages[i].lo = cpu_to_le32(dma & 0xFFFFFFFF);
559 pages[i].hi = cpu_to_le32(upper_32_bits(dma));
560 dma += PAGE_SIZE_4K;
561 }
562}
563
564/* Converts interrupt delay in microseconds to multiplier value */
565static u32 eq_delay_to_mult(u32 usec_delay)
566{
567#define MAX_INTR_RATE 651042
568 const u32 round = 10;
569 u32 multiplier;
570
571 if (usec_delay == 0)
572 multiplier = 0;
573 else {
574 u32 interrupt_rate = 1000000 / usec_delay;
575 /* Max delay, corresponding to the lowest interrupt rate */
576 if (interrupt_rate == 0)
577 multiplier = 1023;
578 else {
579 multiplier = (MAX_INTR_RATE - interrupt_rate) * round;
580 multiplier /= interrupt_rate;
581 /* Round the multiplier to the closest value.*/
582 multiplier = (multiplier + round/2) / round;
583 multiplier = min(multiplier, (u32)1023);
584 }
585 }
586 return multiplier;
587}
588
b31c50a7 589static inline struct be_mcc_wrb *wrb_from_mbox(struct be_adapter *adapter)
6b7c5b94 590{
b31c50a7
SP		 591 struct be_dma_mem *mbox_mem = &adapter->mbox_mem;
592 struct be_mcc_wrb *wrb
593 = &((struct be_mcc_mailbox *)(mbox_mem->va))->wrb;
594 memset(wrb, 0, sizeof(*wrb));
595 return wrb;
6b7c5b94
SP		 596}
597
b31c50a7 598static struct be_mcc_wrb *wrb_from_mccq(struct be_adapter *adapter)
5fb379ee 599{
b31c50a7
SP		 600 struct be_queue_info *mccq = &adapter->mcc_obj.q;
601 struct be_mcc_wrb *wrb;
602
713d0394
SP		 603 if (atomic_read(&mccq->used) >= mccq->len) {
604 dev_err(&adapter->pdev->dev, "Out of MCCQ wrbs\n");
605 return NULL;
606 }
607
b31c50a7
SP		 608 wrb = queue_head_node(mccq);
609 queue_head_inc(mccq);
610 atomic_inc(&mccq->used);
611 memset(wrb, 0, sizeof(*wrb));
5fb379ee
SP		 612 return wrb;
613}
614
2243e2e9
SP		 615/* Tell fw we're about to start firing cmds by writing a
616 * special pattern across the wrb hdr; uses mbox
617 */
618int be_cmd_fw_init(struct be_adapter *adapter)
619{
620 u8 *wrb;
621 int status;
622
bf99e50d
PR		 623 if (lancer_chip(adapter))
624 return 0;
625
2984961c
IV		 626 if (mutex_lock_interruptible(&adapter->mbox_lock))
627 return -1;
2243e2e9
SP		 628
629 wrb = (u8 *)wrb_from_mbox(adapter);
359a972f
SP		 630 *wrb++ = 0xFF;
631 *wrb++ = 0x12;
632 *wrb++ = 0x34;
633 *wrb++ = 0xFF;
634 *wrb++ = 0xFF;
635 *wrb++ = 0x56;
636 *wrb++ = 0x78;
637 *wrb = 0xFF;
2243e2e9
SP		 638
639 status = be_mbox_notify_wait(adapter);
640
2984961c 641 mutex_unlock(&adapter->mbox_lock);
2243e2e9
SP		 642 return status;
643}
644
645/* Tell fw we're done with firing cmds by writing a
646 * special pattern across the wrb hdr; uses mbox
647 */
648int be_cmd_fw_clean(struct be_adapter *adapter)
649{
650 u8 *wrb;
651 int status;
652
bf99e50d
PR		 653 if (lancer_chip(adapter))
654 return 0;
655
2984961c
IV		 656 if (mutex_lock_interruptible(&adapter->mbox_lock))
657 return -1;
2243e2e9
SP		 658
659 wrb = (u8 *)wrb_from_mbox(adapter);
660 *wrb++ = 0xFF;
661 *wrb++ = 0xAA;
662 *wrb++ = 0xBB;
663 *wrb++ = 0xFF;
664 *wrb++ = 0xFF;
665 *wrb++ = 0xCC;
666 *wrb++ = 0xDD;
667 *wrb = 0xFF;
668
669 status = be_mbox_notify_wait(adapter);
670
2984961c 671 mutex_unlock(&adapter->mbox_lock);
2243e2e9
SP		 672 return status;
673}
bf99e50d 674
8788fdc2 675int be_cmd_eq_create(struct be_adapter *adapter,
6b7c5b94
SP		 676 struct be_queue_info *eq, int eq_delay)
677{
b31c50a7
SP		 678 struct be_mcc_wrb *wrb;
679 struct be_cmd_req_eq_create *req;
6b7c5b94
SP		 680 struct be_dma_mem *q_mem = &eq->dma_mem;
681 int status;
682
2984961c
IV		 683 if (mutex_lock_interruptible(&adapter->mbox_lock))
684 return -1;
b31c50a7
SP		 685
686 wrb = wrb_from_mbox(adapter);
687 req = embedded_payload(wrb);
6b7c5b94 688
106df1e3
SK		 689 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
690 OPCODE_COMMON_EQ_CREATE, sizeof(*req), wrb, NULL);
6b7c5b94
SP		 691
692 req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
693
6b7c5b94
SP		 694 AMAP_SET_BITS(struct amap_eq_context, valid, req->context, 1);
695 /* 4byte eqe*/
696 AMAP_SET_BITS(struct amap_eq_context, size, req->context, 0);
697 AMAP_SET_BITS(struct amap_eq_context, count, req->context,
698 __ilog2_u32(eq->len/256));
699 AMAP_SET_BITS(struct amap_eq_context, delaymult, req->context,
700 eq_delay_to_mult(eq_delay));
701 be_dws_cpu_to_le(req->context, sizeof(req->context));
702
703 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
704
b31c50a7 705 status = be_mbox_notify_wait(adapter);
6b7c5b94 706 if (!status) {
b31c50a7 707 struct be_cmd_resp_eq_create *resp = embedded_payload(wrb);
6b7c5b94
SP		 708 eq->id = le16_to_cpu(resp->eq_id);
709 eq->created = true;
710 }
b31c50a7 711
2984961c 712 mutex_unlock(&adapter->mbox_lock);
6b7c5b94
SP		 713 return status;
714}
715
f9449ab7 716/* Use MCC */
8788fdc2 717int be_cmd_mac_addr_query(struct be_adapter *adapter, u8 *mac_addr,
590c391d 718 u8 type, bool permanent, u32 if_handle, u32 pmac_id)
6b7c5b94 719{
b31c50a7
SP		 720 struct be_mcc_wrb *wrb;
721 struct be_cmd_req_mac_query *req;
6b7c5b94
SP		 722 int status;
723
f9449ab7 724 spin_lock_bh(&adapter->mcc_lock);
b31c50a7 725
f9449ab7
SP		 726 wrb = wrb_from_mccq(adapter);
727 if (!wrb) {
728 status = -EBUSY;
729 goto err;
730 }
b31c50a7 731 req = embedded_payload(wrb);
6b7c5b94 732
106df1e3
SK		 733 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
734 OPCODE_COMMON_NTWK_MAC_QUERY, sizeof(*req), wrb, NULL);
6b7c5b94
SP		 735 req->type = type;
736 if (permanent) {
737 req->permanent = 1;
738 } else {
b31c50a7 739 req->if_id = cpu_to_le16((u16) if_handle);
590c391d 740 req->pmac_id = cpu_to_le32(pmac_id);
6b7c5b94
SP		 741 req->permanent = 0;
742 }
743
f9449ab7 744 status = be_mcc_notify_wait(adapter);
b31c50a7
SP		 745 if (!status) {
746 struct be_cmd_resp_mac_query *resp = embedded_payload(wrb);
6b7c5b94 747 memcpy(mac_addr, resp->mac.addr, ETH_ALEN);
b31c50a7 748 }
6b7c5b94 749
f9449ab7
SP		 750err:
751 spin_unlock_bh(&adapter->mcc_lock);
6b7c5b94
SP		 752 return status;
753}
754
b31c50a7 755/* Uses synchronous MCCQ */
8788fdc2 756int be_cmd_pmac_add(struct be_adapter *adapter, u8 *mac_addr,
f8617e08 757 u32 if_id, u32 *pmac_id, u32 domain)
6b7c5b94 758{
b31c50a7
SP		 759 struct be_mcc_wrb *wrb;
760 struct be_cmd_req_pmac_add *req;
6b7c5b94
SP		 761 int status;
762
b31c50a7
SP		 763 spin_lock_bh(&adapter->mcc_lock);
764
765 wrb = wrb_from_mccq(adapter);
713d0394
SP		 766 if (!wrb) {
767 status = -EBUSY;
768 goto err;
769 }
b31c50a7 770 req = embedded_payload(wrb);
6b7c5b94 771
106df1e3
SK		 772 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
773 OPCODE_COMMON_NTWK_PMAC_ADD, sizeof(*req), wrb, NULL);
6b7c5b94 774
f8617e08 775 req->hdr.domain = domain;
6b7c5b94
SP		 776 req->if_id = cpu_to_le32(if_id);
777 memcpy(req->mac_address, mac_addr, ETH_ALEN);
778
b31c50a7 779 status = be_mcc_notify_wait(adapter);
6b7c5b94
SP		 780 if (!status) {
781 struct be_cmd_resp_pmac_add *resp = embedded_payload(wrb);
782 *pmac_id = le32_to_cpu(resp->pmac_id);
783 }
784
713d0394 785err:
b31c50a7 786 spin_unlock_bh(&adapter->mcc_lock);
e3a7ae2c
SK		 787
788 if (status == MCC_STATUS_UNAUTHORIZED_REQUEST)
789 status = -EPERM;
790
6b7c5b94
SP		 791 return status;
792}
793
b31c50a7 794/* Uses synchronous MCCQ */
30128031 795int be_cmd_pmac_del(struct be_adapter *adapter, u32 if_id, int pmac_id, u32 dom)
6b7c5b94 796{
b31c50a7
SP		 797 struct be_mcc_wrb *wrb;
798 struct be_cmd_req_pmac_del *req;
6b7c5b94
SP		 799 int status;
800
30128031
SP		 801 if (pmac_id == -1)
802 return 0;
803
b31c50a7
SP		 804 spin_lock_bh(&adapter->mcc_lock);
805
806 wrb = wrb_from_mccq(adapter);
713d0394
SP		 807 if (!wrb) {
808 status = -EBUSY;
809 goto err;
810 }
b31c50a7 811 req = embedded_payload(wrb);
6b7c5b94 812
106df1e3
SK		 813 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
814 OPCODE_COMMON_NTWK_PMAC_DEL, sizeof(*req), wrb, NULL);
6b7c5b94 815
f8617e08 816 req->hdr.domain = dom;
6b7c5b94
SP		 817 req->if_id = cpu_to_le32(if_id);
818 req->pmac_id = cpu_to_le32(pmac_id);
819
b31c50a7
SP		 820 status = be_mcc_notify_wait(adapter);
821
713d0394 822err:
b31c50a7 823 spin_unlock_bh(&adapter->mcc_lock);
6b7c5b94
SP		 824 return status;
825}
826
b31c50a7 827/* Uses Mbox */
10ef9ab4
SP		 828int be_cmd_cq_create(struct be_adapter *adapter, struct be_queue_info *cq,
829 struct be_queue_info *eq, bool no_delay, int coalesce_wm)
6b7c5b94 830{
b31c50a7
SP		 831 struct be_mcc_wrb *wrb;
832 struct be_cmd_req_cq_create *req;
6b7c5b94 833 struct be_dma_mem *q_mem = &cq->dma_mem;
b31c50a7 834 void *ctxt;
6b7c5b94
SP		 835 int status;
836
2984961c
IV		 837 if (mutex_lock_interruptible(&adapter->mbox_lock))
838 return -1;
b31c50a7
SP		 839
840 wrb = wrb_from_mbox(adapter);
841 req = embedded_payload(wrb);
842 ctxt = &req->context;
6b7c5b94 843
106df1e3
SK		 844 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
845 OPCODE_COMMON_CQ_CREATE, sizeof(*req), wrb, NULL);
6b7c5b94
SP		 846
847 req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
fe6d2a38 848 if (lancer_chip(adapter)) {
8b7756ca 849 req->hdr.version = 2;
fe6d2a38 850 req->page_size = 1; /* 1 for 4K */
fe6d2a38
SP		 851 AMAP_SET_BITS(struct amap_cq_context_lancer, nodelay, ctxt,
852 no_delay);
853 AMAP_SET_BITS(struct amap_cq_context_lancer, count, ctxt,
854 __ilog2_u32(cq->len/256));
855 AMAP_SET_BITS(struct amap_cq_context_lancer, valid, ctxt, 1);
856 AMAP_SET_BITS(struct amap_cq_context_lancer, eventable,
857 ctxt, 1);
858 AMAP_SET_BITS(struct amap_cq_context_lancer, eqid,
859 ctxt, eq->id);
fe6d2a38
SP		 860 } else {
861 AMAP_SET_BITS(struct amap_cq_context_be, coalescwm, ctxt,
862 coalesce_wm);
863 AMAP_SET_BITS(struct amap_cq_context_be, nodelay,
864 ctxt, no_delay);
865 AMAP_SET_BITS(struct amap_cq_context_be, count, ctxt,
866 __ilog2_u32(cq->len/256));
867 AMAP_SET_BITS(struct amap_cq_context_be, valid, ctxt, 1);
fe6d2a38
SP		 868 AMAP_SET_BITS(struct amap_cq_context_be, eventable, ctxt, 1);
869 AMAP_SET_BITS(struct amap_cq_context_be, eqid, ctxt, eq->id);
fe6d2a38 870 }
6b7c5b94 871
6b7c5b94
SP		 872 be_dws_cpu_to_le(ctxt, sizeof(req->context));
873
874 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
875
b31c50a7 876 status = be_mbox_notify_wait(adapter);
6b7c5b94 877 if (!status) {
b31c50a7 878 struct be_cmd_resp_cq_create *resp = embedded_payload(wrb);
6b7c5b94
SP		 879 cq->id = le16_to_cpu(resp->cq_id);
880 cq->created = true;
881 }
b31c50a7 882
2984961c 883 mutex_unlock(&adapter->mbox_lock);
5fb379ee
SP		 884
885 return status;
886}
887
888static u32 be_encoded_q_len(int q_len)
889{
890 u32 len_encoded = fls(q_len); /* log2(len) + 1 */
891 if (len_encoded == 16)
892 len_encoded = 0;
893 return len_encoded;
894}
895
34b1ef04 896int be_cmd_mccq_ext_create(struct be_adapter *adapter,
5fb379ee
SP		 897 struct be_queue_info *mccq,
898 struct be_queue_info *cq)
899{
b31c50a7 900 struct be_mcc_wrb *wrb;
34b1ef04 901 struct be_cmd_req_mcc_ext_create *req;
5fb379ee 902 struct be_dma_mem *q_mem = &mccq->dma_mem;
b31c50a7 903 void *ctxt;
5fb379ee
SP		 904 int status;
905
2984961c
IV		 906 if (mutex_lock_interruptible(&adapter->mbox_lock))
907 return -1;
b31c50a7
SP		 908
909 wrb = wrb_from_mbox(adapter);
910 req = embedded_payload(wrb);
911 ctxt = &req->context;
5fb379ee 912
106df1e3
SK		 913 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
914 OPCODE_COMMON_MCC_CREATE_EXT, sizeof(*req), wrb, NULL);
5fb379ee 915
d4a2ac3e 916 req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
fe6d2a38
SP		 917 if (lancer_chip(adapter)) {
918 req->hdr.version = 1;
919 req->cq_id = cpu_to_le16(cq->id);
920
921 AMAP_SET_BITS(struct amap_mcc_context_lancer, ring_size, ctxt,
922 be_encoded_q_len(mccq->len));
923 AMAP_SET_BITS(struct amap_mcc_context_lancer, valid, ctxt, 1);
924 AMAP_SET_BITS(struct amap_mcc_context_lancer, async_cq_id,
925 ctxt, cq->id);
926 AMAP_SET_BITS(struct amap_mcc_context_lancer, async_cq_valid,
927 ctxt, 1);
928
929 } else {
930 AMAP_SET_BITS(struct amap_mcc_context_be, valid, ctxt, 1);
931 AMAP_SET_BITS(struct amap_mcc_context_be, ring_size, ctxt,
932 be_encoded_q_len(mccq->len));
933 AMAP_SET_BITS(struct amap_mcc_context_be, cq_id, ctxt, cq->id);
934 }
5fb379ee 935
cc4ce020 936 /* Subscribe to Link State and Group 5 Events(bits 1 and 5 set) */
fe6d2a38 937 req->async_event_bitmap[0] = cpu_to_le32(0x00000022);
5fb379ee
SP		 938 be_dws_cpu_to_le(ctxt, sizeof(req->context));
939
940 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
941
b31c50a7 942 status = be_mbox_notify_wait(adapter);
5fb379ee
SP		 943 if (!status) {
944 struct be_cmd_resp_mcc_create *resp = embedded_payload(wrb);
945 mccq->id = le16_to_cpu(resp->id);
946 mccq->created = true;
947 }
2984961c 948 mutex_unlock(&adapter->mbox_lock);
6b7c5b94
SP		 949
950 return status;
951}
952
34b1ef04
SK		 953int be_cmd_mccq_org_create(struct be_adapter *adapter,
954 struct be_queue_info *mccq,
955 struct be_queue_info *cq)
956{
957 struct be_mcc_wrb *wrb;
958 struct be_cmd_req_mcc_create *req;
959 struct be_dma_mem *q_mem = &mccq->dma_mem;
960 void *ctxt;
961 int status;
962
963 if (mutex_lock_interruptible(&adapter->mbox_lock))
964 return -1;
965
966 wrb = wrb_from_mbox(adapter);
967 req = embedded_payload(wrb);
968 ctxt = &req->context;
969
106df1e3
SK		 970 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
971 OPCODE_COMMON_MCC_CREATE, sizeof(*req), wrb, NULL);
34b1ef04
SK		 972
973 req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
974
975 AMAP_SET_BITS(struct amap_mcc_context_be, valid, ctxt, 1);
976 AMAP_SET_BITS(struct amap_mcc_context_be, ring_size, ctxt,
977 be_encoded_q_len(mccq->len));
978 AMAP_SET_BITS(struct amap_mcc_context_be, cq_id, ctxt, cq->id);
979
980 be_dws_cpu_to_le(ctxt, sizeof(req->context));
981
982 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
983
984 status = be_mbox_notify_wait(adapter);
985 if (!status) {
986 struct be_cmd_resp_mcc_create *resp = embedded_payload(wrb);
987 mccq->id = le16_to_cpu(resp->id);
988 mccq->created = true;
989 }
990
991 mutex_unlock(&adapter->mbox_lock);
992 return status;
993}
994
995int be_cmd_mccq_create(struct be_adapter *adapter,
996 struct be_queue_info *mccq,
997 struct be_queue_info *cq)
998{
999 int status;
1000
1001 status = be_cmd_mccq_ext_create(adapter, mccq, cq);
1002 if (status && !lancer_chip(adapter)) {
1003 dev_warn(&adapter->pdev->dev, "Upgrade to F/W ver 2.102.235.0 "
1004 "or newer to avoid conflicting priorities between NIC "
1005 "and FCoE traffic");
1006 status = be_cmd_mccq_org_create(adapter, mccq, cq);
1007 }
1008 return status;
1009}
1010
8788fdc2 1011int be_cmd_txq_create(struct be_adapter *adapter,
6b7c5b94
SP		 1012 struct be_queue_info *txq,
1013 struct be_queue_info *cq)
1014{
b31c50a7
SP		 1015 struct be_mcc_wrb *wrb;
1016 struct be_cmd_req_eth_tx_create *req;
6b7c5b94 1017 struct be_dma_mem *q_mem = &txq->dma_mem;
b31c50a7 1018 void *ctxt;
6b7c5b94 1019 int status;
6b7c5b94 1020
293c4a7d
PR		 1021 spin_lock_bh(&adapter->mcc_lock);
1022
1023 wrb = wrb_from_mccq(adapter);
1024 if (!wrb) {
1025 status = -EBUSY;
1026 goto err;
1027 }
b31c50a7 1028
b31c50a7
SP		 1029 req = embedded_payload(wrb);
1030 ctxt = &req->context;
6b7c5b94 1031
106df1e3
SK		 1032 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1033 OPCODE_ETH_TX_CREATE, sizeof(*req), wrb, NULL);
6b7c5b94 1034
8b7756ca
PR		 1035 if (lancer_chip(adapter)) {
1036 req->hdr.version = 1;
1037 AMAP_SET_BITS(struct amap_tx_context, if_id, ctxt,
1038 adapter->if_handle);
1039 }
1040
6b7c5b94
SP		 1041 req->num_pages = PAGES_4K_SPANNED(q_mem->va, q_mem->size);
1042 req->ulp_num = BE_ULP1_NUM;
1043 req->type = BE_ETH_TX_RING_TYPE_STANDARD;
1044
b31c50a7
SP		 1045 AMAP_SET_BITS(struct amap_tx_context, tx_ring_size, ctxt,
1046 be_encoded_q_len(txq->len));
6b7c5b94
SP		 1047 AMAP_SET_BITS(struct amap_tx_context, ctx_valid, ctxt, 1);
1048 AMAP_SET_BITS(struct amap_tx_context, cq_id_send, ctxt, cq->id);
1049
1050 be_dws_cpu_to_le(ctxt, sizeof(req->context));
1051
1052 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
1053
293c4a7d 1054 status = be_mcc_notify_wait(adapter);
6b7c5b94
SP		 1055 if (!status) {
1056 struct be_cmd_resp_eth_tx_create *resp = embedded_payload(wrb);
1057 txq->id = le16_to_cpu(resp->cid);
1058 txq->created = true;
1059 }
b31c50a7 1060
293c4a7d
PR		 1061err:
1062 spin_unlock_bh(&adapter->mcc_lock);
6b7c5b94
SP		 1063
1064 return status;
1065}
1066
482c9e79 1067/* Uses MCC */
8788fdc2 1068int be_cmd_rxq_create(struct be_adapter *adapter,
6b7c5b94 1069 struct be_queue_info *rxq, u16 cq_id, u16 frag_size,
10ef9ab4 1070 u32 if_id, u32 rss, u8 *rss_id)
6b7c5b94 1071{
b31c50a7
SP		 1072 struct be_mcc_wrb *wrb;
1073 struct be_cmd_req_eth_rx_create *req;
6b7c5b94
SP		 1074 struct be_dma_mem *q_mem = &rxq->dma_mem;
1075 int status;
1076
482c9e79 1077 spin_lock_bh(&adapter->mcc_lock);
b31c50a7 1078
482c9e79
SP		 1079 wrb = wrb_from_mccq(adapter);
1080 if (!wrb) {
1081 status = -EBUSY;
1082 goto err;
1083 }
b31c50a7 1084 req = embedded_payload(wrb);
6b7c5b94 1085
106df1e3
SK		 1086 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1087 OPCODE_ETH_RX_CREATE, sizeof(*req), wrb, NULL);
6b7c5b94
SP		 1088
1089 req->cq_id = cpu_to_le16(cq_id);
1090 req->frag_size = fls(frag_size) - 1;
1091 req->num_pages = 2;
1092 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
1093 req->interface_id = cpu_to_le32(if_id);
10ef9ab4 1094 req->max_frame_size = cpu_to_le16(BE_MAX_JUMBO_FRAME_SIZE);
6b7c5b94
SP		 1095 req->rss_queue = cpu_to_le32(rss);
1096
482c9e79 1097 status = be_mcc_notify_wait(adapter);
6b7c5b94
SP		 1098 if (!status) {
1099 struct be_cmd_resp_eth_rx_create *resp = embedded_payload(wrb);
1100 rxq->id = le16_to_cpu(resp->id);
1101 rxq->created = true;
3abcdeda 1102 *rss_id = resp->rss_id;
6b7c5b94 1103 }
b31c50a7 1104
482c9e79
SP		 1105err:
1106 spin_unlock_bh(&adapter->mcc_lock);
6b7c5b94
SP		 1107 return status;
1108}
1109
b31c50a7
SP		 1110/* Generic destroyer function for all types of queues
1111 * Uses Mbox
1112 */
8788fdc2 1113int be_cmd_q_destroy(struct be_adapter *adapter, struct be_queue_info *q,
6b7c5b94
SP		 1114 int queue_type)
1115{
b31c50a7
SP		 1116 struct be_mcc_wrb *wrb;
1117 struct be_cmd_req_q_destroy *req;
6b7c5b94
SP		 1118 u8 subsys = 0, opcode = 0;
1119 int status;
1120
2984961c
IV		 1121 if (mutex_lock_interruptible(&adapter->mbox_lock))
1122 return -1;
6b7c5b94 1123
b31c50a7
SP		 1124 wrb = wrb_from_mbox(adapter);
1125 req = embedded_payload(wrb);
1126
6b7c5b94
SP		 1127 switch (queue_type) {
1128 case QTYPE_EQ:
1129 subsys = CMD_SUBSYSTEM_COMMON;
1130 opcode = OPCODE_COMMON_EQ_DESTROY;
1131 break;
1132 case QTYPE_CQ:
1133 subsys = CMD_SUBSYSTEM_COMMON;
1134 opcode = OPCODE_COMMON_CQ_DESTROY;
1135 break;
1136 case QTYPE_TXQ:
1137 subsys = CMD_SUBSYSTEM_ETH;
1138 opcode = OPCODE_ETH_TX_DESTROY;
1139 break;
1140 case QTYPE_RXQ:
1141 subsys = CMD_SUBSYSTEM_ETH;
1142 opcode = OPCODE_ETH_RX_DESTROY;
1143 break;
5fb379ee
SP		 1144 case QTYPE_MCCQ:
1145 subsys = CMD_SUBSYSTEM_COMMON;
1146 opcode = OPCODE_COMMON_MCC_DESTROY;
1147 break;
6b7c5b94 1148 default:
5f0b849e 1149 BUG();
6b7c5b94 1150 }
d744b44e 1151
106df1e3
SK		 1152 be_wrb_cmd_hdr_prepare(&req->hdr, subsys, opcode, sizeof(*req), wrb,
1153 NULL);
6b7c5b94
SP		 1154 req->id = cpu_to_le16(q->id);
1155
b31c50a7 1156 status = be_mbox_notify_wait(adapter);
482c9e79
SP		 1157 if (!status)
1158 q->created = false;
5f0b849e 1159
2984961c 1160 mutex_unlock(&adapter->mbox_lock);
482c9e79
SP		 1161 return status;
1162}
6b7c5b94 1163
482c9e79
SP		 1164/* Uses MCC */
1165int be_cmd_rxq_destroy(struct be_adapter *adapter, struct be_queue_info *q)
1166{
1167 struct be_mcc_wrb *wrb;
1168 struct be_cmd_req_q_destroy *req;
1169 int status;
1170
1171 spin_lock_bh(&adapter->mcc_lock);
1172
1173 wrb = wrb_from_mccq(adapter);
1174 if (!wrb) {
1175 status = -EBUSY;
1176 goto err;
1177 }
1178 req = embedded_payload(wrb);
1179
106df1e3
SK		 1180 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1181 OPCODE_ETH_RX_DESTROY, sizeof(*req), wrb, NULL);
482c9e79
SP		 1182 req->id = cpu_to_le16(q->id);
1183
1184 status = be_mcc_notify_wait(adapter);
1185 if (!status)
1186 q->created = false;
1187
1188err:
1189 spin_unlock_bh(&adapter->mcc_lock);
6b7c5b94
SP		 1190 return status;
1191}
1192
b31c50a7 1193/* Create an rx filtering policy configuration on an i/f
f9449ab7 1194 * Uses MCCQ
b31c50a7 1195 */
73d540f2 1196int be_cmd_if_create(struct be_adapter *adapter, u32 cap_flags, u32 en_flags,
1578e777 1197 u32 *if_handle, u32 domain)
6b7c5b94 1198{
b31c50a7
SP		 1199 struct be_mcc_wrb *wrb;
1200 struct be_cmd_req_if_create *req;
6b7c5b94
SP		 1201 int status;
1202
f9449ab7 1203 spin_lock_bh(&adapter->mcc_lock);
b31c50a7 1204
f9449ab7
SP		 1205 wrb = wrb_from_mccq(adapter);
1206 if (!wrb) {
1207 status = -EBUSY;
1208 goto err;
1209 }
b31c50a7 1210 req = embedded_payload(wrb);
6b7c5b94 1211
106df1e3
SK		 1212 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1213 OPCODE_COMMON_NTWK_INTERFACE_CREATE, sizeof(*req), wrb, NULL);
ba343c77 1214 req->hdr.domain = domain;
73d540f2
SP		 1215 req->capability_flags = cpu_to_le32(cap_flags);
1216 req->enable_flags = cpu_to_le32(en_flags);
1578e777
PR		 1217
1218 req->pmac_invalid = true;
6b7c5b94 1219
f9449ab7 1220 status = be_mcc_notify_wait(adapter);
6b7c5b94
SP		 1221 if (!status) {
1222 struct be_cmd_resp_if_create *resp = embedded_payload(wrb);
1223 *if_handle = le32_to_cpu(resp->interface_id);
6b7c5b94
SP		 1224 }
1225
f9449ab7
SP		 1226err:
1227 spin_unlock_bh(&adapter->mcc_lock);
6b7c5b94
SP		 1228 return status;
1229}
1230
f9449ab7 1231/* Uses MCCQ */
30128031 1232int be_cmd_if_destroy(struct be_adapter *adapter, int interface_id, u32 domain)
6b7c5b94 1233{
b31c50a7
SP		 1234 struct be_mcc_wrb *wrb;
1235 struct be_cmd_req_if_destroy *req;
6b7c5b94
SP		 1236 int status;
1237
30128031 1238 if (interface_id == -1)
f9449ab7 1239 return 0;
b31c50a7 1240
f9449ab7
SP		 1241 spin_lock_bh(&adapter->mcc_lock);
1242
1243 wrb = wrb_from_mccq(adapter);
1244 if (!wrb) {
1245 status = -EBUSY;
1246 goto err;
1247 }
b31c50a7 1248 req = embedded_payload(wrb);
6b7c5b94 1249
106df1e3
SK		 1250 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1251 OPCODE_COMMON_NTWK_INTERFACE_DESTROY, sizeof(*req), wrb, NULL);
658681f7 1252 req->hdr.domain = domain;
6b7c5b94 1253 req->interface_id = cpu_to_le32(interface_id);
b31c50a7 1254
f9449ab7
SP		 1255 status = be_mcc_notify_wait(adapter);
1256err:
1257 spin_unlock_bh(&adapter->mcc_lock);
6b7c5b94
SP		 1258 return status;
1259}
1260
1261/* Get stats is a non embedded command: the request is not embedded inside
1262 * WRB but is a separate dma memory block
b31c50a7 1263 * Uses asynchronous MCC
6b7c5b94 1264 */
8788fdc2 1265int be_cmd_get_stats(struct be_adapter *adapter, struct be_dma_mem *nonemb_cmd)
6b7c5b94 1266{
b31c50a7 1267 struct be_mcc_wrb *wrb;
89a88ab8 1268 struct be_cmd_req_hdr *hdr;
713d0394 1269 int status = 0;
6b7c5b94 1270
b31c50a7 1271 spin_lock_bh(&adapter->mcc_lock);
6b7c5b94 1272
b31c50a7 1273 wrb = wrb_from_mccq(adapter);
713d0394
SP		 1274 if (!wrb) {
1275 status = -EBUSY;
1276 goto err;
1277 }
89a88ab8 1278 hdr = nonemb_cmd->va;
6b7c5b94 1279
106df1e3
SK		 1280 be_wrb_cmd_hdr_prepare(hdr, CMD_SUBSYSTEM_ETH,
1281 OPCODE_ETH_GET_STATISTICS, nonemb_cmd->size, wrb, nonemb_cmd);
89a88ab8
AK		 1282
1283 if (adapter->generation == BE_GEN3)
1284 hdr->version = 1;
1285
b31c50a7 1286 be_mcc_notify(adapter);
b2aebe6d 1287 adapter->stats_cmd_sent = true;
6b7c5b94 1288
713d0394 1289err:
b31c50a7 1290 spin_unlock_bh(&adapter->mcc_lock);
713d0394 1291 return status;
6b7c5b94
SP		 1292}
1293
005d5696
SX		 1294/* Lancer Stats */
1295int lancer_cmd_get_pport_stats(struct be_adapter *adapter,
1296 struct be_dma_mem *nonemb_cmd)
1297{
1298
1299 struct be_mcc_wrb *wrb;
1300 struct lancer_cmd_req_pport_stats *req;
005d5696
SX		 1301 int status = 0;
1302
1303 spin_lock_bh(&adapter->mcc_lock);
1304
1305 wrb = wrb_from_mccq(adapter);
1306 if (!wrb) {
1307 status = -EBUSY;
1308 goto err;
1309 }
1310 req = nonemb_cmd->va;
005d5696 1311
106df1e3
SK		 1312 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1313 OPCODE_ETH_GET_PPORT_STATS, nonemb_cmd->size, wrb,
1314 nonemb_cmd);
005d5696 1315
d51ebd33 1316 req->cmd_params.params.pport_num = cpu_to_le16(adapter->hba_port_num);
005d5696
SX		 1317 req->cmd_params.params.reset_stats = 0;
1318
005d5696
SX		 1319 be_mcc_notify(adapter);
1320 adapter->stats_cmd_sent = true;
1321
1322err:
1323 spin_unlock_bh(&adapter->mcc_lock);
1324 return status;
1325}
1326
b31c50a7 1327/* Uses synchronous mcc */
ea172a01 1328int be_cmd_link_status_query(struct be_adapter *adapter, u8 *mac_speed,
b236916a 1329 u16 *link_speed, u8 *link_status, u32 dom)
6b7c5b94 1330{
b31c50a7
SP		 1331 struct be_mcc_wrb *wrb;
1332 struct be_cmd_req_link_status *req;
6b7c5b94
SP		 1333 int status;
1334
b31c50a7
SP		 1335 spin_lock_bh(&adapter->mcc_lock);
1336
b236916a
AK		 1337 if (link_status)
1338 *link_status = LINK_DOWN;
1339
b31c50a7 1340 wrb = wrb_from_mccq(adapter);
713d0394
SP		 1341 if (!wrb) {
1342 status = -EBUSY;
1343 goto err;
1344 }
b31c50a7 1345 req = embedded_payload(wrb);
a8f447bd 1346
57cd80d4
PR		 1347 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1348 OPCODE_COMMON_NTWK_LINK_STATUS_QUERY, sizeof(*req), wrb, NULL);
1349
b236916a 1350 if (adapter->generation == BE_GEN3 || lancer_chip(adapter))
daad6167
PR		 1351 req->hdr.version = 1;
1352
57cd80d4 1353 req->hdr.domain = dom;
6b7c5b94 1354
b31c50a7 1355 status = be_mcc_notify_wait(adapter);
6b7c5b94
SP		 1356 if (!status) {
1357 struct be_cmd_resp_link_status *resp = embedded_payload(wrb);
0388f251 1358 if (resp->mac_speed != PHY_LINK_SPEED_ZERO) {
b236916a
AK		 1359 if (link_speed)
1360 *link_speed = le16_to_cpu(resp->link_speed);
f9449ab7
SP		 1361 if (mac_speed)
1362 *mac_speed = resp->mac_speed;
0388f251 1363 }
b236916a
AK		 1364 if (link_status)
1365 *link_status = resp->logical_link_status;
6b7c5b94
SP		 1366 }
1367
713d0394 1368err:
b31c50a7 1369 spin_unlock_bh(&adapter->mcc_lock);
6b7c5b94
SP		 1370 return status;
1371}
1372
609ff3bb
AK		 1373/* Uses synchronous mcc */
1374int be_cmd_get_die_temperature(struct be_adapter *adapter)
1375{
1376 struct be_mcc_wrb *wrb;
1377 struct be_cmd_req_get_cntl_addnl_attribs *req;
1378 int status;
1379
1380 spin_lock_bh(&adapter->mcc_lock);
1381
1382 wrb = wrb_from_mccq(adapter);
1383 if (!wrb) {
1384 status = -EBUSY;
1385 goto err;
1386 }
1387 req = embedded_payload(wrb);
1388
106df1e3
SK		 1389 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1390 OPCODE_COMMON_GET_CNTL_ADDITIONAL_ATTRIBUTES, sizeof(*req),
1391 wrb, NULL);
609ff3bb 1392
3de09455 1393 be_mcc_notify(adapter);
609ff3bb
AK		 1394
1395err:
1396 spin_unlock_bh(&adapter->mcc_lock);
1397 return status;
1398}
1399
311fddc7
SK		 1400/* Uses synchronous mcc */
1401int be_cmd_get_reg_len(struct be_adapter *adapter, u32 *log_size)
1402{
1403 struct be_mcc_wrb *wrb;
1404 struct be_cmd_req_get_fat *req;
1405 int status;
1406
1407 spin_lock_bh(&adapter->mcc_lock);
1408
1409 wrb = wrb_from_mccq(adapter);
1410 if (!wrb) {
1411 status = -EBUSY;
1412 goto err;
1413 }
1414 req = embedded_payload(wrb);
1415
106df1e3
SK		 1416 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1417 OPCODE_COMMON_MANAGE_FAT, sizeof(*req), wrb, NULL);
311fddc7
SK		 1418 req->fat_operation = cpu_to_le32(QUERY_FAT);
1419 status = be_mcc_notify_wait(adapter);
1420 if (!status) {
1421 struct be_cmd_resp_get_fat *resp = embedded_payload(wrb);
1422 if (log_size && resp->log_size)
fe2a70ee
SK		 1423 *log_size = le32_to_cpu(resp->log_size) -
1424 sizeof(u32);
311fddc7
SK		 1425 }
1426err:
1427 spin_unlock_bh(&adapter->mcc_lock);
1428 return status;
1429}
1430
1431void be_cmd_get_regs(struct be_adapter *adapter, u32 buf_len, void *buf)
1432{
1433 struct be_dma_mem get_fat_cmd;
1434 struct be_mcc_wrb *wrb;
1435 struct be_cmd_req_get_fat *req;
fe2a70ee
SK		 1436 u32 offset = 0, total_size, buf_size,
1437 log_offset = sizeof(u32), payload_len;
311fddc7
SK		 1438 int status;
1439
1440 if (buf_len == 0)
1441 return;
1442
1443 total_size = buf_len;
1444
fe2a70ee
SK		 1445 get_fat_cmd.size = sizeof(struct be_cmd_req_get_fat) + 60*1024;
1446 get_fat_cmd.va = pci_alloc_consistent(adapter->pdev,
1447 get_fat_cmd.size,
1448 &get_fat_cmd.dma);
1449 if (!get_fat_cmd.va) {
1450 status = -ENOMEM;
1451 dev_err(&adapter->pdev->dev,
1452 "Memory allocation failure while retrieving FAT data\n");
1453 return;
1454 }
1455
311fddc7
SK		 1456 spin_lock_bh(&adapter->mcc_lock);
1457
311fddc7
SK		 1458 while (total_size) {
1459 buf_size = min(total_size, (u32)60*1024);
1460 total_size -= buf_size;
1461
fe2a70ee
SK		 1462 wrb = wrb_from_mccq(adapter);
1463 if (!wrb) {
1464 status = -EBUSY;
311fddc7
SK		 1465 goto err;
1466 }
1467 req = get_fat_cmd.va;
311fddc7 1468
fe2a70ee 1469 payload_len = sizeof(struct be_cmd_req_get_fat) + buf_size;
106df1e3
SK		 1470 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1471 OPCODE_COMMON_MANAGE_FAT, payload_len, wrb,
1472 &get_fat_cmd);
311fddc7
SK		 1473
1474 req->fat_operation = cpu_to_le32(RETRIEVE_FAT);
1475 req->read_log_offset = cpu_to_le32(log_offset);
1476 req->read_log_length = cpu_to_le32(buf_size);
1477 req->data_buffer_size = cpu_to_le32(buf_size);
1478
1479 status = be_mcc_notify_wait(adapter);
1480 if (!status) {
1481 struct be_cmd_resp_get_fat *resp = get_fat_cmd.va;
1482 memcpy(buf + offset,
1483 resp->data_buffer,
92aa9214 1484 le32_to_cpu(resp->read_log_length));
fe2a70ee 1485 } else {
311fddc7 1486 dev_err(&adapter->pdev->dev, "FAT Table Retrieve error\n");
fe2a70ee
SK		 1487 goto err;
1488 }
311fddc7
SK		 1489 offset += buf_size;
1490 log_offset += buf_size;
1491 }
1492err:
fe2a70ee
SK		 1493 pci_free_consistent(adapter->pdev, get_fat_cmd.size,
1494 get_fat_cmd.va,
1495 get_fat_cmd.dma);
311fddc7
SK		 1496 spin_unlock_bh(&adapter->mcc_lock);
1497}
1498
04b71175
SP		 1499/* Uses synchronous mcc */
1500int be_cmd_get_fw_ver(struct be_adapter *adapter, char *fw_ver,
1501 char *fw_on_flash)
6b7c5b94 1502{
b31c50a7
SP		 1503 struct be_mcc_wrb *wrb;
1504 struct be_cmd_req_get_fw_version *req;
6b7c5b94
SP		 1505 int status;
1506
04b71175 1507 spin_lock_bh(&adapter->mcc_lock);
b31c50a7 1508
04b71175
SP		 1509 wrb = wrb_from_mccq(adapter);
1510 if (!wrb) {
1511 status = -EBUSY;
1512 goto err;
1513 }
6b7c5b94 1514
04b71175 1515 req = embedded_payload(wrb);
6b7c5b94 1516
106df1e3
SK		 1517 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1518 OPCODE_COMMON_GET_FW_VERSION, sizeof(*req), wrb, NULL);
04b71175 1519 status = be_mcc_notify_wait(adapter);
6b7c5b94
SP		 1520 if (!status) {
1521 struct be_cmd_resp_get_fw_version *resp = embedded_payload(wrb);
04b71175
SP		 1522 strcpy(fw_ver, resp->firmware_version_string);
1523 if (fw_on_flash)
1524 strcpy(fw_on_flash, resp->fw_on_flash_version_string);
6b7c5b94 1525 }
04b71175
SP		 1526err:
1527 spin_unlock_bh(&adapter->mcc_lock);
6b7c5b94
SP		 1528 return status;
1529}
1530
b31c50a7
SP		 1531/* set the EQ delay interval of an EQ to specified value
1532 * Uses async mcc
1533 */
8788fdc2 1534int be_cmd_modify_eqd(struct be_adapter *adapter, u32 eq_id, u32 eqd)
6b7c5b94 1535{
b31c50a7
SP		 1536 struct be_mcc_wrb *wrb;
1537 struct be_cmd_req_modify_eq_delay *req;
713d0394 1538 int status = 0;
6b7c5b94 1539
b31c50a7
SP		 1540 spin_lock_bh(&adapter->mcc_lock);
1541
1542 wrb = wrb_from_mccq(adapter);
713d0394
SP		 1543 if (!wrb) {
1544 status = -EBUSY;
1545 goto err;
1546 }
b31c50a7 1547 req = embedded_payload(wrb);
6b7c5b94 1548
106df1e3
SK		 1549 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1550 OPCODE_COMMON_MODIFY_EQ_DELAY, sizeof(*req), wrb, NULL);
6b7c5b94
SP		 1551
1552 req->num_eq = cpu_to_le32(1);
1553 req->delay[0].eq_id = cpu_to_le32(eq_id);
1554 req->delay[0].phase = 0;
1555 req->delay[0].delay_multiplier = cpu_to_le32(eqd);
1556
b31c50a7 1557 be_mcc_notify(adapter);
6b7c5b94 1558
713d0394 1559err:
b31c50a7 1560 spin_unlock_bh(&adapter->mcc_lock);
713d0394 1561 return status;
6b7c5b94
SP		 1562}
1563
b31c50a7 1564/* Uses sycnhronous mcc */
8788fdc2 1565int be_cmd_vlan_config(struct be_adapter *adapter, u32 if_id, u16 *vtag_array,
6b7c5b94
SP		 1566 u32 num, bool untagged, bool promiscuous)
1567{
b31c50a7
SP		 1568 struct be_mcc_wrb *wrb;
1569 struct be_cmd_req_vlan_config *req;
6b7c5b94
SP		 1570 int status;
1571
b31c50a7
SP		 1572 spin_lock_bh(&adapter->mcc_lock);
1573
1574 wrb = wrb_from_mccq(adapter);
713d0394
SP		 1575 if (!wrb) {
1576 status = -EBUSY;
1577 goto err;
1578 }
b31c50a7 1579 req = embedded_payload(wrb);
6b7c5b94 1580
106df1e3
SK		 1581 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1582 OPCODE_COMMON_NTWK_VLAN_CONFIG, sizeof(*req), wrb, NULL);
6b7c5b94
SP		 1583
1584 req->interface_id = if_id;
1585 req->promiscuous = promiscuous;
1586 req->untagged = untagged;
1587 req->num_vlan = num;
1588 if (!promiscuous) {
1589 memcpy(req->normal_vlan, vtag_array,
1590 req->num_vlan * sizeof(vtag_array[0]));
1591 }
1592
b31c50a7 1593 status = be_mcc_notify_wait(adapter);
6b7c5b94 1594
713d0394 1595err:
b31c50a7 1596 spin_unlock_bh(&adapter->mcc_lock);
6b7c5b94
SP		 1597 return status;
1598}
1599
5b8821b7 1600int be_cmd_rx_filter(struct be_adapter *adapter, u32 flags, u32 value)
6b7c5b94 1601{
6ac7b687 1602 struct be_mcc_wrb *wrb;
5b8821b7
SP		 1603 struct be_dma_mem *mem = &adapter->rx_filter;
1604 struct be_cmd_req_rx_filter *req = mem->va;
e7b909a6 1605 int status;
6b7c5b94 1606
8788fdc2 1607 spin_lock_bh(&adapter->mcc_lock);
6ac7b687 1608
b31c50a7 1609 wrb = wrb_from_mccq(adapter);
713d0394
SP		 1610 if (!wrb) {
1611 status = -EBUSY;
1612 goto err;
1613 }
5b8821b7 1614 memset(req, 0, sizeof(*req));
106df1e3
SK		 1615 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1616 OPCODE_COMMON_NTWK_RX_FILTER, sizeof(*req),
1617 wrb, mem);
6b7c5b94 1618
5b8821b7
SP		 1619 req->if_id = cpu_to_le32(adapter->if_handle);
1620 if (flags & IFF_PROMISC) {
1621 req->if_flags_mask = cpu_to_le32(BE_IF_FLAGS_PROMISCUOUS |
1622 BE_IF_FLAGS_VLAN_PROMISCUOUS);
1623 if (value == ON)
1624 req->if_flags = cpu_to_le32(BE_IF_FLAGS_PROMISCUOUS |
8e7d3f68 1625 BE_IF_FLAGS_VLAN_PROMISCUOUS);
5b8821b7
SP		 1626 } else if (flags & IFF_ALLMULTI) {
1627 req->if_flags_mask = req->if_flags =
8e7d3f68 1628 cpu_to_le32(BE_IF_FLAGS_MCAST_PROMISCUOUS);
5b8821b7 1629 } else {
22bedad3 1630 struct netdev_hw_addr *ha;
5b8821b7 1631 int i = 0;
24307eef 1632
8e7d3f68
SP		 1633 req->if_flags_mask = req->if_flags =
1634 cpu_to_le32(BE_IF_FLAGS_MULTICAST);
1610c79f
PR		 1635
1636 /* Reset mcast promisc mode if already set by setting mask
1637 * and not setting flags field
1638 */
0b13fb45
PR		 1639 if (!lancer_chip(adapter) || be_physfn(adapter))
1640 req->if_flags_mask |=
1610c79f
PR		 1641 cpu_to_le32(BE_IF_FLAGS_MCAST_PROMISCUOUS);
1642
016f97b1 1643 req->mcast_num = cpu_to_le32(netdev_mc_count(adapter->netdev));
5b8821b7
SP		 1644 netdev_for_each_mc_addr(ha, adapter->netdev)
1645 memcpy(req->mcast_mac[i++].byte, ha->addr, ETH_ALEN);
6b7c5b94
SP		 1646 }
1647
0d1d5875 1648 status = be_mcc_notify_wait(adapter);
713d0394 1649err:
8788fdc2 1650 spin_unlock_bh(&adapter->mcc_lock);
e7b909a6 1651 return status;
6b7c5b94
SP		 1652}
1653
b31c50a7 1654/* Uses synchrounous mcc */
8788fdc2 1655int be_cmd_set_flow_control(struct be_adapter *adapter, u32 tx_fc, u32 rx_fc)
6b7c5b94 1656{
b31c50a7
SP		 1657 struct be_mcc_wrb *wrb;
1658 struct be_cmd_req_set_flow_control *req;
6b7c5b94
SP		 1659 int status;
1660
b31c50a7 1661 spin_lock_bh(&adapter->mcc_lock);
6b7c5b94 1662
b31c50a7 1663 wrb = wrb_from_mccq(adapter);
713d0394
SP		 1664 if (!wrb) {
1665 status = -EBUSY;
1666 goto err;
1667 }
b31c50a7 1668 req = embedded_payload(wrb);
6b7c5b94 1669
106df1e3
SK		 1670 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1671 OPCODE_COMMON_SET_FLOW_CONTROL, sizeof(*req), wrb, NULL);
6b7c5b94
SP		 1672
1673 req->tx_flow_control = cpu_to_le16((u16)tx_fc);
1674 req->rx_flow_control = cpu_to_le16((u16)rx_fc);
1675
b31c50a7 1676 status = be_mcc_notify_wait(adapter);
6b7c5b94 1677
713d0394 1678err:
b31c50a7 1679 spin_unlock_bh(&adapter->mcc_lock);
6b7c5b94
SP		 1680 return status;
1681}
1682
b31c50a7 1683/* Uses sycn mcc */
8788fdc2 1684int be_cmd_get_flow_control(struct be_adapter *adapter, u32 *tx_fc, u32 *rx_fc)
6b7c5b94 1685{
b31c50a7
SP		 1686 struct be_mcc_wrb *wrb;
1687 struct be_cmd_req_get_flow_control *req;
6b7c5b94
SP		 1688 int status;
1689
b31c50a7 1690 spin_lock_bh(&adapter->mcc_lock);
6b7c5b94 1691
b31c50a7 1692 wrb = wrb_from_mccq(adapter);
713d0394
SP		 1693 if (!wrb) {
1694 status = -EBUSY;
1695 goto err;
1696 }
b31c50a7 1697 req = embedded_payload(wrb);
6b7c5b94 1698
106df1e3
SK		 1699 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1700 OPCODE_COMMON_GET_FLOW_CONTROL, sizeof(*req), wrb, NULL);
6b7c5b94 1701
b31c50a7 1702 status = be_mcc_notify_wait(adapter);
6b7c5b94
SP		 1703 if (!status) {
1704 struct be_cmd_resp_get_flow_control *resp =
1705 embedded_payload(wrb);
1706 *tx_fc = le16_to_cpu(resp->tx_flow_control);
1707 *rx_fc = le16_to_cpu(resp->rx_flow_control);
1708 }
1709
713d0394 1710err:
b31c50a7 1711 spin_unlock_bh(&adapter->mcc_lock);
6b7c5b94
SP		 1712 return status;
1713}
1714
b31c50a7 1715/* Uses mbox */
3abcdeda
SP		 1716int be_cmd_query_fw_cfg(struct be_adapter *adapter, u32 *port_num,
1717 u32 *mode, u32 *caps)
6b7c5b94 1718{
b31c50a7
SP		 1719 struct be_mcc_wrb *wrb;
1720 struct be_cmd_req_query_fw_cfg *req;
6b7c5b94
SP		 1721 int status;
1722
2984961c
IV		 1723 if (mutex_lock_interruptible(&adapter->mbox_lock))
1724 return -1;
6b7c5b94 1725
b31c50a7
SP		 1726 wrb = wrb_from_mbox(adapter);
1727 req = embedded_payload(wrb);
6b7c5b94 1728
106df1e3
SK		 1729 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1730 OPCODE_COMMON_QUERY_FIRMWARE_CONFIG, sizeof(*req), wrb, NULL);
6b7c5b94 1731
b31c50a7 1732 status = be_mbox_notify_wait(adapter);
6b7c5b94
SP		 1733 if (!status) {
1734 struct be_cmd_resp_query_fw_cfg *resp = embedded_payload(wrb);
1735 *port_num = le32_to_cpu(resp->phys_port);
3486be29 1736 *mode = le32_to_cpu(resp->function_mode);
3abcdeda 1737 *caps = le32_to_cpu(resp->function_caps);
6b7c5b94
SP		 1738 }
1739
2984961c 1740 mutex_unlock(&adapter->mbox_lock);
6b7c5b94
SP		 1741 return status;
1742}
14074eab 1743
b31c50a7 1744/* Uses mbox */
14074eab 1745int be_cmd_reset_function(struct be_adapter *adapter)
1746{
b31c50a7
SP		 1747 struct be_mcc_wrb *wrb;
1748 struct be_cmd_req_hdr *req;
14074eab 1749 int status;
1750
bf99e50d
PR		 1751 if (lancer_chip(adapter)) {
1752 status = lancer_wait_ready(adapter);
1753 if (!status) {
1754 iowrite32(SLI_PORT_CONTROL_IP_MASK,
1755 adapter->db + SLIPORT_CONTROL_OFFSET);
1756 status = lancer_test_and_set_rdy_state(adapter);
1757 }
1758 if (status) {
1759 dev_err(&adapter->pdev->dev,
1760 "Adapter in non recoverable error\n");
1761 }
1762 return status;
1763 }
1764
2984961c
IV		 1765 if (mutex_lock_interruptible(&adapter->mbox_lock))
1766 return -1;
14074eab 1767
b31c50a7
SP		 1768 wrb = wrb_from_mbox(adapter);
1769 req = embedded_payload(wrb);
14074eab 1770
106df1e3
SK		 1771 be_wrb_cmd_hdr_prepare(req, CMD_SUBSYSTEM_COMMON,
1772 OPCODE_COMMON_FUNCTION_RESET, sizeof(*req), wrb, NULL);
14074eab 1773
b31c50a7 1774 status = be_mbox_notify_wait(adapter);
14074eab 1775
2984961c 1776 mutex_unlock(&adapter->mbox_lock);
14074eab 1777 return status;
1778}
84517482 1779
3abcdeda
SP		 1780int be_cmd_rss_config(struct be_adapter *adapter, u8 *rsstable, u16 table_size)
1781{
1782 struct be_mcc_wrb *wrb;
1783 struct be_cmd_req_rss_config *req;
65f8584e
PR		 1784 u32 myhash[10] = {0x15d43fa5, 0x2534685a, 0x5f87693a, 0x5668494e,
1785 0x33cf6a53, 0x383334c6, 0x76ac4257, 0x59b242b2,
1786 0x3ea83c02, 0x4a110304};
3abcdeda
SP		 1787 int status;
1788
2984961c
IV		 1789 if (mutex_lock_interruptible(&adapter->mbox_lock))
1790 return -1;
3abcdeda
SP		 1791
1792 wrb = wrb_from_mbox(adapter);
1793 req = embedded_payload(wrb);
1794
106df1e3
SK		 1795 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1796 OPCODE_ETH_RSS_CONFIG, sizeof(*req), wrb, NULL);
3abcdeda
SP		 1797
1798 req->if_id = cpu_to_le32(adapter->if_handle);
1ca7ba92
SP		 1799 req->enable_rss = cpu_to_le16(RSS_ENABLE_TCP_IPV4 | RSS_ENABLE_IPV4 |
1800 RSS_ENABLE_TCP_IPV6 | RSS_ENABLE_IPV6);
d3bd3a5e
PR		 1801
1802 if (lancer_chip(adapter) || skyhawk_chip(adapter)) {
1803 req->hdr.version = 1;
1804 req->enable_rss |= cpu_to_le16(RSS_ENABLE_UDP_IPV4 |
1805 RSS_ENABLE_UDP_IPV6);
1806 }
1807
3abcdeda
SP		 1808 req->cpu_table_size_log2 = cpu_to_le16(fls(table_size) - 1);
1809 memcpy(req->cpu_table, rsstable, table_size);
1810 memcpy(req->hash, myhash, sizeof(myhash));
1811 be_dws_cpu_to_le(req->hash, sizeof(req->hash));
1812
1813 status = be_mbox_notify_wait(adapter);
1814
2984961c 1815 mutex_unlock(&adapter->mbox_lock);
3abcdeda
SP		 1816 return status;
1817}
1818
fad9ab2c
SB		 1819/* Uses sync mcc */
1820int be_cmd_set_beacon_state(struct be_adapter *adapter, u8 port_num,
1821 u8 bcn, u8 sts, u8 state)
1822{
1823 struct be_mcc_wrb *wrb;
1824 struct be_cmd_req_enable_disable_beacon *req;
1825 int status;
1826
1827 spin_lock_bh(&adapter->mcc_lock);
1828
1829 wrb = wrb_from_mccq(adapter);
713d0394
SP		 1830 if (!wrb) {
1831 status = -EBUSY;
1832 goto err;
1833 }
fad9ab2c
SB		 1834 req = embedded_payload(wrb);
1835
106df1e3
SK		 1836 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1837 OPCODE_COMMON_ENABLE_DISABLE_BEACON, sizeof(*req), wrb, NULL);
fad9ab2c
SB		 1838
1839 req->port_num = port_num;
1840 req->beacon_state = state;
1841 req->beacon_duration = bcn;
1842 req->status_duration = sts;
1843
1844 status = be_mcc_notify_wait(adapter);
1845
713d0394 1846err:
fad9ab2c
SB		 1847 spin_unlock_bh(&adapter->mcc_lock);
1848 return status;
1849}
1850
1851/* Uses sync mcc */
1852int be_cmd_get_beacon_state(struct be_adapter *adapter, u8 port_num, u32 *state)
1853{
1854 struct be_mcc_wrb *wrb;
1855 struct be_cmd_req_get_beacon_state *req;
1856 int status;
1857
1858 spin_lock_bh(&adapter->mcc_lock);
1859
1860 wrb = wrb_from_mccq(adapter);
713d0394
SP		 1861 if (!wrb) {
1862 status = -EBUSY;
1863 goto err;
1864 }
fad9ab2c
SB		 1865 req = embedded_payload(wrb);
1866
106df1e3
SK		 1867 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1868 OPCODE_COMMON_GET_BEACON_STATE, sizeof(*req), wrb, NULL);
fad9ab2c
SB		 1869
1870 req->port_num = port_num;
1871
1872 status = be_mcc_notify_wait(adapter);
1873 if (!status) {
1874 struct be_cmd_resp_get_beacon_state *resp =
1875 embedded_payload(wrb);
1876 *state = resp->beacon_state;
1877 }
1878
713d0394 1879err:
fad9ab2c
SB		 1880 spin_unlock_bh(&adapter->mcc_lock);
1881 return status;
1882}
1883
485bf569 1884int lancer_cmd_write_object(struct be_adapter *adapter, struct be_dma_mem *cmd,
f67ef7ba
PR		 1885 u32 data_size, u32 data_offset,
1886 const char *obj_name, u32 *data_written,
1887 u8 *change_status, u8 *addn_status)
485bf569
SN		 1888{
1889 struct be_mcc_wrb *wrb;
1890 struct lancer_cmd_req_write_object *req;
1891 struct lancer_cmd_resp_write_object *resp;
1892 void *ctxt = NULL;
1893 int status;
1894
1895 spin_lock_bh(&adapter->mcc_lock);
1896 adapter->flash_status = 0;
1897
1898 wrb = wrb_from_mccq(adapter);
1899 if (!wrb) {
1900 status = -EBUSY;
1901 goto err_unlock;
1902 }
1903
1904 req = embedded_payload(wrb);
1905
106df1e3 1906 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
485bf569 1907 OPCODE_COMMON_WRITE_OBJECT,
106df1e3
SK		 1908 sizeof(struct lancer_cmd_req_write_object), wrb,
1909 NULL);
485bf569
SN		 1910
1911 ctxt = &req->context;
1912 AMAP_SET_BITS(struct amap_lancer_write_obj_context,
1913 write_length, ctxt, data_size);
1914
1915 if (data_size == 0)
1916 AMAP_SET_BITS(struct amap_lancer_write_obj_context,
1917 eof, ctxt, 1);
1918 else
1919 AMAP_SET_BITS(struct amap_lancer_write_obj_context,
1920 eof, ctxt, 0);
1921
1922 be_dws_cpu_to_le(ctxt, sizeof(req->context));
1923 req->write_offset = cpu_to_le32(data_offset);
1924 strcpy(req->object_name, obj_name);
1925 req->descriptor_count = cpu_to_le32(1);
1926 req->buf_len = cpu_to_le32(data_size);
1927 req->addr_low = cpu_to_le32((cmd->dma +
1928 sizeof(struct lancer_cmd_req_write_object))
1929 & 0xFFFFFFFF);
1930 req->addr_high = cpu_to_le32(upper_32_bits(cmd->dma +
1931 sizeof(struct lancer_cmd_req_write_object)));
1932
1933 be_mcc_notify(adapter);
1934 spin_unlock_bh(&adapter->mcc_lock);
1935
1936 if (!wait_for_completion_timeout(&adapter->flash_compl,
804c7515 1937 msecs_to_jiffies(30000)))
485bf569
SN		 1938 status = -1;
1939 else
1940 status = adapter->flash_status;
1941
1942 resp = embedded_payload(wrb);
f67ef7ba 1943 if (!status) {
485bf569 1944 *data_written = le32_to_cpu(resp->actual_write_len);
f67ef7ba
PR		 1945 *change_status = resp->change_status;
1946 } else {
485bf569 1947 *addn_status = resp->additional_status;
f67ef7ba 1948 }
485bf569
SN		 1949
1950 return status;
1951
1952err_unlock:
1953 spin_unlock_bh(&adapter->mcc_lock);
1954 return status;
1955}
1956
de49bd5a
PR		 1957int lancer_cmd_read_object(struct be_adapter *adapter, struct be_dma_mem *cmd,
1958 u32 data_size, u32 data_offset, const char *obj_name,
1959 u32 *data_read, u32 *eof, u8 *addn_status)
1960{
1961 struct be_mcc_wrb *wrb;
1962 struct lancer_cmd_req_read_object *req;
1963 struct lancer_cmd_resp_read_object *resp;
1964 int status;
1965
1966 spin_lock_bh(&adapter->mcc_lock);
1967
1968 wrb = wrb_from_mccq(adapter);
1969 if (!wrb) {
1970 status = -EBUSY;
1971 goto err_unlock;
1972 }
1973
1974 req = embedded_payload(wrb);
1975
1976 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1977 OPCODE_COMMON_READ_OBJECT,
1978 sizeof(struct lancer_cmd_req_read_object), wrb,
1979 NULL);
1980
1981 req->desired_read_len = cpu_to_le32(data_size);
1982 req->read_offset = cpu_to_le32(data_offset);
1983 strcpy(req->object_name, obj_name);
1984 req->descriptor_count = cpu_to_le32(1);
1985 req->buf_len = cpu_to_le32(data_size);
1986 req->addr_low = cpu_to_le32((cmd->dma & 0xFFFFFFFF));
1987 req->addr_high = cpu_to_le32(upper_32_bits(cmd->dma));
1988
1989 status = be_mcc_notify_wait(adapter);
1990
1991 resp = embedded_payload(wrb);
1992 if (!status) {
1993 *data_read = le32_to_cpu(resp->actual_read_len);
1994 *eof = le32_to_cpu(resp->eof);
1995 } else {
1996 *addn_status = resp->additional_status;
1997 }
1998
1999err_unlock:
2000 spin_unlock_bh(&adapter->mcc_lock);
2001 return status;
2002}
2003
84517482
AK		 2004int be_cmd_write_flashrom(struct be_adapter *adapter, struct be_dma_mem *cmd,
2005 u32 flash_type, u32 flash_opcode, u32 buf_size)
2006{
b31c50a7 2007 struct be_mcc_wrb *wrb;
3f0d4560 2008 struct be_cmd_write_flashrom *req;
84517482
AK		 2009 int status;
2010
b31c50a7 2011 spin_lock_bh(&adapter->mcc_lock);
dd131e76 2012 adapter->flash_status = 0;
b31c50a7
SP		 2013
2014 wrb = wrb_from_mccq(adapter);
713d0394
SP		 2015 if (!wrb) {
2016 status = -EBUSY;
2892d9c2 2017 goto err_unlock;
713d0394
SP		 2018 }
2019 req = cmd->va;
84517482 2020
106df1e3
SK		 2021 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2022 OPCODE_COMMON_WRITE_FLASHROM, cmd->size, wrb, cmd);
84517482
AK		 2023
2024 req->params.op_type = cpu_to_le32(flash_type);
2025 req->params.op_code = cpu_to_le32(flash_opcode);
2026 req->params.data_buf_size = cpu_to_le32(buf_size);
2027
dd131e76
SB		 2028 be_mcc_notify(adapter);
2029 spin_unlock_bh(&adapter->mcc_lock);
2030
2031 if (!wait_for_completion_timeout(&adapter->flash_compl,
e2edb7d5 2032 msecs_to_jiffies(40000)))
dd131e76
SB		 2033 status = -1;
2034 else
2035 status = adapter->flash_status;
84517482 2036
2892d9c2
DC		 2037 return status;
2038
2039err_unlock:
2040 spin_unlock_bh(&adapter->mcc_lock);
84517482
AK		 2041 return status;
2042}
fa9a6fed 2043
3f0d4560
AK		 2044int be_cmd_get_flash_crc(struct be_adapter *adapter, u8 *flashed_crc,
2045 int offset)
fa9a6fed
SB		 2046{
2047 struct be_mcc_wrb *wrb;
2048 struct be_cmd_write_flashrom *req;
2049 int status;
2050
2051 spin_lock_bh(&adapter->mcc_lock);
2052
2053 wrb = wrb_from_mccq(adapter);
713d0394
SP		 2054 if (!wrb) {
2055 status = -EBUSY;
2056 goto err;
2057 }
fa9a6fed
SB		 2058 req = embedded_payload(wrb);
2059
106df1e3
SK		 2060 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2061 OPCODE_COMMON_READ_FLASHROM, sizeof(*req)+4, wrb, NULL);
fa9a6fed 2062
c165541e 2063 req->params.op_type = cpu_to_le32(OPTYPE_REDBOOT);
fa9a6fed 2064 req->params.op_code = cpu_to_le32(FLASHROM_OPER_REPORT);
8b93b710
AK		 2065 req->params.offset = cpu_to_le32(offset);
2066 req->params.data_buf_size = cpu_to_le32(0x4);
fa9a6fed
SB		 2067
2068 status = be_mcc_notify_wait(adapter);
2069 if (!status)
2070 memcpy(flashed_crc, req->params.data_buf, 4);
2071
713d0394 2072err:
fa9a6fed
SB		 2073 spin_unlock_bh(&adapter->mcc_lock);
2074 return status;
2075}
71d8d1b5 2076
c196b02c 2077int be_cmd_enable_magic_wol(struct be_adapter *adapter, u8 *mac,
71d8d1b5
AK		 2078 struct be_dma_mem *nonemb_cmd)
2079{
2080 struct be_mcc_wrb *wrb;
2081 struct be_cmd_req_acpi_wol_magic_config *req;
71d8d1b5
AK		 2082 int status;
2083
2084 spin_lock_bh(&adapter->mcc_lock);
2085
2086 wrb = wrb_from_mccq(adapter);
2087 if (!wrb) {
2088 status = -EBUSY;
2089 goto err;
2090 }
2091 req = nonemb_cmd->va;
71d8d1b5 2092
106df1e3
SK		 2093 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
2094 OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG, sizeof(*req), wrb,
2095 nonemb_cmd);
71d8d1b5
AK		 2096 memcpy(req->magic_mac, mac, ETH_ALEN);
2097
71d8d1b5
AK		 2098 status = be_mcc_notify_wait(adapter);
2099
2100err:
2101 spin_unlock_bh(&adapter->mcc_lock);
2102 return status;
2103}
ff33a6e2 2104
fced9999
SB		 2105int be_cmd_set_loopback(struct be_adapter *adapter, u8 port_num,
2106 u8 loopback_type, u8 enable)
2107{
2108 struct be_mcc_wrb *wrb;
2109 struct be_cmd_req_set_lmode *req;
2110 int status;
2111
2112 spin_lock_bh(&adapter->mcc_lock);
2113
2114 wrb = wrb_from_mccq(adapter);
2115 if (!wrb) {
2116 status = -EBUSY;
2117 goto err;
2118 }
2119
2120 req = embedded_payload(wrb);
2121
106df1e3
SK		 2122 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
2123 OPCODE_LOWLEVEL_SET_LOOPBACK_MODE, sizeof(*req), wrb,
2124 NULL);
fced9999
SB		 2125
2126 req->src_port = port_num;
2127 req->dest_port = port_num;
2128 req->loopback_type = loopback_type;
2129 req->loopback_state = enable;
2130
2131 status = be_mcc_notify_wait(adapter);
2132err:
2133 spin_unlock_bh(&adapter->mcc_lock);
2134 return status;
2135}
2136
ff33a6e2
S		 2137int be_cmd_loopback_test(struct be_adapter *adapter, u32 port_num,
2138 u32 loopback_type, u32 pkt_size, u32 num_pkts, u64 pattern)
2139{
2140 struct be_mcc_wrb *wrb;
2141 struct be_cmd_req_loopback_test *req;
2142 int status;
2143
2144 spin_lock_bh(&adapter->mcc_lock);
2145
2146 wrb = wrb_from_mccq(adapter);
2147 if (!wrb) {
2148 status = -EBUSY;
2149 goto err;
2150 }
2151
2152 req = embedded_payload(wrb);
2153
106df1e3
SK		 2154 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
2155 OPCODE_LOWLEVEL_LOOPBACK_TEST, sizeof(*req), wrb, NULL);
3ffd0515 2156 req->hdr.timeout = cpu_to_le32(4);
ff33a6e2
S		 2157
2158 req->pattern = cpu_to_le64(pattern);
2159 req->src_port = cpu_to_le32(port_num);
2160 req->dest_port = cpu_to_le32(port_num);
2161 req->pkt_size = cpu_to_le32(pkt_size);
2162 req->num_pkts = cpu_to_le32(num_pkts);
2163 req->loopback_type = cpu_to_le32(loopback_type);
2164
2165 status = be_mcc_notify_wait(adapter);
2166 if (!status) {
2167 struct be_cmd_resp_loopback_test *resp = embedded_payload(wrb);
2168 status = le32_to_cpu(resp->status);
2169 }
2170
2171err:
2172 spin_unlock_bh(&adapter->mcc_lock);
2173 return status;
2174}
2175
2176int be_cmd_ddr_dma_test(struct be_adapter *adapter, u64 pattern,
2177 u32 byte_cnt, struct be_dma_mem *cmd)
2178{
2179 struct be_mcc_wrb *wrb;
2180 struct be_cmd_req_ddrdma_test *req;
ff33a6e2
S		 2181 int status;
2182 int i, j = 0;
2183
2184 spin_lock_bh(&adapter->mcc_lock);
2185
2186 wrb = wrb_from_mccq(adapter);
2187 if (!wrb) {
2188 status = -EBUSY;
2189 goto err;
2190 }
2191 req = cmd->va;
106df1e3
SK		 2192 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
2193 OPCODE_LOWLEVEL_HOST_DDR_DMA, cmd->size, wrb, cmd);
ff33a6e2
S		 2194
2195 req->pattern = cpu_to_le64(pattern);
2196 req->byte_count = cpu_to_le32(byte_cnt);
2197 for (i = 0; i < byte_cnt; i++) {
2198 req->snd_buff[i] = (u8)(pattern >> (j*8));
2199 j++;
2200 if (j > 7)
2201 j = 0;
2202 }
2203
2204 status = be_mcc_notify_wait(adapter);
2205
2206 if (!status) {
2207 struct be_cmd_resp_ddrdma_test *resp;
2208 resp = cmd->va;
2209 if ((memcmp(resp->rcv_buff, req->snd_buff, byte_cnt) != 0) ||
2210 resp->snd_err) {
2211 status = -1;
2212 }
2213 }
2214
2215err:
2216 spin_unlock_bh(&adapter->mcc_lock);
2217 return status;
2218}
368c0ca2 2219
c196b02c 2220int be_cmd_get_seeprom_data(struct be_adapter *adapter,
368c0ca2
SB		 2221 struct be_dma_mem *nonemb_cmd)
2222{
2223 struct be_mcc_wrb *wrb;
2224 struct be_cmd_req_seeprom_read *req;
2225 struct be_sge *sge;
2226 int status;
2227
2228 spin_lock_bh(&adapter->mcc_lock);
2229
2230 wrb = wrb_from_mccq(adapter);
e45ff01d
AK		 2231 if (!wrb) {
2232 status = -EBUSY;
2233 goto err;
2234 }
368c0ca2
SB		 2235 req = nonemb_cmd->va;
2236 sge = nonembedded_sgl(wrb);
2237
106df1e3
SK		 2238 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2239 OPCODE_COMMON_SEEPROM_READ, sizeof(*req), wrb,
2240 nonemb_cmd);
368c0ca2
SB		 2241
2242 status = be_mcc_notify_wait(adapter);
2243
e45ff01d 2244err:
368c0ca2
SB		 2245 spin_unlock_bh(&adapter->mcc_lock);
2246 return status;
2247}
ee3cb629 2248
42f11cf2 2249int be_cmd_get_phy_info(struct be_adapter *adapter)
ee3cb629
AK		 2250{
2251 struct be_mcc_wrb *wrb;
2252 struct be_cmd_req_get_phy_info *req;
306f1348 2253 struct be_dma_mem cmd;
ee3cb629
AK		 2254 int status;
2255
2256 spin_lock_bh(&adapter->mcc_lock);
2257
2258 wrb = wrb_from_mccq(adapter);
2259 if (!wrb) {
2260 status = -EBUSY;
2261 goto err;
2262 }
306f1348
SP		 2263 cmd.size = sizeof(struct be_cmd_req_get_phy_info);
2264 cmd.va = pci_alloc_consistent(adapter->pdev, cmd.size,
2265 &cmd.dma);
2266 if (!cmd.va) {
2267 dev_err(&adapter->pdev->dev, "Memory alloc failure\n");
2268 status = -ENOMEM;
2269 goto err;
2270 }
ee3cb629 2271
306f1348 2272 req = cmd.va;
ee3cb629 2273
106df1e3
SK		 2274 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2275 OPCODE_COMMON_GET_PHY_DETAILS, sizeof(*req),
2276 wrb, &cmd);
ee3cb629
AK		 2277
2278 status = be_mcc_notify_wait(adapter);
306f1348
SP		 2279 if (!status) {
2280 struct be_phy_info *resp_phy_info =
2281 cmd.va + sizeof(struct be_cmd_req_hdr);
42f11cf2
AK		 2282 adapter->phy.phy_type = le16_to_cpu(resp_phy_info->phy_type);
2283 adapter->phy.interface_type =
306f1348 2284 le16_to_cpu(resp_phy_info->interface_type);
42f11cf2
AK		 2285 adapter->phy.auto_speeds_supported =
2286 le16_to_cpu(resp_phy_info->auto_speeds_supported);
2287 adapter->phy.fixed_speeds_supported =
2288 le16_to_cpu(resp_phy_info->fixed_speeds_supported);
2289 adapter->phy.misc_params =
2290 le32_to_cpu(resp_phy_info->misc_params);
306f1348
SP		 2291 }
2292 pci_free_consistent(adapter->pdev, cmd.size,
2293 cmd.va, cmd.dma);
ee3cb629
AK		 2294err:
2295 spin_unlock_bh(&adapter->mcc_lock);
2296 return status;
2297}
e1d18735
AK		 2298
2299int be_cmd_set_qos(struct be_adapter *adapter, u32 bps, u32 domain)
2300{
2301 struct be_mcc_wrb *wrb;
2302 struct be_cmd_req_set_qos *req;
2303 int status;
2304
2305 spin_lock_bh(&adapter->mcc_lock);
2306
2307 wrb = wrb_from_mccq(adapter);
2308 if (!wrb) {
2309 status = -EBUSY;
2310 goto err;
2311 }
2312
2313 req = embedded_payload(wrb);
2314
106df1e3
SK		 2315 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2316 OPCODE_COMMON_SET_QOS, sizeof(*req), wrb, NULL);
e1d18735
AK		 2317
2318 req->hdr.domain = domain;
6bff57a7
AK		 2319 req->valid_bits = cpu_to_le32(BE_QOS_BITS_NIC);
2320 req->max_bps_nic = cpu_to_le32(bps);
e1d18735
AK		 2321
2322 status = be_mcc_notify_wait(adapter);
2323
2324err:
2325 spin_unlock_bh(&adapter->mcc_lock);
2326 return status;
2327}
9e1453c5
AK		 2328
2329int be_cmd_get_cntl_attributes(struct be_adapter *adapter)
2330{
2331 struct be_mcc_wrb *wrb;
2332 struct be_cmd_req_cntl_attribs *req;
2333 struct be_cmd_resp_cntl_attribs *resp;
9e1453c5
AK		 2334 int status;
2335 int payload_len = max(sizeof(*req), sizeof(*resp));
2336 struct mgmt_controller_attrib *attribs;
2337 struct be_dma_mem attribs_cmd;
2338
2339 memset(&attribs_cmd, 0, sizeof(struct be_dma_mem));
2340 attribs_cmd.size = sizeof(struct be_cmd_resp_cntl_attribs);
2341 attribs_cmd.va = pci_alloc_consistent(adapter->pdev, attribs_cmd.size,
2342 &attribs_cmd.dma);
2343 if (!attribs_cmd.va) {
2344 dev_err(&adapter->pdev->dev,
2345 "Memory allocation failure\n");
2346 return -ENOMEM;
2347 }
2348
2349 if (mutex_lock_interruptible(&adapter->mbox_lock))
2350 return -1;
2351
2352 wrb = wrb_from_mbox(adapter);
2353 if (!wrb) {
2354 status = -EBUSY;
2355 goto err;
2356 }
2357 req = attribs_cmd.va;
9e1453c5 2358
106df1e3
SK		 2359 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2360 OPCODE_COMMON_GET_CNTL_ATTRIBUTES, payload_len, wrb,
2361 &attribs_cmd);
9e1453c5
AK		 2362
2363 status = be_mbox_notify_wait(adapter);
2364 if (!status) {
43d620c8 2365 attribs = attribs_cmd.va + sizeof(struct be_cmd_resp_hdr);
9e1453c5
AK		 2366 adapter->hba_port_num = attribs->hba_attribs.phy_port;
2367 }
2368
2369err:
2370 mutex_unlock(&adapter->mbox_lock);
2371 pci_free_consistent(adapter->pdev, attribs_cmd.size, attribs_cmd.va,
2372 attribs_cmd.dma);
2373 return status;
2374}
2e588f84
SP		 2375
2376/* Uses mbox */
2dc1deb6 2377int be_cmd_req_native_mode(struct be_adapter *adapter)
2e588f84
SP		 2378{
2379 struct be_mcc_wrb *wrb;
2380 struct be_cmd_req_set_func_cap *req;
2381 int status;
2382
2383 if (mutex_lock_interruptible(&adapter->mbox_lock))
2384 return -1;
2385
2386 wrb = wrb_from_mbox(adapter);
2387 if (!wrb) {
2388 status = -EBUSY;
2389 goto err;
2390 }
2391
2392 req = embedded_payload(wrb);
2393
106df1e3
SK		 2394 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2395 OPCODE_COMMON_SET_DRIVER_FUNCTION_CAP, sizeof(*req), wrb, NULL);
2e588f84
SP		 2396
2397 req->valid_cap_flags = cpu_to_le32(CAPABILITY_SW_TIMESTAMPS |
2398 CAPABILITY_BE3_NATIVE_ERX_API);
2399 req->cap_flags = cpu_to_le32(CAPABILITY_BE3_NATIVE_ERX_API);
2400
2401 status = be_mbox_notify_wait(adapter);
2402 if (!status) {
2403 struct be_cmd_resp_set_func_cap *resp = embedded_payload(wrb);
2404 adapter->be3_native = le32_to_cpu(resp->cap_flags) &
2405 CAPABILITY_BE3_NATIVE_ERX_API;
2406 }
2407err:
2408 mutex_unlock(&adapter->mbox_lock);
2409 return status;
2410}
590c391d
PR		 2411
2412/* Uses synchronous MCCQ */
1578e777
PR		 2413int be_cmd_get_mac_from_list(struct be_adapter *adapter, u8 *mac,
2414 bool *pmac_id_active, u32 *pmac_id, u8 domain)
590c391d
PR		 2415{
2416 struct be_mcc_wrb *wrb;
2417 struct be_cmd_req_get_mac_list *req;
2418 int status;
2419 int mac_count;
e5e1ee89
PR		 2420 struct be_dma_mem get_mac_list_cmd;
2421 int i;
2422
2423 memset(&get_mac_list_cmd, 0, sizeof(struct be_dma_mem));
2424 get_mac_list_cmd.size = sizeof(struct be_cmd_resp_get_mac_list);
2425 get_mac_list_cmd.va = pci_alloc_consistent(adapter->pdev,
2426 get_mac_list_cmd.size,
2427 &get_mac_list_cmd.dma);
2428
2429 if (!get_mac_list_cmd.va) {
2430 dev_err(&adapter->pdev->dev,
2431 "Memory allocation failure during GET_MAC_LIST\n");
2432 return -ENOMEM;
2433 }
590c391d
PR		 2434
2435 spin_lock_bh(&adapter->mcc_lock);
2436
2437 wrb = wrb_from_mccq(adapter);
2438 if (!wrb) {
2439 status = -EBUSY;
e5e1ee89 2440 goto out;
590c391d 2441 }
e5e1ee89
PR		 2442
2443 req = get_mac_list_cmd.va;
590c391d
PR		 2444
2445 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2446 OPCODE_COMMON_GET_MAC_LIST, sizeof(*req),
e5e1ee89 2447 wrb, &get_mac_list_cmd);
590c391d
PR		 2448
2449 req->hdr.domain = domain;
e5e1ee89
PR		 2450 req->mac_type = MAC_ADDRESS_TYPE_NETWORK;
2451 req->perm_override = 1;
590c391d
PR		 2452
2453 status = be_mcc_notify_wait(adapter);
2454 if (!status) {
2455 struct be_cmd_resp_get_mac_list *resp =
e5e1ee89
PR		 2456 get_mac_list_cmd.va;
2457 mac_count = resp->true_mac_count + resp->pseudo_mac_count;
2458 /* Mac list returned could contain one or more active mac_ids
1578e777
PR		 2459 * or one or more true or pseudo permanant mac addresses.
2460 * If an active mac_id is present, return first active mac_id
2461 * found.
e5e1ee89 2462 */
590c391d 2463 for (i = 0; i < mac_count; i++) {
e5e1ee89
PR		 2464 struct get_list_macaddr *mac_entry;
2465 u16 mac_addr_size;
2466 u32 mac_id;
2467
2468 mac_entry = &resp->macaddr_list[i];
2469 mac_addr_size = le16_to_cpu(mac_entry->mac_addr_size);
2470 /* mac_id is a 32 bit value and mac_addr size
2471 * is 6 bytes
2472 */
2473 if (mac_addr_size == sizeof(u32)) {
2474 *pmac_id_active = true;
2475 mac_id = mac_entry->mac_addr_id.s_mac_id.mac_id;
2476 *pmac_id = le32_to_cpu(mac_id);
2477 goto out;
590c391d 2478 }
590c391d 2479 }
1578e777 2480 /* If no active mac_id found, return first mac addr */
e5e1ee89
PR		 2481 *pmac_id_active = false;
2482 memcpy(mac, resp->macaddr_list[0].mac_addr_id.macaddr,
2483 ETH_ALEN);
590c391d
PR		 2484 }
2485
e5e1ee89 2486out:
590c391d 2487 spin_unlock_bh(&adapter->mcc_lock);
e5e1ee89
PR		 2488 pci_free_consistent(adapter->pdev, get_mac_list_cmd.size,
2489 get_mac_list_cmd.va, get_mac_list_cmd.dma);
590c391d
PR		 2490 return status;
2491}
2492
2493/* Uses synchronous MCCQ */
2494int be_cmd_set_mac_list(struct be_adapter *adapter, u8 *mac_array,
2495 u8 mac_count, u32 domain)
2496{
2497 struct be_mcc_wrb *wrb;
2498 struct be_cmd_req_set_mac_list *req;
2499 int status;
2500 struct be_dma_mem cmd;
2501
2502 memset(&cmd, 0, sizeof(struct be_dma_mem));
2503 cmd.size = sizeof(struct be_cmd_req_set_mac_list);
2504 cmd.va = dma_alloc_coherent(&adapter->pdev->dev, cmd.size,
2505 &cmd.dma, GFP_KERNEL);
2506 if (!cmd.va) {
2507 dev_err(&adapter->pdev->dev, "Memory alloc failure\n");
2508 return -ENOMEM;
2509 }
2510
2511 spin_lock_bh(&adapter->mcc_lock);
2512
2513 wrb = wrb_from_mccq(adapter);
2514 if (!wrb) {
2515 status = -EBUSY;
2516 goto err;
2517 }
2518
2519 req = cmd.va;
2520 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2521 OPCODE_COMMON_SET_MAC_LIST, sizeof(*req),
2522 wrb, &cmd);
2523
2524 req->hdr.domain = domain;
2525 req->mac_count = mac_count;
2526 if (mac_count)
2527 memcpy(req->mac, mac_array, ETH_ALEN*mac_count);
2528
2529 status = be_mcc_notify_wait(adapter);
2530
2531err:
2532 dma_free_coherent(&adapter->pdev->dev, cmd.size,
2533 cmd.va, cmd.dma);
2534 spin_unlock_bh(&adapter->mcc_lock);
2535 return status;
2536}
4762f6ce 2537
f1f3ee1b
AK		 2538int be_cmd_set_hsw_config(struct be_adapter *adapter, u16 pvid,
2539 u32 domain, u16 intf_id)
2540{
2541 struct be_mcc_wrb *wrb;
2542 struct be_cmd_req_set_hsw_config *req;
2543 void *ctxt;
2544 int status;
2545
2546 spin_lock_bh(&adapter->mcc_lock);
2547
2548 wrb = wrb_from_mccq(adapter);
2549 if (!wrb) {
2550 status = -EBUSY;
2551 goto err;
2552 }
2553
2554 req = embedded_payload(wrb);
2555 ctxt = &req->context;
2556
2557 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2558 OPCODE_COMMON_SET_HSW_CONFIG, sizeof(*req), wrb, NULL);
2559
2560 req->hdr.domain = domain;
2561 AMAP_SET_BITS(struct amap_set_hsw_context, interface_id, ctxt, intf_id);
2562 if (pvid) {
2563 AMAP_SET_BITS(struct amap_set_hsw_context, pvid_valid, ctxt, 1);
2564 AMAP_SET_BITS(struct amap_set_hsw_context, pvid, ctxt, pvid);
2565 }
2566
2567 be_dws_cpu_to_le(req->context, sizeof(req->context));
2568 status = be_mcc_notify_wait(adapter);
2569
2570err:
2571 spin_unlock_bh(&adapter->mcc_lock);
2572 return status;
2573}
2574
2575/* Get Hyper switch config */
2576int be_cmd_get_hsw_config(struct be_adapter *adapter, u16 *pvid,
2577 u32 domain, u16 intf_id)
2578{
2579 struct be_mcc_wrb *wrb;
2580 struct be_cmd_req_get_hsw_config *req;
2581 void *ctxt;
2582 int status;
2583 u16 vid;
2584
2585 spin_lock_bh(&adapter->mcc_lock);
2586
2587 wrb = wrb_from_mccq(adapter);
2588 if (!wrb) {
2589 status = -EBUSY;
2590 goto err;
2591 }
2592
2593 req = embedded_payload(wrb);
2594 ctxt = &req->context;
2595
2596 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2597 OPCODE_COMMON_GET_HSW_CONFIG, sizeof(*req), wrb, NULL);
2598
2599 req->hdr.domain = domain;
2600 AMAP_SET_BITS(struct amap_get_hsw_req_context, interface_id, ctxt,
2601 intf_id);
2602 AMAP_SET_BITS(struct amap_get_hsw_req_context, pvid_valid, ctxt, 1);
2603 be_dws_cpu_to_le(req->context, sizeof(req->context));
2604
2605 status = be_mcc_notify_wait(adapter);
2606 if (!status) {
2607 struct be_cmd_resp_get_hsw_config *resp =
2608 embedded_payload(wrb);
2609 be_dws_le_to_cpu(&resp->context,
2610 sizeof(resp->context));
2611 vid = AMAP_GET_BITS(struct amap_get_hsw_resp_context,
2612 pvid, &resp->context);
2613 *pvid = le16_to_cpu(vid);
2614 }
2615
2616err:
2617 spin_unlock_bh(&adapter->mcc_lock);
2618 return status;
2619}
2620
4762f6ce
AK		 2621int be_cmd_get_acpi_wol_cap(struct be_adapter *adapter)
2622{
2623 struct be_mcc_wrb *wrb;
2624 struct be_cmd_req_acpi_wol_magic_config_v1 *req;
2625 int status;
2626 int payload_len = sizeof(*req);
2627 struct be_dma_mem cmd;
2628
2629 memset(&cmd, 0, sizeof(struct be_dma_mem));
2630 cmd.size = sizeof(struct be_cmd_resp_acpi_wol_magic_config_v1);
2631 cmd.va = pci_alloc_consistent(adapter->pdev, cmd.size,
2632 &cmd.dma);
2633 if (!cmd.va) {
2634 dev_err(&adapter->pdev->dev,
2635 "Memory allocation failure\n");
2636 return -ENOMEM;
2637 }
2638
2639 if (mutex_lock_interruptible(&adapter->mbox_lock))
2640 return -1;
2641
2642 wrb = wrb_from_mbox(adapter);
2643 if (!wrb) {
2644 status = -EBUSY;
2645 goto err;
2646 }
2647
2648 req = cmd.va;
2649
2650 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
2651 OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG,
2652 payload_len, wrb, &cmd);
2653
2654 req->hdr.version = 1;
2655 req->query_options = BE_GET_WOL_CAP;
2656
2657 status = be_mbox_notify_wait(adapter);
2658 if (!status) {
2659 struct be_cmd_resp_acpi_wol_magic_config_v1 *resp;
2660 resp = (struct be_cmd_resp_acpi_wol_magic_config_v1 *) cmd.va;
2661
2662 /* the command could succeed misleadingly on old f/w
2663 * which is not aware of the V1 version. fake an error. */
2664 if (resp->hdr.response_length < payload_len) {
2665 status = -1;
2666 goto err;
2667 }
2668 adapter->wol_cap = resp->wol_settings;
2669 }
2670err:
2671 mutex_unlock(&adapter->mbox_lock);
2672 pci_free_consistent(adapter->pdev, cmd.size, cmd.va, cmd.dma);
2673 return status;
941a77d5
SK		 2674
2675}
2676int be_cmd_get_ext_fat_capabilites(struct be_adapter *adapter,
2677 struct be_dma_mem *cmd)
2678{
2679 struct be_mcc_wrb *wrb;
2680 struct be_cmd_req_get_ext_fat_caps *req;
2681 int status;
2682
2683 if (mutex_lock_interruptible(&adapter->mbox_lock))
2684 return -1;
2685
2686 wrb = wrb_from_mbox(adapter);
2687 if (!wrb) {
2688 status = -EBUSY;
2689 goto err;
2690 }
2691
2692 req = cmd->va;
2693 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2694 OPCODE_COMMON_GET_EXT_FAT_CAPABILITES,
2695 cmd->size, wrb, cmd);
2696 req->parameter_type = cpu_to_le32(1);
2697
2698 status = be_mbox_notify_wait(adapter);
2699err:
2700 mutex_unlock(&adapter->mbox_lock);
2701 return status;
2702}
2703
2704int be_cmd_set_ext_fat_capabilites(struct be_adapter *adapter,
2705 struct be_dma_mem *cmd,
2706 struct be_fat_conf_params *configs)
2707{
2708 struct be_mcc_wrb *wrb;
2709 struct be_cmd_req_set_ext_fat_caps *req;
2710 int status;
2711
2712 spin_lock_bh(&adapter->mcc_lock);
2713
2714 wrb = wrb_from_mccq(adapter);
2715 if (!wrb) {
2716 status = -EBUSY;
2717 goto err;
2718 }
2719
2720 req = cmd->va;
2721 memcpy(&req->set_params, configs, sizeof(struct be_fat_conf_params));
2722 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2723 OPCODE_COMMON_SET_EXT_FAT_CAPABILITES,
2724 cmd->size, wrb, cmd);
2725
2726 status = be_mcc_notify_wait(adapter);
2727err:
2728 spin_unlock_bh(&adapter->mcc_lock);
2729 return status;
4762f6ce 2730}
6a4ab669 2731
b4e32a71
PR		 2732int be_cmd_query_port_name(struct be_adapter *adapter, u8 *port_name)
2733{
2734 struct be_mcc_wrb *wrb;
2735 struct be_cmd_req_get_port_name *req;
2736 int status;
2737
2738 if (!lancer_chip(adapter)) {
2739 *port_name = adapter->hba_port_num + '0';
2740 return 0;
2741 }
2742
2743 spin_lock_bh(&adapter->mcc_lock);
2744
2745 wrb = wrb_from_mccq(adapter);
2746 if (!wrb) {
2747 status = -EBUSY;
2748 goto err;
2749 }
2750
2751 req = embedded_payload(wrb);
2752
2753 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2754 OPCODE_COMMON_GET_PORT_NAME, sizeof(*req), wrb,
2755 NULL);
2756 req->hdr.version = 1;
2757
2758 status = be_mcc_notify_wait(adapter);
2759 if (!status) {
2760 struct be_cmd_resp_get_port_name *resp = embedded_payload(wrb);
2761 *port_name = resp->port_name[adapter->hba_port_num];
2762 } else {
2763 *port_name = adapter->hba_port_num + '0';
2764 }
2765err:
2766 spin_unlock_bh(&adapter->mcc_lock);
2767 return status;
2768}
2769
6a4ab669
PP		 2770int be_roce_mcc_cmd(void *netdev_handle, void *wrb_payload,
2771 int wrb_payload_size, u16 *cmd_status, u16 *ext_status)
2772{
2773 struct be_adapter *adapter = netdev_priv(netdev_handle);
2774 struct be_mcc_wrb *wrb;
2775 struct be_cmd_req_hdr *hdr = (struct be_cmd_req_hdr *) wrb_payload;
2776 struct be_cmd_req_hdr *req;
2777 struct be_cmd_resp_hdr *resp;
2778 int status;
2779
2780 spin_lock_bh(&adapter->mcc_lock);
2781
2782 wrb = wrb_from_mccq(adapter);
2783 if (!wrb) {
2784 status = -EBUSY;
2785 goto err;
2786 }
2787 req = embedded_payload(wrb);
2788 resp = embedded_payload(wrb);
2789
2790 be_wrb_cmd_hdr_prepare(req, hdr->subsystem,
2791 hdr->opcode, wrb_payload_size, wrb, NULL);
2792 memcpy(req, wrb_payload, wrb_payload_size);
2793 be_dws_cpu_to_le(req, wrb_payload_size);
2794
2795 status = be_mcc_notify_wait(adapter);
2796 if (cmd_status)
2797 *cmd_status = (status & 0xffff);
2798 if (ext_status)
2799 *ext_status = 0;
2800 memcpy(wrb_payload, resp, sizeof(*resp) + resp->response_length);
2801 be_dws_le_to_cpu(wrb_payload, sizeof(*resp) + resp->response_length);
2802err:
2803 spin_unlock_bh(&adapter->mcc_lock);
2804 return status;
2805}
2806EXPORT_SYMBOL(be_roce_mcc_cmd);
Linux kernel - Deliverables
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