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be2net: remove duplicate code in be_cmd_rx_filter()
[deliverable/linux.git] / drivers / net / ethernet / emulex / benet / be_cmds.c
CommitLineData
6b7c5b94 1/*
40263820 2 * Copyright (C) 2005 - 2014 Emulex
6b7c5b94
SP		 3 * All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License version 2
7 * as published by the Free Software Foundation. The full GNU General
8 * Public License is included in this distribution in the file called COPYING.
9 *
10 * Contact Information:
d2145cde 11 * linux-drivers@emulex.com
6b7c5b94 12 *
d2145cde
AK		 13 * Emulex
14 * 3333 Susan Street
15 * Costa Mesa, CA 92626
6b7c5b94
SP		 16 */
17
6a4ab669 18#include <linux/module.h>
6b7c5b94 19#include "be.h"
8788fdc2 20#include "be_cmds.h"
6b7c5b94 21
f25b119c
PR		 22static struct be_cmd_priv_map cmd_priv_map[] = {
23 {
24 OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG,
25 CMD_SUBSYSTEM_ETH,
26 BE_PRIV_LNKMGMT | BE_PRIV_VHADM |
27 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC
28 },
29 {
30 OPCODE_COMMON_GET_FLOW_CONTROL,
31 CMD_SUBSYSTEM_COMMON,
32 BE_PRIV_LNKQUERY | BE_PRIV_VHADM |
33 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC
34 },
35 {
36 OPCODE_COMMON_SET_FLOW_CONTROL,
37 CMD_SUBSYSTEM_COMMON,
38 BE_PRIV_LNKMGMT | BE_PRIV_VHADM |
39 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC
40 },
41 {
42 OPCODE_ETH_GET_PPORT_STATS,
43 CMD_SUBSYSTEM_ETH,
44 BE_PRIV_LNKMGMT | BE_PRIV_VHADM |
45 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC
46 },
47 {
48 OPCODE_COMMON_GET_PHY_DETAILS,
49 CMD_SUBSYSTEM_COMMON,
50 BE_PRIV_LNKMGMT | BE_PRIV_VHADM |
51 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC
52 }
53};
54
a2cc4e0b 55static bool be_cmd_allowed(struct be_adapter *adapter, u8 opcode, u8 subsystem)
f25b119c
PR		 56{
57 int i;
58 int num_entries = sizeof(cmd_priv_map)/sizeof(struct be_cmd_priv_map);
59 u32 cmd_privileges = adapter->cmd_privileges;
60
61 for (i = 0; i < num_entries; i++)
62 if (opcode == cmd_priv_map[i].opcode &&
63 subsystem == cmd_priv_map[i].subsystem)
64 if (!(cmd_privileges & cmd_priv_map[i].priv_mask))
65 return false;
66
67 return true;
68}
69
3de09455
SK		 70static inline void *embedded_payload(struct be_mcc_wrb *wrb)
71{
72 return wrb->payload.embedded_payload;
73}
609ff3bb 74
8788fdc2 75static void be_mcc_notify(struct be_adapter *adapter)
5fb379ee 76{
8788fdc2 77 struct be_queue_info *mccq = &adapter->mcc_obj.q;
5fb379ee
SP		 78 u32 val = 0;
79
6589ade0 80 if (be_error(adapter))
7acc2087 81 return;
7acc2087 82
5fb379ee
SP		 83 val |= mccq->id & DB_MCCQ_RING_ID_MASK;
84 val |= 1 << DB_MCCQ_NUM_POSTED_SHIFT;
f3eb62d2
SP		 85
86 wmb();
8788fdc2 87 iowrite32(val, adapter->db + DB_MCCQ_OFFSET);
5fb379ee
SP		 88}
89
90/* To check if valid bit is set, check the entire word as we don't know
91 * the endianness of the data (old entry is host endian while a new entry is
92 * little endian) */
efd2e40a 93static inline bool be_mcc_compl_is_new(struct be_mcc_compl *compl)
5fb379ee 94{
9e9ff4b7
SP		 95 u32 flags;
96
5fb379ee 97 if (compl->flags != 0) {
9e9ff4b7
SP		 98 flags = le32_to_cpu(compl->flags);
99 if (flags & CQE_FLAGS_VALID_MASK) {
100 compl->flags = flags;
101 return true;
102 }
5fb379ee 103 }
9e9ff4b7 104 return false;
5fb379ee
SP		 105}
106
107/* Need to reset the entire word that houses the valid bit */
efd2e40a 108static inline void be_mcc_compl_use(struct be_mcc_compl *compl)
5fb379ee
SP		 109{
110 compl->flags = 0;
111}
112
652bf646
PR		 113static struct be_cmd_resp_hdr *be_decode_resp_hdr(u32 tag0, u32 tag1)
114{
115 unsigned long addr;
116
117 addr = tag1;
118 addr = ((addr << 16) << 16) | tag0;
119 return (void *)addr;
120}
121
4c60005f
KA		 122static bool be_skip_err_log(u8 opcode, u16 base_status, u16 addl_status)
123{
124 if (base_status == MCC_STATUS_NOT_SUPPORTED ||
125 base_status == MCC_STATUS_ILLEGAL_REQUEST ||
126 addl_status == MCC_ADDL_STATUS_TOO_MANY_INTERFACES ||
127 (opcode == OPCODE_COMMON_WRITE_FLASHROM &&
128 (base_status == MCC_STATUS_ILLEGAL_FIELD ||
129 addl_status == MCC_ADDL_STATUS_FLASH_IMAGE_CRC_MISMATCH)))
130 return true;
131 else
132 return false;
133}
134
559b633f
SP		 135/* Place holder for all the async MCC cmds wherein the caller is not in a busy
136 * loop (has not issued be_mcc_notify_wait())
137 */
138static void be_async_cmd_process(struct be_adapter *adapter,
139 struct be_mcc_compl *compl,
140 struct be_cmd_resp_hdr *resp_hdr)
141{
142 enum mcc_base_status base_status = base_status(compl->status);
143 u8 opcode = 0, subsystem = 0;
144
145 if (resp_hdr) {
146 opcode = resp_hdr->opcode;
147 subsystem = resp_hdr->subsystem;
148 }
149
150 if (opcode == OPCODE_LOWLEVEL_LOOPBACK_TEST &&
151 subsystem == CMD_SUBSYSTEM_LOWLEVEL) {
152 complete(&adapter->et_cmd_compl);
153 return;
154 }
155
156 if ((opcode == OPCODE_COMMON_WRITE_FLASHROM ||
157 opcode == OPCODE_COMMON_WRITE_OBJECT) &&
158 subsystem == CMD_SUBSYSTEM_COMMON) {
159 adapter->flash_status = compl->status;
160 complete(&adapter->et_cmd_compl);
161 return;
162 }
163
164 if ((opcode == OPCODE_ETH_GET_STATISTICS ||
165 opcode == OPCODE_ETH_GET_PPORT_STATS) &&
166 subsystem == CMD_SUBSYSTEM_ETH &&
167 base_status == MCC_STATUS_SUCCESS) {
168 be_parse_stats(adapter);
169 adapter->stats_cmd_sent = false;
170 return;
171 }
172
173 if (opcode == OPCODE_COMMON_GET_CNTL_ADDITIONAL_ATTRIBUTES &&
174 subsystem == CMD_SUBSYSTEM_COMMON) {
175 if (base_status == MCC_STATUS_SUCCESS) {
176 struct be_cmd_resp_get_cntl_addnl_attribs *resp =
177 (void *)resp_hdr;
178 adapter->drv_stats.be_on_die_temperature =
179 resp->on_die_temperature;
180 } else {
181 adapter->be_get_temp_freq = 0;
182 }
183 return;
184 }
185}
186
8788fdc2 187static int be_mcc_compl_process(struct be_adapter *adapter,
652bf646 188 struct be_mcc_compl *compl)
5fb379ee 189{
4c60005f
KA		 190 enum mcc_base_status base_status;
191 enum mcc_addl_status addl_status;
652bf646
PR		 192 struct be_cmd_resp_hdr *resp_hdr;
193 u8 opcode = 0, subsystem = 0;
5fb379ee
SP		 194
195 /* Just swap the status to host endian; mcc tag is opaquely copied
196 * from mcc_wrb */
197 be_dws_le_to_cpu(compl, 4);
198
4c60005f
KA		 199 base_status = base_status(compl->status);
200 addl_status = addl_status(compl->status);
96c9b2e4 201
652bf646 202 resp_hdr = be_decode_resp_hdr(compl->tag0, compl->tag1);
652bf646
PR		 203 if (resp_hdr) {
204 opcode = resp_hdr->opcode;
205 subsystem = resp_hdr->subsystem;
206 }
207
559b633f 208 be_async_cmd_process(adapter, compl, resp_hdr);
3de09455 209
559b633f
SP		 210 if (base_status != MCC_STATUS_SUCCESS &&
211 !be_skip_err_log(opcode, base_status, addl_status)) {
4c60005f 212 if (base_status == MCC_STATUS_UNAUTHORIZED_REQUEST) {
97f1d8cd 213 dev_warn(&adapter->pdev->dev,
522609f2 214 "VF is not privileged to issue opcode %d-%d\n",
97f1d8cd 215 opcode, subsystem);
2b3f291b 216 } else {
97f1d8cd
VV		 217 dev_err(&adapter->pdev->dev,
218 "opcode %d-%d failed:status %d-%d\n",
4c60005f 219 opcode, subsystem, base_status, addl_status);
2b3f291b 220 }
5fb379ee 221 }
4c60005f 222 return compl->status;
5fb379ee
SP		 223}
224
a8f447bd 225/* Link state evt is a string of bytes; no need for endian swapping */
8788fdc2 226static void be_async_link_state_process(struct be_adapter *adapter,
3acf19d9 227 struct be_mcc_compl *compl)
a8f447bd 228{
3acf19d9
SP		 229 struct be_async_event_link_state *evt =
230 (struct be_async_event_link_state *)compl;
231
b236916a 232 /* When link status changes, link speed must be re-queried from FW */
42f11cf2 233 adapter->phy.link_speed = -1;
b236916a 234
bdce2ad7
SR		 235 /* On BEx the FW does not send a separate link status
236 * notification for physical and logical link.
237 * On other chips just process the logical link
238 * status notification
239 */
240 if (!BEx_chip(adapter) &&
2e177a5c
PR		 241 !(evt->port_link_status & LOGICAL_LINK_STATUS_MASK))
242 return;
243
b236916a
AK		 244 /* For the initial link status do not rely on the ASYNC event as
245 * it may not be received in some cases.
246 */
247 if (adapter->flags & BE_FLAGS_LINK_STATUS_INIT)
bdce2ad7
SR		 248 be_link_status_update(adapter,
249 evt->port_link_status & LINK_STATUS_MASK);
a8f447bd
SP		 250}
251
cc4ce020
SK		 252/* Grp5 CoS Priority evt */
253static void be_async_grp5_cos_priority_process(struct be_adapter *adapter,
3acf19d9 254 struct be_mcc_compl *compl)
cc4ce020 255{
3acf19d9
SP		 256 struct be_async_event_grp5_cos_priority *evt =
257 (struct be_async_event_grp5_cos_priority *)compl;
258
cc4ce020
SK		 259 if (evt->valid) {
260 adapter->vlan_prio_bmap = evt->available_priority_bmap;
60964dd7 261 adapter->recommended_prio &= ~VLAN_PRIO_MASK;
cc4ce020
SK		 262 adapter->recommended_prio =
263 evt->reco_default_priority << VLAN_PRIO_SHIFT;
264 }
265}
266
323ff71e 267/* Grp5 QOS Speed evt: qos_link_speed is in units of 10 Mbps */
cc4ce020 268static void be_async_grp5_qos_speed_process(struct be_adapter *adapter,
3acf19d9 269 struct be_mcc_compl *compl)
cc4ce020 270{
3acf19d9
SP		 271 struct be_async_event_grp5_qos_link_speed *evt =
272 (struct be_async_event_grp5_qos_link_speed *)compl;
273
323ff71e
SP		 274 if (adapter->phy.link_speed >= 0 &&
275 evt->physical_port == adapter->port_num)
276 adapter->phy.link_speed = le16_to_cpu(evt->qos_link_speed) * 10;
cc4ce020
SK		 277}
278
3968fa1e
AK		 279/*Grp5 PVID evt*/
280static void be_async_grp5_pvid_state_process(struct be_adapter *adapter,
3acf19d9 281 struct be_mcc_compl *compl)
3968fa1e 282{
3acf19d9
SP		 283 struct be_async_event_grp5_pvid_state *evt =
284 (struct be_async_event_grp5_pvid_state *)compl;
285
bdac85b5 286 if (evt->enabled) {
939cf306 287 adapter->pvid = le16_to_cpu(evt->tag) & VLAN_VID_MASK;
bdac85b5
RN		 288 dev_info(&adapter->pdev->dev, "LPVID: %d\n", adapter->pvid);
289 } else {
3968fa1e 290 adapter->pvid = 0;
bdac85b5 291 }
3968fa1e
AK		 292}
293
cc4ce020 294static void be_async_grp5_evt_process(struct be_adapter *adapter,
3acf19d9 295 struct be_mcc_compl *compl)
cc4ce020 296{
3acf19d9
SP		 297 u8 event_type = (compl->flags >> ASYNC_EVENT_TYPE_SHIFT) &
298 ASYNC_EVENT_TYPE_MASK;
cc4ce020
SK		 299
300 switch (event_type) {
301 case ASYNC_EVENT_COS_PRIORITY:
3acf19d9
SP		 302 be_async_grp5_cos_priority_process(adapter, compl);
303 break;
cc4ce020 304 case ASYNC_EVENT_QOS_SPEED:
3acf19d9
SP		 305 be_async_grp5_qos_speed_process(adapter, compl);
306 break;
3968fa1e 307 case ASYNC_EVENT_PVID_STATE:
3acf19d9
SP		 308 be_async_grp5_pvid_state_process(adapter, compl);
309 break;
cc4ce020 310 default:
cc4ce020
SK		 311 break;
312 }
313}
314
bc0c3405 315static void be_async_dbg_evt_process(struct be_adapter *adapter,
3acf19d9 316 struct be_mcc_compl *cmp)
bc0c3405
AK		 317{
318 u8 event_type = 0;
504fbf1e 319 struct be_async_event_qnq *evt = (struct be_async_event_qnq *)cmp;
bc0c3405 320
3acf19d9
SP		 321 event_type = (cmp->flags >> ASYNC_EVENT_TYPE_SHIFT) &
322 ASYNC_EVENT_TYPE_MASK;
bc0c3405
AK		 323
324 switch (event_type) {
325 case ASYNC_DEBUG_EVENT_TYPE_QNQ:
326 if (evt->valid)
327 adapter->qnq_vid = le16_to_cpu(evt->vlan_tag);
328 adapter->flags |= BE_FLAGS_QNQ_ASYNC_EVT_RCVD;
329 break;
330 default:
05ccaa2b
VV		 331 dev_warn(&adapter->pdev->dev, "Unknown debug event 0x%x!\n",
332 event_type);
bc0c3405
AK		 333 break;
334 }
335}
336
3acf19d9 337static inline bool is_link_state_evt(u32 flags)
a8f447bd 338{
3acf19d9
SP		 339 return ((flags >> ASYNC_EVENT_CODE_SHIFT) & ASYNC_EVENT_CODE_MASK) ==
340 ASYNC_EVENT_CODE_LINK_STATE;
a8f447bd 341}
5fb379ee 342
3acf19d9 343static inline bool is_grp5_evt(u32 flags)
cc4ce020 344{
3acf19d9
SP		 345 return ((flags >> ASYNC_EVENT_CODE_SHIFT) & ASYNC_EVENT_CODE_MASK) ==
346 ASYNC_EVENT_CODE_GRP_5;
cc4ce020
SK		 347}
348
3acf19d9 349static inline bool is_dbg_evt(u32 flags)
bc0c3405 350{
3acf19d9
SP		 351 return ((flags >> ASYNC_EVENT_CODE_SHIFT) & ASYNC_EVENT_CODE_MASK) ==
352 ASYNC_EVENT_CODE_QNQ;
353}
354
355static void be_mcc_event_process(struct be_adapter *adapter,
356 struct be_mcc_compl *compl)
357{
358 if (is_link_state_evt(compl->flags))
359 be_async_link_state_process(adapter, compl);
360 else if (is_grp5_evt(compl->flags))
361 be_async_grp5_evt_process(adapter, compl);
362 else if (is_dbg_evt(compl->flags))
363 be_async_dbg_evt_process(adapter, compl);
bc0c3405
AK		 364}
365
efd2e40a 366static struct be_mcc_compl *be_mcc_compl_get(struct be_adapter *adapter)
5fb379ee 367{
8788fdc2 368 struct be_queue_info *mcc_cq = &adapter->mcc_obj.cq;
efd2e40a 369 struct be_mcc_compl *compl = queue_tail_node(mcc_cq);
5fb379ee
SP		 370
371 if (be_mcc_compl_is_new(compl)) {
372 queue_tail_inc(mcc_cq);
373 return compl;
374 }
375 return NULL;
376}
377
7a1e9b20
SP		 378void be_async_mcc_enable(struct be_adapter *adapter)
379{
380 spin_lock_bh(&adapter->mcc_cq_lock);
381
382 be_cq_notify(adapter, adapter->mcc_obj.cq.id, true, 0);
383 adapter->mcc_obj.rearm_cq = true;
384
385 spin_unlock_bh(&adapter->mcc_cq_lock);
386}
387
388void be_async_mcc_disable(struct be_adapter *adapter)
389{
a323d9bf
SP		 390 spin_lock_bh(&adapter->mcc_cq_lock);
391
7a1e9b20 392 adapter->mcc_obj.rearm_cq = false;
a323d9bf
SP		 393 be_cq_notify(adapter, adapter->mcc_obj.cq.id, false, 0);
394
395 spin_unlock_bh(&adapter->mcc_cq_lock);
7a1e9b20
SP		 396}
397
10ef9ab4 398int be_process_mcc(struct be_adapter *adapter)
5fb379ee 399{
efd2e40a 400 struct be_mcc_compl *compl;
10ef9ab4 401 int num = 0, status = 0;
7a1e9b20 402 struct be_mcc_obj *mcc_obj = &adapter->mcc_obj;
5fb379ee 403
072a9c48 404 spin_lock(&adapter->mcc_cq_lock);
3acf19d9 405
8788fdc2 406 while ((compl = be_mcc_compl_get(adapter))) {
a8f447bd 407 if (compl->flags & CQE_FLAGS_ASYNC_MASK) {
3acf19d9 408 be_mcc_event_process(adapter, compl);
b31c50a7 409 } else if (compl->flags & CQE_FLAGS_COMPLETED_MASK) {
3acf19d9
SP		 410 status = be_mcc_compl_process(adapter, compl);
411 atomic_dec(&mcc_obj->q.used);
5fb379ee
SP		 412 }
413 be_mcc_compl_use(compl);
414 num++;
415 }
b31c50a7 416
10ef9ab4
SP		 417 if (num)
418 be_cq_notify(adapter, mcc_obj->cq.id, mcc_obj->rearm_cq, num);
419
072a9c48 420 spin_unlock(&adapter->mcc_cq_lock);
10ef9ab4 421 return status;
5fb379ee
SP		 422}
423
6ac7b687 424/* Wait till no more pending mcc requests are present */
b31c50a7 425static int be_mcc_wait_compl(struct be_adapter *adapter)
6ac7b687 426{
b31c50a7 427#define mcc_timeout 120000 /* 12s timeout */
10ef9ab4 428 int i, status = 0;
f31e50a8
SP		 429 struct be_mcc_obj *mcc_obj = &adapter->mcc_obj;
430
6ac7b687 431 for (i = 0; i < mcc_timeout; i++) {
6589ade0
SP		 432 if (be_error(adapter))
433 return -EIO;
434
072a9c48 435 local_bh_disable();
10ef9ab4 436 status = be_process_mcc(adapter);
072a9c48 437 local_bh_enable();
b31c50a7 438
f31e50a8 439 if (atomic_read(&mcc_obj->q.used) == 0)
6ac7b687
SP		 440 break;
441 udelay(100);
442 }
b31c50a7 443 if (i == mcc_timeout) {
6589ade0
SP		 444 dev_err(&adapter->pdev->dev, "FW not responding\n");
445 adapter->fw_timeout = true;
652bf646 446 return -EIO;
b31c50a7 447 }
f31e50a8 448 return status;
6ac7b687
SP		 449}
450
451/* Notify MCC requests and wait for completion */
b31c50a7 452static int be_mcc_notify_wait(struct be_adapter *adapter)
6ac7b687 453{
652bf646
PR		 454 int status;
455 struct be_mcc_wrb *wrb;
456 struct be_mcc_obj *mcc_obj = &adapter->mcc_obj;
457 u16 index = mcc_obj->q.head;
458 struct be_cmd_resp_hdr *resp;
459
460 index_dec(&index, mcc_obj->q.len);
461 wrb = queue_index_node(&mcc_obj->q, index);
462
463 resp = be_decode_resp_hdr(wrb->tag0, wrb->tag1);
464
8788fdc2 465 be_mcc_notify(adapter);
652bf646
PR		 466
467 status = be_mcc_wait_compl(adapter);
468 if (status == -EIO)
469 goto out;
470
4c60005f
KA		 471 status = (resp->base_status |
472 ((resp->addl_status & CQE_ADDL_STATUS_MASK) <<
473 CQE_ADDL_STATUS_SHIFT));
652bf646
PR		 474out:
475 return status;
6ac7b687
SP		 476}
477
5f0b849e 478static int be_mbox_db_ready_wait(struct be_adapter *adapter, void __iomem *db)
6b7c5b94 479{
f25b03a7 480 int msecs = 0;
6b7c5b94
SP		 481 u32 ready;
482
483 do {
6589ade0
SP		 484 if (be_error(adapter))
485 return -EIO;
486
cf588477 487 ready = ioread32(db);
434b3648 488 if (ready == 0xffffffff)
cf588477 489 return -1;
cf588477
SP		 490
491 ready &= MPU_MAILBOX_DB_RDY_MASK;
6b7c5b94
SP		 492 if (ready)
493 break;
494
f25b03a7 495 if (msecs > 4000) {
6589ade0
SP		 496 dev_err(&adapter->pdev->dev, "FW not responding\n");
497 adapter->fw_timeout = true;
f67ef7ba 498 be_detect_error(adapter);
6b7c5b94
SP		 499 return -1;
500 }
501
1dbf53a2 502 msleep(1);
f25b03a7 503 msecs++;
6b7c5b94
SP		 504 } while (true);
505
506 return 0;
507}
508
509/*
510 * Insert the mailbox address into the doorbell in two steps
5fb379ee 511 * Polls on the mbox doorbell till a command completion (or a timeout) occurs
6b7c5b94 512 */
b31c50a7 513static int be_mbox_notify_wait(struct be_adapter *adapter)
6b7c5b94
SP		 514{
515 int status;
6b7c5b94 516 u32 val = 0;
8788fdc2
SP		 517 void __iomem *db = adapter->db + MPU_MAILBOX_DB_OFFSET;
518 struct be_dma_mem *mbox_mem = &adapter->mbox_mem;
6b7c5b94 519 struct be_mcc_mailbox *mbox = mbox_mem->va;
efd2e40a 520 struct be_mcc_compl *compl = &mbox->compl;
6b7c5b94 521
cf588477
SP		 522 /* wait for ready to be set */
523 status = be_mbox_db_ready_wait(adapter, db);
524 if (status != 0)
525 return status;
526
6b7c5b94
SP		 527 val |= MPU_MAILBOX_DB_HI_MASK;
528 /* at bits 2 - 31 place mbox dma addr msb bits 34 - 63 */
529 val |= (upper_32_bits(mbox_mem->dma) >> 2) << 2;
530 iowrite32(val, db);
531
532 /* wait for ready to be set */
5f0b849e 533 status = be_mbox_db_ready_wait(adapter, db);
6b7c5b94
SP		 534 if (status != 0)
535 return status;
536
537 val = 0;
6b7c5b94
SP		 538 /* at bits 2 - 31 place mbox dma addr lsb bits 4 - 33 */
539 val |= (u32)(mbox_mem->dma >> 4) << 2;
540 iowrite32(val, db);
541
5f0b849e 542 status = be_mbox_db_ready_wait(adapter, db);
6b7c5b94
SP		 543 if (status != 0)
544 return status;
545
5fb379ee 546 /* A cq entry has been made now */
efd2e40a
SP		 547 if (be_mcc_compl_is_new(compl)) {
548 status = be_mcc_compl_process(adapter, &mbox->compl);
549 be_mcc_compl_use(compl);
5fb379ee
SP		 550 if (status)
551 return status;
552 } else {
5f0b849e 553 dev_err(&adapter->pdev->dev, "invalid mailbox completion\n");
6b7c5b94
SP		 554 return -1;
555 }
5fb379ee 556 return 0;
6b7c5b94
SP		 557}
558
c5b3ad4c 559static u16 be_POST_stage_get(struct be_adapter *adapter)
6b7c5b94 560{
fe6d2a38
SP		 561 u32 sem;
562
c5b3ad4c
SP		 563 if (BEx_chip(adapter))
564 sem = ioread32(adapter->csr + SLIPORT_SEMAPHORE_OFFSET_BEx);
6b7c5b94 565 else
c5b3ad4c
SP		 566 pci_read_config_dword(adapter->pdev,
567 SLIPORT_SEMAPHORE_OFFSET_SH, &sem);
568
569 return sem & POST_STAGE_MASK;
6b7c5b94
SP		 570}
571
87f20c26 572static int lancer_wait_ready(struct be_adapter *adapter)
bf99e50d
PR		 573{
574#define SLIPORT_READY_TIMEOUT 30
575 u32 sliport_status;
e673244a 576 int i;
bf99e50d
PR		 577
578 for (i = 0; i < SLIPORT_READY_TIMEOUT; i++) {
579 sliport_status = ioread32(adapter->db + SLIPORT_STATUS_OFFSET);
580 if (sliport_status & SLIPORT_STATUS_RDY_MASK)
581 break;
582
583 msleep(1000);
584 }
585
586 if (i == SLIPORT_READY_TIMEOUT)
e673244a 587 return sliport_status ? : -1;
bf99e50d 588
e673244a 589 return 0;
bf99e50d
PR		 590}
591
67297ad8
PR		 592static bool lancer_provisioning_error(struct be_adapter *adapter)
593{
594 u32 sliport_status = 0, sliport_err1 = 0, sliport_err2 = 0;
03d28ffe 595
67297ad8
PR		 596 sliport_status = ioread32(adapter->db + SLIPORT_STATUS_OFFSET);
597 if (sliport_status & SLIPORT_STATUS_ERR_MASK) {
a2cc4e0b
SP		 598 sliport_err1 = ioread32(adapter->db + SLIPORT_ERROR1_OFFSET);
599 sliport_err2 = ioread32(adapter->db + SLIPORT_ERROR2_OFFSET);
67297ad8
PR		 600
601 if (sliport_err1 == SLIPORT_ERROR_NO_RESOURCE1 &&
602 sliport_err2 == SLIPORT_ERROR_NO_RESOURCE2)
603 return true;
604 }
605 return false;
606}
607
bf99e50d
PR		 608int lancer_test_and_set_rdy_state(struct be_adapter *adapter)
609{
610 int status;
611 u32 sliport_status, err, reset_needed;
67297ad8
PR		 612 bool resource_error;
613
614 resource_error = lancer_provisioning_error(adapter);
615 if (resource_error)
01e5b2c4 616 return -EAGAIN;
67297ad8 617
bf99e50d
PR		 618 status = lancer_wait_ready(adapter);
619 if (!status) {
620 sliport_status = ioread32(adapter->db + SLIPORT_STATUS_OFFSET);
621 err = sliport_status & SLIPORT_STATUS_ERR_MASK;
622 reset_needed = sliport_status & SLIPORT_STATUS_RN_MASK;
623 if (err && reset_needed) {
624 iowrite32(SLI_PORT_CONTROL_IP_MASK,
625 adapter->db + SLIPORT_CONTROL_OFFSET);
626
e673244a 627 /* check if adapter has corrected the error */
bf99e50d
PR		 628 status = lancer_wait_ready(adapter);
629 sliport_status = ioread32(adapter->db +
630 SLIPORT_STATUS_OFFSET);
631 sliport_status &= (SLIPORT_STATUS_ERR_MASK |
632 SLIPORT_STATUS_RN_MASK);
633 if (status || sliport_status)
634 status = -1;
635 } else if (err || reset_needed) {
636 status = -1;
637 }
638 }
67297ad8
PR		 639 /* Stop error recovery if error is not recoverable.
640 * No resource error is temporary errors and will go away
641 * when PF provisions resources.
642 */
643 resource_error = lancer_provisioning_error(adapter);
01e5b2c4
SK		 644 if (resource_error)
645 status = -EAGAIN;
67297ad8 646
bf99e50d
PR		 647 return status;
648}
649
650int be_fw_wait_ready(struct be_adapter *adapter)
6b7c5b94 651{
43a04fdc
SP		 652 u16 stage;
653 int status, timeout = 0;
6ed35eea 654 struct device *dev = &adapter->pdev->dev;
6b7c5b94 655
bf99e50d
PR		 656 if (lancer_chip(adapter)) {
657 status = lancer_wait_ready(adapter);
e673244a
KA		 658 if (status) {
659 stage = status;
660 goto err;
661 }
662 return 0;
bf99e50d
PR		 663 }
664
43a04fdc 665 do {
c5b3ad4c 666 stage = be_POST_stage_get(adapter);
66d29cbc 667 if (stage == POST_STAGE_ARMFW_RDY)
43a04fdc 668 return 0;
66d29cbc 669
a2cc4e0b 670 dev_info(dev, "Waiting for POST, %ds elapsed\n", timeout);
66d29cbc
GS		 671 if (msleep_interruptible(2000)) {
672 dev_err(dev, "Waiting for POST aborted\n");
673 return -EINTR;
43a04fdc 674 }
66d29cbc 675 timeout += 2;
3ab81b5f 676 } while (timeout < 60);
6b7c5b94 677
e673244a
KA		 678err:
679 dev_err(dev, "POST timeout; stage=%#x\n", stage);
43a04fdc 680 return -1;
6b7c5b94
SP		 681}
682
6b7c5b94
SP		 683static inline struct be_sge *nonembedded_sgl(struct be_mcc_wrb *wrb)
684{
685 return &wrb->payload.sgl[0];
686}
687
a2cc4e0b 688static inline void fill_wrb_tags(struct be_mcc_wrb *wrb, unsigned long addr)
bea50988
SP		 689{
690 wrb->tag0 = addr & 0xFFFFFFFF;
691 wrb->tag1 = upper_32_bits(addr);
692}
6b7c5b94
SP		 693
694/* Don't touch the hdr after it's prepared */
106df1e3
SK		 695/* mem will be NULL for embedded commands */
696static void be_wrb_cmd_hdr_prepare(struct be_cmd_req_hdr *req_hdr,
a2cc4e0b
SP		 697 u8 subsystem, u8 opcode, int cmd_len,
698 struct be_mcc_wrb *wrb,
699 struct be_dma_mem *mem)
6b7c5b94 700{
106df1e3
SK		 701 struct be_sge *sge;
702
6b7c5b94
SP		 703 req_hdr->opcode = opcode;
704 req_hdr->subsystem = subsystem;
705 req_hdr->request_length = cpu_to_le32(cmd_len - sizeof(*req_hdr));
07793d33 706 req_hdr->version = 0;
bea50988 707 fill_wrb_tags(wrb, (ulong) req_hdr);
106df1e3
SK		 708 wrb->payload_length = cmd_len;
709 if (mem) {
710 wrb->embedded |= (1 & MCC_WRB_SGE_CNT_MASK) <<
711 MCC_WRB_SGE_CNT_SHIFT;
712 sge = nonembedded_sgl(wrb);
713 sge->pa_hi = cpu_to_le32(upper_32_bits(mem->dma));
714 sge->pa_lo = cpu_to_le32(mem->dma & 0xFFFFFFFF);
715 sge->len = cpu_to_le32(mem->size);
716 } else
717 wrb->embedded |= MCC_WRB_EMBEDDED_MASK;
718 be_dws_cpu_to_le(wrb, 8);
6b7c5b94
SP		 719}
720
721static void be_cmd_page_addrs_prepare(struct phys_addr *pages, u32 max_pages,
a2cc4e0b 722 struct be_dma_mem *mem)
6b7c5b94
SP		 723{
724 int i, buf_pages = min(PAGES_4K_SPANNED(mem->va, mem->size), max_pages);
725 u64 dma = (u64)mem->dma;
726
727 for (i = 0; i < buf_pages; i++) {
728 pages[i].lo = cpu_to_le32(dma & 0xFFFFFFFF);
729 pages[i].hi = cpu_to_le32(upper_32_bits(dma));
730 dma += PAGE_SIZE_4K;
731 }
732}
733
b31c50a7 734static inline struct be_mcc_wrb *wrb_from_mbox(struct be_adapter *adapter)
6b7c5b94 735{
b31c50a7
SP		 736 struct be_dma_mem *mbox_mem = &adapter->mbox_mem;
737 struct be_mcc_wrb *wrb
738 = &((struct be_mcc_mailbox *)(mbox_mem->va))->wrb;
739 memset(wrb, 0, sizeof(*wrb));
740 return wrb;
6b7c5b94
SP		 741}
742
b31c50a7 743static struct be_mcc_wrb *wrb_from_mccq(struct be_adapter *adapter)
5fb379ee 744{
b31c50a7
SP		 745 struct be_queue_info *mccq = &adapter->mcc_obj.q;
746 struct be_mcc_wrb *wrb;
747
aa790db9
PR		 748 if (!mccq->created)
749 return NULL;
750
4d277125 751 if (atomic_read(&mccq->used) >= mccq->len)
713d0394 752 return NULL;
713d0394 753
b31c50a7
SP		 754 wrb = queue_head_node(mccq);
755 queue_head_inc(mccq);
756 atomic_inc(&mccq->used);
757 memset(wrb, 0, sizeof(*wrb));
5fb379ee
SP		 758 return wrb;
759}
760
bea50988
SP		 761static bool use_mcc(struct be_adapter *adapter)
762{
763 return adapter->mcc_obj.q.created;
764}
765
766/* Must be used only in process context */
767static int be_cmd_lock(struct be_adapter *adapter)
768{
769 if (use_mcc(adapter)) {
770 spin_lock_bh(&adapter->mcc_lock);
771 return 0;
772 } else {
773 return mutex_lock_interruptible(&adapter->mbox_lock);
774 }
775}
776
777/* Must be used only in process context */
778static void be_cmd_unlock(struct be_adapter *adapter)
779{
780 if (use_mcc(adapter))
781 spin_unlock_bh(&adapter->mcc_lock);
782 else
783 return mutex_unlock(&adapter->mbox_lock);
784}
785
786static struct be_mcc_wrb *be_cmd_copy(struct be_adapter *adapter,
787 struct be_mcc_wrb *wrb)
788{
789 struct be_mcc_wrb *dest_wrb;
790
791 if (use_mcc(adapter)) {
792 dest_wrb = wrb_from_mccq(adapter);
793 if (!dest_wrb)
794 return NULL;
795 } else {
796 dest_wrb = wrb_from_mbox(adapter);
797 }
798
799 memcpy(dest_wrb, wrb, sizeof(*wrb));
800 if (wrb->embedded & cpu_to_le32(MCC_WRB_EMBEDDED_MASK))
801 fill_wrb_tags(dest_wrb, (ulong) embedded_payload(wrb));
802
803 return dest_wrb;
804}
805
806/* Must be used only in process context */
807static int be_cmd_notify_wait(struct be_adapter *adapter,
808 struct be_mcc_wrb *wrb)
809{
810 struct be_mcc_wrb *dest_wrb;
811 int status;
812
813 status = be_cmd_lock(adapter);
814 if (status)
815 return status;
816
817 dest_wrb = be_cmd_copy(adapter, wrb);
818 if (!dest_wrb)
819 return -EBUSY;
820
821 if (use_mcc(adapter))
822 status = be_mcc_notify_wait(adapter);
823 else
824 status = be_mbox_notify_wait(adapter);
825
826 if (!status)
827 memcpy(wrb, dest_wrb, sizeof(*wrb));
828
829 be_cmd_unlock(adapter);
830 return status;
831}
832
2243e2e9
SP		 833/* Tell fw we're about to start firing cmds by writing a
834 * special pattern across the wrb hdr; uses mbox
835 */
836int be_cmd_fw_init(struct be_adapter *adapter)
837{
838 u8 *wrb;
839 int status;
840
bf99e50d
PR		 841 if (lancer_chip(adapter))
842 return 0;
843
2984961c
IV		 844 if (mutex_lock_interruptible(&adapter->mbox_lock))
845 return -1;
2243e2e9
SP		 846
847 wrb = (u8 *)wrb_from_mbox(adapter);
359a972f
SP		 848 *wrb++ = 0xFF;
849 *wrb++ = 0x12;
850 *wrb++ = 0x34;
851 *wrb++ = 0xFF;
852 *wrb++ = 0xFF;
853 *wrb++ = 0x56;
854 *wrb++ = 0x78;
855 *wrb = 0xFF;
2243e2e9
SP		 856
857 status = be_mbox_notify_wait(adapter);
858
2984961c 859 mutex_unlock(&adapter->mbox_lock);
2243e2e9
SP		 860 return status;
861}
862
863/* Tell fw we're done with firing cmds by writing a
864 * special pattern across the wrb hdr; uses mbox
865 */
866int be_cmd_fw_clean(struct be_adapter *adapter)
867{
868 u8 *wrb;
869 int status;
870
bf99e50d
PR		 871 if (lancer_chip(adapter))
872 return 0;
873
2984961c
IV		 874 if (mutex_lock_interruptible(&adapter->mbox_lock))
875 return -1;
2243e2e9
SP		 876
877 wrb = (u8 *)wrb_from_mbox(adapter);
878 *wrb++ = 0xFF;
879 *wrb++ = 0xAA;
880 *wrb++ = 0xBB;
881 *wrb++ = 0xFF;
882 *wrb++ = 0xFF;
883 *wrb++ = 0xCC;
884 *wrb++ = 0xDD;
885 *wrb = 0xFF;
886
887 status = be_mbox_notify_wait(adapter);
888
2984961c 889 mutex_unlock(&adapter->mbox_lock);
2243e2e9
SP		 890 return status;
891}
bf99e50d 892
f2f781a7 893int be_cmd_eq_create(struct be_adapter *adapter, struct be_eq_obj *eqo)
6b7c5b94 894{
b31c50a7
SP		 895 struct be_mcc_wrb *wrb;
896 struct be_cmd_req_eq_create *req;
f2f781a7
SP		 897 struct be_dma_mem *q_mem = &eqo->q.dma_mem;
898 int status, ver = 0;
6b7c5b94 899
2984961c
IV		 900 if (mutex_lock_interruptible(&adapter->mbox_lock))
901 return -1;
b31c50a7
SP		 902
903 wrb = wrb_from_mbox(adapter);
904 req = embedded_payload(wrb);
6b7c5b94 905
106df1e3 906 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 907 OPCODE_COMMON_EQ_CREATE, sizeof(*req), wrb,
908 NULL);
6b7c5b94 909
f2f781a7
SP		 910 /* Support for EQ_CREATEv2 available only SH-R onwards */
911 if (!(BEx_chip(adapter) || lancer_chip(adapter)))
912 ver = 2;
913
914 req->hdr.version = ver;
6b7c5b94
SP		 915 req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
916
6b7c5b94
SP		 917 AMAP_SET_BITS(struct amap_eq_context, valid, req->context, 1);
918 /* 4byte eqe*/
919 AMAP_SET_BITS(struct amap_eq_context, size, req->context, 0);
920 AMAP_SET_BITS(struct amap_eq_context, count, req->context,
f2f781a7 921 __ilog2_u32(eqo->q.len / 256));
6b7c5b94
SP		 922 be_dws_cpu_to_le(req->context, sizeof(req->context));
923
924 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
925
b31c50a7 926 status = be_mbox_notify_wait(adapter);
6b7c5b94 927 if (!status) {
b31c50a7 928 struct be_cmd_resp_eq_create *resp = embedded_payload(wrb);
03d28ffe 929
f2f781a7
SP		 930 eqo->q.id = le16_to_cpu(resp->eq_id);
931 eqo->msix_idx =
932 (ver == 2) ? le16_to_cpu(resp->msix_idx) : eqo->idx;
933 eqo->q.created = true;
6b7c5b94 934 }
b31c50a7 935
2984961c 936 mutex_unlock(&adapter->mbox_lock);
6b7c5b94
SP		 937 return status;
938}
939
f9449ab7 940/* Use MCC */
8788fdc2 941int be_cmd_mac_addr_query(struct be_adapter *adapter, u8 *mac_addr,
5ee4979b 942 bool permanent, u32 if_handle, u32 pmac_id)
6b7c5b94 943{
b31c50a7
SP		 944 struct be_mcc_wrb *wrb;
945 struct be_cmd_req_mac_query *req;
6b7c5b94
SP		 946 int status;
947
f9449ab7 948 spin_lock_bh(&adapter->mcc_lock);
b31c50a7 949
f9449ab7
SP		 950 wrb = wrb_from_mccq(adapter);
951 if (!wrb) {
952 status = -EBUSY;
953 goto err;
954 }
b31c50a7 955 req = embedded_payload(wrb);
6b7c5b94 956
106df1e3 957 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 958 OPCODE_COMMON_NTWK_MAC_QUERY, sizeof(*req), wrb,
959 NULL);
5ee4979b 960 req->type = MAC_ADDRESS_TYPE_NETWORK;
6b7c5b94
SP		 961 if (permanent) {
962 req->permanent = 1;
963 } else {
504fbf1e 964 req->if_id = cpu_to_le16((u16)if_handle);
590c391d 965 req->pmac_id = cpu_to_le32(pmac_id);
6b7c5b94
SP		 966 req->permanent = 0;
967 }
968
f9449ab7 969 status = be_mcc_notify_wait(adapter);
b31c50a7
SP		 970 if (!status) {
971 struct be_cmd_resp_mac_query *resp = embedded_payload(wrb);
03d28ffe 972
6b7c5b94 973 memcpy(mac_addr, resp->mac.addr, ETH_ALEN);
b31c50a7 974 }
6b7c5b94 975
f9449ab7
SP		 976err:
977 spin_unlock_bh(&adapter->mcc_lock);
6b7c5b94
SP		 978 return status;
979}
980
b31c50a7 981/* Uses synchronous MCCQ */
8788fdc2 982int be_cmd_pmac_add(struct be_adapter *adapter, u8 *mac_addr,
a2cc4e0b 983 u32 if_id, u32 *pmac_id, u32 domain)
6b7c5b94 984{
b31c50a7
SP		 985 struct be_mcc_wrb *wrb;
986 struct be_cmd_req_pmac_add *req;
6b7c5b94
SP		 987 int status;
988
b31c50a7
SP		 989 spin_lock_bh(&adapter->mcc_lock);
990
991 wrb = wrb_from_mccq(adapter);
713d0394
SP		 992 if (!wrb) {
993 status = -EBUSY;
994 goto err;
995 }
b31c50a7 996 req = embedded_payload(wrb);
6b7c5b94 997
106df1e3 998 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 999 OPCODE_COMMON_NTWK_PMAC_ADD, sizeof(*req), wrb,
1000 NULL);
6b7c5b94 1001
f8617e08 1002 req->hdr.domain = domain;
6b7c5b94
SP		 1003 req->if_id = cpu_to_le32(if_id);
1004 memcpy(req->mac_address, mac_addr, ETH_ALEN);
1005
b31c50a7 1006 status = be_mcc_notify_wait(adapter);
6b7c5b94
SP		 1007 if (!status) {
1008 struct be_cmd_resp_pmac_add *resp = embedded_payload(wrb);
03d28ffe 1009
6b7c5b94
SP		 1010 *pmac_id = le32_to_cpu(resp->pmac_id);
1011 }
1012
713d0394 1013err:
b31c50a7 1014 spin_unlock_bh(&adapter->mcc_lock);
e3a7ae2c
SK		 1015
1016 if (status == MCC_STATUS_UNAUTHORIZED_REQUEST)
1017 status = -EPERM;
1018
6b7c5b94
SP		 1019 return status;
1020}
1021
b31c50a7 1022/* Uses synchronous MCCQ */
30128031 1023int be_cmd_pmac_del(struct be_adapter *adapter, u32 if_id, int pmac_id, u32 dom)
6b7c5b94 1024{
b31c50a7
SP		 1025 struct be_mcc_wrb *wrb;
1026 struct be_cmd_req_pmac_del *req;
6b7c5b94
SP		 1027 int status;
1028
30128031
SP		 1029 if (pmac_id == -1)
1030 return 0;
1031
b31c50a7
SP		 1032 spin_lock_bh(&adapter->mcc_lock);
1033
1034 wrb = wrb_from_mccq(adapter);
713d0394
SP		 1035 if (!wrb) {
1036 status = -EBUSY;
1037 goto err;
1038 }
b31c50a7 1039 req = embedded_payload(wrb);
6b7c5b94 1040
106df1e3 1041 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
cd3307aa
KA		 1042 OPCODE_COMMON_NTWK_PMAC_DEL, sizeof(*req),
1043 wrb, NULL);
6b7c5b94 1044
f8617e08 1045 req->hdr.domain = dom;
6b7c5b94
SP		 1046 req->if_id = cpu_to_le32(if_id);
1047 req->pmac_id = cpu_to_le32(pmac_id);
1048
b31c50a7
SP		 1049 status = be_mcc_notify_wait(adapter);
1050
713d0394 1051err:
b31c50a7 1052 spin_unlock_bh(&adapter->mcc_lock);
6b7c5b94
SP		 1053 return status;
1054}
1055
b31c50a7 1056/* Uses Mbox */
10ef9ab4 1057int be_cmd_cq_create(struct be_adapter *adapter, struct be_queue_info *cq,
a2cc4e0b 1058 struct be_queue_info *eq, bool no_delay, int coalesce_wm)
6b7c5b94 1059{
b31c50a7
SP		 1060 struct be_mcc_wrb *wrb;
1061 struct be_cmd_req_cq_create *req;
6b7c5b94 1062 struct be_dma_mem *q_mem = &cq->dma_mem;
b31c50a7 1063 void *ctxt;
6b7c5b94
SP		 1064 int status;
1065
2984961c
IV		 1066 if (mutex_lock_interruptible(&adapter->mbox_lock))
1067 return -1;
b31c50a7
SP		 1068
1069 wrb = wrb_from_mbox(adapter);
1070 req = embedded_payload(wrb);
1071 ctxt = &req->context;
6b7c5b94 1072
106df1e3 1073 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 1074 OPCODE_COMMON_CQ_CREATE, sizeof(*req), wrb,
1075 NULL);
6b7c5b94
SP		 1076
1077 req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
bbdc42f8
AK		 1078
1079 if (BEx_chip(adapter)) {
fe6d2a38 1080 AMAP_SET_BITS(struct amap_cq_context_be, coalescwm, ctxt,
a2cc4e0b 1081 coalesce_wm);
fe6d2a38 1082 AMAP_SET_BITS(struct amap_cq_context_be, nodelay,
a2cc4e0b 1083 ctxt, no_delay);
fe6d2a38 1084 AMAP_SET_BITS(struct amap_cq_context_be, count, ctxt,
a2cc4e0b 1085 __ilog2_u32(cq->len / 256));
fe6d2a38 1086 AMAP_SET_BITS(struct amap_cq_context_be, valid, ctxt, 1);
fe6d2a38
SP		 1087 AMAP_SET_BITS(struct amap_cq_context_be, eventable, ctxt, 1);
1088 AMAP_SET_BITS(struct amap_cq_context_be, eqid, ctxt, eq->id);
bbdc42f8
AK		 1089 } else {
1090 req->hdr.version = 2;
1091 req->page_size = 1; /* 1 for 4K */
09e83a9d
AK		 1092
1093 /* coalesce-wm field in this cmd is not relevant to Lancer.
1094 * Lancer uses COMMON_MODIFY_CQ to set this field
1095 */
1096 if (!lancer_chip(adapter))
1097 AMAP_SET_BITS(struct amap_cq_context_v2, coalescwm,
1098 ctxt, coalesce_wm);
bbdc42f8 1099 AMAP_SET_BITS(struct amap_cq_context_v2, nodelay, ctxt,
a2cc4e0b 1100 no_delay);
bbdc42f8 1101 AMAP_SET_BITS(struct amap_cq_context_v2, count, ctxt,
a2cc4e0b 1102 __ilog2_u32(cq->len / 256));
bbdc42f8 1103 AMAP_SET_BITS(struct amap_cq_context_v2, valid, ctxt, 1);
a2cc4e0b
SP		 1104 AMAP_SET_BITS(struct amap_cq_context_v2, eventable, ctxt, 1);
1105 AMAP_SET_BITS(struct amap_cq_context_v2, eqid, ctxt, eq->id);
fe6d2a38 1106 }
6b7c5b94 1107
6b7c5b94
SP		 1108 be_dws_cpu_to_le(ctxt, sizeof(req->context));
1109
1110 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
1111
b31c50a7 1112 status = be_mbox_notify_wait(adapter);
6b7c5b94 1113 if (!status) {
b31c50a7 1114 struct be_cmd_resp_cq_create *resp = embedded_payload(wrb);
03d28ffe 1115
6b7c5b94
SP		 1116 cq->id = le16_to_cpu(resp->cq_id);
1117 cq->created = true;
1118 }
b31c50a7 1119
2984961c 1120 mutex_unlock(&adapter->mbox_lock);
5fb379ee
SP		 1121
1122 return status;
1123}
1124
1125static u32 be_encoded_q_len(int q_len)
1126{
1127 u32 len_encoded = fls(q_len); /* log2(len) + 1 */
03d28ffe 1128
5fb379ee
SP		 1129 if (len_encoded == 16)
1130 len_encoded = 0;
1131 return len_encoded;
1132}
1133
4188e7df 1134static int be_cmd_mccq_ext_create(struct be_adapter *adapter,
a2cc4e0b
SP		 1135 struct be_queue_info *mccq,
1136 struct be_queue_info *cq)
5fb379ee 1137{
b31c50a7 1138 struct be_mcc_wrb *wrb;
34b1ef04 1139 struct be_cmd_req_mcc_ext_create *req;
5fb379ee 1140 struct be_dma_mem *q_mem = &mccq->dma_mem;
b31c50a7 1141 void *ctxt;
5fb379ee
SP		 1142 int status;
1143
2984961c
IV		 1144 if (mutex_lock_interruptible(&adapter->mbox_lock))
1145 return -1;
b31c50a7
SP		 1146
1147 wrb = wrb_from_mbox(adapter);
1148 req = embedded_payload(wrb);
1149 ctxt = &req->context;
5fb379ee 1150
106df1e3 1151 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 1152 OPCODE_COMMON_MCC_CREATE_EXT, sizeof(*req), wrb,
1153 NULL);
5fb379ee 1154
d4a2ac3e 1155 req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
666d39c7 1156 if (BEx_chip(adapter)) {
fe6d2a38
SP		 1157 AMAP_SET_BITS(struct amap_mcc_context_be, valid, ctxt, 1);
1158 AMAP_SET_BITS(struct amap_mcc_context_be, ring_size, ctxt,
a2cc4e0b 1159 be_encoded_q_len(mccq->len));
fe6d2a38 1160 AMAP_SET_BITS(struct amap_mcc_context_be, cq_id, ctxt, cq->id);
666d39c7
VV		 1161 } else {
1162 req->hdr.version = 1;
1163 req->cq_id = cpu_to_le16(cq->id);
1164
1165 AMAP_SET_BITS(struct amap_mcc_context_v1, ring_size, ctxt,
1166 be_encoded_q_len(mccq->len));
1167 AMAP_SET_BITS(struct amap_mcc_context_v1, valid, ctxt, 1);
1168 AMAP_SET_BITS(struct amap_mcc_context_v1, async_cq_id,
1169 ctxt, cq->id);
1170 AMAP_SET_BITS(struct amap_mcc_context_v1, async_cq_valid,
1171 ctxt, 1);
fe6d2a38 1172 }
5fb379ee 1173
cc4ce020 1174 /* Subscribe to Link State and Group 5 Events(bits 1 and 5 set) */
fe6d2a38 1175 req->async_event_bitmap[0] = cpu_to_le32(0x00000022);
bc0c3405 1176 req->async_event_bitmap[0] |= cpu_to_le32(1 << ASYNC_EVENT_CODE_QNQ);
5fb379ee
SP		 1177 be_dws_cpu_to_le(ctxt, sizeof(req->context));
1178
1179 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
1180
b31c50a7 1181 status = be_mbox_notify_wait(adapter);
5fb379ee
SP		 1182 if (!status) {
1183 struct be_cmd_resp_mcc_create *resp = embedded_payload(wrb);
03d28ffe 1184
5fb379ee
SP		 1185 mccq->id = le16_to_cpu(resp->id);
1186 mccq->created = true;
1187 }
2984961c 1188 mutex_unlock(&adapter->mbox_lock);
6b7c5b94
SP		 1189
1190 return status;
1191}
1192
4188e7df 1193static int be_cmd_mccq_org_create(struct be_adapter *adapter,
a2cc4e0b
SP		 1194 struct be_queue_info *mccq,
1195 struct be_queue_info *cq)
34b1ef04
SK		 1196{
1197 struct be_mcc_wrb *wrb;
1198 struct be_cmd_req_mcc_create *req;
1199 struct be_dma_mem *q_mem = &mccq->dma_mem;
1200 void *ctxt;
1201 int status;
1202
1203 if (mutex_lock_interruptible(&adapter->mbox_lock))
1204 return -1;
1205
1206 wrb = wrb_from_mbox(adapter);
1207 req = embedded_payload(wrb);
1208 ctxt = &req->context;
1209
106df1e3 1210 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 1211 OPCODE_COMMON_MCC_CREATE, sizeof(*req), wrb,
1212 NULL);
34b1ef04
SK		 1213
1214 req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
1215
1216 AMAP_SET_BITS(struct amap_mcc_context_be, valid, ctxt, 1);
1217 AMAP_SET_BITS(struct amap_mcc_context_be, ring_size, ctxt,
a2cc4e0b 1218 be_encoded_q_len(mccq->len));
34b1ef04
SK		 1219 AMAP_SET_BITS(struct amap_mcc_context_be, cq_id, ctxt, cq->id);
1220
1221 be_dws_cpu_to_le(ctxt, sizeof(req->context));
1222
1223 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
1224
1225 status = be_mbox_notify_wait(adapter);
1226 if (!status) {
1227 struct be_cmd_resp_mcc_create *resp = embedded_payload(wrb);
03d28ffe 1228
34b1ef04
SK		 1229 mccq->id = le16_to_cpu(resp->id);
1230 mccq->created = true;
1231 }
1232
1233 mutex_unlock(&adapter->mbox_lock);
1234 return status;
1235}
1236
1237int be_cmd_mccq_create(struct be_adapter *adapter,
a2cc4e0b 1238 struct be_queue_info *mccq, struct be_queue_info *cq)
34b1ef04
SK		 1239{
1240 int status;
1241
1242 status = be_cmd_mccq_ext_create(adapter, mccq, cq);
666d39c7 1243 if (status && BEx_chip(adapter)) {
34b1ef04
SK		 1244 dev_warn(&adapter->pdev->dev, "Upgrade to F/W ver 2.102.235.0 "
1245 "or newer to avoid conflicting priorities between NIC "
1246 "and FCoE traffic");
1247 status = be_cmd_mccq_org_create(adapter, mccq, cq);
1248 }
1249 return status;
1250}
1251
94d73aaa 1252int be_cmd_txq_create(struct be_adapter *adapter, struct be_tx_obj *txo)
6b7c5b94 1253{
7707133c 1254 struct be_mcc_wrb wrb = {0};
b31c50a7 1255 struct be_cmd_req_eth_tx_create *req;
94d73aaa
VV		 1256 struct be_queue_info *txq = &txo->q;
1257 struct be_queue_info *cq = &txo->cq;
6b7c5b94 1258 struct be_dma_mem *q_mem = &txq->dma_mem;
94d73aaa 1259 int status, ver = 0;
6b7c5b94 1260
7707133c 1261 req = embedded_payload(&wrb);
106df1e3 1262 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
a2cc4e0b 1263 OPCODE_ETH_TX_CREATE, sizeof(*req), &wrb, NULL);
6b7c5b94 1264
8b7756ca
PR		 1265 if (lancer_chip(adapter)) {
1266 req->hdr.version = 1;
94d73aaa
VV		 1267 } else if (BEx_chip(adapter)) {
1268 if (adapter->function_caps & BE_FUNCTION_CAPS_SUPER_NIC)
1269 req->hdr.version = 2;
1270 } else { /* For SH */
1271 req->hdr.version = 2;
8b7756ca
PR		 1272 }
1273
81b02655
VV		 1274 if (req->hdr.version > 0)
1275 req->if_id = cpu_to_le16(adapter->if_handle);
6b7c5b94
SP		 1276 req->num_pages = PAGES_4K_SPANNED(q_mem->va, q_mem->size);
1277 req->ulp_num = BE_ULP1_NUM;
1278 req->type = BE_ETH_TX_RING_TYPE_STANDARD;
94d73aaa
VV		 1279 req->cq_id = cpu_to_le16(cq->id);
1280 req->queue_size = be_encoded_q_len(txq->len);
6b7c5b94 1281 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
94d73aaa
VV		 1282 ver = req->hdr.version;
1283
7707133c 1284 status = be_cmd_notify_wait(adapter, &wrb);
6b7c5b94 1285 if (!status) {
7707133c 1286 struct be_cmd_resp_eth_tx_create *resp = embedded_payload(&wrb);
03d28ffe 1287
6b7c5b94 1288 txq->id = le16_to_cpu(resp->cid);
94d73aaa
VV		 1289 if (ver == 2)
1290 txo->db_offset = le32_to_cpu(resp->db_offset);
1291 else
1292 txo->db_offset = DB_TXULP1_OFFSET;
6b7c5b94
SP		 1293 txq->created = true;
1294 }
b31c50a7 1295
6b7c5b94
SP		 1296 return status;
1297}
1298
482c9e79 1299/* Uses MCC */
8788fdc2 1300int be_cmd_rxq_create(struct be_adapter *adapter,
a2cc4e0b
SP		 1301 struct be_queue_info *rxq, u16 cq_id, u16 frag_size,
1302 u32 if_id, u32 rss, u8 *rss_id)
6b7c5b94 1303{
b31c50a7
SP		 1304 struct be_mcc_wrb *wrb;
1305 struct be_cmd_req_eth_rx_create *req;
6b7c5b94
SP		 1306 struct be_dma_mem *q_mem = &rxq->dma_mem;
1307 int status;
1308
482c9e79 1309 spin_lock_bh(&adapter->mcc_lock);
b31c50a7 1310
482c9e79
SP		 1311 wrb = wrb_from_mccq(adapter);
1312 if (!wrb) {
1313 status = -EBUSY;
1314 goto err;
1315 }
b31c50a7 1316 req = embedded_payload(wrb);
6b7c5b94 1317
106df1e3 1318 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
a2cc4e0b 1319 OPCODE_ETH_RX_CREATE, sizeof(*req), wrb, NULL);
6b7c5b94
SP		 1320
1321 req->cq_id = cpu_to_le16(cq_id);
1322 req->frag_size = fls(frag_size) - 1;
1323 req->num_pages = 2;
1324 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
1325 req->interface_id = cpu_to_le32(if_id);
10ef9ab4 1326 req->max_frame_size = cpu_to_le16(BE_MAX_JUMBO_FRAME_SIZE);
6b7c5b94
SP		 1327 req->rss_queue = cpu_to_le32(rss);
1328
482c9e79 1329 status = be_mcc_notify_wait(adapter);
6b7c5b94
SP		 1330 if (!status) {
1331 struct be_cmd_resp_eth_rx_create *resp = embedded_payload(wrb);
03d28ffe 1332
6b7c5b94
SP		 1333 rxq->id = le16_to_cpu(resp->id);
1334 rxq->created = true;
3abcdeda 1335 *rss_id = resp->rss_id;
6b7c5b94 1336 }
b31c50a7 1337
482c9e79
SP		 1338err:
1339 spin_unlock_bh(&adapter->mcc_lock);
6b7c5b94
SP		 1340 return status;
1341}
1342
b31c50a7
SP		 1343/* Generic destroyer function for all types of queues
1344 * Uses Mbox
1345 */
8788fdc2 1346int be_cmd_q_destroy(struct be_adapter *adapter, struct be_queue_info *q,
a2cc4e0b 1347 int queue_type)
6b7c5b94 1348{
b31c50a7
SP		 1349 struct be_mcc_wrb *wrb;
1350 struct be_cmd_req_q_destroy *req;
6b7c5b94
SP		 1351 u8 subsys = 0, opcode = 0;
1352 int status;
1353
2984961c
IV		 1354 if (mutex_lock_interruptible(&adapter->mbox_lock))
1355 return -1;
6b7c5b94 1356
b31c50a7
SP		 1357 wrb = wrb_from_mbox(adapter);
1358 req = embedded_payload(wrb);
1359
6b7c5b94
SP		 1360 switch (queue_type) {
1361 case QTYPE_EQ:
1362 subsys = CMD_SUBSYSTEM_COMMON;
1363 opcode = OPCODE_COMMON_EQ_DESTROY;
1364 break;
1365 case QTYPE_CQ:
1366 subsys = CMD_SUBSYSTEM_COMMON;
1367 opcode = OPCODE_COMMON_CQ_DESTROY;
1368 break;
1369 case QTYPE_TXQ:
1370 subsys = CMD_SUBSYSTEM_ETH;
1371 opcode = OPCODE_ETH_TX_DESTROY;
1372 break;
1373 case QTYPE_RXQ:
1374 subsys = CMD_SUBSYSTEM_ETH;
1375 opcode = OPCODE_ETH_RX_DESTROY;
1376 break;
5fb379ee
SP		 1377 case QTYPE_MCCQ:
1378 subsys = CMD_SUBSYSTEM_COMMON;
1379 opcode = OPCODE_COMMON_MCC_DESTROY;
1380 break;
6b7c5b94 1381 default:
5f0b849e 1382 BUG();
6b7c5b94 1383 }
d744b44e 1384
106df1e3 1385 be_wrb_cmd_hdr_prepare(&req->hdr, subsys, opcode, sizeof(*req), wrb,
a2cc4e0b 1386 NULL);
6b7c5b94
SP		 1387 req->id = cpu_to_le16(q->id);
1388
b31c50a7 1389 status = be_mbox_notify_wait(adapter);
aa790db9 1390 q->created = false;
5f0b849e 1391
2984961c 1392 mutex_unlock(&adapter->mbox_lock);
482c9e79
SP		 1393 return status;
1394}
6b7c5b94 1395
482c9e79
SP		 1396/* Uses MCC */
1397int be_cmd_rxq_destroy(struct be_adapter *adapter, struct be_queue_info *q)
1398{
1399 struct be_mcc_wrb *wrb;
1400 struct be_cmd_req_q_destroy *req;
1401 int status;
1402
1403 spin_lock_bh(&adapter->mcc_lock);
1404
1405 wrb = wrb_from_mccq(adapter);
1406 if (!wrb) {
1407 status = -EBUSY;
1408 goto err;
1409 }
1410 req = embedded_payload(wrb);
1411
106df1e3 1412 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
a2cc4e0b 1413 OPCODE_ETH_RX_DESTROY, sizeof(*req), wrb, NULL);
482c9e79
SP		 1414 req->id = cpu_to_le16(q->id);
1415
1416 status = be_mcc_notify_wait(adapter);
aa790db9 1417 q->created = false;
482c9e79
SP		 1418
1419err:
1420 spin_unlock_bh(&adapter->mcc_lock);
6b7c5b94
SP		 1421 return status;
1422}
1423
b31c50a7 1424/* Create an rx filtering policy configuration on an i/f
bea50988 1425 * Will use MBOX only if MCCQ has not been created.
b31c50a7 1426 */
73d540f2 1427int be_cmd_if_create(struct be_adapter *adapter, u32 cap_flags, u32 en_flags,
1578e777 1428 u32 *if_handle, u32 domain)
6b7c5b94 1429{
bea50988 1430 struct be_mcc_wrb wrb = {0};
b31c50a7 1431 struct be_cmd_req_if_create *req;
6b7c5b94
SP		 1432 int status;
1433
bea50988 1434 req = embedded_payload(&wrb);
106df1e3 1435 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 1436 OPCODE_COMMON_NTWK_INTERFACE_CREATE,
1437 sizeof(*req), &wrb, NULL);
ba343c77 1438 req->hdr.domain = domain;
73d540f2
SP		 1439 req->capability_flags = cpu_to_le32(cap_flags);
1440 req->enable_flags = cpu_to_le32(en_flags);
1578e777 1441 req->pmac_invalid = true;
6b7c5b94 1442
bea50988 1443 status = be_cmd_notify_wait(adapter, &wrb);
6b7c5b94 1444 if (!status) {
bea50988 1445 struct be_cmd_resp_if_create *resp = embedded_payload(&wrb);
03d28ffe 1446
6b7c5b94 1447 *if_handle = le32_to_cpu(resp->interface_id);
b5bb9776
SP		 1448
1449 /* Hack to retrieve VF's pmac-id on BE3 */
1450 if (BE3_chip(adapter) && !be_physfn(adapter))
1451 adapter->pmac_id[0] = le32_to_cpu(resp->pmac_id);
6b7c5b94 1452 }
6b7c5b94
SP		 1453 return status;
1454}
1455
f9449ab7 1456/* Uses MCCQ */
30128031 1457int be_cmd_if_destroy(struct be_adapter *adapter, int interface_id, u32 domain)
6b7c5b94 1458{
b31c50a7
SP		 1459 struct be_mcc_wrb *wrb;
1460 struct be_cmd_req_if_destroy *req;
6b7c5b94
SP		 1461 int status;
1462
30128031 1463 if (interface_id == -1)
f9449ab7 1464 return 0;
b31c50a7 1465
f9449ab7
SP		 1466 spin_lock_bh(&adapter->mcc_lock);
1467
1468 wrb = wrb_from_mccq(adapter);
1469 if (!wrb) {
1470 status = -EBUSY;
1471 goto err;
1472 }
b31c50a7 1473 req = embedded_payload(wrb);
6b7c5b94 1474
106df1e3 1475 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 1476 OPCODE_COMMON_NTWK_INTERFACE_DESTROY,
1477 sizeof(*req), wrb, NULL);
658681f7 1478 req->hdr.domain = domain;
6b7c5b94 1479 req->interface_id = cpu_to_le32(interface_id);
b31c50a7 1480
f9449ab7
SP		 1481 status = be_mcc_notify_wait(adapter);
1482err:
1483 spin_unlock_bh(&adapter->mcc_lock);
6b7c5b94
SP		 1484 return status;
1485}
1486
1487/* Get stats is a non embedded command: the request is not embedded inside
1488 * WRB but is a separate dma memory block
b31c50a7 1489 * Uses asynchronous MCC
6b7c5b94 1490 */
8788fdc2 1491int be_cmd_get_stats(struct be_adapter *adapter, struct be_dma_mem *nonemb_cmd)
6b7c5b94 1492{
b31c50a7 1493 struct be_mcc_wrb *wrb;
89a88ab8 1494 struct be_cmd_req_hdr *hdr;
713d0394 1495 int status = 0;
6b7c5b94 1496
b31c50a7 1497 spin_lock_bh(&adapter->mcc_lock);
6b7c5b94 1498
b31c50a7 1499 wrb = wrb_from_mccq(adapter);
713d0394
SP		 1500 if (!wrb) {
1501 status = -EBUSY;
1502 goto err;
1503 }
89a88ab8 1504 hdr = nonemb_cmd->va;
6b7c5b94 1505
106df1e3 1506 be_wrb_cmd_hdr_prepare(hdr, CMD_SUBSYSTEM_ETH,
a2cc4e0b
SP		 1507 OPCODE_ETH_GET_STATISTICS, nonemb_cmd->size, wrb,
1508 nonemb_cmd);
89a88ab8 1509
ca34fe38 1510 /* version 1 of the cmd is not supported only by BE2 */
61000861
AK		 1511 if (BE2_chip(adapter))
1512 hdr->version = 0;
1513 if (BE3_chip(adapter) || lancer_chip(adapter))
89a88ab8 1514 hdr->version = 1;
61000861
AK		 1515 else
1516 hdr->version = 2;
89a88ab8 1517
b31c50a7 1518 be_mcc_notify(adapter);
b2aebe6d 1519 adapter->stats_cmd_sent = true;
6b7c5b94 1520
713d0394 1521err:
b31c50a7 1522 spin_unlock_bh(&adapter->mcc_lock);
713d0394 1523 return status;
6b7c5b94
SP		 1524}
1525
005d5696
SX		 1526/* Lancer Stats */
1527int lancer_cmd_get_pport_stats(struct be_adapter *adapter,
a2cc4e0b 1528 struct be_dma_mem *nonemb_cmd)
005d5696 1529{
005d5696
SX		 1530 struct be_mcc_wrb *wrb;
1531 struct lancer_cmd_req_pport_stats *req;
005d5696
SX		 1532 int status = 0;
1533
f25b119c
PR		 1534 if (!be_cmd_allowed(adapter, OPCODE_ETH_GET_PPORT_STATS,
1535 CMD_SUBSYSTEM_ETH))
1536 return -EPERM;
1537
005d5696
SX		 1538 spin_lock_bh(&adapter->mcc_lock);
1539
1540 wrb = wrb_from_mccq(adapter);
1541 if (!wrb) {
1542 status = -EBUSY;
1543 goto err;
1544 }
1545 req = nonemb_cmd->va;
005d5696 1546
106df1e3 1547 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
a2cc4e0b
SP		 1548 OPCODE_ETH_GET_PPORT_STATS, nonemb_cmd->size,
1549 wrb, nonemb_cmd);
005d5696 1550
d51ebd33 1551 req->cmd_params.params.pport_num = cpu_to_le16(adapter->hba_port_num);
005d5696
SX		 1552 req->cmd_params.params.reset_stats = 0;
1553
005d5696
SX		 1554 be_mcc_notify(adapter);
1555 adapter->stats_cmd_sent = true;
1556
1557err:
1558 spin_unlock_bh(&adapter->mcc_lock);
1559 return status;
1560}
1561
323ff71e
SP		 1562static int be_mac_to_link_speed(int mac_speed)
1563{
1564 switch (mac_speed) {
1565 case PHY_LINK_SPEED_ZERO:
1566 return 0;
1567 case PHY_LINK_SPEED_10MBPS:
1568 return 10;
1569 case PHY_LINK_SPEED_100MBPS:
1570 return 100;
1571 case PHY_LINK_SPEED_1GBPS:
1572 return 1000;
1573 case PHY_LINK_SPEED_10GBPS:
1574 return 10000;
b971f847
VV		 1575 case PHY_LINK_SPEED_20GBPS:
1576 return 20000;
1577 case PHY_LINK_SPEED_25GBPS:
1578 return 25000;
1579 case PHY_LINK_SPEED_40GBPS:
1580 return 40000;
323ff71e
SP		 1581 }
1582 return 0;
1583}
1584
1585/* Uses synchronous mcc
1586 * Returns link_speed in Mbps
1587 */
1588int be_cmd_link_status_query(struct be_adapter *adapter, u16 *link_speed,
1589 u8 *link_status, u32 dom)
6b7c5b94 1590{
b31c50a7
SP		 1591 struct be_mcc_wrb *wrb;
1592 struct be_cmd_req_link_status *req;
6b7c5b94
SP		 1593 int status;
1594
b31c50a7
SP		 1595 spin_lock_bh(&adapter->mcc_lock);
1596
b236916a
AK		 1597 if (link_status)
1598 *link_status = LINK_DOWN;
1599
b31c50a7 1600 wrb = wrb_from_mccq(adapter);
713d0394
SP		 1601 if (!wrb) {
1602 status = -EBUSY;
1603 goto err;
1604 }
b31c50a7 1605 req = embedded_payload(wrb);
a8f447bd 1606
57cd80d4 1607 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 1608 OPCODE_COMMON_NTWK_LINK_STATUS_QUERY,
1609 sizeof(*req), wrb, NULL);
57cd80d4 1610
ca34fe38
SP		 1611 /* version 1 of the cmd is not supported only by BE2 */
1612 if (!BE2_chip(adapter))
daad6167
PR		 1613 req->hdr.version = 1;
1614
57cd80d4 1615 req->hdr.domain = dom;
6b7c5b94 1616
b31c50a7 1617 status = be_mcc_notify_wait(adapter);
6b7c5b94
SP		 1618 if (!status) {
1619 struct be_cmd_resp_link_status *resp = embedded_payload(wrb);
03d28ffe 1620
323ff71e
SP		 1621 if (link_speed) {
1622 *link_speed = resp->link_speed ?
1623 le16_to_cpu(resp->link_speed) * 10 :
1624 be_mac_to_link_speed(resp->mac_speed);
1625
1626 if (!resp->logical_link_status)
1627 *link_speed = 0;
0388f251 1628 }
b236916a
AK		 1629 if (link_status)
1630 *link_status = resp->logical_link_status;
6b7c5b94
SP		 1631 }
1632
713d0394 1633err:
b31c50a7 1634 spin_unlock_bh(&adapter->mcc_lock);
6b7c5b94
SP		 1635 return status;
1636}
1637
609ff3bb
AK		 1638/* Uses synchronous mcc */
1639int be_cmd_get_die_temperature(struct be_adapter *adapter)
1640{
1641 struct be_mcc_wrb *wrb;
1642 struct be_cmd_req_get_cntl_addnl_attribs *req;
117affe3 1643 int status = 0;
609ff3bb
AK		 1644
1645 spin_lock_bh(&adapter->mcc_lock);
1646
1647 wrb = wrb_from_mccq(adapter);
1648 if (!wrb) {
1649 status = -EBUSY;
1650 goto err;
1651 }
1652 req = embedded_payload(wrb);
1653
106df1e3 1654 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 1655 OPCODE_COMMON_GET_CNTL_ADDITIONAL_ATTRIBUTES,
1656 sizeof(*req), wrb, NULL);
609ff3bb 1657
3de09455 1658 be_mcc_notify(adapter);
609ff3bb
AK		 1659
1660err:
1661 spin_unlock_bh(&adapter->mcc_lock);
1662 return status;
1663}
1664
311fddc7
SK		 1665/* Uses synchronous mcc */
1666int be_cmd_get_reg_len(struct be_adapter *adapter, u32 *log_size)
1667{
1668 struct be_mcc_wrb *wrb;
1669 struct be_cmd_req_get_fat *req;
1670 int status;
1671
1672 spin_lock_bh(&adapter->mcc_lock);
1673
1674 wrb = wrb_from_mccq(adapter);
1675 if (!wrb) {
1676 status = -EBUSY;
1677 goto err;
1678 }
1679 req = embedded_payload(wrb);
1680
106df1e3 1681 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 1682 OPCODE_COMMON_MANAGE_FAT, sizeof(*req), wrb,
1683 NULL);
311fddc7
SK		 1684 req->fat_operation = cpu_to_le32(QUERY_FAT);
1685 status = be_mcc_notify_wait(adapter);
1686 if (!status) {
1687 struct be_cmd_resp_get_fat *resp = embedded_payload(wrb);
03d28ffe 1688
311fddc7 1689 if (log_size && resp->log_size)
fe2a70ee
SK		 1690 *log_size = le32_to_cpu(resp->log_size) -
1691 sizeof(u32);
311fddc7
SK		 1692 }
1693err:
1694 spin_unlock_bh(&adapter->mcc_lock);
1695 return status;
1696}
1697
c5f156de 1698int be_cmd_get_regs(struct be_adapter *adapter, u32 buf_len, void *buf)
311fddc7
SK		 1699{
1700 struct be_dma_mem get_fat_cmd;
1701 struct be_mcc_wrb *wrb;
1702 struct be_cmd_req_get_fat *req;
fe2a70ee
SK		 1703 u32 offset = 0, total_size, buf_size,
1704 log_offset = sizeof(u32), payload_len;
c5f156de 1705 int status = 0;
311fddc7
SK		 1706
1707 if (buf_len == 0)
c5f156de 1708 return -EIO;
311fddc7
SK		 1709
1710 total_size = buf_len;
1711
fe2a70ee
SK		 1712 get_fat_cmd.size = sizeof(struct be_cmd_req_get_fat) + 60*1024;
1713 get_fat_cmd.va = pci_alloc_consistent(adapter->pdev,
a2cc4e0b
SP		 1714 get_fat_cmd.size,
1715 &get_fat_cmd.dma);
fe2a70ee 1716 if (!get_fat_cmd.va) {
fe2a70ee 1717 dev_err(&adapter->pdev->dev,
cd3307aa 1718 "Memory allocation failure while reading FAT data\n");
c5f156de 1719 return -ENOMEM;
fe2a70ee
SK		 1720 }
1721
311fddc7
SK		 1722 spin_lock_bh(&adapter->mcc_lock);
1723
311fddc7
SK		 1724 while (total_size) {
1725 buf_size = min(total_size, (u32)60*1024);
1726 total_size -= buf_size;
1727
fe2a70ee
SK		 1728 wrb = wrb_from_mccq(adapter);
1729 if (!wrb) {
1730 status = -EBUSY;
311fddc7
SK		 1731 goto err;
1732 }
1733 req = get_fat_cmd.va;
311fddc7 1734
fe2a70ee 1735 payload_len = sizeof(struct be_cmd_req_get_fat) + buf_size;
106df1e3 1736 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 1737 OPCODE_COMMON_MANAGE_FAT, payload_len,
1738 wrb, &get_fat_cmd);
311fddc7
SK		 1739
1740 req->fat_operation = cpu_to_le32(RETRIEVE_FAT);
1741 req->read_log_offset = cpu_to_le32(log_offset);
1742 req->read_log_length = cpu_to_le32(buf_size);
1743 req->data_buffer_size = cpu_to_le32(buf_size);
1744
1745 status = be_mcc_notify_wait(adapter);
1746 if (!status) {
1747 struct be_cmd_resp_get_fat *resp = get_fat_cmd.va;
03d28ffe 1748
311fddc7 1749 memcpy(buf + offset,
a2cc4e0b
SP		 1750 resp->data_buffer,
1751 le32_to_cpu(resp->read_log_length));
fe2a70ee 1752 } else {
311fddc7 1753 dev_err(&adapter->pdev->dev, "FAT Table Retrieve error\n");
fe2a70ee
SK		 1754 goto err;
1755 }
311fddc7
SK		 1756 offset += buf_size;
1757 log_offset += buf_size;
1758 }
1759err:
fe2a70ee 1760 pci_free_consistent(adapter->pdev, get_fat_cmd.size,
a2cc4e0b 1761 get_fat_cmd.va, get_fat_cmd.dma);
311fddc7 1762 spin_unlock_bh(&adapter->mcc_lock);
c5f156de 1763 return status;
311fddc7
SK		 1764}
1765
04b71175 1766/* Uses synchronous mcc */
e97e3cda 1767int be_cmd_get_fw_ver(struct be_adapter *adapter)
6b7c5b94 1768{
b31c50a7
SP		 1769 struct be_mcc_wrb *wrb;
1770 struct be_cmd_req_get_fw_version *req;
6b7c5b94
SP		 1771 int status;
1772
04b71175 1773 spin_lock_bh(&adapter->mcc_lock);
b31c50a7 1774
04b71175
SP		 1775 wrb = wrb_from_mccq(adapter);
1776 if (!wrb) {
1777 status = -EBUSY;
1778 goto err;
1779 }
6b7c5b94 1780
04b71175 1781 req = embedded_payload(wrb);
6b7c5b94 1782
106df1e3 1783 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 1784 OPCODE_COMMON_GET_FW_VERSION, sizeof(*req), wrb,
1785 NULL);
04b71175 1786 status = be_mcc_notify_wait(adapter);
6b7c5b94
SP		 1787 if (!status) {
1788 struct be_cmd_resp_get_fw_version *resp = embedded_payload(wrb);
acbafeb1 1789
242eb470
VV		 1790 strlcpy(adapter->fw_ver, resp->firmware_version_string,
1791 sizeof(adapter->fw_ver));
1792 strlcpy(adapter->fw_on_flash, resp->fw_on_flash_version_string,
1793 sizeof(adapter->fw_on_flash));
6b7c5b94 1794 }
04b71175
SP		 1795err:
1796 spin_unlock_bh(&adapter->mcc_lock);
6b7c5b94
SP		 1797 return status;
1798}
1799
b31c50a7
SP		 1800/* set the EQ delay interval of an EQ to specified value
1801 * Uses async mcc
1802 */
b502ae8d
KA		 1803static int __be_cmd_modify_eqd(struct be_adapter *adapter,
1804 struct be_set_eqd *set_eqd, int num)
6b7c5b94 1805{
b31c50a7
SP		 1806 struct be_mcc_wrb *wrb;
1807 struct be_cmd_req_modify_eq_delay *req;
2632bafd 1808 int status = 0, i;
6b7c5b94 1809
b31c50a7
SP		 1810 spin_lock_bh(&adapter->mcc_lock);
1811
1812 wrb = wrb_from_mccq(adapter);
713d0394
SP		 1813 if (!wrb) {
1814 status = -EBUSY;
1815 goto err;
1816 }
b31c50a7 1817 req = embedded_payload(wrb);
6b7c5b94 1818
106df1e3 1819 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 1820 OPCODE_COMMON_MODIFY_EQ_DELAY, sizeof(*req), wrb,
1821 NULL);
6b7c5b94 1822
2632bafd
SP		 1823 req->num_eq = cpu_to_le32(num);
1824 for (i = 0; i < num; i++) {
1825 req->set_eqd[i].eq_id = cpu_to_le32(set_eqd[i].eq_id);
1826 req->set_eqd[i].phase = 0;
1827 req->set_eqd[i].delay_multiplier =
1828 cpu_to_le32(set_eqd[i].delay_multiplier);
1829 }
6b7c5b94 1830
b31c50a7 1831 be_mcc_notify(adapter);
713d0394 1832err:
b31c50a7 1833 spin_unlock_bh(&adapter->mcc_lock);
713d0394 1834 return status;
6b7c5b94
SP		 1835}
1836
93676703
KA		 1837int be_cmd_modify_eqd(struct be_adapter *adapter, struct be_set_eqd *set_eqd,
1838 int num)
1839{
1840 int num_eqs, i = 0;
1841
1842 if (lancer_chip(adapter) && num > 8) {
1843 while (num) {
1844 num_eqs = min(num, 8);
1845 __be_cmd_modify_eqd(adapter, &set_eqd[i], num_eqs);
1846 i += num_eqs;
1847 num -= num_eqs;
1848 }
1849 } else {
1850 __be_cmd_modify_eqd(adapter, set_eqd, num);
1851 }
1852
1853 return 0;
1854}
1855
b31c50a7 1856/* Uses sycnhronous mcc */
8788fdc2 1857int be_cmd_vlan_config(struct be_adapter *adapter, u32 if_id, u16 *vtag_array,
4d567d97 1858 u32 num)
6b7c5b94 1859{
b31c50a7
SP		 1860 struct be_mcc_wrb *wrb;
1861 struct be_cmd_req_vlan_config *req;
6b7c5b94
SP		 1862 int status;
1863
b31c50a7
SP		 1864 spin_lock_bh(&adapter->mcc_lock);
1865
1866 wrb = wrb_from_mccq(adapter);
713d0394
SP		 1867 if (!wrb) {
1868 status = -EBUSY;
1869 goto err;
1870 }
b31c50a7 1871 req = embedded_payload(wrb);
6b7c5b94 1872
106df1e3 1873 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 1874 OPCODE_COMMON_NTWK_VLAN_CONFIG, sizeof(*req),
1875 wrb, NULL);
6b7c5b94
SP		 1876
1877 req->interface_id = if_id;
012bd387 1878 req->untagged = BE_IF_FLAGS_UNTAGGED & be_if_cap_flags(adapter) ? 1 : 0;
6b7c5b94 1879 req->num_vlan = num;
4d567d97
KA		 1880 memcpy(req->normal_vlan, vtag_array,
1881 req->num_vlan * sizeof(vtag_array[0]));
6b7c5b94 1882
b31c50a7 1883 status = be_mcc_notify_wait(adapter);
713d0394 1884err:
b31c50a7 1885 spin_unlock_bh(&adapter->mcc_lock);
6b7c5b94
SP		 1886 return status;
1887}
1888
ac34b743 1889static int __be_cmd_rx_filter(struct be_adapter *adapter, u32 flags, u32 value)
6b7c5b94 1890{
6ac7b687 1891 struct be_mcc_wrb *wrb;
5b8821b7
SP		 1892 struct be_dma_mem *mem = &adapter->rx_filter;
1893 struct be_cmd_req_rx_filter *req = mem->va;
e7b909a6 1894 int status;
6b7c5b94 1895
8788fdc2 1896 spin_lock_bh(&adapter->mcc_lock);
6ac7b687 1897
b31c50a7 1898 wrb = wrb_from_mccq(adapter);
713d0394
SP		 1899 if (!wrb) {
1900 status = -EBUSY;
1901 goto err;
1902 }
5b8821b7 1903 memset(req, 0, sizeof(*req));
106df1e3 1904 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 1905 OPCODE_COMMON_NTWK_RX_FILTER, sizeof(*req),
1906 wrb, mem);
6b7c5b94 1907
5b8821b7 1908 req->if_id = cpu_to_le32(adapter->if_handle);
ac34b743
SP		 1909 req->if_flags_mask = cpu_to_le32(flags);
1910 req->if_flags = (value == ON) ? req->if_flags_mask : 0;
1911
1912 if (flags & BE_IF_FLAGS_MULTICAST) {
22bedad3 1913 struct netdev_hw_addr *ha;
5b8821b7 1914 int i = 0;
24307eef 1915
1610c79f
PR		 1916 /* Reset mcast promisc mode if already set by setting mask
1917 * and not setting flags field
1918 */
abb93951
PR		 1919 req->if_flags_mask |=
1920 cpu_to_le32(BE_IF_FLAGS_MCAST_PROMISCUOUS &
92bf14ab 1921 be_if_cap_flags(adapter));
016f97b1 1922 req->mcast_num = cpu_to_le32(netdev_mc_count(adapter->netdev));
5b8821b7
SP		 1923 netdev_for_each_mc_addr(ha, adapter->netdev)
1924 memcpy(req->mcast_mac[i++].byte, ha->addr, ETH_ALEN);
6b7c5b94
SP		 1925 }
1926
0d1d5875 1927 status = be_mcc_notify_wait(adapter);
713d0394 1928err:
8788fdc2 1929 spin_unlock_bh(&adapter->mcc_lock);
e7b909a6 1930 return status;
6b7c5b94
SP		 1931}
1932
ac34b743
SP		 1933int be_cmd_rx_filter(struct be_adapter *adapter, u32 flags, u32 value)
1934{
1935 struct device *dev = &adapter->pdev->dev;
1936
1937 if ((flags & be_if_cap_flags(adapter)) != flags) {
1938 dev_warn(dev, "Cannot set rx filter flags 0x%x\n", flags);
1939 dev_warn(dev, "Interface is capable of 0x%x flags only\n",
1940 be_if_cap_flags(adapter));
1941 }
1942 flags &= be_if_cap_flags(adapter);
1943
1944 return __be_cmd_rx_filter(adapter, flags, value);
1945}
1946
b31c50a7 1947/* Uses synchrounous mcc */
8788fdc2 1948int be_cmd_set_flow_control(struct be_adapter *adapter, u32 tx_fc, u32 rx_fc)
6b7c5b94 1949{
b31c50a7
SP		 1950 struct be_mcc_wrb *wrb;
1951 struct be_cmd_req_set_flow_control *req;
6b7c5b94
SP		 1952 int status;
1953
f25b119c
PR		 1954 if (!be_cmd_allowed(adapter, OPCODE_COMMON_SET_FLOW_CONTROL,
1955 CMD_SUBSYSTEM_COMMON))
1956 return -EPERM;
1957
b31c50a7 1958 spin_lock_bh(&adapter->mcc_lock);
6b7c5b94 1959
b31c50a7 1960 wrb = wrb_from_mccq(adapter);
713d0394
SP		 1961 if (!wrb) {
1962 status = -EBUSY;
1963 goto err;
1964 }
b31c50a7 1965 req = embedded_payload(wrb);
6b7c5b94 1966
106df1e3 1967 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 1968 OPCODE_COMMON_SET_FLOW_CONTROL, sizeof(*req),
1969 wrb, NULL);
6b7c5b94 1970
b29812c1 1971 req->hdr.version = 1;
6b7c5b94
SP		 1972 req->tx_flow_control = cpu_to_le16((u16)tx_fc);
1973 req->rx_flow_control = cpu_to_le16((u16)rx_fc);
1974
b31c50a7 1975 status = be_mcc_notify_wait(adapter);
6b7c5b94 1976
713d0394 1977err:
b31c50a7 1978 spin_unlock_bh(&adapter->mcc_lock);
b29812c1
SR		 1979
1980 if (base_status(status) == MCC_STATUS_FEATURE_NOT_SUPPORTED)
1981 return -EOPNOTSUPP;
1982
6b7c5b94
SP		 1983 return status;
1984}
1985
b31c50a7 1986/* Uses sycn mcc */
8788fdc2 1987int be_cmd_get_flow_control(struct be_adapter *adapter, u32 *tx_fc, u32 *rx_fc)
6b7c5b94 1988{
b31c50a7
SP		 1989 struct be_mcc_wrb *wrb;
1990 struct be_cmd_req_get_flow_control *req;
6b7c5b94
SP		 1991 int status;
1992
f25b119c
PR		 1993 if (!be_cmd_allowed(adapter, OPCODE_COMMON_GET_FLOW_CONTROL,
1994 CMD_SUBSYSTEM_COMMON))
1995 return -EPERM;
1996
b31c50a7 1997 spin_lock_bh(&adapter->mcc_lock);
6b7c5b94 1998
b31c50a7 1999 wrb = wrb_from_mccq(adapter);
713d0394
SP		 2000 if (!wrb) {
2001 status = -EBUSY;
2002 goto err;
2003 }
b31c50a7 2004 req = embedded_payload(wrb);
6b7c5b94 2005
106df1e3 2006 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 2007 OPCODE_COMMON_GET_FLOW_CONTROL, sizeof(*req),
2008 wrb, NULL);
6b7c5b94 2009
b31c50a7 2010 status = be_mcc_notify_wait(adapter);
6b7c5b94
SP		 2011 if (!status) {
2012 struct be_cmd_resp_get_flow_control *resp =
2013 embedded_payload(wrb);
03d28ffe 2014
6b7c5b94
SP		 2015 *tx_fc = le16_to_cpu(resp->tx_flow_control);
2016 *rx_fc = le16_to_cpu(resp->rx_flow_control);
2017 }
2018
713d0394 2019err:
b31c50a7 2020 spin_unlock_bh(&adapter->mcc_lock);
6b7c5b94
SP		 2021 return status;
2022}
2023
b31c50a7 2024/* Uses mbox */
e97e3cda 2025int be_cmd_query_fw_cfg(struct be_adapter *adapter)
6b7c5b94 2026{
b31c50a7
SP		 2027 struct be_mcc_wrb *wrb;
2028 struct be_cmd_req_query_fw_cfg *req;
6b7c5b94
SP		 2029 int status;
2030
2984961c
IV		 2031 if (mutex_lock_interruptible(&adapter->mbox_lock))
2032 return -1;
6b7c5b94 2033
b31c50a7
SP		 2034 wrb = wrb_from_mbox(adapter);
2035 req = embedded_payload(wrb);
6b7c5b94 2036
106df1e3 2037 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 2038 OPCODE_COMMON_QUERY_FIRMWARE_CONFIG,
2039 sizeof(*req), wrb, NULL);
6b7c5b94 2040
b31c50a7 2041 status = be_mbox_notify_wait(adapter);
6b7c5b94
SP		 2042 if (!status) {
2043 struct be_cmd_resp_query_fw_cfg *resp = embedded_payload(wrb);
03d28ffe 2044
e97e3cda
KA		 2045 adapter->port_num = le32_to_cpu(resp->phys_port);
2046 adapter->function_mode = le32_to_cpu(resp->function_mode);
2047 adapter->function_caps = le32_to_cpu(resp->function_caps);
2048 adapter->asic_rev = le32_to_cpu(resp->asic_revision) & 0xFF;
acbafeb1
SP		 2049 dev_info(&adapter->pdev->dev,
2050 "FW config: function_mode=0x%x, function_caps=0x%x\n",
2051 adapter->function_mode, adapter->function_caps);
6b7c5b94
SP		 2052 }
2053
2984961c 2054 mutex_unlock(&adapter->mbox_lock);
6b7c5b94
SP		 2055 return status;
2056}
14074eab 2057
b31c50a7 2058/* Uses mbox */
14074eab 2059int be_cmd_reset_function(struct be_adapter *adapter)
2060{
b31c50a7
SP		 2061 struct be_mcc_wrb *wrb;
2062 struct be_cmd_req_hdr *req;
14074eab 2063 int status;
2064
bf99e50d
PR		 2065 if (lancer_chip(adapter)) {
2066 status = lancer_wait_ready(adapter);
2067 if (!status) {
2068 iowrite32(SLI_PORT_CONTROL_IP_MASK,
2069 adapter->db + SLIPORT_CONTROL_OFFSET);
2070 status = lancer_test_and_set_rdy_state(adapter);
2071 }
2072 if (status) {
2073 dev_err(&adapter->pdev->dev,
2074 "Adapter in non recoverable error\n");
2075 }
2076 return status;
2077 }
2078
2984961c
IV		 2079 if (mutex_lock_interruptible(&adapter->mbox_lock))
2080 return -1;
14074eab 2081
b31c50a7
SP		 2082 wrb = wrb_from_mbox(adapter);
2083 req = embedded_payload(wrb);
14074eab 2084
106df1e3 2085 be_wrb_cmd_hdr_prepare(req, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 2086 OPCODE_COMMON_FUNCTION_RESET, sizeof(*req), wrb,
2087 NULL);
14074eab 2088
b31c50a7 2089 status = be_mbox_notify_wait(adapter);
14074eab 2090
2984961c 2091 mutex_unlock(&adapter->mbox_lock);
14074eab 2092 return status;
2093}
84517482 2094
594ad54a 2095int be_cmd_rss_config(struct be_adapter *adapter, u8 *rsstable,
33cb0fa7 2096 u32 rss_hash_opts, u16 table_size, const u8 *rss_hkey)
3abcdeda
SP		 2097{
2098 struct be_mcc_wrb *wrb;
2099 struct be_cmd_req_rss_config *req;
3abcdeda
SP		 2100 int status;
2101
da1388d6
VV		 2102 if (!(be_if_cap_flags(adapter) & BE_IF_FLAGS_RSS))
2103 return 0;
2104
b51aa367 2105 spin_lock_bh(&adapter->mcc_lock);
3abcdeda 2106
b51aa367
KA		 2107 wrb = wrb_from_mccq(adapter);
2108 if (!wrb) {
2109 status = -EBUSY;
2110 goto err;
2111 }
3abcdeda
SP		 2112 req = embedded_payload(wrb);
2113
106df1e3 2114 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
a2cc4e0b 2115 OPCODE_ETH_RSS_CONFIG, sizeof(*req), wrb, NULL);
3abcdeda
SP		 2116
2117 req->if_id = cpu_to_le32(adapter->if_handle);
594ad54a
SR		 2118 req->enable_rss = cpu_to_le16(rss_hash_opts);
2119 req->cpu_table_size_log2 = cpu_to_le16(fls(table_size) - 1);
d3bd3a5e 2120
b51aa367 2121 if (!BEx_chip(adapter))
d3bd3a5e 2122 req->hdr.version = 1;
d3bd3a5e 2123
3abcdeda 2124 memcpy(req->cpu_table, rsstable, table_size);
e2557877 2125 memcpy(req->hash, rss_hkey, RSS_HASH_KEY_LEN);
3abcdeda
SP		 2126 be_dws_cpu_to_le(req->hash, sizeof(req->hash));
2127
b51aa367
KA		 2128 status = be_mcc_notify_wait(adapter);
2129err:
2130 spin_unlock_bh(&adapter->mcc_lock);
3abcdeda
SP		 2131 return status;
2132}
2133
fad9ab2c
SB		 2134/* Uses sync mcc */
2135int be_cmd_set_beacon_state(struct be_adapter *adapter, u8 port_num,
a2cc4e0b 2136 u8 bcn, u8 sts, u8 state)
fad9ab2c
SB		 2137{
2138 struct be_mcc_wrb *wrb;
2139 struct be_cmd_req_enable_disable_beacon *req;
2140 int status;
2141
2142 spin_lock_bh(&adapter->mcc_lock);
2143
2144 wrb = wrb_from_mccq(adapter);
713d0394
SP		 2145 if (!wrb) {
2146 status = -EBUSY;
2147 goto err;
2148 }
fad9ab2c
SB		 2149 req = embedded_payload(wrb);
2150
106df1e3 2151 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 2152 OPCODE_COMMON_ENABLE_DISABLE_BEACON,
2153 sizeof(*req), wrb, NULL);
fad9ab2c
SB		 2154
2155 req->port_num = port_num;
2156 req->beacon_state = state;
2157 req->beacon_duration = bcn;
2158 req->status_duration = sts;
2159
2160 status = be_mcc_notify_wait(adapter);
2161
713d0394 2162err:
fad9ab2c
SB		 2163 spin_unlock_bh(&adapter->mcc_lock);
2164 return status;
2165}
2166
2167/* Uses sync mcc */
2168int be_cmd_get_beacon_state(struct be_adapter *adapter, u8 port_num, u32 *state)
2169{
2170 struct be_mcc_wrb *wrb;
2171 struct be_cmd_req_get_beacon_state *req;
2172 int status;
2173
2174 spin_lock_bh(&adapter->mcc_lock);
2175
2176 wrb = wrb_from_mccq(adapter);
713d0394
SP		 2177 if (!wrb) {
2178 status = -EBUSY;
2179 goto err;
2180 }
fad9ab2c
SB		 2181 req = embedded_payload(wrb);
2182
106df1e3 2183 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 2184 OPCODE_COMMON_GET_BEACON_STATE, sizeof(*req),
2185 wrb, NULL);
fad9ab2c
SB		 2186
2187 req->port_num = port_num;
2188
2189 status = be_mcc_notify_wait(adapter);
2190 if (!status) {
2191 struct be_cmd_resp_get_beacon_state *resp =
2192 embedded_payload(wrb);
03d28ffe 2193
fad9ab2c
SB		 2194 *state = resp->beacon_state;
2195 }
2196
713d0394 2197err:
fad9ab2c
SB		 2198 spin_unlock_bh(&adapter->mcc_lock);
2199 return status;
2200}
2201
e36edd9d
ML		 2202/* Uses sync mcc */
2203int be_cmd_read_port_transceiver_data(struct be_adapter *adapter,
2204 u8 page_num, u8 *data)
2205{
2206 struct be_dma_mem cmd;
2207 struct be_mcc_wrb *wrb;
2208 struct be_cmd_req_port_type *req;
2209 int status;
2210
2211 if (page_num > TR_PAGE_A2)
2212 return -EINVAL;
2213
2214 cmd.size = sizeof(struct be_cmd_resp_port_type);
2215 cmd.va = pci_alloc_consistent(adapter->pdev, cmd.size, &cmd.dma);
2216 if (!cmd.va) {
2217 dev_err(&adapter->pdev->dev, "Memory allocation failed\n");
2218 return -ENOMEM;
2219 }
2220 memset(cmd.va, 0, cmd.size);
2221
2222 spin_lock_bh(&adapter->mcc_lock);
2223
2224 wrb = wrb_from_mccq(adapter);
2225 if (!wrb) {
2226 status = -EBUSY;
2227 goto err;
2228 }
2229 req = cmd.va;
2230
2231 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2232 OPCODE_COMMON_READ_TRANSRECV_DATA,
2233 cmd.size, wrb, &cmd);
2234
2235 req->port = cpu_to_le32(adapter->hba_port_num);
2236 req->page_num = cpu_to_le32(page_num);
2237 status = be_mcc_notify_wait(adapter);
2238 if (!status) {
2239 struct be_cmd_resp_port_type *resp = cmd.va;
2240
2241 memcpy(data, resp->page_data, PAGE_DATA_LEN);
2242 }
2243err:
2244 spin_unlock_bh(&adapter->mcc_lock);
2245 pci_free_consistent(adapter->pdev, cmd.size, cmd.va, cmd.dma);
2246 return status;
2247}
2248
485bf569 2249int lancer_cmd_write_object(struct be_adapter *adapter, struct be_dma_mem *cmd,
f67ef7ba
PR		 2250 u32 data_size, u32 data_offset,
2251 const char *obj_name, u32 *data_written,
2252 u8 *change_status, u8 *addn_status)
485bf569
SN		 2253{
2254 struct be_mcc_wrb *wrb;
2255 struct lancer_cmd_req_write_object *req;
2256 struct lancer_cmd_resp_write_object *resp;
2257 void *ctxt = NULL;
2258 int status;
2259
2260 spin_lock_bh(&adapter->mcc_lock);
2261 adapter->flash_status = 0;
2262
2263 wrb = wrb_from_mccq(adapter);
2264 if (!wrb) {
2265 status = -EBUSY;
2266 goto err_unlock;
2267 }
2268
2269 req = embedded_payload(wrb);
2270
106df1e3 2271 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 2272 OPCODE_COMMON_WRITE_OBJECT,
2273 sizeof(struct lancer_cmd_req_write_object), wrb,
2274 NULL);
485bf569
SN		 2275
2276 ctxt = &req->context;
2277 AMAP_SET_BITS(struct amap_lancer_write_obj_context,
a2cc4e0b 2278 write_length, ctxt, data_size);
485bf569
SN		 2279
2280 if (data_size == 0)
2281 AMAP_SET_BITS(struct amap_lancer_write_obj_context,
a2cc4e0b 2282 eof, ctxt, 1);
485bf569
SN		 2283 else
2284 AMAP_SET_BITS(struct amap_lancer_write_obj_context,
a2cc4e0b 2285 eof, ctxt, 0);
485bf569
SN		 2286
2287 be_dws_cpu_to_le(ctxt, sizeof(req->context));
2288 req->write_offset = cpu_to_le32(data_offset);
242eb470 2289 strlcpy(req->object_name, obj_name, sizeof(req->object_name));
485bf569
SN		 2290 req->descriptor_count = cpu_to_le32(1);
2291 req->buf_len = cpu_to_le32(data_size);
2292 req->addr_low = cpu_to_le32((cmd->dma +
a2cc4e0b
SP		 2293 sizeof(struct lancer_cmd_req_write_object))
2294 & 0xFFFFFFFF);
485bf569
SN		 2295 req->addr_high = cpu_to_le32(upper_32_bits(cmd->dma +
2296 sizeof(struct lancer_cmd_req_write_object)));
2297
2298 be_mcc_notify(adapter);
2299 spin_unlock_bh(&adapter->mcc_lock);
2300
5eeff635 2301 if (!wait_for_completion_timeout(&adapter->et_cmd_compl,
701962d0 2302 msecs_to_jiffies(60000)))
fd45160c 2303 status = -ETIMEDOUT;
485bf569
SN		 2304 else
2305 status = adapter->flash_status;
2306
2307 resp = embedded_payload(wrb);
f67ef7ba 2308 if (!status) {
485bf569 2309 *data_written = le32_to_cpu(resp->actual_write_len);
f67ef7ba
PR		 2310 *change_status = resp->change_status;
2311 } else {
485bf569 2312 *addn_status = resp->additional_status;
f67ef7ba 2313 }
485bf569
SN		 2314
2315 return status;
2316
2317err_unlock:
2318 spin_unlock_bh(&adapter->mcc_lock);
2319 return status;
2320}
2321
6809cee0
RN		 2322int be_cmd_query_cable_type(struct be_adapter *adapter)
2323{
2324 u8 page_data[PAGE_DATA_LEN];
2325 int status;
2326
2327 status = be_cmd_read_port_transceiver_data(adapter, TR_PAGE_A0,
2328 page_data);
2329 if (!status) {
2330 switch (adapter->phy.interface_type) {
2331 case PHY_TYPE_QSFP:
2332 adapter->phy.cable_type =
2333 page_data[QSFP_PLUS_CABLE_TYPE_OFFSET];
2334 break;
2335 case PHY_TYPE_SFP_PLUS_10GB:
2336 adapter->phy.cable_type =
2337 page_data[SFP_PLUS_CABLE_TYPE_OFFSET];
2338 break;
2339 default:
2340 adapter->phy.cable_type = 0;
2341 break;
2342 }
2343 }
2344 return status;
2345}
2346
f0613380
KA		 2347int lancer_cmd_delete_object(struct be_adapter *adapter, const char *obj_name)
2348{
2349 struct lancer_cmd_req_delete_object *req;
2350 struct be_mcc_wrb *wrb;
2351 int status;
2352
2353 spin_lock_bh(&adapter->mcc_lock);
2354
2355 wrb = wrb_from_mccq(adapter);
2356 if (!wrb) {
2357 status = -EBUSY;
2358 goto err;
2359 }
2360
2361 req = embedded_payload(wrb);
2362
2363 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2364 OPCODE_COMMON_DELETE_OBJECT,
2365 sizeof(*req), wrb, NULL);
2366
242eb470 2367 strlcpy(req->object_name, obj_name, sizeof(req->object_name));
f0613380
KA		 2368
2369 status = be_mcc_notify_wait(adapter);
2370err:
2371 spin_unlock_bh(&adapter->mcc_lock);
2372 return status;
2373}
2374
de49bd5a 2375int lancer_cmd_read_object(struct be_adapter *adapter, struct be_dma_mem *cmd,
a2cc4e0b
SP		 2376 u32 data_size, u32 data_offset, const char *obj_name,
2377 u32 *data_read, u32 *eof, u8 *addn_status)
de49bd5a
PR		 2378{
2379 struct be_mcc_wrb *wrb;
2380 struct lancer_cmd_req_read_object *req;
2381 struct lancer_cmd_resp_read_object *resp;
2382 int status;
2383
2384 spin_lock_bh(&adapter->mcc_lock);
2385
2386 wrb = wrb_from_mccq(adapter);
2387 if (!wrb) {
2388 status = -EBUSY;
2389 goto err_unlock;
2390 }
2391
2392 req = embedded_payload(wrb);
2393
2394 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 2395 OPCODE_COMMON_READ_OBJECT,
2396 sizeof(struct lancer_cmd_req_read_object), wrb,
2397 NULL);
de49bd5a
PR		 2398
2399 req->desired_read_len = cpu_to_le32(data_size);
2400 req->read_offset = cpu_to_le32(data_offset);
2401 strcpy(req->object_name, obj_name);
2402 req->descriptor_count = cpu_to_le32(1);
2403 req->buf_len = cpu_to_le32(data_size);
2404 req->addr_low = cpu_to_le32((cmd->dma & 0xFFFFFFFF));
2405 req->addr_high = cpu_to_le32(upper_32_bits(cmd->dma));
2406
2407 status = be_mcc_notify_wait(adapter);
2408
2409 resp = embedded_payload(wrb);
2410 if (!status) {
2411 *data_read = le32_to_cpu(resp->actual_read_len);
2412 *eof = le32_to_cpu(resp->eof);
2413 } else {
2414 *addn_status = resp->additional_status;
2415 }
2416
2417err_unlock:
2418 spin_unlock_bh(&adapter->mcc_lock);
2419 return status;
2420}
2421
84517482 2422int be_cmd_write_flashrom(struct be_adapter *adapter, struct be_dma_mem *cmd,
70a7b525
VV		 2423 u32 flash_type, u32 flash_opcode, u32 img_offset,
2424 u32 buf_size)
84517482 2425{
b31c50a7 2426 struct be_mcc_wrb *wrb;
3f0d4560 2427 struct be_cmd_write_flashrom *req;
84517482
AK		 2428 int status;
2429
b31c50a7 2430 spin_lock_bh(&adapter->mcc_lock);
dd131e76 2431 adapter->flash_status = 0;
b31c50a7
SP		 2432
2433 wrb = wrb_from_mccq(adapter);
713d0394
SP		 2434 if (!wrb) {
2435 status = -EBUSY;
2892d9c2 2436 goto err_unlock;
713d0394
SP		 2437 }
2438 req = cmd->va;
84517482 2439
106df1e3 2440 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 2441 OPCODE_COMMON_WRITE_FLASHROM, cmd->size, wrb,
2442 cmd);
84517482
AK		 2443
2444 req->params.op_type = cpu_to_le32(flash_type);
70a7b525
VV		 2445 if (flash_type == OPTYPE_OFFSET_SPECIFIED)
2446 req->params.offset = cpu_to_le32(img_offset);
2447
84517482
AK		 2448 req->params.op_code = cpu_to_le32(flash_opcode);
2449 req->params.data_buf_size = cpu_to_le32(buf_size);
2450
dd131e76
SB		 2451 be_mcc_notify(adapter);
2452 spin_unlock_bh(&adapter->mcc_lock);
2453
5eeff635
SR		 2454 if (!wait_for_completion_timeout(&adapter->et_cmd_compl,
2455 msecs_to_jiffies(40000)))
fd45160c 2456 status = -ETIMEDOUT;
dd131e76
SB		 2457 else
2458 status = adapter->flash_status;
84517482 2459
2892d9c2
DC		 2460 return status;
2461
2462err_unlock:
2463 spin_unlock_bh(&adapter->mcc_lock);
84517482
AK		 2464 return status;
2465}
fa9a6fed 2466
3f0d4560 2467int be_cmd_get_flash_crc(struct be_adapter *adapter, u8 *flashed_crc,
70a7b525 2468 u16 img_optype, u32 img_offset, u32 crc_offset)
fa9a6fed 2469{
be716446 2470 struct be_cmd_read_flash_crc *req;
70a7b525 2471 struct be_mcc_wrb *wrb;
fa9a6fed
SB		 2472 int status;
2473
2474 spin_lock_bh(&adapter->mcc_lock);
2475
2476 wrb = wrb_from_mccq(adapter);
713d0394
SP		 2477 if (!wrb) {
2478 status = -EBUSY;
2479 goto err;
2480 }
fa9a6fed
SB		 2481 req = embedded_payload(wrb);
2482
106df1e3 2483 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
be716446
PR		 2484 OPCODE_COMMON_READ_FLASHROM, sizeof(*req),
2485 wrb, NULL);
fa9a6fed 2486
70a7b525
VV		 2487 req->params.op_type = cpu_to_le32(img_optype);
2488 if (img_optype == OPTYPE_OFFSET_SPECIFIED)
2489 req->params.offset = cpu_to_le32(img_offset + crc_offset);
2490 else
2491 req->params.offset = cpu_to_le32(crc_offset);
2492
fa9a6fed 2493 req->params.op_code = cpu_to_le32(FLASHROM_OPER_REPORT);
8b93b710 2494 req->params.data_buf_size = cpu_to_le32(0x4);
fa9a6fed
SB		 2495
2496 status = be_mcc_notify_wait(adapter);
2497 if (!status)
be716446 2498 memcpy(flashed_crc, req->crc, 4);
fa9a6fed 2499
713d0394 2500err:
fa9a6fed
SB		 2501 spin_unlock_bh(&adapter->mcc_lock);
2502 return status;
2503}
71d8d1b5 2504
c196b02c 2505int be_cmd_enable_magic_wol(struct be_adapter *adapter, u8 *mac,
a2cc4e0b 2506 struct be_dma_mem *nonemb_cmd)
71d8d1b5
AK		 2507{
2508 struct be_mcc_wrb *wrb;
2509 struct be_cmd_req_acpi_wol_magic_config *req;
71d8d1b5
AK		 2510 int status;
2511
2512 spin_lock_bh(&adapter->mcc_lock);
2513
2514 wrb = wrb_from_mccq(adapter);
2515 if (!wrb) {
2516 status = -EBUSY;
2517 goto err;
2518 }
2519 req = nonemb_cmd->va;
71d8d1b5 2520
106df1e3 2521 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
a2cc4e0b
SP		 2522 OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG, sizeof(*req),
2523 wrb, nonemb_cmd);
71d8d1b5
AK		 2524 memcpy(req->magic_mac, mac, ETH_ALEN);
2525
71d8d1b5
AK		 2526 status = be_mcc_notify_wait(adapter);
2527
2528err:
2529 spin_unlock_bh(&adapter->mcc_lock);
2530 return status;
2531}
ff33a6e2 2532
fced9999
SB		 2533int be_cmd_set_loopback(struct be_adapter *adapter, u8 port_num,
2534 u8 loopback_type, u8 enable)
2535{
2536 struct be_mcc_wrb *wrb;
2537 struct be_cmd_req_set_lmode *req;
2538 int status;
2539
2540 spin_lock_bh(&adapter->mcc_lock);
2541
2542 wrb = wrb_from_mccq(adapter);
2543 if (!wrb) {
2544 status = -EBUSY;
2545 goto err;
2546 }
2547
2548 req = embedded_payload(wrb);
2549
106df1e3 2550 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
a2cc4e0b
SP		 2551 OPCODE_LOWLEVEL_SET_LOOPBACK_MODE, sizeof(*req),
2552 wrb, NULL);
fced9999
SB		 2553
2554 req->src_port = port_num;
2555 req->dest_port = port_num;
2556 req->loopback_type = loopback_type;
2557 req->loopback_state = enable;
2558
2559 status = be_mcc_notify_wait(adapter);
2560err:
2561 spin_unlock_bh(&adapter->mcc_lock);
2562 return status;
2563}
2564
ff33a6e2 2565int be_cmd_loopback_test(struct be_adapter *adapter, u32 port_num,
a2cc4e0b
SP		 2566 u32 loopback_type, u32 pkt_size, u32 num_pkts,
2567 u64 pattern)
ff33a6e2
S		 2568{
2569 struct be_mcc_wrb *wrb;
2570 struct be_cmd_req_loopback_test *req;
5eeff635 2571 struct be_cmd_resp_loopback_test *resp;
ff33a6e2
S		 2572 int status;
2573
2574 spin_lock_bh(&adapter->mcc_lock);
2575
2576 wrb = wrb_from_mccq(adapter);
2577 if (!wrb) {
2578 status = -EBUSY;
2579 goto err;
2580 }
2581
2582 req = embedded_payload(wrb);
2583
106df1e3 2584 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
a2cc4e0b
SP		 2585 OPCODE_LOWLEVEL_LOOPBACK_TEST, sizeof(*req), wrb,
2586 NULL);
ff33a6e2 2587
5eeff635 2588 req->hdr.timeout = cpu_to_le32(15);
ff33a6e2
S		 2589 req->pattern = cpu_to_le64(pattern);
2590 req->src_port = cpu_to_le32(port_num);
2591 req->dest_port = cpu_to_le32(port_num);
2592 req->pkt_size = cpu_to_le32(pkt_size);
2593 req->num_pkts = cpu_to_le32(num_pkts);
2594 req->loopback_type = cpu_to_le32(loopback_type);
2595
5eeff635
SR		 2596 be_mcc_notify(adapter);
2597
2598 spin_unlock_bh(&adapter->mcc_lock);
ff33a6e2 2599
5eeff635
SR		 2600 wait_for_completion(&adapter->et_cmd_compl);
2601 resp = embedded_payload(wrb);
2602 status = le32_to_cpu(resp->status);
2603
2604 return status;
ff33a6e2
S		 2605err:
2606 spin_unlock_bh(&adapter->mcc_lock);
2607 return status;
2608}
2609
2610int be_cmd_ddr_dma_test(struct be_adapter *adapter, u64 pattern,
a2cc4e0b 2611 u32 byte_cnt, struct be_dma_mem *cmd)
ff33a6e2
S		 2612{
2613 struct be_mcc_wrb *wrb;
2614 struct be_cmd_req_ddrdma_test *req;
ff33a6e2
S		 2615 int status;
2616 int i, j = 0;
2617
2618 spin_lock_bh(&adapter->mcc_lock);
2619
2620 wrb = wrb_from_mccq(adapter);
2621 if (!wrb) {
2622 status = -EBUSY;
2623 goto err;
2624 }
2625 req = cmd->va;
106df1e3 2626 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
a2cc4e0b
SP		 2627 OPCODE_LOWLEVEL_HOST_DDR_DMA, cmd->size, wrb,
2628 cmd);
ff33a6e2
S		 2629
2630 req->pattern = cpu_to_le64(pattern);
2631 req->byte_count = cpu_to_le32(byte_cnt);
2632 for (i = 0; i < byte_cnt; i++) {
2633 req->snd_buff[i] = (u8)(pattern >> (j*8));
2634 j++;
2635 if (j > 7)
2636 j = 0;
2637 }
2638
2639 status = be_mcc_notify_wait(adapter);
2640
2641 if (!status) {
2642 struct be_cmd_resp_ddrdma_test *resp;
03d28ffe 2643
ff33a6e2
S		 2644 resp = cmd->va;
2645 if ((memcmp(resp->rcv_buff, req->snd_buff, byte_cnt) != 0) ||
cd3307aa 2646 resp->snd_err) {
ff33a6e2
S		 2647 status = -1;
2648 }
2649 }
2650
2651err:
2652 spin_unlock_bh(&adapter->mcc_lock);
2653 return status;
2654}
368c0ca2 2655
c196b02c 2656int be_cmd_get_seeprom_data(struct be_adapter *adapter,
a2cc4e0b 2657 struct be_dma_mem *nonemb_cmd)
368c0ca2
SB		 2658{
2659 struct be_mcc_wrb *wrb;
2660 struct be_cmd_req_seeprom_read *req;
368c0ca2
SB		 2661 int status;
2662
2663 spin_lock_bh(&adapter->mcc_lock);
2664
2665 wrb = wrb_from_mccq(adapter);
e45ff01d
AK		 2666 if (!wrb) {
2667 status = -EBUSY;
2668 goto err;
2669 }
368c0ca2 2670 req = nonemb_cmd->va;
368c0ca2 2671
106df1e3 2672 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 2673 OPCODE_COMMON_SEEPROM_READ, sizeof(*req), wrb,
2674 nonemb_cmd);
368c0ca2
SB		 2675
2676 status = be_mcc_notify_wait(adapter);
2677
e45ff01d 2678err:
368c0ca2
SB		 2679 spin_unlock_bh(&adapter->mcc_lock);
2680 return status;
2681}
ee3cb629 2682
42f11cf2 2683int be_cmd_get_phy_info(struct be_adapter *adapter)
ee3cb629
AK		 2684{
2685 struct be_mcc_wrb *wrb;
2686 struct be_cmd_req_get_phy_info *req;
306f1348 2687 struct be_dma_mem cmd;
ee3cb629
AK		 2688 int status;
2689
f25b119c
PR		 2690 if (!be_cmd_allowed(adapter, OPCODE_COMMON_GET_PHY_DETAILS,
2691 CMD_SUBSYSTEM_COMMON))
2692 return -EPERM;
2693
ee3cb629
AK		 2694 spin_lock_bh(&adapter->mcc_lock);
2695
2696 wrb = wrb_from_mccq(adapter);
2697 if (!wrb) {
2698 status = -EBUSY;
2699 goto err;
2700 }
306f1348 2701 cmd.size = sizeof(struct be_cmd_req_get_phy_info);
a2cc4e0b 2702 cmd.va = pci_alloc_consistent(adapter->pdev, cmd.size, &cmd.dma);
306f1348
SP		 2703 if (!cmd.va) {
2704 dev_err(&adapter->pdev->dev, "Memory alloc failure\n");
2705 status = -ENOMEM;
2706 goto err;
2707 }
ee3cb629 2708
306f1348 2709 req = cmd.va;
ee3cb629 2710
106df1e3 2711 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 2712 OPCODE_COMMON_GET_PHY_DETAILS, sizeof(*req),
2713 wrb, &cmd);
ee3cb629
AK		 2714
2715 status = be_mcc_notify_wait(adapter);
306f1348
SP		 2716 if (!status) {
2717 struct be_phy_info *resp_phy_info =
2718 cmd.va + sizeof(struct be_cmd_req_hdr);
03d28ffe 2719
42f11cf2
AK		 2720 adapter->phy.phy_type = le16_to_cpu(resp_phy_info->phy_type);
2721 adapter->phy.interface_type =
306f1348 2722 le16_to_cpu(resp_phy_info->interface_type);
42f11cf2
AK		 2723 adapter->phy.auto_speeds_supported =
2724 le16_to_cpu(resp_phy_info->auto_speeds_supported);
2725 adapter->phy.fixed_speeds_supported =
2726 le16_to_cpu(resp_phy_info->fixed_speeds_supported);
2727 adapter->phy.misc_params =
2728 le32_to_cpu(resp_phy_info->misc_params);
68cb7e47
VV		 2729
2730 if (BE2_chip(adapter)) {
2731 adapter->phy.fixed_speeds_supported =
2732 BE_SUPPORTED_SPEED_10GBPS |
2733 BE_SUPPORTED_SPEED_1GBPS;
2734 }
306f1348 2735 }
a2cc4e0b 2736 pci_free_consistent(adapter->pdev, cmd.size, cmd.va, cmd.dma);
ee3cb629
AK		 2737err:
2738 spin_unlock_bh(&adapter->mcc_lock);
2739 return status;
2740}
e1d18735 2741
bc0ee163 2742static int be_cmd_set_qos(struct be_adapter *adapter, u32 bps, u32 domain)
e1d18735
AK		 2743{
2744 struct be_mcc_wrb *wrb;
2745 struct be_cmd_req_set_qos *req;
2746 int status;
2747
2748 spin_lock_bh(&adapter->mcc_lock);
2749
2750 wrb = wrb_from_mccq(adapter);
2751 if (!wrb) {
2752 status = -EBUSY;
2753 goto err;
2754 }
2755
2756 req = embedded_payload(wrb);
2757
106df1e3 2758 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b 2759 OPCODE_COMMON_SET_QOS, sizeof(*req), wrb, NULL);
e1d18735
AK		 2760
2761 req->hdr.domain = domain;
6bff57a7
AK		 2762 req->valid_bits = cpu_to_le32(BE_QOS_BITS_NIC);
2763 req->max_bps_nic = cpu_to_le32(bps);
e1d18735
AK		 2764
2765 status = be_mcc_notify_wait(adapter);
2766
2767err:
2768 spin_unlock_bh(&adapter->mcc_lock);
2769 return status;
2770}
9e1453c5
AK		 2771
2772int be_cmd_get_cntl_attributes(struct be_adapter *adapter)
2773{
2774 struct be_mcc_wrb *wrb;
2775 struct be_cmd_req_cntl_attribs *req;
2776 struct be_cmd_resp_cntl_attribs *resp;
9e1453c5
AK		 2777 int status;
2778 int payload_len = max(sizeof(*req), sizeof(*resp));
2779 struct mgmt_controller_attrib *attribs;
2780 struct be_dma_mem attribs_cmd;
2781
d98ef50f
SR		 2782 if (mutex_lock_interruptible(&adapter->mbox_lock))
2783 return -1;
2784
9e1453c5
AK		 2785 memset(&attribs_cmd, 0, sizeof(struct be_dma_mem));
2786 attribs_cmd.size = sizeof(struct be_cmd_resp_cntl_attribs);
2787 attribs_cmd.va = pci_alloc_consistent(adapter->pdev, attribs_cmd.size,
a2cc4e0b 2788 &attribs_cmd.dma);
9e1453c5 2789 if (!attribs_cmd.va) {
a2cc4e0b 2790 dev_err(&adapter->pdev->dev, "Memory allocation failure\n");
d98ef50f
SR		 2791 status = -ENOMEM;
2792 goto err;
9e1453c5
AK		 2793 }
2794
9e1453c5
AK		 2795 wrb = wrb_from_mbox(adapter);
2796 if (!wrb) {
2797 status = -EBUSY;
2798 goto err;
2799 }
2800 req = attribs_cmd.va;
9e1453c5 2801
106df1e3 2802 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 2803 OPCODE_COMMON_GET_CNTL_ATTRIBUTES, payload_len,
2804 wrb, &attribs_cmd);
9e1453c5
AK		 2805
2806 status = be_mbox_notify_wait(adapter);
2807 if (!status) {
43d620c8 2808 attribs = attribs_cmd.va + sizeof(struct be_cmd_resp_hdr);
9e1453c5
AK		 2809 adapter->hba_port_num = attribs->hba_attribs.phy_port;
2810 }
2811
2812err:
2813 mutex_unlock(&adapter->mbox_lock);
d98ef50f
SR		 2814 if (attribs_cmd.va)
2815 pci_free_consistent(adapter->pdev, attribs_cmd.size,
2816 attribs_cmd.va, attribs_cmd.dma);
9e1453c5
AK		 2817 return status;
2818}
2e588f84
SP		 2819
2820/* Uses mbox */
2dc1deb6 2821int be_cmd_req_native_mode(struct be_adapter *adapter)
2e588f84
SP		 2822{
2823 struct be_mcc_wrb *wrb;
2824 struct be_cmd_req_set_func_cap *req;
2825 int status;
2826
2827 if (mutex_lock_interruptible(&adapter->mbox_lock))
2828 return -1;
2829
2830 wrb = wrb_from_mbox(adapter);
2831 if (!wrb) {
2832 status = -EBUSY;
2833 goto err;
2834 }
2835
2836 req = embedded_payload(wrb);
2837
106df1e3 2838 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 2839 OPCODE_COMMON_SET_DRIVER_FUNCTION_CAP,
2840 sizeof(*req), wrb, NULL);
2e588f84
SP		 2841
2842 req->valid_cap_flags = cpu_to_le32(CAPABILITY_SW_TIMESTAMPS |
2843 CAPABILITY_BE3_NATIVE_ERX_API);
2844 req->cap_flags = cpu_to_le32(CAPABILITY_BE3_NATIVE_ERX_API);
2845
2846 status = be_mbox_notify_wait(adapter);
2847 if (!status) {
2848 struct be_cmd_resp_set_func_cap *resp = embedded_payload(wrb);
03d28ffe 2849
2e588f84
SP		 2850 adapter->be3_native = le32_to_cpu(resp->cap_flags) &
2851 CAPABILITY_BE3_NATIVE_ERX_API;
d379142b
SP		 2852 if (!adapter->be3_native)
2853 dev_warn(&adapter->pdev->dev,
2854 "adapter not in advanced mode\n");
2e588f84
SP		 2855 }
2856err:
2857 mutex_unlock(&adapter->mbox_lock);
2858 return status;
2859}
590c391d 2860
f25b119c
PR		 2861/* Get privilege(s) for a function */
2862int be_cmd_get_fn_privileges(struct be_adapter *adapter, u32 *privilege,
2863 u32 domain)
2864{
2865 struct be_mcc_wrb *wrb;
2866 struct be_cmd_req_get_fn_privileges *req;
2867 int status;
2868
2869 spin_lock_bh(&adapter->mcc_lock);
2870
2871 wrb = wrb_from_mccq(adapter);
2872 if (!wrb) {
2873 status = -EBUSY;
2874 goto err;
2875 }
2876
2877 req = embedded_payload(wrb);
2878
2879 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2880 OPCODE_COMMON_GET_FN_PRIVILEGES, sizeof(*req),
2881 wrb, NULL);
2882
2883 req->hdr.domain = domain;
2884
2885 status = be_mcc_notify_wait(adapter);
2886 if (!status) {
2887 struct be_cmd_resp_get_fn_privileges *resp =
2888 embedded_payload(wrb);
03d28ffe 2889
f25b119c 2890 *privilege = le32_to_cpu(resp->privilege_mask);
02308d74
SR		 2891
2892 /* In UMC mode FW does not return right privileges.
2893 * Override with correct privilege equivalent to PF.
2894 */
2895 if (BEx_chip(adapter) && be_is_mc(adapter) &&
2896 be_physfn(adapter))
2897 *privilege = MAX_PRIVILEGES;
f25b119c
PR		 2898 }
2899
2900err:
2901 spin_unlock_bh(&adapter->mcc_lock);
2902 return status;
2903}
2904
04a06028
SP		 2905/* Set privilege(s) for a function */
2906int be_cmd_set_fn_privileges(struct be_adapter *adapter, u32 privileges,
2907 u32 domain)
2908{
2909 struct be_mcc_wrb *wrb;
2910 struct be_cmd_req_set_fn_privileges *req;
2911 int status;
2912
2913 spin_lock_bh(&adapter->mcc_lock);
2914
2915 wrb = wrb_from_mccq(adapter);
2916 if (!wrb) {
2917 status = -EBUSY;
2918 goto err;
2919 }
2920
2921 req = embedded_payload(wrb);
2922 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2923 OPCODE_COMMON_SET_FN_PRIVILEGES, sizeof(*req),
2924 wrb, NULL);
2925 req->hdr.domain = domain;
2926 if (lancer_chip(adapter))
2927 req->privileges_lancer = cpu_to_le32(privileges);
2928 else
2929 req->privileges = cpu_to_le32(privileges);
2930
2931 status = be_mcc_notify_wait(adapter);
2932err:
2933 spin_unlock_bh(&adapter->mcc_lock);
2934 return status;
2935}
2936
5a712c13
SP		 2937/* pmac_id_valid: true => pmac_id is supplied and MAC address is requested.
2938 * pmac_id_valid: false => pmac_id or MAC address is requested.
2939 * If pmac_id is returned, pmac_id_valid is returned as true
2940 */
1578e777 2941int be_cmd_get_mac_from_list(struct be_adapter *adapter, u8 *mac,
b188f090
SR		 2942 bool *pmac_id_valid, u32 *pmac_id, u32 if_handle,
2943 u8 domain)
590c391d
PR		 2944{
2945 struct be_mcc_wrb *wrb;
2946 struct be_cmd_req_get_mac_list *req;
2947 int status;
2948 int mac_count;
e5e1ee89
PR		 2949 struct be_dma_mem get_mac_list_cmd;
2950 int i;
2951
2952 memset(&get_mac_list_cmd, 0, sizeof(struct be_dma_mem));
2953 get_mac_list_cmd.size = sizeof(struct be_cmd_resp_get_mac_list);
2954 get_mac_list_cmd.va = pci_alloc_consistent(adapter->pdev,
a2cc4e0b
SP		 2955 get_mac_list_cmd.size,
2956 &get_mac_list_cmd.dma);
e5e1ee89
PR		 2957
2958 if (!get_mac_list_cmd.va) {
2959 dev_err(&adapter->pdev->dev,
a2cc4e0b 2960 "Memory allocation failure during GET_MAC_LIST\n");
e5e1ee89
PR		 2961 return -ENOMEM;
2962 }
590c391d
PR		 2963
2964 spin_lock_bh(&adapter->mcc_lock);
2965
2966 wrb = wrb_from_mccq(adapter);
2967 if (!wrb) {
2968 status = -EBUSY;
e5e1ee89 2969 goto out;
590c391d 2970 }
e5e1ee89
PR		 2971
2972 req = get_mac_list_cmd.va;
590c391d
PR		 2973
2974 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
bf591f51
SP		 2975 OPCODE_COMMON_GET_MAC_LIST,
2976 get_mac_list_cmd.size, wrb, &get_mac_list_cmd);
590c391d 2977 req->hdr.domain = domain;
e5e1ee89 2978 req->mac_type = MAC_ADDRESS_TYPE_NETWORK;
5a712c13
SP		 2979 if (*pmac_id_valid) {
2980 req->mac_id = cpu_to_le32(*pmac_id);
b188f090 2981 req->iface_id = cpu_to_le16(if_handle);
5a712c13
SP		 2982 req->perm_override = 0;
2983 } else {
2984 req->perm_override = 1;
2985 }
590c391d
PR		 2986
2987 status = be_mcc_notify_wait(adapter);
2988 if (!status) {
2989 struct be_cmd_resp_get_mac_list *resp =
e5e1ee89 2990 get_mac_list_cmd.va;
5a712c13
SP		 2991
2992 if (*pmac_id_valid) {
2993 memcpy(mac, resp->macid_macaddr.mac_addr_id.macaddr,
2994 ETH_ALEN);
2995 goto out;
2996 }
2997
e5e1ee89
PR		 2998 mac_count = resp->true_mac_count + resp->pseudo_mac_count;
2999 /* Mac list returned could contain one or more active mac_ids
1578e777
PR		 3000 * or one or more true or pseudo permanant mac addresses.
3001 * If an active mac_id is present, return first active mac_id
3002 * found.
e5e1ee89 3003 */
590c391d 3004 for (i = 0; i < mac_count; i++) {
e5e1ee89
PR		 3005 struct get_list_macaddr *mac_entry;
3006 u16 mac_addr_size;
3007 u32 mac_id;
3008
3009 mac_entry = &resp->macaddr_list[i];
3010 mac_addr_size = le16_to_cpu(mac_entry->mac_addr_size);
3011 /* mac_id is a 32 bit value and mac_addr size
3012 * is 6 bytes
3013 */
3014 if (mac_addr_size == sizeof(u32)) {
5a712c13 3015 *pmac_id_valid = true;
e5e1ee89
PR		 3016 mac_id = mac_entry->mac_addr_id.s_mac_id.mac_id;
3017 *pmac_id = le32_to_cpu(mac_id);
3018 goto out;
590c391d 3019 }
590c391d 3020 }
1578e777 3021 /* If no active mac_id found, return first mac addr */
5a712c13 3022 *pmac_id_valid = false;
e5e1ee89 3023 memcpy(mac, resp->macaddr_list[0].mac_addr_id.macaddr,
a2cc4e0b 3024 ETH_ALEN);
590c391d
PR		 3025 }
3026
e5e1ee89 3027out:
590c391d 3028 spin_unlock_bh(&adapter->mcc_lock);
e5e1ee89 3029 pci_free_consistent(adapter->pdev, get_mac_list_cmd.size,
a2cc4e0b 3030 get_mac_list_cmd.va, get_mac_list_cmd.dma);
590c391d
PR		 3031 return status;
3032}
3033
a2cc4e0b
SP		 3034int be_cmd_get_active_mac(struct be_adapter *adapter, u32 curr_pmac_id,
3035 u8 *mac, u32 if_handle, bool active, u32 domain)
5a712c13 3036{
b188f090
SR		 3037 if (!active)
3038 be_cmd_get_mac_from_list(adapter, mac, &active, &curr_pmac_id,
3039 if_handle, domain);
3175d8c2 3040 if (BEx_chip(adapter))
5a712c13 3041 return be_cmd_mac_addr_query(adapter, mac, false,
b188f090 3042 if_handle, curr_pmac_id);
3175d8c2
SP		 3043 else
3044 /* Fetch the MAC address using pmac_id */
3045 return be_cmd_get_mac_from_list(adapter, mac, &active,
b188f090
SR		 3046 &curr_pmac_id,
3047 if_handle, domain);
5a712c13
SP		 3048}
3049
95046b92
SP		 3050int be_cmd_get_perm_mac(struct be_adapter *adapter, u8 *mac)
3051{
3052 int status;
3053 bool pmac_valid = false;
3054
3055 memset(mac, 0, ETH_ALEN);
3056
3175d8c2
SP		 3057 if (BEx_chip(adapter)) {
3058 if (be_physfn(adapter))
3059 status = be_cmd_mac_addr_query(adapter, mac, true, 0,
3060 0);
3061 else
3062 status = be_cmd_mac_addr_query(adapter, mac, false,
3063 adapter->if_handle, 0);
3064 } else {
95046b92 3065 status = be_cmd_get_mac_from_list(adapter, mac, &pmac_valid,
b188f090 3066 NULL, adapter->if_handle, 0);
3175d8c2
SP		 3067 }
3068
95046b92
SP		 3069 return status;
3070}
3071
590c391d
PR		 3072/* Uses synchronous MCCQ */
3073int be_cmd_set_mac_list(struct be_adapter *adapter, u8 *mac_array,
3074 u8 mac_count, u32 domain)
3075{
3076 struct be_mcc_wrb *wrb;
3077 struct be_cmd_req_set_mac_list *req;
3078 int status;
3079 struct be_dma_mem cmd;
3080
3081 memset(&cmd, 0, sizeof(struct be_dma_mem));
3082 cmd.size = sizeof(struct be_cmd_req_set_mac_list);
3083 cmd.va = dma_alloc_coherent(&adapter->pdev->dev, cmd.size,
a2cc4e0b 3084 &cmd.dma, GFP_KERNEL);
d0320f75 3085 if (!cmd.va)
590c391d 3086 return -ENOMEM;
590c391d
PR		 3087
3088 spin_lock_bh(&adapter->mcc_lock);
3089
3090 wrb = wrb_from_mccq(adapter);
3091 if (!wrb) {
3092 status = -EBUSY;
3093 goto err;
3094 }
3095
3096 req = cmd.va;
3097 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 3098 OPCODE_COMMON_SET_MAC_LIST, sizeof(*req),
3099 wrb, &cmd);
590c391d
PR		 3100
3101 req->hdr.domain = domain;
3102 req->mac_count = mac_count;
3103 if (mac_count)
3104 memcpy(req->mac, mac_array, ETH_ALEN*mac_count);
3105
3106 status = be_mcc_notify_wait(adapter);
3107
3108err:
a2cc4e0b 3109 dma_free_coherent(&adapter->pdev->dev, cmd.size, cmd.va, cmd.dma);
590c391d
PR		 3110 spin_unlock_bh(&adapter->mcc_lock);
3111 return status;
3112}
4762f6ce 3113
3175d8c2
SP		 3114/* Wrapper to delete any active MACs and provision the new mac.
3115 * Changes to MAC_LIST are allowed iff none of the MAC addresses in the
3116 * current list are active.
3117 */
3118int be_cmd_set_mac(struct be_adapter *adapter, u8 *mac, int if_id, u32 dom)
3119{
3120 bool active_mac = false;
3121 u8 old_mac[ETH_ALEN];
3122 u32 pmac_id;
3123 int status;
3124
3125 status = be_cmd_get_mac_from_list(adapter, old_mac, &active_mac,
b188f090
SR		 3126 &pmac_id, if_id, dom);
3127
3175d8c2
SP		 3128 if (!status && active_mac)
3129 be_cmd_pmac_del(adapter, if_id, pmac_id, dom);
3130
3131 return be_cmd_set_mac_list(adapter, mac, mac ? 1 : 0, dom);
3132}
3133
f1f3ee1b 3134int be_cmd_set_hsw_config(struct be_adapter *adapter, u16 pvid,
a77dcb8c 3135 u32 domain, u16 intf_id, u16 hsw_mode)
f1f3ee1b
AK		 3136{
3137 struct be_mcc_wrb *wrb;
3138 struct be_cmd_req_set_hsw_config *req;
3139 void *ctxt;
3140 int status;
3141
3142 spin_lock_bh(&adapter->mcc_lock);
3143
3144 wrb = wrb_from_mccq(adapter);
3145 if (!wrb) {
3146 status = -EBUSY;
3147 goto err;
3148 }
3149
3150 req = embedded_payload(wrb);
3151 ctxt = &req->context;
3152
3153 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 3154 OPCODE_COMMON_SET_HSW_CONFIG, sizeof(*req), wrb,
3155 NULL);
f1f3ee1b
AK		 3156
3157 req->hdr.domain = domain;
3158 AMAP_SET_BITS(struct amap_set_hsw_context, interface_id, ctxt, intf_id);
3159 if (pvid) {
3160 AMAP_SET_BITS(struct amap_set_hsw_context, pvid_valid, ctxt, 1);
3161 AMAP_SET_BITS(struct amap_set_hsw_context, pvid, ctxt, pvid);
3162 }
a77dcb8c
AK		 3163 if (!BEx_chip(adapter) && hsw_mode) {
3164 AMAP_SET_BITS(struct amap_set_hsw_context, interface_id,
3165 ctxt, adapter->hba_port_num);
3166 AMAP_SET_BITS(struct amap_set_hsw_context, pport, ctxt, 1);
3167 AMAP_SET_BITS(struct amap_set_hsw_context, port_fwd_type,
3168 ctxt, hsw_mode);
3169 }
f1f3ee1b
AK		 3170
3171 be_dws_cpu_to_le(req->context, sizeof(req->context));
3172 status = be_mcc_notify_wait(adapter);
3173
3174err:
3175 spin_unlock_bh(&adapter->mcc_lock);
3176 return status;
3177}
3178
3179/* Get Hyper switch config */
3180int be_cmd_get_hsw_config(struct be_adapter *adapter, u16 *pvid,
a77dcb8c 3181 u32 domain, u16 intf_id, u8 *mode)
f1f3ee1b
AK		 3182{
3183 struct be_mcc_wrb *wrb;
3184 struct be_cmd_req_get_hsw_config *req;
3185 void *ctxt;
3186 int status;
3187 u16 vid;
3188
3189 spin_lock_bh(&adapter->mcc_lock);
3190
3191 wrb = wrb_from_mccq(adapter);
3192 if (!wrb) {
3193 status = -EBUSY;
3194 goto err;
3195 }
3196
3197 req = embedded_payload(wrb);
3198 ctxt = &req->context;
3199
3200 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 3201 OPCODE_COMMON_GET_HSW_CONFIG, sizeof(*req), wrb,
3202 NULL);
f1f3ee1b
AK		 3203
3204 req->hdr.domain = domain;
a77dcb8c
AK		 3205 AMAP_SET_BITS(struct amap_get_hsw_req_context, interface_id,
3206 ctxt, intf_id);
f1f3ee1b 3207 AMAP_SET_BITS(struct amap_get_hsw_req_context, pvid_valid, ctxt, 1);
a77dcb8c 3208
2c07c1d7 3209 if (!BEx_chip(adapter) && mode) {
a77dcb8c
AK		 3210 AMAP_SET_BITS(struct amap_get_hsw_req_context, interface_id,
3211 ctxt, adapter->hba_port_num);
3212 AMAP_SET_BITS(struct amap_get_hsw_req_context, pport, ctxt, 1);
3213 }
f1f3ee1b
AK		 3214 be_dws_cpu_to_le(req->context, sizeof(req->context));
3215
3216 status = be_mcc_notify_wait(adapter);
3217 if (!status) {
3218 struct be_cmd_resp_get_hsw_config *resp =
3219 embedded_payload(wrb);
03d28ffe 3220
a2cc4e0b 3221 be_dws_le_to_cpu(&resp->context, sizeof(resp->context));
f1f3ee1b 3222 vid = AMAP_GET_BITS(struct amap_get_hsw_resp_context,
a2cc4e0b 3223 pvid, &resp->context);
a77dcb8c
AK		 3224 if (pvid)
3225 *pvid = le16_to_cpu(vid);
3226 if (mode)
3227 *mode = AMAP_GET_BITS(struct amap_get_hsw_resp_context,
3228 port_fwd_type, &resp->context);
f1f3ee1b
AK		 3229 }
3230
3231err:
3232 spin_unlock_bh(&adapter->mcc_lock);
3233 return status;
3234}
3235
f7062ee5
SP		 3236static bool be_is_wol_excluded(struct be_adapter *adapter)
3237{
3238 struct pci_dev *pdev = adapter->pdev;
3239
3240 if (!be_physfn(adapter))
3241 return true;
3242
3243 switch (pdev->subsystem_device) {
3244 case OC_SUBSYS_DEVICE_ID1:
3245 case OC_SUBSYS_DEVICE_ID2:
3246 case OC_SUBSYS_DEVICE_ID3:
3247 case OC_SUBSYS_DEVICE_ID4:
3248 return true;
3249 default:
3250 return false;
3251 }
3252}
3253
4762f6ce
AK		 3254int be_cmd_get_acpi_wol_cap(struct be_adapter *adapter)
3255{
3256 struct be_mcc_wrb *wrb;
3257 struct be_cmd_req_acpi_wol_magic_config_v1 *req;
76a9e08e 3258 int status = 0;
4762f6ce
AK		 3259 struct be_dma_mem cmd;
3260
f25b119c
PR		 3261 if (!be_cmd_allowed(adapter, OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG,
3262 CMD_SUBSYSTEM_ETH))
3263 return -EPERM;
3264
76a9e08e
SR		 3265 if (be_is_wol_excluded(adapter))
3266 return status;
3267
d98ef50f
SR		 3268 if (mutex_lock_interruptible(&adapter->mbox_lock))
3269 return -1;
3270
4762f6ce
AK		 3271 memset(&cmd, 0, sizeof(struct be_dma_mem));
3272 cmd.size = sizeof(struct be_cmd_resp_acpi_wol_magic_config_v1);
a2cc4e0b 3273 cmd.va = pci_alloc_consistent(adapter->pdev, cmd.size, &cmd.dma);
4762f6ce 3274 if (!cmd.va) {
a2cc4e0b 3275 dev_err(&adapter->pdev->dev, "Memory allocation failure\n");
d98ef50f
SR		 3276 status = -ENOMEM;
3277 goto err;
4762f6ce
AK		 3278 }
3279
4762f6ce
AK		 3280 wrb = wrb_from_mbox(adapter);
3281 if (!wrb) {
3282 status = -EBUSY;
3283 goto err;
3284 }
3285
3286 req = cmd.va;
3287
3288 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
3289 OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG,
76a9e08e 3290 sizeof(*req), wrb, &cmd);
4762f6ce
AK		 3291
3292 req->hdr.version = 1;
3293 req->query_options = BE_GET_WOL_CAP;
3294
3295 status = be_mbox_notify_wait(adapter);
3296 if (!status) {
3297 struct be_cmd_resp_acpi_wol_magic_config_v1 *resp;
03d28ffe 3298
504fbf1e 3299 resp = (struct be_cmd_resp_acpi_wol_magic_config_v1 *)cmd.va;
4762f6ce 3300
4762f6ce 3301 adapter->wol_cap = resp->wol_settings;
76a9e08e
SR		 3302 if (adapter->wol_cap & BE_WOL_CAP)
3303 adapter->wol_en = true;
4762f6ce
AK		 3304 }
3305err:
3306 mutex_unlock(&adapter->mbox_lock);
d98ef50f
SR		 3307 if (cmd.va)
3308 pci_free_consistent(adapter->pdev, cmd.size, cmd.va, cmd.dma);
4762f6ce 3309 return status;
941a77d5
SK		 3310
3311}
baaa08d1
VV		 3312
3313int be_cmd_set_fw_log_level(struct be_adapter *adapter, u32 level)
3314{
3315 struct be_dma_mem extfat_cmd;
3316 struct be_fat_conf_params *cfgs;
3317 int status;
3318 int i, j;
3319
3320 memset(&extfat_cmd, 0, sizeof(struct be_dma_mem));
3321 extfat_cmd.size = sizeof(struct be_cmd_resp_get_ext_fat_caps);
3322 extfat_cmd.va = pci_alloc_consistent(adapter->pdev, extfat_cmd.size,
3323 &extfat_cmd.dma);
3324 if (!extfat_cmd.va)
3325 return -ENOMEM;
3326
3327 status = be_cmd_get_ext_fat_capabilites(adapter, &extfat_cmd);
3328 if (status)
3329 goto err;
3330
3331 cfgs = (struct be_fat_conf_params *)
3332 (extfat_cmd.va + sizeof(struct be_cmd_resp_hdr));
3333 for (i = 0; i < le32_to_cpu(cfgs->num_modules); i++) {
3334 u32 num_modes = le32_to_cpu(cfgs->module[i].num_modes);
03d28ffe 3335
baaa08d1
VV		 3336 for (j = 0; j < num_modes; j++) {
3337 if (cfgs->module[i].trace_lvl[j].mode == MODE_UART)
3338 cfgs->module[i].trace_lvl[j].dbg_lvl =
3339 cpu_to_le32(level);
3340 }
3341 }
3342
3343 status = be_cmd_set_ext_fat_capabilites(adapter, &extfat_cmd, cfgs);
3344err:
3345 pci_free_consistent(adapter->pdev, extfat_cmd.size, extfat_cmd.va,
3346 extfat_cmd.dma);
3347 return status;
3348}
3349
3350int be_cmd_get_fw_log_level(struct be_adapter *adapter)
3351{
3352 struct be_dma_mem extfat_cmd;
3353 struct be_fat_conf_params *cfgs;
3354 int status, j;
3355 int level = 0;
3356
3357 memset(&extfat_cmd, 0, sizeof(struct be_dma_mem));
3358 extfat_cmd.size = sizeof(struct be_cmd_resp_get_ext_fat_caps);
3359 extfat_cmd.va = pci_alloc_consistent(adapter->pdev, extfat_cmd.size,
3360 &extfat_cmd.dma);
3361
3362 if (!extfat_cmd.va) {
3363 dev_err(&adapter->pdev->dev, "%s: Memory allocation failure\n",
3364 __func__);
3365 goto err;
3366 }
3367
3368 status = be_cmd_get_ext_fat_capabilites(adapter, &extfat_cmd);
3369 if (!status) {
3370 cfgs = (struct be_fat_conf_params *)(extfat_cmd.va +
3371 sizeof(struct be_cmd_resp_hdr));
03d28ffe 3372
baaa08d1
VV		 3373 for (j = 0; j < le32_to_cpu(cfgs->module[0].num_modes); j++) {
3374 if (cfgs->module[0].trace_lvl[j].mode == MODE_UART)
3375 level = cfgs->module[0].trace_lvl[j].dbg_lvl;
3376 }
3377 }
3378 pci_free_consistent(adapter->pdev, extfat_cmd.size, extfat_cmd.va,
3379 extfat_cmd.dma);
3380err:
3381 return level;
3382}
3383
941a77d5
SK		 3384int be_cmd_get_ext_fat_capabilites(struct be_adapter *adapter,
3385 struct be_dma_mem *cmd)
3386{
3387 struct be_mcc_wrb *wrb;
3388 struct be_cmd_req_get_ext_fat_caps *req;
3389 int status;
3390
3391 if (mutex_lock_interruptible(&adapter->mbox_lock))
3392 return -1;
3393
3394 wrb = wrb_from_mbox(adapter);
3395 if (!wrb) {
3396 status = -EBUSY;
3397 goto err;
3398 }
3399
3400 req = cmd->va;
3401 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3402 OPCODE_COMMON_GET_EXT_FAT_CAPABILITES,
3403 cmd->size, wrb, cmd);
3404 req->parameter_type = cpu_to_le32(1);
3405
3406 status = be_mbox_notify_wait(adapter);
3407err:
3408 mutex_unlock(&adapter->mbox_lock);
3409 return status;
3410}
3411
3412int be_cmd_set_ext_fat_capabilites(struct be_adapter *adapter,
3413 struct be_dma_mem *cmd,
3414 struct be_fat_conf_params *configs)
3415{
3416 struct be_mcc_wrb *wrb;
3417 struct be_cmd_req_set_ext_fat_caps *req;
3418 int status;
3419
3420 spin_lock_bh(&adapter->mcc_lock);
3421
3422 wrb = wrb_from_mccq(adapter);
3423 if (!wrb) {
3424 status = -EBUSY;
3425 goto err;
3426 }
3427
3428 req = cmd->va;
3429 memcpy(&req->set_params, configs, sizeof(struct be_fat_conf_params));
3430 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3431 OPCODE_COMMON_SET_EXT_FAT_CAPABILITES,
3432 cmd->size, wrb, cmd);
3433
3434 status = be_mcc_notify_wait(adapter);
3435err:
3436 spin_unlock_bh(&adapter->mcc_lock);
3437 return status;
4762f6ce 3438}
6a4ab669 3439
b4e32a71
PR		 3440int be_cmd_query_port_name(struct be_adapter *adapter, u8 *port_name)
3441{
3442 struct be_mcc_wrb *wrb;
3443 struct be_cmd_req_get_port_name *req;
3444 int status;
3445
3446 if (!lancer_chip(adapter)) {
3447 *port_name = adapter->hba_port_num + '0';
3448 return 0;
3449 }
3450
3451 spin_lock_bh(&adapter->mcc_lock);
3452
3453 wrb = wrb_from_mccq(adapter);
3454 if (!wrb) {
3455 status = -EBUSY;
3456 goto err;
3457 }
3458
3459 req = embedded_payload(wrb);
3460
3461 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3462 OPCODE_COMMON_GET_PORT_NAME, sizeof(*req), wrb,
3463 NULL);
3464 req->hdr.version = 1;
3465
3466 status = be_mcc_notify_wait(adapter);
3467 if (!status) {
3468 struct be_cmd_resp_get_port_name *resp = embedded_payload(wrb);
03d28ffe 3469
b4e32a71
PR		 3470 *port_name = resp->port_name[adapter->hba_port_num];
3471 } else {
3472 *port_name = adapter->hba_port_num + '0';
3473 }
3474err:
3475 spin_unlock_bh(&adapter->mcc_lock);
3476 return status;
3477}
3478
10cccf60
VV		 3479/* Descriptor type */
3480enum {
3481 FUNC_DESC = 1,
3482 VFT_DESC = 2
3483};
3484
3485static struct be_nic_res_desc *be_get_nic_desc(u8 *buf, u32 desc_count,
3486 int desc_type)
abb93951 3487{
150d58c7 3488 struct be_res_desc_hdr *hdr = (struct be_res_desc_hdr *)buf;
10cccf60 3489 struct be_nic_res_desc *nic;
abb93951
PR		 3490 int i;
3491
3492 for (i = 0; i < desc_count; i++) {
150d58c7 3493 if (hdr->desc_type == NIC_RESOURCE_DESC_TYPE_V0 ||
10cccf60
VV		 3494 hdr->desc_type == NIC_RESOURCE_DESC_TYPE_V1) {
3495 nic = (struct be_nic_res_desc *)hdr;
3496 if (desc_type == FUNC_DESC ||
3497 (desc_type == VFT_DESC &&
3498 nic->flags & (1 << VFT_SHIFT)))
3499 return nic;
3500 }
abb93951 3501
150d58c7
VV		 3502 hdr->desc_len = hdr->desc_len ? : RESOURCE_DESC_SIZE_V0;
3503 hdr = (void *)hdr + hdr->desc_len;
abb93951 3504 }
150d58c7
VV		 3505 return NULL;
3506}
3507
10cccf60
VV		 3508static struct be_nic_res_desc *be_get_vft_desc(u8 *buf, u32 desc_count)
3509{
3510 return be_get_nic_desc(buf, desc_count, VFT_DESC);
3511}
3512
3513static struct be_nic_res_desc *be_get_func_nic_desc(u8 *buf, u32 desc_count)
3514{
3515 return be_get_nic_desc(buf, desc_count, FUNC_DESC);
3516}
3517
150d58c7
VV		 3518static struct be_pcie_res_desc *be_get_pcie_desc(u8 devfn, u8 *buf,
3519 u32 desc_count)
3520{
3521 struct be_res_desc_hdr *hdr = (struct be_res_desc_hdr *)buf;
3522 struct be_pcie_res_desc *pcie;
3523 int i;
3524
3525 for (i = 0; i < desc_count; i++) {
3526 if ((hdr->desc_type == PCIE_RESOURCE_DESC_TYPE_V0 ||
3527 hdr->desc_type == PCIE_RESOURCE_DESC_TYPE_V1)) {
3528 pcie = (struct be_pcie_res_desc *)hdr;
3529 if (pcie->pf_num == devfn)
3530 return pcie;
3531 }
abb93951 3532
150d58c7
VV		 3533 hdr->desc_len = hdr->desc_len ? : RESOURCE_DESC_SIZE_V0;
3534 hdr = (void *)hdr + hdr->desc_len;
3535 }
950e2958 3536 return NULL;
abb93951
PR		 3537}
3538
f93f160b
VV		 3539static struct be_port_res_desc *be_get_port_desc(u8 *buf, u32 desc_count)
3540{
3541 struct be_res_desc_hdr *hdr = (struct be_res_desc_hdr *)buf;
3542 int i;
3543
3544 for (i = 0; i < desc_count; i++) {
3545 if (hdr->desc_type == PORT_RESOURCE_DESC_TYPE_V1)
3546 return (struct be_port_res_desc *)hdr;
3547
3548 hdr->desc_len = hdr->desc_len ? : RESOURCE_DESC_SIZE_V0;
3549 hdr = (void *)hdr + hdr->desc_len;
3550 }
3551 return NULL;
3552}
3553
92bf14ab
SP		 3554static void be_copy_nic_desc(struct be_resources *res,
3555 struct be_nic_res_desc *desc)
3556{
3557 res->max_uc_mac = le16_to_cpu(desc->unicast_mac_count);
3558 res->max_vlans = le16_to_cpu(desc->vlan_count);
3559 res->max_mcast_mac = le16_to_cpu(desc->mcast_mac_count);
3560 res->max_tx_qs = le16_to_cpu(desc->txq_count);
3561 res->max_rss_qs = le16_to_cpu(desc->rssq_count);
3562 res->max_rx_qs = le16_to_cpu(desc->rq_count);
3563 res->max_evt_qs = le16_to_cpu(desc->eq_count);
3564 /* Clear flags that driver is not interested in */
3565 res->if_cap_flags = le32_to_cpu(desc->cap_flags) &
3566 BE_IF_CAP_FLAGS_WANT;
3567 /* Need 1 RXQ as the default RXQ */
3568 if (res->max_rss_qs && res->max_rss_qs == res->max_rx_qs)
3569 res->max_rss_qs -= 1;
3570}
3571
abb93951 3572/* Uses Mbox */
92bf14ab 3573int be_cmd_get_func_config(struct be_adapter *adapter, struct be_resources *res)
abb93951
PR		 3574{
3575 struct be_mcc_wrb *wrb;
3576 struct be_cmd_req_get_func_config *req;
3577 int status;
3578 struct be_dma_mem cmd;
3579
d98ef50f
SR		 3580 if (mutex_lock_interruptible(&adapter->mbox_lock))
3581 return -1;
3582
abb93951
PR		 3583 memset(&cmd, 0, sizeof(struct be_dma_mem));
3584 cmd.size = sizeof(struct be_cmd_resp_get_func_config);
a2cc4e0b 3585 cmd.va = pci_alloc_consistent(adapter->pdev, cmd.size, &cmd.dma);
abb93951
PR		 3586 if (!cmd.va) {
3587 dev_err(&adapter->pdev->dev, "Memory alloc failure\n");
d98ef50f
SR		 3588 status = -ENOMEM;
3589 goto err;
abb93951 3590 }
abb93951
PR		 3591
3592 wrb = wrb_from_mbox(adapter);
3593 if (!wrb) {
3594 status = -EBUSY;
3595 goto err;
3596 }
3597
3598 req = cmd.va;
3599
3600 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3601 OPCODE_COMMON_GET_FUNC_CONFIG,
3602 cmd.size, wrb, &cmd);
3603
28710c55
KA		 3604 if (skyhawk_chip(adapter))
3605 req->hdr.version = 1;
3606
abb93951
PR		 3607 status = be_mbox_notify_wait(adapter);
3608 if (!status) {
3609 struct be_cmd_resp_get_func_config *resp = cmd.va;
3610 u32 desc_count = le32_to_cpu(resp->desc_count);
150d58c7 3611 struct be_nic_res_desc *desc;
abb93951 3612
10cccf60 3613 desc = be_get_func_nic_desc(resp->func_param, desc_count);
abb93951
PR		 3614 if (!desc) {
3615 status = -EINVAL;
3616 goto err;
3617 }
3618
d5c18473 3619 adapter->pf_number = desc->pf_num;
92bf14ab 3620 be_copy_nic_desc(res, desc);
abb93951
PR		 3621 }
3622err:
3623 mutex_unlock(&adapter->mbox_lock);
d98ef50f
SR		 3624 if (cmd.va)
3625 pci_free_consistent(adapter->pdev, cmd.size, cmd.va, cmd.dma);
abb93951
PR		 3626 return status;
3627}
3628
ba48c0c9 3629/* Will use MBOX only if MCCQ has not been created */
92bf14ab
SP		 3630int be_cmd_get_profile_config(struct be_adapter *adapter,
3631 struct be_resources *res, u8 domain)
a05f99db 3632{
150d58c7 3633 struct be_cmd_resp_get_profile_config *resp;
ba48c0c9 3634 struct be_cmd_req_get_profile_config *req;
10cccf60 3635 struct be_nic_res_desc *vf_res;
150d58c7 3636 struct be_pcie_res_desc *pcie;
f93f160b 3637 struct be_port_res_desc *port;
150d58c7 3638 struct be_nic_res_desc *nic;
ba48c0c9 3639 struct be_mcc_wrb wrb = {0};
a05f99db 3640 struct be_dma_mem cmd;
150d58c7 3641 u32 desc_count;
a05f99db
VV		 3642 int status;
3643
3644 memset(&cmd, 0, sizeof(struct be_dma_mem));
150d58c7
VV		 3645 cmd.size = sizeof(struct be_cmd_resp_get_profile_config);
3646 cmd.va = pci_alloc_consistent(adapter->pdev, cmd.size, &cmd.dma);
3647 if (!cmd.va)
a05f99db 3648 return -ENOMEM;
a05f99db 3649
ba48c0c9
VV		 3650 req = cmd.va;
3651 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3652 OPCODE_COMMON_GET_PROFILE_CONFIG,
3653 cmd.size, &wrb, &cmd);
3654
3655 req->hdr.domain = domain;
3656 if (!lancer_chip(adapter))
3657 req->hdr.version = 1;
3658 req->type = ACTIVE_PROFILE_TYPE;
3659
3660 status = be_cmd_notify_wait(adapter, &wrb);
150d58c7
VV		 3661 if (status)
3662 goto err;
abb93951 3663
150d58c7
VV		 3664 resp = cmd.va;
3665 desc_count = le32_to_cpu(resp->desc_count);
abb93951 3666
a2cc4e0b
SP		 3667 pcie = be_get_pcie_desc(adapter->pdev->devfn, resp->func_param,
3668 desc_count);
150d58c7 3669 if (pcie)
92bf14ab 3670 res->max_vfs = le16_to_cpu(pcie->num_vfs);
150d58c7 3671
f93f160b
VV		 3672 port = be_get_port_desc(resp->func_param, desc_count);
3673 if (port)
3674 adapter->mc_type = port->mc_type;
3675
10cccf60 3676 nic = be_get_func_nic_desc(resp->func_param, desc_count);
92bf14ab
SP		 3677 if (nic)
3678 be_copy_nic_desc(res, nic);
3679
10cccf60
VV		 3680 vf_res = be_get_vft_desc(resp->func_param, desc_count);
3681 if (vf_res)
3682 res->vf_if_cap_flags = vf_res->cap_flags;
abb93951 3683err:
a05f99db 3684 if (cmd.va)
150d58c7 3685 pci_free_consistent(adapter->pdev, cmd.size, cmd.va, cmd.dma);
abb93951
PR		 3686 return status;
3687}
3688
bec84e6b
VV		 3689/* Will use MBOX only if MCCQ has not been created */
3690static int be_cmd_set_profile_config(struct be_adapter *adapter, void *desc,
3691 int size, int count, u8 version, u8 domain)
d5c18473 3692{
d5c18473 3693 struct be_cmd_req_set_profile_config *req;
bec84e6b
VV		 3694 struct be_mcc_wrb wrb = {0};
3695 struct be_dma_mem cmd;
d5c18473
PR		 3696 int status;
3697
bec84e6b
VV		 3698 memset(&cmd, 0, sizeof(struct be_dma_mem));
3699 cmd.size = sizeof(struct be_cmd_req_set_profile_config);
3700 cmd.va = pci_alloc_consistent(adapter->pdev, cmd.size, &cmd.dma);
3701 if (!cmd.va)
3702 return -ENOMEM;
d5c18473 3703
bec84e6b 3704 req = cmd.va;
d5c18473 3705 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
bec84e6b
VV		 3706 OPCODE_COMMON_SET_PROFILE_CONFIG, cmd.size,
3707 &wrb, &cmd);
a401801c 3708 req->hdr.version = version;
d5c18473 3709 req->hdr.domain = domain;
bec84e6b 3710 req->desc_count = cpu_to_le32(count);
a401801c
SP		 3711 memcpy(req->desc, desc, size);
3712
bec84e6b
VV		 3713 status = be_cmd_notify_wait(adapter, &wrb);
3714
3715 if (cmd.va)
3716 pci_free_consistent(adapter->pdev, cmd.size, cmd.va, cmd.dma);
d5c18473
PR		 3717 return status;
3718}
3719
a401801c 3720/* Mark all fields invalid */
bec84e6b 3721static void be_reset_nic_desc(struct be_nic_res_desc *nic)
a401801c
SP		 3722{
3723 memset(nic, 0, sizeof(*nic));
3724 nic->unicast_mac_count = 0xFFFF;
3725 nic->mcc_count = 0xFFFF;
3726 nic->vlan_count = 0xFFFF;
3727 nic->mcast_mac_count = 0xFFFF;
3728 nic->txq_count = 0xFFFF;
3729 nic->rq_count = 0xFFFF;
3730 nic->rssq_count = 0xFFFF;
3731 nic->lro_count = 0xFFFF;
3732 nic->cq_count = 0xFFFF;
3733 nic->toe_conn_count = 0xFFFF;
3734 nic->eq_count = 0xFFFF;
0f77ba73 3735 nic->iface_count = 0xFFFF;
a401801c 3736 nic->link_param = 0xFF;
0f77ba73 3737 nic->channel_id_param = cpu_to_le16(0xF000);
a401801c
SP		 3738 nic->acpi_params = 0xFF;
3739 nic->wol_param = 0x0F;
0f77ba73
RN		 3740 nic->tunnel_iface_count = 0xFFFF;
3741 nic->direct_tenant_iface_count = 0xFFFF;
bec84e6b 3742 nic->bw_min = 0xFFFFFFFF;
a401801c
SP		 3743 nic->bw_max = 0xFFFFFFFF;
3744}
3745
bec84e6b
VV		 3746/* Mark all fields invalid */
3747static void be_reset_pcie_desc(struct be_pcie_res_desc *pcie)
3748{
3749 memset(pcie, 0, sizeof(*pcie));
3750 pcie->sriov_state = 0xFF;
3751 pcie->pf_state = 0xFF;
3752 pcie->pf_type = 0xFF;
3753 pcie->num_vfs = 0xFFFF;
3754}
3755
0f77ba73
RN		 3756int be_cmd_config_qos(struct be_adapter *adapter, u32 max_rate, u16 link_speed,
3757 u8 domain)
a401801c 3758{
0f77ba73
RN		 3759 struct be_nic_res_desc nic_desc;
3760 u32 bw_percent;
3761 u16 version = 0;
3762
3763 if (BE3_chip(adapter))
3764 return be_cmd_set_qos(adapter, max_rate / 10, domain);
a401801c 3765
0f77ba73
RN		 3766 be_reset_nic_desc(&nic_desc);
3767 nic_desc.pf_num = adapter->pf_number;
3768 nic_desc.vf_num = domain;
58bdeaa6 3769 nic_desc.bw_min = 0;
0f77ba73 3770 if (lancer_chip(adapter)) {
a401801c
SP		 3771 nic_desc.hdr.desc_type = NIC_RESOURCE_DESC_TYPE_V0;
3772 nic_desc.hdr.desc_len = RESOURCE_DESC_SIZE_V0;
3773 nic_desc.flags = (1 << QUN_SHIFT) | (1 << IMM_SHIFT) |
3774 (1 << NOSV_SHIFT);
0f77ba73 3775 nic_desc.bw_max = cpu_to_le32(max_rate / 10);
a401801c 3776 } else {
0f77ba73
RN		 3777 version = 1;
3778 nic_desc.hdr.desc_type = NIC_RESOURCE_DESC_TYPE_V1;
3779 nic_desc.hdr.desc_len = RESOURCE_DESC_SIZE_V1;
3780 nic_desc.flags = (1 << IMM_SHIFT) | (1 << NOSV_SHIFT);
3781 bw_percent = max_rate ? (max_rate * 100) / link_speed : 100;
3782 nic_desc.bw_max = cpu_to_le32(bw_percent);
a401801c 3783 }
0f77ba73
RN		 3784
3785 return be_cmd_set_profile_config(adapter, &nic_desc,
3786 nic_desc.hdr.desc_len,
bec84e6b
VV		 3787 1, version, domain);
3788}
3789
3790int be_cmd_set_sriov_config(struct be_adapter *adapter,
3791 struct be_resources res, u16 num_vfs)
3792{
3793 struct {
3794 struct be_pcie_res_desc pcie;
3795 struct be_nic_res_desc nic_vft;
3796 } __packed desc;
3797 u16 vf_q_count;
3798
3799 if (BEx_chip(adapter) || lancer_chip(adapter))
3800 return 0;
3801
3802 /* PF PCIE descriptor */
3803 be_reset_pcie_desc(&desc.pcie);
3804 desc.pcie.hdr.desc_type = PCIE_RESOURCE_DESC_TYPE_V1;
3805 desc.pcie.hdr.desc_len = RESOURCE_DESC_SIZE_V1;
3806 desc.pcie.flags = (1 << IMM_SHIFT) | (1 << NOSV_SHIFT);
3807 desc.pcie.pf_num = adapter->pdev->devfn;
3808 desc.pcie.sriov_state = num_vfs ? 1 : 0;
3809 desc.pcie.num_vfs = cpu_to_le16(num_vfs);
3810
3811 /* VF NIC Template descriptor */
3812 be_reset_nic_desc(&desc.nic_vft);
3813 desc.nic_vft.hdr.desc_type = NIC_RESOURCE_DESC_TYPE_V1;
3814 desc.nic_vft.hdr.desc_len = RESOURCE_DESC_SIZE_V1;
3815 desc.nic_vft.flags = (1 << VFT_SHIFT) | (1 << IMM_SHIFT) |
3816 (1 << NOSV_SHIFT);
3817 desc.nic_vft.pf_num = adapter->pdev->devfn;
3818 desc.nic_vft.vf_num = 0;
3819
3820 if (num_vfs && res.vf_if_cap_flags & BE_IF_FLAGS_RSS) {
3821 /* If number of VFs requested is 8 less than max supported,
3822 * assign 8 queue pairs to the PF and divide the remaining
3823 * resources evenly among the VFs
3824 */
3825 if (num_vfs < (be_max_vfs(adapter) - 8))
3826 vf_q_count = (res.max_rss_qs - 8) / num_vfs;
3827 else
3828 vf_q_count = res.max_rss_qs / num_vfs;
3829
3830 desc.nic_vft.rq_count = cpu_to_le16(vf_q_count);
3831 desc.nic_vft.txq_count = cpu_to_le16(vf_q_count);
3832 desc.nic_vft.rssq_count = cpu_to_le16(vf_q_count - 1);
3833 desc.nic_vft.cq_count = cpu_to_le16(3 * vf_q_count);
3834 } else {
3835 desc.nic_vft.txq_count = cpu_to_le16(1);
3836 desc.nic_vft.rq_count = cpu_to_le16(1);
3837 desc.nic_vft.rssq_count = cpu_to_le16(0);
3838 /* One CQ for each TX, RX and MCCQ */
3839 desc.nic_vft.cq_count = cpu_to_le16(3);
3840 }
3841
3842 return be_cmd_set_profile_config(adapter, &desc,
3843 2 * RESOURCE_DESC_SIZE_V1, 2, 1, 0);
a401801c
SP		 3844}
3845
3846int be_cmd_manage_iface(struct be_adapter *adapter, u32 iface, u8 op)
3847{
3848 struct be_mcc_wrb *wrb;
3849 struct be_cmd_req_manage_iface_filters *req;
3850 int status;
3851
3852 if (iface == 0xFFFFFFFF)
3853 return -1;
3854
3855 spin_lock_bh(&adapter->mcc_lock);
3856
3857 wrb = wrb_from_mccq(adapter);
3858 if (!wrb) {
3859 status = -EBUSY;
3860 goto err;
3861 }
3862 req = embedded_payload(wrb);
3863
3864 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3865 OPCODE_COMMON_MANAGE_IFACE_FILTERS, sizeof(*req),
3866 wrb, NULL);
3867 req->op = op;
3868 req->target_iface_id = cpu_to_le32(iface);
3869
3870 status = be_mcc_notify_wait(adapter);
3871err:
3872 spin_unlock_bh(&adapter->mcc_lock);
3873 return status;
3874}
3875
3876int be_cmd_set_vxlan_port(struct be_adapter *adapter, __be16 port)
3877{
3878 struct be_port_res_desc port_desc;
3879
3880 memset(&port_desc, 0, sizeof(port_desc));
3881 port_desc.hdr.desc_type = PORT_RESOURCE_DESC_TYPE_V1;
3882 port_desc.hdr.desc_len = RESOURCE_DESC_SIZE_V1;
3883 port_desc.flags = (1 << IMM_SHIFT) | (1 << NOSV_SHIFT);
3884 port_desc.link_num = adapter->hba_port_num;
3885 if (port) {
3886 port_desc.nv_flags = NV_TYPE_VXLAN | (1 << SOCVID_SHIFT) |
3887 (1 << RCVID_SHIFT);
3888 port_desc.nv_port = swab16(port);
3889 } else {
3890 port_desc.nv_flags = NV_TYPE_DISABLED;
3891 port_desc.nv_port = 0;
3892 }
3893
3894 return be_cmd_set_profile_config(adapter, &port_desc,
bec84e6b 3895 RESOURCE_DESC_SIZE_V1, 1, 1, 0);
a401801c
SP		 3896}
3897
4c876616
SP		 3898int be_cmd_get_if_id(struct be_adapter *adapter, struct be_vf_cfg *vf_cfg,
3899 int vf_num)
3900{
3901 struct be_mcc_wrb *wrb;
3902 struct be_cmd_req_get_iface_list *req;
3903 struct be_cmd_resp_get_iface_list *resp;
3904 int status;
3905
3906 spin_lock_bh(&adapter->mcc_lock);
3907
3908 wrb = wrb_from_mccq(adapter);
3909 if (!wrb) {
3910 status = -EBUSY;
3911 goto err;
3912 }
3913 req = embedded_payload(wrb);
3914
3915 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3916 OPCODE_COMMON_GET_IFACE_LIST, sizeof(*resp),
3917 wrb, NULL);
3918 req->hdr.domain = vf_num + 1;
3919
3920 status = be_mcc_notify_wait(adapter);
3921 if (!status) {
3922 resp = (struct be_cmd_resp_get_iface_list *)req;
3923 vf_cfg->if_handle = le32_to_cpu(resp->if_desc.if_id);
3924 }
3925
3926err:
3927 spin_unlock_bh(&adapter->mcc_lock);
3928 return status;
3929}
3930
5c510811
SK		 3931static int lancer_wait_idle(struct be_adapter *adapter)
3932{
3933#define SLIPORT_IDLE_TIMEOUT 30
3934 u32 reg_val;
3935 int status = 0, i;
3936
3937 for (i = 0; i < SLIPORT_IDLE_TIMEOUT; i++) {
3938 reg_val = ioread32(adapter->db + PHYSDEV_CONTROL_OFFSET);
3939 if ((reg_val & PHYSDEV_CONTROL_INP_MASK) == 0)
3940 break;
3941
3942 ssleep(1);
3943 }
3944
3945 if (i == SLIPORT_IDLE_TIMEOUT)
3946 status = -1;
3947
3948 return status;
3949}
3950
3951int lancer_physdev_ctrl(struct be_adapter *adapter, u32 mask)
3952{
3953 int status = 0;
3954
3955 status = lancer_wait_idle(adapter);
3956 if (status)
3957 return status;
3958
3959 iowrite32(mask, adapter->db + PHYSDEV_CONTROL_OFFSET);
3960
3961 return status;
3962}
3963
3964/* Routine to check whether dump image is present or not */
3965bool dump_present(struct be_adapter *adapter)
3966{
3967 u32 sliport_status = 0;
3968
3969 sliport_status = ioread32(adapter->db + SLIPORT_STATUS_OFFSET);
3970 return !!(sliport_status & SLIPORT_STATUS_DIP_MASK);
3971}
3972
3973int lancer_initiate_dump(struct be_adapter *adapter)
3974{
f0613380 3975 struct device *dev = &adapter->pdev->dev;
5c510811
SK		 3976 int status;
3977
f0613380
KA		 3978 if (dump_present(adapter)) {
3979 dev_info(dev, "Previous dump not cleared, not forcing dump\n");
3980 return -EEXIST;
3981 }
3982
5c510811
SK		 3983 /* give firmware reset and diagnostic dump */
3984 status = lancer_physdev_ctrl(adapter, PHYSDEV_CONTROL_FW_RESET_MASK |
3985 PHYSDEV_CONTROL_DD_MASK);
3986 if (status < 0) {
f0613380 3987 dev_err(dev, "FW reset failed\n");
5c510811
SK		 3988 return status;
3989 }
3990
3991 status = lancer_wait_idle(adapter);
3992 if (status)
3993 return status;
3994
3995 if (!dump_present(adapter)) {
f0613380
KA		 3996 dev_err(dev, "FW dump not generated\n");
3997 return -EIO;
5c510811
SK		 3998 }
3999
4000 return 0;
4001}
4002
f0613380
KA		 4003int lancer_delete_dump(struct be_adapter *adapter)
4004{
4005 int status;
4006
4007 status = lancer_cmd_delete_object(adapter, LANCER_FW_DUMP_FILE);
4008 return be_cmd_status(status);
4009}
4010
dcf7ebba
PR		 4011/* Uses sync mcc */
4012int be_cmd_enable_vf(struct be_adapter *adapter, u8 domain)
4013{
4014 struct be_mcc_wrb *wrb;
4015 struct be_cmd_enable_disable_vf *req;
4016 int status;
4017
0599863d 4018 if (BEx_chip(adapter))
dcf7ebba
PR		 4019 return 0;
4020
4021 spin_lock_bh(&adapter->mcc_lock);
4022
4023 wrb = wrb_from_mccq(adapter);
4024 if (!wrb) {
4025 status = -EBUSY;
4026 goto err;
4027 }
4028
4029 req = embedded_payload(wrb);
4030
4031 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
4032 OPCODE_COMMON_ENABLE_DISABLE_VF, sizeof(*req),
4033 wrb, NULL);
4034
4035 req->hdr.domain = domain;
4036 req->enable = 1;
4037 status = be_mcc_notify_wait(adapter);
4038err:
4039 spin_unlock_bh(&adapter->mcc_lock);
4040 return status;
4041}
4042
68c45a2d
SK		 4043int be_cmd_intr_set(struct be_adapter *adapter, bool intr_enable)
4044{
4045 struct be_mcc_wrb *wrb;
4046 struct be_cmd_req_intr_set *req;
4047 int status;
4048
4049 if (mutex_lock_interruptible(&adapter->mbox_lock))
4050 return -1;
4051
4052 wrb = wrb_from_mbox(adapter);
4053
4054 req = embedded_payload(wrb);
4055
4056 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
4057 OPCODE_COMMON_SET_INTERRUPT_ENABLE, sizeof(*req),
4058 wrb, NULL);
4059
4060 req->intr_enabled = intr_enable;
4061
4062 status = be_mbox_notify_wait(adapter);
4063
4064 mutex_unlock(&adapter->mbox_lock);
4065 return status;
4066}
4067
542963b7
VV		 4068/* Uses MBOX */
4069int be_cmd_get_active_profile(struct be_adapter *adapter, u16 *profile_id)
4070{
4071 struct be_cmd_req_get_active_profile *req;
4072 struct be_mcc_wrb *wrb;
4073 int status;
4074
4075 if (mutex_lock_interruptible(&adapter->mbox_lock))
4076 return -1;
4077
4078 wrb = wrb_from_mbox(adapter);
4079 if (!wrb) {
4080 status = -EBUSY;
4081 goto err;
4082 }
4083
4084 req = embedded_payload(wrb);
4085
4086 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
4087 OPCODE_COMMON_GET_ACTIVE_PROFILE, sizeof(*req),
4088 wrb, NULL);
4089
4090 status = be_mbox_notify_wait(adapter);
4091 if (!status) {
4092 struct be_cmd_resp_get_active_profile *resp =
4093 embedded_payload(wrb);
03d28ffe 4094
542963b7
VV		 4095 *profile_id = le16_to_cpu(resp->active_profile_id);
4096 }
4097
4098err:
4099 mutex_unlock(&adapter->mbox_lock);
4100 return status;
4101}
4102
bdce2ad7
SR		 4103int be_cmd_set_logical_link_config(struct be_adapter *adapter,
4104 int link_state, u8 domain)
4105{
4106 struct be_mcc_wrb *wrb;
4107 struct be_cmd_req_set_ll_link *req;
4108 int status;
4109
4110 if (BEx_chip(adapter) || lancer_chip(adapter))
18fd6025 4111 return -EOPNOTSUPP;
bdce2ad7
SR		 4112
4113 spin_lock_bh(&adapter->mcc_lock);
4114
4115 wrb = wrb_from_mccq(adapter);
4116 if (!wrb) {
4117 status = -EBUSY;
4118 goto err;
4119 }
4120
4121 req = embedded_payload(wrb);
4122
4123 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
4124 OPCODE_COMMON_SET_LOGICAL_LINK_CONFIG,
4125 sizeof(*req), wrb, NULL);
4126
4127 req->hdr.version = 1;
4128 req->hdr.domain = domain;
4129
4130 if (link_state == IFLA_VF_LINK_STATE_ENABLE)
4131 req->link_config |= 1;
4132
4133 if (link_state == IFLA_VF_LINK_STATE_AUTO)
4134 req->link_config |= 1 << PLINK_TRACK_SHIFT;
4135
4136 status = be_mcc_notify_wait(adapter);
4137err:
4138 spin_unlock_bh(&adapter->mcc_lock);
4139 return status;
4140}
4141
6a4ab669 4142int be_roce_mcc_cmd(void *netdev_handle, void *wrb_payload,
a2cc4e0b 4143 int wrb_payload_size, u16 *cmd_status, u16 *ext_status)
6a4ab669
PP		 4144{
4145 struct be_adapter *adapter = netdev_priv(netdev_handle);
4146 struct be_mcc_wrb *wrb;
504fbf1e 4147 struct be_cmd_req_hdr *hdr = (struct be_cmd_req_hdr *)wrb_payload;
6a4ab669
PP		 4148 struct be_cmd_req_hdr *req;
4149 struct be_cmd_resp_hdr *resp;
4150 int status;
4151
4152 spin_lock_bh(&adapter->mcc_lock);
4153
4154 wrb = wrb_from_mccq(adapter);
4155 if (!wrb) {
4156 status = -EBUSY;
4157 goto err;
4158 }
4159 req = embedded_payload(wrb);
4160 resp = embedded_payload(wrb);
4161
4162 be_wrb_cmd_hdr_prepare(req, hdr->subsystem,
4163 hdr->opcode, wrb_payload_size, wrb, NULL);
4164 memcpy(req, wrb_payload, wrb_payload_size);
4165 be_dws_cpu_to_le(req, wrb_payload_size);
4166
4167 status = be_mcc_notify_wait(adapter);
4168 if (cmd_status)
4169 *cmd_status = (status & 0xffff);
4170 if (ext_status)
4171 *ext_status = 0;
4172 memcpy(wrb_payload, resp, sizeof(*resp) + resp->response_length);
4173 be_dws_le_to_cpu(wrb_payload, sizeof(*resp) + resp->response_length);
4174err:
4175 spin_unlock_bh(&adapter->mcc_lock);
4176 return status;
4177}
4178EXPORT_SYMBOL(be_roce_mcc_cmd);
Linux kernel - Deliverables
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