projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
be2net: update copyright year to 2015
[deliverable/linux.git] / drivers / net / ethernet / emulex / benet / be_cmds.c
CommitLineData
6b7c5b94 1/*
d19261b8 2 * Copyright (C) 2005 - 2015 Emulex
6b7c5b94
SP		 3 * All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License version 2
7 * as published by the Free Software Foundation. The full GNU General
8 * Public License is included in this distribution in the file called COPYING.
9 *
10 * Contact Information:
d2145cde 11 * linux-drivers@emulex.com
6b7c5b94 12 *
d2145cde
AK		 13 * Emulex
14 * 3333 Susan Street
15 * Costa Mesa, CA 92626
6b7c5b94
SP		 16 */
17
6a4ab669 18#include <linux/module.h>
6b7c5b94 19#include "be.h"
8788fdc2 20#include "be_cmds.h"
6b7c5b94 21
21252377
VV		 22static char *be_port_misconfig_evt_desc[] = {
23 "A valid SFP module detected",
24 "Optics faulted/ incorrectly installed/ not installed.",
25 "Optics of two types installed.",
26 "Incompatible optics.",
27 "Unknown port SFP status"
28};
29
30static char *be_port_misconfig_remedy_desc[] = {
31 "",
32 "Reseat optics. If issue not resolved, replace",
33 "Remove one optic or install matching pair of optics",
34 "Replace with compatible optics for card to function",
35 ""
36};
37
f25b119c
PR		 38static struct be_cmd_priv_map cmd_priv_map[] = {
39 {
40 OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG,
41 CMD_SUBSYSTEM_ETH,
42 BE_PRIV_LNKMGMT | BE_PRIV_VHADM |
43 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC
44 },
45 {
46 OPCODE_COMMON_GET_FLOW_CONTROL,
47 CMD_SUBSYSTEM_COMMON,
48 BE_PRIV_LNKQUERY | BE_PRIV_VHADM |
49 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC
50 },
51 {
52 OPCODE_COMMON_SET_FLOW_CONTROL,
53 CMD_SUBSYSTEM_COMMON,
54 BE_PRIV_LNKMGMT | BE_PRIV_VHADM |
55 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC
56 },
57 {
58 OPCODE_ETH_GET_PPORT_STATS,
59 CMD_SUBSYSTEM_ETH,
60 BE_PRIV_LNKMGMT | BE_PRIV_VHADM |
61 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC
62 },
63 {
64 OPCODE_COMMON_GET_PHY_DETAILS,
65 CMD_SUBSYSTEM_COMMON,
66 BE_PRIV_LNKMGMT | BE_PRIV_VHADM |
67 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC
68 }
69};
70
a2cc4e0b 71static bool be_cmd_allowed(struct be_adapter *adapter, u8 opcode, u8 subsystem)
f25b119c
PR		 72{
73 int i;
74 int num_entries = sizeof(cmd_priv_map)/sizeof(struct be_cmd_priv_map);
75 u32 cmd_privileges = adapter->cmd_privileges;
76
77 for (i = 0; i < num_entries; i++)
78 if (opcode == cmd_priv_map[i].opcode &&
79 subsystem == cmd_priv_map[i].subsystem)
80 if (!(cmd_privileges & cmd_priv_map[i].priv_mask))
81 return false;
82
83 return true;
84}
85
3de09455
SK		 86static inline void *embedded_payload(struct be_mcc_wrb *wrb)
87{
88 return wrb->payload.embedded_payload;
89}
609ff3bb 90
8788fdc2 91static void be_mcc_notify(struct be_adapter *adapter)
5fb379ee 92{
8788fdc2 93 struct be_queue_info *mccq = &adapter->mcc_obj.q;
5fb379ee
SP		 94 u32 val = 0;
95
6589ade0 96 if (be_error(adapter))
7acc2087 97 return;
7acc2087 98
5fb379ee
SP		 99 val |= mccq->id & DB_MCCQ_RING_ID_MASK;
100 val |= 1 << DB_MCCQ_NUM_POSTED_SHIFT;
f3eb62d2
SP		 101
102 wmb();
8788fdc2 103 iowrite32(val, adapter->db + DB_MCCQ_OFFSET);
5fb379ee
SP		 104}
105
106/* To check if valid bit is set, check the entire word as we don't know
107 * the endianness of the data (old entry is host endian while a new entry is
108 * little endian) */
efd2e40a 109static inline bool be_mcc_compl_is_new(struct be_mcc_compl *compl)
5fb379ee 110{
9e9ff4b7
SP		 111 u32 flags;
112
5fb379ee 113 if (compl->flags != 0) {
9e9ff4b7
SP		 114 flags = le32_to_cpu(compl->flags);
115 if (flags & CQE_FLAGS_VALID_MASK) {
116 compl->flags = flags;
117 return true;
118 }
5fb379ee 119 }
9e9ff4b7 120 return false;
5fb379ee
SP		 121}
122
123/* Need to reset the entire word that houses the valid bit */
efd2e40a 124static inline void be_mcc_compl_use(struct be_mcc_compl *compl)
5fb379ee
SP		 125{
126 compl->flags = 0;
127}
128
652bf646
PR		 129static struct be_cmd_resp_hdr *be_decode_resp_hdr(u32 tag0, u32 tag1)
130{
131 unsigned long addr;
132
133 addr = tag1;
134 addr = ((addr << 16) << 16) | tag0;
135 return (void *)addr;
136}
137
4c60005f
KA		 138static bool be_skip_err_log(u8 opcode, u16 base_status, u16 addl_status)
139{
140 if (base_status == MCC_STATUS_NOT_SUPPORTED ||
141 base_status == MCC_STATUS_ILLEGAL_REQUEST ||
142 addl_status == MCC_ADDL_STATUS_TOO_MANY_INTERFACES ||
77be8c1c 143 addl_status == MCC_ADDL_STATUS_INSUFFICIENT_VLANS ||
4c60005f
KA		 144 (opcode == OPCODE_COMMON_WRITE_FLASHROM &&
145 (base_status == MCC_STATUS_ILLEGAL_FIELD ||
146 addl_status == MCC_ADDL_STATUS_FLASH_IMAGE_CRC_MISMATCH)))
147 return true;
148 else
149 return false;
150}
151
559b633f
SP		 152/* Place holder for all the async MCC cmds wherein the caller is not in a busy
153 * loop (has not issued be_mcc_notify_wait())
154 */
155static void be_async_cmd_process(struct be_adapter *adapter,
156 struct be_mcc_compl *compl,
157 struct be_cmd_resp_hdr *resp_hdr)
158{
159 enum mcc_base_status base_status = base_status(compl->status);
160 u8 opcode = 0, subsystem = 0;
161
162 if (resp_hdr) {
163 opcode = resp_hdr->opcode;
164 subsystem = resp_hdr->subsystem;
165 }
166
167 if (opcode == OPCODE_LOWLEVEL_LOOPBACK_TEST &&
168 subsystem == CMD_SUBSYSTEM_LOWLEVEL) {
169 complete(&adapter->et_cmd_compl);
170 return;
171 }
172
173 if ((opcode == OPCODE_COMMON_WRITE_FLASHROM ||
174 opcode == OPCODE_COMMON_WRITE_OBJECT) &&
175 subsystem == CMD_SUBSYSTEM_COMMON) {
176 adapter->flash_status = compl->status;
177 complete(&adapter->et_cmd_compl);
178 return;
179 }
180
181 if ((opcode == OPCODE_ETH_GET_STATISTICS ||
182 opcode == OPCODE_ETH_GET_PPORT_STATS) &&
183 subsystem == CMD_SUBSYSTEM_ETH &&
184 base_status == MCC_STATUS_SUCCESS) {
185 be_parse_stats(adapter);
186 adapter->stats_cmd_sent = false;
187 return;
188 }
189
190 if (opcode == OPCODE_COMMON_GET_CNTL_ADDITIONAL_ATTRIBUTES &&
191 subsystem == CMD_SUBSYSTEM_COMMON) {
192 if (base_status == MCC_STATUS_SUCCESS) {
193 struct be_cmd_resp_get_cntl_addnl_attribs *resp =
194 (void *)resp_hdr;
195 adapter->drv_stats.be_on_die_temperature =
196 resp->on_die_temperature;
197 } else {
198 adapter->be_get_temp_freq = 0;
199 }
200 return;
201 }
202}
203
8788fdc2 204static int be_mcc_compl_process(struct be_adapter *adapter,
652bf646 205 struct be_mcc_compl *compl)
5fb379ee 206{
4c60005f
KA		 207 enum mcc_base_status base_status;
208 enum mcc_addl_status addl_status;
652bf646
PR		 209 struct be_cmd_resp_hdr *resp_hdr;
210 u8 opcode = 0, subsystem = 0;
5fb379ee
SP		 211
212 /* Just swap the status to host endian; mcc tag is opaquely copied
213 * from mcc_wrb */
214 be_dws_le_to_cpu(compl, 4);
215
4c60005f
KA		 216 base_status = base_status(compl->status);
217 addl_status = addl_status(compl->status);
96c9b2e4 218
652bf646 219 resp_hdr = be_decode_resp_hdr(compl->tag0, compl->tag1);
652bf646
PR		 220 if (resp_hdr) {
221 opcode = resp_hdr->opcode;
222 subsystem = resp_hdr->subsystem;
223 }
224
559b633f 225 be_async_cmd_process(adapter, compl, resp_hdr);
3de09455 226
559b633f
SP		 227 if (base_status != MCC_STATUS_SUCCESS &&
228 !be_skip_err_log(opcode, base_status, addl_status)) {
4c60005f 229 if (base_status == MCC_STATUS_UNAUTHORIZED_REQUEST) {
97f1d8cd 230 dev_warn(&adapter->pdev->dev,
522609f2 231 "VF is not privileged to issue opcode %d-%d\n",
97f1d8cd 232 opcode, subsystem);
2b3f291b 233 } else {
97f1d8cd
VV		 234 dev_err(&adapter->pdev->dev,
235 "opcode %d-%d failed:status %d-%d\n",
4c60005f 236 opcode, subsystem, base_status, addl_status);
2b3f291b 237 }
5fb379ee 238 }
4c60005f 239 return compl->status;
5fb379ee
SP		 240}
241
a8f447bd 242/* Link state evt is a string of bytes; no need for endian swapping */
8788fdc2 243static void be_async_link_state_process(struct be_adapter *adapter,
3acf19d9 244 struct be_mcc_compl *compl)
a8f447bd 245{
3acf19d9
SP		 246 struct be_async_event_link_state *evt =
247 (struct be_async_event_link_state *)compl;
248
b236916a 249 /* When link status changes, link speed must be re-queried from FW */
42f11cf2 250 adapter->phy.link_speed = -1;
b236916a 251
bdce2ad7
SR		 252 /* On BEx the FW does not send a separate link status
253 * notification for physical and logical link.
254 * On other chips just process the logical link
255 * status notification
256 */
257 if (!BEx_chip(adapter) &&
2e177a5c
PR		 258 !(evt->port_link_status & LOGICAL_LINK_STATUS_MASK))
259 return;
260
b236916a
AK		 261 /* For the initial link status do not rely on the ASYNC event as
262 * it may not be received in some cases.
263 */
264 if (adapter->flags & BE_FLAGS_LINK_STATUS_INIT)
bdce2ad7
SR		 265 be_link_status_update(adapter,
266 evt->port_link_status & LINK_STATUS_MASK);
a8f447bd
SP		 267}
268
21252377
VV		 269static void be_async_port_misconfig_event_process(struct be_adapter *adapter,
270 struct be_mcc_compl *compl)
271{
272 struct be_async_event_misconfig_port *evt =
273 (struct be_async_event_misconfig_port *)compl;
274 u32 sfp_mismatch_evt = le32_to_cpu(evt->event_data_word1);
275 struct device *dev = &adapter->pdev->dev;
276 u8 port_misconfig_evt;
277
278 port_misconfig_evt =
279 ((sfp_mismatch_evt >> (adapter->hba_port_num * 8)) & 0xff);
280
281 /* Log an error message that would allow a user to determine
282 * whether the SFPs have an issue
283 */
284 dev_info(dev, "Port %c: %s %s", adapter->port_name,
285 be_port_misconfig_evt_desc[port_misconfig_evt],
286 be_port_misconfig_remedy_desc[port_misconfig_evt]);
287
288 if (port_misconfig_evt == INCOMPATIBLE_SFP)
289 adapter->flags |= BE_FLAGS_EVT_INCOMPATIBLE_SFP;
290}
291
cc4ce020
SK		 292/* Grp5 CoS Priority evt */
293static void be_async_grp5_cos_priority_process(struct be_adapter *adapter,
3acf19d9 294 struct be_mcc_compl *compl)
cc4ce020 295{
3acf19d9
SP		 296 struct be_async_event_grp5_cos_priority *evt =
297 (struct be_async_event_grp5_cos_priority *)compl;
298
cc4ce020
SK		 299 if (evt->valid) {
300 adapter->vlan_prio_bmap = evt->available_priority_bmap;
60964dd7 301 adapter->recommended_prio &= ~VLAN_PRIO_MASK;
cc4ce020
SK		 302 adapter->recommended_prio =
303 evt->reco_default_priority << VLAN_PRIO_SHIFT;
304 }
305}
306
323ff71e 307/* Grp5 QOS Speed evt: qos_link_speed is in units of 10 Mbps */
cc4ce020 308static void be_async_grp5_qos_speed_process(struct be_adapter *adapter,
3acf19d9 309 struct be_mcc_compl *compl)
cc4ce020 310{
3acf19d9
SP		 311 struct be_async_event_grp5_qos_link_speed *evt =
312 (struct be_async_event_grp5_qos_link_speed *)compl;
313
323ff71e
SP		 314 if (adapter->phy.link_speed >= 0 &&
315 evt->physical_port == adapter->port_num)
316 adapter->phy.link_speed = le16_to_cpu(evt->qos_link_speed) * 10;
cc4ce020
SK		 317}
318
3968fa1e
AK		 319/*Grp5 PVID evt*/
320static void be_async_grp5_pvid_state_process(struct be_adapter *adapter,
3acf19d9 321 struct be_mcc_compl *compl)
3968fa1e 322{
3acf19d9
SP		 323 struct be_async_event_grp5_pvid_state *evt =
324 (struct be_async_event_grp5_pvid_state *)compl;
325
bdac85b5 326 if (evt->enabled) {
939cf306 327 adapter->pvid = le16_to_cpu(evt->tag) & VLAN_VID_MASK;
bdac85b5
RN		 328 dev_info(&adapter->pdev->dev, "LPVID: %d\n", adapter->pvid);
329 } else {
3968fa1e 330 adapter->pvid = 0;
bdac85b5 331 }
3968fa1e
AK		 332}
333
cc4ce020 334static void be_async_grp5_evt_process(struct be_adapter *adapter,
3acf19d9 335 struct be_mcc_compl *compl)
cc4ce020 336{
3acf19d9
SP		 337 u8 event_type = (compl->flags >> ASYNC_EVENT_TYPE_SHIFT) &
338 ASYNC_EVENT_TYPE_MASK;
cc4ce020
SK		 339
340 switch (event_type) {
341 case ASYNC_EVENT_COS_PRIORITY:
3acf19d9
SP		 342 be_async_grp5_cos_priority_process(adapter, compl);
343 break;
cc4ce020 344 case ASYNC_EVENT_QOS_SPEED:
3acf19d9
SP		 345 be_async_grp5_qos_speed_process(adapter, compl);
346 break;
3968fa1e 347 case ASYNC_EVENT_PVID_STATE:
3acf19d9
SP		 348 be_async_grp5_pvid_state_process(adapter, compl);
349 break;
cc4ce020 350 default:
cc4ce020
SK		 351 break;
352 }
353}
354
bc0c3405 355static void be_async_dbg_evt_process(struct be_adapter *adapter,
3acf19d9 356 struct be_mcc_compl *cmp)
bc0c3405
AK		 357{
358 u8 event_type = 0;
504fbf1e 359 struct be_async_event_qnq *evt = (struct be_async_event_qnq *)cmp;
bc0c3405 360
3acf19d9
SP		 361 event_type = (cmp->flags >> ASYNC_EVENT_TYPE_SHIFT) &
362 ASYNC_EVENT_TYPE_MASK;
bc0c3405
AK		 363
364 switch (event_type) {
365 case ASYNC_DEBUG_EVENT_TYPE_QNQ:
366 if (evt->valid)
367 adapter->qnq_vid = le16_to_cpu(evt->vlan_tag);
368 adapter->flags |= BE_FLAGS_QNQ_ASYNC_EVT_RCVD;
369 break;
370 default:
05ccaa2b
VV		 371 dev_warn(&adapter->pdev->dev, "Unknown debug event 0x%x!\n",
372 event_type);
bc0c3405
AK		 373 break;
374 }
375}
376
21252377
VV		 377static void be_async_sliport_evt_process(struct be_adapter *adapter,
378 struct be_mcc_compl *cmp)
379{
380 u8 event_type = (cmp->flags >> ASYNC_EVENT_TYPE_SHIFT) &
381 ASYNC_EVENT_TYPE_MASK;
382
383 if (event_type == ASYNC_EVENT_PORT_MISCONFIG)
384 be_async_port_misconfig_event_process(adapter, cmp);
385}
386
3acf19d9 387static inline bool is_link_state_evt(u32 flags)
a8f447bd 388{
3acf19d9
SP		 389 return ((flags >> ASYNC_EVENT_CODE_SHIFT) & ASYNC_EVENT_CODE_MASK) ==
390 ASYNC_EVENT_CODE_LINK_STATE;
a8f447bd 391}
5fb379ee 392
3acf19d9 393static inline bool is_grp5_evt(u32 flags)
cc4ce020 394{
3acf19d9
SP		 395 return ((flags >> ASYNC_EVENT_CODE_SHIFT) & ASYNC_EVENT_CODE_MASK) ==
396 ASYNC_EVENT_CODE_GRP_5;
cc4ce020
SK		 397}
398
3acf19d9 399static inline bool is_dbg_evt(u32 flags)
bc0c3405 400{
3acf19d9
SP		 401 return ((flags >> ASYNC_EVENT_CODE_SHIFT) & ASYNC_EVENT_CODE_MASK) ==
402 ASYNC_EVENT_CODE_QNQ;
403}
404
21252377
VV		 405static inline bool is_sliport_evt(u32 flags)
406{
407 return ((flags >> ASYNC_EVENT_CODE_SHIFT) & ASYNC_EVENT_CODE_MASK) ==
408 ASYNC_EVENT_CODE_SLIPORT;
409}
410
3acf19d9
SP		 411static void be_mcc_event_process(struct be_adapter *adapter,
412 struct be_mcc_compl *compl)
413{
414 if (is_link_state_evt(compl->flags))
415 be_async_link_state_process(adapter, compl);
416 else if (is_grp5_evt(compl->flags))
417 be_async_grp5_evt_process(adapter, compl);
418 else if (is_dbg_evt(compl->flags))
419 be_async_dbg_evt_process(adapter, compl);
21252377
VV		 420 else if (is_sliport_evt(compl->flags))
421 be_async_sliport_evt_process(adapter, compl);
bc0c3405
AK		 422}
423
efd2e40a 424static struct be_mcc_compl *be_mcc_compl_get(struct be_adapter *adapter)
5fb379ee 425{
8788fdc2 426 struct be_queue_info *mcc_cq = &adapter->mcc_obj.cq;
efd2e40a 427 struct be_mcc_compl *compl = queue_tail_node(mcc_cq);
5fb379ee
SP		 428
429 if (be_mcc_compl_is_new(compl)) {
430 queue_tail_inc(mcc_cq);
431 return compl;
432 }
433 return NULL;
434}
435
7a1e9b20
SP		 436void be_async_mcc_enable(struct be_adapter *adapter)
437{
438 spin_lock_bh(&adapter->mcc_cq_lock);
439
440 be_cq_notify(adapter, adapter->mcc_obj.cq.id, true, 0);
441 adapter->mcc_obj.rearm_cq = true;
442
443 spin_unlock_bh(&adapter->mcc_cq_lock);
444}
445
446void be_async_mcc_disable(struct be_adapter *adapter)
447{
a323d9bf
SP		 448 spin_lock_bh(&adapter->mcc_cq_lock);
449
7a1e9b20 450 adapter->mcc_obj.rearm_cq = false;
a323d9bf
SP		 451 be_cq_notify(adapter, adapter->mcc_obj.cq.id, false, 0);
452
453 spin_unlock_bh(&adapter->mcc_cq_lock);
7a1e9b20
SP		 454}
455
10ef9ab4 456int be_process_mcc(struct be_adapter *adapter)
5fb379ee 457{
efd2e40a 458 struct be_mcc_compl *compl;
10ef9ab4 459 int num = 0, status = 0;
7a1e9b20 460 struct be_mcc_obj *mcc_obj = &adapter->mcc_obj;
5fb379ee 461
072a9c48 462 spin_lock(&adapter->mcc_cq_lock);
3acf19d9 463
8788fdc2 464 while ((compl = be_mcc_compl_get(adapter))) {
a8f447bd 465 if (compl->flags & CQE_FLAGS_ASYNC_MASK) {
3acf19d9 466 be_mcc_event_process(adapter, compl);
b31c50a7 467 } else if (compl->flags & CQE_FLAGS_COMPLETED_MASK) {
3acf19d9
SP		 468 status = be_mcc_compl_process(adapter, compl);
469 atomic_dec(&mcc_obj->q.used);
5fb379ee
SP		 470 }
471 be_mcc_compl_use(compl);
472 num++;
473 }
b31c50a7 474
10ef9ab4
SP		 475 if (num)
476 be_cq_notify(adapter, mcc_obj->cq.id, mcc_obj->rearm_cq, num);
477
072a9c48 478 spin_unlock(&adapter->mcc_cq_lock);
10ef9ab4 479 return status;
5fb379ee
SP		 480}
481
6ac7b687 482/* Wait till no more pending mcc requests are present */
b31c50a7 483static int be_mcc_wait_compl(struct be_adapter *adapter)
6ac7b687 484{
b31c50a7 485#define mcc_timeout 120000 /* 12s timeout */
10ef9ab4 486 int i, status = 0;
f31e50a8
SP		 487 struct be_mcc_obj *mcc_obj = &adapter->mcc_obj;
488
6ac7b687 489 for (i = 0; i < mcc_timeout; i++) {
6589ade0
SP		 490 if (be_error(adapter))
491 return -EIO;
492
072a9c48 493 local_bh_disable();
10ef9ab4 494 status = be_process_mcc(adapter);
072a9c48 495 local_bh_enable();
b31c50a7 496
f31e50a8 497 if (atomic_read(&mcc_obj->q.used) == 0)
6ac7b687
SP		 498 break;
499 udelay(100);
500 }
b31c50a7 501 if (i == mcc_timeout) {
6589ade0
SP		 502 dev_err(&adapter->pdev->dev, "FW not responding\n");
503 adapter->fw_timeout = true;
652bf646 504 return -EIO;
b31c50a7 505 }
f31e50a8 506 return status;
6ac7b687
SP		 507}
508
509/* Notify MCC requests and wait for completion */
b31c50a7 510static int be_mcc_notify_wait(struct be_adapter *adapter)
6ac7b687 511{
652bf646
PR		 512 int status;
513 struct be_mcc_wrb *wrb;
514 struct be_mcc_obj *mcc_obj = &adapter->mcc_obj;
515 u16 index = mcc_obj->q.head;
516 struct be_cmd_resp_hdr *resp;
517
518 index_dec(&index, mcc_obj->q.len);
519 wrb = queue_index_node(&mcc_obj->q, index);
520
521 resp = be_decode_resp_hdr(wrb->tag0, wrb->tag1);
522
8788fdc2 523 be_mcc_notify(adapter);
652bf646
PR		 524
525 status = be_mcc_wait_compl(adapter);
526 if (status == -EIO)
527 goto out;
528
4c60005f
KA		 529 status = (resp->base_status |
530 ((resp->addl_status & CQE_ADDL_STATUS_MASK) <<
531 CQE_ADDL_STATUS_SHIFT));
652bf646
PR		 532out:
533 return status;
6ac7b687
SP		 534}
535
5f0b849e 536static int be_mbox_db_ready_wait(struct be_adapter *adapter, void __iomem *db)
6b7c5b94 537{
f25b03a7 538 int msecs = 0;
6b7c5b94
SP		 539 u32 ready;
540
541 do {
6589ade0
SP		 542 if (be_error(adapter))
543 return -EIO;
544
cf588477 545 ready = ioread32(db);
434b3648 546 if (ready == 0xffffffff)
cf588477 547 return -1;
cf588477
SP		 548
549 ready &= MPU_MAILBOX_DB_RDY_MASK;
6b7c5b94
SP		 550 if (ready)
551 break;
552
f25b03a7 553 if (msecs > 4000) {
6589ade0
SP		 554 dev_err(&adapter->pdev->dev, "FW not responding\n");
555 adapter->fw_timeout = true;
f67ef7ba 556 be_detect_error(adapter);
6b7c5b94
SP		 557 return -1;
558 }
559
1dbf53a2 560 msleep(1);
f25b03a7 561 msecs++;
6b7c5b94
SP		 562 } while (true);
563
564 return 0;
565}
566
567/*
568 * Insert the mailbox address into the doorbell in two steps
5fb379ee 569 * Polls on the mbox doorbell till a command completion (or a timeout) occurs
6b7c5b94 570 */
b31c50a7 571static int be_mbox_notify_wait(struct be_adapter *adapter)
6b7c5b94
SP		 572{
573 int status;
6b7c5b94 574 u32 val = 0;
8788fdc2
SP		 575 void __iomem *db = adapter->db + MPU_MAILBOX_DB_OFFSET;
576 struct be_dma_mem *mbox_mem = &adapter->mbox_mem;
6b7c5b94 577 struct be_mcc_mailbox *mbox = mbox_mem->va;
efd2e40a 578 struct be_mcc_compl *compl = &mbox->compl;
6b7c5b94 579
cf588477
SP		 580 /* wait for ready to be set */
581 status = be_mbox_db_ready_wait(adapter, db);
582 if (status != 0)
583 return status;
584
6b7c5b94
SP		 585 val |= MPU_MAILBOX_DB_HI_MASK;
586 /* at bits 2 - 31 place mbox dma addr msb bits 34 - 63 */
587 val |= (upper_32_bits(mbox_mem->dma) >> 2) << 2;
588 iowrite32(val, db);
589
590 /* wait for ready to be set */
5f0b849e 591 status = be_mbox_db_ready_wait(adapter, db);
6b7c5b94
SP		 592 if (status != 0)
593 return status;
594
595 val = 0;
6b7c5b94
SP		 596 /* at bits 2 - 31 place mbox dma addr lsb bits 4 - 33 */
597 val |= (u32)(mbox_mem->dma >> 4) << 2;
598 iowrite32(val, db);
599
5f0b849e 600 status = be_mbox_db_ready_wait(adapter, db);
6b7c5b94
SP		 601 if (status != 0)
602 return status;
603
5fb379ee 604 /* A cq entry has been made now */
efd2e40a
SP		 605 if (be_mcc_compl_is_new(compl)) {
606 status = be_mcc_compl_process(adapter, &mbox->compl);
607 be_mcc_compl_use(compl);
5fb379ee
SP		 608 if (status)
609 return status;
610 } else {
5f0b849e 611 dev_err(&adapter->pdev->dev, "invalid mailbox completion\n");
6b7c5b94
SP		 612 return -1;
613 }
5fb379ee 614 return 0;
6b7c5b94
SP		 615}
616
c5b3ad4c 617static u16 be_POST_stage_get(struct be_adapter *adapter)
6b7c5b94 618{
fe6d2a38
SP		 619 u32 sem;
620
c5b3ad4c
SP		 621 if (BEx_chip(adapter))
622 sem = ioread32(adapter->csr + SLIPORT_SEMAPHORE_OFFSET_BEx);
6b7c5b94 623 else
c5b3ad4c
SP		 624 pci_read_config_dword(adapter->pdev,
625 SLIPORT_SEMAPHORE_OFFSET_SH, &sem);
626
627 return sem & POST_STAGE_MASK;
6b7c5b94
SP		 628}
629
87f20c26 630static int lancer_wait_ready(struct be_adapter *adapter)
bf99e50d
PR		 631{
632#define SLIPORT_READY_TIMEOUT 30
633 u32 sliport_status;
e673244a 634 int i;
bf99e50d
PR		 635
636 for (i = 0; i < SLIPORT_READY_TIMEOUT; i++) {
637 sliport_status = ioread32(adapter->db + SLIPORT_STATUS_OFFSET);
638 if (sliport_status & SLIPORT_STATUS_RDY_MASK)
9fa465c0 639 return 0;
67297ad8 640
9fa465c0
SP		 641 if (sliport_status & SLIPORT_STATUS_ERR_MASK &&
642 !(sliport_status & SLIPORT_STATUS_RN_MASK))
643 return -EIO;
67297ad8 644
9fa465c0 645 msleep(1000);
bf99e50d 646 }
67297ad8 647
9fa465c0 648 return sliport_status ? : -1;
bf99e50d
PR		 649}
650
651int be_fw_wait_ready(struct be_adapter *adapter)
6b7c5b94 652{
43a04fdc
SP		 653 u16 stage;
654 int status, timeout = 0;
6ed35eea 655 struct device *dev = &adapter->pdev->dev;
6b7c5b94 656
bf99e50d
PR		 657 if (lancer_chip(adapter)) {
658 status = lancer_wait_ready(adapter);
e673244a
KA		 659 if (status) {
660 stage = status;
661 goto err;
662 }
663 return 0;
bf99e50d
PR		 664 }
665
43a04fdc 666 do {
ca3de6b2
SP		 667 /* There's no means to poll POST state on BE2/3 VFs */
668 if (BEx_chip(adapter) && be_virtfn(adapter))
669 return 0;
670
c5b3ad4c 671 stage = be_POST_stage_get(adapter);
66d29cbc 672 if (stage == POST_STAGE_ARMFW_RDY)
43a04fdc 673 return 0;
66d29cbc 674
a2cc4e0b 675 dev_info(dev, "Waiting for POST, %ds elapsed\n", timeout);
66d29cbc
GS		 676 if (msleep_interruptible(2000)) {
677 dev_err(dev, "Waiting for POST aborted\n");
678 return -EINTR;
43a04fdc 679 }
66d29cbc 680 timeout += 2;
3ab81b5f 681 } while (timeout < 60);
6b7c5b94 682
e673244a
KA		 683err:
684 dev_err(dev, "POST timeout; stage=%#x\n", stage);
9fa465c0 685 return -ETIMEDOUT;
6b7c5b94
SP		 686}
687
6b7c5b94
SP		 688static inline struct be_sge *nonembedded_sgl(struct be_mcc_wrb *wrb)
689{
690 return &wrb->payload.sgl[0];
691}
692
a2cc4e0b 693static inline void fill_wrb_tags(struct be_mcc_wrb *wrb, unsigned long addr)
bea50988
SP		 694{
695 wrb->tag0 = addr & 0xFFFFFFFF;
696 wrb->tag1 = upper_32_bits(addr);
697}
6b7c5b94
SP		 698
699/* Don't touch the hdr after it's prepared */
106df1e3
SK		 700/* mem will be NULL for embedded commands */
701static void be_wrb_cmd_hdr_prepare(struct be_cmd_req_hdr *req_hdr,
a2cc4e0b
SP		 702 u8 subsystem, u8 opcode, int cmd_len,
703 struct be_mcc_wrb *wrb,
704 struct be_dma_mem *mem)
6b7c5b94 705{
106df1e3
SK		 706 struct be_sge *sge;
707
6b7c5b94
SP		 708 req_hdr->opcode = opcode;
709 req_hdr->subsystem = subsystem;
710 req_hdr->request_length = cpu_to_le32(cmd_len - sizeof(*req_hdr));
07793d33 711 req_hdr->version = 0;
bea50988 712 fill_wrb_tags(wrb, (ulong) req_hdr);
106df1e3
SK		 713 wrb->payload_length = cmd_len;
714 if (mem) {
715 wrb->embedded |= (1 & MCC_WRB_SGE_CNT_MASK) <<
716 MCC_WRB_SGE_CNT_SHIFT;
717 sge = nonembedded_sgl(wrb);
718 sge->pa_hi = cpu_to_le32(upper_32_bits(mem->dma));
719 sge->pa_lo = cpu_to_le32(mem->dma & 0xFFFFFFFF);
720 sge->len = cpu_to_le32(mem->size);
721 } else
722 wrb->embedded |= MCC_WRB_EMBEDDED_MASK;
723 be_dws_cpu_to_le(wrb, 8);
6b7c5b94
SP		 724}
725
726static void be_cmd_page_addrs_prepare(struct phys_addr *pages, u32 max_pages,
a2cc4e0b 727 struct be_dma_mem *mem)
6b7c5b94
SP		 728{
729 int i, buf_pages = min(PAGES_4K_SPANNED(mem->va, mem->size), max_pages);
730 u64 dma = (u64)mem->dma;
731
732 for (i = 0; i < buf_pages; i++) {
733 pages[i].lo = cpu_to_le32(dma & 0xFFFFFFFF);
734 pages[i].hi = cpu_to_le32(upper_32_bits(dma));
735 dma += PAGE_SIZE_4K;
736 }
737}
738
b31c50a7 739static inline struct be_mcc_wrb *wrb_from_mbox(struct be_adapter *adapter)
6b7c5b94 740{
b31c50a7
SP		 741 struct be_dma_mem *mbox_mem = &adapter->mbox_mem;
742 struct be_mcc_wrb *wrb
743 = &((struct be_mcc_mailbox *)(mbox_mem->va))->wrb;
744 memset(wrb, 0, sizeof(*wrb));
745 return wrb;
6b7c5b94
SP		 746}
747
b31c50a7 748static struct be_mcc_wrb *wrb_from_mccq(struct be_adapter *adapter)
5fb379ee 749{
b31c50a7
SP		 750 struct be_queue_info *mccq = &adapter->mcc_obj.q;
751 struct be_mcc_wrb *wrb;
752
aa790db9
PR		 753 if (!mccq->created)
754 return NULL;
755
4d277125 756 if (atomic_read(&mccq->used) >= mccq->len)
713d0394 757 return NULL;
713d0394 758
b31c50a7
SP		 759 wrb = queue_head_node(mccq);
760 queue_head_inc(mccq);
761 atomic_inc(&mccq->used);
762 memset(wrb, 0, sizeof(*wrb));
5fb379ee
SP		 763 return wrb;
764}
765
bea50988
SP		 766static bool use_mcc(struct be_adapter *adapter)
767{
768 return adapter->mcc_obj.q.created;
769}
770
771/* Must be used only in process context */
772static int be_cmd_lock(struct be_adapter *adapter)
773{
774 if (use_mcc(adapter)) {
775 spin_lock_bh(&adapter->mcc_lock);
776 return 0;
777 } else {
778 return mutex_lock_interruptible(&adapter->mbox_lock);
779 }
780}
781
782/* Must be used only in process context */
783static void be_cmd_unlock(struct be_adapter *adapter)
784{
785 if (use_mcc(adapter))
786 spin_unlock_bh(&adapter->mcc_lock);
787 else
788 return mutex_unlock(&adapter->mbox_lock);
789}
790
791static struct be_mcc_wrb *be_cmd_copy(struct be_adapter *adapter,
792 struct be_mcc_wrb *wrb)
793{
794 struct be_mcc_wrb *dest_wrb;
795
796 if (use_mcc(adapter)) {
797 dest_wrb = wrb_from_mccq(adapter);
798 if (!dest_wrb)
799 return NULL;
800 } else {
801 dest_wrb = wrb_from_mbox(adapter);
802 }
803
804 memcpy(dest_wrb, wrb, sizeof(*wrb));
805 if (wrb->embedded & cpu_to_le32(MCC_WRB_EMBEDDED_MASK))
806 fill_wrb_tags(dest_wrb, (ulong) embedded_payload(wrb));
807
808 return dest_wrb;
809}
810
811/* Must be used only in process context */
812static int be_cmd_notify_wait(struct be_adapter *adapter,
813 struct be_mcc_wrb *wrb)
814{
815 struct be_mcc_wrb *dest_wrb;
816 int status;
817
818 status = be_cmd_lock(adapter);
819 if (status)
820 return status;
821
822 dest_wrb = be_cmd_copy(adapter, wrb);
823 if (!dest_wrb)
824 return -EBUSY;
825
826 if (use_mcc(adapter))
827 status = be_mcc_notify_wait(adapter);
828 else
829 status = be_mbox_notify_wait(adapter);
830
831 if (!status)
832 memcpy(wrb, dest_wrb, sizeof(*wrb));
833
834 be_cmd_unlock(adapter);
835 return status;
836}
837
2243e2e9
SP		 838/* Tell fw we're about to start firing cmds by writing a
839 * special pattern across the wrb hdr; uses mbox
840 */
841int be_cmd_fw_init(struct be_adapter *adapter)
842{
843 u8 *wrb;
844 int status;
845
bf99e50d
PR		 846 if (lancer_chip(adapter))
847 return 0;
848
2984961c
IV		 849 if (mutex_lock_interruptible(&adapter->mbox_lock))
850 return -1;
2243e2e9
SP		 851
852 wrb = (u8 *)wrb_from_mbox(adapter);
359a972f
SP		 853 *wrb++ = 0xFF;
854 *wrb++ = 0x12;
855 *wrb++ = 0x34;
856 *wrb++ = 0xFF;
857 *wrb++ = 0xFF;
858 *wrb++ = 0x56;
859 *wrb++ = 0x78;
860 *wrb = 0xFF;
2243e2e9
SP		 861
862 status = be_mbox_notify_wait(adapter);
863
2984961c 864 mutex_unlock(&adapter->mbox_lock);
2243e2e9
SP		 865 return status;
866}
867
868/* Tell fw we're done with firing cmds by writing a
869 * special pattern across the wrb hdr; uses mbox
870 */
871int be_cmd_fw_clean(struct be_adapter *adapter)
872{
873 u8 *wrb;
874 int status;
875
bf99e50d
PR		 876 if (lancer_chip(adapter))
877 return 0;
878
2984961c
IV		 879 if (mutex_lock_interruptible(&adapter->mbox_lock))
880 return -1;
2243e2e9
SP		 881
882 wrb = (u8 *)wrb_from_mbox(adapter);
883 *wrb++ = 0xFF;
884 *wrb++ = 0xAA;
885 *wrb++ = 0xBB;
886 *wrb++ = 0xFF;
887 *wrb++ = 0xFF;
888 *wrb++ = 0xCC;
889 *wrb++ = 0xDD;
890 *wrb = 0xFF;
891
892 status = be_mbox_notify_wait(adapter);
893
2984961c 894 mutex_unlock(&adapter->mbox_lock);
2243e2e9
SP		 895 return status;
896}
bf99e50d 897
f2f781a7 898int be_cmd_eq_create(struct be_adapter *adapter, struct be_eq_obj *eqo)
6b7c5b94 899{
b31c50a7
SP		 900 struct be_mcc_wrb *wrb;
901 struct be_cmd_req_eq_create *req;
f2f781a7
SP		 902 struct be_dma_mem *q_mem = &eqo->q.dma_mem;
903 int status, ver = 0;
6b7c5b94 904
2984961c
IV		 905 if (mutex_lock_interruptible(&adapter->mbox_lock))
906 return -1;
b31c50a7
SP		 907
908 wrb = wrb_from_mbox(adapter);
909 req = embedded_payload(wrb);
6b7c5b94 910
106df1e3 911 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 912 OPCODE_COMMON_EQ_CREATE, sizeof(*req), wrb,
913 NULL);
6b7c5b94 914
f2f781a7
SP		 915 /* Support for EQ_CREATEv2 available only SH-R onwards */
916 if (!(BEx_chip(adapter) || lancer_chip(adapter)))
917 ver = 2;
918
919 req->hdr.version = ver;
6b7c5b94
SP		 920 req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
921
6b7c5b94
SP		 922 AMAP_SET_BITS(struct amap_eq_context, valid, req->context, 1);
923 /* 4byte eqe*/
924 AMAP_SET_BITS(struct amap_eq_context, size, req->context, 0);
925 AMAP_SET_BITS(struct amap_eq_context, count, req->context,
f2f781a7 926 __ilog2_u32(eqo->q.len / 256));
6b7c5b94
SP		 927 be_dws_cpu_to_le(req->context, sizeof(req->context));
928
929 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
930
b31c50a7 931 status = be_mbox_notify_wait(adapter);
6b7c5b94 932 if (!status) {
b31c50a7 933 struct be_cmd_resp_eq_create *resp = embedded_payload(wrb);
03d28ffe 934
f2f781a7
SP		 935 eqo->q.id = le16_to_cpu(resp->eq_id);
936 eqo->msix_idx =
937 (ver == 2) ? le16_to_cpu(resp->msix_idx) : eqo->idx;
938 eqo->q.created = true;
6b7c5b94 939 }
b31c50a7 940
2984961c 941 mutex_unlock(&adapter->mbox_lock);
6b7c5b94
SP		 942 return status;
943}
944
f9449ab7 945/* Use MCC */
8788fdc2 946int be_cmd_mac_addr_query(struct be_adapter *adapter, u8 *mac_addr,
5ee4979b 947 bool permanent, u32 if_handle, u32 pmac_id)
6b7c5b94 948{
b31c50a7
SP		 949 struct be_mcc_wrb *wrb;
950 struct be_cmd_req_mac_query *req;
6b7c5b94
SP		 951 int status;
952
f9449ab7 953 spin_lock_bh(&adapter->mcc_lock);
b31c50a7 954
f9449ab7
SP		 955 wrb = wrb_from_mccq(adapter);
956 if (!wrb) {
957 status = -EBUSY;
958 goto err;
959 }
b31c50a7 960 req = embedded_payload(wrb);
6b7c5b94 961
106df1e3 962 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 963 OPCODE_COMMON_NTWK_MAC_QUERY, sizeof(*req), wrb,
964 NULL);
5ee4979b 965 req->type = MAC_ADDRESS_TYPE_NETWORK;
6b7c5b94
SP		 966 if (permanent) {
967 req->permanent = 1;
968 } else {
504fbf1e 969 req->if_id = cpu_to_le16((u16)if_handle);
590c391d 970 req->pmac_id = cpu_to_le32(pmac_id);
6b7c5b94
SP		 971 req->permanent = 0;
972 }
973
f9449ab7 974 status = be_mcc_notify_wait(adapter);
b31c50a7
SP		 975 if (!status) {
976 struct be_cmd_resp_mac_query *resp = embedded_payload(wrb);
03d28ffe 977
6b7c5b94 978 memcpy(mac_addr, resp->mac.addr, ETH_ALEN);
b31c50a7 979 }
6b7c5b94 980
f9449ab7
SP		 981err:
982 spin_unlock_bh(&adapter->mcc_lock);
6b7c5b94
SP		 983 return status;
984}
985
b31c50a7 986/* Uses synchronous MCCQ */
8788fdc2 987int be_cmd_pmac_add(struct be_adapter *adapter, u8 *mac_addr,
a2cc4e0b 988 u32 if_id, u32 *pmac_id, u32 domain)
6b7c5b94 989{
b31c50a7
SP		 990 struct be_mcc_wrb *wrb;
991 struct be_cmd_req_pmac_add *req;
6b7c5b94
SP		 992 int status;
993
b31c50a7
SP		 994 spin_lock_bh(&adapter->mcc_lock);
995
996 wrb = wrb_from_mccq(adapter);
713d0394
SP		 997 if (!wrb) {
998 status = -EBUSY;
999 goto err;
1000 }
b31c50a7 1001 req = embedded_payload(wrb);
6b7c5b94 1002
106df1e3 1003 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 1004 OPCODE_COMMON_NTWK_PMAC_ADD, sizeof(*req), wrb,
1005 NULL);
6b7c5b94 1006
f8617e08 1007 req->hdr.domain = domain;
6b7c5b94
SP		 1008 req->if_id = cpu_to_le32(if_id);
1009 memcpy(req->mac_address, mac_addr, ETH_ALEN);
1010
b31c50a7 1011 status = be_mcc_notify_wait(adapter);
6b7c5b94
SP		 1012 if (!status) {
1013 struct be_cmd_resp_pmac_add *resp = embedded_payload(wrb);
03d28ffe 1014
6b7c5b94
SP		 1015 *pmac_id = le32_to_cpu(resp->pmac_id);
1016 }
1017
713d0394 1018err:
b31c50a7 1019 spin_unlock_bh(&adapter->mcc_lock);
e3a7ae2c
SK		 1020
1021 if (status == MCC_STATUS_UNAUTHORIZED_REQUEST)
1022 status = -EPERM;
1023
6b7c5b94
SP		 1024 return status;
1025}
1026
b31c50a7 1027/* Uses synchronous MCCQ */
30128031 1028int be_cmd_pmac_del(struct be_adapter *adapter, u32 if_id, int pmac_id, u32 dom)
6b7c5b94 1029{
b31c50a7
SP		 1030 struct be_mcc_wrb *wrb;
1031 struct be_cmd_req_pmac_del *req;
6b7c5b94
SP		 1032 int status;
1033
30128031
SP		 1034 if (pmac_id == -1)
1035 return 0;
1036
b31c50a7
SP		 1037 spin_lock_bh(&adapter->mcc_lock);
1038
1039 wrb = wrb_from_mccq(adapter);
713d0394
SP		 1040 if (!wrb) {
1041 status = -EBUSY;
1042 goto err;
1043 }
b31c50a7 1044 req = embedded_payload(wrb);
6b7c5b94 1045
106df1e3 1046 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
cd3307aa
KA		 1047 OPCODE_COMMON_NTWK_PMAC_DEL, sizeof(*req),
1048 wrb, NULL);
6b7c5b94 1049
f8617e08 1050 req->hdr.domain = dom;
6b7c5b94
SP		 1051 req->if_id = cpu_to_le32(if_id);
1052 req->pmac_id = cpu_to_le32(pmac_id);
1053
b31c50a7
SP		 1054 status = be_mcc_notify_wait(adapter);
1055
713d0394 1056err:
b31c50a7 1057 spin_unlock_bh(&adapter->mcc_lock);
6b7c5b94
SP		 1058 return status;
1059}
1060
b31c50a7 1061/* Uses Mbox */
10ef9ab4 1062int be_cmd_cq_create(struct be_adapter *adapter, struct be_queue_info *cq,
a2cc4e0b 1063 struct be_queue_info *eq, bool no_delay, int coalesce_wm)
6b7c5b94 1064{
b31c50a7
SP		 1065 struct be_mcc_wrb *wrb;
1066 struct be_cmd_req_cq_create *req;
6b7c5b94 1067 struct be_dma_mem *q_mem = &cq->dma_mem;
b31c50a7 1068 void *ctxt;
6b7c5b94
SP		 1069 int status;
1070
2984961c
IV		 1071 if (mutex_lock_interruptible(&adapter->mbox_lock))
1072 return -1;
b31c50a7
SP		 1073
1074 wrb = wrb_from_mbox(adapter);
1075 req = embedded_payload(wrb);
1076 ctxt = &req->context;
6b7c5b94 1077
106df1e3 1078 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 1079 OPCODE_COMMON_CQ_CREATE, sizeof(*req), wrb,
1080 NULL);
6b7c5b94
SP		 1081
1082 req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
bbdc42f8
AK		 1083
1084 if (BEx_chip(adapter)) {
fe6d2a38 1085 AMAP_SET_BITS(struct amap_cq_context_be, coalescwm, ctxt,
a2cc4e0b 1086 coalesce_wm);
fe6d2a38 1087 AMAP_SET_BITS(struct amap_cq_context_be, nodelay,
a2cc4e0b 1088 ctxt, no_delay);
fe6d2a38 1089 AMAP_SET_BITS(struct amap_cq_context_be, count, ctxt,
a2cc4e0b 1090 __ilog2_u32(cq->len / 256));
fe6d2a38 1091 AMAP_SET_BITS(struct amap_cq_context_be, valid, ctxt, 1);
fe6d2a38
SP		 1092 AMAP_SET_BITS(struct amap_cq_context_be, eventable, ctxt, 1);
1093 AMAP_SET_BITS(struct amap_cq_context_be, eqid, ctxt, eq->id);
bbdc42f8
AK		 1094 } else {
1095 req->hdr.version = 2;
1096 req->page_size = 1; /* 1 for 4K */
09e83a9d
AK		 1097
1098 /* coalesce-wm field in this cmd is not relevant to Lancer.
1099 * Lancer uses COMMON_MODIFY_CQ to set this field
1100 */
1101 if (!lancer_chip(adapter))
1102 AMAP_SET_BITS(struct amap_cq_context_v2, coalescwm,
1103 ctxt, coalesce_wm);
bbdc42f8 1104 AMAP_SET_BITS(struct amap_cq_context_v2, nodelay, ctxt,
a2cc4e0b 1105 no_delay);
bbdc42f8 1106 AMAP_SET_BITS(struct amap_cq_context_v2, count, ctxt,
a2cc4e0b 1107 __ilog2_u32(cq->len / 256));
bbdc42f8 1108 AMAP_SET_BITS(struct amap_cq_context_v2, valid, ctxt, 1);
a2cc4e0b
SP		 1109 AMAP_SET_BITS(struct amap_cq_context_v2, eventable, ctxt, 1);
1110 AMAP_SET_BITS(struct amap_cq_context_v2, eqid, ctxt, eq->id);
fe6d2a38 1111 }
6b7c5b94 1112
6b7c5b94
SP		 1113 be_dws_cpu_to_le(ctxt, sizeof(req->context));
1114
1115 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
1116
b31c50a7 1117 status = be_mbox_notify_wait(adapter);
6b7c5b94 1118 if (!status) {
b31c50a7 1119 struct be_cmd_resp_cq_create *resp = embedded_payload(wrb);
03d28ffe 1120
6b7c5b94
SP		 1121 cq->id = le16_to_cpu(resp->cq_id);
1122 cq->created = true;
1123 }
b31c50a7 1124
2984961c 1125 mutex_unlock(&adapter->mbox_lock);
5fb379ee
SP		 1126
1127 return status;
1128}
1129
1130static u32 be_encoded_q_len(int q_len)
1131{
1132 u32 len_encoded = fls(q_len); /* log2(len) + 1 */
03d28ffe 1133
5fb379ee
SP		 1134 if (len_encoded == 16)
1135 len_encoded = 0;
1136 return len_encoded;
1137}
1138
4188e7df 1139static int be_cmd_mccq_ext_create(struct be_adapter *adapter,
a2cc4e0b
SP		 1140 struct be_queue_info *mccq,
1141 struct be_queue_info *cq)
5fb379ee 1142{
b31c50a7 1143 struct be_mcc_wrb *wrb;
34b1ef04 1144 struct be_cmd_req_mcc_ext_create *req;
5fb379ee 1145 struct be_dma_mem *q_mem = &mccq->dma_mem;
b31c50a7 1146 void *ctxt;
5fb379ee
SP		 1147 int status;
1148
2984961c
IV		 1149 if (mutex_lock_interruptible(&adapter->mbox_lock))
1150 return -1;
b31c50a7
SP		 1151
1152 wrb = wrb_from_mbox(adapter);
1153 req = embedded_payload(wrb);
1154 ctxt = &req->context;
5fb379ee 1155
106df1e3 1156 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 1157 OPCODE_COMMON_MCC_CREATE_EXT, sizeof(*req), wrb,
1158 NULL);
5fb379ee 1159
d4a2ac3e 1160 req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
666d39c7 1161 if (BEx_chip(adapter)) {
fe6d2a38
SP		 1162 AMAP_SET_BITS(struct amap_mcc_context_be, valid, ctxt, 1);
1163 AMAP_SET_BITS(struct amap_mcc_context_be, ring_size, ctxt,
a2cc4e0b 1164 be_encoded_q_len(mccq->len));
fe6d2a38 1165 AMAP_SET_BITS(struct amap_mcc_context_be, cq_id, ctxt, cq->id);
666d39c7
VV		 1166 } else {
1167 req->hdr.version = 1;
1168 req->cq_id = cpu_to_le16(cq->id);
1169
1170 AMAP_SET_BITS(struct amap_mcc_context_v1, ring_size, ctxt,
1171 be_encoded_q_len(mccq->len));
1172 AMAP_SET_BITS(struct amap_mcc_context_v1, valid, ctxt, 1);
1173 AMAP_SET_BITS(struct amap_mcc_context_v1, async_cq_id,
1174 ctxt, cq->id);
1175 AMAP_SET_BITS(struct amap_mcc_context_v1, async_cq_valid,
1176 ctxt, 1);
fe6d2a38 1177 }
5fb379ee 1178
21252377
VV		 1179 /* Subscribe to Link State, Sliport Event and Group 5 Events
1180 * (bits 1, 5 and 17 set)
1181 */
1182 req->async_event_bitmap[0] =
1183 cpu_to_le32(BIT(ASYNC_EVENT_CODE_LINK_STATE) |
1184 BIT(ASYNC_EVENT_CODE_GRP_5) |
1185 BIT(ASYNC_EVENT_CODE_QNQ) |
1186 BIT(ASYNC_EVENT_CODE_SLIPORT));
1187
5fb379ee
SP		 1188 be_dws_cpu_to_le(ctxt, sizeof(req->context));
1189
1190 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
1191
b31c50a7 1192 status = be_mbox_notify_wait(adapter);
5fb379ee
SP		 1193 if (!status) {
1194 struct be_cmd_resp_mcc_create *resp = embedded_payload(wrb);
03d28ffe 1195
5fb379ee
SP		 1196 mccq->id = le16_to_cpu(resp->id);
1197 mccq->created = true;
1198 }
2984961c 1199 mutex_unlock(&adapter->mbox_lock);
6b7c5b94
SP		 1200
1201 return status;
1202}
1203
4188e7df 1204static int be_cmd_mccq_org_create(struct be_adapter *adapter,
a2cc4e0b
SP		 1205 struct be_queue_info *mccq,
1206 struct be_queue_info *cq)
34b1ef04
SK		 1207{
1208 struct be_mcc_wrb *wrb;
1209 struct be_cmd_req_mcc_create *req;
1210 struct be_dma_mem *q_mem = &mccq->dma_mem;
1211 void *ctxt;
1212 int status;
1213
1214 if (mutex_lock_interruptible(&adapter->mbox_lock))
1215 return -1;
1216
1217 wrb = wrb_from_mbox(adapter);
1218 req = embedded_payload(wrb);
1219 ctxt = &req->context;
1220
106df1e3 1221 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 1222 OPCODE_COMMON_MCC_CREATE, sizeof(*req), wrb,
1223 NULL);
34b1ef04
SK		 1224
1225 req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
1226
1227 AMAP_SET_BITS(struct amap_mcc_context_be, valid, ctxt, 1);
1228 AMAP_SET_BITS(struct amap_mcc_context_be, ring_size, ctxt,
a2cc4e0b 1229 be_encoded_q_len(mccq->len));
34b1ef04
SK		 1230 AMAP_SET_BITS(struct amap_mcc_context_be, cq_id, ctxt, cq->id);
1231
1232 be_dws_cpu_to_le(ctxt, sizeof(req->context));
1233
1234 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
1235
1236 status = be_mbox_notify_wait(adapter);
1237 if (!status) {
1238 struct be_cmd_resp_mcc_create *resp = embedded_payload(wrb);
03d28ffe 1239
34b1ef04
SK		 1240 mccq->id = le16_to_cpu(resp->id);
1241 mccq->created = true;
1242 }
1243
1244 mutex_unlock(&adapter->mbox_lock);
1245 return status;
1246}
1247
1248int be_cmd_mccq_create(struct be_adapter *adapter,
a2cc4e0b 1249 struct be_queue_info *mccq, struct be_queue_info *cq)
34b1ef04
SK		 1250{
1251 int status;
1252
1253 status = be_cmd_mccq_ext_create(adapter, mccq, cq);
666d39c7 1254 if (status && BEx_chip(adapter)) {
34b1ef04
SK		 1255 dev_warn(&adapter->pdev->dev, "Upgrade to F/W ver 2.102.235.0 "
1256 "or newer to avoid conflicting priorities between NIC "
1257 "and FCoE traffic");
1258 status = be_cmd_mccq_org_create(adapter, mccq, cq);
1259 }
1260 return status;
1261}
1262
94d73aaa 1263int be_cmd_txq_create(struct be_adapter *adapter, struct be_tx_obj *txo)
6b7c5b94 1264{
7707133c 1265 struct be_mcc_wrb wrb = {0};
b31c50a7 1266 struct be_cmd_req_eth_tx_create *req;
94d73aaa
VV		 1267 struct be_queue_info *txq = &txo->q;
1268 struct be_queue_info *cq = &txo->cq;
6b7c5b94 1269 struct be_dma_mem *q_mem = &txq->dma_mem;
94d73aaa 1270 int status, ver = 0;
6b7c5b94 1271
7707133c 1272 req = embedded_payload(&wrb);
106df1e3 1273 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
a2cc4e0b 1274 OPCODE_ETH_TX_CREATE, sizeof(*req), &wrb, NULL);
6b7c5b94 1275
8b7756ca
PR		 1276 if (lancer_chip(adapter)) {
1277 req->hdr.version = 1;
94d73aaa
VV		 1278 } else if (BEx_chip(adapter)) {
1279 if (adapter->function_caps & BE_FUNCTION_CAPS_SUPER_NIC)
1280 req->hdr.version = 2;
1281 } else { /* For SH */
1282 req->hdr.version = 2;
8b7756ca
PR		 1283 }
1284
81b02655
VV		 1285 if (req->hdr.version > 0)
1286 req->if_id = cpu_to_le16(adapter->if_handle);
6b7c5b94
SP		 1287 req->num_pages = PAGES_4K_SPANNED(q_mem->va, q_mem->size);
1288 req->ulp_num = BE_ULP1_NUM;
1289 req->type = BE_ETH_TX_RING_TYPE_STANDARD;
94d73aaa
VV		 1290 req->cq_id = cpu_to_le16(cq->id);
1291 req->queue_size = be_encoded_q_len(txq->len);
6b7c5b94 1292 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
94d73aaa
VV		 1293 ver = req->hdr.version;
1294
7707133c 1295 status = be_cmd_notify_wait(adapter, &wrb);
6b7c5b94 1296 if (!status) {
7707133c 1297 struct be_cmd_resp_eth_tx_create *resp = embedded_payload(&wrb);
03d28ffe 1298
6b7c5b94 1299 txq->id = le16_to_cpu(resp->cid);
94d73aaa
VV		 1300 if (ver == 2)
1301 txo->db_offset = le32_to_cpu(resp->db_offset);
1302 else
1303 txo->db_offset = DB_TXULP1_OFFSET;
6b7c5b94
SP		 1304 txq->created = true;
1305 }
b31c50a7 1306
6b7c5b94
SP		 1307 return status;
1308}
1309
482c9e79 1310/* Uses MCC */
8788fdc2 1311int be_cmd_rxq_create(struct be_adapter *adapter,
a2cc4e0b
SP		 1312 struct be_queue_info *rxq, u16 cq_id, u16 frag_size,
1313 u32 if_id, u32 rss, u8 *rss_id)
6b7c5b94 1314{
b31c50a7
SP		 1315 struct be_mcc_wrb *wrb;
1316 struct be_cmd_req_eth_rx_create *req;
6b7c5b94
SP		 1317 struct be_dma_mem *q_mem = &rxq->dma_mem;
1318 int status;
1319
482c9e79 1320 spin_lock_bh(&adapter->mcc_lock);
b31c50a7 1321
482c9e79
SP		 1322 wrb = wrb_from_mccq(adapter);
1323 if (!wrb) {
1324 status = -EBUSY;
1325 goto err;
1326 }
b31c50a7 1327 req = embedded_payload(wrb);
6b7c5b94 1328
106df1e3 1329 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
a2cc4e0b 1330 OPCODE_ETH_RX_CREATE, sizeof(*req), wrb, NULL);
6b7c5b94
SP		 1331
1332 req->cq_id = cpu_to_le16(cq_id);
1333 req->frag_size = fls(frag_size) - 1;
1334 req->num_pages = 2;
1335 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
1336 req->interface_id = cpu_to_le32(if_id);
10ef9ab4 1337 req->max_frame_size = cpu_to_le16(BE_MAX_JUMBO_FRAME_SIZE);
6b7c5b94
SP		 1338 req->rss_queue = cpu_to_le32(rss);
1339
482c9e79 1340 status = be_mcc_notify_wait(adapter);
6b7c5b94
SP		 1341 if (!status) {
1342 struct be_cmd_resp_eth_rx_create *resp = embedded_payload(wrb);
03d28ffe 1343
6b7c5b94
SP		 1344 rxq->id = le16_to_cpu(resp->id);
1345 rxq->created = true;
3abcdeda 1346 *rss_id = resp->rss_id;
6b7c5b94 1347 }
b31c50a7 1348
482c9e79
SP		 1349err:
1350 spin_unlock_bh(&adapter->mcc_lock);
6b7c5b94
SP		 1351 return status;
1352}
1353
b31c50a7
SP		 1354/* Generic destroyer function for all types of queues
1355 * Uses Mbox
1356 */
8788fdc2 1357int be_cmd_q_destroy(struct be_adapter *adapter, struct be_queue_info *q,
a2cc4e0b 1358 int queue_type)
6b7c5b94 1359{
b31c50a7
SP		 1360 struct be_mcc_wrb *wrb;
1361 struct be_cmd_req_q_destroy *req;
6b7c5b94
SP		 1362 u8 subsys = 0, opcode = 0;
1363 int status;
1364
2984961c
IV		 1365 if (mutex_lock_interruptible(&adapter->mbox_lock))
1366 return -1;
6b7c5b94 1367
b31c50a7
SP		 1368 wrb = wrb_from_mbox(adapter);
1369 req = embedded_payload(wrb);
1370
6b7c5b94
SP		 1371 switch (queue_type) {
1372 case QTYPE_EQ:
1373 subsys = CMD_SUBSYSTEM_COMMON;
1374 opcode = OPCODE_COMMON_EQ_DESTROY;
1375 break;
1376 case QTYPE_CQ:
1377 subsys = CMD_SUBSYSTEM_COMMON;
1378 opcode = OPCODE_COMMON_CQ_DESTROY;
1379 break;
1380 case QTYPE_TXQ:
1381 subsys = CMD_SUBSYSTEM_ETH;
1382 opcode = OPCODE_ETH_TX_DESTROY;
1383 break;
1384 case QTYPE_RXQ:
1385 subsys = CMD_SUBSYSTEM_ETH;
1386 opcode = OPCODE_ETH_RX_DESTROY;
1387 break;
5fb379ee
SP		 1388 case QTYPE_MCCQ:
1389 subsys = CMD_SUBSYSTEM_COMMON;
1390 opcode = OPCODE_COMMON_MCC_DESTROY;
1391 break;
6b7c5b94 1392 default:
5f0b849e 1393 BUG();
6b7c5b94 1394 }
d744b44e 1395
106df1e3 1396 be_wrb_cmd_hdr_prepare(&req->hdr, subsys, opcode, sizeof(*req), wrb,
a2cc4e0b 1397 NULL);
6b7c5b94
SP		 1398 req->id = cpu_to_le16(q->id);
1399
b31c50a7 1400 status = be_mbox_notify_wait(adapter);
aa790db9 1401 q->created = false;
5f0b849e 1402
2984961c 1403 mutex_unlock(&adapter->mbox_lock);
482c9e79
SP		 1404 return status;
1405}
6b7c5b94 1406
482c9e79
SP		 1407/* Uses MCC */
1408int be_cmd_rxq_destroy(struct be_adapter *adapter, struct be_queue_info *q)
1409{
1410 struct be_mcc_wrb *wrb;
1411 struct be_cmd_req_q_destroy *req;
1412 int status;
1413
1414 spin_lock_bh(&adapter->mcc_lock);
1415
1416 wrb = wrb_from_mccq(adapter);
1417 if (!wrb) {
1418 status = -EBUSY;
1419 goto err;
1420 }
1421 req = embedded_payload(wrb);
1422
106df1e3 1423 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
a2cc4e0b 1424 OPCODE_ETH_RX_DESTROY, sizeof(*req), wrb, NULL);
482c9e79
SP		 1425 req->id = cpu_to_le16(q->id);
1426
1427 status = be_mcc_notify_wait(adapter);
aa790db9 1428 q->created = false;
482c9e79
SP		 1429
1430err:
1431 spin_unlock_bh(&adapter->mcc_lock);
6b7c5b94
SP		 1432 return status;
1433}
1434
b31c50a7 1435/* Create an rx filtering policy configuration on an i/f
bea50988 1436 * Will use MBOX only if MCCQ has not been created.
b31c50a7 1437 */
73d540f2 1438int be_cmd_if_create(struct be_adapter *adapter, u32 cap_flags, u32 en_flags,
1578e777 1439 u32 *if_handle, u32 domain)
6b7c5b94 1440{
bea50988 1441 struct be_mcc_wrb wrb = {0};
b31c50a7 1442 struct be_cmd_req_if_create *req;
6b7c5b94
SP		 1443 int status;
1444
bea50988 1445 req = embedded_payload(&wrb);
106df1e3 1446 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 1447 OPCODE_COMMON_NTWK_INTERFACE_CREATE,
1448 sizeof(*req), &wrb, NULL);
ba343c77 1449 req->hdr.domain = domain;
73d540f2
SP		 1450 req->capability_flags = cpu_to_le32(cap_flags);
1451 req->enable_flags = cpu_to_le32(en_flags);
1578e777 1452 req->pmac_invalid = true;
6b7c5b94 1453
bea50988 1454 status = be_cmd_notify_wait(adapter, &wrb);
6b7c5b94 1455 if (!status) {
bea50988 1456 struct be_cmd_resp_if_create *resp = embedded_payload(&wrb);
03d28ffe 1457
6b7c5b94 1458 *if_handle = le32_to_cpu(resp->interface_id);
b5bb9776
SP		 1459
1460 /* Hack to retrieve VF's pmac-id on BE3 */
18c57c74 1461 if (BE3_chip(adapter) && be_virtfn(adapter))
b5bb9776 1462 adapter->pmac_id[0] = le32_to_cpu(resp->pmac_id);
6b7c5b94 1463 }
6b7c5b94
SP		 1464 return status;
1465}
1466
f9449ab7 1467/* Uses MCCQ */
30128031 1468int be_cmd_if_destroy(struct be_adapter *adapter, int interface_id, u32 domain)
6b7c5b94 1469{
b31c50a7
SP		 1470 struct be_mcc_wrb *wrb;
1471 struct be_cmd_req_if_destroy *req;
6b7c5b94
SP		 1472 int status;
1473
30128031 1474 if (interface_id == -1)
f9449ab7 1475 return 0;
b31c50a7 1476
f9449ab7
SP		 1477 spin_lock_bh(&adapter->mcc_lock);
1478
1479 wrb = wrb_from_mccq(adapter);
1480 if (!wrb) {
1481 status = -EBUSY;
1482 goto err;
1483 }
b31c50a7 1484 req = embedded_payload(wrb);
6b7c5b94 1485
106df1e3 1486 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 1487 OPCODE_COMMON_NTWK_INTERFACE_DESTROY,
1488 sizeof(*req), wrb, NULL);
658681f7 1489 req->hdr.domain = domain;
6b7c5b94 1490 req->interface_id = cpu_to_le32(interface_id);
b31c50a7 1491
f9449ab7
SP		 1492 status = be_mcc_notify_wait(adapter);
1493err:
1494 spin_unlock_bh(&adapter->mcc_lock);
6b7c5b94
SP		 1495 return status;
1496}
1497
1498/* Get stats is a non embedded command: the request is not embedded inside
1499 * WRB but is a separate dma memory block
b31c50a7 1500 * Uses asynchronous MCC
6b7c5b94 1501 */
8788fdc2 1502int be_cmd_get_stats(struct be_adapter *adapter, struct be_dma_mem *nonemb_cmd)
6b7c5b94 1503{
b31c50a7 1504 struct be_mcc_wrb *wrb;
89a88ab8 1505 struct be_cmd_req_hdr *hdr;
713d0394 1506 int status = 0;
6b7c5b94 1507
b31c50a7 1508 spin_lock_bh(&adapter->mcc_lock);
6b7c5b94 1509
b31c50a7 1510 wrb = wrb_from_mccq(adapter);
713d0394
SP		 1511 if (!wrb) {
1512 status = -EBUSY;
1513 goto err;
1514 }
89a88ab8 1515 hdr = nonemb_cmd->va;
6b7c5b94 1516
106df1e3 1517 be_wrb_cmd_hdr_prepare(hdr, CMD_SUBSYSTEM_ETH,
a2cc4e0b
SP		 1518 OPCODE_ETH_GET_STATISTICS, nonemb_cmd->size, wrb,
1519 nonemb_cmd);
89a88ab8 1520
ca34fe38 1521 /* version 1 of the cmd is not supported only by BE2 */
61000861
AK		 1522 if (BE2_chip(adapter))
1523 hdr->version = 0;
1524 if (BE3_chip(adapter) || lancer_chip(adapter))
89a88ab8 1525 hdr->version = 1;
61000861
AK		 1526 else
1527 hdr->version = 2;
89a88ab8 1528
b31c50a7 1529 be_mcc_notify(adapter);
b2aebe6d 1530 adapter->stats_cmd_sent = true;
6b7c5b94 1531
713d0394 1532err:
b31c50a7 1533 spin_unlock_bh(&adapter->mcc_lock);
713d0394 1534 return status;
6b7c5b94
SP		 1535}
1536
005d5696
SX		 1537/* Lancer Stats */
1538int lancer_cmd_get_pport_stats(struct be_adapter *adapter,
a2cc4e0b 1539 struct be_dma_mem *nonemb_cmd)
005d5696 1540{
005d5696
SX		 1541 struct be_mcc_wrb *wrb;
1542 struct lancer_cmd_req_pport_stats *req;
005d5696
SX		 1543 int status = 0;
1544
f25b119c
PR		 1545 if (!be_cmd_allowed(adapter, OPCODE_ETH_GET_PPORT_STATS,
1546 CMD_SUBSYSTEM_ETH))
1547 return -EPERM;
1548
005d5696
SX		 1549 spin_lock_bh(&adapter->mcc_lock);
1550
1551 wrb = wrb_from_mccq(adapter);
1552 if (!wrb) {
1553 status = -EBUSY;
1554 goto err;
1555 }
1556 req = nonemb_cmd->va;
005d5696 1557
106df1e3 1558 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
a2cc4e0b
SP		 1559 OPCODE_ETH_GET_PPORT_STATS, nonemb_cmd->size,
1560 wrb, nonemb_cmd);
005d5696 1561
d51ebd33 1562 req->cmd_params.params.pport_num = cpu_to_le16(adapter->hba_port_num);
005d5696
SX		 1563 req->cmd_params.params.reset_stats = 0;
1564
005d5696
SX		 1565 be_mcc_notify(adapter);
1566 adapter->stats_cmd_sent = true;
1567
1568err:
1569 spin_unlock_bh(&adapter->mcc_lock);
1570 return status;
1571}
1572
323ff71e
SP		 1573static int be_mac_to_link_speed(int mac_speed)
1574{
1575 switch (mac_speed) {
1576 case PHY_LINK_SPEED_ZERO:
1577 return 0;
1578 case PHY_LINK_SPEED_10MBPS:
1579 return 10;
1580 case PHY_LINK_SPEED_100MBPS:
1581 return 100;
1582 case PHY_LINK_SPEED_1GBPS:
1583 return 1000;
1584 case PHY_LINK_SPEED_10GBPS:
1585 return 10000;
b971f847
VV		 1586 case PHY_LINK_SPEED_20GBPS:
1587 return 20000;
1588 case PHY_LINK_SPEED_25GBPS:
1589 return 25000;
1590 case PHY_LINK_SPEED_40GBPS:
1591 return 40000;
323ff71e
SP		 1592 }
1593 return 0;
1594}
1595
1596/* Uses synchronous mcc
1597 * Returns link_speed in Mbps
1598 */
1599int be_cmd_link_status_query(struct be_adapter *adapter, u16 *link_speed,
1600 u8 *link_status, u32 dom)
6b7c5b94 1601{
b31c50a7
SP		 1602 struct be_mcc_wrb *wrb;
1603 struct be_cmd_req_link_status *req;
6b7c5b94
SP		 1604 int status;
1605
b31c50a7
SP		 1606 spin_lock_bh(&adapter->mcc_lock);
1607
b236916a
AK		 1608 if (link_status)
1609 *link_status = LINK_DOWN;
1610
b31c50a7 1611 wrb = wrb_from_mccq(adapter);
713d0394
SP		 1612 if (!wrb) {
1613 status = -EBUSY;
1614 goto err;
1615 }
b31c50a7 1616 req = embedded_payload(wrb);
a8f447bd 1617
57cd80d4 1618 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 1619 OPCODE_COMMON_NTWK_LINK_STATUS_QUERY,
1620 sizeof(*req), wrb, NULL);
57cd80d4 1621
ca34fe38
SP		 1622 /* version 1 of the cmd is not supported only by BE2 */
1623 if (!BE2_chip(adapter))
daad6167
PR		 1624 req->hdr.version = 1;
1625
57cd80d4 1626 req->hdr.domain = dom;
6b7c5b94 1627
b31c50a7 1628 status = be_mcc_notify_wait(adapter);
6b7c5b94
SP		 1629 if (!status) {
1630 struct be_cmd_resp_link_status *resp = embedded_payload(wrb);
03d28ffe 1631
323ff71e
SP		 1632 if (link_speed) {
1633 *link_speed = resp->link_speed ?
1634 le16_to_cpu(resp->link_speed) * 10 :
1635 be_mac_to_link_speed(resp->mac_speed);
1636
1637 if (!resp->logical_link_status)
1638 *link_speed = 0;
0388f251 1639 }
b236916a
AK		 1640 if (link_status)
1641 *link_status = resp->logical_link_status;
6b7c5b94
SP		 1642 }
1643
713d0394 1644err:
b31c50a7 1645 spin_unlock_bh(&adapter->mcc_lock);
6b7c5b94
SP		 1646 return status;
1647}
1648
609ff3bb
AK		 1649/* Uses synchronous mcc */
1650int be_cmd_get_die_temperature(struct be_adapter *adapter)
1651{
1652 struct be_mcc_wrb *wrb;
1653 struct be_cmd_req_get_cntl_addnl_attribs *req;
117affe3 1654 int status = 0;
609ff3bb
AK		 1655
1656 spin_lock_bh(&adapter->mcc_lock);
1657
1658 wrb = wrb_from_mccq(adapter);
1659 if (!wrb) {
1660 status = -EBUSY;
1661 goto err;
1662 }
1663 req = embedded_payload(wrb);
1664
106df1e3 1665 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 1666 OPCODE_COMMON_GET_CNTL_ADDITIONAL_ATTRIBUTES,
1667 sizeof(*req), wrb, NULL);
609ff3bb 1668
3de09455 1669 be_mcc_notify(adapter);
609ff3bb
AK		 1670
1671err:
1672 spin_unlock_bh(&adapter->mcc_lock);
1673 return status;
1674}
1675
311fddc7
SK		 1676/* Uses synchronous mcc */
1677int be_cmd_get_reg_len(struct be_adapter *adapter, u32 *log_size)
1678{
1679 struct be_mcc_wrb *wrb;
1680 struct be_cmd_req_get_fat *req;
1681 int status;
1682
1683 spin_lock_bh(&adapter->mcc_lock);
1684
1685 wrb = wrb_from_mccq(adapter);
1686 if (!wrb) {
1687 status = -EBUSY;
1688 goto err;
1689 }
1690 req = embedded_payload(wrb);
1691
106df1e3 1692 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 1693 OPCODE_COMMON_MANAGE_FAT, sizeof(*req), wrb,
1694 NULL);
311fddc7
SK		 1695 req->fat_operation = cpu_to_le32(QUERY_FAT);
1696 status = be_mcc_notify_wait(adapter);
1697 if (!status) {
1698 struct be_cmd_resp_get_fat *resp = embedded_payload(wrb);
03d28ffe 1699
311fddc7 1700 if (log_size && resp->log_size)
fe2a70ee
SK		 1701 *log_size = le32_to_cpu(resp->log_size) -
1702 sizeof(u32);
311fddc7
SK		 1703 }
1704err:
1705 spin_unlock_bh(&adapter->mcc_lock);
1706 return status;
1707}
1708
c5f156de 1709int be_cmd_get_regs(struct be_adapter *adapter, u32 buf_len, void *buf)
311fddc7
SK		 1710{
1711 struct be_dma_mem get_fat_cmd;
1712 struct be_mcc_wrb *wrb;
1713 struct be_cmd_req_get_fat *req;
fe2a70ee
SK		 1714 u32 offset = 0, total_size, buf_size,
1715 log_offset = sizeof(u32), payload_len;
c5f156de 1716 int status = 0;
311fddc7
SK		 1717
1718 if (buf_len == 0)
c5f156de 1719 return -EIO;
311fddc7
SK		 1720
1721 total_size = buf_len;
1722
fe2a70ee
SK		 1723 get_fat_cmd.size = sizeof(struct be_cmd_req_get_fat) + 60*1024;
1724 get_fat_cmd.va = pci_alloc_consistent(adapter->pdev,
a2cc4e0b
SP		 1725 get_fat_cmd.size,
1726 &get_fat_cmd.dma);
fe2a70ee 1727 if (!get_fat_cmd.va) {
fe2a70ee 1728 dev_err(&adapter->pdev->dev,
cd3307aa 1729 "Memory allocation failure while reading FAT data\n");
c5f156de 1730 return -ENOMEM;
fe2a70ee
SK		 1731 }
1732
311fddc7
SK		 1733 spin_lock_bh(&adapter->mcc_lock);
1734
311fddc7
SK		 1735 while (total_size) {
1736 buf_size = min(total_size, (u32)60*1024);
1737 total_size -= buf_size;
1738
fe2a70ee
SK		 1739 wrb = wrb_from_mccq(adapter);
1740 if (!wrb) {
1741 status = -EBUSY;
311fddc7
SK		 1742 goto err;
1743 }
1744 req = get_fat_cmd.va;
311fddc7 1745
fe2a70ee 1746 payload_len = sizeof(struct be_cmd_req_get_fat) + buf_size;
106df1e3 1747 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 1748 OPCODE_COMMON_MANAGE_FAT, payload_len,
1749 wrb, &get_fat_cmd);
311fddc7
SK		 1750
1751 req->fat_operation = cpu_to_le32(RETRIEVE_FAT);
1752 req->read_log_offset = cpu_to_le32(log_offset);
1753 req->read_log_length = cpu_to_le32(buf_size);
1754 req->data_buffer_size = cpu_to_le32(buf_size);
1755
1756 status = be_mcc_notify_wait(adapter);
1757 if (!status) {
1758 struct be_cmd_resp_get_fat *resp = get_fat_cmd.va;
03d28ffe 1759
311fddc7 1760 memcpy(buf + offset,
a2cc4e0b
SP		 1761 resp->data_buffer,
1762 le32_to_cpu(resp->read_log_length));
fe2a70ee 1763 } else {
311fddc7 1764 dev_err(&adapter->pdev->dev, "FAT Table Retrieve error\n");
fe2a70ee
SK		 1765 goto err;
1766 }
311fddc7
SK		 1767 offset += buf_size;
1768 log_offset += buf_size;
1769 }
1770err:
fe2a70ee 1771 pci_free_consistent(adapter->pdev, get_fat_cmd.size,
a2cc4e0b 1772 get_fat_cmd.va, get_fat_cmd.dma);
311fddc7 1773 spin_unlock_bh(&adapter->mcc_lock);
c5f156de 1774 return status;
311fddc7
SK		 1775}
1776
04b71175 1777/* Uses synchronous mcc */
e97e3cda 1778int be_cmd_get_fw_ver(struct be_adapter *adapter)
6b7c5b94 1779{
b31c50a7
SP		 1780 struct be_mcc_wrb *wrb;
1781 struct be_cmd_req_get_fw_version *req;
6b7c5b94
SP		 1782 int status;
1783
04b71175 1784 spin_lock_bh(&adapter->mcc_lock);
b31c50a7 1785
04b71175
SP		 1786 wrb = wrb_from_mccq(adapter);
1787 if (!wrb) {
1788 status = -EBUSY;
1789 goto err;
1790 }
6b7c5b94 1791
04b71175 1792 req = embedded_payload(wrb);
6b7c5b94 1793
106df1e3 1794 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 1795 OPCODE_COMMON_GET_FW_VERSION, sizeof(*req), wrb,
1796 NULL);
04b71175 1797 status = be_mcc_notify_wait(adapter);
6b7c5b94
SP		 1798 if (!status) {
1799 struct be_cmd_resp_get_fw_version *resp = embedded_payload(wrb);
acbafeb1 1800
242eb470
VV		 1801 strlcpy(adapter->fw_ver, resp->firmware_version_string,
1802 sizeof(adapter->fw_ver));
1803 strlcpy(adapter->fw_on_flash, resp->fw_on_flash_version_string,
1804 sizeof(adapter->fw_on_flash));
6b7c5b94 1805 }
04b71175
SP		 1806err:
1807 spin_unlock_bh(&adapter->mcc_lock);
6b7c5b94
SP		 1808 return status;
1809}
1810
b31c50a7
SP		 1811/* set the EQ delay interval of an EQ to specified value
1812 * Uses async mcc
1813 */
b502ae8d
KA		 1814static int __be_cmd_modify_eqd(struct be_adapter *adapter,
1815 struct be_set_eqd *set_eqd, int num)
6b7c5b94 1816{
b31c50a7
SP		 1817 struct be_mcc_wrb *wrb;
1818 struct be_cmd_req_modify_eq_delay *req;
2632bafd 1819 int status = 0, i;
6b7c5b94 1820
b31c50a7
SP		 1821 spin_lock_bh(&adapter->mcc_lock);
1822
1823 wrb = wrb_from_mccq(adapter);
713d0394
SP		 1824 if (!wrb) {
1825 status = -EBUSY;
1826 goto err;
1827 }
b31c50a7 1828 req = embedded_payload(wrb);
6b7c5b94 1829
106df1e3 1830 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 1831 OPCODE_COMMON_MODIFY_EQ_DELAY, sizeof(*req), wrb,
1832 NULL);
6b7c5b94 1833
2632bafd
SP		 1834 req->num_eq = cpu_to_le32(num);
1835 for (i = 0; i < num; i++) {
1836 req->set_eqd[i].eq_id = cpu_to_le32(set_eqd[i].eq_id);
1837 req->set_eqd[i].phase = 0;
1838 req->set_eqd[i].delay_multiplier =
1839 cpu_to_le32(set_eqd[i].delay_multiplier);
1840 }
6b7c5b94 1841
b31c50a7 1842 be_mcc_notify(adapter);
713d0394 1843err:
b31c50a7 1844 spin_unlock_bh(&adapter->mcc_lock);
713d0394 1845 return status;
6b7c5b94
SP		 1846}
1847
93676703
KA		 1848int be_cmd_modify_eqd(struct be_adapter *adapter, struct be_set_eqd *set_eqd,
1849 int num)
1850{
1851 int num_eqs, i = 0;
1852
c8ba4ad0
SR		 1853 while (num) {
1854 num_eqs = min(num, 8);
1855 __be_cmd_modify_eqd(adapter, &set_eqd[i], num_eqs);
1856 i += num_eqs;
1857 num -= num_eqs;
93676703
KA		 1858 }
1859
1860 return 0;
1861}
1862
b31c50a7 1863/* Uses sycnhronous mcc */
8788fdc2 1864int be_cmd_vlan_config(struct be_adapter *adapter, u32 if_id, u16 *vtag_array,
435452aa 1865 u32 num, u32 domain)
6b7c5b94 1866{
b31c50a7
SP		 1867 struct be_mcc_wrb *wrb;
1868 struct be_cmd_req_vlan_config *req;
6b7c5b94
SP		 1869 int status;
1870
b31c50a7
SP		 1871 spin_lock_bh(&adapter->mcc_lock);
1872
1873 wrb = wrb_from_mccq(adapter);
713d0394
SP		 1874 if (!wrb) {
1875 status = -EBUSY;
1876 goto err;
1877 }
b31c50a7 1878 req = embedded_payload(wrb);
6b7c5b94 1879
106df1e3 1880 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 1881 OPCODE_COMMON_NTWK_VLAN_CONFIG, sizeof(*req),
1882 wrb, NULL);
435452aa 1883 req->hdr.domain = domain;
6b7c5b94
SP		 1884
1885 req->interface_id = if_id;
012bd387 1886 req->untagged = BE_IF_FLAGS_UNTAGGED & be_if_cap_flags(adapter) ? 1 : 0;
6b7c5b94 1887 req->num_vlan = num;
4d567d97
KA		 1888 memcpy(req->normal_vlan, vtag_array,
1889 req->num_vlan * sizeof(vtag_array[0]));
6b7c5b94 1890
b31c50a7 1891 status = be_mcc_notify_wait(adapter);
713d0394 1892err:
b31c50a7 1893 spin_unlock_bh(&adapter->mcc_lock);
6b7c5b94
SP		 1894 return status;
1895}
1896
ac34b743 1897static int __be_cmd_rx_filter(struct be_adapter *adapter, u32 flags, u32 value)
6b7c5b94 1898{
6ac7b687 1899 struct be_mcc_wrb *wrb;
5b8821b7
SP		 1900 struct be_dma_mem *mem = &adapter->rx_filter;
1901 struct be_cmd_req_rx_filter *req = mem->va;
e7b909a6 1902 int status;
6b7c5b94 1903
8788fdc2 1904 spin_lock_bh(&adapter->mcc_lock);
6ac7b687 1905
b31c50a7 1906 wrb = wrb_from_mccq(adapter);
713d0394
SP		 1907 if (!wrb) {
1908 status = -EBUSY;
1909 goto err;
1910 }
5b8821b7 1911 memset(req, 0, sizeof(*req));
106df1e3 1912 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 1913 OPCODE_COMMON_NTWK_RX_FILTER, sizeof(*req),
1914 wrb, mem);
6b7c5b94 1915
5b8821b7 1916 req->if_id = cpu_to_le32(adapter->if_handle);
ac34b743
SP		 1917 req->if_flags_mask = cpu_to_le32(flags);
1918 req->if_flags = (value == ON) ? req->if_flags_mask : 0;
1919
1920 if (flags & BE_IF_FLAGS_MULTICAST) {
22bedad3 1921 struct netdev_hw_addr *ha;
5b8821b7 1922 int i = 0;
24307eef 1923
1610c79f
PR		 1924 /* Reset mcast promisc mode if already set by setting mask
1925 * and not setting flags field
1926 */
abb93951
PR		 1927 req->if_flags_mask |=
1928 cpu_to_le32(BE_IF_FLAGS_MCAST_PROMISCUOUS &
92bf14ab 1929 be_if_cap_flags(adapter));
016f97b1 1930 req->mcast_num = cpu_to_le32(netdev_mc_count(adapter->netdev));
5b8821b7
SP		 1931 netdev_for_each_mc_addr(ha, adapter->netdev)
1932 memcpy(req->mcast_mac[i++].byte, ha->addr, ETH_ALEN);
6b7c5b94
SP		 1933 }
1934
0d1d5875 1935 status = be_mcc_notify_wait(adapter);
713d0394 1936err:
8788fdc2 1937 spin_unlock_bh(&adapter->mcc_lock);
e7b909a6 1938 return status;
6b7c5b94
SP		 1939}
1940
ac34b743
SP		 1941int be_cmd_rx_filter(struct be_adapter *adapter, u32 flags, u32 value)
1942{
1943 struct device *dev = &adapter->pdev->dev;
1944
1945 if ((flags & be_if_cap_flags(adapter)) != flags) {
1946 dev_warn(dev, "Cannot set rx filter flags 0x%x\n", flags);
1947 dev_warn(dev, "Interface is capable of 0x%x flags only\n",
1948 be_if_cap_flags(adapter));
1949 }
1950 flags &= be_if_cap_flags(adapter);
1951
1952 return __be_cmd_rx_filter(adapter, flags, value);
1953}
1954
b31c50a7 1955/* Uses synchrounous mcc */
8788fdc2 1956int be_cmd_set_flow_control(struct be_adapter *adapter, u32 tx_fc, u32 rx_fc)
6b7c5b94 1957{
b31c50a7
SP		 1958 struct be_mcc_wrb *wrb;
1959 struct be_cmd_req_set_flow_control *req;
6b7c5b94
SP		 1960 int status;
1961
f25b119c
PR		 1962 if (!be_cmd_allowed(adapter, OPCODE_COMMON_SET_FLOW_CONTROL,
1963 CMD_SUBSYSTEM_COMMON))
1964 return -EPERM;
1965
b31c50a7 1966 spin_lock_bh(&adapter->mcc_lock);
6b7c5b94 1967
b31c50a7 1968 wrb = wrb_from_mccq(adapter);
713d0394
SP		 1969 if (!wrb) {
1970 status = -EBUSY;
1971 goto err;
1972 }
b31c50a7 1973 req = embedded_payload(wrb);
6b7c5b94 1974
106df1e3 1975 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 1976 OPCODE_COMMON_SET_FLOW_CONTROL, sizeof(*req),
1977 wrb, NULL);
6b7c5b94 1978
b29812c1 1979 req->hdr.version = 1;
6b7c5b94
SP		 1980 req->tx_flow_control = cpu_to_le16((u16)tx_fc);
1981 req->rx_flow_control = cpu_to_le16((u16)rx_fc);
1982
b31c50a7 1983 status = be_mcc_notify_wait(adapter);
6b7c5b94 1984
713d0394 1985err:
b31c50a7 1986 spin_unlock_bh(&adapter->mcc_lock);
b29812c1
SR		 1987
1988 if (base_status(status) == MCC_STATUS_FEATURE_NOT_SUPPORTED)
1989 return -EOPNOTSUPP;
1990
6b7c5b94
SP		 1991 return status;
1992}
1993
b31c50a7 1994/* Uses sycn mcc */
8788fdc2 1995int be_cmd_get_flow_control(struct be_adapter *adapter, u32 *tx_fc, u32 *rx_fc)
6b7c5b94 1996{
b31c50a7
SP		 1997 struct be_mcc_wrb *wrb;
1998 struct be_cmd_req_get_flow_control *req;
6b7c5b94
SP		 1999 int status;
2000
f25b119c
PR		 2001 if (!be_cmd_allowed(adapter, OPCODE_COMMON_GET_FLOW_CONTROL,
2002 CMD_SUBSYSTEM_COMMON))
2003 return -EPERM;
2004
b31c50a7 2005 spin_lock_bh(&adapter->mcc_lock);
6b7c5b94 2006
b31c50a7 2007 wrb = wrb_from_mccq(adapter);
713d0394
SP		 2008 if (!wrb) {
2009 status = -EBUSY;
2010 goto err;
2011 }
b31c50a7 2012 req = embedded_payload(wrb);
6b7c5b94 2013
106df1e3 2014 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 2015 OPCODE_COMMON_GET_FLOW_CONTROL, sizeof(*req),
2016 wrb, NULL);
6b7c5b94 2017
b31c50a7 2018 status = be_mcc_notify_wait(adapter);
6b7c5b94
SP		 2019 if (!status) {
2020 struct be_cmd_resp_get_flow_control *resp =
2021 embedded_payload(wrb);
03d28ffe 2022
6b7c5b94
SP		 2023 *tx_fc = le16_to_cpu(resp->tx_flow_control);
2024 *rx_fc = le16_to_cpu(resp->rx_flow_control);
2025 }
2026
713d0394 2027err:
b31c50a7 2028 spin_unlock_bh(&adapter->mcc_lock);
6b7c5b94
SP		 2029 return status;
2030}
2031
b31c50a7 2032/* Uses mbox */
e97e3cda 2033int be_cmd_query_fw_cfg(struct be_adapter *adapter)
6b7c5b94 2034{
b31c50a7
SP		 2035 struct be_mcc_wrb *wrb;
2036 struct be_cmd_req_query_fw_cfg *req;
6b7c5b94
SP		 2037 int status;
2038
2984961c
IV		 2039 if (mutex_lock_interruptible(&adapter->mbox_lock))
2040 return -1;
6b7c5b94 2041
b31c50a7
SP		 2042 wrb = wrb_from_mbox(adapter);
2043 req = embedded_payload(wrb);
6b7c5b94 2044
106df1e3 2045 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 2046 OPCODE_COMMON_QUERY_FIRMWARE_CONFIG,
2047 sizeof(*req), wrb, NULL);
6b7c5b94 2048
b31c50a7 2049 status = be_mbox_notify_wait(adapter);
6b7c5b94
SP		 2050 if (!status) {
2051 struct be_cmd_resp_query_fw_cfg *resp = embedded_payload(wrb);
03d28ffe 2052
e97e3cda
KA		 2053 adapter->port_num = le32_to_cpu(resp->phys_port);
2054 adapter->function_mode = le32_to_cpu(resp->function_mode);
2055 adapter->function_caps = le32_to_cpu(resp->function_caps);
2056 adapter->asic_rev = le32_to_cpu(resp->asic_revision) & 0xFF;
acbafeb1
SP		 2057 dev_info(&adapter->pdev->dev,
2058 "FW config: function_mode=0x%x, function_caps=0x%x\n",
2059 adapter->function_mode, adapter->function_caps);
6b7c5b94
SP		 2060 }
2061
2984961c 2062 mutex_unlock(&adapter->mbox_lock);
6b7c5b94
SP		 2063 return status;
2064}
14074eab 2065
b31c50a7 2066/* Uses mbox */
14074eab 2067int be_cmd_reset_function(struct be_adapter *adapter)
2068{
b31c50a7
SP		 2069 struct be_mcc_wrb *wrb;
2070 struct be_cmd_req_hdr *req;
14074eab 2071 int status;
2072
bf99e50d 2073 if (lancer_chip(adapter)) {
9fa465c0
SP		 2074 iowrite32(SLI_PORT_CONTROL_IP_MASK,
2075 adapter->db + SLIPORT_CONTROL_OFFSET);
bf99e50d 2076 status = lancer_wait_ready(adapter);
9fa465c0 2077 if (status)
bf99e50d
PR		 2078 dev_err(&adapter->pdev->dev,
2079 "Adapter in non recoverable error\n");
bf99e50d
PR		 2080 return status;
2081 }
2082
2984961c
IV		 2083 if (mutex_lock_interruptible(&adapter->mbox_lock))
2084 return -1;
14074eab 2085
b31c50a7
SP		 2086 wrb = wrb_from_mbox(adapter);
2087 req = embedded_payload(wrb);
14074eab 2088
106df1e3 2089 be_wrb_cmd_hdr_prepare(req, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 2090 OPCODE_COMMON_FUNCTION_RESET, sizeof(*req), wrb,
2091 NULL);
14074eab 2092
b31c50a7 2093 status = be_mbox_notify_wait(adapter);
14074eab 2094
2984961c 2095 mutex_unlock(&adapter->mbox_lock);
14074eab 2096 return status;
2097}
84517482 2098
594ad54a 2099int be_cmd_rss_config(struct be_adapter *adapter, u8 *rsstable,
33cb0fa7 2100 u32 rss_hash_opts, u16 table_size, const u8 *rss_hkey)
3abcdeda
SP		 2101{
2102 struct be_mcc_wrb *wrb;
2103 struct be_cmd_req_rss_config *req;
3abcdeda
SP		 2104 int status;
2105
da1388d6
VV		 2106 if (!(be_if_cap_flags(adapter) & BE_IF_FLAGS_RSS))
2107 return 0;
2108
b51aa367 2109 spin_lock_bh(&adapter->mcc_lock);
3abcdeda 2110
b51aa367
KA		 2111 wrb = wrb_from_mccq(adapter);
2112 if (!wrb) {
2113 status = -EBUSY;
2114 goto err;
2115 }
3abcdeda
SP		 2116 req = embedded_payload(wrb);
2117
106df1e3 2118 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
a2cc4e0b 2119 OPCODE_ETH_RSS_CONFIG, sizeof(*req), wrb, NULL);
3abcdeda
SP		 2120
2121 req->if_id = cpu_to_le32(adapter->if_handle);
594ad54a
SR		 2122 req->enable_rss = cpu_to_le16(rss_hash_opts);
2123 req->cpu_table_size_log2 = cpu_to_le16(fls(table_size) - 1);
d3bd3a5e 2124
b51aa367 2125 if (!BEx_chip(adapter))
d3bd3a5e 2126 req->hdr.version = 1;
d3bd3a5e 2127
3abcdeda 2128 memcpy(req->cpu_table, rsstable, table_size);
e2557877 2129 memcpy(req->hash, rss_hkey, RSS_HASH_KEY_LEN);
3abcdeda
SP		 2130 be_dws_cpu_to_le(req->hash, sizeof(req->hash));
2131
b51aa367
KA		 2132 status = be_mcc_notify_wait(adapter);
2133err:
2134 spin_unlock_bh(&adapter->mcc_lock);
3abcdeda
SP		 2135 return status;
2136}
2137
fad9ab2c
SB		 2138/* Uses sync mcc */
2139int be_cmd_set_beacon_state(struct be_adapter *adapter, u8 port_num,
a2cc4e0b 2140 u8 bcn, u8 sts, u8 state)
fad9ab2c
SB		 2141{
2142 struct be_mcc_wrb *wrb;
2143 struct be_cmd_req_enable_disable_beacon *req;
2144 int status;
2145
2146 spin_lock_bh(&adapter->mcc_lock);
2147
2148 wrb = wrb_from_mccq(adapter);
713d0394
SP		 2149 if (!wrb) {
2150 status = -EBUSY;
2151 goto err;
2152 }
fad9ab2c
SB		 2153 req = embedded_payload(wrb);
2154
106df1e3 2155 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 2156 OPCODE_COMMON_ENABLE_DISABLE_BEACON,
2157 sizeof(*req), wrb, NULL);
fad9ab2c
SB		 2158
2159 req->port_num = port_num;
2160 req->beacon_state = state;
2161 req->beacon_duration = bcn;
2162 req->status_duration = sts;
2163
2164 status = be_mcc_notify_wait(adapter);
2165
713d0394 2166err:
fad9ab2c
SB		 2167 spin_unlock_bh(&adapter->mcc_lock);
2168 return status;
2169}
2170
2171/* Uses sync mcc */
2172int be_cmd_get_beacon_state(struct be_adapter *adapter, u8 port_num, u32 *state)
2173{
2174 struct be_mcc_wrb *wrb;
2175 struct be_cmd_req_get_beacon_state *req;
2176 int status;
2177
2178 spin_lock_bh(&adapter->mcc_lock);
2179
2180 wrb = wrb_from_mccq(adapter);
713d0394
SP		 2181 if (!wrb) {
2182 status = -EBUSY;
2183 goto err;
2184 }
fad9ab2c
SB		 2185 req = embedded_payload(wrb);
2186
106df1e3 2187 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 2188 OPCODE_COMMON_GET_BEACON_STATE, sizeof(*req),
2189 wrb, NULL);
fad9ab2c
SB		 2190
2191 req->port_num = port_num;
2192
2193 status = be_mcc_notify_wait(adapter);
2194 if (!status) {
2195 struct be_cmd_resp_get_beacon_state *resp =
2196 embedded_payload(wrb);
03d28ffe 2197
fad9ab2c
SB		 2198 *state = resp->beacon_state;
2199 }
2200
713d0394 2201err:
fad9ab2c
SB		 2202 spin_unlock_bh(&adapter->mcc_lock);
2203 return status;
2204}
2205
e36edd9d
ML		 2206/* Uses sync mcc */
2207int be_cmd_read_port_transceiver_data(struct be_adapter *adapter,
2208 u8 page_num, u8 *data)
2209{
2210 struct be_dma_mem cmd;
2211 struct be_mcc_wrb *wrb;
2212 struct be_cmd_req_port_type *req;
2213 int status;
2214
2215 if (page_num > TR_PAGE_A2)
2216 return -EINVAL;
2217
2218 cmd.size = sizeof(struct be_cmd_resp_port_type);
2219 cmd.va = pci_alloc_consistent(adapter->pdev, cmd.size, &cmd.dma);
2220 if (!cmd.va) {
2221 dev_err(&adapter->pdev->dev, "Memory allocation failed\n");
2222 return -ENOMEM;
2223 }
2224 memset(cmd.va, 0, cmd.size);
2225
2226 spin_lock_bh(&adapter->mcc_lock);
2227
2228 wrb = wrb_from_mccq(adapter);
2229 if (!wrb) {
2230 status = -EBUSY;
2231 goto err;
2232 }
2233 req = cmd.va;
2234
2235 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2236 OPCODE_COMMON_READ_TRANSRECV_DATA,
2237 cmd.size, wrb, &cmd);
2238
2239 req->port = cpu_to_le32(adapter->hba_port_num);
2240 req->page_num = cpu_to_le32(page_num);
2241 status = be_mcc_notify_wait(adapter);
2242 if (!status) {
2243 struct be_cmd_resp_port_type *resp = cmd.va;
2244
2245 memcpy(data, resp->page_data, PAGE_DATA_LEN);
2246 }
2247err:
2248 spin_unlock_bh(&adapter->mcc_lock);
2249 pci_free_consistent(adapter->pdev, cmd.size, cmd.va, cmd.dma);
2250 return status;
2251}
2252
485bf569 2253int lancer_cmd_write_object(struct be_adapter *adapter, struct be_dma_mem *cmd,
f67ef7ba
PR		 2254 u32 data_size, u32 data_offset,
2255 const char *obj_name, u32 *data_written,
2256 u8 *change_status, u8 *addn_status)
485bf569
SN		 2257{
2258 struct be_mcc_wrb *wrb;
2259 struct lancer_cmd_req_write_object *req;
2260 struct lancer_cmd_resp_write_object *resp;
2261 void *ctxt = NULL;
2262 int status;
2263
2264 spin_lock_bh(&adapter->mcc_lock);
2265 adapter->flash_status = 0;
2266
2267 wrb = wrb_from_mccq(adapter);
2268 if (!wrb) {
2269 status = -EBUSY;
2270 goto err_unlock;
2271 }
2272
2273 req = embedded_payload(wrb);
2274
106df1e3 2275 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 2276 OPCODE_COMMON_WRITE_OBJECT,
2277 sizeof(struct lancer_cmd_req_write_object), wrb,
2278 NULL);
485bf569
SN		 2279
2280 ctxt = &req->context;
2281 AMAP_SET_BITS(struct amap_lancer_write_obj_context,
a2cc4e0b 2282 write_length, ctxt, data_size);
485bf569
SN		 2283
2284 if (data_size == 0)
2285 AMAP_SET_BITS(struct amap_lancer_write_obj_context,
a2cc4e0b 2286 eof, ctxt, 1);
485bf569
SN		 2287 else
2288 AMAP_SET_BITS(struct amap_lancer_write_obj_context,
a2cc4e0b 2289 eof, ctxt, 0);
485bf569
SN		 2290
2291 be_dws_cpu_to_le(ctxt, sizeof(req->context));
2292 req->write_offset = cpu_to_le32(data_offset);
242eb470 2293 strlcpy(req->object_name, obj_name, sizeof(req->object_name));
485bf569
SN		 2294 req->descriptor_count = cpu_to_le32(1);
2295 req->buf_len = cpu_to_le32(data_size);
2296 req->addr_low = cpu_to_le32((cmd->dma +
a2cc4e0b
SP		 2297 sizeof(struct lancer_cmd_req_write_object))
2298 & 0xFFFFFFFF);
485bf569
SN		 2299 req->addr_high = cpu_to_le32(upper_32_bits(cmd->dma +
2300 sizeof(struct lancer_cmd_req_write_object)));
2301
2302 be_mcc_notify(adapter);
2303 spin_unlock_bh(&adapter->mcc_lock);
2304
5eeff635 2305 if (!wait_for_completion_timeout(&adapter->et_cmd_compl,
701962d0 2306 msecs_to_jiffies(60000)))
fd45160c 2307 status = -ETIMEDOUT;
485bf569
SN		 2308 else
2309 status = adapter->flash_status;
2310
2311 resp = embedded_payload(wrb);
f67ef7ba 2312 if (!status) {
485bf569 2313 *data_written = le32_to_cpu(resp->actual_write_len);
f67ef7ba
PR		 2314 *change_status = resp->change_status;
2315 } else {
485bf569 2316 *addn_status = resp->additional_status;
f67ef7ba 2317 }
485bf569
SN		 2318
2319 return status;
2320
2321err_unlock:
2322 spin_unlock_bh(&adapter->mcc_lock);
2323 return status;
2324}
2325
6809cee0
RN		 2326int be_cmd_query_cable_type(struct be_adapter *adapter)
2327{
2328 u8 page_data[PAGE_DATA_LEN];
2329 int status;
2330
2331 status = be_cmd_read_port_transceiver_data(adapter, TR_PAGE_A0,
2332 page_data);
2333 if (!status) {
2334 switch (adapter->phy.interface_type) {
2335 case PHY_TYPE_QSFP:
2336 adapter->phy.cable_type =
2337 page_data[QSFP_PLUS_CABLE_TYPE_OFFSET];
2338 break;
2339 case PHY_TYPE_SFP_PLUS_10GB:
2340 adapter->phy.cable_type =
2341 page_data[SFP_PLUS_CABLE_TYPE_OFFSET];
2342 break;
2343 default:
2344 adapter->phy.cable_type = 0;
2345 break;
2346 }
2347 }
2348 return status;
2349}
2350
21252377
VV		 2351int be_cmd_query_sfp_info(struct be_adapter *adapter)
2352{
2353 u8 page_data[PAGE_DATA_LEN];
2354 int status;
2355
2356 status = be_cmd_read_port_transceiver_data(adapter, TR_PAGE_A0,
2357 page_data);
2358 if (!status) {
2359 strlcpy(adapter->phy.vendor_name, page_data +
2360 SFP_VENDOR_NAME_OFFSET, SFP_VENDOR_NAME_LEN - 1);
2361 strlcpy(adapter->phy.vendor_pn,
2362 page_data + SFP_VENDOR_PN_OFFSET,
2363 SFP_VENDOR_NAME_LEN - 1);
2364 }
2365
2366 return status;
2367}
2368
f0613380
KA		 2369int lancer_cmd_delete_object(struct be_adapter *adapter, const char *obj_name)
2370{
2371 struct lancer_cmd_req_delete_object *req;
2372 struct be_mcc_wrb *wrb;
2373 int status;
2374
2375 spin_lock_bh(&adapter->mcc_lock);
2376
2377 wrb = wrb_from_mccq(adapter);
2378 if (!wrb) {
2379 status = -EBUSY;
2380 goto err;
2381 }
2382
2383 req = embedded_payload(wrb);
2384
2385 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2386 OPCODE_COMMON_DELETE_OBJECT,
2387 sizeof(*req), wrb, NULL);
2388
242eb470 2389 strlcpy(req->object_name, obj_name, sizeof(req->object_name));
f0613380
KA		 2390
2391 status = be_mcc_notify_wait(adapter);
2392err:
2393 spin_unlock_bh(&adapter->mcc_lock);
2394 return status;
2395}
2396
de49bd5a 2397int lancer_cmd_read_object(struct be_adapter *adapter, struct be_dma_mem *cmd,
a2cc4e0b
SP		 2398 u32 data_size, u32 data_offset, const char *obj_name,
2399 u32 *data_read, u32 *eof, u8 *addn_status)
de49bd5a
PR		 2400{
2401 struct be_mcc_wrb *wrb;
2402 struct lancer_cmd_req_read_object *req;
2403 struct lancer_cmd_resp_read_object *resp;
2404 int status;
2405
2406 spin_lock_bh(&adapter->mcc_lock);
2407
2408 wrb = wrb_from_mccq(adapter);
2409 if (!wrb) {
2410 status = -EBUSY;
2411 goto err_unlock;
2412 }
2413
2414 req = embedded_payload(wrb);
2415
2416 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 2417 OPCODE_COMMON_READ_OBJECT,
2418 sizeof(struct lancer_cmd_req_read_object), wrb,
2419 NULL);
de49bd5a
PR		 2420
2421 req->desired_read_len = cpu_to_le32(data_size);
2422 req->read_offset = cpu_to_le32(data_offset);
2423 strcpy(req->object_name, obj_name);
2424 req->descriptor_count = cpu_to_le32(1);
2425 req->buf_len = cpu_to_le32(data_size);
2426 req->addr_low = cpu_to_le32((cmd->dma & 0xFFFFFFFF));
2427 req->addr_high = cpu_to_le32(upper_32_bits(cmd->dma));
2428
2429 status = be_mcc_notify_wait(adapter);
2430
2431 resp = embedded_payload(wrb);
2432 if (!status) {
2433 *data_read = le32_to_cpu(resp->actual_read_len);
2434 *eof = le32_to_cpu(resp->eof);
2435 } else {
2436 *addn_status = resp->additional_status;
2437 }
2438
2439err_unlock:
2440 spin_unlock_bh(&adapter->mcc_lock);
2441 return status;
2442}
2443
84517482 2444int be_cmd_write_flashrom(struct be_adapter *adapter, struct be_dma_mem *cmd,
70a7b525
VV		 2445 u32 flash_type, u32 flash_opcode, u32 img_offset,
2446 u32 buf_size)
84517482 2447{
b31c50a7 2448 struct be_mcc_wrb *wrb;
3f0d4560 2449 struct be_cmd_write_flashrom *req;
84517482
AK		 2450 int status;
2451
b31c50a7 2452 spin_lock_bh(&adapter->mcc_lock);
dd131e76 2453 adapter->flash_status = 0;
b31c50a7
SP		 2454
2455 wrb = wrb_from_mccq(adapter);
713d0394
SP		 2456 if (!wrb) {
2457 status = -EBUSY;
2892d9c2 2458 goto err_unlock;
713d0394
SP		 2459 }
2460 req = cmd->va;
84517482 2461
106df1e3 2462 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 2463 OPCODE_COMMON_WRITE_FLASHROM, cmd->size, wrb,
2464 cmd);
84517482
AK		 2465
2466 req->params.op_type = cpu_to_le32(flash_type);
70a7b525
VV		 2467 if (flash_type == OPTYPE_OFFSET_SPECIFIED)
2468 req->params.offset = cpu_to_le32(img_offset);
2469
84517482
AK		 2470 req->params.op_code = cpu_to_le32(flash_opcode);
2471 req->params.data_buf_size = cpu_to_le32(buf_size);
2472
dd131e76
SB		 2473 be_mcc_notify(adapter);
2474 spin_unlock_bh(&adapter->mcc_lock);
2475
5eeff635
SR		 2476 if (!wait_for_completion_timeout(&adapter->et_cmd_compl,
2477 msecs_to_jiffies(40000)))
fd45160c 2478 status = -ETIMEDOUT;
dd131e76
SB		 2479 else
2480 status = adapter->flash_status;
84517482 2481
2892d9c2
DC		 2482 return status;
2483
2484err_unlock:
2485 spin_unlock_bh(&adapter->mcc_lock);
84517482
AK		 2486 return status;
2487}
fa9a6fed 2488
3f0d4560 2489int be_cmd_get_flash_crc(struct be_adapter *adapter, u8 *flashed_crc,
70a7b525 2490 u16 img_optype, u32 img_offset, u32 crc_offset)
fa9a6fed 2491{
be716446 2492 struct be_cmd_read_flash_crc *req;
70a7b525 2493 struct be_mcc_wrb *wrb;
fa9a6fed
SB		 2494 int status;
2495
2496 spin_lock_bh(&adapter->mcc_lock);
2497
2498 wrb = wrb_from_mccq(adapter);
713d0394
SP		 2499 if (!wrb) {
2500 status = -EBUSY;
2501 goto err;
2502 }
fa9a6fed
SB		 2503 req = embedded_payload(wrb);
2504
106df1e3 2505 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
be716446
PR		 2506 OPCODE_COMMON_READ_FLASHROM, sizeof(*req),
2507 wrb, NULL);
fa9a6fed 2508
70a7b525
VV		 2509 req->params.op_type = cpu_to_le32(img_optype);
2510 if (img_optype == OPTYPE_OFFSET_SPECIFIED)
2511 req->params.offset = cpu_to_le32(img_offset + crc_offset);
2512 else
2513 req->params.offset = cpu_to_le32(crc_offset);
2514
fa9a6fed 2515 req->params.op_code = cpu_to_le32(FLASHROM_OPER_REPORT);
8b93b710 2516 req->params.data_buf_size = cpu_to_le32(0x4);
fa9a6fed
SB		 2517
2518 status = be_mcc_notify_wait(adapter);
2519 if (!status)
be716446 2520 memcpy(flashed_crc, req->crc, 4);
fa9a6fed 2521
713d0394 2522err:
fa9a6fed
SB		 2523 spin_unlock_bh(&adapter->mcc_lock);
2524 return status;
2525}
71d8d1b5 2526
c196b02c 2527int be_cmd_enable_magic_wol(struct be_adapter *adapter, u8 *mac,
a2cc4e0b 2528 struct be_dma_mem *nonemb_cmd)
71d8d1b5
AK		 2529{
2530 struct be_mcc_wrb *wrb;
2531 struct be_cmd_req_acpi_wol_magic_config *req;
71d8d1b5
AK		 2532 int status;
2533
2534 spin_lock_bh(&adapter->mcc_lock);
2535
2536 wrb = wrb_from_mccq(adapter);
2537 if (!wrb) {
2538 status = -EBUSY;
2539 goto err;
2540 }
2541 req = nonemb_cmd->va;
71d8d1b5 2542
106df1e3 2543 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
a2cc4e0b
SP		 2544 OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG, sizeof(*req),
2545 wrb, nonemb_cmd);
71d8d1b5
AK		 2546 memcpy(req->magic_mac, mac, ETH_ALEN);
2547
71d8d1b5
AK		 2548 status = be_mcc_notify_wait(adapter);
2549
2550err:
2551 spin_unlock_bh(&adapter->mcc_lock);
2552 return status;
2553}
ff33a6e2 2554
fced9999
SB		 2555int be_cmd_set_loopback(struct be_adapter *adapter, u8 port_num,
2556 u8 loopback_type, u8 enable)
2557{
2558 struct be_mcc_wrb *wrb;
2559 struct be_cmd_req_set_lmode *req;
2560 int status;
2561
2562 spin_lock_bh(&adapter->mcc_lock);
2563
2564 wrb = wrb_from_mccq(adapter);
2565 if (!wrb) {
2566 status = -EBUSY;
2567 goto err;
2568 }
2569
2570 req = embedded_payload(wrb);
2571
106df1e3 2572 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
a2cc4e0b
SP		 2573 OPCODE_LOWLEVEL_SET_LOOPBACK_MODE, sizeof(*req),
2574 wrb, NULL);
fced9999
SB		 2575
2576 req->src_port = port_num;
2577 req->dest_port = port_num;
2578 req->loopback_type = loopback_type;
2579 req->loopback_state = enable;
2580
2581 status = be_mcc_notify_wait(adapter);
2582err:
2583 spin_unlock_bh(&adapter->mcc_lock);
2584 return status;
2585}
2586
ff33a6e2 2587int be_cmd_loopback_test(struct be_adapter *adapter, u32 port_num,
a2cc4e0b
SP		 2588 u32 loopback_type, u32 pkt_size, u32 num_pkts,
2589 u64 pattern)
ff33a6e2
S		 2590{
2591 struct be_mcc_wrb *wrb;
2592 struct be_cmd_req_loopback_test *req;
5eeff635 2593 struct be_cmd_resp_loopback_test *resp;
ff33a6e2
S		 2594 int status;
2595
2596 spin_lock_bh(&adapter->mcc_lock);
2597
2598 wrb = wrb_from_mccq(adapter);
2599 if (!wrb) {
2600 status = -EBUSY;
2601 goto err;
2602 }
2603
2604 req = embedded_payload(wrb);
2605
106df1e3 2606 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
a2cc4e0b
SP		 2607 OPCODE_LOWLEVEL_LOOPBACK_TEST, sizeof(*req), wrb,
2608 NULL);
ff33a6e2 2609
5eeff635 2610 req->hdr.timeout = cpu_to_le32(15);
ff33a6e2
S		 2611 req->pattern = cpu_to_le64(pattern);
2612 req->src_port = cpu_to_le32(port_num);
2613 req->dest_port = cpu_to_le32(port_num);
2614 req->pkt_size = cpu_to_le32(pkt_size);
2615 req->num_pkts = cpu_to_le32(num_pkts);
2616 req->loopback_type = cpu_to_le32(loopback_type);
2617
5eeff635
SR		 2618 be_mcc_notify(adapter);
2619
2620 spin_unlock_bh(&adapter->mcc_lock);
ff33a6e2 2621
5eeff635
SR		 2622 wait_for_completion(&adapter->et_cmd_compl);
2623 resp = embedded_payload(wrb);
2624 status = le32_to_cpu(resp->status);
2625
2626 return status;
ff33a6e2
S		 2627err:
2628 spin_unlock_bh(&adapter->mcc_lock);
2629 return status;
2630}
2631
2632int be_cmd_ddr_dma_test(struct be_adapter *adapter, u64 pattern,
a2cc4e0b 2633 u32 byte_cnt, struct be_dma_mem *cmd)
ff33a6e2
S		 2634{
2635 struct be_mcc_wrb *wrb;
2636 struct be_cmd_req_ddrdma_test *req;
ff33a6e2
S		 2637 int status;
2638 int i, j = 0;
2639
2640 spin_lock_bh(&adapter->mcc_lock);
2641
2642 wrb = wrb_from_mccq(adapter);
2643 if (!wrb) {
2644 status = -EBUSY;
2645 goto err;
2646 }
2647 req = cmd->va;
106df1e3 2648 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
a2cc4e0b
SP		 2649 OPCODE_LOWLEVEL_HOST_DDR_DMA, cmd->size, wrb,
2650 cmd);
ff33a6e2
S		 2651
2652 req->pattern = cpu_to_le64(pattern);
2653 req->byte_count = cpu_to_le32(byte_cnt);
2654 for (i = 0; i < byte_cnt; i++) {
2655 req->snd_buff[i] = (u8)(pattern >> (j*8));
2656 j++;
2657 if (j > 7)
2658 j = 0;
2659 }
2660
2661 status = be_mcc_notify_wait(adapter);
2662
2663 if (!status) {
2664 struct be_cmd_resp_ddrdma_test *resp;
03d28ffe 2665
ff33a6e2
S		 2666 resp = cmd->va;
2667 if ((memcmp(resp->rcv_buff, req->snd_buff, byte_cnt) != 0) ||
cd3307aa 2668 resp->snd_err) {
ff33a6e2
S		 2669 status = -1;
2670 }
2671 }
2672
2673err:
2674 spin_unlock_bh(&adapter->mcc_lock);
2675 return status;
2676}
368c0ca2 2677
c196b02c 2678int be_cmd_get_seeprom_data(struct be_adapter *adapter,
a2cc4e0b 2679 struct be_dma_mem *nonemb_cmd)
368c0ca2
SB		 2680{
2681 struct be_mcc_wrb *wrb;
2682 struct be_cmd_req_seeprom_read *req;
368c0ca2
SB		 2683 int status;
2684
2685 spin_lock_bh(&adapter->mcc_lock);
2686
2687 wrb = wrb_from_mccq(adapter);
e45ff01d
AK		 2688 if (!wrb) {
2689 status = -EBUSY;
2690 goto err;
2691 }
368c0ca2 2692 req = nonemb_cmd->va;
368c0ca2 2693
106df1e3 2694 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 2695 OPCODE_COMMON_SEEPROM_READ, sizeof(*req), wrb,
2696 nonemb_cmd);
368c0ca2
SB		 2697
2698 status = be_mcc_notify_wait(adapter);
2699
e45ff01d 2700err:
368c0ca2
SB		 2701 spin_unlock_bh(&adapter->mcc_lock);
2702 return status;
2703}
ee3cb629 2704
42f11cf2 2705int be_cmd_get_phy_info(struct be_adapter *adapter)
ee3cb629
AK		 2706{
2707 struct be_mcc_wrb *wrb;
2708 struct be_cmd_req_get_phy_info *req;
306f1348 2709 struct be_dma_mem cmd;
ee3cb629
AK		 2710 int status;
2711
f25b119c
PR		 2712 if (!be_cmd_allowed(adapter, OPCODE_COMMON_GET_PHY_DETAILS,
2713 CMD_SUBSYSTEM_COMMON))
2714 return -EPERM;
2715
ee3cb629
AK		 2716 spin_lock_bh(&adapter->mcc_lock);
2717
2718 wrb = wrb_from_mccq(adapter);
2719 if (!wrb) {
2720 status = -EBUSY;
2721 goto err;
2722 }
306f1348 2723 cmd.size = sizeof(struct be_cmd_req_get_phy_info);
a2cc4e0b 2724 cmd.va = pci_alloc_consistent(adapter->pdev, cmd.size, &cmd.dma);
306f1348
SP		 2725 if (!cmd.va) {
2726 dev_err(&adapter->pdev->dev, "Memory alloc failure\n");
2727 status = -ENOMEM;
2728 goto err;
2729 }
ee3cb629 2730
306f1348 2731 req = cmd.va;
ee3cb629 2732
106df1e3 2733 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 2734 OPCODE_COMMON_GET_PHY_DETAILS, sizeof(*req),
2735 wrb, &cmd);
ee3cb629
AK		 2736
2737 status = be_mcc_notify_wait(adapter);
306f1348
SP		 2738 if (!status) {
2739 struct be_phy_info *resp_phy_info =
2740 cmd.va + sizeof(struct be_cmd_req_hdr);
03d28ffe 2741
42f11cf2
AK		 2742 adapter->phy.phy_type = le16_to_cpu(resp_phy_info->phy_type);
2743 adapter->phy.interface_type =
306f1348 2744 le16_to_cpu(resp_phy_info->interface_type);
42f11cf2
AK		 2745 adapter->phy.auto_speeds_supported =
2746 le16_to_cpu(resp_phy_info->auto_speeds_supported);
2747 adapter->phy.fixed_speeds_supported =
2748 le16_to_cpu(resp_phy_info->fixed_speeds_supported);
2749 adapter->phy.misc_params =
2750 le32_to_cpu(resp_phy_info->misc_params);
68cb7e47
VV		 2751
2752 if (BE2_chip(adapter)) {
2753 adapter->phy.fixed_speeds_supported =
2754 BE_SUPPORTED_SPEED_10GBPS |
2755 BE_SUPPORTED_SPEED_1GBPS;
2756 }
306f1348 2757 }
a2cc4e0b 2758 pci_free_consistent(adapter->pdev, cmd.size, cmd.va, cmd.dma);
ee3cb629
AK		 2759err:
2760 spin_unlock_bh(&adapter->mcc_lock);
2761 return status;
2762}
e1d18735 2763
bc0ee163 2764static int be_cmd_set_qos(struct be_adapter *adapter, u32 bps, u32 domain)
e1d18735
AK		 2765{
2766 struct be_mcc_wrb *wrb;
2767 struct be_cmd_req_set_qos *req;
2768 int status;
2769
2770 spin_lock_bh(&adapter->mcc_lock);
2771
2772 wrb = wrb_from_mccq(adapter);
2773 if (!wrb) {
2774 status = -EBUSY;
2775 goto err;
2776 }
2777
2778 req = embedded_payload(wrb);
2779
106df1e3 2780 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b 2781 OPCODE_COMMON_SET_QOS, sizeof(*req), wrb, NULL);
e1d18735
AK		 2782
2783 req->hdr.domain = domain;
6bff57a7
AK		 2784 req->valid_bits = cpu_to_le32(BE_QOS_BITS_NIC);
2785 req->max_bps_nic = cpu_to_le32(bps);
e1d18735
AK		 2786
2787 status = be_mcc_notify_wait(adapter);
2788
2789err:
2790 spin_unlock_bh(&adapter->mcc_lock);
2791 return status;
2792}
9e1453c5
AK		 2793
2794int be_cmd_get_cntl_attributes(struct be_adapter *adapter)
2795{
2796 struct be_mcc_wrb *wrb;
2797 struct be_cmd_req_cntl_attribs *req;
2798 struct be_cmd_resp_cntl_attribs *resp;
9e1453c5
AK		 2799 int status;
2800 int payload_len = max(sizeof(*req), sizeof(*resp));
2801 struct mgmt_controller_attrib *attribs;
2802 struct be_dma_mem attribs_cmd;
2803
d98ef50f
SR		 2804 if (mutex_lock_interruptible(&adapter->mbox_lock))
2805 return -1;
2806
9e1453c5
AK		 2807 memset(&attribs_cmd, 0, sizeof(struct be_dma_mem));
2808 attribs_cmd.size = sizeof(struct be_cmd_resp_cntl_attribs);
2809 attribs_cmd.va = pci_alloc_consistent(adapter->pdev, attribs_cmd.size,
a2cc4e0b 2810 &attribs_cmd.dma);
9e1453c5 2811 if (!attribs_cmd.va) {
a2cc4e0b 2812 dev_err(&adapter->pdev->dev, "Memory allocation failure\n");
d98ef50f
SR		 2813 status = -ENOMEM;
2814 goto err;
9e1453c5
AK		 2815 }
2816
9e1453c5
AK		 2817 wrb = wrb_from_mbox(adapter);
2818 if (!wrb) {
2819 status = -EBUSY;
2820 goto err;
2821 }
2822 req = attribs_cmd.va;
9e1453c5 2823
106df1e3 2824 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 2825 OPCODE_COMMON_GET_CNTL_ATTRIBUTES, payload_len,
2826 wrb, &attribs_cmd);
9e1453c5
AK		 2827
2828 status = be_mbox_notify_wait(adapter);
2829 if (!status) {
43d620c8 2830 attribs = attribs_cmd.va + sizeof(struct be_cmd_resp_hdr);
9e1453c5
AK		 2831 adapter->hba_port_num = attribs->hba_attribs.phy_port;
2832 }
2833
2834err:
2835 mutex_unlock(&adapter->mbox_lock);
d98ef50f
SR		 2836 if (attribs_cmd.va)
2837 pci_free_consistent(adapter->pdev, attribs_cmd.size,
2838 attribs_cmd.va, attribs_cmd.dma);
9e1453c5
AK		 2839 return status;
2840}
2e588f84
SP		 2841
2842/* Uses mbox */
2dc1deb6 2843int be_cmd_req_native_mode(struct be_adapter *adapter)
2e588f84
SP		 2844{
2845 struct be_mcc_wrb *wrb;
2846 struct be_cmd_req_set_func_cap *req;
2847 int status;
2848
2849 if (mutex_lock_interruptible(&adapter->mbox_lock))
2850 return -1;
2851
2852 wrb = wrb_from_mbox(adapter);
2853 if (!wrb) {
2854 status = -EBUSY;
2855 goto err;
2856 }
2857
2858 req = embedded_payload(wrb);
2859
106df1e3 2860 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 2861 OPCODE_COMMON_SET_DRIVER_FUNCTION_CAP,
2862 sizeof(*req), wrb, NULL);
2e588f84
SP		 2863
2864 req->valid_cap_flags = cpu_to_le32(CAPABILITY_SW_TIMESTAMPS |
2865 CAPABILITY_BE3_NATIVE_ERX_API);
2866 req->cap_flags = cpu_to_le32(CAPABILITY_BE3_NATIVE_ERX_API);
2867
2868 status = be_mbox_notify_wait(adapter);
2869 if (!status) {
2870 struct be_cmd_resp_set_func_cap *resp = embedded_payload(wrb);
03d28ffe 2871
2e588f84
SP		 2872 adapter->be3_native = le32_to_cpu(resp->cap_flags) &
2873 CAPABILITY_BE3_NATIVE_ERX_API;
d379142b
SP		 2874 if (!adapter->be3_native)
2875 dev_warn(&adapter->pdev->dev,
2876 "adapter not in advanced mode\n");
2e588f84
SP		 2877 }
2878err:
2879 mutex_unlock(&adapter->mbox_lock);
2880 return status;
2881}
590c391d 2882
f25b119c
PR		 2883/* Get privilege(s) for a function */
2884int be_cmd_get_fn_privileges(struct be_adapter *adapter, u32 *privilege,
2885 u32 domain)
2886{
2887 struct be_mcc_wrb *wrb;
2888 struct be_cmd_req_get_fn_privileges *req;
2889 int status;
2890
2891 spin_lock_bh(&adapter->mcc_lock);
2892
2893 wrb = wrb_from_mccq(adapter);
2894 if (!wrb) {
2895 status = -EBUSY;
2896 goto err;
2897 }
2898
2899 req = embedded_payload(wrb);
2900
2901 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2902 OPCODE_COMMON_GET_FN_PRIVILEGES, sizeof(*req),
2903 wrb, NULL);
2904
2905 req->hdr.domain = domain;
2906
2907 status = be_mcc_notify_wait(adapter);
2908 if (!status) {
2909 struct be_cmd_resp_get_fn_privileges *resp =
2910 embedded_payload(wrb);
03d28ffe 2911
f25b119c 2912 *privilege = le32_to_cpu(resp->privilege_mask);
02308d74
SR		 2913
2914 /* In UMC mode FW does not return right privileges.
2915 * Override with correct privilege equivalent to PF.
2916 */
2917 if (BEx_chip(adapter) && be_is_mc(adapter) &&
2918 be_physfn(adapter))
2919 *privilege = MAX_PRIVILEGES;
f25b119c
PR		 2920 }
2921
2922err:
2923 spin_unlock_bh(&adapter->mcc_lock);
2924 return status;
2925}
2926
04a06028
SP		 2927/* Set privilege(s) for a function */
2928int be_cmd_set_fn_privileges(struct be_adapter *adapter, u32 privileges,
2929 u32 domain)
2930{
2931 struct be_mcc_wrb *wrb;
2932 struct be_cmd_req_set_fn_privileges *req;
2933 int status;
2934
2935 spin_lock_bh(&adapter->mcc_lock);
2936
2937 wrb = wrb_from_mccq(adapter);
2938 if (!wrb) {
2939 status = -EBUSY;
2940 goto err;
2941 }
2942
2943 req = embedded_payload(wrb);
2944 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2945 OPCODE_COMMON_SET_FN_PRIVILEGES, sizeof(*req),
2946 wrb, NULL);
2947 req->hdr.domain = domain;
2948 if (lancer_chip(adapter))
2949 req->privileges_lancer = cpu_to_le32(privileges);
2950 else
2951 req->privileges = cpu_to_le32(privileges);
2952
2953 status = be_mcc_notify_wait(adapter);
2954err:
2955 spin_unlock_bh(&adapter->mcc_lock);
2956 return status;
2957}
2958
5a712c13
SP		 2959/* pmac_id_valid: true => pmac_id is supplied and MAC address is requested.
2960 * pmac_id_valid: false => pmac_id or MAC address is requested.
2961 * If pmac_id is returned, pmac_id_valid is returned as true
2962 */
1578e777 2963int be_cmd_get_mac_from_list(struct be_adapter *adapter, u8 *mac,
b188f090
SR		 2964 bool *pmac_id_valid, u32 *pmac_id, u32 if_handle,
2965 u8 domain)
590c391d
PR		 2966{
2967 struct be_mcc_wrb *wrb;
2968 struct be_cmd_req_get_mac_list *req;
2969 int status;
2970 int mac_count;
e5e1ee89
PR		 2971 struct be_dma_mem get_mac_list_cmd;
2972 int i;
2973
2974 memset(&get_mac_list_cmd, 0, sizeof(struct be_dma_mem));
2975 get_mac_list_cmd.size = sizeof(struct be_cmd_resp_get_mac_list);
2976 get_mac_list_cmd.va = pci_alloc_consistent(adapter->pdev,
a2cc4e0b
SP		 2977 get_mac_list_cmd.size,
2978 &get_mac_list_cmd.dma);
e5e1ee89
PR		 2979
2980 if (!get_mac_list_cmd.va) {
2981 dev_err(&adapter->pdev->dev,
a2cc4e0b 2982 "Memory allocation failure during GET_MAC_LIST\n");
e5e1ee89
PR		 2983 return -ENOMEM;
2984 }
590c391d
PR		 2985
2986 spin_lock_bh(&adapter->mcc_lock);
2987
2988 wrb = wrb_from_mccq(adapter);
2989 if (!wrb) {
2990 status = -EBUSY;
e5e1ee89 2991 goto out;
590c391d 2992 }
e5e1ee89
PR		 2993
2994 req = get_mac_list_cmd.va;
590c391d
PR		 2995
2996 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
bf591f51
SP		 2997 OPCODE_COMMON_GET_MAC_LIST,
2998 get_mac_list_cmd.size, wrb, &get_mac_list_cmd);
590c391d 2999 req->hdr.domain = domain;
e5e1ee89 3000 req->mac_type = MAC_ADDRESS_TYPE_NETWORK;
5a712c13
SP		 3001 if (*pmac_id_valid) {
3002 req->mac_id = cpu_to_le32(*pmac_id);
b188f090 3003 req->iface_id = cpu_to_le16(if_handle);
5a712c13
SP		 3004 req->perm_override = 0;
3005 } else {
3006 req->perm_override = 1;
3007 }
590c391d
PR		 3008
3009 status = be_mcc_notify_wait(adapter);
3010 if (!status) {
3011 struct be_cmd_resp_get_mac_list *resp =
e5e1ee89 3012 get_mac_list_cmd.va;
5a712c13
SP		 3013
3014 if (*pmac_id_valid) {
3015 memcpy(mac, resp->macid_macaddr.mac_addr_id.macaddr,
3016 ETH_ALEN);
3017 goto out;
3018 }
3019
e5e1ee89
PR		 3020 mac_count = resp->true_mac_count + resp->pseudo_mac_count;
3021 /* Mac list returned could contain one or more active mac_ids
dbedd44e 3022 * or one or more true or pseudo permanent mac addresses.
1578e777
PR		 3023 * If an active mac_id is present, return first active mac_id
3024 * found.
e5e1ee89 3025 */
590c391d 3026 for (i = 0; i < mac_count; i++) {
e5e1ee89
PR		 3027 struct get_list_macaddr *mac_entry;
3028 u16 mac_addr_size;
3029 u32 mac_id;
3030
3031 mac_entry = &resp->macaddr_list[i];
3032 mac_addr_size = le16_to_cpu(mac_entry->mac_addr_size);
3033 /* mac_id is a 32 bit value and mac_addr size
3034 * is 6 bytes
3035 */
3036 if (mac_addr_size == sizeof(u32)) {
5a712c13 3037 *pmac_id_valid = true;
e5e1ee89
PR		 3038 mac_id = mac_entry->mac_addr_id.s_mac_id.mac_id;
3039 *pmac_id = le32_to_cpu(mac_id);
3040 goto out;
590c391d 3041 }
590c391d 3042 }
1578e777 3043 /* If no active mac_id found, return first mac addr */
5a712c13 3044 *pmac_id_valid = false;
e5e1ee89 3045 memcpy(mac, resp->macaddr_list[0].mac_addr_id.macaddr,
a2cc4e0b 3046 ETH_ALEN);
590c391d
PR		 3047 }
3048
e5e1ee89 3049out:
590c391d 3050 spin_unlock_bh(&adapter->mcc_lock);
e5e1ee89 3051 pci_free_consistent(adapter->pdev, get_mac_list_cmd.size,
a2cc4e0b 3052 get_mac_list_cmd.va, get_mac_list_cmd.dma);
590c391d
PR		 3053 return status;
3054}
3055
a2cc4e0b
SP		 3056int be_cmd_get_active_mac(struct be_adapter *adapter, u32 curr_pmac_id,
3057 u8 *mac, u32 if_handle, bool active, u32 domain)
5a712c13 3058{
b188f090
SR		 3059 if (!active)
3060 be_cmd_get_mac_from_list(adapter, mac, &active, &curr_pmac_id,
3061 if_handle, domain);
3175d8c2 3062 if (BEx_chip(adapter))
5a712c13 3063 return be_cmd_mac_addr_query(adapter, mac, false,
b188f090 3064 if_handle, curr_pmac_id);
3175d8c2
SP		 3065 else
3066 /* Fetch the MAC address using pmac_id */
3067 return be_cmd_get_mac_from_list(adapter, mac, &active,
b188f090
SR		 3068 &curr_pmac_id,
3069 if_handle, domain);
5a712c13
SP		 3070}
3071
95046b92
SP		 3072int be_cmd_get_perm_mac(struct be_adapter *adapter, u8 *mac)
3073{
3074 int status;
3075 bool pmac_valid = false;
3076
c7bf7169 3077 eth_zero_addr(mac);
95046b92 3078
3175d8c2
SP		 3079 if (BEx_chip(adapter)) {
3080 if (be_physfn(adapter))
3081 status = be_cmd_mac_addr_query(adapter, mac, true, 0,
3082 0);
3083 else
3084 status = be_cmd_mac_addr_query(adapter, mac, false,
3085 adapter->if_handle, 0);
3086 } else {
95046b92 3087 status = be_cmd_get_mac_from_list(adapter, mac, &pmac_valid,
b188f090 3088 NULL, adapter->if_handle, 0);
3175d8c2
SP		 3089 }
3090
95046b92
SP		 3091 return status;
3092}
3093
590c391d
PR		 3094/* Uses synchronous MCCQ */
3095int be_cmd_set_mac_list(struct be_adapter *adapter, u8 *mac_array,
3096 u8 mac_count, u32 domain)
3097{
3098 struct be_mcc_wrb *wrb;
3099 struct be_cmd_req_set_mac_list *req;
3100 int status;
3101 struct be_dma_mem cmd;
3102
3103 memset(&cmd, 0, sizeof(struct be_dma_mem));
3104 cmd.size = sizeof(struct be_cmd_req_set_mac_list);
3105 cmd.va = dma_alloc_coherent(&adapter->pdev->dev, cmd.size,
a2cc4e0b 3106 &cmd.dma, GFP_KERNEL);
d0320f75 3107 if (!cmd.va)
590c391d 3108 return -ENOMEM;
590c391d
PR		 3109
3110 spin_lock_bh(&adapter->mcc_lock);
3111
3112 wrb = wrb_from_mccq(adapter);
3113 if (!wrb) {
3114 status = -EBUSY;
3115 goto err;
3116 }
3117
3118 req = cmd.va;
3119 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 3120 OPCODE_COMMON_SET_MAC_LIST, sizeof(*req),
3121 wrb, &cmd);
590c391d
PR		 3122
3123 req->hdr.domain = domain;
3124 req->mac_count = mac_count;
3125 if (mac_count)
3126 memcpy(req->mac, mac_array, ETH_ALEN*mac_count);
3127
3128 status = be_mcc_notify_wait(adapter);
3129
3130err:
a2cc4e0b 3131 dma_free_coherent(&adapter->pdev->dev, cmd.size, cmd.va, cmd.dma);
590c391d
PR		 3132 spin_unlock_bh(&adapter->mcc_lock);
3133 return status;
3134}
4762f6ce 3135
3175d8c2
SP		 3136/* Wrapper to delete any active MACs and provision the new mac.
3137 * Changes to MAC_LIST are allowed iff none of the MAC addresses in the
3138 * current list are active.
3139 */
3140int be_cmd_set_mac(struct be_adapter *adapter, u8 *mac, int if_id, u32 dom)
3141{
3142 bool active_mac = false;
3143 u8 old_mac[ETH_ALEN];
3144 u32 pmac_id;
3145 int status;
3146
3147 status = be_cmd_get_mac_from_list(adapter, old_mac, &active_mac,
b188f090
SR		 3148 &pmac_id, if_id, dom);
3149
3175d8c2
SP		 3150 if (!status && active_mac)
3151 be_cmd_pmac_del(adapter, if_id, pmac_id, dom);
3152
3153 return be_cmd_set_mac_list(adapter, mac, mac ? 1 : 0, dom);
3154}
3155
f1f3ee1b 3156int be_cmd_set_hsw_config(struct be_adapter *adapter, u16 pvid,
e7bcbd7b 3157 u32 domain, u16 intf_id, u16 hsw_mode, u8 spoofchk)
f1f3ee1b
AK		 3158{
3159 struct be_mcc_wrb *wrb;
3160 struct be_cmd_req_set_hsw_config *req;
3161 void *ctxt;
3162 int status;
3163
3164 spin_lock_bh(&adapter->mcc_lock);
3165
3166 wrb = wrb_from_mccq(adapter);
3167 if (!wrb) {
3168 status = -EBUSY;
3169 goto err;
3170 }
3171
3172 req = embedded_payload(wrb);
3173 ctxt = &req->context;
3174
3175 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 3176 OPCODE_COMMON_SET_HSW_CONFIG, sizeof(*req), wrb,
3177 NULL);
f1f3ee1b
AK		 3178
3179 req->hdr.domain = domain;
3180 AMAP_SET_BITS(struct amap_set_hsw_context, interface_id, ctxt, intf_id);
3181 if (pvid) {
3182 AMAP_SET_BITS(struct amap_set_hsw_context, pvid_valid, ctxt, 1);
3183 AMAP_SET_BITS(struct amap_set_hsw_context, pvid, ctxt, pvid);
3184 }
a77dcb8c
AK		 3185 if (!BEx_chip(adapter) && hsw_mode) {
3186 AMAP_SET_BITS(struct amap_set_hsw_context, interface_id,
3187 ctxt, adapter->hba_port_num);
3188 AMAP_SET_BITS(struct amap_set_hsw_context, pport, ctxt, 1);
3189 AMAP_SET_BITS(struct amap_set_hsw_context, port_fwd_type,
3190 ctxt, hsw_mode);
3191 }
f1f3ee1b 3192
e7bcbd7b
KA		 3193 /* Enable/disable both mac and vlan spoof checking */
3194 if (!BEx_chip(adapter) && spoofchk) {
3195 AMAP_SET_BITS(struct amap_set_hsw_context, mac_spoofchk,
3196 ctxt, spoofchk);
3197 AMAP_SET_BITS(struct amap_set_hsw_context, vlan_spoofchk,
3198 ctxt, spoofchk);
3199 }
3200
f1f3ee1b
AK		 3201 be_dws_cpu_to_le(req->context, sizeof(req->context));
3202 status = be_mcc_notify_wait(adapter);
3203
3204err:
3205 spin_unlock_bh(&adapter->mcc_lock);
3206 return status;
3207}
3208
3209/* Get Hyper switch config */
3210int be_cmd_get_hsw_config(struct be_adapter *adapter, u16 *pvid,
e7bcbd7b 3211 u32 domain, u16 intf_id, u8 *mode, bool *spoofchk)
f1f3ee1b
AK		 3212{
3213 struct be_mcc_wrb *wrb;
3214 struct be_cmd_req_get_hsw_config *req;
3215 void *ctxt;
3216 int status;
3217 u16 vid;
3218
3219 spin_lock_bh(&adapter->mcc_lock);
3220
3221 wrb = wrb_from_mccq(adapter);
3222 if (!wrb) {
3223 status = -EBUSY;
3224 goto err;
3225 }
3226
3227 req = embedded_payload(wrb);
3228 ctxt = &req->context;
3229
3230 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 3231 OPCODE_COMMON_GET_HSW_CONFIG, sizeof(*req), wrb,
3232 NULL);
f1f3ee1b
AK		 3233
3234 req->hdr.domain = domain;
a77dcb8c
AK		 3235 AMAP_SET_BITS(struct amap_get_hsw_req_context, interface_id,
3236 ctxt, intf_id);
f1f3ee1b 3237 AMAP_SET_BITS(struct amap_get_hsw_req_context, pvid_valid, ctxt, 1);
a77dcb8c 3238
2c07c1d7 3239 if (!BEx_chip(adapter) && mode) {
a77dcb8c
AK		 3240 AMAP_SET_BITS(struct amap_get_hsw_req_context, interface_id,
3241 ctxt, adapter->hba_port_num);
3242 AMAP_SET_BITS(struct amap_get_hsw_req_context, pport, ctxt, 1);
3243 }
f1f3ee1b
AK		 3244 be_dws_cpu_to_le(req->context, sizeof(req->context));
3245
3246 status = be_mcc_notify_wait(adapter);
3247 if (!status) {
3248 struct be_cmd_resp_get_hsw_config *resp =
3249 embedded_payload(wrb);
03d28ffe 3250
a2cc4e0b 3251 be_dws_le_to_cpu(&resp->context, sizeof(resp->context));
f1f3ee1b 3252 vid = AMAP_GET_BITS(struct amap_get_hsw_resp_context,
a2cc4e0b 3253 pvid, &resp->context);
a77dcb8c
AK		 3254 if (pvid)
3255 *pvid = le16_to_cpu(vid);
3256 if (mode)
3257 *mode = AMAP_GET_BITS(struct amap_get_hsw_resp_context,
3258 port_fwd_type, &resp->context);
e7bcbd7b
KA		 3259 if (spoofchk)
3260 *spoofchk =
3261 AMAP_GET_BITS(struct amap_get_hsw_resp_context,
3262 spoofchk, &resp->context);
f1f3ee1b
AK		 3263 }
3264
3265err:
3266 spin_unlock_bh(&adapter->mcc_lock);
3267 return status;
3268}
3269
f7062ee5
SP		 3270static bool be_is_wol_excluded(struct be_adapter *adapter)
3271{
3272 struct pci_dev *pdev = adapter->pdev;
3273
18c57c74 3274 if (be_virtfn(adapter))
f7062ee5
SP		 3275 return true;
3276
3277 switch (pdev->subsystem_device) {
3278 case OC_SUBSYS_DEVICE_ID1:
3279 case OC_SUBSYS_DEVICE_ID2:
3280 case OC_SUBSYS_DEVICE_ID3:
3281 case OC_SUBSYS_DEVICE_ID4:
3282 return true;
3283 default:
3284 return false;
3285 }
3286}
3287
4762f6ce
AK		 3288int be_cmd_get_acpi_wol_cap(struct be_adapter *adapter)
3289{
3290 struct be_mcc_wrb *wrb;
3291 struct be_cmd_req_acpi_wol_magic_config_v1 *req;
76a9e08e 3292 int status = 0;
4762f6ce
AK		 3293 struct be_dma_mem cmd;
3294
f25b119c
PR		 3295 if (!be_cmd_allowed(adapter, OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG,
3296 CMD_SUBSYSTEM_ETH))
3297 return -EPERM;
3298
76a9e08e
SR		 3299 if (be_is_wol_excluded(adapter))
3300 return status;
3301
d98ef50f
SR		 3302 if (mutex_lock_interruptible(&adapter->mbox_lock))
3303 return -1;
3304
4762f6ce
AK		 3305 memset(&cmd, 0, sizeof(struct be_dma_mem));
3306 cmd.size = sizeof(struct be_cmd_resp_acpi_wol_magic_config_v1);
a2cc4e0b 3307 cmd.va = pci_alloc_consistent(adapter->pdev, cmd.size, &cmd.dma);
4762f6ce 3308 if (!cmd.va) {
a2cc4e0b 3309 dev_err(&adapter->pdev->dev, "Memory allocation failure\n");
d98ef50f
SR		 3310 status = -ENOMEM;
3311 goto err;
4762f6ce
AK		 3312 }
3313
4762f6ce
AK		 3314 wrb = wrb_from_mbox(adapter);
3315 if (!wrb) {
3316 status = -EBUSY;
3317 goto err;
3318 }
3319
3320 req = cmd.va;
3321
3322 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
3323 OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG,
76a9e08e 3324 sizeof(*req), wrb, &cmd);
4762f6ce
AK		 3325
3326 req->hdr.version = 1;
3327 req->query_options = BE_GET_WOL_CAP;
3328
3329 status = be_mbox_notify_wait(adapter);
3330 if (!status) {
3331 struct be_cmd_resp_acpi_wol_magic_config_v1 *resp;
03d28ffe 3332
504fbf1e 3333 resp = (struct be_cmd_resp_acpi_wol_magic_config_v1 *)cmd.va;
4762f6ce 3334
4762f6ce 3335 adapter->wol_cap = resp->wol_settings;
76a9e08e
SR		 3336 if (adapter->wol_cap & BE_WOL_CAP)
3337 adapter->wol_en = true;
4762f6ce
AK		 3338 }
3339err:
3340 mutex_unlock(&adapter->mbox_lock);
d98ef50f
SR		 3341 if (cmd.va)
3342 pci_free_consistent(adapter->pdev, cmd.size, cmd.va, cmd.dma);
4762f6ce 3343 return status;
941a77d5
SK		 3344
3345}
baaa08d1
VV		 3346
3347int be_cmd_set_fw_log_level(struct be_adapter *adapter, u32 level)
3348{
3349 struct be_dma_mem extfat_cmd;
3350 struct be_fat_conf_params *cfgs;
3351 int status;
3352 int i, j;
3353
3354 memset(&extfat_cmd, 0, sizeof(struct be_dma_mem));
3355 extfat_cmd.size = sizeof(struct be_cmd_resp_get_ext_fat_caps);
3356 extfat_cmd.va = pci_alloc_consistent(adapter->pdev, extfat_cmd.size,
3357 &extfat_cmd.dma);
3358 if (!extfat_cmd.va)
3359 return -ENOMEM;
3360
3361 status = be_cmd_get_ext_fat_capabilites(adapter, &extfat_cmd);
3362 if (status)
3363 goto err;
3364
3365 cfgs = (struct be_fat_conf_params *)
3366 (extfat_cmd.va + sizeof(struct be_cmd_resp_hdr));
3367 for (i = 0; i < le32_to_cpu(cfgs->num_modules); i++) {
3368 u32 num_modes = le32_to_cpu(cfgs->module[i].num_modes);
03d28ffe 3369
baaa08d1
VV		 3370 for (j = 0; j < num_modes; j++) {
3371 if (cfgs->module[i].trace_lvl[j].mode == MODE_UART)
3372 cfgs->module[i].trace_lvl[j].dbg_lvl =
3373 cpu_to_le32(level);
3374 }
3375 }
3376
3377 status = be_cmd_set_ext_fat_capabilites(adapter, &extfat_cmd, cfgs);
3378err:
3379 pci_free_consistent(adapter->pdev, extfat_cmd.size, extfat_cmd.va,
3380 extfat_cmd.dma);
3381 return status;
3382}
3383
3384int be_cmd_get_fw_log_level(struct be_adapter *adapter)
3385{
3386 struct be_dma_mem extfat_cmd;
3387 struct be_fat_conf_params *cfgs;
3388 int status, j;
3389 int level = 0;
3390
3391 memset(&extfat_cmd, 0, sizeof(struct be_dma_mem));
3392 extfat_cmd.size = sizeof(struct be_cmd_resp_get_ext_fat_caps);
3393 extfat_cmd.va = pci_alloc_consistent(adapter->pdev, extfat_cmd.size,
3394 &extfat_cmd.dma);
3395
3396 if (!extfat_cmd.va) {
3397 dev_err(&adapter->pdev->dev, "%s: Memory allocation failure\n",
3398 __func__);
3399 goto err;
3400 }
3401
3402 status = be_cmd_get_ext_fat_capabilites(adapter, &extfat_cmd);
3403 if (!status) {
3404 cfgs = (struct be_fat_conf_params *)(extfat_cmd.va +
3405 sizeof(struct be_cmd_resp_hdr));
03d28ffe 3406
baaa08d1
VV		 3407 for (j = 0; j < le32_to_cpu(cfgs->module[0].num_modes); j++) {
3408 if (cfgs->module[0].trace_lvl[j].mode == MODE_UART)
3409 level = cfgs->module[0].trace_lvl[j].dbg_lvl;
3410 }
3411 }
3412 pci_free_consistent(adapter->pdev, extfat_cmd.size, extfat_cmd.va,
3413 extfat_cmd.dma);
3414err:
3415 return level;
3416}
3417
941a77d5
SK		 3418int be_cmd_get_ext_fat_capabilites(struct be_adapter *adapter,
3419 struct be_dma_mem *cmd)
3420{
3421 struct be_mcc_wrb *wrb;
3422 struct be_cmd_req_get_ext_fat_caps *req;
3423 int status;
3424
3425 if (mutex_lock_interruptible(&adapter->mbox_lock))
3426 return -1;
3427
3428 wrb = wrb_from_mbox(adapter);
3429 if (!wrb) {
3430 status = -EBUSY;
3431 goto err;
3432 }
3433
3434 req = cmd->va;
3435 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3436 OPCODE_COMMON_GET_EXT_FAT_CAPABILITES,
3437 cmd->size, wrb, cmd);
3438 req->parameter_type = cpu_to_le32(1);
3439
3440 status = be_mbox_notify_wait(adapter);
3441err:
3442 mutex_unlock(&adapter->mbox_lock);
3443 return status;
3444}
3445
3446int be_cmd_set_ext_fat_capabilites(struct be_adapter *adapter,
3447 struct be_dma_mem *cmd,
3448 struct be_fat_conf_params *configs)
3449{
3450 struct be_mcc_wrb *wrb;
3451 struct be_cmd_req_set_ext_fat_caps *req;
3452 int status;
3453
3454 spin_lock_bh(&adapter->mcc_lock);
3455
3456 wrb = wrb_from_mccq(adapter);
3457 if (!wrb) {
3458 status = -EBUSY;
3459 goto err;
3460 }
3461
3462 req = cmd->va;
3463 memcpy(&req->set_params, configs, sizeof(struct be_fat_conf_params));
3464 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3465 OPCODE_COMMON_SET_EXT_FAT_CAPABILITES,
3466 cmd->size, wrb, cmd);
3467
3468 status = be_mcc_notify_wait(adapter);
3469err:
3470 spin_unlock_bh(&adapter->mcc_lock);
3471 return status;
4762f6ce 3472}
6a4ab669 3473
21252377 3474int be_cmd_query_port_name(struct be_adapter *adapter)
b4e32a71 3475{
b4e32a71 3476 struct be_cmd_req_get_port_name *req;
21252377 3477 struct be_mcc_wrb *wrb;
b4e32a71
PR		 3478 int status;
3479
21252377
VV		 3480 if (mutex_lock_interruptible(&adapter->mbox_lock))
3481 return -1;
b4e32a71 3482
21252377 3483 wrb = wrb_from_mbox(adapter);
b4e32a71
PR		 3484 req = embedded_payload(wrb);
3485
3486 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3487 OPCODE_COMMON_GET_PORT_NAME, sizeof(*req), wrb,
3488 NULL);
21252377
VV		 3489 if (!BEx_chip(adapter))
3490 req->hdr.version = 1;
b4e32a71 3491
21252377 3492 status = be_mbox_notify_wait(adapter);
b4e32a71
PR		 3493 if (!status) {
3494 struct be_cmd_resp_get_port_name *resp = embedded_payload(wrb);
03d28ffe 3495
21252377 3496 adapter->port_name = resp->port_name[adapter->hba_port_num];
b4e32a71 3497 } else {
21252377 3498 adapter->port_name = adapter->hba_port_num + '0';
b4e32a71 3499 }
21252377
VV		 3500
3501 mutex_unlock(&adapter->mbox_lock);
b4e32a71
PR		 3502 return status;
3503}
3504
10cccf60
VV		 3505/* Descriptor type */
3506enum {
3507 FUNC_DESC = 1,
3508 VFT_DESC = 2
3509};
3510
3511static struct be_nic_res_desc *be_get_nic_desc(u8 *buf, u32 desc_count,
3512 int desc_type)
abb93951 3513{
150d58c7 3514 struct be_res_desc_hdr *hdr = (struct be_res_desc_hdr *)buf;
10cccf60 3515 struct be_nic_res_desc *nic;
abb93951
PR		 3516 int i;
3517
3518 for (i = 0; i < desc_count; i++) {
150d58c7 3519 if (hdr->desc_type == NIC_RESOURCE_DESC_TYPE_V0 ||
10cccf60
VV		 3520 hdr->desc_type == NIC_RESOURCE_DESC_TYPE_V1) {
3521 nic = (struct be_nic_res_desc *)hdr;
3522 if (desc_type == FUNC_DESC ||
3523 (desc_type == VFT_DESC &&
3524 nic->flags & (1 << VFT_SHIFT)))
3525 return nic;
3526 }
abb93951 3527
150d58c7
VV		 3528 hdr->desc_len = hdr->desc_len ? : RESOURCE_DESC_SIZE_V0;
3529 hdr = (void *)hdr + hdr->desc_len;
abb93951 3530 }
150d58c7
VV		 3531 return NULL;
3532}
3533
10cccf60
VV		 3534static struct be_nic_res_desc *be_get_vft_desc(u8 *buf, u32 desc_count)
3535{
3536 return be_get_nic_desc(buf, desc_count, VFT_DESC);
3537}
3538
3539static struct be_nic_res_desc *be_get_func_nic_desc(u8 *buf, u32 desc_count)
3540{
3541 return be_get_nic_desc(buf, desc_count, FUNC_DESC);
3542}
3543
150d58c7
VV		 3544static struct be_pcie_res_desc *be_get_pcie_desc(u8 devfn, u8 *buf,
3545 u32 desc_count)
3546{
3547 struct be_res_desc_hdr *hdr = (struct be_res_desc_hdr *)buf;
3548 struct be_pcie_res_desc *pcie;
3549 int i;
3550
3551 for (i = 0; i < desc_count; i++) {
3552 if ((hdr->desc_type == PCIE_RESOURCE_DESC_TYPE_V0 ||
3553 hdr->desc_type == PCIE_RESOURCE_DESC_TYPE_V1)) {
3554 pcie = (struct be_pcie_res_desc *)hdr;
3555 if (pcie->pf_num == devfn)
3556 return pcie;
3557 }
abb93951 3558
150d58c7
VV		 3559 hdr->desc_len = hdr->desc_len ? : RESOURCE_DESC_SIZE_V0;
3560 hdr = (void *)hdr + hdr->desc_len;
3561 }
950e2958 3562 return NULL;
abb93951
PR		 3563}
3564
f93f160b
VV		 3565static struct be_port_res_desc *be_get_port_desc(u8 *buf, u32 desc_count)
3566{
3567 struct be_res_desc_hdr *hdr = (struct be_res_desc_hdr *)buf;
3568 int i;
3569
3570 for (i = 0; i < desc_count; i++) {
3571 if (hdr->desc_type == PORT_RESOURCE_DESC_TYPE_V1)
3572 return (struct be_port_res_desc *)hdr;
3573
3574 hdr->desc_len = hdr->desc_len ? : RESOURCE_DESC_SIZE_V0;
3575 hdr = (void *)hdr + hdr->desc_len;
3576 }
3577 return NULL;
3578}
3579
92bf14ab
SP		 3580static void be_copy_nic_desc(struct be_resources *res,
3581 struct be_nic_res_desc *desc)
3582{
3583 res->max_uc_mac = le16_to_cpu(desc->unicast_mac_count);
3584 res->max_vlans = le16_to_cpu(desc->vlan_count);
3585 res->max_mcast_mac = le16_to_cpu(desc->mcast_mac_count);
3586 res->max_tx_qs = le16_to_cpu(desc->txq_count);
3587 res->max_rss_qs = le16_to_cpu(desc->rssq_count);
3588 res->max_rx_qs = le16_to_cpu(desc->rq_count);
3589 res->max_evt_qs = le16_to_cpu(desc->eq_count);
f2858738
VV		 3590 res->max_cq_count = le16_to_cpu(desc->cq_count);
3591 res->max_iface_count = le16_to_cpu(desc->iface_count);
3592 res->max_mcc_count = le16_to_cpu(desc->mcc_count);
92bf14ab
SP		 3593 /* Clear flags that driver is not interested in */
3594 res->if_cap_flags = le32_to_cpu(desc->cap_flags) &
3595 BE_IF_CAP_FLAGS_WANT;
92bf14ab
SP		 3596}
3597
abb93951 3598/* Uses Mbox */
92bf14ab 3599int be_cmd_get_func_config(struct be_adapter *adapter, struct be_resources *res)
abb93951
PR		 3600{
3601 struct be_mcc_wrb *wrb;
3602 struct be_cmd_req_get_func_config *req;
3603 int status;
3604 struct be_dma_mem cmd;
3605
d98ef50f
SR		 3606 if (mutex_lock_interruptible(&adapter->mbox_lock))
3607 return -1;
3608
abb93951
PR		 3609 memset(&cmd, 0, sizeof(struct be_dma_mem));
3610 cmd.size = sizeof(struct be_cmd_resp_get_func_config);
a2cc4e0b 3611 cmd.va = pci_alloc_consistent(adapter->pdev, cmd.size, &cmd.dma);
abb93951
PR		 3612 if (!cmd.va) {
3613 dev_err(&adapter->pdev->dev, "Memory alloc failure\n");
d98ef50f
SR		 3614 status = -ENOMEM;
3615 goto err;
abb93951 3616 }
abb93951
PR		 3617
3618 wrb = wrb_from_mbox(adapter);
3619 if (!wrb) {
3620 status = -EBUSY;
3621 goto err;
3622 }
3623
3624 req = cmd.va;
3625
3626 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3627 OPCODE_COMMON_GET_FUNC_CONFIG,
3628 cmd.size, wrb, &cmd);
3629
28710c55
KA		 3630 if (skyhawk_chip(adapter))
3631 req->hdr.version = 1;
3632
abb93951
PR		 3633 status = be_mbox_notify_wait(adapter);
3634 if (!status) {
3635 struct be_cmd_resp_get_func_config *resp = cmd.va;
3636 u32 desc_count = le32_to_cpu(resp->desc_count);
150d58c7 3637 struct be_nic_res_desc *desc;
abb93951 3638
10cccf60 3639 desc = be_get_func_nic_desc(resp->func_param, desc_count);
abb93951
PR		 3640 if (!desc) {
3641 status = -EINVAL;
3642 goto err;
3643 }
3644
d5c18473 3645 adapter->pf_number = desc->pf_num;
92bf14ab 3646 be_copy_nic_desc(res, desc);
abb93951
PR		 3647 }
3648err:
3649 mutex_unlock(&adapter->mbox_lock);
d98ef50f
SR		 3650 if (cmd.va)
3651 pci_free_consistent(adapter->pdev, cmd.size, cmd.va, cmd.dma);
abb93951
PR		 3652 return status;
3653}
3654
ba48c0c9 3655/* Will use MBOX only if MCCQ has not been created */
92bf14ab 3656int be_cmd_get_profile_config(struct be_adapter *adapter,
f2858738 3657 struct be_resources *res, u8 query, u8 domain)
a05f99db 3658{
150d58c7 3659 struct be_cmd_resp_get_profile_config *resp;
ba48c0c9 3660 struct be_cmd_req_get_profile_config *req;
10cccf60 3661 struct be_nic_res_desc *vf_res;
150d58c7 3662 struct be_pcie_res_desc *pcie;
f93f160b 3663 struct be_port_res_desc *port;
150d58c7 3664 struct be_nic_res_desc *nic;
ba48c0c9 3665 struct be_mcc_wrb wrb = {0};
a05f99db 3666 struct be_dma_mem cmd;
f2858738 3667 u16 desc_count;
a05f99db
VV		 3668 int status;
3669
3670 memset(&cmd, 0, sizeof(struct be_dma_mem));
150d58c7
VV		 3671 cmd.size = sizeof(struct be_cmd_resp_get_profile_config);
3672 cmd.va = pci_alloc_consistent(adapter->pdev, cmd.size, &cmd.dma);
3673 if (!cmd.va)
a05f99db 3674 return -ENOMEM;
a05f99db 3675
ba48c0c9
VV		 3676 req = cmd.va;
3677 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3678 OPCODE_COMMON_GET_PROFILE_CONFIG,
3679 cmd.size, &wrb, &cmd);
3680
3681 req->hdr.domain = domain;
3682 if (!lancer_chip(adapter))
3683 req->hdr.version = 1;
3684 req->type = ACTIVE_PROFILE_TYPE;
3685
f2858738
VV		 3686 /* When QUERY_MODIFIABLE_FIELDS_TYPE bit is set, cmd returns the
3687 * descriptors with all bits set to "1" for the fields which can be
3688 * modified using SET_PROFILE_CONFIG cmd.
3689 */
3690 if (query == RESOURCE_MODIFIABLE)
3691 req->type |= QUERY_MODIFIABLE_FIELDS_TYPE;
3692
ba48c0c9 3693 status = be_cmd_notify_wait(adapter, &wrb);
150d58c7
VV		 3694 if (status)
3695 goto err;
abb93951 3696
150d58c7 3697 resp = cmd.va;
f2858738 3698 desc_count = le16_to_cpu(resp->desc_count);
abb93951 3699
a2cc4e0b
SP		 3700 pcie = be_get_pcie_desc(adapter->pdev->devfn, resp->func_param,
3701 desc_count);
150d58c7 3702 if (pcie)
92bf14ab 3703 res->max_vfs = le16_to_cpu(pcie->num_vfs);
150d58c7 3704
f93f160b
VV		 3705 port = be_get_port_desc(resp->func_param, desc_count);
3706 if (port)
3707 adapter->mc_type = port->mc_type;
3708
10cccf60 3709 nic = be_get_func_nic_desc(resp->func_param, desc_count);
92bf14ab
SP		 3710 if (nic)
3711 be_copy_nic_desc(res, nic);
3712
10cccf60
VV		 3713 vf_res = be_get_vft_desc(resp->func_param, desc_count);
3714 if (vf_res)
3715 res->vf_if_cap_flags = vf_res->cap_flags;
abb93951 3716err:
a05f99db 3717 if (cmd.va)
150d58c7 3718 pci_free_consistent(adapter->pdev, cmd.size, cmd.va, cmd.dma);
abb93951
PR		 3719 return status;
3720}
3721
bec84e6b
VV		 3722/* Will use MBOX only if MCCQ has not been created */
3723static int be_cmd_set_profile_config(struct be_adapter *adapter, void *desc,
3724 int size, int count, u8 version, u8 domain)
d5c18473 3725{
d5c18473 3726 struct be_cmd_req_set_profile_config *req;
bec84e6b
VV		 3727 struct be_mcc_wrb wrb = {0};
3728 struct be_dma_mem cmd;
d5c18473
PR		 3729 int status;
3730
bec84e6b
VV		 3731 memset(&cmd, 0, sizeof(struct be_dma_mem));
3732 cmd.size = sizeof(struct be_cmd_req_set_profile_config);
3733 cmd.va = pci_alloc_consistent(adapter->pdev, cmd.size, &cmd.dma);
3734 if (!cmd.va)
3735 return -ENOMEM;
d5c18473 3736
bec84e6b 3737 req = cmd.va;
d5c18473 3738 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
bec84e6b
VV		 3739 OPCODE_COMMON_SET_PROFILE_CONFIG, cmd.size,
3740 &wrb, &cmd);
a401801c 3741 req->hdr.version = version;
d5c18473 3742 req->hdr.domain = domain;
bec84e6b 3743 req->desc_count = cpu_to_le32(count);
a401801c
SP		 3744 memcpy(req->desc, desc, size);
3745
bec84e6b
VV		 3746 status = be_cmd_notify_wait(adapter, &wrb);
3747
3748 if (cmd.va)
3749 pci_free_consistent(adapter->pdev, cmd.size, cmd.va, cmd.dma);
d5c18473
PR		 3750 return status;
3751}
3752
a401801c 3753/* Mark all fields invalid */
bec84e6b 3754static void be_reset_nic_desc(struct be_nic_res_desc *nic)
a401801c
SP		 3755{
3756 memset(nic, 0, sizeof(*nic));
3757 nic->unicast_mac_count = 0xFFFF;
3758 nic->mcc_count = 0xFFFF;
3759 nic->vlan_count = 0xFFFF;
3760 nic->mcast_mac_count = 0xFFFF;
3761 nic->txq_count = 0xFFFF;
3762 nic->rq_count = 0xFFFF;
3763 nic->rssq_count = 0xFFFF;
3764 nic->lro_count = 0xFFFF;
3765 nic->cq_count = 0xFFFF;
3766 nic->toe_conn_count = 0xFFFF;
3767 nic->eq_count = 0xFFFF;
0f77ba73 3768 nic->iface_count = 0xFFFF;
a401801c 3769 nic->link_param = 0xFF;
0f77ba73 3770 nic->channel_id_param = cpu_to_le16(0xF000);
a401801c
SP		 3771 nic->acpi_params = 0xFF;
3772 nic->wol_param = 0x0F;
0f77ba73
RN		 3773 nic->tunnel_iface_count = 0xFFFF;
3774 nic->direct_tenant_iface_count = 0xFFFF;
bec84e6b 3775 nic->bw_min = 0xFFFFFFFF;
a401801c
SP		 3776 nic->bw_max = 0xFFFFFFFF;
3777}
3778
bec84e6b
VV		 3779/* Mark all fields invalid */
3780static void be_reset_pcie_desc(struct be_pcie_res_desc *pcie)
3781{
3782 memset(pcie, 0, sizeof(*pcie));
3783 pcie->sriov_state = 0xFF;
3784 pcie->pf_state = 0xFF;
3785 pcie->pf_type = 0xFF;
3786 pcie->num_vfs = 0xFFFF;
3787}
3788
0f77ba73
RN		 3789int be_cmd_config_qos(struct be_adapter *adapter, u32 max_rate, u16 link_speed,
3790 u8 domain)
a401801c 3791{
0f77ba73
RN		 3792 struct be_nic_res_desc nic_desc;
3793 u32 bw_percent;
3794 u16 version = 0;
3795
3796 if (BE3_chip(adapter))
3797 return be_cmd_set_qos(adapter, max_rate / 10, domain);
a401801c 3798
0f77ba73
RN		 3799 be_reset_nic_desc(&nic_desc);
3800 nic_desc.pf_num = adapter->pf_number;
3801 nic_desc.vf_num = domain;
58bdeaa6 3802 nic_desc.bw_min = 0;
0f77ba73 3803 if (lancer_chip(adapter)) {
a401801c
SP		 3804 nic_desc.hdr.desc_type = NIC_RESOURCE_DESC_TYPE_V0;
3805 nic_desc.hdr.desc_len = RESOURCE_DESC_SIZE_V0;
3806 nic_desc.flags = (1 << QUN_SHIFT) | (1 << IMM_SHIFT) |
3807 (1 << NOSV_SHIFT);
0f77ba73 3808 nic_desc.bw_max = cpu_to_le32(max_rate / 10);
a401801c 3809 } else {
0f77ba73
RN		 3810 version = 1;
3811 nic_desc.hdr.desc_type = NIC_RESOURCE_DESC_TYPE_V1;
3812 nic_desc.hdr.desc_len = RESOURCE_DESC_SIZE_V1;
3813 nic_desc.flags = (1 << IMM_SHIFT) | (1 << NOSV_SHIFT);
3814 bw_percent = max_rate ? (max_rate * 100) / link_speed : 100;
3815 nic_desc.bw_max = cpu_to_le32(bw_percent);
a401801c 3816 }
0f77ba73
RN		 3817
3818 return be_cmd_set_profile_config(adapter, &nic_desc,
3819 nic_desc.hdr.desc_len,
bec84e6b
VV		 3820 1, version, domain);
3821}
3822
f2858738
VV		 3823static void be_fill_vf_res_template(struct be_adapter *adapter,
3824 struct be_resources pool_res,
3825 u16 num_vfs, u16 num_vf_qs,
3826 struct be_nic_res_desc *nic_vft)
3827{
3828 u32 vf_if_cap_flags = pool_res.vf_if_cap_flags;
3829 struct be_resources res_mod = {0};
3830
3831 /* Resource with fields set to all '1's by GET_PROFILE_CONFIG cmd,
3832 * which are modifiable using SET_PROFILE_CONFIG cmd.
3833 */
3834 be_cmd_get_profile_config(adapter, &res_mod, RESOURCE_MODIFIABLE, 0);
3835
3836 /* If RSS IFACE capability flags are modifiable for a VF, set the
3837 * capability flag as valid and set RSS and DEFQ_RSS IFACE flags if
3838 * more than 1 RSSQ is available for a VF.
3839 * Otherwise, provision only 1 queue pair for VF.
3840 */
3841 if (res_mod.vf_if_cap_flags & BE_IF_FLAGS_RSS) {
3842 nic_vft->flags |= BIT(IF_CAPS_FLAGS_VALID_SHIFT);
3843 if (num_vf_qs > 1) {
3844 vf_if_cap_flags |= BE_IF_FLAGS_RSS;
3845 if (pool_res.if_cap_flags & BE_IF_FLAGS_DEFQ_RSS)
3846 vf_if_cap_flags |= BE_IF_FLAGS_DEFQ_RSS;
3847 } else {
3848 vf_if_cap_flags &= ~(BE_IF_FLAGS_RSS |
3849 BE_IF_FLAGS_DEFQ_RSS);
3850 }
3851
3852 nic_vft->cap_flags = cpu_to_le32(vf_if_cap_flags);
3853 } else {
3854 num_vf_qs = 1;
3855 }
3856
3857 nic_vft->rq_count = cpu_to_le16(num_vf_qs);
3858 nic_vft->txq_count = cpu_to_le16(num_vf_qs);
3859 nic_vft->rssq_count = cpu_to_le16(num_vf_qs);
3860 nic_vft->cq_count = cpu_to_le16(pool_res.max_cq_count /
3861 (num_vfs + 1));
3862
3863 /* Distribute unicast MACs, VLANs, IFACE count and MCCQ count equally
3864 * among the PF and it's VFs, if the fields are changeable
3865 */
3866 if (res_mod.max_uc_mac == FIELD_MODIFIABLE)
3867 nic_vft->unicast_mac_count = cpu_to_le16(pool_res.max_uc_mac /
3868 (num_vfs + 1));
3869
3870 if (res_mod.max_vlans == FIELD_MODIFIABLE)
3871 nic_vft->vlan_count = cpu_to_le16(pool_res.max_vlans /
3872 (num_vfs + 1));
3873
3874 if (res_mod.max_iface_count == FIELD_MODIFIABLE)
3875 nic_vft->iface_count = cpu_to_le16(pool_res.max_iface_count /
3876 (num_vfs + 1));
3877
3878 if (res_mod.max_mcc_count == FIELD_MODIFIABLE)
3879 nic_vft->mcc_count = cpu_to_le16(pool_res.max_mcc_count /
3880 (num_vfs + 1));
3881}
3882
bec84e6b 3883int be_cmd_set_sriov_config(struct be_adapter *adapter,
f2858738
VV		 3884 struct be_resources pool_res, u16 num_vfs,
3885 u16 num_vf_qs)
bec84e6b
VV		 3886{
3887 struct {
3888 struct be_pcie_res_desc pcie;
3889 struct be_nic_res_desc nic_vft;
3890 } __packed desc;
bec84e6b 3891
bec84e6b
VV		 3892 /* PF PCIE descriptor */
3893 be_reset_pcie_desc(&desc.pcie);
3894 desc.pcie.hdr.desc_type = PCIE_RESOURCE_DESC_TYPE_V1;
3895 desc.pcie.hdr.desc_len = RESOURCE_DESC_SIZE_V1;
f2858738 3896 desc.pcie.flags = BIT(IMM_SHIFT) | BIT(NOSV_SHIFT);
bec84e6b
VV		 3897 desc.pcie.pf_num = adapter->pdev->devfn;
3898 desc.pcie.sriov_state = num_vfs ? 1 : 0;
3899 desc.pcie.num_vfs = cpu_to_le16(num_vfs);
3900
3901 /* VF NIC Template descriptor */
3902 be_reset_nic_desc(&desc.nic_vft);
3903 desc.nic_vft.hdr.desc_type = NIC_RESOURCE_DESC_TYPE_V1;
3904 desc.nic_vft.hdr.desc_len = RESOURCE_DESC_SIZE_V1;
f2858738 3905 desc.nic_vft.flags = BIT(VFT_SHIFT) | BIT(IMM_SHIFT) | BIT(NOSV_SHIFT);
bec84e6b
VV		 3906 desc.nic_vft.pf_num = adapter->pdev->devfn;
3907 desc.nic_vft.vf_num = 0;
3908
f2858738
VV		 3909 be_fill_vf_res_template(adapter, pool_res, num_vfs, num_vf_qs,
3910 &desc.nic_vft);
bec84e6b
VV		 3911
3912 return be_cmd_set_profile_config(adapter, &desc,
3913 2 * RESOURCE_DESC_SIZE_V1, 2, 1, 0);
a401801c
SP		 3914}
3915
3916int be_cmd_manage_iface(struct be_adapter *adapter, u32 iface, u8 op)
3917{
3918 struct be_mcc_wrb *wrb;
3919 struct be_cmd_req_manage_iface_filters *req;
3920 int status;
3921
3922 if (iface == 0xFFFFFFFF)
3923 return -1;
3924
3925 spin_lock_bh(&adapter->mcc_lock);
3926
3927 wrb = wrb_from_mccq(adapter);
3928 if (!wrb) {
3929 status = -EBUSY;
3930 goto err;
3931 }
3932 req = embedded_payload(wrb);
3933
3934 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3935 OPCODE_COMMON_MANAGE_IFACE_FILTERS, sizeof(*req),
3936 wrb, NULL);
3937 req->op = op;
3938 req->target_iface_id = cpu_to_le32(iface);
3939
3940 status = be_mcc_notify_wait(adapter);
3941err:
3942 spin_unlock_bh(&adapter->mcc_lock);
3943 return status;
3944}
3945
3946int be_cmd_set_vxlan_port(struct be_adapter *adapter, __be16 port)
3947{
3948 struct be_port_res_desc port_desc;
3949
3950 memset(&port_desc, 0, sizeof(port_desc));
3951 port_desc.hdr.desc_type = PORT_RESOURCE_DESC_TYPE_V1;
3952 port_desc.hdr.desc_len = RESOURCE_DESC_SIZE_V1;
3953 port_desc.flags = (1 << IMM_SHIFT) | (1 << NOSV_SHIFT);
3954 port_desc.link_num = adapter->hba_port_num;
3955 if (port) {
3956 port_desc.nv_flags = NV_TYPE_VXLAN | (1 << SOCVID_SHIFT) |
3957 (1 << RCVID_SHIFT);
3958 port_desc.nv_port = swab16(port);
3959 } else {
3960 port_desc.nv_flags = NV_TYPE_DISABLED;
3961 port_desc.nv_port = 0;
3962 }
3963
3964 return be_cmd_set_profile_config(adapter, &port_desc,
bec84e6b 3965 RESOURCE_DESC_SIZE_V1, 1, 1, 0);
a401801c
SP		 3966}
3967
4c876616
SP		 3968int be_cmd_get_if_id(struct be_adapter *adapter, struct be_vf_cfg *vf_cfg,
3969 int vf_num)
3970{
3971 struct be_mcc_wrb *wrb;
3972 struct be_cmd_req_get_iface_list *req;
3973 struct be_cmd_resp_get_iface_list *resp;
3974 int status;
3975
3976 spin_lock_bh(&adapter->mcc_lock);
3977
3978 wrb = wrb_from_mccq(adapter);
3979 if (!wrb) {
3980 status = -EBUSY;
3981 goto err;
3982 }
3983 req = embedded_payload(wrb);
3984
3985 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3986 OPCODE_COMMON_GET_IFACE_LIST, sizeof(*resp),
3987 wrb, NULL);
3988 req->hdr.domain = vf_num + 1;
3989
3990 status = be_mcc_notify_wait(adapter);
3991 if (!status) {
3992 resp = (struct be_cmd_resp_get_iface_list *)req;
3993 vf_cfg->if_handle = le32_to_cpu(resp->if_desc.if_id);
3994 }
3995
3996err:
3997 spin_unlock_bh(&adapter->mcc_lock);
3998 return status;
3999}
4000
5c510811
SK		 4001static int lancer_wait_idle(struct be_adapter *adapter)
4002{
4003#define SLIPORT_IDLE_TIMEOUT 30
4004 u32 reg_val;
4005 int status = 0, i;
4006
4007 for (i = 0; i < SLIPORT_IDLE_TIMEOUT; i++) {
4008 reg_val = ioread32(adapter->db + PHYSDEV_CONTROL_OFFSET);
4009 if ((reg_val & PHYSDEV_CONTROL_INP_MASK) == 0)
4010 break;
4011
4012 ssleep(1);
4013 }
4014
4015 if (i == SLIPORT_IDLE_TIMEOUT)
4016 status = -1;
4017
4018 return status;
4019}
4020
4021int lancer_physdev_ctrl(struct be_adapter *adapter, u32 mask)
4022{
4023 int status = 0;
4024
4025 status = lancer_wait_idle(adapter);
4026 if (status)
4027 return status;
4028
4029 iowrite32(mask, adapter->db + PHYSDEV_CONTROL_OFFSET);
4030
4031 return status;
4032}
4033
4034/* Routine to check whether dump image is present or not */
4035bool dump_present(struct be_adapter *adapter)
4036{
4037 u32 sliport_status = 0;
4038
4039 sliport_status = ioread32(adapter->db + SLIPORT_STATUS_OFFSET);
4040 return !!(sliport_status & SLIPORT_STATUS_DIP_MASK);
4041}
4042
4043int lancer_initiate_dump(struct be_adapter *adapter)
4044{
f0613380 4045 struct device *dev = &adapter->pdev->dev;
5c510811
SK		 4046 int status;
4047
f0613380
KA		 4048 if (dump_present(adapter)) {
4049 dev_info(dev, "Previous dump not cleared, not forcing dump\n");
4050 return -EEXIST;
4051 }
4052
5c510811
SK		 4053 /* give firmware reset and diagnostic dump */
4054 status = lancer_physdev_ctrl(adapter, PHYSDEV_CONTROL_FW_RESET_MASK |
4055 PHYSDEV_CONTROL_DD_MASK);
4056 if (status < 0) {
f0613380 4057 dev_err(dev, "FW reset failed\n");
5c510811
SK		 4058 return status;
4059 }
4060
4061 status = lancer_wait_idle(adapter);
4062 if (status)
4063 return status;
4064
4065 if (!dump_present(adapter)) {
f0613380
KA		 4066 dev_err(dev, "FW dump not generated\n");
4067 return -EIO;
5c510811
SK		 4068 }
4069
4070 return 0;
4071}
4072
f0613380
KA		 4073int lancer_delete_dump(struct be_adapter *adapter)
4074{
4075 int status;
4076
4077 status = lancer_cmd_delete_object(adapter, LANCER_FW_DUMP_FILE);
4078 return be_cmd_status(status);
4079}
4080
dcf7ebba
PR		 4081/* Uses sync mcc */
4082int be_cmd_enable_vf(struct be_adapter *adapter, u8 domain)
4083{
4084 struct be_mcc_wrb *wrb;
4085 struct be_cmd_enable_disable_vf *req;
4086 int status;
4087
0599863d 4088 if (BEx_chip(adapter))
dcf7ebba
PR		 4089 return 0;
4090
4091 spin_lock_bh(&adapter->mcc_lock);
4092
4093 wrb = wrb_from_mccq(adapter);
4094 if (!wrb) {
4095 status = -EBUSY;
4096 goto err;
4097 }
4098
4099 req = embedded_payload(wrb);
4100
4101 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
4102 OPCODE_COMMON_ENABLE_DISABLE_VF, sizeof(*req),
4103 wrb, NULL);
4104
4105 req->hdr.domain = domain;
4106 req->enable = 1;
4107 status = be_mcc_notify_wait(adapter);
4108err:
4109 spin_unlock_bh(&adapter->mcc_lock);
4110 return status;
4111}
4112
68c45a2d
SK		 4113int be_cmd_intr_set(struct be_adapter *adapter, bool intr_enable)
4114{
4115 struct be_mcc_wrb *wrb;
4116 struct be_cmd_req_intr_set *req;
4117 int status;
4118
4119 if (mutex_lock_interruptible(&adapter->mbox_lock))
4120 return -1;
4121
4122 wrb = wrb_from_mbox(adapter);
4123
4124 req = embedded_payload(wrb);
4125
4126 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
4127 OPCODE_COMMON_SET_INTERRUPT_ENABLE, sizeof(*req),
4128 wrb, NULL);
4129
4130 req->intr_enabled = intr_enable;
4131
4132 status = be_mbox_notify_wait(adapter);
4133
4134 mutex_unlock(&adapter->mbox_lock);
4135 return status;
4136}
4137
542963b7
VV		 4138/* Uses MBOX */
4139int be_cmd_get_active_profile(struct be_adapter *adapter, u16 *profile_id)
4140{
4141 struct be_cmd_req_get_active_profile *req;
4142 struct be_mcc_wrb *wrb;
4143 int status;
4144
4145 if (mutex_lock_interruptible(&adapter->mbox_lock))
4146 return -1;
4147
4148 wrb = wrb_from_mbox(adapter);
4149 if (!wrb) {
4150 status = -EBUSY;
4151 goto err;
4152 }
4153
4154 req = embedded_payload(wrb);
4155
4156 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
4157 OPCODE_COMMON_GET_ACTIVE_PROFILE, sizeof(*req),
4158 wrb, NULL);
4159
4160 status = be_mbox_notify_wait(adapter);
4161 if (!status) {
4162 struct be_cmd_resp_get_active_profile *resp =
4163 embedded_payload(wrb);
03d28ffe 4164
542963b7
VV		 4165 *profile_id = le16_to_cpu(resp->active_profile_id);
4166 }
4167
4168err:
4169 mutex_unlock(&adapter->mbox_lock);
4170 return status;
4171}
4172
bdce2ad7
SR		 4173int be_cmd_set_logical_link_config(struct be_adapter *adapter,
4174 int link_state, u8 domain)
4175{
4176 struct be_mcc_wrb *wrb;
4177 struct be_cmd_req_set_ll_link *req;
4178 int status;
4179
4180 if (BEx_chip(adapter) || lancer_chip(adapter))
18fd6025 4181 return -EOPNOTSUPP;
bdce2ad7
SR		 4182
4183 spin_lock_bh(&adapter->mcc_lock);
4184
4185 wrb = wrb_from_mccq(adapter);
4186 if (!wrb) {
4187 status = -EBUSY;
4188 goto err;
4189 }
4190
4191 req = embedded_payload(wrb);
4192
4193 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
4194 OPCODE_COMMON_SET_LOGICAL_LINK_CONFIG,
4195 sizeof(*req), wrb, NULL);
4196
4197 req->hdr.version = 1;
4198 req->hdr.domain = domain;
4199
4200 if (link_state == IFLA_VF_LINK_STATE_ENABLE)
4201 req->link_config |= 1;
4202
4203 if (link_state == IFLA_VF_LINK_STATE_AUTO)
4204 req->link_config |= 1 << PLINK_TRACK_SHIFT;
4205
4206 status = be_mcc_notify_wait(adapter);
4207err:
4208 spin_unlock_bh(&adapter->mcc_lock);
4209 return status;
4210}
4211
6a4ab669 4212int be_roce_mcc_cmd(void *netdev_handle, void *wrb_payload,
a2cc4e0b 4213 int wrb_payload_size, u16 *cmd_status, u16 *ext_status)
6a4ab669
PP		 4214{
4215 struct be_adapter *adapter = netdev_priv(netdev_handle);
4216 struct be_mcc_wrb *wrb;
504fbf1e 4217 struct be_cmd_req_hdr *hdr = (struct be_cmd_req_hdr *)wrb_payload;
6a4ab669
PP		 4218 struct be_cmd_req_hdr *req;
4219 struct be_cmd_resp_hdr *resp;
4220 int status;
4221
4222 spin_lock_bh(&adapter->mcc_lock);
4223
4224 wrb = wrb_from_mccq(adapter);
4225 if (!wrb) {
4226 status = -EBUSY;
4227 goto err;
4228 }
4229 req = embedded_payload(wrb);
4230 resp = embedded_payload(wrb);
4231
4232 be_wrb_cmd_hdr_prepare(req, hdr->subsystem,
4233 hdr->opcode, wrb_payload_size, wrb, NULL);
4234 memcpy(req, wrb_payload, wrb_payload_size);
4235 be_dws_cpu_to_le(req, wrb_payload_size);
4236
4237 status = be_mcc_notify_wait(adapter);
4238 if (cmd_status)
4239 *cmd_status = (status & 0xffff);
4240 if (ext_status)
4241 *ext_status = 0;
4242 memcpy(wrb_payload, resp, sizeof(*resp) + resp->response_length);
4243 be_dws_le_to_cpu(wrb_payload, sizeof(*resp) + resp->response_length);
4244err:
4245 spin_unlock_bh(&adapter->mcc_lock);
4246 return status;
4247}
4248EXPORT_SYMBOL(be_roce_mcc_cmd);
Linux kernel - Deliverables
This page took 0.803895 seconds and 5 git commands to generate.