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Merge branch 'for-davem' into for-next
[deliverable/linux.git] / drivers / net / ethernet / emulex / benet / be_cmds.h
CommitLineData
6b7c5b94 1/*
40263820 2 * Copyright (C) 2005 - 2014 Emulex
6b7c5b94
SP		 3 * All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License version 2
7 * as published by the Free Software Foundation. The full GNU General
8 * Public License is included in this distribution in the file called COPYING.
9 *
10 * Contact Information:
d2145cde 11 * linux-drivers@emulex.com
6b7c5b94 12 *
d2145cde
AK		 13 * Emulex
14 * 3333 Susan Street
15 * Costa Mesa, CA 92626
6b7c5b94
SP		 16 */
17
18/*
19 * The driver sends configuration and managements command requests to the
20 * firmware in the BE. These requests are communicated to the processor
21 * using Work Request Blocks (WRBs) submitted to the MCC-WRB ring or via one
22 * WRB inside a MAILBOX.
23 * The commands are serviced by the ARM processor in the BladeEngine's MPU.
24 */
25
26struct be_sge {
27 u32 pa_lo;
28 u32 pa_hi;
29 u32 len;
30};
31
32#define MCC_WRB_EMBEDDED_MASK 1 /* bit 0 of dword 0*/
33#define MCC_WRB_SGE_CNT_SHIFT 3 /* bits 3 - 7 of dword 0 */
34#define MCC_WRB_SGE_CNT_MASK 0x1F /* bits 3 - 7 of dword 0 */
35struct be_mcc_wrb {
36 u32 embedded; /* dword 0 */
37 u32 payload_length; /* dword 1 */
38 u32 tag0; /* dword 2 */
39 u32 tag1; /* dword 3 */
40 u32 rsvd; /* dword 4 */
41 union {
42 u8 embedded_payload[236]; /* used by embedded cmds */
43 struct be_sge sgl[19]; /* used by non-embedded cmds */
44 } payload;
45};
46
83b06116
VV		 47#define CQE_FLAGS_VALID_MASK BIT(31)
48#define CQE_FLAGS_ASYNC_MASK BIT(30)
49#define CQE_FLAGS_COMPLETED_MASK BIT(28)
50#define CQE_FLAGS_CONSUMED_MASK BIT(27)
6b7c5b94
SP		 51
52/* Completion Status */
4c60005f 53enum mcc_base_status {
2b3f291b
SP		 54 MCC_STATUS_SUCCESS = 0,
55 MCC_STATUS_FAILED = 1,
56 MCC_STATUS_ILLEGAL_REQUEST = 2,
57 MCC_STATUS_ILLEGAL_FIELD = 3,
58 MCC_STATUS_INSUFFICIENT_BUFFER = 4,
59 MCC_STATUS_UNAUTHORIZED_REQUEST = 5,
b29812c1
SR		 60 MCC_STATUS_NOT_SUPPORTED = 66,
61 MCC_STATUS_FEATURE_NOT_SUPPORTED = 68
6b7c5b94
SP		 62};
63
4c60005f
KA		 64/* Additional status */
65enum mcc_addl_status {
66 MCC_ADDL_STATUS_INSUFFICIENT_RESOURCES = 0x16,
67 MCC_ADDL_STATUS_FLASH_IMAGE_CRC_MISMATCH = 0x4d,
68 MCC_ADDL_STATUS_TOO_MANY_INTERFACES = 0x4a
69};
70
71#define CQE_BASE_STATUS_MASK 0xFFFF
72#define CQE_BASE_STATUS_SHIFT 0 /* bits 0 - 15 */
73#define CQE_ADDL_STATUS_MASK 0xFF
74#define CQE_ADDL_STATUS_SHIFT 16 /* bits 16 - 31 */
d9d604f8 75
4c60005f
KA		 76#define base_status(status) \
77 ((enum mcc_base_status) \
78 (status > 0 ? (status & CQE_BASE_STATUS_MASK) : 0))
79#define addl_status(status) \
80 ((enum mcc_addl_status) \
81 (status > 0 ? (status >> CQE_ADDL_STATUS_SHIFT) & \
82 CQE_ADDL_STATUS_MASK : 0))
6b7c5b94 83
efd2e40a 84struct be_mcc_compl {
6b7c5b94
SP		 85 u32 status; /* dword 0 */
86 u32 tag0; /* dword 1 */
87 u32 tag1; /* dword 2 */
88 u32 flags; /* dword 3 */
89};
90
3acf19d9
SP		 91/* When the async bit of mcc_compl flags is set, flags
92 * is interpreted as follows:
a8f447bd 93 */
3acf19d9
SP		 94#define ASYNC_EVENT_CODE_SHIFT 8 /* bits 8 - 15 */
95#define ASYNC_EVENT_CODE_MASK 0xFF
96#define ASYNC_EVENT_TYPE_SHIFT 16
97#define ASYNC_EVENT_TYPE_MASK 0xFF
a8f447bd 98#define ASYNC_EVENT_CODE_LINK_STATE 0x1
cc4ce020
SK		 99#define ASYNC_EVENT_CODE_GRP_5 0x5
100#define ASYNC_EVENT_QOS_SPEED 0x1
101#define ASYNC_EVENT_COS_PRIORITY 0x2
3968fa1e 102#define ASYNC_EVENT_PVID_STATE 0x3
bc0c3405
AK		 103#define ASYNC_EVENT_CODE_QNQ 0x6
104#define ASYNC_DEBUG_EVENT_TYPE_QNQ 1
21252377
VV		 105#define ASYNC_EVENT_CODE_SLIPORT 0x11
106#define ASYNC_EVENT_PORT_MISCONFIG 0x9
bc0c3405 107
a8f447bd 108enum {
ea172a01
SP		 109 LINK_DOWN = 0x0,
110 LINK_UP = 0x1
a8f447bd 111};
ea172a01 112#define LINK_STATUS_MASK 0x1
2e177a5c 113#define LOGICAL_LINK_STATUS_MASK 0x2
a8f447bd 114
3acf19d9 115/* When the event code of compl->flags is link-state, the mcc_compl
a8f447bd
SP		 116 * must be interpreted as follows
117 */
118struct be_async_event_link_state {
119 u8 physical_port;
120 u8 port_link_status;
121 u8 port_duplex;
122 u8 port_speed;
123 u8 port_fault;
124 u8 rsvd0[7];
3acf19d9 125 u32 flags;
a8f447bd
SP		 126} __packed;
127
3acf19d9 128/* When the event code of compl->flags is GRP-5 and event_type is QOS_SPEED
cc4ce020
SK		 129 * the mcc_compl must be interpreted as follows
130 */
131struct be_async_event_grp5_qos_link_speed {
132 u8 physical_port;
133 u8 rsvd[5];
134 u16 qos_link_speed;
135 u32 event_tag;
3acf19d9 136 u32 flags;
cc4ce020
SK		 137} __packed;
138
3acf19d9 139/* When the event code of compl->flags is GRP5 and event type is
cc4ce020
SK		 140 * CoS-Priority, the mcc_compl must be interpreted as follows
141 */
142struct be_async_event_grp5_cos_priority {
143 u8 physical_port;
144 u8 available_priority_bmap;
145 u8 reco_default_priority;
146 u8 valid;
147 u8 rsvd0;
148 u8 event_tag;
3acf19d9 149 u32 flags;
cc4ce020
SK		 150} __packed;
151
3acf19d9 152/* When the event code of compl->flags is GRP5 and event type is
3968fa1e
AK		 153 * PVID state, the mcc_compl must be interpreted as follows
154 */
155struct be_async_event_grp5_pvid_state {
156 u8 enabled;
157 u8 rsvd0;
158 u16 tag;
159 u32 event_tag;
160 u32 rsvd1;
3acf19d9 161 u32 flags;
3968fa1e
AK		 162} __packed;
163
bc0c3405
AK		 164/* async event indicating outer VLAN tag in QnQ */
165struct be_async_event_qnq {
166 u8 valid; /* Indicates if outer VLAN is valid */
167 u8 rsvd0;
168 u16 vlan_tag;
169 u32 event_tag;
170 u8 rsvd1[4];
3acf19d9 171 u32 flags;
bc0c3405
AK		 172} __packed;
173
21252377
VV		 174#define INCOMPATIBLE_SFP 0x3
175/* async event indicating misconfigured port */
176struct be_async_event_misconfig_port {
177 u32 event_data_word1;
178 u32 event_data_word2;
179 u32 rsvd0;
180 u32 flags;
181} __packed;
182
6b7c5b94
SP		 183struct be_mcc_mailbox {
184 struct be_mcc_wrb wrb;
efd2e40a 185 struct be_mcc_compl compl;
6b7c5b94
SP		 186};
187
188#define CMD_SUBSYSTEM_COMMON 0x1
189#define CMD_SUBSYSTEM_ETH 0x3
ff33a6e2 190#define CMD_SUBSYSTEM_LOWLEVEL 0xb
6b7c5b94
SP		 191
192#define OPCODE_COMMON_NTWK_MAC_QUERY 1
193#define OPCODE_COMMON_NTWK_MAC_SET 2
194#define OPCODE_COMMON_NTWK_MULTICAST_SET 3
195#define OPCODE_COMMON_NTWK_VLAN_CONFIG 4
196#define OPCODE_COMMON_NTWK_LINK_STATUS_QUERY 5
fa9a6fed 197#define OPCODE_COMMON_READ_FLASHROM 6
84517482 198#define OPCODE_COMMON_WRITE_FLASHROM 7
6b7c5b94
SP		 199#define OPCODE_COMMON_CQ_CREATE 12
200#define OPCODE_COMMON_EQ_CREATE 13
cc4ce020 201#define OPCODE_COMMON_MCC_CREATE 21
e1d18735 202#define OPCODE_COMMON_SET_QOS 28
cc4ce020 203#define OPCODE_COMMON_MCC_CREATE_EXT 90
368c0ca2 204#define OPCODE_COMMON_SEEPROM_READ 30
9e1453c5 205#define OPCODE_COMMON_GET_CNTL_ATTRIBUTES 32
6b7c5b94
SP		 206#define OPCODE_COMMON_NTWK_RX_FILTER 34
207#define OPCODE_COMMON_GET_FW_VERSION 35
208#define OPCODE_COMMON_SET_FLOW_CONTROL 36
209#define OPCODE_COMMON_GET_FLOW_CONTROL 37
210#define OPCODE_COMMON_SET_FRAME_SIZE 39
211#define OPCODE_COMMON_MODIFY_EQ_DELAY 41
212#define OPCODE_COMMON_FIRMWARE_CONFIG 42
213#define OPCODE_COMMON_NTWK_INTERFACE_CREATE 50
214#define OPCODE_COMMON_NTWK_INTERFACE_DESTROY 51
5fb379ee 215#define OPCODE_COMMON_MCC_DESTROY 53
6b7c5b94
SP		 216#define OPCODE_COMMON_CQ_DESTROY 54
217#define OPCODE_COMMON_EQ_DESTROY 55
218#define OPCODE_COMMON_QUERY_FIRMWARE_CONFIG 58
219#define OPCODE_COMMON_NTWK_PMAC_ADD 59
220#define OPCODE_COMMON_NTWK_PMAC_DEL 60
14074eab 221#define OPCODE_COMMON_FUNCTION_RESET 61
311fddc7 222#define OPCODE_COMMON_MANAGE_FAT 68
fad9ab2c
SB		 223#define OPCODE_COMMON_ENABLE_DISABLE_BEACON 69
224#define OPCODE_COMMON_GET_BEACON_STATE 70
0388f251 225#define OPCODE_COMMON_READ_TRANSRECV_DATA 73
b4e32a71 226#define OPCODE_COMMON_GET_PORT_NAME 77
bdce2ad7 227#define OPCODE_COMMON_SET_LOGICAL_LINK_CONFIG 80
68c45a2d 228#define OPCODE_COMMON_SET_INTERRUPT_ENABLE 89
04a06028 229#define OPCODE_COMMON_SET_FN_PRIVILEGES 100
ee3cb629 230#define OPCODE_COMMON_GET_PHY_DETAILS 102
2e588f84 231#define OPCODE_COMMON_SET_DRIVER_FUNCTION_CAP 103
609ff3bb 232#define OPCODE_COMMON_GET_CNTL_ADDITIONAL_ATTRIBUTES 121
941a77d5
SK		 233#define OPCODE_COMMON_GET_EXT_FAT_CAPABILITES 125
234#define OPCODE_COMMON_SET_EXT_FAT_CAPABILITES 126
590c391d
PR		 235#define OPCODE_COMMON_GET_MAC_LIST 147
236#define OPCODE_COMMON_SET_MAC_LIST 148
f1f3ee1b 237#define OPCODE_COMMON_GET_HSW_CONFIG 152
abb93951
PR		 238#define OPCODE_COMMON_GET_FUNC_CONFIG 160
239#define OPCODE_COMMON_GET_PROFILE_CONFIG 164
d5c18473 240#define OPCODE_COMMON_SET_PROFILE_CONFIG 165
542963b7 241#define OPCODE_COMMON_GET_ACTIVE_PROFILE 167
f1f3ee1b 242#define OPCODE_COMMON_SET_HSW_CONFIG 153
f25b119c 243#define OPCODE_COMMON_GET_FN_PRIVILEGES 170
de49bd5a 244#define OPCODE_COMMON_READ_OBJECT 171
485bf569 245#define OPCODE_COMMON_WRITE_OBJECT 172
f0613380 246#define OPCODE_COMMON_DELETE_OBJECT 174
a401801c 247#define OPCODE_COMMON_MANAGE_IFACE_FILTERS 193
4c876616 248#define OPCODE_COMMON_GET_IFACE_LIST 194
dcf7ebba 249#define OPCODE_COMMON_ENABLE_DISABLE_VF 196
6b7c5b94 250
3abcdeda 251#define OPCODE_ETH_RSS_CONFIG 1
6b7c5b94
SP		 252#define OPCODE_ETH_ACPI_CONFIG 2
253#define OPCODE_ETH_PROMISCUOUS 3
254#define OPCODE_ETH_GET_STATISTICS 4
255#define OPCODE_ETH_TX_CREATE 7
256#define OPCODE_ETH_RX_CREATE 8
257#define OPCODE_ETH_TX_DESTROY 9
258#define OPCODE_ETH_RX_DESTROY 10
71d8d1b5 259#define OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG 12
005d5696 260#define OPCODE_ETH_GET_PPORT_STATS 18
6b7c5b94 261
ff33a6e2
S		 262#define OPCODE_LOWLEVEL_HOST_DDR_DMA 17
263#define OPCODE_LOWLEVEL_LOOPBACK_TEST 18
fced9999 264#define OPCODE_LOWLEVEL_SET_LOOPBACK_MODE 19
ff33a6e2 265
6b7c5b94
SP		 266struct be_cmd_req_hdr {
267 u8 opcode; /* dword 0 */
268 u8 subsystem; /* dword 0 */
269 u8 port_number; /* dword 0 */
270 u8 domain; /* dword 0 */
271 u32 timeout; /* dword 1 */
272 u32 request_length; /* dword 2 */
7b139c83
AK		 273 u8 version; /* dword 3 */
274 u8 rsvd[3]; /* dword 3 */
6b7c5b94
SP		 275};
276
277#define RESP_HDR_INFO_OPCODE_SHIFT 0 /* bits 0 - 7 */
278#define RESP_HDR_INFO_SUBSYS_SHIFT 8 /* bits 8 - 15 */
279struct be_cmd_resp_hdr {
652bf646
PR		 280 u8 opcode; /* dword 0 */
281 u8 subsystem; /* dword 0 */
282 u8 rsvd[2]; /* dword 0 */
4c60005f
KA		 283 u8 base_status; /* dword 1 */
284 u8 addl_status; /* dword 1 */
652bf646 285 u8 rsvd1[2]; /* dword 1 */
6b7c5b94
SP		 286 u32 response_length; /* dword 2 */
287 u32 actual_resp_len; /* dword 3 */
288};
289
290struct phys_addr {
291 u32 lo;
292 u32 hi;
293};
294
295/**************************
296 * BE Command definitions *
297 **************************/
298
299/* Pseudo amap definition in which each bit of the actual structure is defined
300 * as a byte: used to calculate offset/shift/mask of each field */
301struct amap_eq_context {
302 u8 cidx[13]; /* dword 0*/
303 u8 rsvd0[3]; /* dword 0*/
304 u8 epidx[13]; /* dword 0*/
305 u8 valid; /* dword 0*/
306 u8 rsvd1; /* dword 0*/
307 u8 size; /* dword 0*/
308 u8 pidx[13]; /* dword 1*/
309 u8 rsvd2[3]; /* dword 1*/
310 u8 pd[10]; /* dword 1*/
311 u8 count[3]; /* dword 1*/
312 u8 solevent; /* dword 1*/
313 u8 stalled; /* dword 1*/
314 u8 armed; /* dword 1*/
315 u8 rsvd3[4]; /* dword 2*/
316 u8 func[8]; /* dword 2*/
317 u8 rsvd4; /* dword 2*/
318 u8 delaymult[10]; /* dword 2*/
319 u8 rsvd5[2]; /* dword 2*/
320 u8 phase[2]; /* dword 2*/
321 u8 nodelay; /* dword 2*/
322 u8 rsvd6[4]; /* dword 2*/
323 u8 rsvd7[32]; /* dword 3*/
324} __packed;
325
326struct be_cmd_req_eq_create {
327 struct be_cmd_req_hdr hdr;
328 u16 num_pages; /* sword */
329 u16 rsvd0; /* sword */
330 u8 context[sizeof(struct amap_eq_context) / 8];
331 struct phys_addr pages[8];
332} __packed;
333
334struct be_cmd_resp_eq_create {
335 struct be_cmd_resp_hdr resp_hdr;
336 u16 eq_id; /* sword */
f2f781a7 337 u16 msix_idx; /* available only in v2 */
6b7c5b94
SP		 338} __packed;
339
340/******************** Mac query ***************************/
341enum {
342 MAC_ADDRESS_TYPE_STORAGE = 0x0,
343 MAC_ADDRESS_TYPE_NETWORK = 0x1,
344 MAC_ADDRESS_TYPE_PD = 0x2,
345 MAC_ADDRESS_TYPE_MANAGEMENT = 0x3
346};
347
348struct mac_addr {
349 u16 size_of_struct;
350 u8 addr[ETH_ALEN];
351} __packed;
352
353struct be_cmd_req_mac_query {
354 struct be_cmd_req_hdr hdr;
355 u8 type;
356 u8 permanent;
357 u16 if_id;
590c391d 358 u32 pmac_id;
6b7c5b94
SP		 359} __packed;
360
361struct be_cmd_resp_mac_query {
362 struct be_cmd_resp_hdr hdr;
363 struct mac_addr mac;
364};
365
366/******************** PMac Add ***************************/
367struct be_cmd_req_pmac_add {
368 struct be_cmd_req_hdr hdr;
369 u32 if_id;
370 u8 mac_address[ETH_ALEN];
371 u8 rsvd0[2];
372} __packed;
373
374struct be_cmd_resp_pmac_add {
375 struct be_cmd_resp_hdr hdr;
376 u32 pmac_id;
377};
378
379/******************** PMac Del ***************************/
380struct be_cmd_req_pmac_del {
381 struct be_cmd_req_hdr hdr;
382 u32 if_id;
383 u32 pmac_id;
384};
385
386/******************** Create CQ ***************************/
387/* Pseudo amap definition in which each bit of the actual structure is defined
388 * as a byte: used to calculate offset/shift/mask of each field */
fe6d2a38 389struct amap_cq_context_be {
6b7c5b94
SP		 390 u8 cidx[11]; /* dword 0*/
391 u8 rsvd0; /* dword 0*/
392 u8 coalescwm[2]; /* dword 0*/
393 u8 nodelay; /* dword 0*/
394 u8 epidx[11]; /* dword 0*/
395 u8 rsvd1; /* dword 0*/
396 u8 count[2]; /* dword 0*/
397 u8 valid; /* dword 0*/
398 u8 solevent; /* dword 0*/
399 u8 eventable; /* dword 0*/
400 u8 pidx[11]; /* dword 1*/
401 u8 rsvd2; /* dword 1*/
402 u8 pd[10]; /* dword 1*/
403 u8 eqid[8]; /* dword 1*/
404 u8 stalled; /* dword 1*/
405 u8 armed; /* dword 1*/
406 u8 rsvd3[4]; /* dword 2*/
407 u8 func[8]; /* dword 2*/
408 u8 rsvd4[20]; /* dword 2*/
409 u8 rsvd5[32]; /* dword 3*/
410} __packed;
411
bbdc42f8 412struct amap_cq_context_v2 {
fe6d2a38
SP		 413 u8 rsvd0[12]; /* dword 0*/
414 u8 coalescwm[2]; /* dword 0*/
415 u8 nodelay; /* dword 0*/
416 u8 rsvd1[12]; /* dword 0*/
417 u8 count[2]; /* dword 0*/
418 u8 valid; /* dword 0*/
419 u8 rsvd2; /* dword 0*/
420 u8 eventable; /* dword 0*/
421 u8 eqid[16]; /* dword 1*/
422 u8 rsvd3[15]; /* dword 1*/
423 u8 armed; /* dword 1*/
424 u8 rsvd4[32]; /* dword 2*/
425 u8 rsvd5[32]; /* dword 3*/
426} __packed;
427
6b7c5b94
SP		 428struct be_cmd_req_cq_create {
429 struct be_cmd_req_hdr hdr;
430 u16 num_pages;
fe6d2a38
SP		 431 u8 page_size;
432 u8 rsvd0;
433 u8 context[sizeof(struct amap_cq_context_be) / 8];
6b7c5b94
SP		 434 struct phys_addr pages[8];
435} __packed;
436
fe6d2a38 437
6b7c5b94
SP		 438struct be_cmd_resp_cq_create {
439 struct be_cmd_resp_hdr hdr;
440 u16 cq_id;
441 u16 rsvd0;
442} __packed;
443
311fddc7
SK		 444struct be_cmd_req_get_fat {
445 struct be_cmd_req_hdr hdr;
446 u32 fat_operation;
447 u32 read_log_offset;
448 u32 read_log_length;
449 u32 data_buffer_size;
450 u32 data_buffer[1];
451} __packed;
452
453struct be_cmd_resp_get_fat {
454 struct be_cmd_resp_hdr hdr;
455 u32 log_size;
456 u32 read_log_length;
457 u32 rsvd[2];
458 u32 data_buffer[1];
459} __packed;
460
461
5fb379ee
SP		 462/******************** Create MCCQ ***************************/
463/* Pseudo amap definition in which each bit of the actual structure is defined
464 * as a byte: used to calculate offset/shift/mask of each field */
fe6d2a38 465struct amap_mcc_context_be {
5fb379ee
SP		 466 u8 con_index[14];
467 u8 rsvd0[2];
468 u8 ring_size[4];
469 u8 fetch_wrb;
470 u8 fetch_r2t;
471 u8 cq_id[10];
472 u8 prod_index[14];
473 u8 fid[8];
474 u8 pdid[9];
475 u8 valid;
476 u8 rsvd1[32];
477 u8 rsvd2[32];
478} __packed;
479
666d39c7 480struct amap_mcc_context_v1 {
fe6d2a38
SP		 481 u8 async_cq_id[16];
482 u8 ring_size[4];
483 u8 rsvd0[12];
484 u8 rsvd1[31];
485 u8 valid;
486 u8 async_cq_valid[1];
487 u8 rsvd2[31];
488 u8 rsvd3[32];
489} __packed;
490
5fb379ee 491struct be_cmd_req_mcc_create {
34b1ef04
SK		 492 struct be_cmd_req_hdr hdr;
493 u16 num_pages;
494 u16 cq_id;
495 u8 context[sizeof(struct amap_mcc_context_be) / 8];
496 struct phys_addr pages[8];
497} __packed;
498
499struct be_cmd_req_mcc_ext_create {
5fb379ee
SP		 500 struct be_cmd_req_hdr hdr;
501 u16 num_pages;
fe6d2a38 502 u16 cq_id;
cc4ce020 503 u32 async_event_bitmap[1];
666d39c7 504 u8 context[sizeof(struct amap_mcc_context_v1) / 8];
5fb379ee
SP		 505 struct phys_addr pages[8];
506} __packed;
507
508struct be_cmd_resp_mcc_create {
509 struct be_cmd_resp_hdr hdr;
510 u16 id;
511 u16 rsvd0;
512} __packed;
513
6b7c5b94
SP		 514/******************** Create TxQ ***************************/
515#define BE_ETH_TX_RING_TYPE_STANDARD 2
516#define BE_ULP1_NUM 1
517
6b7c5b94
SP		 518struct be_cmd_req_eth_tx_create {
519 struct be_cmd_req_hdr hdr;
520 u8 num_pages;
521 u8 ulp_num;
94d73aaa
VV		 522 u16 type;
523 u16 if_id;
524 u8 queue_size;
525 u8 rsvd0;
526 u32 rsvd1;
527 u16 cq_id;
528 u16 rsvd2;
529 u32 rsvd3[13];
6b7c5b94
SP		 530 struct phys_addr pages[8];
531} __packed;
532
533struct be_cmd_resp_eth_tx_create {
534 struct be_cmd_resp_hdr hdr;
535 u16 cid;
94d73aaa
VV		 536 u16 rid;
537 u32 db_offset;
538 u32 rsvd0[4];
6b7c5b94
SP		 539} __packed;
540
541/******************** Create RxQ ***************************/
542struct be_cmd_req_eth_rx_create {
543 struct be_cmd_req_hdr hdr;
544 u16 cq_id;
545 u8 frag_size;
546 u8 num_pages;
547 struct phys_addr pages[2];
548 u32 interface_id;
549 u16 max_frame_size;
550 u16 rsvd0;
551 u32 rss_queue;
552} __packed;
553
554struct be_cmd_resp_eth_rx_create {
555 struct be_cmd_resp_hdr hdr;
556 u16 id;
3abcdeda 557 u8 rss_id;
6b7c5b94
SP		 558 u8 rsvd0;
559} __packed;
560
561/******************** Q Destroy ***************************/
562/* Type of Queue to be destroyed */
563enum {
564 QTYPE_EQ = 1,
565 QTYPE_CQ,
566 QTYPE_TXQ,
5fb379ee
SP		 567 QTYPE_RXQ,
568 QTYPE_MCCQ
6b7c5b94
SP		 569};
570
571struct be_cmd_req_q_destroy {
572 struct be_cmd_req_hdr hdr;
573 u16 id;
574 u16 bypass_flush; /* valid only for rx q destroy */
575} __packed;
576
577/************ I/f Create (it's actually I/f Config Create)**********/
578
579/* Capability flags for the i/f */
580enum be_if_flags {
581 BE_IF_FLAGS_RSS = 0x4,
582 BE_IF_FLAGS_PROMISCUOUS = 0x8,
583 BE_IF_FLAGS_BROADCAST = 0x10,
584 BE_IF_FLAGS_UNTAGGED = 0x20,
585 BE_IF_FLAGS_ULP = 0x40,
586 BE_IF_FLAGS_VLAN_PROMISCUOUS = 0x80,
587 BE_IF_FLAGS_VLAN = 0x100,
588 BE_IF_FLAGS_MCAST_PROMISCUOUS = 0x200,
589 BE_IF_FLAGS_PASS_L2_ERRORS = 0x400,
f21b538c 590 BE_IF_FLAGS_PASS_L3L4_ERRORS = 0x800,
71bb8bd0
VV		 591 BE_IF_FLAGS_MULTICAST = 0x1000,
592 BE_IF_FLAGS_DEFQ_RSS = 0x1000000
6b7c5b94
SP		 593};
594
3da988c9
SB		 595#define BE_IF_CAP_FLAGS_WANT (BE_IF_FLAGS_RSS | BE_IF_FLAGS_PROMISCUOUS |\
596 BE_IF_FLAGS_BROADCAST | BE_IF_FLAGS_VLAN_PROMISCUOUS |\
597 BE_IF_FLAGS_VLAN | BE_IF_FLAGS_MCAST_PROMISCUOUS |\
598 BE_IF_FLAGS_PASS_L3L4_ERRORS | BE_IF_FLAGS_MULTICAST |\
71bb8bd0 599 BE_IF_FLAGS_UNTAGGED | BE_IF_FLAGS_DEFQ_RSS)
3da988c9 600
ac34b743
SP		 601#define BE_IF_FLAGS_ALL_PROMISCUOUS (BE_IF_FLAGS_PROMISCUOUS | \
602 BE_IF_FLAGS_VLAN_PROMISCUOUS |\
603 BE_IF_FLAGS_MCAST_PROMISCUOUS)
604
6b7c5b94
SP		 605/* An RX interface is an object with one or more MAC addresses and
606 * filtering capabilities. */
607struct be_cmd_req_if_create {
608 struct be_cmd_req_hdr hdr;
af901ca1 609 u32 version; /* ignore currently */
6b7c5b94
SP		 610 u32 capability_flags;
611 u32 enable_flags;
612 u8 mac_addr[ETH_ALEN];
613 u8 rsvd0;
614 u8 pmac_invalid; /* if set, don't attach the mac addr to the i/f */
615 u32 vlan_tag; /* not used currently */
616} __packed;
617
618struct be_cmd_resp_if_create {
619 struct be_cmd_resp_hdr hdr;
620 u32 interface_id;
621 u32 pmac_id;
622};
623
624/****** I/f Destroy(it's actually I/f Config Destroy )**********/
625struct be_cmd_req_if_destroy {
626 struct be_cmd_req_hdr hdr;
627 u32 interface_id;
628};
629
630/*************** HW Stats Get **********************************/
89a88ab8 631struct be_port_rxf_stats_v0 {
6b7c5b94
SP		 632 u32 rx_bytes_lsd; /* dword 0*/
633 u32 rx_bytes_msd; /* dword 1*/
634 u32 rx_total_frames; /* dword 2*/
635 u32 rx_unicast_frames; /* dword 3*/
636 u32 rx_multicast_frames; /* dword 4*/
637 u32 rx_broadcast_frames; /* dword 5*/
638 u32 rx_crc_errors; /* dword 6*/
639 u32 rx_alignment_symbol_errors; /* dword 7*/
640 u32 rx_pause_frames; /* dword 8*/
641 u32 rx_control_frames; /* dword 9*/
642 u32 rx_in_range_errors; /* dword 10*/
643 u32 rx_out_range_errors; /* dword 11*/
644 u32 rx_frame_too_long; /* dword 12*/
18fb06a1
SR		 645 u32 rx_address_filtered; /* dword 13*/
646 u32 rx_vlan_filtered; /* dword 14*/
6b7c5b94
SP		 647 u32 rx_dropped_too_small; /* dword 15*/
648 u32 rx_dropped_too_short; /* dword 16*/
649 u32 rx_dropped_header_too_small; /* dword 17*/
650 u32 rx_dropped_tcp_length; /* dword 18*/
651 u32 rx_dropped_runt; /* dword 19*/
652 u32 rx_64_byte_packets; /* dword 20*/
653 u32 rx_65_127_byte_packets; /* dword 21*/
654 u32 rx_128_256_byte_packets; /* dword 22*/
655 u32 rx_256_511_byte_packets; /* dword 23*/
656 u32 rx_512_1023_byte_packets; /* dword 24*/
657 u32 rx_1024_1518_byte_packets; /* dword 25*/
658 u32 rx_1519_2047_byte_packets; /* dword 26*/
659 u32 rx_2048_4095_byte_packets; /* dword 27*/
660 u32 rx_4096_8191_byte_packets; /* dword 28*/
661 u32 rx_8192_9216_byte_packets; /* dword 29*/
662 u32 rx_ip_checksum_errs; /* dword 30*/
663 u32 rx_tcp_checksum_errs; /* dword 31*/
664 u32 rx_udp_checksum_errs; /* dword 32*/
665 u32 rx_non_rss_packets; /* dword 33*/
666 u32 rx_ipv4_packets; /* dword 34*/
667 u32 rx_ipv6_packets; /* dword 35*/
668 u32 rx_ipv4_bytes_lsd; /* dword 36*/
669 u32 rx_ipv4_bytes_msd; /* dword 37*/
670 u32 rx_ipv6_bytes_lsd; /* dword 38*/
671 u32 rx_ipv6_bytes_msd; /* dword 39*/
672 u32 rx_chute1_packets; /* dword 40*/
673 u32 rx_chute2_packets; /* dword 41*/
674 u32 rx_chute3_packets; /* dword 42*/
675 u32 rx_management_packets; /* dword 43*/
676 u32 rx_switched_unicast_packets; /* dword 44*/
677 u32 rx_switched_multicast_packets; /* dword 45*/
678 u32 rx_switched_broadcast_packets; /* dword 46*/
679 u32 tx_bytes_lsd; /* dword 47*/
680 u32 tx_bytes_msd; /* dword 48*/
681 u32 tx_unicastframes; /* dword 49*/
682 u32 tx_multicastframes; /* dword 50*/
683 u32 tx_broadcastframes; /* dword 51*/
684 u32 tx_pauseframes; /* dword 52*/
685 u32 tx_controlframes; /* dword 53*/
686 u32 tx_64_byte_packets; /* dword 54*/
687 u32 tx_65_127_byte_packets; /* dword 55*/
688 u32 tx_128_256_byte_packets; /* dword 56*/
689 u32 tx_256_511_byte_packets; /* dword 57*/
690 u32 tx_512_1023_byte_packets; /* dword 58*/
691 u32 tx_1024_1518_byte_packets; /* dword 59*/
692 u32 tx_1519_2047_byte_packets; /* dword 60*/
693 u32 tx_2048_4095_byte_packets; /* dword 61*/
694 u32 tx_4096_8191_byte_packets; /* dword 62*/
695 u32 tx_8192_9216_byte_packets; /* dword 63*/
696 u32 rx_fifo_overflow; /* dword 64*/
697 u32 rx_input_fifo_overflow; /* dword 65*/
698};
699
89a88ab8
AK		 700struct be_rxf_stats_v0 {
701 struct be_port_rxf_stats_v0 port[2];
6b7c5b94
SP		 702 u32 rx_drops_no_pbuf; /* dword 132*/
703 u32 rx_drops_no_txpb; /* dword 133*/
704 u32 rx_drops_no_erx_descr; /* dword 134*/
705 u32 rx_drops_no_tpre_descr; /* dword 135*/
706 u32 management_rx_port_packets; /* dword 136*/
707 u32 management_rx_port_bytes; /* dword 137*/
708 u32 management_rx_port_pause_frames; /* dword 138*/
709 u32 management_rx_port_errors; /* dword 139*/
710 u32 management_tx_port_packets; /* dword 140*/
711 u32 management_tx_port_bytes; /* dword 141*/
712 u32 management_tx_port_pause; /* dword 142*/
713 u32 management_rx_port_rxfifo_overflow; /* dword 143*/
714 u32 rx_drops_too_many_frags; /* dword 144*/
715 u32 rx_drops_invalid_ring; /* dword 145*/
716 u32 forwarded_packets; /* dword 146*/
717 u32 rx_drops_mtu; /* dword 147*/
f6c4bf3e
AK		 718 u32 rsvd0[7];
719 u32 port0_jabber_events;
720 u32 port1_jabber_events;
721 u32 rsvd1[6];
6b7c5b94
SP		 722};
723
89a88ab8 724struct be_erx_stats_v0 {
6b7c5b94 725 u32 rx_drops_no_fragments[44]; /* dwordS 0 to 43*/
89a88ab8 726 u32 rsvd[4];
6b7c5b94
SP		 727};
728
f6c4bf3e
AK		 729struct be_pmem_stats {
730 u32 eth_red_drops;
89a88ab8 731 u32 rsvd[5];
f6c4bf3e
AK		 732};
733
89a88ab8
AK		 734struct be_hw_stats_v0 {
735 struct be_rxf_stats_v0 rxf;
6b7c5b94 736 u32 rsvd[48];
89a88ab8 737 struct be_erx_stats_v0 erx;
f6c4bf3e 738 struct be_pmem_stats pmem;
6b7c5b94
SP		 739};
740
89a88ab8 741struct be_cmd_req_get_stats_v0 {
6b7c5b94 742 struct be_cmd_req_hdr hdr;
89a88ab8 743 u8 rsvd[sizeof(struct be_hw_stats_v0)];
6b7c5b94
SP		 744};
745
89a88ab8 746struct be_cmd_resp_get_stats_v0 {
6b7c5b94 747 struct be_cmd_resp_hdr hdr;
89a88ab8 748 struct be_hw_stats_v0 hw_stats;
6b7c5b94
SP		 749};
750
ac124ff9 751struct lancer_pport_stats {
005d5696
SX		 752 u32 tx_packets_lo;
753 u32 tx_packets_hi;
754 u32 tx_unicast_packets_lo;
755 u32 tx_unicast_packets_hi;
756 u32 tx_multicast_packets_lo;
757 u32 tx_multicast_packets_hi;
758 u32 tx_broadcast_packets_lo;
759 u32 tx_broadcast_packets_hi;
760 u32 tx_bytes_lo;
761 u32 tx_bytes_hi;
762 u32 tx_unicast_bytes_lo;
763 u32 tx_unicast_bytes_hi;
764 u32 tx_multicast_bytes_lo;
765 u32 tx_multicast_bytes_hi;
766 u32 tx_broadcast_bytes_lo;
767 u32 tx_broadcast_bytes_hi;
768 u32 tx_discards_lo;
769 u32 tx_discards_hi;
770 u32 tx_errors_lo;
771 u32 tx_errors_hi;
772 u32 tx_pause_frames_lo;
773 u32 tx_pause_frames_hi;
774 u32 tx_pause_on_frames_lo;
775 u32 tx_pause_on_frames_hi;
776 u32 tx_pause_off_frames_lo;
777 u32 tx_pause_off_frames_hi;
778 u32 tx_internal_mac_errors_lo;
779 u32 tx_internal_mac_errors_hi;
780 u32 tx_control_frames_lo;
781 u32 tx_control_frames_hi;
782 u32 tx_packets_64_bytes_lo;
783 u32 tx_packets_64_bytes_hi;
784 u32 tx_packets_65_to_127_bytes_lo;
785 u32 tx_packets_65_to_127_bytes_hi;
786 u32 tx_packets_128_to_255_bytes_lo;
787 u32 tx_packets_128_to_255_bytes_hi;
788 u32 tx_packets_256_to_511_bytes_lo;
789 u32 tx_packets_256_to_511_bytes_hi;
790 u32 tx_packets_512_to_1023_bytes_lo;
791 u32 tx_packets_512_to_1023_bytes_hi;
792 u32 tx_packets_1024_to_1518_bytes_lo;
793 u32 tx_packets_1024_to_1518_bytes_hi;
794 u32 tx_packets_1519_to_2047_bytes_lo;
795 u32 tx_packets_1519_to_2047_bytes_hi;
796 u32 tx_packets_2048_to_4095_bytes_lo;
797 u32 tx_packets_2048_to_4095_bytes_hi;
798 u32 tx_packets_4096_to_8191_bytes_lo;
799 u32 tx_packets_4096_to_8191_bytes_hi;
800 u32 tx_packets_8192_to_9216_bytes_lo;
801 u32 tx_packets_8192_to_9216_bytes_hi;
802 u32 tx_lso_packets_lo;
803 u32 tx_lso_packets_hi;
804 u32 rx_packets_lo;
805 u32 rx_packets_hi;
806 u32 rx_unicast_packets_lo;
807 u32 rx_unicast_packets_hi;
808 u32 rx_multicast_packets_lo;
809 u32 rx_multicast_packets_hi;
810 u32 rx_broadcast_packets_lo;
811 u32 rx_broadcast_packets_hi;
812 u32 rx_bytes_lo;
813 u32 rx_bytes_hi;
814 u32 rx_unicast_bytes_lo;
815 u32 rx_unicast_bytes_hi;
816 u32 rx_multicast_bytes_lo;
817 u32 rx_multicast_bytes_hi;
818 u32 rx_broadcast_bytes_lo;
819 u32 rx_broadcast_bytes_hi;
820 u32 rx_unknown_protos;
821 u32 rsvd_69; /* Word 69 is reserved */
822 u32 rx_discards_lo;
823 u32 rx_discards_hi;
824 u32 rx_errors_lo;
825 u32 rx_errors_hi;
826 u32 rx_crc_errors_lo;
827 u32 rx_crc_errors_hi;
828 u32 rx_alignment_errors_lo;
829 u32 rx_alignment_errors_hi;
830 u32 rx_symbol_errors_lo;
831 u32 rx_symbol_errors_hi;
832 u32 rx_pause_frames_lo;
833 u32 rx_pause_frames_hi;
834 u32 rx_pause_on_frames_lo;
835 u32 rx_pause_on_frames_hi;
836 u32 rx_pause_off_frames_lo;
837 u32 rx_pause_off_frames_hi;
838 u32 rx_frames_too_long_lo;
839 u32 rx_frames_too_long_hi;
840 u32 rx_internal_mac_errors_lo;
841 u32 rx_internal_mac_errors_hi;
842 u32 rx_undersize_packets;
843 u32 rx_oversize_packets;
844 u32 rx_fragment_packets;
845 u32 rx_jabbers;
846 u32 rx_control_frames_lo;
847 u32 rx_control_frames_hi;
848 u32 rx_control_frames_unknown_opcode_lo;
849 u32 rx_control_frames_unknown_opcode_hi;
850 u32 rx_in_range_errors;
851 u32 rx_out_of_range_errors;
18fb06a1
SR		 852 u32 rx_address_filtered;
853 u32 rx_vlan_filtered;
005d5696
SX		 854 u32 rx_dropped_too_small;
855 u32 rx_dropped_too_short;
856 u32 rx_dropped_header_too_small;
857 u32 rx_dropped_invalid_tcp_length;
858 u32 rx_dropped_runt;
859 u32 rx_ip_checksum_errors;
860 u32 rx_tcp_checksum_errors;
861 u32 rx_udp_checksum_errors;
862 u32 rx_non_rss_packets;
863 u32 rsvd_111;
864 u32 rx_ipv4_packets_lo;
865 u32 rx_ipv4_packets_hi;
866 u32 rx_ipv6_packets_lo;
867 u32 rx_ipv6_packets_hi;
868 u32 rx_ipv4_bytes_lo;
869 u32 rx_ipv4_bytes_hi;
870 u32 rx_ipv6_bytes_lo;
871 u32 rx_ipv6_bytes_hi;
872 u32 rx_nic_packets_lo;
873 u32 rx_nic_packets_hi;
874 u32 rx_tcp_packets_lo;
875 u32 rx_tcp_packets_hi;
876 u32 rx_iscsi_packets_lo;
877 u32 rx_iscsi_packets_hi;
878 u32 rx_management_packets_lo;
879 u32 rx_management_packets_hi;
880 u32 rx_switched_unicast_packets_lo;
881 u32 rx_switched_unicast_packets_hi;
882 u32 rx_switched_multicast_packets_lo;
883 u32 rx_switched_multicast_packets_hi;
884 u32 rx_switched_broadcast_packets_lo;
885 u32 rx_switched_broadcast_packets_hi;
886 u32 num_forwards_lo;
887 u32 num_forwards_hi;
888 u32 rx_fifo_overflow;
889 u32 rx_input_fifo_overflow;
890 u32 rx_drops_too_many_frags_lo;
891 u32 rx_drops_too_many_frags_hi;
892 u32 rx_drops_invalid_queue;
893 u32 rsvd_141;
894 u32 rx_drops_mtu_lo;
895 u32 rx_drops_mtu_hi;
896 u32 rx_packets_64_bytes_lo;
897 u32 rx_packets_64_bytes_hi;
898 u32 rx_packets_65_to_127_bytes_lo;
899 u32 rx_packets_65_to_127_bytes_hi;
900 u32 rx_packets_128_to_255_bytes_lo;
901 u32 rx_packets_128_to_255_bytes_hi;
902 u32 rx_packets_256_to_511_bytes_lo;
903 u32 rx_packets_256_to_511_bytes_hi;
904 u32 rx_packets_512_to_1023_bytes_lo;
905 u32 rx_packets_512_to_1023_bytes_hi;
906 u32 rx_packets_1024_to_1518_bytes_lo;
907 u32 rx_packets_1024_to_1518_bytes_hi;
908 u32 rx_packets_1519_to_2047_bytes_lo;
909 u32 rx_packets_1519_to_2047_bytes_hi;
910 u32 rx_packets_2048_to_4095_bytes_lo;
911 u32 rx_packets_2048_to_4095_bytes_hi;
912 u32 rx_packets_4096_to_8191_bytes_lo;
913 u32 rx_packets_4096_to_8191_bytes_hi;
914 u32 rx_packets_8192_to_9216_bytes_lo;
915 u32 rx_packets_8192_to_9216_bytes_hi;
916};
917
918struct pport_stats_params {
919 u16 pport_num;
920 u8 rsvd;
921 u8 reset_stats;
922};
923
924struct lancer_cmd_req_pport_stats {
925 struct be_cmd_req_hdr hdr;
926 union {
927 struct pport_stats_params params;
ac124ff9 928 u8 rsvd[sizeof(struct lancer_pport_stats)];
005d5696
SX		 929 } cmd_params;
930};
931
932struct lancer_cmd_resp_pport_stats {
933 struct be_cmd_resp_hdr hdr;
ac124ff9 934 struct lancer_pport_stats pport_stats;
005d5696
SX		 935};
936
ac124ff9 937static inline struct lancer_pport_stats*
005d5696
SX		 938 pport_stats_from_cmd(struct be_adapter *adapter)
939{
940 struct lancer_cmd_resp_pport_stats *cmd = adapter->stats_cmd.va;
941 return &cmd->pport_stats;
942}
943
609ff3bb
AK		 944struct be_cmd_req_get_cntl_addnl_attribs {
945 struct be_cmd_req_hdr hdr;
946 u8 rsvd[8];
947};
948
949struct be_cmd_resp_get_cntl_addnl_attribs {
950 struct be_cmd_resp_hdr hdr;
951 u16 ipl_file_number;
952 u8 ipl_file_version;
953 u8 rsvd0;
954 u8 on_die_temperature; /* in degrees centigrade*/
955 u8 rsvd1[3];
956};
957
6b7c5b94
SP		 958struct be_cmd_req_vlan_config {
959 struct be_cmd_req_hdr hdr;
960 u8 interface_id;
961 u8 promiscuous;
962 u8 untagged;
963 u8 num_vlan;
964 u16 normal_vlan[64];
965} __packed;
966
5b8821b7 967/******************* RX FILTER ******************************/
e7b909a6 968#define BE_MAX_MC 64 /* set mcast promisc if > 64 */
6b7c5b94
SP		 969struct macaddr {
970 u8 byte[ETH_ALEN];
971};
972
ecd0bf0f
PR		 973struct be_cmd_req_rx_filter {
974 struct be_cmd_req_hdr hdr;
975 u32 global_flags_mask;
976 u32 global_flags;
977 u32 if_flags_mask;
978 u32 if_flags;
979 u32 if_id;
5b8821b7
SP		 980 u32 mcast_num;
981 struct macaddr mcast_mac[BE_MAX_MC];
ecd0bf0f
PR		 982};
983
6b7c5b94
SP		 984/******************** Link Status Query *******************/
985struct be_cmd_req_link_status {
986 struct be_cmd_req_hdr hdr;
987 u32 rsvd;
988};
989
6b7c5b94
SP		 990enum {
991 PHY_LINK_DUPLEX_NONE = 0x0,
992 PHY_LINK_DUPLEX_HALF = 0x1,
993 PHY_LINK_DUPLEX_FULL = 0x2
994};
995
996enum {
997 PHY_LINK_SPEED_ZERO = 0x0, /* => No link */
998 PHY_LINK_SPEED_10MBPS = 0x1,
999 PHY_LINK_SPEED_100MBPS = 0x2,
1000 PHY_LINK_SPEED_1GBPS = 0x3,
b971f847
VV		 1001 PHY_LINK_SPEED_10GBPS = 0x4,
1002 PHY_LINK_SPEED_20GBPS = 0x5,
1003 PHY_LINK_SPEED_25GBPS = 0x6,
1004 PHY_LINK_SPEED_40GBPS = 0x7
6b7c5b94
SP		 1005};
1006
1007struct be_cmd_resp_link_status {
1008 struct be_cmd_resp_hdr hdr;
1009 u8 physical_port;
1010 u8 mac_duplex;
1011 u8 mac_speed;
1012 u8 mac_fault;
1013 u8 mgmt_mac_duplex;
1014 u8 mgmt_mac_speed;
0388f251 1015 u16 link_speed;
b236916a
AK		 1016 u8 logical_link_status;
1017 u8 rsvd1[3];
6b7c5b94
SP		 1018} __packed;
1019
0388f251
SB		 1020/******************** Port Identification ***************************/
1021/* Identifies the type of port attached to NIC */
1022struct be_cmd_req_port_type {
1023 struct be_cmd_req_hdr hdr;
72d7e2bf
SR		 1024 __le32 page_num;
1025 __le32 port;
0388f251
SB		 1026};
1027
1028enum {
1029 TR_PAGE_A0 = 0xa0,
1030 TR_PAGE_A2 = 0xa2
1031};
1032
6809cee0
RN		 1033/* From SFF-8436 QSFP+ spec */
1034#define QSFP_PLUS_CABLE_TYPE_OFFSET 0x83
1035#define QSFP_PLUS_CR4_CABLE 0x8
1036#define QSFP_PLUS_SR4_CABLE 0x4
1037#define QSFP_PLUS_LR4_CABLE 0x2
1038
e36edd9d 1039/* From SFF-8472 spec */
6809cee0
RN		 1040#define SFP_PLUS_SFF_8472_COMP 0x5E
1041#define SFP_PLUS_CABLE_TYPE_OFFSET 0x8
1042#define SFP_PLUS_COPPER_CABLE 0x4
21252377
VV		 1043#define SFP_VENDOR_NAME_OFFSET 0x14
1044#define SFP_VENDOR_PN_OFFSET 0x28
e36edd9d
ML		 1045
1046#define PAGE_DATA_LEN 256
0388f251
SB		 1047struct be_cmd_resp_port_type {
1048 struct be_cmd_resp_hdr hdr;
1049 u32 page_num;
1050 u32 port;
e36edd9d 1051 u8 page_data[PAGE_DATA_LEN];
0388f251
SB		 1052};
1053
6b7c5b94 1054/******************** Get FW Version *******************/
6b7c5b94
SP		 1055struct be_cmd_req_get_fw_version {
1056 struct be_cmd_req_hdr hdr;
1057 u8 rsvd0[FW_VER_LEN];
1058 u8 rsvd1[FW_VER_LEN];
1059} __packed;
1060
1061struct be_cmd_resp_get_fw_version {
1062 struct be_cmd_resp_hdr hdr;
1063 u8 firmware_version_string[FW_VER_LEN];
1064 u8 fw_on_flash_version_string[FW_VER_LEN];
1065} __packed;
1066
1067/******************** Set Flow Contrl *******************/
1068struct be_cmd_req_set_flow_control {
1069 struct be_cmd_req_hdr hdr;
1070 u16 tx_flow_control;
1071 u16 rx_flow_control;
1072} __packed;
1073
1074/******************** Get Flow Contrl *******************/
1075struct be_cmd_req_get_flow_control {
1076 struct be_cmd_req_hdr hdr;
1077 u32 rsvd;
1078};
1079
1080struct be_cmd_resp_get_flow_control {
1081 struct be_cmd_resp_hdr hdr;
1082 u16 tx_flow_control;
1083 u16 rx_flow_control;
1084} __packed;
1085
1086/******************** Modify EQ Delay *******************/
2632bafd
SP		 1087struct be_set_eqd {
1088 u32 eq_id;
1089 u32 phase;
1090 u32 delay_multiplier;
1091};
1092
6b7c5b94
SP		 1093struct be_cmd_req_modify_eq_delay {
1094 struct be_cmd_req_hdr hdr;
1095 u32 num_eq;
2632bafd 1096 struct be_set_eqd set_eqd[MAX_EVT_QS];
6b7c5b94
SP		 1097} __packed;
1098
6b7c5b94 1099/******************** Get FW Config *******************/
752961a1
SP		 1100/* The HW can come up in either of the following multi-channel modes
1101 * based on the skew/IPL.
1102 */
045508a8 1103#define RDMA_ENABLED 0x4
66064dbc 1104#define QNQ_MODE 0x400
752961a1
SP		 1105#define VNIC_MODE 0x20000
1106#define UMC_ENABLED 0x1000000
6b7c5b94
SP		 1107struct be_cmd_req_query_fw_cfg {
1108 struct be_cmd_req_hdr hdr;
3abcdeda 1109 u32 rsvd[31];
6b7c5b94
SP		 1110};
1111
5d3acd0d
VV		 1112/* ASIC revisions */
1113#define ASIC_REV_B0 0x10
81a9e226 1114#define ASIC_REV_P2 0x11
5d3acd0d 1115
6b7c5b94
SP		 1116struct be_cmd_resp_query_fw_cfg {
1117 struct be_cmd_resp_hdr hdr;
1118 u32 be_config_number;
1119 u32 asic_revision;
1120 u32 phys_port;
3486be29 1121 u32 function_mode;
6b7c5b94 1122 u32 rsvd[26];
3abcdeda
SP		 1123 u32 function_caps;
1124};
1125
73dea398
PR		 1126/******************** RSS Config ****************************************/
1127/* RSS type Input parameters used to compute RX hash
1128 * RSS_ENABLE_IPV4 SRC IPv4, DST IPv4
1129 * RSS_ENABLE_TCP_IPV4 SRC IPv4, DST IPv4, TCP SRC PORT, TCP DST PORT
1130 * RSS_ENABLE_IPV6 SRC IPv6, DST IPv6
1131 * RSS_ENABLE_TCP_IPV6 SRC IPv6, DST IPv6, TCP SRC PORT, TCP DST PORT
1132 * RSS_ENABLE_UDP_IPV4 SRC IPv4, DST IPv4, UDP SRC PORT, UDP DST PORT
1133 * RSS_ENABLE_UDP_IPV6 SRC IPv6, DST IPv6, UDP SRC PORT, UDP DST PORT
1134 *
1135 * When multiple RSS types are enabled, HW picks the best hash policy
1136 * based on the type of the received packet.
1137 */
3abcdeda
SP		 1138#define RSS_ENABLE_NONE 0x0
1139#define RSS_ENABLE_IPV4 0x1
1140#define RSS_ENABLE_TCP_IPV4 0x2
1141#define RSS_ENABLE_IPV6 0x4
1142#define RSS_ENABLE_TCP_IPV6 0x8
d3bd3a5e
PR		 1143#define RSS_ENABLE_UDP_IPV4 0x10
1144#define RSS_ENABLE_UDP_IPV6 0x20
3abcdeda 1145
594ad54a
SR		 1146#define L3_RSS_FLAGS (RXH_IP_DST | RXH_IP_SRC)
1147#define L4_RSS_FLAGS (RXH_L4_B_0_1 | RXH_L4_B_2_3)
1148
3abcdeda
SP		 1149struct be_cmd_req_rss_config {
1150 struct be_cmd_req_hdr hdr;
1151 u32 if_id;
1152 u16 enable_rss;
1153 u16 cpu_table_size_log2;
1154 u32 hash[10];
1155 u8 cpu_table[128];
1156 u8 flush;
1157 u8 rsvd0[3];
6b7c5b94
SP		 1158};
1159
fad9ab2c
SB		 1160/******************** Port Beacon ***************************/
1161
1162#define BEACON_STATE_ENABLED 0x1
1163#define BEACON_STATE_DISABLED 0x0
1164
1165struct be_cmd_req_enable_disable_beacon {
1166 struct be_cmd_req_hdr hdr;
1167 u8 port_num;
1168 u8 beacon_state;
1169 u8 beacon_duration;
1170 u8 status_duration;
1171} __packed;
1172
fad9ab2c
SB		 1173struct be_cmd_req_get_beacon_state {
1174 struct be_cmd_req_hdr hdr;
1175 u8 port_num;
1176 u8 rsvd0;
1177 u16 rsvd1;
1178} __packed;
1179
1180struct be_cmd_resp_get_beacon_state {
1181 struct be_cmd_resp_hdr resp_hdr;
1182 u8 beacon_state;
1183 u8 rsvd0[3];
1184} __packed;
1185
e02cfd96
VV		 1186/* Flashrom related descriptors */
1187#define MAX_FLASH_COMP 32
1188
1189#define OPTYPE_ISCSI_ACTIVE 0
1190#define OPTYPE_REDBOOT 1
1191#define OPTYPE_BIOS 2
1192#define OPTYPE_PXE_BIOS 3
70a7b525 1193#define OPTYPE_OFFSET_SPECIFIED 7
e02cfd96
VV		 1194#define OPTYPE_FCOE_BIOS 8
1195#define OPTYPE_ISCSI_BACKUP 9
1196#define OPTYPE_FCOE_FW_ACTIVE 10
1197#define OPTYPE_FCOE_FW_BACKUP 11
1198#define OPTYPE_NCSI_FW 13
1199#define OPTYPE_REDBOOT_DIR 18
1200#define OPTYPE_REDBOOT_CONFIG 19
1201#define OPTYPE_SH_PHY_FW 21
1202#define OPTYPE_FLASHISM_JUMPVECTOR 22
1203#define OPTYPE_UFI_DIR 23
1204#define OPTYPE_PHY_FW 99
1205
1206#define FLASH_BIOS_IMAGE_MAX_SIZE_g2 262144 /* Max OPTION ROM image sz */
1207#define FLASH_REDBOOT_IMAGE_MAX_SIZE_g2 262144 /* Max Redboot image sz */
1208#define FLASH_IMAGE_MAX_SIZE_g2 1310720 /* Max firmware image size */
1209
1210#define FLASH_NCSI_IMAGE_MAX_SIZE_g3 262144
1211#define FLASH_PHY_FW_IMAGE_MAX_SIZE_g3 262144
1212#define FLASH_BIOS_IMAGE_MAX_SIZE_g3 524288 /* Max OPTION ROM image sz */
1213#define FLASH_REDBOOT_IMAGE_MAX_SIZE_g3 1048576 /* Max Redboot image sz */
1214#define FLASH_IMAGE_MAX_SIZE_g3 2097152 /* Max firmware image size */
1215
1216/* Offsets for components on Flash. */
1217#define FLASH_REDBOOT_START_g2 0
1218#define FLASH_FCoE_BIOS_START_g2 524288
1219#define FLASH_iSCSI_PRIMARY_IMAGE_START_g2 1048576
1220#define FLASH_iSCSI_BACKUP_IMAGE_START_g2 2359296
1221#define FLASH_FCoE_PRIMARY_IMAGE_START_g2 3670016
1222#define FLASH_FCoE_BACKUP_IMAGE_START_g2 4980736
1223#define FLASH_iSCSI_BIOS_START_g2 7340032
1224#define FLASH_PXE_BIOS_START_g2 7864320
1225
1226#define FLASH_REDBOOT_START_g3 262144
1227#define FLASH_PHY_FW_START_g3 1310720
1228#define FLASH_iSCSI_PRIMARY_IMAGE_START_g3 2097152
1229#define FLASH_iSCSI_BACKUP_IMAGE_START_g3 4194304
1230#define FLASH_FCoE_PRIMARY_IMAGE_START_g3 6291456
1231#define FLASH_FCoE_BACKUP_IMAGE_START_g3 8388608
1232#define FLASH_iSCSI_BIOS_START_g3 12582912
1233#define FLASH_PXE_BIOS_START_g3 13107200
1234#define FLASH_FCoE_BIOS_START_g3 13631488
1235#define FLASH_NCSI_START_g3 15990784
1236
1237#define IMAGE_NCSI 16
1238#define IMAGE_OPTION_ROM_PXE 32
1239#define IMAGE_OPTION_ROM_FCoE 33
1240#define IMAGE_OPTION_ROM_ISCSI 34
1241#define IMAGE_FLASHISM_JUMPVECTOR 48
1242#define IMAGE_FIRMWARE_iSCSI 160
1243#define IMAGE_FIRMWARE_FCoE 162
1244#define IMAGE_FIRMWARE_BACKUP_iSCSI 176
1245#define IMAGE_FIRMWARE_BACKUP_FCoE 178
1246#define IMAGE_FIRMWARE_PHY 192
1247#define IMAGE_REDBOOT_DIR 208
1248#define IMAGE_REDBOOT_CONFIG 209
1249#define IMAGE_UFI_DIR 210
1250#define IMAGE_BOOT_CODE 224
1251
1252struct controller_id {
1253 u32 vendor;
1254 u32 device;
1255 u32 subvendor;
1256 u32 subdevice;
1257};
1258
1259struct flash_comp {
1260 unsigned long offset;
1261 int optype;
1262 int size;
1263 int img_type;
1264};
1265
1266struct image_hdr {
1267 u32 imageid;
1268 u32 imageoffset;
1269 u32 imagelength;
1270 u32 image_checksum;
1271 u8 image_version[32];
1272};
1273
1274struct flash_file_hdr_g2 {
1275 u8 sign[32];
1276 u32 cksum;
1277 u32 antidote;
1278 struct controller_id cont_id;
1279 u32 file_len;
1280 u32 chunk_num;
1281 u32 total_chunks;
1282 u32 num_imgs;
1283 u8 build[24];
1284};
1285
5d3acd0d
VV		 1286/* First letter of the build version of the image */
1287#define BLD_STR_UFI_TYPE_BE2 '2'
1288#define BLD_STR_UFI_TYPE_BE3 '3'
1289#define BLD_STR_UFI_TYPE_SH '4'
1290
e02cfd96
VV		 1291struct flash_file_hdr_g3 {
1292 u8 sign[52];
1293 u8 ufi_version[4];
1294 u32 file_len;
1295 u32 cksum;
1296 u32 antidote;
1297 u32 num_imgs;
1298 u8 build[24];
1299 u8 asic_type_rev;
1300 u8 rsvd[31];
1301};
1302
1303struct flash_section_hdr {
1304 u32 format_rev;
1305 u32 cksum;
1306 u32 antidote;
1307 u32 num_images;
1308 u8 id_string[128];
1309 u32 rsvd[4];
1310} __packed;
1311
1312struct flash_section_hdr_g2 {
1313 u32 format_rev;
1314 u32 cksum;
1315 u32 antidote;
1316 u32 build_num;
1317 u8 id_string[128];
1318 u32 rsvd[8];
1319} __packed;
1320
1321struct flash_section_entry {
1322 u32 type;
1323 u32 offset;
1324 u32 pad_size;
1325 u32 image_size;
1326 u32 cksum;
1327 u32 entry_point;
1328 u16 optype;
1329 u16 rsvd0;
1330 u32 rsvd1;
1331 u8 ver_data[32];
1332} __packed;
1333
1334struct flash_section_info {
1335 u8 cookie[32];
1336 struct flash_section_hdr fsec_hdr;
1337 struct flash_section_entry fsec_entry[32];
1338} __packed;
1339
1340struct flash_section_info_g2 {
1341 u8 cookie[32];
1342 struct flash_section_hdr_g2 fsec_hdr;
1343 struct flash_section_entry fsec_entry[32];
1344} __packed;
1345
84517482 1346/****************** Firmware Flash ******************/
e02cfd96
VV		 1347#define FLASHROM_OPER_FLASH 1
1348#define FLASHROM_OPER_SAVE 2
1349#define FLASHROM_OPER_REPORT 4
1350#define FLASHROM_OPER_PHY_FLASH 9
1351#define FLASHROM_OPER_PHY_SAVE 10
1352
84517482
AK		 1353struct flashrom_params {
1354 u32 op_code;
1355 u32 op_type;
1356 u32 data_buf_size;
1357 u32 offset;
84517482
AK		 1358};
1359
1360struct be_cmd_write_flashrom {
1361 struct be_cmd_req_hdr hdr;
1362 struct flashrom_params params;
be716446
PR		 1363 u8 data_buf[32768];
1364 u8 rsvd[4];
1365} __packed;
84517482 1366
be716446
PR		 1367/* cmd to read flash crc */
1368struct be_cmd_read_flash_crc {
1369 struct be_cmd_req_hdr hdr;
1370 struct flashrom_params params;
1371 u8 crc[4];
1372 u8 rsvd[4];
96c9b2e4
VV		 1373} __packed;
1374
485bf569
SN		 1375/**************** Lancer Firmware Flash ************/
1376struct amap_lancer_write_obj_context {
1377 u8 write_length[24];
1378 u8 reserved1[7];
1379 u8 eof;
1380} __packed;
1381
1382struct lancer_cmd_req_write_object {
1383 struct be_cmd_req_hdr hdr;
1384 u8 context[sizeof(struct amap_lancer_write_obj_context) / 8];
1385 u32 write_offset;
1386 u8 object_name[104];
1387 u32 descriptor_count;
1388 u32 buf_len;
1389 u32 addr_low;
1390 u32 addr_high;
1391};
1392
f67ef7ba
PR		 1393#define LANCER_NO_RESET_NEEDED 0x00
1394#define LANCER_FW_RESET_NEEDED 0x02
485bf569
SN		 1395struct lancer_cmd_resp_write_object {
1396 u8 opcode;
1397 u8 subsystem;
1398 u8 rsvd1[2];
1399 u8 status;
1400 u8 additional_status;
1401 u8 rsvd2[2];
1402 u32 resp_len;
1403 u32 actual_resp_len;
1404 u32 actual_write_len;
f67ef7ba
PR		 1405 u8 change_status;
1406 u8 rsvd3[3];
485bf569
SN		 1407};
1408
de49bd5a
PR		 1409/************************ Lancer Read FW info **************/
1410#define LANCER_READ_FILE_CHUNK (32*1024)
1411#define LANCER_READ_FILE_EOF_MASK 0x80000000
1412
1413#define LANCER_FW_DUMP_FILE "/dbg/dump.bin"
af5875bd
PR		 1414#define LANCER_VPD_PF_FILE "/vpd/ntr_pf.vpd"
1415#define LANCER_VPD_VF_FILE "/vpd/ntr_vf.vpd"
de49bd5a
PR		 1416
1417struct lancer_cmd_req_read_object {
1418 struct be_cmd_req_hdr hdr;
1419 u32 desired_read_len;
1420 u32 read_offset;
1421 u8 object_name[104];
1422 u32 descriptor_count;
1423 u32 buf_len;
1424 u32 addr_low;
1425 u32 addr_high;
1426};
1427
1428struct lancer_cmd_resp_read_object {
1429 u8 opcode;
1430 u8 subsystem;
1431 u8 rsvd1[2];
1432 u8 status;
1433 u8 additional_status;
1434 u8 rsvd2[2];
1435 u32 resp_len;
1436 u32 actual_resp_len;
1437 u32 actual_read_len;
1438 u32 eof;
1439};
1440
f0613380
KA		 1441struct lancer_cmd_req_delete_object {
1442 struct be_cmd_req_hdr hdr;
1443 u32 rsvd1;
1444 u32 rsvd2;
1445 u8 object_name[104];
1446};
1447
71d8d1b5
AK		 1448/************************ WOL *******************************/
1449struct be_cmd_req_acpi_wol_magic_config{
1450 struct be_cmd_req_hdr hdr;
1451 u32 rsvd0[145];
1452 u8 magic_mac[6];
1453 u8 rsvd2[2];
1454} __packed;
1455
4762f6ce
AK		 1456struct be_cmd_req_acpi_wol_magic_config_v1 {
1457 struct be_cmd_req_hdr hdr;
1458 u8 rsvd0[2];
1459 u8 query_options;
1460 u8 rsvd1[5];
1461 u32 rsvd2[288];
1462 u8 magic_mac[6];
1463 u8 rsvd3[22];
1464} __packed;
1465
1466struct be_cmd_resp_acpi_wol_magic_config_v1 {
1467 struct be_cmd_resp_hdr hdr;
1468 u8 rsvd0[2];
1469 u8 wol_settings;
1470 u8 rsvd1[5];
1471 u32 rsvd2[295];
1472} __packed;
1473
1474#define BE_GET_WOL_CAP 2
1475
1476#define BE_WOL_CAP 0x1
1477#define BE_PME_D0_CAP 0x8
1478#define BE_PME_D1_CAP 0x10
1479#define BE_PME_D2_CAP 0x20
1480#define BE_PME_D3HOT_CAP 0x40
1481#define BE_PME_D3COLD_CAP 0x80
1482
ff33a6e2
S		 1483/********************** LoopBack test *********************/
1484struct be_cmd_req_loopback_test {
1485 struct be_cmd_req_hdr hdr;
1486 u32 loopback_type;
1487 u32 num_pkts;
1488 u64 pattern;
1489 u32 src_port;
1490 u32 dest_port;
1491 u32 pkt_size;
1492};
1493
1494struct be_cmd_resp_loopback_test {
1495 struct be_cmd_resp_hdr resp_hdr;
1496 u32 status;
1497 u32 num_txfer;
1498 u32 num_rx;
1499 u32 miscomp_off;
1500 u32 ticks_compl;
1501};
1502
fced9999
SB		 1503struct be_cmd_req_set_lmode {
1504 struct be_cmd_req_hdr hdr;
1505 u8 src_port;
1506 u8 dest_port;
1507 u8 loopback_type;
1508 u8 loopback_state;
1509};
1510
ff33a6e2
S		 1511/********************** DDR DMA test *********************/
1512struct be_cmd_req_ddrdma_test {
1513 struct be_cmd_req_hdr hdr;
1514 u64 pattern;
1515 u32 byte_count;
1516 u32 rsvd0;
1517 u8 snd_buff[4096];
1518 u8 rsvd1[4096];
1519};
1520
1521struct be_cmd_resp_ddrdma_test {
1522 struct be_cmd_resp_hdr hdr;
1523 u64 pattern;
1524 u32 byte_cnt;
1525 u32 snd_err;
1526 u8 rsvd0[4096];
1527 u8 rcv_buff[4096];
1528};
1529
368c0ca2
SB		 1530/*********************** SEEPROM Read ***********************/
1531
1532#define BE_READ_SEEPROM_LEN 1024
1533struct be_cmd_req_seeprom_read {
1534 struct be_cmd_req_hdr hdr;
1535 u8 rsvd0[BE_READ_SEEPROM_LEN];
1536};
1537
1538struct be_cmd_resp_seeprom_read {
1539 struct be_cmd_req_hdr hdr;
1540 u8 seeprom_data[BE_READ_SEEPROM_LEN];
1541};
1542
ee3cb629
AK		 1543enum {
1544 PHY_TYPE_CX4_10GB = 0,
1545 PHY_TYPE_XFP_10GB,
1546 PHY_TYPE_SFP_1GB,
1547 PHY_TYPE_SFP_PLUS_10GB,
1548 PHY_TYPE_KR_10GB,
1549 PHY_TYPE_KX4_10GB,
1550 PHY_TYPE_BASET_10GB,
1551 PHY_TYPE_BASET_1GB,
42f11cf2
AK		 1552 PHY_TYPE_BASEX_1GB,
1553 PHY_TYPE_SGMII,
6809cee0
RN		 1554 PHY_TYPE_QSFP,
1555 PHY_TYPE_KR4_40GB,
1556 PHY_TYPE_KR2_20GB,
e02cfd96 1557 PHY_TYPE_TN_8022,
ee3cb629
AK		 1558 PHY_TYPE_DISABLED = 255
1559};
1560
42f11cf2
AK		 1561#define BE_SUPPORTED_SPEED_NONE 0
1562#define BE_SUPPORTED_SPEED_10MBPS 1
1563#define BE_SUPPORTED_SPEED_100MBPS 2
1564#define BE_SUPPORTED_SPEED_1GBPS 4
1565#define BE_SUPPORTED_SPEED_10GBPS 8
d6b7a9b7 1566#define BE_SUPPORTED_SPEED_20GBPS 0x10
6809cee0 1567#define BE_SUPPORTED_SPEED_40GBPS 0x20
42f11cf2
AK		 1568
1569#define BE_AN_EN 0x2
1570#define BE_PAUSE_SYM_EN 0x80
1571
1572/* MAC speed valid values */
1573#define SPEED_DEFAULT 0x0
1574#define SPEED_FORCED_10GB 0x1
1575#define SPEED_FORCED_1GB 0x2
1576#define SPEED_AUTONEG_10GB 0x3
1577#define SPEED_AUTONEG_1GB 0x4
1578#define SPEED_AUTONEG_100MB 0x5
1579#define SPEED_AUTONEG_10GB_1GB 0x6
1580#define SPEED_AUTONEG_10GB_1GB_100MB 0x7
1581#define SPEED_AUTONEG_1GB_100MB 0x8
1582#define SPEED_AUTONEG_10MB 0x9
1583#define SPEED_AUTONEG_1GB_100MB_10MB 0xa
1584#define SPEED_AUTONEG_100MB_10MB 0xb
1585#define SPEED_FORCED_100MB 0xc
1586#define SPEED_FORCED_10MB 0xd
1587
ee3cb629
AK		 1588struct be_cmd_req_get_phy_info {
1589 struct be_cmd_req_hdr hdr;
1590 u8 rsvd0[24];
1591};
306f1348
SP		 1592
1593struct be_phy_info {
ee3cb629
AK		 1594 u16 phy_type;
1595 u16 interface_type;
1596 u32 misc_params;
42f11cf2
AK		 1597 u16 ext_phy_details;
1598 u16 rsvd;
1599 u16 auto_speeds_supported;
1600 u16 fixed_speeds_supported;
1601 u32 future_use[2];
ee3cb629
AK		 1602};
1603
306f1348
SP		 1604struct be_cmd_resp_get_phy_info {
1605 struct be_cmd_req_hdr hdr;
1606 struct be_phy_info phy_info;
1607};
1608
e1d18735
AK		 1609/*********************** Set QOS ***********************/
1610
1611#define BE_QOS_BITS_NIC 1
1612
1613struct be_cmd_req_set_qos {
1614 struct be_cmd_req_hdr hdr;
1615 u32 valid_bits;
1616 u32 max_bps_nic;
1617 u32 rsvd[7];
1618};
1619
9e1453c5 1620/*********************** Controller Attributes ***********************/
e02cfd96
VV		 1621struct mgmt_hba_attribs {
1622 u32 rsvd0[24];
1623 u8 controller_model_number[32];
1624 u32 rsvd1[79];
1625 u8 rsvd2[3];
1626 u8 phy_port;
1627 u32 rsvd3[13];
1628} __packed;
1629
1630struct mgmt_controller_attrib {
1631 struct mgmt_hba_attribs hba_attribs;
1632 u32 rsvd0[10];
1633} __packed;
1634
9e1453c5
AK		 1635struct be_cmd_req_cntl_attribs {
1636 struct be_cmd_req_hdr hdr;
1637};
1638
1639struct be_cmd_resp_cntl_attribs {
1640 struct be_cmd_resp_hdr hdr;
1641 struct mgmt_controller_attrib attribs;
1642};
1643
2e588f84
SP		 1644/*********************** Set driver function ***********************/
1645#define CAPABILITY_SW_TIMESTAMPS 2
1646#define CAPABILITY_BE3_NATIVE_ERX_API 4
1647
1648struct be_cmd_req_set_func_cap {
1649 struct be_cmd_req_hdr hdr;
1650 u32 valid_cap_flags;
1651 u32 cap_flags;
1652 u8 rsvd[212];
1653};
1654
1655struct be_cmd_resp_set_func_cap {
1656 struct be_cmd_resp_hdr hdr;
1657 u32 valid_cap_flags;
1658 u32 cap_flags;
1659 u8 rsvd[212];
1660};
1661
f25b119c
PR		 1662/*********************** Function Privileges ***********************/
1663enum {
1664 BE_PRIV_DEFAULT = 0x1,
1665 BE_PRIV_LNKQUERY = 0x2,
1666 BE_PRIV_LNKSTATS = 0x4,
1667 BE_PRIV_LNKMGMT = 0x8,
1668 BE_PRIV_LNKDIAG = 0x10,
1669 BE_PRIV_UTILQUERY = 0x20,
1670 BE_PRIV_FILTMGMT = 0x40,
1671 BE_PRIV_IFACEMGMT = 0x80,
1672 BE_PRIV_VHADM = 0x100,
1673 BE_PRIV_DEVCFG = 0x200,
1674 BE_PRIV_DEVSEC = 0x400
1675};
1676#define MAX_PRIVILEGES (BE_PRIV_VHADM | BE_PRIV_DEVCFG | \
1677 BE_PRIV_DEVSEC)
1678#define MIN_PRIVILEGES BE_PRIV_DEFAULT
1679
1680struct be_cmd_priv_map {
1681 u8 opcode;
1682 u8 subsystem;
1683 u32 priv_mask;
1684};
1685
1686struct be_cmd_req_get_fn_privileges {
1687 struct be_cmd_req_hdr hdr;
1688 u32 rsvd;
1689};
1690
1691struct be_cmd_resp_get_fn_privileges {
1692 struct be_cmd_resp_hdr hdr;
1693 u32 privilege_mask;
1694};
1695
04a06028
SP		 1696struct be_cmd_req_set_fn_privileges {
1697 struct be_cmd_req_hdr hdr;
1698 u32 privileges; /* Used by BE3, SH-R */
1699 u32 privileges_lancer; /* Used by Lancer */
1700};
f25b119c 1701
590c391d
PR		 1702/******************** GET/SET_MACLIST **************************/
1703#define BE_MAX_MAC 64
590c391d
PR		 1704struct be_cmd_req_get_mac_list {
1705 struct be_cmd_req_hdr hdr;
e5e1ee89
PR		 1706 u8 mac_type;
1707 u8 perm_override;
1708 u16 iface_id;
1709 u32 mac_id;
1710 u32 rsvd[3];
1711} __packed;
1712
1713struct get_list_macaddr {
1714 u16 mac_addr_size;
1715 union {
1716 u8 macaddr[6];
1717 struct {
1718 u8 rsvd[2];
1719 u32 mac_id;
1720 } __packed s_mac_id;
1721 } __packed mac_addr_id;
590c391d
PR		 1722} __packed;
1723
1724struct be_cmd_resp_get_mac_list {
1725 struct be_cmd_resp_hdr hdr;
e5e1ee89
PR		 1726 struct get_list_macaddr fd_macaddr; /* Factory default mac */
1727 struct get_list_macaddr macid_macaddr; /* soft mac */
1728 u8 true_mac_count;
1729 u8 pseudo_mac_count;
1730 u8 mac_list_size;
1731 u8 rsvd;
1732 /* perm override mac */
1733 struct get_list_macaddr macaddr_list[BE_MAX_MAC];
590c391d
PR		 1734} __packed;
1735
1736struct be_cmd_req_set_mac_list {
1737 struct be_cmd_req_hdr hdr;
1738 u8 mac_count;
1739 u8 rsvd1;
1740 u16 rsvd2;
1741 struct macaddr mac[BE_MAX_MAC];
1742} __packed;
1743
f1f3ee1b 1744/*********************** HSW Config ***********************/
a77dcb8c
AK		 1745#define PORT_FWD_TYPE_VEPA 0x3
1746#define PORT_FWD_TYPE_VEB 0x2
1747
f1f3ee1b
AK		 1748struct amap_set_hsw_context {
1749 u8 interface_id[16];
1750 u8 rsvd0[14];
1751 u8 pvid_valid;
a77dcb8c
AK		 1752 u8 pport;
1753 u8 rsvd1[6];
1754 u8 port_fwd_type[3];
1755 u8 rsvd2[7];
f1f3ee1b
AK		 1756 u8 pvid[16];
1757 u8 rsvd3[32];
1758 u8 rsvd4[32];
1759 u8 rsvd5[32];
1760} __packed;
1761
1762struct be_cmd_req_set_hsw_config {
1763 struct be_cmd_req_hdr hdr;
1764 u8 context[sizeof(struct amap_set_hsw_context) / 8];
1765} __packed;
1766
f1f3ee1b
AK		 1767struct amap_get_hsw_req_context {
1768 u8 interface_id[16];
1769 u8 rsvd0[14];
1770 u8 pvid_valid;
1771 u8 pport;
1772} __packed;
1773
1774struct amap_get_hsw_resp_context {
a77dcb8c
AK		 1775 u8 rsvd0[6];
1776 u8 port_fwd_type[3];
1777 u8 rsvd1[7];
f1f3ee1b
AK		 1778 u8 pvid[16];
1779 u8 rsvd2[32];
1780 u8 rsvd3[32];
1781 u8 rsvd4[32];
1782} __packed;
1783
1784struct be_cmd_req_get_hsw_config {
1785 struct be_cmd_req_hdr hdr;
1786 u8 context[sizeof(struct amap_get_hsw_req_context) / 8];
1787} __packed;
1788
1789struct be_cmd_resp_get_hsw_config {
1790 struct be_cmd_resp_hdr hdr;
1791 u8 context[sizeof(struct amap_get_hsw_resp_context) / 8];
1792 u32 rsvd;
1793};
1794
b4e32a71
PR		 1795/******************* get port names ***************/
1796struct be_cmd_req_get_port_name {
1797 struct be_cmd_req_hdr hdr;
1798 u32 rsvd0;
1799};
1800
1801struct be_cmd_resp_get_port_name {
1802 struct be_cmd_req_hdr hdr;
1803 u8 port_name[4];
1804};
1805
89a88ab8
AK		 1806/*************** HW Stats Get v1 **********************************/
1807#define BE_TXP_SW_SZ 48
1808struct be_port_rxf_stats_v1 {
1809 u32 rsvd0[12];
1810 u32 rx_crc_errors;
1811 u32 rx_alignment_symbol_errors;
1812 u32 rx_pause_frames;
1813 u32 rx_priority_pause_frames;
1814 u32 rx_control_frames;
1815 u32 rx_in_range_errors;
1816 u32 rx_out_range_errors;
1817 u32 rx_frame_too_long;
18fb06a1 1818 u32 rx_address_filtered;
89a88ab8
AK		 1819 u32 rx_dropped_too_small;
1820 u32 rx_dropped_too_short;
1821 u32 rx_dropped_header_too_small;
1822 u32 rx_dropped_tcp_length;
1823 u32 rx_dropped_runt;
1824 u32 rsvd1[10];
1825 u32 rx_ip_checksum_errs;
1826 u32 rx_tcp_checksum_errs;
1827 u32 rx_udp_checksum_errs;
1828 u32 rsvd2[7];
1829 u32 rx_switched_unicast_packets;
1830 u32 rx_switched_multicast_packets;
1831 u32 rx_switched_broadcast_packets;
1832 u32 rsvd3[3];
1833 u32 tx_pauseframes;
1834 u32 tx_priority_pauseframes;
1835 u32 tx_controlframes;
1836 u32 rsvd4[10];
1837 u32 rxpp_fifo_overflow_drop;
1838 u32 rx_input_fifo_overflow_drop;
1839 u32 pmem_fifo_overflow_drop;
1840 u32 jabber_events;
1841 u32 rsvd5[3];
1842};
1843
1844
1845struct be_rxf_stats_v1 {
1846 struct be_port_rxf_stats_v1 port[4];
1847 u32 rsvd0[2];
1848 u32 rx_drops_no_pbuf;
1849 u32 rx_drops_no_txpb;
1850 u32 rx_drops_no_erx_descr;
1851 u32 rx_drops_no_tpre_descr;
1852 u32 rsvd1[6];
1853 u32 rx_drops_too_many_frags;
1854 u32 rx_drops_invalid_ring;
1855 u32 forwarded_packets;
1856 u32 rx_drops_mtu;
1857 u32 rsvd2[14];
1858};
1859
1860struct be_erx_stats_v1 {
1861 u32 rx_drops_no_fragments[68]; /* dwordS 0 to 67*/
1862 u32 rsvd[4];
1863};
1864
61000861
AK		 1865struct be_port_rxf_stats_v2 {
1866 u32 rsvd0[10];
1867 u32 roce_bytes_received_lsd;
1868 u32 roce_bytes_received_msd;
1869 u32 rsvd1[5];
1870 u32 roce_frames_received;
1871 u32 rx_crc_errors;
1872 u32 rx_alignment_symbol_errors;
1873 u32 rx_pause_frames;
1874 u32 rx_priority_pause_frames;
1875 u32 rx_control_frames;
1876 u32 rx_in_range_errors;
1877 u32 rx_out_range_errors;
1878 u32 rx_frame_too_long;
1879 u32 rx_address_filtered;
1880 u32 rx_dropped_too_small;
1881 u32 rx_dropped_too_short;
1882 u32 rx_dropped_header_too_small;
1883 u32 rx_dropped_tcp_length;
1884 u32 rx_dropped_runt;
1885 u32 rsvd2[10];
1886 u32 rx_ip_checksum_errs;
1887 u32 rx_tcp_checksum_errs;
1888 u32 rx_udp_checksum_errs;
1889 u32 rsvd3[7];
1890 u32 rx_switched_unicast_packets;
1891 u32 rx_switched_multicast_packets;
1892 u32 rx_switched_broadcast_packets;
1893 u32 rsvd4[3];
1894 u32 tx_pauseframes;
1895 u32 tx_priority_pauseframes;
1896 u32 tx_controlframes;
1897 u32 rsvd5[10];
1898 u32 rxpp_fifo_overflow_drop;
1899 u32 rx_input_fifo_overflow_drop;
1900 u32 pmem_fifo_overflow_drop;
1901 u32 jabber_events;
1902 u32 rsvd6[3];
1903 u32 rx_drops_payload_size;
1904 u32 rx_drops_clipped_header;
1905 u32 rx_drops_crc;
1906 u32 roce_drops_payload_len;
1907 u32 roce_drops_crc;
1908 u32 rsvd7[19];
1909};
1910
1911struct be_rxf_stats_v2 {
1912 struct be_port_rxf_stats_v2 port[4];
1913 u32 rsvd0[2];
1914 u32 rx_drops_no_pbuf;
1915 u32 rx_drops_no_txpb;
1916 u32 rx_drops_no_erx_descr;
1917 u32 rx_drops_no_tpre_descr;
1918 u32 rsvd1[6];
1919 u32 rx_drops_too_many_frags;
1920 u32 rx_drops_invalid_ring;
1921 u32 forwarded_packets;
1922 u32 rx_drops_mtu;
1923 u32 rsvd2[35];
1924};
1925
89a88ab8
AK		 1926struct be_hw_stats_v1 {
1927 struct be_rxf_stats_v1 rxf;
1928 u32 rsvd0[BE_TXP_SW_SZ];
1929 struct be_erx_stats_v1 erx;
1930 struct be_pmem_stats pmem;
0b3f0e7a 1931 u32 rsvd1[18];
89a88ab8
AK		 1932};
1933
1934struct be_cmd_req_get_stats_v1 {
1935 struct be_cmd_req_hdr hdr;
1936 u8 rsvd[sizeof(struct be_hw_stats_v1)];
1937};
1938
1939struct be_cmd_resp_get_stats_v1 {
1940 struct be_cmd_resp_hdr hdr;
1941 struct be_hw_stats_v1 hw_stats;
1942};
1943
61000861
AK		 1944struct be_erx_stats_v2 {
1945 u32 rx_drops_no_fragments[136]; /* dwordS 0 to 135*/
1946 u32 rsvd[3];
1947};
1948
1949struct be_hw_stats_v2 {
1950 struct be_rxf_stats_v2 rxf;
1951 u32 rsvd0[BE_TXP_SW_SZ];
1952 struct be_erx_stats_v2 erx;
1953 struct be_pmem_stats pmem;
1954 u32 rsvd1[18];
1955};
1956
1957struct be_cmd_req_get_stats_v2 {
1958 struct be_cmd_req_hdr hdr;
1959 u8 rsvd[sizeof(struct be_hw_stats_v2)];
1960};
1961
1962struct be_cmd_resp_get_stats_v2 {
1963 struct be_cmd_resp_hdr hdr;
1964 struct be_hw_stats_v2 hw_stats;
1965};
1966
941a77d5
SK		 1967/************** get fat capabilites *******************/
1968#define MAX_MODULES 27
1969#define MAX_MODES 4
1970#define MODE_UART 0
1971#define FW_LOG_LEVEL_DEFAULT 48
1972#define FW_LOG_LEVEL_FATAL 64
1973
1974struct ext_fat_mode {
1975 u8 mode;
1976 u8 rsvd0;
1977 u16 port_mask;
1978 u32 dbg_lvl;
1979 u64 fun_mask;
1980} __packed;
1981
1982struct ext_fat_modules {
1983 u8 modules_str[32];
1984 u32 modules_id;
1985 u32 num_modes;
1986 struct ext_fat_mode trace_lvl[MAX_MODES];
1987} __packed;
1988
1989struct be_fat_conf_params {
1990 u32 max_log_entries;
1991 u32 log_entry_size;
1992 u8 log_type;
1993 u8 max_log_funs;
1994 u8 max_log_ports;
1995 u8 rsvd0;
1996 u32 supp_modes;
1997 u32 num_modules;
1998 struct ext_fat_modules module[MAX_MODULES];
1999} __packed;
2000
2001struct be_cmd_req_get_ext_fat_caps {
2002 struct be_cmd_req_hdr hdr;
2003 u32 parameter_type;
2004};
2005
2006struct be_cmd_resp_get_ext_fat_caps {
2007 struct be_cmd_resp_hdr hdr;
2008 struct be_fat_conf_params get_params;
2009};
2010
2011struct be_cmd_req_set_ext_fat_caps {
2012 struct be_cmd_req_hdr hdr;
2013 struct be_fat_conf_params set_params;
2014};
2015
150d58c7
VV		 2016#define RESOURCE_DESC_SIZE_V0 72
2017#define RESOURCE_DESC_SIZE_V1 88
2018#define PCIE_RESOURCE_DESC_TYPE_V0 0x40
a05f99db 2019#define NIC_RESOURCE_DESC_TYPE_V0 0x41
150d58c7 2020#define PCIE_RESOURCE_DESC_TYPE_V1 0x50
a05f99db 2021#define NIC_RESOURCE_DESC_TYPE_V1 0x51
f93f160b 2022#define PORT_RESOURCE_DESC_TYPE_V1 0x55
150d58c7 2023#define MAX_RESOURCE_DESC 264
d5c18473 2024
f2858738 2025#define IF_CAPS_FLAGS_VALID_SHIFT 0 /* IF caps valid */
10cccf60 2026#define VFT_SHIFT 3 /* VF template */
a401801c
SP		 2027#define IMM_SHIFT 6 /* Immediate */
2028#define NOSV_SHIFT 7 /* No save */
d5c18473 2029
150d58c7 2030struct be_res_desc_hdr {
abb93951
PR		 2031 u8 desc_type;
2032 u8 desc_len;
150d58c7
VV		 2033} __packed;
2034
a401801c
SP		 2035struct be_port_res_desc {
2036 struct be_res_desc_hdr hdr;
2037 u8 rsvd0;
2038 u8 flags;
2039 u8 link_num;
2040 u8 mc_type;
2041 u16 rsvd1;
2042
2043#define NV_TYPE_MASK 0x3 /* bits 0-1 */
2044#define NV_TYPE_DISABLED 1
2045#define NV_TYPE_VXLAN 3
2046#define SOCVID_SHIFT 2 /* Strip outer vlan */
2047#define RCVID_SHIFT 4 /* Report vlan */
2048 u8 nv_flags;
2049 u8 rsvd2;
2050 __le16 nv_port; /* vxlan/gre port */
2051 u32 rsvd3[19];
2052} __packed;
2053
150d58c7
VV		 2054struct be_pcie_res_desc {
2055 struct be_res_desc_hdr hdr;
2056 u8 rsvd0;
2057 u8 flags;
2058 u16 rsvd1;
2059 u8 pf_num;
2060 u8 rsvd2;
2061 u32 rsvd3;
2062 u8 sriov_state;
2063 u8 pf_state;
2064 u8 pf_type;
2065 u8 rsvd4;
2066 u16 num_vfs;
2067 u16 rsvd5;
2068 u32 rsvd6[17];
2069} __packed;
2070
2071struct be_nic_res_desc {
2072 struct be_res_desc_hdr hdr;
abb93951 2073 u8 rsvd1;
a401801c
SP		 2074
2075#define QUN_SHIFT 4 /* QoS is in absolute units */
abb93951
PR		 2076 u8 flags;
2077 u8 vf_num;
2078 u8 rsvd2;
2079 u8 pf_num;
2080 u8 rsvd3;
2081 u16 unicast_mac_count;
2082 u8 rsvd4[6];
2083 u16 mcc_count;
2084 u16 vlan_count;
2085 u16 mcast_mac_count;
2086 u16 txq_count;
2087 u16 rq_count;
2088 u16 rssq_count;
2089 u16 lro_count;
2090 u16 cq_count;
2091 u16 toe_conn_count;
2092 u16 eq_count;
0f77ba73
RN		 2093 u16 vlan_id;
2094 u16 iface_count;
abb93951
PR		 2095 u32 cap_flags;
2096 u8 link_param;
0f77ba73
RN		 2097 u8 rsvd6;
2098 u16 channel_id_param;
abb93951
PR		 2099 u32 bw_min;
2100 u32 bw_max;
2101 u8 acpi_params;
2102 u8 wol_param;
2103 u16 rsvd7;
0f77ba73
RN		 2104 u16 tunnel_iface_count;
2105 u16 direct_tenant_iface_count;
2106 u32 rsvd8[6];
150d58c7 2107} __packed;
abb93951 2108
f93f160b
VV		 2109/************ Multi-Channel type ***********/
2110enum mc_type {
2111 MC_NONE = 0x01,
2112 UMC = 0x02,
2113 FLEX10 = 0x03,
2114 vNIC1 = 0x04,
2115 nPAR = 0x05,
2116 UFP = 0x06,
2117 vNIC2 = 0x07
2118};
2119
f93f160b
VV		 2120/* Is BE in a multi-channel mode */
2121static inline bool be_is_mc(struct be_adapter *adapter)
2122{
2123 return adapter->mc_type > MC_NONE;
2124}
2125
abb93951
PR		 2126struct be_cmd_req_get_func_config {
2127 struct be_cmd_req_hdr hdr;
2128};
2129
2130struct be_cmd_resp_get_func_config {
28710c55 2131 struct be_cmd_resp_hdr hdr;
abb93951 2132 u32 desc_count;
150d58c7 2133 u8 func_param[MAX_RESOURCE_DESC * RESOURCE_DESC_SIZE_V1];
abb93951
PR		 2134};
2135
f2858738
VV		 2136enum {
2137 RESOURCE_LIMITS,
2138 RESOURCE_MODIFIABLE
2139};
2140
abb93951
PR		 2141struct be_cmd_req_get_profile_config {
2142 struct be_cmd_req_hdr hdr;
2143 u8 rsvd;
f2858738
VV		 2144#define ACTIVE_PROFILE_TYPE 0x2
2145#define QUERY_MODIFIABLE_FIELDS_TYPE BIT(3)
abb93951
PR		 2146 u8 type;
2147 u16 rsvd1;
2148};
2149
2150struct be_cmd_resp_get_profile_config {
150d58c7 2151 struct be_cmd_resp_hdr hdr;
f2858738
VV		 2152 __le16 desc_count;
2153 u16 rsvd;
150d58c7 2154 u8 func_param[MAX_RESOURCE_DESC * RESOURCE_DESC_SIZE_V1];
a05f99db
VV		 2155};
2156
f2858738 2157#define FIELD_MODIFIABLE 0xFFFF
d5c18473
PR		 2158struct be_cmd_req_set_profile_config {
2159 struct be_cmd_req_hdr hdr;
2160 u32 rsvd;
2161 u32 desc_count;
bec84e6b
VV		 2162 u8 desc[2 * RESOURCE_DESC_SIZE_V1];
2163} __packed;
d5c18473 2164
542963b7
VV		 2165struct be_cmd_req_get_active_profile {
2166 struct be_cmd_req_hdr hdr;
2167 u32 rsvd;
2168} __packed;
2169
2170struct be_cmd_resp_get_active_profile {
2171 struct be_cmd_resp_hdr hdr;
2172 u16 active_profile_id;
2173 u16 next_profile_id;
2174} __packed;
2175
dcf7ebba
PR		 2176struct be_cmd_enable_disable_vf {
2177 struct be_cmd_req_hdr hdr;
2178 u8 enable;
2179 u8 rsvd[3];
2180};
2181
68c45a2d
SK		 2182struct be_cmd_req_intr_set {
2183 struct be_cmd_req_hdr hdr;
2184 u8 intr_enabled;
2185 u8 rsvd[3];
2186};
2187
f25b119c
PR		 2188static inline bool check_privilege(struct be_adapter *adapter, u32 flags)
2189{
2190 return flags & adapter->cmd_privileges ? true : false;
2191}
2192
4c876616
SP		 2193/************** Get IFACE LIST *******************/
2194struct be_if_desc {
2195 u32 if_id;
2196 u32 cap_flags;
2197 u32 en_flags;
2198};
2199
2200struct be_cmd_req_get_iface_list {
2201 struct be_cmd_req_hdr hdr;
2202};
2203
2204struct be_cmd_resp_get_iface_list {
2205 struct be_cmd_req_hdr hdr;
2206 u32 if_cnt;
2207 struct be_if_desc if_desc;
2208};
2209
bdce2ad7
SR		 2210/*************** Set logical link ********************/
2211#define PLINK_TRACK_SHIFT 8
2212struct be_cmd_req_set_ll_link {
2213 struct be_cmd_req_hdr hdr;
2214 u32 link_config; /* Bit 0: UP_DOWN, Bit 9: PLINK */
2215};
2216
a401801c
SP		 2217/************** Manage IFACE Filters *******************/
2218#define OP_CONVERT_NORMAL_TO_TUNNEL 0
2219#define OP_CONVERT_TUNNEL_TO_NORMAL 1
2220
2221struct be_cmd_req_manage_iface_filters {
2222 struct be_cmd_req_hdr hdr;
2223 u8 op;
2224 u8 rsvd0;
2225 u8 flags;
2226 u8 rsvd1;
2227 u32 tunnel_iface_id;
2228 u32 target_iface_id;
2229 u8 mac[6];
2230 u16 vlan_tag;
2231 u32 tenant_id;
2232 u32 filter_id;
2233 u32 cap_flags;
2234 u32 cap_control_flags;
2235} __packed;
2236
31886e87
JP		 2237int be_pci_fnum_get(struct be_adapter *adapter);
2238int be_fw_wait_ready(struct be_adapter *adapter);
2239int be_cmd_mac_addr_query(struct be_adapter *adapter, u8 *mac_addr,
2240 bool permanent, u32 if_handle, u32 pmac_id);
2241int be_cmd_pmac_add(struct be_adapter *adapter, u8 *mac_addr, u32 if_id,
2242 u32 *pmac_id, u32 domain);
2243int be_cmd_pmac_del(struct be_adapter *adapter, u32 if_id, int pmac_id,
2244 u32 domain);
2245int be_cmd_if_create(struct be_adapter *adapter, u32 cap_flags, u32 en_flags,
2246 u32 *if_handle, u32 domain);
2247int be_cmd_if_destroy(struct be_adapter *adapter, int if_handle, u32 domain);
2248int be_cmd_eq_create(struct be_adapter *adapter, struct be_eq_obj *eqo);
2249int be_cmd_cq_create(struct be_adapter *adapter, struct be_queue_info *cq,
2250 struct be_queue_info *eq, bool no_delay,
2251 int num_cqe_dma_coalesce);
2252int be_cmd_mccq_create(struct be_adapter *adapter, struct be_queue_info *mccq,
2253 struct be_queue_info *cq);
2254int be_cmd_txq_create(struct be_adapter *adapter, struct be_tx_obj *txo);
2255int be_cmd_rxq_create(struct be_adapter *adapter, struct be_queue_info *rxq,
2256 u16 cq_id, u16 frag_size, u32 if_id, u32 rss, u8 *rss_id);
2257int be_cmd_q_destroy(struct be_adapter *adapter, struct be_queue_info *q,
2258 int type);
2259int be_cmd_rxq_destroy(struct be_adapter *adapter, struct be_queue_info *q);
2260int be_cmd_link_status_query(struct be_adapter *adapter, u16 *link_speed,
2261 u8 *link_status, u32 dom);
2262int be_cmd_reset(struct be_adapter *adapter);
2263int be_cmd_get_stats(struct be_adapter *adapter, struct be_dma_mem *nonemb_cmd);
2264int lancer_cmd_get_pport_stats(struct be_adapter *adapter,
2265 struct be_dma_mem *nonemb_cmd);
e97e3cda 2266int be_cmd_get_fw_ver(struct be_adapter *adapter);
2632bafd 2267int be_cmd_modify_eqd(struct be_adapter *adapter, struct be_set_eqd *, int num);
31886e87 2268int be_cmd_vlan_config(struct be_adapter *adapter, u32 if_id, u16 *vtag_array,
435452aa 2269 u32 num, u32 domain);
31886e87
JP		 2270int be_cmd_rx_filter(struct be_adapter *adapter, u32 flags, u32 status);
2271int be_cmd_set_flow_control(struct be_adapter *adapter, u32 tx_fc, u32 rx_fc);
2272int be_cmd_get_flow_control(struct be_adapter *adapter, u32 *tx_fc, u32 *rx_fc);
e97e3cda 2273int be_cmd_query_fw_cfg(struct be_adapter *adapter);
31886e87
JP		 2274int be_cmd_reset_function(struct be_adapter *adapter);
2275int be_cmd_rss_config(struct be_adapter *adapter, u8 *rsstable,
33cb0fa7 2276 u32 rss_hash_opts, u16 table_size, const u8 *rss_hkey);
31886e87
JP		 2277int be_process_mcc(struct be_adapter *adapter);
2278int be_cmd_set_beacon_state(struct be_adapter *adapter, u8 port_num, u8 beacon,
2279 u8 status, u8 state);
2280int be_cmd_get_beacon_state(struct be_adapter *adapter, u8 port_num,
2281 u32 *state);
e36edd9d
ML		 2282int be_cmd_read_port_transceiver_data(struct be_adapter *adapter,
2283 u8 page_num, u8 *data);
6809cee0 2284int be_cmd_query_cable_type(struct be_adapter *adapter);
21252377 2285int be_cmd_query_sfp_info(struct be_adapter *adapter);
31886e87 2286int be_cmd_write_flashrom(struct be_adapter *adapter, struct be_dma_mem *cmd,
70a7b525
VV		 2287 u32 flash_oper, u32 flash_opcode, u32 img_offset,
2288 u32 buf_size);
31886e87
JP		 2289int lancer_cmd_write_object(struct be_adapter *adapter, struct be_dma_mem *cmd,
2290 u32 data_size, u32 data_offset,
2291 const char *obj_name, u32 *data_written,
2292 u8 *change_status, u8 *addn_status);
de49bd5a 2293int lancer_cmd_read_object(struct be_adapter *adapter, struct be_dma_mem *cmd,
31886e87
JP		 2294 u32 data_size, u32 data_offset, const char *obj_name,
2295 u32 *data_read, u32 *eof, u8 *addn_status);
f0613380 2296int lancer_cmd_delete_object(struct be_adapter *adapter, const char *obj_name);
3f0d4560 2297int be_cmd_get_flash_crc(struct be_adapter *adapter, u8 *flashed_crc,
70a7b525 2298 u16 img_optype, u32 img_offset, u32 crc_offset);
31886e87
JP		 2299int be_cmd_enable_magic_wol(struct be_adapter *adapter, u8 *mac,
2300 struct be_dma_mem *nonemb_cmd);
2301int be_cmd_fw_init(struct be_adapter *adapter);
2302int be_cmd_fw_clean(struct be_adapter *adapter);
2303void be_async_mcc_enable(struct be_adapter *adapter);
2304void be_async_mcc_disable(struct be_adapter *adapter);
2305int be_cmd_loopback_test(struct be_adapter *adapter, u32 port_num,
2306 u32 loopback_type, u32 pkt_size, u32 num_pkts,
2307 u64 pattern);
2308int be_cmd_ddr_dma_test(struct be_adapter *adapter, u64 pattern, u32 byte_cnt,
2309 struct be_dma_mem *cmd);
2310int be_cmd_get_seeprom_data(struct be_adapter *adapter,
2311 struct be_dma_mem *nonemb_cmd);
2312int be_cmd_set_loopback(struct be_adapter *adapter, u8 port_num,
2313 u8 loopback_type, u8 enable);
2314int be_cmd_get_phy_info(struct be_adapter *adapter);
0f77ba73
RN		 2315int be_cmd_config_qos(struct be_adapter *adapter, u32 max_rate,
2316 u16 link_speed, u8 domain);
31886e87
JP		 2317void be_detect_error(struct be_adapter *adapter);
2318int be_cmd_get_die_temperature(struct be_adapter *adapter);
2319int be_cmd_get_cntl_attributes(struct be_adapter *adapter);
2320int be_cmd_req_native_mode(struct be_adapter *adapter);
2321int be_cmd_get_reg_len(struct be_adapter *adapter, u32 *log_size);
c5f156de 2322int be_cmd_get_regs(struct be_adapter *adapter, u32 buf_len, void *buf);
31886e87
JP		 2323int be_cmd_get_fn_privileges(struct be_adapter *adapter, u32 *privilege,
2324 u32 domain);
2325int be_cmd_set_fn_privileges(struct be_adapter *adapter, u32 privileges,
2326 u32 vf_num);
2327int be_cmd_get_mac_from_list(struct be_adapter *adapter, u8 *mac,
b188f090
SR		 2328 bool *pmac_id_active, u32 *pmac_id,
2329 u32 if_handle, u8 domain);
2330int be_cmd_get_active_mac(struct be_adapter *adapter, u32 pmac_id, u8 *mac,
2331 u32 if_handle, bool active, u32 domain);
31886e87
JP		 2332int be_cmd_get_perm_mac(struct be_adapter *adapter, u8 *mac);
2333int be_cmd_set_mac_list(struct be_adapter *adapter, u8 *mac_array, u8 mac_count,
2334 u32 domain);
2335int be_cmd_set_mac(struct be_adapter *adapter, u8 *mac, int if_id, u32 dom);
2336int be_cmd_set_hsw_config(struct be_adapter *adapter, u16 pvid, u32 domain,
2337 u16 intf_id, u16 hsw_mode);
2338int be_cmd_get_hsw_config(struct be_adapter *adapter, u16 *pvid, u32 domain,
2339 u16 intf_id, u8 *mode);
2340int be_cmd_get_acpi_wol_cap(struct be_adapter *adapter);
baaa08d1
VV		 2341int be_cmd_set_fw_log_level(struct be_adapter *adapter, u32 level);
2342int be_cmd_get_fw_log_level(struct be_adapter *adapter);
31886e87
JP		 2343int be_cmd_get_ext_fat_capabilites(struct be_adapter *adapter,
2344 struct be_dma_mem *cmd);
2345int be_cmd_set_ext_fat_capabilites(struct be_adapter *adapter,
2346 struct be_dma_mem *cmd,
2347 struct be_fat_conf_params *cfgs);
31886e87
JP		 2348int lancer_physdev_ctrl(struct be_adapter *adapter, u32 mask);
2349int lancer_initiate_dump(struct be_adapter *adapter);
f0613380 2350int lancer_delete_dump(struct be_adapter *adapter);
31886e87
JP		 2351bool dump_present(struct be_adapter *adapter);
2352int lancer_test_and_set_rdy_state(struct be_adapter *adapter);
21252377 2353int be_cmd_query_port_name(struct be_adapter *adapter);
92bf14ab
SP		 2354int be_cmd_get_func_config(struct be_adapter *adapter,
2355 struct be_resources *res);
2356int be_cmd_get_profile_config(struct be_adapter *adapter,
f2858738 2357 struct be_resources *res, u8 query, u8 domain);
542963b7 2358int be_cmd_get_active_profile(struct be_adapter *adapter, u16 *profile);
31886e87
JP		 2359int be_cmd_get_if_id(struct be_adapter *adapter, struct be_vf_cfg *vf_cfg,
2360 int vf_num);
2361int be_cmd_enable_vf(struct be_adapter *adapter, u8 domain);
2362int be_cmd_intr_set(struct be_adapter *adapter, bool intr_enable);
bdce2ad7
SR		 2363int be_cmd_set_logical_link_config(struct be_adapter *adapter,
2364 int link_state, u8 domain);
a401801c
SP		 2365int be_cmd_set_vxlan_port(struct be_adapter *adapter, __be16 port);
2366int be_cmd_manage_iface(struct be_adapter *adapter, u32 iface, u8 op);
bec84e6b 2367int be_cmd_set_sriov_config(struct be_adapter *adapter,
f2858738
VV		 2368 struct be_resources res, u16 num_vfs,
2369 u16 num_vf_qs);
Linux kernel - Deliverables
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